-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup BasicAbs Vector Absolute Value
- *
- * Computes the absolute value of a vector on an element-by-element basis.
- *
- *
- * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
- *
- *
- * The functions support in-place computation allowing the source and
- * destination pointers to reference the same memory buffer.
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup BasicAbs
- * @{
- */
-
-/**
- * @brief Floating-point vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
-void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1, in2, in3, in4; /* temporary variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Calculate absolute and then store the results in the destination buffer. */
- /* read sample from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
-
- /* find absolute value */
- in1 = fabsf(in1);
-
- /* read sample from source */
- in4 = *(pSrc + 3);
-
- /* find absolute value */
- in2 = fabsf(in2);
-
- /* read sample from source */
- *pDst = in1;
-
- /* find absolute value */
- in3 = fabsf(in3);
-
- /* find absolute value */
- in4 = fabsf(in4);
-
- /* store result to destination */
- *(pDst + 1) = in2;
-
- /* store result to destination */
- *(pDst + 2) = in3;
-
- /* store result to destination */
- *(pDst + 3) = in4;
-
-
- /* Update source pointer to process next sampels */
- pSrc += 4u;
-
- /* Update destination pointer to process next sampels */
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Calculate absolute and then store the results in the destination buffer. */
- *pDst++ = fabsf(*pSrc++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicAbs group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
deleted file mode 100644
index a084a35..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_abs_q15.c
- * Description: Q15 vector absolute value
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAbs
- * @{
- */
-
-/**
- * @brief Q15 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
- */
-
-void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- __SIMD32_TYPE *simd;
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t in1; /* Input value1 */
- q15_t in2; /* Input value2 */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- simd = __SIMD32_CONST(pDst);
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Read two inputs */
- in1 = *pSrc++;
- in2 = *pSrc++;
-
-
- /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
-#ifndef ARM_MATH_BIG_ENDIAN
- *simd++ =
- __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
- ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
-
-#else
-
-
- *simd++ =
- __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
- ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- in1 = *pSrc++;
- in2 = *pSrc++;
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *simd++ =
- __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
- ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
-
-#else
-
-
- *simd++ =
- __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
- ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- pDst = (q15_t *)simd;
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Read the input */
- in1 = *pSrc++;
-
- /* Calculate absolute value of input and then store the result in the destination buffer. */
- *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t in; /* Temporary input variable */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Read the input */
- in = *pSrc++;
-
- /* Calculate absolute value of input and then store the result in the destination buffer. */
- *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of BasicAbs group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
deleted file mode 100644
index 75595c7..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_abs_q31.c
- * Description: Q31 vector absolute value
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAbs
- * @{
- */
-
-
-/**
- * @brief Q31 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
- */
-
-void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- q31_t in; /* Input value */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
- *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
- *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
- *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
- in = *pSrc++;
- *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of BasicAbs group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
deleted file mode 100644
index 19d9167..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_abs_q7.c
- * Description: Q7 vector absolute value
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAbs
- * @{
- */
-
-/**
- * @brief Q7 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * \par Conditions for optimum performance
- * Input and output buffers should be aligned by 32-bit
- *
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
- */
-
-void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- q7_t in; /* Input value1 */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4; /* temporary input variables */
- q31_t out1, out2, out3, out4; /* temporary output variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Read inputs */
- in1 = (q31_t) * pSrc;
- in2 = (q31_t) * (pSrc + 1);
- in3 = (q31_t) * (pSrc + 2);
-
- /* find absolute value */
- out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
-
- /* read input */
- in4 = (q31_t) * (pSrc + 3);
-
- /* find absolute value */
- out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
-
- /* store result to destination */
- *pDst = (q7_t) out1;
-
- /* find absolute value */
- out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
-
- /* find absolute value */
- out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
-
- /* store result to destination */
- *(pDst + 1) = (q7_t) out2;
-
- /* store result to destination */
- *(pDst + 2) = (q7_t) out3;
-
- /* store result to destination */
- *(pDst + 3) = (q7_t) out4;
-
- /* update pointers to process next samples */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = blockSize;
-
-#endif /* #define ARM_MATH_CM0_FAMILY */
-
- while (blkCnt > 0u)
- {
- /* C = |A| */
- /* Read the input */
- in = *pSrc++;
-
- /* Store the Absolute result in the destination buffer */
- *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicAbs group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
deleted file mode 100644
index 9151261..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_add_f32.c
- * Description: Floating-point vector addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup BasicAdd Vector Addition
- *
- * Element-by-element addition of two vectors.
- *
- *
- * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
- *
- *
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup BasicAdd
- * @{
- */
-
-/**
- * @brief Floating-point vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
-void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
- float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
-
- /* read four inputs from sourceA and four inputs from sourceB */
- inA1 = *pSrcA;
- inB1 = *pSrcB;
- inA2 = *(pSrcA + 1);
- inB2 = *(pSrcB + 1);
- inA3 = *(pSrcA + 2);
- inB3 = *(pSrcB + 2);
- inA4 = *(pSrcA + 3);
- inB4 = *(pSrcB + 3);
-
- /* C = A + B */
- /* add and store result to destination */
- *pDst = inA1 + inB1;
- *(pDst + 1) = inA2 + inB2;
- *(pDst + 2) = inA3 + inB3;
- *(pDst + 3) = inA4 + inB4;
-
- /* update pointers to process next samples */
- pSrcA += 4u;
- pSrcB += 4u;
- pDst += 4u;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (*pSrcA++) + (*pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
deleted file mode 100644
index 111fbd2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_add_q15.c
- * Description: Q15 vector addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAdd
- * @{
- */
-
-/**
- * @brief Q15 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inB1, inB2;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- inA1 = *__SIMD32(pSrcA)++;
- inA2 = *__SIMD32(pSrcA)++;
- inB1 = *__SIMD32(pSrcB)++;
- inB2 = *__SIMD32(pSrcB)++;
-
- *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
- *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-}
-
-/**
- * @} end of BasicAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
deleted file mode 100644
index 8b78fee..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_add_q31.c
- * Description: Q31 vector addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAdd
- * @{
- */
-
-
-/**
- * @brief Q31 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inA3, inA4;
- q31_t inB1, inB2, inB3, inB4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- inA1 = *pSrcA++;
- inA2 = *pSrcA++;
- inB1 = *pSrcB++;
- inB2 = *pSrcB++;
-
- inA3 = *pSrcA++;
- inA4 = *pSrcA++;
- inB3 = *pSrcB++;
- inB4 = *pSrcB++;
-
- *pDst++ = __QADD(inA1, inB1);
- *pDst++ = __QADD(inA2, inB2);
- *pDst++ = __QADD(inA3, inB3);
- *pDst++ = __QADD(inA4, inB4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = __QADD(*pSrcA++, *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of BasicAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
deleted file mode 100644
index 903d1ed..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_add_q7.c
- * Description: Q7 vector addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicAdd
- * @{
- */
-
-/**
- * @brief Q7 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
- */
-
-void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + B */
- /* Add and then store the results in the destination buffer. */
- *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-}
-
-/**
- * @} end of BasicAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
deleted file mode 100644
index bcb2470..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dot_prod_f32.c
- * Description: Floating-point dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup dot_prod Vector Dot Product
- *
- * Computes the dot product of two vectors.
- * The vectors are multiplied element-by-element and then summed.
- *
- *
- * sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
- *
- *
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup dot_prod
- * @{
- */
-
-/**
- * @brief Dot product of floating-point vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
-
-void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result)
-{
- float32_t sum = 0.0f; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the result in a temporary buffer */
- sum += (*pSrcA++) * (*pSrcB++);
- sum += (*pSrcA++) * (*pSrcB++);
- sum += (*pSrcA++) * (*pSrcB++);
- sum += (*pSrcA++) * (*pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the result in a temporary buffer. */
- sum += (*pSrcA++) * (*pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- /* Store the result back in the destination buffer */
- *result = sum;
-}
-
-/**
- * @} end of dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
deleted file mode 100644
index c15c8b8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dot_prod_q15.c
- * Description: Q15 dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup dot_prod
- * @{
- */
-
-/**
- * @brief Dot product of Q15 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
- * results are added to a 64-bit accumulator in 34.30 format.
- * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
- * there is no risk of overflow.
- * The return result is in 34.30 format.
- */
-
-void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result)
-{
- q63_t sum = 0; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the result in a temporary buffer. */
- sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
- sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the results in a temporary buffer. */
- sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the results in a temporary buffer. */
- sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Store the result in the destination buffer in 34.30 format */
- *result = sum;
-
-}
-
-/**
- * @} end of dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
deleted file mode 100644
index 4f1bc58..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dot_prod_q31.c
- * Description: Q31 dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup dot_prod
- * @{
- */
-
-/**
- * @brief Dot product of Q31 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
- * are truncated to 2.48 format by discarding the lower 14 bits.
- * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
- * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
- * the length of the vectors is less than 2^16 elements.
- * The return result is in 16.48 format.
- */
-
-void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result)
-{
- q63_t sum = 0; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inA3, inA4;
- q31_t inB1, inB2, inB3, inB4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the result in a temporary buffer. */
- inA1 = *pSrcA++;
- inA2 = *pSrcA++;
- inA3 = *pSrcA++;
- inA4 = *pSrcA++;
- inB1 = *pSrcB++;
- inB2 = *pSrcB++;
- inB3 = *pSrcB++;
- inB4 = *pSrcB++;
-
- sum += ((q63_t) inA1 * inB1) >> 14u;
- sum += ((q63_t) inA2 * inB2) >> 14u;
- sum += ((q63_t) inA3 * inB3) >> 14u;
- sum += ((q63_t) inA4 * inB4) >> 14u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Calculate dot product and then store the result in a temporary buffer. */
- sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the result in the destination buffer in 16.48 format */
- *result = sum;
-}
-
-/**
- * @} end of dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
deleted file mode 100644
index cd3c509..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dot_prod_q7.c
- * Description: Q7 dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup dot_prod
- * @{
- */
-
-/**
- * @brief Dot product of Q7 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
- * results are added to an accumulator in 18.14 format.
- * Nonsaturating additions are used and there is no danger of wrap around as long as
- * the vectors are less than 2^18 elements long.
- * The return result is in 18.14 format.
- */
-
-void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result)
-{
- uint32_t blkCnt; /* loop counter */
-
- q31_t sum = 0; /* Temporary variables to store output */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t input1, input2; /* Temporary variables to store input */
- q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
-
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read 4 samples at a time from sourceA */
- input1 = *__SIMD32(pSrcA)++;
- /* read 4 samples at a time from sourceB */
- input2 = *__SIMD32(pSrcB)++;
-
- /* extract two q7_t samples to q15_t samples */
- inA1 = __SXTB16(__ROR(input1, 8));
- /* extract reminaing two samples */
- inA2 = __SXTB16(input1);
- /* extract two q7_t samples to q15_t samples */
- inB1 = __SXTB16(__ROR(input2, 8));
- /* extract reminaing two samples */
- inB2 = __SXTB16(input2);
-
- /* multiply and accumulate two samples at a time */
- sum = __SMLAD(inA1, inB1, sum);
- sum = __SMLAD(inA2, inB2, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Dot product and then store the results in a temporary buffer. */
- sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
- /* Dot product and then store the results in a temporary buffer. */
- sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- /* Store the result in the destination buffer in 18.14 format */
- *result = sum;
-}
-
-/**
- * @} end of dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
deleted file mode 100644
index c3a9ff0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mult_f32.c
- * Description: Floating-point vector multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup BasicMult Vector Multiplication
- *
- * Element-by-element multiplication of two vectors.
- *
- *
- * pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
- *
- *
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup BasicMult
- * @{
- */
-
-/**
- * @brief Floating-point vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
-void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counters */
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
- float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
- float32_t out1, out2, out3, out4; /* temporary output variables */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and store the results in output buffer */
- /* read sample from sourceA */
- inA1 = *pSrcA;
- /* read sample from sourceB */
- inB1 = *pSrcB;
- /* read sample from sourceA */
- inA2 = *(pSrcA + 1);
- /* read sample from sourceB */
- inB2 = *(pSrcB + 1);
-
- /* out = sourceA * sourceB */
- out1 = inA1 * inB1;
-
- /* read sample from sourceA */
- inA3 = *(pSrcA + 2);
- /* read sample from sourceB */
- inB3 = *(pSrcB + 2);
-
- /* out = sourceA * sourceB */
- out2 = inA2 * inB2;
-
- /* read sample from sourceA */
- inA4 = *(pSrcA + 3);
-
- /* store result to destination buffer */
- *pDst = out1;
-
- /* read sample from sourceB */
- inB4 = *(pSrcB + 3);
-
- /* out = sourceA * sourceB */
- out3 = inA3 * inB3;
-
- /* store result to destination buffer */
- *(pDst + 1) = out2;
-
- /* out = sourceA * sourceB */
- out4 = inA4 * inB4;
- /* store result to destination buffer */
- *(pDst + 2) = out3;
- /* store result to destination buffer */
- *(pDst + 3) = out4;
-
-
- /* update pointers to process next samples */
- pSrcA += 4u;
- pSrcB += 4u;
- pDst += 4u;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and store the results in output buffer */
- *pDst++ = (*pSrcA++) * (*pSrcB++);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c
deleted file mode 100644
index bdb757e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mult_q15.c
- * Description: Q15 vector multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicMult
- * @{
- */
-
-
-/**
- * @brief Q15 vector multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counters */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
- q15_t out1, out2, out3, out4; /* temporary output variables */
- q31_t mul1, mul2, mul3, mul4; /* temporary variables */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read two samples at a time from sourceA */
- inA1 = *__SIMD32(pSrcA)++;
- /* read two samples at a time from sourceB */
- inB1 = *__SIMD32(pSrcB)++;
- /* read two samples at a time from sourceA */
- inA2 = *__SIMD32(pSrcA)++;
- /* read two samples at a time from sourceB */
- inB2 = *__SIMD32(pSrcB)++;
-
- /* multiply mul = sourceA * sourceB */
- mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
- mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
- mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
- mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
-
- /* saturate result to 16 bit */
- out1 = (q15_t) __SSAT(mul1 >> 15, 16);
- out2 = (q15_t) __SSAT(mul2 >> 15, 16);
- out3 = (q15_t) __SSAT(mul3 >> 15, 16);
- out4 = (q15_t) __SSAT(mul4 >> 15, 16);
-
- /* store the result */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
- *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
- *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and store the result in the destination buffer */
- *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c
deleted file mode 100644
index f13a1a3..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mult_q31.c
- * Description: Q31 vector multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicMult
- * @{
- */
-
-/**
- * @brief Q31 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counters */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
- q31_t inB1, inB2, inB3, inB4; /* temporary input variables */
- q31_t out1, out2, out3, out4; /* temporary output variables */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and then store the results in the destination buffer. */
- inA1 = *pSrcA++;
- inA2 = *pSrcA++;
- inA3 = *pSrcA++;
- inA4 = *pSrcA++;
- inB1 = *pSrcB++;
- inB2 = *pSrcB++;
- inB3 = *pSrcB++;
- inB4 = *pSrcB++;
-
- out1 = ((q63_t) inA1 * inB1) >> 32;
- out2 = ((q63_t) inA2 * inB2) >> 32;
- out3 = ((q63_t) inA3 * inB3) >> 32;
- out4 = ((q63_t) inA4 * inB4) >> 32;
-
- out1 = __SSAT(out1, 31);
- out2 = __SSAT(out2, 31);
- out3 = __SSAT(out3, 31);
- out4 = __SSAT(out4, 31);
-
- *pDst++ = out1 << 1u;
- *pDst++ = out2 << 1u;
- *pDst++ = out3 << 1u;
- *pDst++ = out4 << 1u;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and then store the results in the destination buffer. */
- inA1 = *pSrcA++;
- inB1 = *pSrcB++;
- out1 = ((q63_t) inA1 * inB1) >> 32;
- out1 = __SSAT(out1, 31);
- *pDst++ = out1 << 1u;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and then store the results in the destination buffer. */
- *pDst++ =
- (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-/**
- * @} end of BasicMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
deleted file mode 100644
index 7d4c192..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mult_q7.c
- * Description: Q7 vector multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicMult
- * @{
- */
-
-/**
- * @brief Q7 vector multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
- */
-
-void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counters */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and store the results in temporary variables */
- out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
- out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
- out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
- out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
-
- /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
- *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A * B */
- /* Multiply the inputs and store the result in the destination buffer */
- *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
deleted file mode 100644
index 91115cc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_negate_f32.c
- * Description: Negates floating-point vectors
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup negate Vector Negate
- *
- * Negates the elements of a vector.
- *
- *
- * pDst[n] = -pSrc[n], 0 <= n < blockSize.
- *
- *
- * The functions support in-place computation allowing the source and
- * destination pointers to reference the same memory buffer.
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup negate
- * @{
- */
-
-/**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
-void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1, in2, in3, in4; /* temporary variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read inputs from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- /* negate the input */
- in1 = -in1;
- in2 = -in2;
- in3 = -in3;
- in4 = -in4;
-
- /* store the result to destination */
- *pDst = in1;
- *(pDst + 1) = in2;
- *(pDst + 2) = in3;
- *(pDst + 3) = in4;
-
- /* update pointers to process next samples */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Negate and then store the results in the destination buffer. */
- *pDst++ = -*pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of negate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
deleted file mode 100644
index dac68fe..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_negate_q15.c
- * Description: Negates Q15 vectors
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup negate
- * @{
- */
-
-/**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * \par Conditions for optimum performance
- * Input and output buffers should be aligned by 32-bit
- *
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
- */
-
-void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- q15_t in;
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in1, in2; /* Temporary variables */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Read two inputs at a time */
- in1 = _SIMD32_OFFSET(pSrc);
- in2 = _SIMD32_OFFSET(pSrc + 2);
-
- /* negate two samples at a time */
- in1 = __QSUB16(0, in1);
-
- /* negate two samples at a time */
- in2 = __QSUB16(0, in2);
-
- /* store the result to destination 2 samples at a time */
- _SIMD32_OFFSET(pDst) = in1;
- /* store the result to destination 2 samples at a time */
- _SIMD32_OFFSET(pDst + 2) = in2;
-
-
- /* update pointers to process next samples */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Negate and then store the result in the destination buffer. */
- in = *pSrc++;
- *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of negate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
deleted file mode 100644
index 53cfa77..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_negate_q31.c
- * Description: Negates Q31 vectors
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup negate
- * @{
- */
-
-/**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
- */
-
-void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t in; /* Temporary variable */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Negate and then store the results in the destination buffer. */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- *pDst++ = __QSUB(0, in1);
- *pDst++ = __QSUB(0, in2);
- *pDst++ = __QSUB(0, in3);
- *pDst++ = __QSUB(0, in4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Negate and then store the result in the destination buffer. */
- in = *pSrc++;
- *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of negate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
deleted file mode 100644
index d457e27..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_negate_q7.c
- * Description: Negates Q7 vectors
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup negate
- * @{
- */
-
-/**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
- */
-
-void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- q7_t in;
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t input; /* Input values1-4 */
- q31_t zero = 0x00000000;
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Read four inputs */
- input = *__SIMD32(pSrc)++;
-
- /* Store the Negated results in the destination buffer in a single cycle by packing the results */
- *__SIMD32(pDst)++ = __QSUB8(zero, input);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = -A */
- /* Negate and then store the results in the destination buffer. */ \
- in = *pSrc++;
- *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of negate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
deleted file mode 100644
index a929f8d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_offset_f32.c
- * Description: Floating-point vector offset
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup offset Vector Offset
- *
- * Adds a constant offset to each element of a vector.
- *
- *
- * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
- *
- *
- * The functions support in-place computation allowing the source and
- * destination pointers to reference the same memory buffer.
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup offset
- * @{
- */
-
-/**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
-
-void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination buffer. */
- /* read samples from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
-
- /* add offset to input */
- in1 = in1 + offset;
-
- /* read samples from source */
- in3 = *(pSrc + 2);
-
- /* add offset to input */
- in2 = in2 + offset;
-
- /* read samples from source */
- in4 = *(pSrc + 3);
-
- /* add offset to input */
- in3 = in3 + offset;
-
- /* store result to destination */
- *pDst = in1;
-
- /* add offset to input */
- in4 = in4 + offset;
-
- /* store result to destination */
- *(pDst + 1) = in2;
-
- /* store result to destination */
- *(pDst + 2) = in3;
-
- /* store result to destination */
- *(pDst + 3) = in4;
-
- /* update pointers to process next samples */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the result in the destination buffer. */
- *pDst++ = (*pSrc++) + offset;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of offset group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
deleted file mode 100644
index 6508c15..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_offset_q15.c
- * Description: Q15 vector offset
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup offset
- * @{
- */
-
-/**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
- */
-
-void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t offset_packed; /* Offset packed to 32 bit */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Offset is packed to 32 bit in order to use SIMD32 for addition */
- offset_packed = __PKHBT(offset, offset, 16);
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
- *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
- *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination buffer. */
- *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination buffer. */
- *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of offset group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
deleted file mode 100644
index 35d9c2e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_offset_q31.c
- * Description: Q31 vector offset
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup offset
- * @{
- */
-
-/**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
- */
-
-void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination buffer. */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- *pDst++ = __QADD(in1, offset);
- *pDst++ = __QADD(in2, offset);
- *pDst++ = __QADD(in3, offset);
- *pDst++ = __QADD(in4, offset);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the result in the destination buffer. */
- *pDst++ = __QADD(*pSrc++, offset);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the result in the destination buffer. */
- *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of offset group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
deleted file mode 100644
index 1e76b49..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_offset_q7.c
- * Description: Q7 vector offset
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup offset
- * @{
- */
-
-/**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
- */
-
-void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t offset_packed; /* Offset packed to 32 bit */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Offset is packed to 32 bit in order to use SIMD32 for addition */
- offset_packed = __PACKq7(offset, offset, offset, offset);
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
- *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the result in the destination buffer. */
- *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A + offset */
- /* Add offset and then store the result in the destination buffer. */
- *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of offset group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
deleted file mode 100644
index 9c4202a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_scale_f32.c
- * Description: Multiplies a floating-point vector by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup scale Vector Scale
- *
- * Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
- *
- *
- * pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
- *
- *
- * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by
- * a fractional multiplication scaleFract and an arithmetic shift shift.
- * The shift allows the gain of the scaling operation to exceed 1.0.
- * The algorithm used with fixed-point data is:
- *
- *
- * pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
- *
- *
- * The overall scale factor applied to the fixed-point data is
- *
- * scale = scaleFract * 2^shift.
- *
- *
- * The functions support in-place computation allowing the source and destination
- * pointers to reference the same memory buffer.
- */
-
-/**
- * @addtogroup scale
- * @{
- */
-
-/**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
-
-void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1, in2, in3, in4; /* temporary variabels */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the results in the destination buffer. */
- /* read input samples from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
-
- /* multiply with scaling factor */
- in1 = in1 * scale;
-
- /* read input sample from source */
- in3 = *(pSrc + 2);
-
- /* multiply with scaling factor */
- in2 = in2 * scale;
-
- /* read input sample from source */
- in4 = *(pSrc + 3);
-
- /* multiply with scaling factor */
- in3 = in3 * scale;
- in4 = in4 * scale;
- /* store the result to destination */
- *pDst = in1;
- *(pDst + 1) = in2;
- *(pDst + 2) = in3;
- *(pDst + 3) = in4;
-
- /* update pointers to process next samples */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- *pDst++ = (*pSrc++) * scale;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of scale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
deleted file mode 100644
index cd11e28..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_scale_q15.c
- * Description: Multiplies a Q15 vector by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup scale
- * @{
- */
-
-/**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The input data *pSrc and scaleFract are in 1.15 format.
- * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
- */
-
-
-void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize)
-{
- int8_t kShift = 15 - shift; /* shift to apply after scaling */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q15_t in1, in2, in3, in4;
- q31_t inA1, inA2; /* Temporary variables */
- q31_t out1, out2, out3, out4;
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Reading 2 inputs from memory */
- inA1 = *__SIMD32(pSrc)++;
- inA2 = *__SIMD32(pSrc)++;
-
- /* C = A * scale */
- /* Scale the inputs and then store the 2 results in the destination buffer
- * in single cycle by packing the outputs */
- out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
- out2 = (q31_t) ((q15_t) inA1 * scaleFract);
- out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
- out4 = (q31_t) ((q15_t) inA2 * scaleFract);
-
- /* apply shifting */
- out1 = out1 >> kShift;
- out2 = out2 >> kShift;
- out3 = out3 >> kShift;
- out4 = out4 >> kShift;
-
- /* saturate the output */
- in1 = (q15_t) (__SSAT(out1, 16));
- in2 = (q15_t) (__SSAT(out2, 16));
- in3 = (q15_t) (__SSAT(out3, 16));
- in4 = (q15_t) (__SSAT(out4, 16));
-
- /* store the result to destination */
- *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
- *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of scale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
deleted file mode 100644
index 34d8b96..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_scale_q31.c
- * Description: Multiplies a Q31 vector by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup scale
- * @{
- */
-
-/**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The input data *pSrc and scaleFract are in 1.31 format.
- * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
- */
-
-void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize)
-{
- int8_t kShift = shift + 1; /* Shift to apply after scaling */
- int8_t sign = (kShift & 0x80);
- uint32_t blkCnt; /* loop counter */
- q31_t in, out;
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in1, in2, in3, in4; /* temporary input variables */
- q31_t out1, out2, out3, out4; /* temporary output variabels */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- if (sign == 0u)
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read four inputs from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- /* multiply input with scaler value */
- in1 = ((q63_t) in1 * scaleFract) >> 32;
- in2 = ((q63_t) in2 * scaleFract) >> 32;
- in3 = ((q63_t) in3 * scaleFract) >> 32;
- in4 = ((q63_t) in4 * scaleFract) >> 32;
-
- /* apply shifting */
- out1 = in1 << kShift;
- out2 = in2 << kShift;
-
- /* saturate the results. */
- if (in1 != (out1 >> kShift))
- out1 = 0x7FFFFFFF ^ (in1 >> 31);
-
- if (in2 != (out2 >> kShift))
- out2 = 0x7FFFFFFF ^ (in2 >> 31);
-
- out3 = in3 << kShift;
- out4 = in4 << kShift;
-
- *pDst = out1;
- *(pDst + 1) = out2;
-
- if (in3 != (out3 >> kShift))
- out3 = 0x7FFFFFFF ^ (in3 >> 31);
-
- if (in4 != (out4 >> kShift))
- out4 = 0x7FFFFFFF ^ (in4 >> 31);
-
- /* Store result destination */
- *(pDst + 2) = out3;
- *(pDst + 3) = out4;
-
- /* Update pointers to process next sampels */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- }
- else
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read four inputs from source */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- /* multiply input with scaler value */
- in1 = ((q63_t) in1 * scaleFract) >> 32;
- in2 = ((q63_t) in2 * scaleFract) >> 32;
- in3 = ((q63_t) in3 * scaleFract) >> 32;
- in4 = ((q63_t) in4 * scaleFract) >> 32;
-
- /* apply shifting */
- out1 = in1 >> -kShift;
- out2 = in2 >> -kShift;
-
- out3 = in3 >> -kShift;
- out4 = in4 >> -kShift;
-
- /* Store result destination */
- *pDst = out1;
- *(pDst + 1) = out2;
-
- *(pDst + 2) = out3;
- *(pDst + 3) = out4;
-
- /* Update pointers to process next sampels */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- if (sign == 0)
- {
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- in = *pSrc++;
- in = ((q63_t) in * scaleFract) >> 32;
-
- out = in << kShift;
-
- if (in != (out >> kShift))
- out = 0x7FFFFFFF ^ (in >> 31);
-
- *pDst++ = out;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- in = *pSrc++;
- in = ((q63_t) in * scaleFract) >> 32;
-
- out = in >> -kShift;
-
- *pDst++ = out;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- }
-}
-
-/**
- * @} end of scale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
deleted file mode 100644
index a826321..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_scale_q7.c
- * Description: Multiplies a Q7 vector by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup scale
- * @{
- */
-
-/**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The input data *pSrc and scaleFract are in 1.7 format.
- * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
- */
-
-void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize)
-{
- int8_t kShift = 7 - shift; /* shift to apply after scaling */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Reading 4 inputs from memory */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- /* C = A * scale */
- /* Scale the inputs and then store the results in the temporary variables. */
- out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
- out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
- out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
- out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
-
- /* Packing the individual outputs into 32bit and storing in
- * destination buffer in single write */
- *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A * scale */
- /* Scale the input and then store the result in the destination buffer. */
- *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of scale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c
deleted file mode 100644
index e1f8982..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_shift_q15.c
- * Description: Shifts the elements of a Q15 vector by a specified number of bits
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup shift
- * @{
- */
-
-/**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- uint8_t sign; /* Sign of shiftBits */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t in1, in2; /* Temporary variables */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Getting the sign of shiftBits */
- sign = (shiftBits & 0x80);
-
- /* If the shift value is positive then do right shift else left shift */
- if (sign == 0u)
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Read 2 inputs */
- in1 = *pSrc++;
- in2 = *pSrc++;
- /* C = A << shiftBits */
- /* Shift the inputs and then store the results in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
- __SSAT((in2 << shiftBits), 16), 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
- __SSAT((in1 << shiftBits), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- in1 = *pSrc++;
- in2 = *pSrc++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
- __SSAT((in2 << shiftBits), 16), 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
- __SSAT((in1 << shiftBits), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Shift and then store the results in the destination buffer. */
- *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Read 2 inputs */
- in1 = *pSrc++;
- in2 = *pSrc++;
-
- /* C = A >> shiftBits */
- /* Shift the inputs and then store the results in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
- (in2 >> -shiftBits), 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
- (in1 >> -shiftBits), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- in1 = *pSrc++;
- in2 = *pSrc++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
- (in2 >> -shiftBits), 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
- (in1 >> -shiftBits), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Shift the inputs and then store the results in the destination buffer. */
- *pDst++ = (*pSrc++ >> -shiftBits);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Getting the sign of shiftBits */
- sign = (shiftBits & 0x80);
-
- /* If the shift value is positive then do right shift else left shift */
- if (sign == 0u)
- {
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Shift and then store the results in the destination buffer. */
- *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Shift the inputs and then store the results in the destination buffer. */
- *pDst++ = (*pSrc++ >> -shiftBits);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of shift group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c
deleted file mode 100644
index e495625..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_shift_q31.c
- * Description: Shifts the elements of a Q31 vector by a specified number of bits
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-/**
- * @defgroup shift Vector Shift
- *
- * Shifts the elements of a fixed-point vector by a specified number of bits.
- * There are separate functions for Q7, Q15, and Q31 data types.
- * The underlying algorithm used is:
- *
- *
- * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
- *
- *
- * If shift is positive then the elements of the vector are shifted to the left.
- * If shift is negative then the elements of the vector are shifted to the right.
- *
- * The functions support in-place computation allowing the source and destination
- * pointers to reference the same memory buffer.
- */
-
-/**
- * @addtogroup shift
- * @{
- */
-
-/**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
-
-#if defined (ARM_MATH_DSP)
-
- q31_t in1, in2, in3, in4; /* Temporary input variables */
- q31_t out1, out2, out3, out4; /* Temporary output variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
-
- if (sign == 0u)
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Shift the input and then store the results in the destination buffer. */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- out1 = in1 << shiftBits;
- in3 = *(pSrc + 2);
- out2 = in2 << shiftBits;
- in4 = *(pSrc + 3);
- if (in1 != (out1 >> shiftBits))
- out1 = 0x7FFFFFFF ^ (in1 >> 31);
-
- if (in2 != (out2 >> shiftBits))
- out2 = 0x7FFFFFFF ^ (in2 >> 31);
-
- *pDst = out1;
- out3 = in3 << shiftBits;
- *(pDst + 1) = out2;
- out4 = in4 << shiftBits;
-
- if (in3 != (out3 >> shiftBits))
- out3 = 0x7FFFFFFF ^ (in3 >> 31);
-
- if (in4 != (out4 >> shiftBits))
- out4 = 0x7FFFFFFF ^ (in4 >> 31);
-
- *(pDst + 2) = out3;
- *(pDst + 3) = out4;
-
- /* Update destination pointer to process next sampels */
- pSrc += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Shift the input and then store the results in the destination buffer. */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- *pDst = (in1 >> -shiftBits);
- *(pDst + 1) = (in2 >> -shiftBits);
- *(pDst + 2) = (in3 >> -shiftBits);
- *(pDst + 3) = (in4 >> -shiftBits);
-
-
- pSrc += 4u;
- pDst += 4u;
-
- blkCnt--;
- }
-
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A (>> or <<) shiftBits */
- /* Shift the input and then store the result in the destination buffer. */
- *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
- (*pSrc++ >> -shiftBits);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-}
-
-/**
- * @} end of shift group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
deleted file mode 100644
index 6080cb9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_shift_q7.c
- * Description: Processing function for the Q7 Shifting
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup shift
- * @{
- */
-
-
-/**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- *
- * \par Conditions for optimum performance
- * Input and output buffers should be aligned by 32-bit
- *
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
- */
-
-void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
- uint8_t sign; /* Sign of shiftBits */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q7_t in1; /* Input value1 */
- q7_t in2; /* Input value2 */
- q7_t in3; /* Input value3 */
- q7_t in4; /* Input value4 */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Getting the sign of shiftBits */
- sign = (shiftBits & 0x80);
-
- /* If the shift value is positive then do right shift else left shift */
- if (sign == 0u)
- {
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Read 4 inputs */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
- *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
- __SSAT((in2 << shiftBits), 8),
- __SSAT((in3 << shiftBits), 8),
- __SSAT((in4 << shiftBits), 8));
- /* Update source pointer to process next sampels */
- pSrc += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Shift the input and then store the result in the destination buffer. */
- *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- shiftBits = -shiftBits;
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Read 4 inputs */
- in1 = *pSrc;
- in2 = *(pSrc + 1);
- in3 = *(pSrc + 2);
- in4 = *(pSrc + 3);
-
- /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
- *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
- (in3 >> shiftBits), (in4 >> shiftBits));
-
-
- pSrc += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Shift the input and then store the result in the destination buffer. */
- in1 = *pSrc++;
- *pDst++ = (in1 >> shiftBits);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Getting the sign of shiftBits */
- sign = (shiftBits & 0x80);
-
- /* If the shift value is positive then do right shift else left shift */
- if (sign == 0u)
- {
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A << shiftBits */
- /* Shift the input and then store the result in the destination buffer. */
- *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A >> shiftBits */
- /* Shift the input and then store the result in the destination buffer. */
- *pDst++ = (*pSrc++ >> -shiftBits);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-/**
- * @} end of shift group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
deleted file mode 100644
index fe59c6e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sub_f32.c
- * Description: Floating-point vector subtraction.
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @defgroup BasicSub Vector Subtraction
- *
- * Element-by-element subtraction of two vectors.
- *
- *
- * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
- *
- *
- * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup BasicSub
- * @{
- */
-
-
-/**
- * @brief Floating-point vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
-void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t inA1, inA2, inA3, inA4; /* temporary variables */
- float32_t inB1, inB2, inB3, inB4; /* temporary variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the results in the destination buffer. */
- /* Read 4 input samples from sourceA and sourceB */
- inA1 = *pSrcA;
- inB1 = *pSrcB;
- inA2 = *(pSrcA + 1);
- inB2 = *(pSrcB + 1);
- inA3 = *(pSrcA + 2);
- inB3 = *(pSrcB + 2);
- inA4 = *(pSrcA + 3);
- inB4 = *(pSrcB + 3);
-
- /* dst = srcA - srcB */
- /* subtract and store the result */
- *pDst = inA1 - inB1;
- *(pDst + 1) = inA2 - inB2;
- *(pDst + 2) = inA3 - inB3;
- *(pDst + 3) = inA4 - inB4;
-
-
- /* Update pointers to process next sampels */
- pSrcA += 4u;
- pSrcB += 4u;
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the results in the destination buffer. */
- *pDst++ = (*pSrcA++) - (*pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
deleted file mode 100644
index 758f998..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sub_q15.c
- * Description: Q15 vector subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicSub
- * @{
- */
-
-/**
- * @brief Q15 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2;
- q31_t inB1, inB2;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the results in the destination buffer two samples at a time. */
- inA1 = *__SIMD32(pSrcA)++;
- inA2 = *__SIMD32(pSrcA)++;
- inB1 = *__SIMD32(pSrcB)++;
- inB2 = *__SIMD32(pSrcB)++;
-
- *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
- *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-}
-
-/**
- * @} end of BasicSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
deleted file mode 100644
index b63cada..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sub_q31.c
- * Description: Q31 vector subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicSub
- * @{
- */
-
-/**
- * @brief Q31 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inA1, inA2, inA3, inA4;
- q31_t inB1, inB2, inB3, inB4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the results in the destination buffer. */
- inA1 = *pSrcA++;
- inA2 = *pSrcA++;
- inB1 = *pSrcB++;
- inB2 = *pSrcB++;
-
- inA3 = *pSrcA++;
- inA4 = *pSrcA++;
- inB3 = *pSrcB++;
- inB4 = *pSrcB++;
-
- *pDst++ = __QSUB(inA1, inB1);
- *pDst++ = __QSUB(inA2, inB2);
- *pDst++ = __QSUB(inA3, inB3);
- *pDst++ = __QSUB(inA4, inB4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of BasicSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
deleted file mode 100644
index 8f62545..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sub_q7.c
- * Description: Q7 vector subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMath
- */
-
-/**
- * @addtogroup BasicSub
- * @{
- */
-
-/**
- * @brief Q7 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
- */
-
-void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the results in the destination buffer 4 samples at a time. */
- *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A - B */
- /* Subtract and then store the result in the destination buffer. */
- *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-}
-
-/**
- * @} end of BasicSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
deleted file mode 100644
index 1f8f589..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
+++ /dev/null
@@ -1,22176 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_common_tables.c
- * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup ComplexFFT
- */
-
-/**
- * @addtogroup CFFT_CIFFT Complex FFT Tables
- * @{
- */
-
-/**
-* \par
-* Pseudo code for Generation of Bit reversal Table is
-* \par
-* for(l=1;l <= N/4;l++)
-* {
-* for(i=0;i> 1;
-* }
-* \par
-* where N = 4096 logN2 = 12
-* \par
-* N is the maximum FFT Size supported
-*/
-
-/*
-* @brief Table for bit reversal process
-*/
-const uint16_t armBitRevTable[1024] = {
- 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280,
- 0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140,
- 0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0,
- 0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0,
- 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260,
- 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0,
- 0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,
- 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50,
- 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0,
- 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130,
- 0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0,
- 0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0,
- 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208,
- 0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,
- 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348,
- 0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28,
- 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8,
- 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168,
- 0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8,
- 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98,
- 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,
- 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8,
- 0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338,
- 0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78,
- 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8,
- 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104,
- 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384,
- 0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,
- 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224,
- 0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4,
- 0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364,
- 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14,
- 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294,
- 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154,
- 0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,
- 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4,
- 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274,
- 0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4,
- 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c,
- 0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c,
- 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc,
- 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,
- 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac,
- 0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec,
- 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c,
- 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c,
- 0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c,
- 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c,
- 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,
- 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c,
- 0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc,
- 0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82,
- 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242,
- 0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2,
- 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322,
- 0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,
- 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2,
- 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112,
- 0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392,
- 0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2,
- 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232,
- 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2,
- 0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,
- 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa,
- 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a,
- 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a,
- 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca,
- 0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0xaa,
- 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x6a, 0x46a, 0x26a,
- 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,
- 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a,
- 0x71a, 0x9a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a,
- 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, 0x4da, 0x2da,
- 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x3a, 0x43a, 0x23a, 0x63a, 0x13a,
- 0x53a, 0x33a, 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba,
- 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0xfa,
- 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,
- 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, 0x286, 0x686, 0x186,
- 0x586, 0x386, 0x786, 0x46, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346,
- 0x746, 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x26,
- 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0xa6, 0x4a6, 0x2a6,
- 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, 0x166,
- 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6,
- 0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,
- 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256,
- 0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6,
- 0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336,
- 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76,
- 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6,
- 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e,
- 0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,
- 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce,
- 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e,
- 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae,
- 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e,
- 0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e,
- 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e,
- 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,
- 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de,
- 0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe,
- 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e,
- 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe,
- 0x5fe, 0x3fe, 0x7fe, 0x1
-};
-
-
-/*
-* @brief Floating-point Twiddle factors Table Generation
-*/
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 16 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_16[32] = {
- 1.000000000f, 0.000000000f,
- 0.923879533f, 0.382683432f,
- 0.707106781f, 0.707106781f,
- 0.382683432f, 0.923879533f,
- 0.000000000f, 1.000000000f,
- -0.382683432f, 0.923879533f,
- -0.707106781f, 0.707106781f,
- -0.923879533f, 0.382683432f,
- -1.000000000f, 0.000000000f,
- -0.923879533f, -0.382683432f,
- -0.707106781f, -0.707106781f,
- -0.382683432f, -0.923879533f,
- -0.000000000f, -1.000000000f,
- 0.382683432f, -0.923879533f,
- 0.707106781f, -0.707106781f,
- 0.923879533f, -0.382683432f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 32 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_32[64] = {
- 1.000000000f, 0.000000000f,
- 0.980785280f, 0.195090322f,
- 0.923879533f, 0.382683432f,
- 0.831469612f, 0.555570233f,
- 0.707106781f, 0.707106781f,
- 0.555570233f, 0.831469612f,
- 0.382683432f, 0.923879533f,
- 0.195090322f, 0.980785280f,
- 0.000000000f, 1.000000000f,
- -0.195090322f, 0.980785280f,
- -0.382683432f, 0.923879533f,
- -0.555570233f, 0.831469612f,
- -0.707106781f, 0.707106781f,
- -0.831469612f, 0.555570233f,
- -0.923879533f, 0.382683432f,
- -0.980785280f, 0.195090322f,
- -1.000000000f, 0.000000000f,
- -0.980785280f, -0.195090322f,
- -0.923879533f, -0.382683432f,
- -0.831469612f, -0.555570233f,
- -0.707106781f, -0.707106781f,
- -0.555570233f, -0.831469612f,
- -0.382683432f, -0.923879533f,
- -0.195090322f, -0.980785280f,
- -0.000000000f, -1.000000000f,
- 0.195090322f, -0.980785280f,
- 0.382683432f, -0.923879533f,
- 0.555570233f, -0.831469612f,
- 0.707106781f, -0.707106781f,
- 0.831469612f, -0.555570233f,
- 0.923879533f, -0.382683432f,
- 0.980785280f, -0.195090322f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 64 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_64[128] = {
- 1.000000000f, 0.000000000f,
- 0.995184727f, 0.098017140f,
- 0.980785280f, 0.195090322f,
- 0.956940336f, 0.290284677f,
- 0.923879533f, 0.382683432f,
- 0.881921264f, 0.471396737f,
- 0.831469612f, 0.555570233f,
- 0.773010453f, 0.634393284f,
- 0.707106781f, 0.707106781f,
- 0.634393284f, 0.773010453f,
- 0.555570233f, 0.831469612f,
- 0.471396737f, 0.881921264f,
- 0.382683432f, 0.923879533f,
- 0.290284677f, 0.956940336f,
- 0.195090322f, 0.980785280f,
- 0.098017140f, 0.995184727f,
- 0.000000000f, 1.000000000f,
- -0.098017140f, 0.995184727f,
- -0.195090322f, 0.980785280f,
- -0.290284677f, 0.956940336f,
- -0.382683432f, 0.923879533f,
- -0.471396737f, 0.881921264f,
- -0.555570233f, 0.831469612f,
- -0.634393284f, 0.773010453f,
- -0.707106781f, 0.707106781f,
- -0.773010453f, 0.634393284f,
- -0.831469612f, 0.555570233f,
- -0.881921264f, 0.471396737f,
- -0.923879533f, 0.382683432f,
- -0.956940336f, 0.290284677f,
- -0.980785280f, 0.195090322f,
- -0.995184727f, 0.098017140f,
- -1.000000000f, 0.000000000f,
- -0.995184727f, -0.098017140f,
- -0.980785280f, -0.195090322f,
- -0.956940336f, -0.290284677f,
- -0.923879533f, -0.382683432f,
- -0.881921264f, -0.471396737f,
- -0.831469612f, -0.555570233f,
- -0.773010453f, -0.634393284f,
- -0.707106781f, -0.707106781f,
- -0.634393284f, -0.773010453f,
- -0.555570233f, -0.831469612f,
- -0.471396737f, -0.881921264f,
- -0.382683432f, -0.923879533f,
- -0.290284677f, -0.956940336f,
- -0.195090322f, -0.980785280f,
- -0.098017140f, -0.995184727f,
- -0.000000000f, -1.000000000f,
- 0.098017140f, -0.995184727f,
- 0.195090322f, -0.980785280f,
- 0.290284677f, -0.956940336f,
- 0.382683432f, -0.923879533f,
- 0.471396737f, -0.881921264f,
- 0.555570233f, -0.831469612f,
- 0.634393284f, -0.773010453f,
- 0.707106781f, -0.707106781f,
- 0.773010453f, -0.634393284f,
- 0.831469612f, -0.555570233f,
- 0.881921264f, -0.471396737f,
- 0.923879533f, -0.382683432f,
- 0.956940336f, -0.290284677f,
- 0.980785280f, -0.195090322f,
- 0.995184727f, -0.098017140f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 128 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-
-const float32_t twiddleCoef_128[256] = {
- 1.000000000f, 0.000000000f,
- 0.998795456f, 0.049067674f,
- 0.995184727f, 0.098017140f,
- 0.989176510f, 0.146730474f,
- 0.980785280f, 0.195090322f,
- 0.970031253f, 0.242980180f,
- 0.956940336f, 0.290284677f,
- 0.941544065f, 0.336889853f,
- 0.923879533f, 0.382683432f,
- 0.903989293f, 0.427555093f,
- 0.881921264f, 0.471396737f,
- 0.857728610f, 0.514102744f,
- 0.831469612f, 0.555570233f,
- 0.803207531f, 0.595699304f,
- 0.773010453f, 0.634393284f,
- 0.740951125f, 0.671558955f,
- 0.707106781f, 0.707106781f,
- 0.671558955f, 0.740951125f,
- 0.634393284f, 0.773010453f,
- 0.595699304f, 0.803207531f,
- 0.555570233f, 0.831469612f,
- 0.514102744f, 0.857728610f,
- 0.471396737f, 0.881921264f,
- 0.427555093f, 0.903989293f,
- 0.382683432f, 0.923879533f,
- 0.336889853f, 0.941544065f,
- 0.290284677f, 0.956940336f,
- 0.242980180f, 0.970031253f,
- 0.195090322f, 0.980785280f,
- 0.146730474f, 0.989176510f,
- 0.098017140f, 0.995184727f,
- 0.049067674f, 0.998795456f,
- 0.000000000f, 1.000000000f,
- -0.049067674f, 0.998795456f,
- -0.098017140f, 0.995184727f,
- -0.146730474f, 0.989176510f,
- -0.195090322f, 0.980785280f,
- -0.242980180f, 0.970031253f,
- -0.290284677f, 0.956940336f,
- -0.336889853f, 0.941544065f,
- -0.382683432f, 0.923879533f,
- -0.427555093f, 0.903989293f,
- -0.471396737f, 0.881921264f,
- -0.514102744f, 0.857728610f,
- -0.555570233f, 0.831469612f,
- -0.595699304f, 0.803207531f,
- -0.634393284f, 0.773010453f,
- -0.671558955f, 0.740951125f,
- -0.707106781f, 0.707106781f,
- -0.740951125f, 0.671558955f,
- -0.773010453f, 0.634393284f,
- -0.803207531f, 0.595699304f,
- -0.831469612f, 0.555570233f,
- -0.857728610f, 0.514102744f,
- -0.881921264f, 0.471396737f,
- -0.903989293f, 0.427555093f,
- -0.923879533f, 0.382683432f,
- -0.941544065f, 0.336889853f,
- -0.956940336f, 0.290284677f,
- -0.970031253f, 0.242980180f,
- -0.980785280f, 0.195090322f,
- -0.989176510f, 0.146730474f,
- -0.995184727f, 0.098017140f,
- -0.998795456f, 0.049067674f,
- -1.000000000f, 0.000000000f,
- -0.998795456f, -0.049067674f,
- -0.995184727f, -0.098017140f,
- -0.989176510f, -0.146730474f,
- -0.980785280f, -0.195090322f,
- -0.970031253f, -0.242980180f,
- -0.956940336f, -0.290284677f,
- -0.941544065f, -0.336889853f,
- -0.923879533f, -0.382683432f,
- -0.903989293f, -0.427555093f,
- -0.881921264f, -0.471396737f,
- -0.857728610f, -0.514102744f,
- -0.831469612f, -0.555570233f,
- -0.803207531f, -0.595699304f,
- -0.773010453f, -0.634393284f,
- -0.740951125f, -0.671558955f,
- -0.707106781f, -0.707106781f,
- -0.671558955f, -0.740951125f,
- -0.634393284f, -0.773010453f,
- -0.595699304f, -0.803207531f,
- -0.555570233f, -0.831469612f,
- -0.514102744f, -0.857728610f,
- -0.471396737f, -0.881921264f,
- -0.427555093f, -0.903989293f,
- -0.382683432f, -0.923879533f,
- -0.336889853f, -0.941544065f,
- -0.290284677f, -0.956940336f,
- -0.242980180f, -0.970031253f,
- -0.195090322f, -0.980785280f,
- -0.146730474f, -0.989176510f,
- -0.098017140f, -0.995184727f,
- -0.049067674f, -0.998795456f,
- -0.000000000f, -1.000000000f,
- 0.049067674f, -0.998795456f,
- 0.098017140f, -0.995184727f,
- 0.146730474f, -0.989176510f,
- 0.195090322f, -0.980785280f,
- 0.242980180f, -0.970031253f,
- 0.290284677f, -0.956940336f,
- 0.336889853f, -0.941544065f,
- 0.382683432f, -0.923879533f,
- 0.427555093f, -0.903989293f,
- 0.471396737f, -0.881921264f,
- 0.514102744f, -0.857728610f,
- 0.555570233f, -0.831469612f,
- 0.595699304f, -0.803207531f,
- 0.634393284f, -0.773010453f,
- 0.671558955f, -0.740951125f,
- 0.707106781f, -0.707106781f,
- 0.740951125f, -0.671558955f,
- 0.773010453f, -0.634393284f,
- 0.803207531f, -0.595699304f,
- 0.831469612f, -0.555570233f,
- 0.857728610f, -0.514102744f,
- 0.881921264f, -0.471396737f,
- 0.903989293f, -0.427555093f,
- 0.923879533f, -0.382683432f,
- 0.941544065f, -0.336889853f,
- 0.956940336f, -0.290284677f,
- 0.970031253f, -0.242980180f,
- 0.980785280f, -0.195090322f,
- 0.989176510f, -0.146730474f,
- 0.995184727f, -0.098017140f,
- 0.998795456f, -0.049067674f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 256 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_256[512] = {
- 1.000000000f, 0.000000000f,
- 0.999698819f, 0.024541229f,
- 0.998795456f, 0.049067674f,
- 0.997290457f, 0.073564564f,
- 0.995184727f, 0.098017140f,
- 0.992479535f, 0.122410675f,
- 0.989176510f, 0.146730474f,
- 0.985277642f, 0.170961889f,
- 0.980785280f, 0.195090322f,
- 0.975702130f, 0.219101240f,
- 0.970031253f, 0.242980180f,
- 0.963776066f, 0.266712757f,
- 0.956940336f, 0.290284677f,
- 0.949528181f, 0.313681740f,
- 0.941544065f, 0.336889853f,
- 0.932992799f, 0.359895037f,
- 0.923879533f, 0.382683432f,
- 0.914209756f, 0.405241314f,
- 0.903989293f, 0.427555093f,
- 0.893224301f, 0.449611330f,
- 0.881921264f, 0.471396737f,
- 0.870086991f, 0.492898192f,
- 0.857728610f, 0.514102744f,
- 0.844853565f, 0.534997620f,
- 0.831469612f, 0.555570233f,
- 0.817584813f, 0.575808191f,
- 0.803207531f, 0.595699304f,
- 0.788346428f, 0.615231591f,
- 0.773010453f, 0.634393284f,
- 0.757208847f, 0.653172843f,
- 0.740951125f, 0.671558955f,
- 0.724247083f, 0.689540545f,
- 0.707106781f, 0.707106781f,
- 0.689540545f, 0.724247083f,
- 0.671558955f, 0.740951125f,
- 0.653172843f, 0.757208847f,
- 0.634393284f, 0.773010453f,
- 0.615231591f, 0.788346428f,
- 0.595699304f, 0.803207531f,
- 0.575808191f, 0.817584813f,
- 0.555570233f, 0.831469612f,
- 0.534997620f, 0.844853565f,
- 0.514102744f, 0.857728610f,
- 0.492898192f, 0.870086991f,
- 0.471396737f, 0.881921264f,
- 0.449611330f, 0.893224301f,
- 0.427555093f, 0.903989293f,
- 0.405241314f, 0.914209756f,
- 0.382683432f, 0.923879533f,
- 0.359895037f, 0.932992799f,
- 0.336889853f, 0.941544065f,
- 0.313681740f, 0.949528181f,
- 0.290284677f, 0.956940336f,
- 0.266712757f, 0.963776066f,
- 0.242980180f, 0.970031253f,
- 0.219101240f, 0.975702130f,
- 0.195090322f, 0.980785280f,
- 0.170961889f, 0.985277642f,
- 0.146730474f, 0.989176510f,
- 0.122410675f, 0.992479535f,
- 0.098017140f, 0.995184727f,
- 0.073564564f, 0.997290457f,
- 0.049067674f, 0.998795456f,
- 0.024541229f, 0.999698819f,
- 0.000000000f, 1.000000000f,
- -0.024541229f, 0.999698819f,
- -0.049067674f, 0.998795456f,
- -0.073564564f, 0.997290457f,
- -0.098017140f, 0.995184727f,
- -0.122410675f, 0.992479535f,
- -0.146730474f, 0.989176510f,
- -0.170961889f, 0.985277642f,
- -0.195090322f, 0.980785280f,
- -0.219101240f, 0.975702130f,
- -0.242980180f, 0.970031253f,
- -0.266712757f, 0.963776066f,
- -0.290284677f, 0.956940336f,
- -0.313681740f, 0.949528181f,
- -0.336889853f, 0.941544065f,
- -0.359895037f, 0.932992799f,
- -0.382683432f, 0.923879533f,
- -0.405241314f, 0.914209756f,
- -0.427555093f, 0.903989293f,
- -0.449611330f, 0.893224301f,
- -0.471396737f, 0.881921264f,
- -0.492898192f, 0.870086991f,
- -0.514102744f, 0.857728610f,
- -0.534997620f, 0.844853565f,
- -0.555570233f, 0.831469612f,
- -0.575808191f, 0.817584813f,
- -0.595699304f, 0.803207531f,
- -0.615231591f, 0.788346428f,
- -0.634393284f, 0.773010453f,
- -0.653172843f, 0.757208847f,
- -0.671558955f, 0.740951125f,
- -0.689540545f, 0.724247083f,
- -0.707106781f, 0.707106781f,
- -0.724247083f, 0.689540545f,
- -0.740951125f, 0.671558955f,
- -0.757208847f, 0.653172843f,
- -0.773010453f, 0.634393284f,
- -0.788346428f, 0.615231591f,
- -0.803207531f, 0.595699304f,
- -0.817584813f, 0.575808191f,
- -0.831469612f, 0.555570233f,
- -0.844853565f, 0.534997620f,
- -0.857728610f, 0.514102744f,
- -0.870086991f, 0.492898192f,
- -0.881921264f, 0.471396737f,
- -0.893224301f, 0.449611330f,
- -0.903989293f, 0.427555093f,
- -0.914209756f, 0.405241314f,
- -0.923879533f, 0.382683432f,
- -0.932992799f, 0.359895037f,
- -0.941544065f, 0.336889853f,
- -0.949528181f, 0.313681740f,
- -0.956940336f, 0.290284677f,
- -0.963776066f, 0.266712757f,
- -0.970031253f, 0.242980180f,
- -0.975702130f, 0.219101240f,
- -0.980785280f, 0.195090322f,
- -0.985277642f, 0.170961889f,
- -0.989176510f, 0.146730474f,
- -0.992479535f, 0.122410675f,
- -0.995184727f, 0.098017140f,
- -0.997290457f, 0.073564564f,
- -0.998795456f, 0.049067674f,
- -0.999698819f, 0.024541229f,
- -1.000000000f, 0.000000000f,
- -0.999698819f, -0.024541229f,
- -0.998795456f, -0.049067674f,
- -0.997290457f, -0.073564564f,
- -0.995184727f, -0.098017140f,
- -0.992479535f, -0.122410675f,
- -0.989176510f, -0.146730474f,
- -0.985277642f, -0.170961889f,
- -0.980785280f, -0.195090322f,
- -0.975702130f, -0.219101240f,
- -0.970031253f, -0.242980180f,
- -0.963776066f, -0.266712757f,
- -0.956940336f, -0.290284677f,
- -0.949528181f, -0.313681740f,
- -0.941544065f, -0.336889853f,
- -0.932992799f, -0.359895037f,
- -0.923879533f, -0.382683432f,
- -0.914209756f, -0.405241314f,
- -0.903989293f, -0.427555093f,
- -0.893224301f, -0.449611330f,
- -0.881921264f, -0.471396737f,
- -0.870086991f, -0.492898192f,
- -0.857728610f, -0.514102744f,
- -0.844853565f, -0.534997620f,
- -0.831469612f, -0.555570233f,
- -0.817584813f, -0.575808191f,
- -0.803207531f, -0.595699304f,
- -0.788346428f, -0.615231591f,
- -0.773010453f, -0.634393284f,
- -0.757208847f, -0.653172843f,
- -0.740951125f, -0.671558955f,
- -0.724247083f, -0.689540545f,
- -0.707106781f, -0.707106781f,
- -0.689540545f, -0.724247083f,
- -0.671558955f, -0.740951125f,
- -0.653172843f, -0.757208847f,
- -0.634393284f, -0.773010453f,
- -0.615231591f, -0.788346428f,
- -0.595699304f, -0.803207531f,
- -0.575808191f, -0.817584813f,
- -0.555570233f, -0.831469612f,
- -0.534997620f, -0.844853565f,
- -0.514102744f, -0.857728610f,
- -0.492898192f, -0.870086991f,
- -0.471396737f, -0.881921264f,
- -0.449611330f, -0.893224301f,
- -0.427555093f, -0.903989293f,
- -0.405241314f, -0.914209756f,
- -0.382683432f, -0.923879533f,
- -0.359895037f, -0.932992799f,
- -0.336889853f, -0.941544065f,
- -0.313681740f, -0.949528181f,
- -0.290284677f, -0.956940336f,
- -0.266712757f, -0.963776066f,
- -0.242980180f, -0.970031253f,
- -0.219101240f, -0.975702130f,
- -0.195090322f, -0.980785280f,
- -0.170961889f, -0.985277642f,
- -0.146730474f, -0.989176510f,
- -0.122410675f, -0.992479535f,
- -0.098017140f, -0.995184727f,
- -0.073564564f, -0.997290457f,
- -0.049067674f, -0.998795456f,
- -0.024541229f, -0.999698819f,
- -0.000000000f, -1.000000000f,
- 0.024541229f, -0.999698819f,
- 0.049067674f, -0.998795456f,
- 0.073564564f, -0.997290457f,
- 0.098017140f, -0.995184727f,
- 0.122410675f, -0.992479535f,
- 0.146730474f, -0.989176510f,
- 0.170961889f, -0.985277642f,
- 0.195090322f, -0.980785280f,
- 0.219101240f, -0.975702130f,
- 0.242980180f, -0.970031253f,
- 0.266712757f, -0.963776066f,
- 0.290284677f, -0.956940336f,
- 0.313681740f, -0.949528181f,
- 0.336889853f, -0.941544065f,
- 0.359895037f, -0.932992799f,
- 0.382683432f, -0.923879533f,
- 0.405241314f, -0.914209756f,
- 0.427555093f, -0.903989293f,
- 0.449611330f, -0.893224301f,
- 0.471396737f, -0.881921264f,
- 0.492898192f, -0.870086991f,
- 0.514102744f, -0.857728610f,
- 0.534997620f, -0.844853565f,
- 0.555570233f, -0.831469612f,
- 0.575808191f, -0.817584813f,
- 0.595699304f, -0.803207531f,
- 0.615231591f, -0.788346428f,
- 0.634393284f, -0.773010453f,
- 0.653172843f, -0.757208847f,
- 0.671558955f, -0.740951125f,
- 0.689540545f, -0.724247083f,
- 0.707106781f, -0.707106781f,
- 0.724247083f, -0.689540545f,
- 0.740951125f, -0.671558955f,
- 0.757208847f, -0.653172843f,
- 0.773010453f, -0.634393284f,
- 0.788346428f, -0.615231591f,
- 0.803207531f, -0.595699304f,
- 0.817584813f, -0.575808191f,
- 0.831469612f, -0.555570233f,
- 0.844853565f, -0.534997620f,
- 0.857728610f, -0.514102744f,
- 0.870086991f, -0.492898192f,
- 0.881921264f, -0.471396737f,
- 0.893224301f, -0.449611330f,
- 0.903989293f, -0.427555093f,
- 0.914209756f, -0.405241314f,
- 0.923879533f, -0.382683432f,
- 0.932992799f, -0.359895037f,
- 0.941544065f, -0.336889853f,
- 0.949528181f, -0.313681740f,
- 0.956940336f, -0.290284677f,
- 0.963776066f, -0.266712757f,
- 0.970031253f, -0.242980180f,
- 0.975702130f, -0.219101240f,
- 0.980785280f, -0.195090322f,
- 0.985277642f, -0.170961889f,
- 0.989176510f, -0.146730474f,
- 0.992479535f, -0.122410675f,
- 0.995184727f, -0.098017140f,
- 0.997290457f, -0.073564564f,
- 0.998795456f, -0.049067674f,
- 0.999698819f, -0.024541229f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 512 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_512[1024] = {
- 1.000000000f, 0.000000000f,
- 0.999924702f, 0.012271538f,
- 0.999698819f, 0.024541229f,
- 0.999322385f, 0.036807223f,
- 0.998795456f, 0.049067674f,
- 0.998118113f, 0.061320736f,
- 0.997290457f, 0.073564564f,
- 0.996312612f, 0.085797312f,
- 0.995184727f, 0.098017140f,
- 0.993906970f, 0.110222207f,
- 0.992479535f, 0.122410675f,
- 0.990902635f, 0.134580709f,
- 0.989176510f, 0.146730474f,
- 0.987301418f, 0.158858143f,
- 0.985277642f, 0.170961889f,
- 0.983105487f, 0.183039888f,
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- 0.524589683f, -0.851355193f,
- 0.534997620f, -0.844853565f,
- 0.545324988f, -0.838224706f,
- 0.555570233f, -0.831469612f,
- 0.565731811f, -0.824589303f,
- 0.575808191f, -0.817584813f,
- 0.585797857f, -0.810457198f,
- 0.595699304f, -0.803207531f,
- 0.605511041f, -0.795836905f,
- 0.615231591f, -0.788346428f,
- 0.624859488f, -0.780737229f,
- 0.634393284f, -0.773010453f,
- 0.643831543f, -0.765167266f,
- 0.653172843f, -0.757208847f,
- 0.662415778f, -0.749136395f,
- 0.671558955f, -0.740951125f,
- 0.680600998f, -0.732654272f,
- 0.689540545f, -0.724247083f,
- 0.698376249f, -0.715730825f,
- 0.707106781f, -0.707106781f,
- 0.715730825f, -0.698376249f,
- 0.724247083f, -0.689540545f,
- 0.732654272f, -0.680600998f,
- 0.740951125f, -0.671558955f,
- 0.749136395f, -0.662415778f,
- 0.757208847f, -0.653172843f,
- 0.765167266f, -0.643831543f,
- 0.773010453f, -0.634393284f,
- 0.780737229f, -0.624859488f,
- 0.788346428f, -0.615231591f,
- 0.795836905f, -0.605511041f,
- 0.803207531f, -0.595699304f,
- 0.810457198f, -0.585797857f,
- 0.817584813f, -0.575808191f,
- 0.824589303f, -0.565731811f,
- 0.831469612f, -0.555570233f,
- 0.838224706f, -0.545324988f,
- 0.844853565f, -0.534997620f,
- 0.851355193f, -0.524589683f,
- 0.857728610f, -0.514102744f,
- 0.863972856f, -0.503538384f,
- 0.870086991f, -0.492898192f,
- 0.876070094f, -0.482183772f,
- 0.881921264f, -0.471396737f,
- 0.887639620f, -0.460538711f,
- 0.893224301f, -0.449611330f,
- 0.898674466f, -0.438616239f,
- 0.903989293f, -0.427555093f,
- 0.909167983f, -0.416429560f,
- 0.914209756f, -0.405241314f,
- 0.919113852f, -0.393992040f,
- 0.923879533f, -0.382683432f,
- 0.928506080f, -0.371317194f,
- 0.932992799f, -0.359895037f,
- 0.937339012f, -0.348418680f,
- 0.941544065f, -0.336889853f,
- 0.945607325f, -0.325310292f,
- 0.949528181f, -0.313681740f,
- 0.953306040f, -0.302005949f,
- 0.956940336f, -0.290284677f,
- 0.960430519f, -0.278519689f,
- 0.963776066f, -0.266712757f,
- 0.966976471f, -0.254865660f,
- 0.970031253f, -0.242980180f,
- 0.972939952f, -0.231058108f,
- 0.975702130f, -0.219101240f,
- 0.978317371f, -0.207111376f,
- 0.980785280f, -0.195090322f,
- 0.983105487f, -0.183039888f,
- 0.985277642f, -0.170961889f,
- 0.987301418f, -0.158858143f,
- 0.989176510f, -0.146730474f,
- 0.990902635f, -0.134580709f,
- 0.992479535f, -0.122410675f,
- 0.993906970f, -0.110222207f,
- 0.995184727f, -0.098017140f,
- 0.996312612f, -0.085797312f,
- 0.997290457f, -0.073564564f,
- 0.998118113f, -0.061320736f,
- 0.998795456f, -0.049067674f,
- 0.999322385f, -0.036807223f,
- 0.999698819f, -0.024541229f,
- 0.999924702f, -0.012271538f
-};
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 1024 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_1024[2048] = {
- 1.000000000f, 0.000000000f,
- 0.999981175f, 0.006135885f,
- 0.999924702f, 0.012271538f,
- 0.999830582f, 0.018406730f,
- 0.999698819f, 0.024541229f,
- 0.999529418f, 0.030674803f,
- 0.999322385f, 0.036807223f,
- 0.999077728f, 0.042938257f,
- 0.998795456f, 0.049067674f,
- 0.998475581f, 0.055195244f,
- 0.998118113f, 0.061320736f,
- 0.997723067f, 0.067443920f,
- 0.997290457f, 0.073564564f,
- 0.996820299f, 0.079682438f,
- 0.996312612f, 0.085797312f,
- 0.995767414f, 0.091908956f,
- 0.995184727f, 0.098017140f,
- 0.994564571f, 0.104121634f,
- 0.993906970f, 0.110222207f,
- 0.993211949f, 0.116318631f,
- 0.992479535f, 0.122410675f,
- 0.991709754f, 0.128498111f,
- 0.990902635f, 0.134580709f,
- 0.990058210f, 0.140658239f,
- 0.989176510f, 0.146730474f,
- 0.988257568f, 0.152797185f,
- 0.987301418f, 0.158858143f,
- 0.986308097f, 0.164913120f,
- 0.985277642f, 0.170961889f,
- 0.984210092f, 0.177004220f,
- 0.983105487f, 0.183039888f,
- 0.981963869f, 0.189068664f,
- 0.980785280f, 0.195090322f,
- 0.979569766f, 0.201104635f,
- 0.978317371f, 0.207111376f,
- 0.977028143f, 0.213110320f,
- 0.975702130f, 0.219101240f,
- 0.974339383f, 0.225083911f,
- 0.972939952f, 0.231058108f,
- 0.971503891f, 0.237023606f,
- 0.970031253f, 0.242980180f,
- 0.968522094f, 0.248927606f,
- 0.966976471f, 0.254865660f,
- 0.965394442f, 0.260794118f,
- 0.963776066f, 0.266712757f,
- 0.962121404f, 0.272621355f,
- 0.960430519f, 0.278519689f,
- 0.958703475f, 0.284407537f,
- 0.956940336f, 0.290284677f,
- 0.955141168f, 0.296150888f,
- 0.953306040f, 0.302005949f,
- 0.951435021f, 0.307849640f,
- 0.949528181f, 0.313681740f,
- 0.947585591f, 0.319502031f,
- 0.945607325f, 0.325310292f,
- 0.943593458f, 0.331106306f,
- 0.941544065f, 0.336889853f,
- 0.939459224f, 0.342660717f,
- 0.937339012f, 0.348418680f,
- 0.935183510f, 0.354163525f,
- 0.932992799f, 0.359895037f,
- 0.930766961f, 0.365612998f,
- 0.928506080f, 0.371317194f,
- 0.926210242f, 0.377007410f,
- 0.923879533f, 0.382683432f,
- 0.921514039f, 0.388345047f,
- 0.919113852f, 0.393992040f,
- 0.916679060f, 0.399624200f,
- 0.914209756f, 0.405241314f,
- 0.911706032f, 0.410843171f,
- 0.909167983f, 0.416429560f,
- 0.906595705f, 0.422000271f,
- 0.903989293f, 0.427555093f,
- 0.901348847f, 0.433093819f,
- 0.898674466f, 0.438616239f,
- 0.895966250f, 0.444122145f,
- 0.893224301f, 0.449611330f,
- 0.890448723f, 0.455083587f,
- 0.887639620f, 0.460538711f,
- 0.884797098f, 0.465976496f,
- 0.881921264f, 0.471396737f,
- 0.879012226f, 0.476799230f,
- 0.876070094f, 0.482183772f,
- 0.873094978f, 0.487550160f,
- 0.870086991f, 0.492898192f,
- 0.867046246f, 0.498227667f,
- 0.863972856f, 0.503538384f,
- 0.860866939f, 0.508830143f,
- 0.857728610f, 0.514102744f,
- 0.854557988f, 0.519355990f,
- 0.851355193f, 0.524589683f,
- 0.848120345f, 0.529803625f,
- 0.844853565f, 0.534997620f,
- 0.841554977f, 0.540171473f,
- 0.838224706f, 0.545324988f,
- 0.834862875f, 0.550457973f,
- 0.831469612f, 0.555570233f,
- 0.828045045f, 0.560661576f,
- 0.824589303f, 0.565731811f,
- 0.821102515f, 0.570780746f,
- 0.817584813f, 0.575808191f,
- 0.814036330f, 0.580813958f,
- 0.810457198f, 0.585797857f,
- 0.806847554f, 0.590759702f,
- 0.803207531f, 0.595699304f,
- 0.799537269f, 0.600616479f,
- 0.795836905f, 0.605511041f,
- 0.792106577f, 0.610382806f,
- 0.788346428f, 0.615231591f,
- 0.784556597f, 0.620057212f,
- 0.780737229f, 0.624859488f,
- 0.776888466f, 0.629638239f,
- 0.773010453f, 0.634393284f,
- 0.769103338f, 0.639124445f,
- 0.765167266f, 0.643831543f,
- 0.761202385f, 0.648514401f,
- 0.757208847f, 0.653172843f,
- 0.753186799f, 0.657806693f,
- 0.749136395f, 0.662415778f,
- 0.745057785f, 0.666999922f,
- 0.740951125f, 0.671558955f,
- 0.736816569f, 0.676092704f,
- 0.732654272f, 0.680600998f,
- 0.728464390f, 0.685083668f,
- 0.724247083f, 0.689540545f,
- 0.720002508f, 0.693971461f,
- 0.715730825f, 0.698376249f,
- 0.711432196f, 0.702754744f,
- 0.707106781f, 0.707106781f,
- 0.702754744f, 0.711432196f,
- 0.698376249f, 0.715730825f,
- 0.693971461f, 0.720002508f,
- 0.689540545f, 0.724247083f,
- 0.685083668f, 0.728464390f,
- 0.680600998f, 0.732654272f,
- 0.676092704f, 0.736816569f,
- 0.671558955f, 0.740951125f,
- 0.666999922f, 0.745057785f,
- 0.662415778f, 0.749136395f,
- 0.657806693f, 0.753186799f,
- 0.653172843f, 0.757208847f,
- 0.648514401f, 0.761202385f,
- 0.643831543f, 0.765167266f,
- 0.639124445f, 0.769103338f,
- 0.634393284f, 0.773010453f,
- 0.629638239f, 0.776888466f,
- 0.624859488f, 0.780737229f,
- 0.620057212f, 0.784556597f,
- 0.615231591f, 0.788346428f,
- 0.610382806f, 0.792106577f,
- 0.605511041f, 0.795836905f,
- 0.600616479f, 0.799537269f,
- 0.595699304f, 0.803207531f,
- 0.590759702f, 0.806847554f,
- 0.585797857f, 0.810457198f,
- 0.580813958f, 0.814036330f,
- 0.575808191f, 0.817584813f,
- 0.570780746f, 0.821102515f,
- 0.565731811f, 0.824589303f,
- 0.560661576f, 0.828045045f,
- 0.555570233f, 0.831469612f,
- 0.550457973f, 0.834862875f,
- 0.545324988f, 0.838224706f,
- 0.540171473f, 0.841554977f,
- 0.534997620f, 0.844853565f,
- 0.529803625f, 0.848120345f,
- 0.524589683f, 0.851355193f,
- 0.519355990f, 0.854557988f,
- 0.514102744f, 0.857728610f,
- 0.508830143f, 0.860866939f,
- 0.503538384f, 0.863972856f,
- 0.498227667f, 0.867046246f,
- 0.492898192f, 0.870086991f,
- 0.487550160f, 0.873094978f,
- 0.482183772f, 0.876070094f,
- 0.476799230f, 0.879012226f,
- 0.471396737f, 0.881921264f,
- 0.465976496f, 0.884797098f,
- 0.460538711f, 0.887639620f,
- 0.455083587f, 0.890448723f,
- 0.449611330f, 0.893224301f,
- 0.444122145f, 0.895966250f,
- 0.438616239f, 0.898674466f,
- 0.433093819f, 0.901348847f,
- 0.427555093f, 0.903989293f,
- 0.422000271f, 0.906595705f,
- 0.416429560f, 0.909167983f,
- 0.410843171f, 0.911706032f,
- 0.405241314f, 0.914209756f,
- 0.399624200f, 0.916679060f,
- 0.393992040f, 0.919113852f,
- 0.388345047f, 0.921514039f,
- 0.382683432f, 0.923879533f,
- 0.377007410f, 0.926210242f,
- 0.371317194f, 0.928506080f,
- 0.365612998f, 0.930766961f,
- 0.359895037f, 0.932992799f,
- 0.354163525f, 0.935183510f,
- 0.348418680f, 0.937339012f,
- 0.342660717f, 0.939459224f,
- 0.336889853f, 0.941544065f,
- 0.331106306f, 0.943593458f,
- 0.325310292f, 0.945607325f,
- 0.319502031f, 0.947585591f,
- 0.313681740f, 0.949528181f,
- 0.307849640f, 0.951435021f,
- 0.302005949f, 0.953306040f,
- 0.296150888f, 0.955141168f,
- 0.290284677f, 0.956940336f,
- 0.284407537f, 0.958703475f,
- 0.278519689f, 0.960430519f,
- 0.272621355f, 0.962121404f,
- 0.266712757f, 0.963776066f,
- 0.260794118f, 0.965394442f,
- 0.254865660f, 0.966976471f,
- 0.248927606f, 0.968522094f,
- 0.242980180f, 0.970031253f,
- 0.237023606f, 0.971503891f,
- 0.231058108f, 0.972939952f,
- 0.225083911f, 0.974339383f,
- 0.219101240f, 0.975702130f,
- 0.213110320f, 0.977028143f,
- 0.207111376f, 0.978317371f,
- 0.201104635f, 0.979569766f,
- 0.195090322f, 0.980785280f,
- 0.189068664f, 0.981963869f,
- 0.183039888f, 0.983105487f,
- 0.177004220f, 0.984210092f,
- 0.170961889f, 0.985277642f,
- 0.164913120f, 0.986308097f,
- 0.158858143f, 0.987301418f,
- 0.152797185f, 0.988257568f,
- 0.146730474f, 0.989176510f,
- 0.140658239f, 0.990058210f,
- 0.134580709f, 0.990902635f,
- 0.128498111f, 0.991709754f,
- 0.122410675f, 0.992479535f,
- 0.116318631f, 0.993211949f,
- 0.110222207f, 0.993906970f,
- 0.104121634f, 0.994564571f,
- 0.098017140f, 0.995184727f,
- 0.091908956f, 0.995767414f,
- 0.085797312f, 0.996312612f,
- 0.079682438f, 0.996820299f,
- 0.073564564f, 0.997290457f,
- 0.067443920f, 0.997723067f,
- 0.061320736f, 0.998118113f,
- 0.055195244f, 0.998475581f,
- 0.049067674f, 0.998795456f,
- 0.042938257f, 0.999077728f,
- 0.036807223f, 0.999322385f,
- 0.030674803f, 0.999529418f,
- 0.024541229f, 0.999698819f,
- 0.018406730f, 0.999830582f,
- 0.012271538f, 0.999924702f,
- 0.006135885f, 0.999981175f,
- 0.000000000f, 1.000000000f,
- -0.006135885f, 0.999981175f,
- -0.012271538f, 0.999924702f,
- -0.018406730f, 0.999830582f,
- -0.024541229f, 0.999698819f,
- -0.030674803f, 0.999529418f,
- -0.036807223f, 0.999322385f,
- -0.042938257f, 0.999077728f,
- -0.049067674f, 0.998795456f,
- -0.055195244f, 0.998475581f,
- -0.061320736f, 0.998118113f,
- -0.067443920f, 0.997723067f,
- -0.073564564f, 0.997290457f,
- -0.079682438f, 0.996820299f,
- -0.085797312f, 0.996312612f,
- -0.091908956f, 0.995767414f,
- -0.098017140f, 0.995184727f,
- -0.104121634f, 0.994564571f,
- -0.110222207f, 0.993906970f,
- -0.116318631f, 0.993211949f,
- -0.122410675f, 0.992479535f,
- -0.128498111f, 0.991709754f,
- -0.134580709f, 0.990902635f,
- -0.140658239f, 0.990058210f,
- -0.146730474f, 0.989176510f,
- -0.152797185f, 0.988257568f,
- -0.158858143f, 0.987301418f,
- -0.164913120f, 0.986308097f,
- -0.170961889f, 0.985277642f,
- -0.177004220f, 0.984210092f,
- -0.183039888f, 0.983105487f,
- -0.189068664f, 0.981963869f,
- -0.195090322f, 0.980785280f,
- -0.201104635f, 0.979569766f,
- -0.207111376f, 0.978317371f,
- -0.213110320f, 0.977028143f,
- -0.219101240f, 0.975702130f,
- -0.225083911f, 0.974339383f,
- -0.231058108f, 0.972939952f,
- -0.237023606f, 0.971503891f,
- -0.242980180f, 0.970031253f,
- -0.248927606f, 0.968522094f,
- -0.254865660f, 0.966976471f,
- -0.260794118f, 0.965394442f,
- -0.266712757f, 0.963776066f,
- -0.272621355f, 0.962121404f,
- -0.278519689f, 0.960430519f,
- -0.284407537f, 0.958703475f,
- -0.290284677f, 0.956940336f,
- -0.296150888f, 0.955141168f,
- -0.302005949f, 0.953306040f,
- -0.307849640f, 0.951435021f,
- -0.313681740f, 0.949528181f,
- -0.319502031f, 0.947585591f,
- -0.325310292f, 0.945607325f,
- -0.331106306f, 0.943593458f,
- -0.336889853f, 0.941544065f,
- -0.342660717f, 0.939459224f,
- -0.348418680f, 0.937339012f,
- -0.354163525f, 0.935183510f,
- -0.359895037f, 0.932992799f,
- -0.365612998f, 0.930766961f,
- -0.371317194f, 0.928506080f,
- -0.377007410f, 0.926210242f,
- -0.382683432f, 0.923879533f,
- -0.388345047f, 0.921514039f,
- -0.393992040f, 0.919113852f,
- -0.399624200f, 0.916679060f,
- -0.405241314f, 0.914209756f,
- -0.410843171f, 0.911706032f,
- -0.416429560f, 0.909167983f,
- -0.422000271f, 0.906595705f,
- -0.427555093f, 0.903989293f,
- -0.433093819f, 0.901348847f,
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- -0.225083911f, -0.974339383f,
- -0.219101240f, -0.975702130f,
- -0.213110320f, -0.977028143f,
- -0.207111376f, -0.978317371f,
- -0.201104635f, -0.979569766f,
- -0.195090322f, -0.980785280f,
- -0.189068664f, -0.981963869f,
- -0.183039888f, -0.983105487f,
- -0.177004220f, -0.984210092f,
- -0.170961889f, -0.985277642f,
- -0.164913120f, -0.986308097f,
- -0.158858143f, -0.987301418f,
- -0.152797185f, -0.988257568f,
- -0.146730474f, -0.989176510f,
- -0.140658239f, -0.990058210f,
- -0.134580709f, -0.990902635f,
- -0.128498111f, -0.991709754f,
- -0.122410675f, -0.992479535f,
- -0.116318631f, -0.993211949f,
- -0.110222207f, -0.993906970f,
- -0.104121634f, -0.994564571f,
- -0.098017140f, -0.995184727f,
- -0.091908956f, -0.995767414f,
- -0.085797312f, -0.996312612f,
- -0.079682438f, -0.996820299f,
- -0.073564564f, -0.997290457f,
- -0.067443920f, -0.997723067f,
- -0.061320736f, -0.998118113f,
- -0.055195244f, -0.998475581f,
- -0.049067674f, -0.998795456f,
- -0.042938257f, -0.999077728f,
- -0.036807223f, -0.999322385f,
- -0.030674803f, -0.999529418f,
- -0.024541229f, -0.999698819f,
- -0.018406730f, -0.999830582f,
- -0.012271538f, -0.999924702f,
- -0.006135885f, -0.999981175f,
- -0.000000000f, -1.000000000f,
- 0.006135885f, -0.999981175f,
- 0.012271538f, -0.999924702f,
- 0.018406730f, -0.999830582f,
- 0.024541229f, -0.999698819f,
- 0.030674803f, -0.999529418f,
- 0.036807223f, -0.999322385f,
- 0.042938257f, -0.999077728f,
- 0.049067674f, -0.998795456f,
- 0.055195244f, -0.998475581f,
- 0.061320736f, -0.998118113f,
- 0.067443920f, -0.997723067f,
- 0.073564564f, -0.997290457f,
- 0.079682438f, -0.996820299f,
- 0.085797312f, -0.996312612f,
- 0.091908956f, -0.995767414f,
- 0.098017140f, -0.995184727f,
- 0.104121634f, -0.994564571f,
- 0.110222207f, -0.993906970f,
- 0.116318631f, -0.993211949f,
- 0.122410675f, -0.992479535f,
- 0.128498111f, -0.991709754f,
- 0.134580709f, -0.990902635f,
- 0.140658239f, -0.990058210f,
- 0.146730474f, -0.989176510f,
- 0.152797185f, -0.988257568f,
- 0.158858143f, -0.987301418f,
- 0.164913120f, -0.986308097f,
- 0.170961889f, -0.985277642f,
- 0.177004220f, -0.984210092f,
- 0.183039888f, -0.983105487f,
- 0.189068664f, -0.981963869f,
- 0.195090322f, -0.980785280f,
- 0.201104635f, -0.979569766f,
- 0.207111376f, -0.978317371f,
- 0.213110320f, -0.977028143f,
- 0.219101240f, -0.975702130f,
- 0.225083911f, -0.974339383f,
- 0.231058108f, -0.972939952f,
- 0.237023606f, -0.971503891f,
- 0.242980180f, -0.970031253f,
- 0.248927606f, -0.968522094f,
- 0.254865660f, -0.966976471f,
- 0.260794118f, -0.965394442f,
- 0.266712757f, -0.963776066f,
- 0.272621355f, -0.962121404f,
- 0.278519689f, -0.960430519f,
- 0.284407537f, -0.958703475f,
- 0.290284677f, -0.956940336f,
- 0.296150888f, -0.955141168f,
- 0.302005949f, -0.953306040f,
- 0.307849640f, -0.951435021f,
- 0.313681740f, -0.949528181f,
- 0.319502031f, -0.947585591f,
- 0.325310292f, -0.945607325f,
- 0.331106306f, -0.943593458f,
- 0.336889853f, -0.941544065f,
- 0.342660717f, -0.939459224f,
- 0.348418680f, -0.937339012f,
- 0.354163525f, -0.935183510f,
- 0.359895037f, -0.932992799f,
- 0.365612998f, -0.930766961f,
- 0.371317194f, -0.928506080f,
- 0.377007410f, -0.926210242f,
- 0.382683432f, -0.923879533f,
- 0.388345047f, -0.921514039f,
- 0.393992040f, -0.919113852f,
- 0.399624200f, -0.916679060f,
- 0.405241314f, -0.914209756f,
- 0.410843171f, -0.911706032f,
- 0.416429560f, -0.909167983f,
- 0.422000271f, -0.906595705f,
- 0.427555093f, -0.903989293f,
- 0.433093819f, -0.901348847f,
- 0.438616239f, -0.898674466f,
- 0.444122145f, -0.895966250f,
- 0.449611330f, -0.893224301f,
- 0.455083587f, -0.890448723f,
- 0.460538711f, -0.887639620f,
- 0.465976496f, -0.884797098f,
- 0.471396737f, -0.881921264f,
- 0.476799230f, -0.879012226f,
- 0.482183772f, -0.876070094f,
- 0.487550160f, -0.873094978f,
- 0.492898192f, -0.870086991f,
- 0.498227667f, -0.867046246f,
- 0.503538384f, -0.863972856f,
- 0.508830143f, -0.860866939f,
- 0.514102744f, -0.857728610f,
- 0.519355990f, -0.854557988f,
- 0.524589683f, -0.851355193f,
- 0.529803625f, -0.848120345f,
- 0.534997620f, -0.844853565f,
- 0.540171473f, -0.841554977f,
- 0.545324988f, -0.838224706f,
- 0.550457973f, -0.834862875f,
- 0.555570233f, -0.831469612f,
- 0.560661576f, -0.828045045f,
- 0.565731811f, -0.824589303f,
- 0.570780746f, -0.821102515f,
- 0.575808191f, -0.817584813f,
- 0.580813958f, -0.814036330f,
- 0.585797857f, -0.810457198f,
- 0.590759702f, -0.806847554f,
- 0.595699304f, -0.803207531f,
- 0.600616479f, -0.799537269f,
- 0.605511041f, -0.795836905f,
- 0.610382806f, -0.792106577f,
- 0.615231591f, -0.788346428f,
- 0.620057212f, -0.784556597f,
- 0.624859488f, -0.780737229f,
- 0.629638239f, -0.776888466f,
- 0.634393284f, -0.773010453f,
- 0.639124445f, -0.769103338f,
- 0.643831543f, -0.765167266f,
- 0.648514401f, -0.761202385f,
- 0.653172843f, -0.757208847f,
- 0.657806693f, -0.753186799f,
- 0.662415778f, -0.749136395f,
- 0.666999922f, -0.745057785f,
- 0.671558955f, -0.740951125f,
- 0.676092704f, -0.736816569f,
- 0.680600998f, -0.732654272f,
- 0.685083668f, -0.728464390f,
- 0.689540545f, -0.724247083f,
- 0.693971461f, -0.720002508f,
- 0.698376249f, -0.715730825f,
- 0.702754744f, -0.711432196f,
- 0.707106781f, -0.707106781f,
- 0.711432196f, -0.702754744f,
- 0.715730825f, -0.698376249f,
- 0.720002508f, -0.693971461f,
- 0.724247083f, -0.689540545f,
- 0.728464390f, -0.685083668f,
- 0.732654272f, -0.680600998f,
- 0.736816569f, -0.676092704f,
- 0.740951125f, -0.671558955f,
- 0.745057785f, -0.666999922f,
- 0.749136395f, -0.662415778f,
- 0.753186799f, -0.657806693f,
- 0.757208847f, -0.653172843f,
- 0.761202385f, -0.648514401f,
- 0.765167266f, -0.643831543f,
- 0.769103338f, -0.639124445f,
- 0.773010453f, -0.634393284f,
- 0.776888466f, -0.629638239f,
- 0.780737229f, -0.624859488f,
- 0.784556597f, -0.620057212f,
- 0.788346428f, -0.615231591f,
- 0.792106577f, -0.610382806f,
- 0.795836905f, -0.605511041f,
- 0.799537269f, -0.600616479f,
- 0.803207531f, -0.595699304f,
- 0.806847554f, -0.590759702f,
- 0.810457198f, -0.585797857f,
- 0.814036330f, -0.580813958f,
- 0.817584813f, -0.575808191f,
- 0.821102515f, -0.570780746f,
- 0.824589303f, -0.565731811f,
- 0.828045045f, -0.560661576f,
- 0.831469612f, -0.555570233f,
- 0.834862875f, -0.550457973f,
- 0.838224706f, -0.545324988f,
- 0.841554977f, -0.540171473f,
- 0.844853565f, -0.534997620f,
- 0.848120345f, -0.529803625f,
- 0.851355193f, -0.524589683f,
- 0.854557988f, -0.519355990f,
- 0.857728610f, -0.514102744f,
- 0.860866939f, -0.508830143f,
- 0.863972856f, -0.503538384f,
- 0.867046246f, -0.498227667f,
- 0.870086991f, -0.492898192f,
- 0.873094978f, -0.487550160f,
- 0.876070094f, -0.482183772f,
- 0.879012226f, -0.476799230f,
- 0.881921264f, -0.471396737f,
- 0.884797098f, -0.465976496f,
- 0.887639620f, -0.460538711f,
- 0.890448723f, -0.455083587f,
- 0.893224301f, -0.449611330f,
- 0.895966250f, -0.444122145f,
- 0.898674466f, -0.438616239f,
- 0.901348847f, -0.433093819f,
- 0.903989293f, -0.427555093f,
- 0.906595705f, -0.422000271f,
- 0.909167983f, -0.416429560f,
- 0.911706032f, -0.410843171f,
- 0.914209756f, -0.405241314f,
- 0.916679060f, -0.399624200f,
- 0.919113852f, -0.393992040f,
- 0.921514039f, -0.388345047f,
- 0.923879533f, -0.382683432f,
- 0.926210242f, -0.377007410f,
- 0.928506080f, -0.371317194f,
- 0.930766961f, -0.365612998f,
- 0.932992799f, -0.359895037f,
- 0.935183510f, -0.354163525f,
- 0.937339012f, -0.348418680f,
- 0.939459224f, -0.342660717f,
- 0.941544065f, -0.336889853f,
- 0.943593458f, -0.331106306f,
- 0.945607325f, -0.325310292f,
- 0.947585591f, -0.319502031f,
- 0.949528181f, -0.313681740f,
- 0.951435021f, -0.307849640f,
- 0.953306040f, -0.302005949f,
- 0.955141168f, -0.296150888f,
- 0.956940336f, -0.290284677f,
- 0.958703475f, -0.284407537f,
- 0.960430519f, -0.278519689f,
- 0.962121404f, -0.272621355f,
- 0.963776066f, -0.266712757f,
- 0.965394442f, -0.260794118f,
- 0.966976471f, -0.254865660f,
- 0.968522094f, -0.248927606f,
- 0.970031253f, -0.242980180f,
- 0.971503891f, -0.237023606f,
- 0.972939952f, -0.231058108f,
- 0.974339383f, -0.225083911f,
- 0.975702130f, -0.219101240f,
- 0.977028143f, -0.213110320f,
- 0.978317371f, -0.207111376f,
- 0.979569766f, -0.201104635f,
- 0.980785280f, -0.195090322f,
- 0.981963869f, -0.189068664f,
- 0.983105487f, -0.183039888f,
- 0.984210092f, -0.177004220f,
- 0.985277642f, -0.170961889f,
- 0.986308097f, -0.164913120f,
- 0.987301418f, -0.158858143f,
- 0.988257568f, -0.152797185f,
- 0.989176510f, -0.146730474f,
- 0.990058210f, -0.140658239f,
- 0.990902635f, -0.134580709f,
- 0.991709754f, -0.128498111f,
- 0.992479535f, -0.122410675f,
- 0.993211949f, -0.116318631f,
- 0.993906970f, -0.110222207f,
- 0.994564571f, -0.104121634f,
- 0.995184727f, -0.098017140f,
- 0.995767414f, -0.091908956f,
- 0.996312612f, -0.085797312f,
- 0.996820299f, -0.079682438f,
- 0.997290457f, -0.073564564f,
- 0.997723067f, -0.067443920f,
- 0.998118113f, -0.061320736f,
- 0.998475581f, -0.055195244f,
- 0.998795456f, -0.049067674f,
- 0.999077728f, -0.042938257f,
- 0.999322385f, -0.036807223f,
- 0.999529418f, -0.030674803f,
- 0.999698819f, -0.024541229f,
- 0.999830582f, -0.018406730f,
- 0.999924702f, -0.012271538f,
- 0.999981175f, -0.006135885f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 2048 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_2048[4096] = {
- 1.000000000f, 0.000000000f,
- 0.999995294f, 0.003067957f,
- 0.999981175f, 0.006135885f,
- 0.999957645f, 0.009203755f,
- 0.999924702f, 0.012271538f,
- 0.999882347f, 0.015339206f,
- 0.999830582f, 0.018406730f,
- 0.999769405f, 0.021474080f,
- 0.999698819f, 0.024541229f,
- 0.999618822f, 0.027608146f,
- 0.999529418f, 0.030674803f,
- 0.999430605f, 0.033741172f,
- 0.999322385f, 0.036807223f,
- 0.999204759f, 0.039872928f,
- 0.999077728f, 0.042938257f,
- 0.998941293f, 0.046003182f,
- 0.998795456f, 0.049067674f,
- 0.998640218f, 0.052131705f,
- 0.998475581f, 0.055195244f,
- 0.998301545f, 0.058258265f,
- 0.998118113f, 0.061320736f,
- 0.997925286f, 0.064382631f,
- 0.997723067f, 0.067443920f,
- 0.997511456f, 0.070504573f,
- 0.997290457f, 0.073564564f,
- 0.997060070f, 0.076623861f,
- 0.996820299f, 0.079682438f,
- 0.996571146f, 0.082740265f,
- 0.996312612f, 0.085797312f,
- 0.996044701f, 0.088853553f,
- 0.995767414f, 0.091908956f,
- 0.995480755f, 0.094963495f,
- 0.995184727f, 0.098017140f,
- 0.994879331f, 0.101069863f,
- 0.994564571f, 0.104121634f,
- 0.994240449f, 0.107172425f,
- 0.993906970f, 0.110222207f,
- 0.993564136f, 0.113270952f,
- 0.993211949f, 0.116318631f,
- 0.992850414f, 0.119365215f,
- 0.992479535f, 0.122410675f,
- 0.992099313f, 0.125454983f,
- 0.991709754f, 0.128498111f,
- 0.991310860f, 0.131540029f,
- 0.990902635f, 0.134580709f,
- 0.990485084f, 0.137620122f,
- 0.990058210f, 0.140658239f,
- 0.989622017f, 0.143695033f,
- 0.989176510f, 0.146730474f,
- 0.988721692f, 0.149764535f,
- 0.988257568f, 0.152797185f,
- 0.987784142f, 0.155828398f,
- 0.987301418f, 0.158858143f,
- 0.986809402f, 0.161886394f,
- 0.986308097f, 0.164913120f,
- 0.985797509f, 0.167938295f,
- 0.985277642f, 0.170961889f,
- 0.984748502f, 0.173983873f,
- 0.984210092f, 0.177004220f,
- 0.983662419f, 0.180022901f,
- 0.983105487f, 0.183039888f,
- 0.982539302f, 0.186055152f,
- 0.981963869f, 0.189068664f,
- 0.981379193f, 0.192080397f,
- 0.980785280f, 0.195090322f,
- 0.980182136f, 0.198098411f,
- 0.979569766f, 0.201104635f,
- 0.978948175f, 0.204108966f,
- 0.978317371f, 0.207111376f,
- 0.977677358f, 0.210111837f,
- 0.977028143f, 0.213110320f,
- 0.976369731f, 0.216106797f,
- 0.975702130f, 0.219101240f,
- 0.975025345f, 0.222093621f,
- 0.974339383f, 0.225083911f,
- 0.973644250f, 0.228072083f,
- 0.972939952f, 0.231058108f,
- 0.972226497f, 0.234041959f,
- 0.971503891f, 0.237023606f,
- 0.970772141f, 0.240003022f,
- 0.970031253f, 0.242980180f,
- 0.969281235f, 0.245955050f,
- 0.968522094f, 0.248927606f,
- 0.967753837f, 0.251897818f,
- 0.966976471f, 0.254865660f,
- 0.966190003f, 0.257831102f,
- 0.965394442f, 0.260794118f,
- 0.964589793f, 0.263754679f,
- 0.963776066f, 0.266712757f,
- 0.962953267f, 0.269668326f,
- 0.962121404f, 0.272621355f,
- 0.961280486f, 0.275571819f,
- 0.960430519f, 0.278519689f,
- 0.959571513f, 0.281464938f,
- 0.958703475f, 0.284407537f,
- 0.957826413f, 0.287347460f,
- 0.956940336f, 0.290284677f,
- 0.956045251f, 0.293219163f,
- 0.955141168f, 0.296150888f,
- 0.954228095f, 0.299079826f,
- 0.953306040f, 0.302005949f,
- 0.952375013f, 0.304929230f,
- 0.951435021f, 0.307849640f,
- 0.950486074f, 0.310767153f,
- 0.949528181f, 0.313681740f,
- 0.948561350f, 0.316593376f,
- 0.947585591f, 0.319502031f,
- 0.946600913f, 0.322407679f,
- 0.945607325f, 0.325310292f,
- 0.944604837f, 0.328209844f,
- 0.943593458f, 0.331106306f,
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- 0.620057212f, -0.784556597f,
- 0.622461279f, -0.782650596f,
- 0.624859488f, -0.780737229f,
- 0.627251815f, -0.778816512f,
- 0.629638239f, -0.776888466f,
- 0.632018736f, -0.774953107f,
- 0.634393284f, -0.773010453f,
- 0.636761861f, -0.771060524f,
- 0.639124445f, -0.769103338f,
- 0.641481013f, -0.767138912f,
- 0.643831543f, -0.765167266f,
- 0.646176013f, -0.763188417f,
- 0.648514401f, -0.761202385f,
- 0.650846685f, -0.759209189f,
- 0.653172843f, -0.757208847f,
- 0.655492853f, -0.755201377f,
- 0.657806693f, -0.753186799f,
- 0.660114342f, -0.751165132f,
- 0.662415778f, -0.749136395f,
- 0.664710978f, -0.747100606f,
- 0.666999922f, -0.745057785f,
- 0.669282588f, -0.743007952f,
- 0.671558955f, -0.740951125f,
- 0.673829000f, -0.738887324f,
- 0.676092704f, -0.736816569f,
- 0.678350043f, -0.734738878f,
- 0.680600998f, -0.732654272f,
- 0.682845546f, -0.730562769f,
- 0.685083668f, -0.728464390f,
- 0.687315341f, -0.726359155f,
- 0.689540545f, -0.724247083f,
- 0.691759258f, -0.722128194f,
- 0.693971461f, -0.720002508f,
- 0.696177131f, -0.717870045f,
- 0.698376249f, -0.715730825f,
- 0.700568794f, -0.713584869f,
- 0.702754744f, -0.711432196f,
- 0.704934080f, -0.709272826f,
- 0.707106781f, -0.707106781f,
- 0.709272826f, -0.704934080f,
- 0.711432196f, -0.702754744f,
- 0.713584869f, -0.700568794f,
- 0.715730825f, -0.698376249f,
- 0.717870045f, -0.696177131f,
- 0.720002508f, -0.693971461f,
- 0.722128194f, -0.691759258f,
- 0.724247083f, -0.689540545f,
- 0.726359155f, -0.687315341f,
- 0.728464390f, -0.685083668f,
- 0.730562769f, -0.682845546f,
- 0.732654272f, -0.680600998f,
- 0.734738878f, -0.678350043f,
- 0.736816569f, -0.676092704f,
- 0.738887324f, -0.673829000f,
- 0.740951125f, -0.671558955f,
- 0.743007952f, -0.669282588f,
- 0.745057785f, -0.666999922f,
- 0.747100606f, -0.664710978f,
- 0.749136395f, -0.662415778f,
- 0.751165132f, -0.660114342f,
- 0.753186799f, -0.657806693f,
- 0.755201377f, -0.655492853f,
- 0.757208847f, -0.653172843f,
- 0.759209189f, -0.650846685f,
- 0.761202385f, -0.648514401f,
- 0.763188417f, -0.646176013f,
- 0.765167266f, -0.643831543f,
- 0.767138912f, -0.641481013f,
- 0.769103338f, -0.639124445f,
- 0.771060524f, -0.636761861f,
- 0.773010453f, -0.634393284f,
- 0.774953107f, -0.632018736f,
- 0.776888466f, -0.629638239f,
- 0.778816512f, -0.627251815f,
- 0.780737229f, -0.624859488f,
- 0.782650596f, -0.622461279f,
- 0.784556597f, -0.620057212f,
- 0.786455214f, -0.617647308f,
- 0.788346428f, -0.615231591f,
- 0.790230221f, -0.612810082f,
- 0.792106577f, -0.610382806f,
- 0.793975478f, -0.607949785f,
- 0.795836905f, -0.605511041f,
- 0.797690841f, -0.603066599f,
- 0.799537269f, -0.600616479f,
- 0.801376172f, -0.598160707f,
- 0.803207531f, -0.595699304f,
- 0.805031331f, -0.593232295f,
- 0.806847554f, -0.590759702f,
- 0.808656182f, -0.588281548f,
- 0.810457198f, -0.585797857f,
- 0.812250587f, -0.583308653f,
- 0.814036330f, -0.580813958f,
- 0.815814411f, -0.578313796f,
- 0.817584813f, -0.575808191f,
- 0.819347520f, -0.573297167f,
- 0.821102515f, -0.570780746f,
- 0.822849781f, -0.568258953f,
- 0.824589303f, -0.565731811f,
- 0.826321063f, -0.563199344f,
- 0.828045045f, -0.560661576f,
- 0.829761234f, -0.558118531f,
- 0.831469612f, -0.555570233f,
- 0.833170165f, -0.553016706f,
- 0.834862875f, -0.550457973f,
- 0.836547727f, -0.547894059f,
- 0.838224706f, -0.545324988f,
- 0.839893794f, -0.542750785f,
- 0.841554977f, -0.540171473f,
- 0.843208240f, -0.537587076f,
- 0.844853565f, -0.534997620f,
- 0.846490939f, -0.532403128f,
- 0.848120345f, -0.529803625f,
- 0.849741768f, -0.527199135f,
- 0.851355193f, -0.524589683f,
- 0.852960605f, -0.521975293f,
- 0.854557988f, -0.519355990f,
- 0.856147328f, -0.516731799f,
- 0.857728610f, -0.514102744f,
- 0.859301818f, -0.511468850f,
- 0.860866939f, -0.508830143f,
- 0.862423956f, -0.506186645f,
- 0.863972856f, -0.503538384f,
- 0.865513624f, -0.500885383f,
- 0.867046246f, -0.498227667f,
- 0.868570706f, -0.495565262f,
- 0.870086991f, -0.492898192f,
- 0.871595087f, -0.490226483f,
- 0.873094978f, -0.487550160f,
- 0.874586652f, -0.484869248f,
- 0.876070094f, -0.482183772f,
- 0.877545290f, -0.479493758f,
- 0.879012226f, -0.476799230f,
- 0.880470889f, -0.474100215f,
- 0.881921264f, -0.471396737f,
- 0.883363339f, -0.468688822f,
- 0.884797098f, -0.465976496f,
- 0.886222530f, -0.463259784f,
- 0.887639620f, -0.460538711f,
- 0.889048356f, -0.457813304f,
- 0.890448723f, -0.455083587f,
- 0.891840709f, -0.452349587f,
- 0.893224301f, -0.449611330f,
- 0.894599486f, -0.446868840f,
- 0.895966250f, -0.444122145f,
- 0.897324581f, -0.441371269f,
- 0.898674466f, -0.438616239f,
- 0.900015892f, -0.435857080f,
- 0.901348847f, -0.433093819f,
- 0.902673318f, -0.430326481f,
- 0.903989293f, -0.427555093f,
- 0.905296759f, -0.424779681f,
- 0.906595705f, -0.422000271f,
- 0.907886116f, -0.419216888f,
- 0.909167983f, -0.416429560f,
- 0.910441292f, -0.413638312f,
- 0.911706032f, -0.410843171f,
- 0.912962190f, -0.408044163f,
- 0.914209756f, -0.405241314f,
- 0.915448716f, -0.402434651f,
- 0.916679060f, -0.399624200f,
- 0.917900776f, -0.396809987f,
- 0.919113852f, -0.393992040f,
- 0.920318277f, -0.391170384f,
- 0.921514039f, -0.388345047f,
- 0.922701128f, -0.385516054f,
- 0.923879533f, -0.382683432f,
- 0.925049241f, -0.379847209f,
- 0.926210242f, -0.377007410f,
- 0.927362526f, -0.374164063f,
- 0.928506080f, -0.371317194f,
- 0.929640896f, -0.368466830f,
- 0.930766961f, -0.365612998f,
- 0.931884266f, -0.362755724f,
- 0.932992799f, -0.359895037f,
- 0.934092550f, -0.357030961f,
- 0.935183510f, -0.354163525f,
- 0.936265667f, -0.351292756f,
- 0.937339012f, -0.348418680f,
- 0.938403534f, -0.345541325f,
- 0.939459224f, -0.342660717f,
- 0.940506071f, -0.339776884f,
- 0.941544065f, -0.336889853f,
- 0.942573198f, -0.333999651f,
- 0.943593458f, -0.331106306f,
- 0.944604837f, -0.328209844f,
- 0.945607325f, -0.325310292f,
- 0.946600913f, -0.322407679f,
- 0.947585591f, -0.319502031f,
- 0.948561350f, -0.316593376f,
- 0.949528181f, -0.313681740f,
- 0.950486074f, -0.310767153f,
- 0.951435021f, -0.307849640f,
- 0.952375013f, -0.304929230f,
- 0.953306040f, -0.302005949f,
- 0.954228095f, -0.299079826f,
- 0.955141168f, -0.296150888f,
- 0.956045251f, -0.293219163f,
- 0.956940336f, -0.290284677f,
- 0.957826413f, -0.287347460f,
- 0.958703475f, -0.284407537f,
- 0.959571513f, -0.281464938f,
- 0.960430519f, -0.278519689f,
- 0.961280486f, -0.275571819f,
- 0.962121404f, -0.272621355f,
- 0.962953267f, -0.269668326f,
- 0.963776066f, -0.266712757f,
- 0.964589793f, -0.263754679f,
- 0.965394442f, -0.260794118f,
- 0.966190003f, -0.257831102f,
- 0.966976471f, -0.254865660f,
- 0.967753837f, -0.251897818f,
- 0.968522094f, -0.248927606f,
- 0.969281235f, -0.245955050f,
- 0.970031253f, -0.242980180f,
- 0.970772141f, -0.240003022f,
- 0.971503891f, -0.237023606f,
- 0.972226497f, -0.234041959f,
- 0.972939952f, -0.231058108f,
- 0.973644250f, -0.228072083f,
- 0.974339383f, -0.225083911f,
- 0.975025345f, -0.222093621f,
- 0.975702130f, -0.219101240f,
- 0.976369731f, -0.216106797f,
- 0.977028143f, -0.213110320f,
- 0.977677358f, -0.210111837f,
- 0.978317371f, -0.207111376f,
- 0.978948175f, -0.204108966f,
- 0.979569766f, -0.201104635f,
- 0.980182136f, -0.198098411f,
- 0.980785280f, -0.195090322f,
- 0.981379193f, -0.192080397f,
- 0.981963869f, -0.189068664f,
- 0.982539302f, -0.186055152f,
- 0.983105487f, -0.183039888f,
- 0.983662419f, -0.180022901f,
- 0.984210092f, -0.177004220f,
- 0.984748502f, -0.173983873f,
- 0.985277642f, -0.170961889f,
- 0.985797509f, -0.167938295f,
- 0.986308097f, -0.164913120f,
- 0.986809402f, -0.161886394f,
- 0.987301418f, -0.158858143f,
- 0.987784142f, -0.155828398f,
- 0.988257568f, -0.152797185f,
- 0.988721692f, -0.149764535f,
- 0.989176510f, -0.146730474f,
- 0.989622017f, -0.143695033f,
- 0.990058210f, -0.140658239f,
- 0.990485084f, -0.137620122f,
- 0.990902635f, -0.134580709f,
- 0.991310860f, -0.131540029f,
- 0.991709754f, -0.128498111f,
- 0.992099313f, -0.125454983f,
- 0.992479535f, -0.122410675f,
- 0.992850414f, -0.119365215f,
- 0.993211949f, -0.116318631f,
- 0.993564136f, -0.113270952f,
- 0.993906970f, -0.110222207f,
- 0.994240449f, -0.107172425f,
- 0.994564571f, -0.104121634f,
- 0.994879331f, -0.101069863f,
- 0.995184727f, -0.098017140f,
- 0.995480755f, -0.094963495f,
- 0.995767414f, -0.091908956f,
- 0.996044701f, -0.088853553f,
- 0.996312612f, -0.085797312f,
- 0.996571146f, -0.082740265f,
- 0.996820299f, -0.079682438f,
- 0.997060070f, -0.076623861f,
- 0.997290457f, -0.073564564f,
- 0.997511456f, -0.070504573f,
- 0.997723067f, -0.067443920f,
- 0.997925286f, -0.064382631f,
- 0.998118113f, -0.061320736f,
- 0.998301545f, -0.058258265f,
- 0.998475581f, -0.055195244f,
- 0.998640218f, -0.052131705f,
- 0.998795456f, -0.049067674f,
- 0.998941293f, -0.046003182f,
- 0.999077728f, -0.042938257f,
- 0.999204759f, -0.039872928f,
- 0.999322385f, -0.036807223f,
- 0.999430605f, -0.033741172f,
- 0.999529418f, -0.030674803f,
- 0.999618822f, -0.027608146f,
- 0.999698819f, -0.024541229f,
- 0.999769405f, -0.021474080f,
- 0.999830582f, -0.018406730f,
- 0.999882347f, -0.015339206f,
- 0.999924702f, -0.012271538f,
- 0.999957645f, -0.009203755f,
- 0.999981175f, -0.006135885f,
- 0.999995294f, -0.003067957f
-};
-
-/**
-* \par
-* Example code for Floating-point Twiddle factors Generation:
-* \par
-* for(i = 0; i< N/; i++)
-* {
-* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 4096 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are in interleaved fashion
-*
-*/
-const float32_t twiddleCoef_4096[8192] = {
- 1.000000000f, 0.000000000f,
- 0.999998823f, 0.001533980f,
- 0.999995294f, 0.003067957f,
- 0.999989411f, 0.004601926f,
- 0.999981175f, 0.006135885f,
- 0.999970586f, 0.007669829f,
- 0.999957645f, 0.009203755f,
- 0.999942350f, 0.010737659f,
- 0.999924702f, 0.012271538f,
- 0.999904701f, 0.013805389f,
- 0.999882347f, 0.015339206f,
- 0.999857641f, 0.016872988f,
- 0.999830582f, 0.018406730f,
- 0.999801170f, 0.019940429f,
- 0.999769405f, 0.021474080f,
- 0.999735288f, 0.023007681f,
- 0.999698819f, 0.024541229f,
- 0.999659997f, 0.026074718f,
- 0.999618822f, 0.027608146f,
- 0.999575296f, 0.029141509f,
- 0.999529418f, 0.030674803f,
- 0.999481187f, 0.032208025f,
- 0.999430605f, 0.033741172f,
- 0.999377670f, 0.035274239f,
- 0.999322385f, 0.036807223f,
- 0.999264747f, 0.038340120f,
- 0.999204759f, 0.039872928f,
- 0.999142419f, 0.041405641f,
- 0.999077728f, 0.042938257f,
- 0.999010686f, 0.044470772f,
- 0.998941293f, 0.046003182f,
- 0.998869550f, 0.047535484f,
- 0.998795456f, 0.049067674f,
- 0.998719012f, 0.050599749f,
- 0.998640218f, 0.052131705f,
- 0.998559074f, 0.053663538f,
- 0.998475581f, 0.055195244f,
- 0.998389737f, 0.056726821f,
- 0.998301545f, 0.058258265f,
- 0.998211003f, 0.059789571f,
- 0.998118113f, 0.061320736f,
- 0.998022874f, 0.062851758f,
- 0.997925286f, 0.064382631f,
- 0.997825350f, 0.065913353f,
- 0.997723067f, 0.067443920f,
- 0.997618435f, 0.068974328f,
- 0.997511456f, 0.070504573f,
- 0.997402130f, 0.072034653f,
- 0.997290457f, 0.073564564f,
- 0.997176437f, 0.075094301f,
- 0.997060070f, 0.076623861f,
- 0.996941358f, 0.078153242f,
- 0.996820299f, 0.079682438f,
- 0.996696895f, 0.081211447f,
- 0.996571146f, 0.082740265f,
- 0.996443051f, 0.084268888f,
- 0.996312612f, 0.085797312f,
- 0.996179829f, 0.087325535f,
- 0.996044701f, 0.088853553f,
- 0.995907229f, 0.090381361f,
- 0.995767414f, 0.091908956f,
- 0.995625256f, 0.093436336f,
- 0.995480755f, 0.094963495f,
- 0.995333912f, 0.096490431f,
- 0.995184727f, 0.098017140f,
- 0.995033199f, 0.099543619f,
- 0.994879331f, 0.101069863f,
- 0.994723121f, 0.102595869f,
- 0.994564571f, 0.104121634f,
- 0.994403680f, 0.105647154f,
- 0.994240449f, 0.107172425f,
- 0.994074879f, 0.108697444f,
- 0.993906970f, 0.110222207f,
- 0.993736722f, 0.111746711f,
- 0.993564136f, 0.113270952f,
- 0.993389211f, 0.114794927f,
- 0.993211949f, 0.116318631f,
- 0.993032350f, 0.117842062f,
- 0.992850414f, 0.119365215f,
- 0.992666142f, 0.120888087f,
- 0.992479535f, 0.122410675f,
- 0.992290591f, 0.123932975f,
- 0.992099313f, 0.125454983f,
- 0.991905700f, 0.126976696f,
- 0.991709754f, 0.128498111f,
- 0.991511473f, 0.130019223f,
- 0.991310860f, 0.131540029f,
- 0.991107914f, 0.133060525f,
- 0.990902635f, 0.134580709f,
- 0.990695025f, 0.136100575f,
- 0.990485084f, 0.137620122f,
- 0.990272812f, 0.139139344f,
- 0.990058210f, 0.140658239f,
- 0.989841278f, 0.142176804f,
- 0.989622017f, 0.143695033f,
- 0.989400428f, 0.145212925f,
- 0.989176510f, 0.146730474f,
- 0.988950265f, 0.148247679f,
- 0.988721692f, 0.149764535f,
- 0.988490793f, 0.151281038f,
- 0.988257568f, 0.152797185f,
- 0.988022017f, 0.154312973f,
- 0.987784142f, 0.155828398f,
- 0.987543942f, 0.157343456f,
- 0.987301418f, 0.158858143f,
- 0.987056571f, 0.160372457f,
- 0.986809402f, 0.161886394f,
- 0.986559910f, 0.163399949f,
- 0.986308097f, 0.164913120f,
- 0.986053963f, 0.166425904f,
- 0.985797509f, 0.167938295f,
- 0.985538735f, 0.169450291f,
- 0.985277642f, 0.170961889f,
- 0.985014231f, 0.172473084f,
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- 0.909167983f, -0.416429560f,
- 0.909805708f, -0.415034424f,
- 0.910441292f, -0.413638312f,
- 0.911074734f, -0.412241227f,
- 0.911706032f, -0.410843171f,
- 0.912335185f, -0.409444149f,
- 0.912962190f, -0.408044163f,
- 0.913587048f, -0.406643217f,
- 0.914209756f, -0.405241314f,
- 0.914830312f, -0.403838458f,
- 0.915448716f, -0.402434651f,
- 0.916064966f, -0.401029897f,
- 0.916679060f, -0.399624200f,
- 0.917290997f, -0.398217562f,
- 0.917900776f, -0.396809987f,
- 0.918508394f, -0.395401479f,
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- 0.936803442f, -0.349856130f,
- 0.937339012f, -0.348418680f,
- 0.937872376f, -0.346980411f,
- 0.938403534f, -0.345541325f,
- 0.938932484f, -0.344101426f,
- 0.939459224f, -0.342660717f,
- 0.939983753f, -0.341219202f,
- 0.940506071f, -0.339776884f,
- 0.941026175f, -0.338333767f,
- 0.941544065f, -0.336889853f,
- 0.942059740f, -0.335445147f,
- 0.942573198f, -0.333999651f,
- 0.943084437f, -0.332553370f,
- 0.943593458f, -0.331106306f,
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- 0.972226497f, -0.234041959f,
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- 0.972939952f, -0.231058108f,
- 0.973293246f, -0.229565366f,
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- 0.974339383f, -0.225083911f,
- 0.974683511f, -0.223589029f,
- 0.975025345f, -0.222093621f,
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- 0.999857641f, -0.016872988f,
- 0.999882347f, -0.015339206f,
- 0.999904701f, -0.013805389f,
- 0.999924702f, -0.012271538f,
- 0.999942350f, -0.010737659f,
- 0.999957645f, -0.009203755f,
- 0.999970586f, -0.007669829f,
- 0.999981175f, -0.006135885f,
- 0.999989411f, -0.004601926f,
- 0.999995294f, -0.003067957f,
- 0.999998823f, -0.001533980f
-};
-
-/*
-* @brief Q31 Twiddle factors Table
-*/
-
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 16 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_16_q31[24] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000,
- (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
- (q31_t)0x5A82799A, (q31_t)0x5A82799A,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C,
- (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
- (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A,
- (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
- (q31_t)0x80000000, (q31_t)0x00000000,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2,
- (q31_t)0xA57D8666, (q31_t)0xA57D8666,
- (q31_t)0xCF043AB2, (q31_t)0x89BE50C3
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 32 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_32_q31[48] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000,
- (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
- (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
- (q31_t)0x6A6D98A4, (q31_t)0x471CECE6,
- (q31_t)0x5A82799A, (q31_t)0x5A82799A,
- (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C,
- (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
- (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F,
- (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
- (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A,
- (q31_t)0x9592675B, (q31_t)0x471CECE6,
- (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C,
- (q31_t)0x80000000, (q31_t)0x00000000,
- (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2,
- (q31_t)0x9592675B, (q31_t)0xB8E31319,
- (q31_t)0xA57D8666, (q31_t)0xA57D8666,
- (q31_t)0xB8E31319, (q31_t)0x9592675B,
- (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
- (q31_t)0xE70747C3, (q31_t)0x8275A0C0
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 64 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_64_q31[96] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F,
- (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C,
- (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
- (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC,
- (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A,
- (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6,
- (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D,
- (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
- (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000,
- (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2,
- (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
- (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319,
- (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53,
- (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6,
- (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3,
- (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970,
- (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0,
- (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A,
- (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666,
- (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F,
- (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3,
- (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 128 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_128_q31[192] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D,
- (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F,
- (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413,
- (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
- (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6,
- (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64,
- (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F,
- (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94,
- (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A,
- (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89,
- (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3,
- (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
- (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70,
- (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB,
- (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B,
- (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C,
- (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC,
- (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C,
- (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
- (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1,
- (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684,
- (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B,
- (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2,
- (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0,
- (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B,
- (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
- (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B,
- (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376,
- (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94,
- (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B,
- (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64,
- (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F,
- (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
- (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4,
- (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03,
- (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
- (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000,
- (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03,
- (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
- (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4,
- (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F,
- (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
- (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B,
- (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376,
- (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
- (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B,
- (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B,
- (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2,
- (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684,
- (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1,
- (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 256 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_256_q31[384] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182,
- (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
- (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F,
- (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9,
- (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
- (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE,
- (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1,
- (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB,
- (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C,
- (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287,
- (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84,
- (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
- (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14,
- (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50,
- (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81,
- (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3,
- (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC,
- (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF,
- (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF,
- (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A,
- (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2,
- (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830,
- (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4,
- (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F,
- (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6,
- (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960,
- (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7,
- (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6,
- (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013,
- (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62,
- (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413,
- (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D,
- (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D,
- (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A,
- (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F,
- (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E,
- (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3,
- (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049,
- (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D,
- (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000,
- (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182,
- (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6,
- (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F,
- (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91,
- (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95,
- (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE,
- (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2,
- (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1,
- (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E,
- (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
- (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC,
- (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84,
- (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648,
- (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14,
- (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319,
- (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81,
- (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B,
- (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
- (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D,
- (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20,
- (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2,
- (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53,
- (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4,
- (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E,
- (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6,
- (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB,
- (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7,
- (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B,
- (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013,
- (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3,
- (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62,
- (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E,
- (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
- (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411,
- (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16,
- (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E,
- (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970,
- (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049,
- (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D,
- (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000,
- (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872,
- (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C,
- (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91,
- (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0,
- (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95,
- (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62,
- (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
- (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC,
- (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA,
- (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC,
- (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A,
- (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648,
- (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F,
- (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319,
- (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0,
- (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0,
- (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D,
- (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666,
- (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20,
- (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510,
- (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
- (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C,
- (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF,
- (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
- (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F,
- (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78,
- (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
- (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14,
- (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A,
- (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411,
- (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3,
- (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4,
- (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
- (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683,
- (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 512 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_512_q31[768] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A,
- (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF,
- (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D,
- (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E,
- (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3,
- (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
- (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3,
- (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493,
- (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444,
- (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F,
- (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025,
- (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD,
- (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
- (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D,
- (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD,
- (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928,
- (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413,
- (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA,
- (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988,
- (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
- (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345,
- (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056,
- (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0,
- (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32,
- (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6,
- (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5,
- (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C,
- (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64,
- (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960,
- (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F,
- (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C,
- (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533,
- (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F,
- (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4,
- (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F,
- (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94,
- (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830,
- (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A,
- (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C,
- (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54,
- (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A,
- (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153,
- (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9,
- (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89,
- (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x539B2AEF,
- (q31_t)0x60EC3830, (q31_t)0x5269126E, (q31_t)0x61F1003E,
- (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4FFB654D,
- (q31_t)0x63EF328F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926,
- (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4C3FDFF3,
- (q31_t)0x66CF811F, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC,
- (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4869E664,
- (q31_t)0x698C246C, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4,
- (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x447ACD50,
- (q31_t)0x6C242960, (q31_t)0x4325C135, (q31_t)0x6CF934FB,
- (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4073F21D,
- (q31_t)0x6E96A99C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1,
- (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3C56BA70,
- (q31_t)0x70E2CBC6, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2,
- (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x382493B0,
- (q31_t)0x7307C3D0, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0,
- (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x33DEF287,
- (q31_t)0x7504D345, (q31_t)0x326E54C7, (q31_t)0x75A585CF,
- (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2F875262,
- (q31_t)0x76D94988, (q31_t)0x2E110A62, (q31_t)0x776C4EDB,
- (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2B1F34EB,
- (q31_t)0x78848413, (q31_t)0x29A3C484, (q31_t)0x7909A92C,
- (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x26A82185,
- (q31_t)0x7A05EEAD, (q31_t)0x25280C5D, (q31_t)0x7A7D055B,
- (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2223A4C5,
- (q31_t)0x7B5D039D, (q31_t)0x209F701C, (q31_t)0x7BC5E28F,
- (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1D934FE5,
- (q31_t)0x7C894BDD, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1,
- (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x18F8B83C,
- (q31_t)0x7D8A5F3F, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E,
- (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x145576B1,
- (q31_t)0x7E5FE493, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC,
- (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x0FAB272B,
- (q31_t)0x7F0991C3, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5,
- (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0AFB6805,
- (q31_t)0x7F872BF3, (q31_t)0x096A9049, (q31_t)0x7FA736B4,
- (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0647D97C,
- (q31_t)0x7FD8878D, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0,
- (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x01921D1F,
- (q31_t)0x7FFD885A, (q31_t)0x00000000, (q31_t)0x7FFFFFFF,
- (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFCDBD541,
- (q31_t)0x7FF62182, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0,
- (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF826A461,
- (q31_t)0x7FC25596, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4,
- (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF3742CA1,
- (q31_t)0x7F62368F, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5,
- (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEEC60F31,
- (q31_t)0x7ED5E5C6, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC,
- (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEA1DEBBB,
- (q31_t)0x7E1D93E9, (q31_t)0xE8922621, (q31_t)0x7DD6668E,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE57D5FDA,
- (q31_t)0x7D3980EC, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1,
- (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE0E60684,
- (q31_t)0x7C29FBEE, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F,
- (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDC597781,
- (q31_t)0x7AEF6323, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B,
- (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD7D946D7,
- (q31_t)0x798A23B1, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C,
- (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD3670445,
- (q31_t)0x77FAB988, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB,
- (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCF043AB2,
- (q31_t)0x7641AF3C, (q31_t)0xCD91AB38, (q31_t)0x75A585CF,
- (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCAB26FA9,
- (q31_t)0x745F9DD1, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0,
- (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC67322CD,
- (q31_t)0x72552C84, (q31_t)0xC50D1148, (q31_t)0x719E2CD2,
- (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC247CD5A,
- (q31_t)0x70231099, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1,
- (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBE31E19B,
- (q31_t)0x6DCA0D14, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB,
- (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBA32CA70,
- (q31_t)0x6B4AF278, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4,
- (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB64BEACC,
- (q31_t)0x68A69E81, (q31_t)0xB5049368, (q31_t)0x67BD0FBC,
- (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB27E9D3B,
- (q31_t)0x65DDFBD3, (q31_t)0xB140175B, (q31_t)0x64E88926,
- (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAECC336B,
- (q31_t)0x62F201AC, (q31_t)0xAD96ED91, (q31_t)0x61F1003E,
- (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAB35F5B5,
- (q31_t)0x5FE3B38D, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89,
- (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA7BD22AB,
- (q31_t)0x5CB420DF, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153,
- (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA462EEAC,
- (q31_t)0x59646497, (q31_t)0xA34BDF20, (q31_t)0x5842DD54,
- (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1288376,
- (q31_t)0x55F5A4D2, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A,
- (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E0EFFC1,
- (q31_t)0x5269126E, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94,
- (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B1776D9,
- (q31_t)0x4EBFE8A4, (q31_t)0x9A22042C, (q31_t)0x4D8162C4,
- (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9842F043,
- (q31_t)0x4AFB6C97, (q31_t)0x9759617E, (q31_t)0x49B41533,
- (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x9592675B,
- (q31_t)0x471CECE6, (q31_t)0x94B50D87, (q31_t)0x45CD358F,
- (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9306CB04,
- (q31_t)0x4325C135, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64,
- (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x90A0FD4E,
- (q31_t)0x3F1749B7, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5,
- (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8E61D32D,
- (q31_t)0x3AF2EEB7, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32,
- (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8C4A142F,
- (q31_t)0x36BA2013, (q31_t)0x8BA0622F, (q31_t)0x354D9056,
- (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8A5A7A30,
- (q31_t)0x326E54C7, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D,
- (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x8893B124,
- (q31_t)0x2E110A62, (q31_t)0x88054677, (q31_t)0x2C98FBBA,
- (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x86F656D3,
- (q31_t)0x29A3C484, (q31_t)0x8675DC4E, (q31_t)0x2826B928,
- (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x8582FAA4,
- (q31_t)0x25280C5D, (q31_t)0x85109CDC, (q31_t)0x23A6887E,
- (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x843A1D70,
- (q31_t)0x209F701C, (q31_t)0x83D60411, (q31_t)0x1F19F97B,
- (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x831C314E,
- (q31_t)0x1C0B826A, (q31_t)0x82C67F13, (q31_t)0x1A82A025,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82299971,
- (q31_t)0x176DD9DE, (q31_t)0x81E26C16, (q31_t)0x15E21444,
- (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8162AA03,
- (q31_t)0x12C8106E, (q31_t)0x812A1A39, (q31_t)0x1139F0CE,
- (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A,
- (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
- (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C,
- (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E,
- (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440,
- (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF,
- (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000,
- (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0,
- (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440,
- (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683,
- (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C,
- (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A,
- (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4,
- (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03,
- (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E,
- (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971,
- (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
- (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E,
- (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A,
- (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70,
- (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A,
- (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4,
- (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A,
- (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3,
- (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
- (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124,
- (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30,
- (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78,
- (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F,
- (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50,
- (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D,
- (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
- (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E,
- (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2,
- (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04,
- (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF,
- (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B,
- (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B,
- (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043,
- (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
- (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9,
- (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1,
- (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510,
- (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376,
- (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106,
- (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC,
- (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
- (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB,
- (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283,
- (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5,
- (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0,
- (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B,
- (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70,
- (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B,
- (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
- (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC,
- (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70,
- (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F,
- (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B,
- (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663,
- (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A,
- (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
- (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD,
- (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9,
- (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA,
- (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2,
- (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677,
- (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445,
- (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
- (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7,
- (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781,
- (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62,
- (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684,
- (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422,
- (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA,
- (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
- (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB,
- (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31,
- (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C,
- (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1,
- (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D,
- (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461,
- (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872,
- (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541,
- (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 1024 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_1024_q31[1536] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216,
- (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F,
- (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182,
- (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6,
- (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B,
- (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
- (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596,
- (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A,
- (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC,
- (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805,
- (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F,
- (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92,
- (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4,
- (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
- (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6,
- (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956,
- (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1,
- (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9,
- (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305,
- (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7,
- (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
- (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC,
- (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF,
- (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724,
- (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5,
- (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE,
- (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A,
- (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89,
- (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
- (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323,
- (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8,
- (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185,
- (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1,
- (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A,
- (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1,
- (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB,
- (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988,
- (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB,
- (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D,
- (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262,
- (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C,
- (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D,
- (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B,
- (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287,
- (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1,
- (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9,
- (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626,
- (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0,
- (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84,
- (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1,
- (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804,
- (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70,
- (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099,
- (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C,
- (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12,
- (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D,
- (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14,
- (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0,
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- (q31_t)0x66573CBB, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3,
- (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB140175B,
- (q31_t)0x64E88926, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF,
- (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAF6803A1,
- (q31_t)0x637114CC, (q31_t)0xAECC336B, (q31_t)0x62F201AC,
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- (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xABCCFD82,
- (q31_t)0x60686CCE, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D,
- (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA0A5B2D,
- (q31_t)0x5ED77C89, (q31_t)0xA975CB56, (q31_t)0x5E50015D,
- (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA84F2DA9,
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- (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA69B9B68,
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- (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA4EFCA31,
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- (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1AFFEA2,
- (q31_t)0x568A34A9, (q31_t)0xA1288376, (q31_t)0x55F5A4D2,
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- (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A22042C,
- (q31_t)0x4D8162C4, (q31_t)0x99A8C344, (q31_t)0x4CE10034,
- (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x98B93828,
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- (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x96029EB5,
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- (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x94B50D87,
- (q31_t)0x45CD358F, (q31_t)0x9447ED2F, (q31_t)0x452456BC,
- (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9370CAE4,
- (q31_t)0x43D09AEC, (q31_t)0x9306CB04, (q31_t)0x4325C135,
- (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9235F2EB,
- (q31_t)0x41CE1E64, (q31_t)0x91CF1CB6, (q31_t)0x4121589A,
- (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x9104A0ED,
- (q31_t)0x3FC5EC97, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7,
- (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x8FDCEF66,
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- (q31_t)0x3BA51E29, (q31_t)0x8E61D32D, (q31_t)0x3AF2EEB7,
- (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DAAD37B,
- (q31_t)0x398CDD32, (q31_t)0x8D50FA59, (q31_t)0x38D8FE93,
- (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CA099D9,
- (q31_t)0x376F9E46, (q31_t)0x8C4A142F, (q31_t)0x36BA2013,
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- (q31_t)0x354D9056, (q31_t)0x8B4D377C, (q31_t)0x3496824F,
- (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AAA42B4,
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- (q31_t)0x30FBC54D, (q31_t)0x8971F15A, (q31_t)0x3041C760,
- (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x88DCA0D3,
- (q31_t)0x2ECC681E, (q31_t)0x8893B124, (q31_t)0x2E110A62,
- (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x88054677,
- (q31_t)0x2C98FBBA, (q31_t)0x87BFCCD7, (q31_t)0x2BDC4E6F,
- (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8738545E,
- (q31_t)0x2A61B101, (q31_t)0x86F656D3, (q31_t)0x29A3C484,
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- (q31_t)0x2826B928, (q31_t)0x86376092, (q31_t)0x27679DF4,
- (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85BDEF27,
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- (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x85109CDC,
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- (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x846DF476,
- (q31_t)0x2161B39F, (q31_t)0x843A1D70, (q31_t)0x209F701C,
- (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83D60411,
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- (q31_t)0x183366E8, (q31_t)0x82299971, (q31_t)0x176DD9DE,
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- (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80277872,
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- (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A,
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- (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D,
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- (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30,
- (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C,
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- (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663,
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- (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805,
- (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA,
- (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F,
- (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943,
- (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B,
- (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319,
- (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94,
- (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811,
- (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855,
- (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368,
- (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0,
- (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB,
- (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D,
- (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B,
- (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70,
- (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596,
- (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91,
- (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0,
- (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82,
- (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C,
- (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D,
- (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283,
- (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9,
- (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533,
- (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68,
- (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666,
- (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31,
- (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173,
- (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20,
- (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106,
- (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2,
- (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D,
- (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72,
- (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510,
- (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94,
- (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91,
- (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53,
- (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2,
- (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640,
- (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8,
- (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C,
- (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C,
- (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828,
- (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362,
- (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
- (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B,
- (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8,
- (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87,
- (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF,
- (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4,
- (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F,
- (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
- (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2,
- (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED,
- (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3,
- (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66,
- (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F,
- (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB,
- (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E,
- (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
- (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50,
- (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527,
- (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F,
- (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78,
- (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4,
- (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2,
- (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
- (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D,
- (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3,
- (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504,
- (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677,
- (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14,
- (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E,
- (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5,
- (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
- (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A,
- (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8,
- (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC,
- (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A,
- (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476,
- (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5,
- (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411,
- (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A,
- (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB,
- (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10,
- (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13,
- (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3,
- (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208,
- (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB,
- (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
- (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E,
- (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B,
- (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39,
- (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4,
- (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C,
- (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D,
- (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
- (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA,
- (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143,
- (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65,
- (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69,
- (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683,
- (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894,
- (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919,
- (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D,
- (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0,
- (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 2048 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_2048_q31[3072] = {
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885,
- (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88,
- (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A,
- (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296,
- (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1,
- (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF,
- (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477,
- (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176,
- (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108,
- (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034,
- (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D,
- (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F,
- (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853,
- (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E,
- (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2,
- (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A,
- (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15,
- (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC,
- (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3,
- (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F,
- (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4,
- (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E,
- (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450,
- (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376,
- (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E,
- (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765,
- (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3,
- (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD,
- (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635,
- (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE,
- (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39,
- (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1,
- (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0,
- (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493,
- (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F,
- (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF,
- (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444,
- (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7,
- (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D,
- (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D,
- (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8,
- (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F,
- (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9,
- (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E,
- (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025,
- (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218,
- (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334,
- (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168,
- (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3,
- (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD,
- (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F,
- (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2,
- (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B,
- (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830,
- (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D,
- (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31,
- (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F,
- (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D,
- (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF,
- (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C,
- (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E,
- (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3,
- (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8,
- (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5,
- (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD,
- (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6,
- (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715,
- (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928,
- (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11,
- (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2,
- (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1,
- (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101,
- (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413,
- (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17,
- (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64,
- (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA,
- (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF,
- (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7,
- (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE,
- (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E,
- (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988,
- (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6,
- (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376,
- (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D,
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- (q31_t)0x209F701C, (q31_t)0x8420A46B, (q31_t)0x203E300D,
- (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83EE97AC,
- (q31_t)0x1F7B7480, (q31_t)0x83D60411, (q31_t)0x1F19F97B,
- (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83A5C2B0,
- (q31_t)0x1E56CA1E, (q31_t)0x838E1507, (q31_t)0x1DF5163F,
- (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x835FA00E,
- (q31_t)0x1D31774D, (q31_t)0x8348D8DB, (q31_t)0x1CCF8CB3,
- (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x831C314E,
- (q31_t)0x1C0B826A, (q31_t)0x8306510F, (q31_t)0x1BA96334,
- (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82DB77E5,
- (q31_t)0x1AE4F1D6, (q31_t)0x82C67F13, (q31_t)0x1A82A025,
- (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x829D753A,
- (q31_t)0x19BDCBF2, (q31_t)0x8289644A, (q31_t)0x195B49E9,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82622AA5,
- (q31_t)0x18961727, (q31_t)0x824F0208, (q31_t)0x183366E8,
- (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x82299971,
- (q31_t)0x176DD9DE, (q31_t)0x8217598F, (q31_t)0x170AFD8D,
- (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81F3C2D7,
- (q31_t)0x16451A83, (q31_t)0x81E26C16, (q31_t)0x15E21444,
- (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C0A801,
- (q31_t)0x151BDF85, (q31_t)0x81B03AC1, (q31_t)0x14B8B17F,
- (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x81904A0C,
- (q31_t)0x13F22F57, (q31_t)0x8180C6A9, (q31_t)0x138EDBB0,
- (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x8162AA03,
- (q31_t)0x12C8106E, (q31_t)0x815410D3, (q31_t)0x1264994E,
- (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x8137C8E6,
- (q31_t)0x119D8940, (q31_t)0x812A1A39, (q31_t)0x1139F0CE,
- (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x810FA7A0,
- (q31_t)0x1072A047, (q31_t)0x8102E3C3, (q31_t)0x100EE8AD,
- (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80EA4712,
- (q31_t)0x0F475BFE, (q31_t)0x80DE6E4C, (q31_t)0x0EE38765,
- (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80C7A80A,
- (q31_t)0x0E1BC2E3, (q31_t)0x80BCBA9C, (q31_t)0x0DB7D376,
- (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80A7CB49,
- (q31_t)0x0CEFDB75, (q31_t)0x809DC970, (q31_t)0x0C8BD35E,
- (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808AB180,
- (q31_t)0x0BC3AC35, (q31_t)0x80819B74, (q31_t)0x0B5F8D9F,
- (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80705B50,
- (q31_t)0x0A973BA5, (q31_t)0x80683143, (q31_t)0x0A3308BC,
- (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x8058C94C,
- (q31_t)0x096A9049, (q31_t)0x80518B6B, (q31_t)0x09064B3A,
- (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x8043FBF6,
- (q31_t)0x083DB0A7, (q31_t)0x803DAA69, (q31_t)0x07D95B9E,
- (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8031F3C1,
- (q31_t)0x0710A344, (q31_t)0x802C8EAD, (q31_t)0x06AC406F,
- (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8022B113,
- (q31_t)0x05E36EA9, (q31_t)0x801E3894, (q31_t)0x057F0034,
- (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x80163440,
- (q31_t)0x04B6195D, (q31_t)0x8012A86F, (q31_t)0x0451A176,
- (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800C7D8C,
- (q31_t)0x0388A9E9, (q31_t)0x8009DE7D, (q31_t)0x03242ABF,
- (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x80058D2E,
- (q31_t)0x025B26D7, (q31_t)0x8003DAF0, (q31_t)0x01F6A296,
- (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001634D,
- (q31_t)0x012D96B0, (q31_t)0x80009DE9, (q31_t)0x00C90F88,
- (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x80000000,
- (q31_t)0x00000000, (q31_t)0x8000277A, (q31_t)0xFF9B781D,
- (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8001634D,
- (q31_t)0xFED2694F, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0,
- (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x80058D2E,
- (q31_t)0xFDA4D928, (q31_t)0x80078E5E, (q31_t)0xFD40565B,
- (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800C7D8C,
- (q31_t)0xFC775616, (q31_t)0x800F6B88, (q31_t)0xFC12D919,
- (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x80163440,
- (q31_t)0xFB49E6A2, (q31_t)0x801A0EF7, (q31_t)0xFAE571A4,
- (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x8022B113,
- (q31_t)0xFA1C9156, (q31_t)0x80277872, (q31_t)0xF9B82683,
- (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x8031F3C1,
- (q31_t)0xF8EF5CBB, (q31_t)0x8037A7AC, (q31_t)0xF88AFE41,
- (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8043FBF6,
- (q31_t)0xF7C24F58, (q31_t)0x804A9C4D, (q31_t)0xF75DFF65,
- (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x8058C94C,
- (q31_t)0xF6956FB6, (q31_t)0x806055EA, (q31_t)0xF6313076,
- (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x80705B50,
- (q31_t)0xF568C45A, (q31_t)0x8078D40D, (q31_t)0xF50497FA,
- (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x808AB180,
- (q31_t)0xF43C53CA, (q31_t)0x8094162B, (q31_t)0xF3D83C76,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A7CB49,
- (q31_t)0xF310248A, (q31_t)0x80B21BAF, (q31_t)0xF2AC246D,
- (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C7A80A,
- (q31_t)0xF1E43D1C, (q31_t)0x80D2E3F1, (q31_t)0xF1805662,
- (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80EA4712,
- (q31_t)0xF0B8A401, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4,
- (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x810FA7A0,
- (q31_t)0xEF8D5FB8, (q31_t)0x811CB9CA, (q31_t)0xEF29B243,
- (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8137C8E6,
- (q31_t)0xEE6276BF, (q31_t)0x8145C5C6, (q31_t)0xEDFEE92B,
- (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x8162AA03,
- (q31_t)0xED37EF91, (q31_t)0x8171914E, (q31_t)0xECD48406,
- (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81904A0C,
- (q31_t)0xEC0DD0A8, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E,
- (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81C0A801,
- (q31_t)0xEAE4207A, (q31_t)0x81D16320, (q31_t)0xEA80FF79,
- (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81F3C2D7,
- (q31_t)0xE9BAE57C, (q31_t)0x82056758, (q31_t)0xE957ECFB,
- (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82299971,
- (q31_t)0xE8922621, (q31_t)0x823C26F2, (q31_t)0xE82F5844,
- (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82622AA5,
- (q31_t)0xE769E8D8, (q31_t)0x8275A0C0, (q31_t)0xE70747C3,
- (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x829D753A,
- (q31_t)0xE642340D, (q31_t)0x82B1D381, (q31_t)0xE5DFC1E4,
- (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82DB77E5,
- (q31_t)0xE51B0E2A, (q31_t)0x82F0BDE8, (q31_t)0xE4B8CD10,
- (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x831C314E,
- (q31_t)0xE3F47D95, (q31_t)0x83325E97, (q31_t)0xE3926FAC,
- (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835FA00E,
- (q31_t)0xE2CE88B2, (q31_t)0x8376B422, (q31_t)0xE26CB01A,
- (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x83A5C2B0,
- (q31_t)0xE1A935E1, (q31_t)0x83BDBD0D, (q31_t)0xE14794B9,
- (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83EE97AC,
- (q31_t)0xE0848B7F, (q31_t)0x840777CF, (q31_t)0xE02323E5,
- (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x843A1D70,
- (q31_t)0xDF608FE3, (q31_t)0x8453E2CE, (q31_t)0xDEFF63F4,
- (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84885257,
- (q31_t)0xDE3D4963, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A,
- (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84D934B0,
- (q31_t)0xDD1ABE51, (q31_t)0x84F4C2D3, (q31_t)0xDCBA1008,
- (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x852CC2BA,
- (q31_t)0xDBF8F4F8, (q31_t)0x8549345C, (q31_t)0xDB9888A8,
- (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x8582FAA4,
- (q31_t)0xDAD7F3A2, (q31_t)0x85A04F28, (q31_t)0xDA77CB62,
- (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85DBDA91,
- (q31_t)0xD9B7C093, (q31_t)0x85FA1152, (q31_t)0xD957DE7A,
- (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x86376092,
- (q31_t)0xD898620C, (q31_t)0x865678EA, (q31_t)0xD838C82D,
- (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86958AAB,
- (q31_t)0xD779DE46, (q31_t)0x86B583EE, (q31_t)0xD71A8EB5,
- (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86F656D3,
- (q31_t)0xD65C3B7B, (q31_t)0x8717304E, (q31_t)0xD5FD3847,
- (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x8759C2EF,
- (q31_t)0xD53F7FDA, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14,
- (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87BFCCD7,
- (q31_t)0xD423B190, (q31_t)0x87E2649B, (q31_t)0xD3C54D46,
- (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x88287255,
- (q31_t)0xD308D6C6, (q31_t)0x884BE820, (q31_t)0xD2AAC504,
- (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8893B124,
- (q31_t)0xD1EEF59E, (q31_t)0x88B80431, (q31_t)0xD191386D,
- (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x890186F1,
- (q31_t)0xD0D61433, (q31_t)0x8926B677, (q31_t)0xD078AD9D,
- (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x8971F15A,
- (q31_t)0xCFBE389F, (q31_t)0x8997FC89, (q31_t)0xCF612AAA,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89E4EDEE,
- (q31_t)0xCEA768F2, (q31_t)0x8A0BD3F5, (q31_t)0xCE4AB5A2,
- (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A5A7A30,
- (q31_t)0xCD91AB38, (q31_t)0x8A823A35, (q31_t)0xCD355490,
- (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AD29393,
- (q31_t)0xCC7D0577, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78,
- (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B4D377C,
- (q31_t)0xCB697DB0, (q31_t)0x8B76A8E4, (q31_t)0xCB0DE658,
- (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BCA6342,
- (q31_t)0xCA5719DB, (q31_t)0x8BF4AC05, (q31_t)0xC9FBE527,
- (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C4A142F,
- (q31_t)0xC945DFEC, (q31_t)0x8C753361, (q31_t)0xC8EB0FD6,
- (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CCC477D,
- (q31_t)0xC835D5D0, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50,
- (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D50FA59,
- (q31_t)0xC727016C, (q31_t)0x8D7DC399, (q31_t)0xC6CD0079,
- (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DD829E4,
- (q31_t)0xC61968A2, (q31_t)0x8E05C6B7, (q31_t)0xC5BFD22E,
- (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E61D32D,
- (q31_t)0xC50D1148, (q31_t)0x8E904298, (q31_t)0xC4B3E746,
- (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8EEDF33B,
- (q31_t)0xC4020132, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F,
- (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F7C8701,
- (q31_t)0xC2F83E2A, (q31_t)0x8FAC988E, (q31_t)0xC29FF2D4,
- (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x900D8B69,
- (q31_t)0xC1EFCDF2, (q31_t)0x903E6C7A, (q31_t)0xC197F4D3,
- (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90A0FD4E,
- (q31_t)0xC0E8B648, (q31_t)0x90D2ACD3, (q31_t)0xC0915147,
- (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x9136D97D,
- (q31_t)0xBFE2FCDF, (q31_t)0x91695663, (q31_t)0xBF8C0DE2,
- (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91CF1CB6,
- (q31_t)0xBEDEA765, (q31_t)0x920265E4, (q31_t)0xBE88304F,
- (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9269C3AC,
- (q31_t)0xBDDBBB7F, (q31_t)0x929DD805, (q31_t)0xBD85BE2F,
- (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x9306CB04,
- (q31_t)0xBCDA3ECA, (q31_t)0x933BA968, (q31_t)0xBC84BD1E,
- (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93A62F56,
- (q31_t)0xBBDA36DC, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF,
- (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x9447ED2F,
- (q31_t)0xBADBA943, (q31_t)0x947E5C32, (q31_t)0xBA87246C,
- (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94EC010B,
- (q31_t)0xB9DE9B83, (q31_t)0x9523369B, (q31_t)0xB98A97D8,
- (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x9592675B,
- (q31_t)0xB8E31319, (q31_t)0x95CA6246, (q31_t)0xB88F926C,
- (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x963B1C85,
- (q31_t)0xB7E9157A, (q31_t)0x9673DB94, (q31_t)0xB796199B,
- (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96E61CDF,
- (q31_t)0xB6F0A811, (q31_t)0x971F9ED6, (q31_t)0xB69E32CD,
- (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x979364B5,
- (q31_t)0xB5F9D042, (q31_t)0x97CDA855, (q31_t)0xB5A7E362,
- (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9842F043,
- (q31_t)0xB5049368, (q31_t)0x987DF449, (q31_t)0xB4B330B2,
- (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98F4BBBC,
- (q31_t)0xB410F6D2, (q31_t)0x99307EE0, (q31_t)0xB3C0200C,
- (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x99A8C344,
- (q31_t)0xB31EFFCB, (q31_t)0x99E5443A, (q31_t)0xB2CEB6B5,
- (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A5F02F5,
- (q31_t)0xB22EB392, (q31_t)0x9A9C406D, (q31_t)0xB1DEF9E8,
- (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9B1776D9,
- (q31_t)0xB140175B, (q31_t)0x9B556F80, (q31_t)0xB0F0EEDA,
- (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BD21AF2,
- (q31_t)0xB0533055, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2,
- (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C8EEB33,
- (q31_t)0xAF6803A1, (q31_t)0x9CCE562B, (q31_t)0xAF1A0293,
- (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D4DE384,
- (q31_t)0xAE7E965B, (q31_t)0x9D8E0596, (q31_t)0xAE312B91,
- (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9E0EFFC1,
- (q31_t)0xAD96ED91, (q31_t)0x9E4FD789, (q31_t)0xAD4A1ABA,
- (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9ED23BB9,
- (q31_t)0xACB10E4A, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510,
- (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F979331,
- (q31_t)0xABCCFD82, (q31_t)0x9FD9D22A, (q31_t)0xAB815F8C,
- (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA05F01E1,
- (q31_t)0xAAEAC02B, (q31_t)0xA0A1F24C, (q31_t)0xAA9FBF1D,
- (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA1288376,
- (q31_t)0xAA0A5B2D, (q31_t)0xA16C23E1, (q31_t)0xA9BFF8A8,
- (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1F41391,
- (q31_t)0xA92BD366, (q31_t)0xA2386283, (q31_t)0xA8E21106,
- (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA2C1ADC9,
- (q31_t)0xA84F2DA9, (q31_t)0xA306A9C7, (q31_t)0xA8060D08,
- (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3914DA7,
- (q31_t)0xA7746EC0, (q31_t)0xA3D6F533, (q31_t)0xA72BF173,
- (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA462EEAC,
- (q31_t)0xA69B9B68, (q31_t)0xA4A94042, (q31_t)0xA653C302,
- (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA5368C4B,
- (q31_t)0xA5C4B855, (q31_t)0xA57D8666, (q31_t)0xA57D8666,
- (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA60C21ED,
- (q31_t)0xA4EFCA31, (q31_t)0xA653C302, (q31_t)0xA4A94042,
- (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6E3AAF2,
- (q31_t)0xA41CD598, (q31_t)0xA72BF173, (q31_t)0xA3D6F533,
- (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA7BD22AB,
- (q31_t)0xA34BDF20, (q31_t)0xA8060D08, (q31_t)0xA306A9C7,
- (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8988463,
- (q31_t)0xA27CEB4F, (q31_t)0xA8E21106, (q31_t)0xA2386283,
- (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA975CB56,
- (q31_t)0xA1AFFEA2, (q31_t)0xA9BFF8A8, (q31_t)0xA16C23E1,
- (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA54F2B9,
- (q31_t)0xA0E51D8C, (q31_t)0xAA9FBF1D, (q31_t)0xA0A1F24C,
- (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB35F5B5,
- (q31_t)0xA01C4C72, (q31_t)0xAB815F8C, (q31_t)0x9FD9D22A,
- (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC18CF68,
- (q31_t)0x9F558FB0, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0,
- (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACFD7AE8,
- (q31_t)0x9E90EB94, (q31_t)0xAD4A1ABA, (q31_t)0x9E4FD789,
- (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADE3F33E,
- (q31_t)0x9DCE6462, (q31_t)0xAE312B91, (q31_t)0x9D8E0596,
- (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAECC336B,
- (q31_t)0x9D0DFE53, (q31_t)0xAF1A0293, (q31_t)0x9CCE562B,
- (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAFB63667,
- (q31_t)0x9C4FBD92, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70,
- (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB0A1F71C,
- (q31_t)0x9B93A640, (q31_t)0xB0F0EEDA, (q31_t)0x9B556F80,
- (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB18F7070,
- (q31_t)0x9AD9BC71, (q31_t)0xB1DEF9E8, (q31_t)0x9A9C406D,
- (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB27E9D3B,
- (q31_t)0x9A22042C, (q31_t)0xB2CEB6B5, (q31_t)0x99E5443A,
- (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB36F784E,
- (q31_t)0x996C816F, (q31_t)0xB3C0200C, (q31_t)0x99307EE0,
- (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB461FC70,
- (q31_t)0x98B93828, (q31_t)0xB4B330B2, (q31_t)0x987DF449,
- (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB556245E,
- (q31_t)0x98082C3B, (q31_t)0xB5A7E362, (q31_t)0x97CDA855,
- (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB64BEACC,
- (q31_t)0x9759617E, (q31_t)0xB69E32CD, (q31_t)0x971F9ED6,
- (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB7434A67,
- (q31_t)0x96ACDBBD, (q31_t)0xB796199B, (q31_t)0x9673DB94,
- (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB83C3DD1,
- (q31_t)0x96029EB5, (q31_t)0xB88F926C, (q31_t)0x95CA6246,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB936BFA3,
- (q31_t)0x955AAE17, (q31_t)0xB98A97D8, (q31_t)0x9523369B,
- (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA32CA70,
- (q31_t)0x94B50D87, (q31_t)0xBA87246C, (q31_t)0x947E5C32,
- (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB3058C0,
- (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F,
- (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513,
- (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968,
- (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1,
- (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805,
- (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B,
- (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4,
- (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8,
- (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663,
- (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368,
- (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3,
- (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233,
- (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A,
- (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A,
- (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E,
- (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25,
- (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A,
- (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7,
- (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298,
- (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8,
- (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7,
- (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD,
- (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399,
- (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571,
- (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30,
- (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA,
- (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4,
- (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05,
- (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9,
- (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4,
- (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578,
- (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA,
- (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D,
- (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35,
- (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC,
- (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5,
- (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2,
- (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89,
- (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459,
- (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677,
- (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1,
- (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431,
- (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38,
- (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820,
- (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445,
- (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B,
- (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8,
- (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC,
- (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE,
- (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E,
- (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D,
- (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE,
- (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7,
- (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA,
- (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439,
- (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152,
- (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A,
- (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD,
- (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C,
- (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781,
- (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3,
- (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220,
- (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62,
- (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60,
- (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE,
- (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2,
- (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF,
- (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684,
- (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D,
- (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1,
- (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422,
- (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C,
- (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97,
- (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB,
- (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8,
- (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA,
- (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381,
- (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616,
- (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0,
- (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917,
- (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2,
- (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273,
- (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758,
- (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB,
- (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320,
- (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80,
- (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C,
- (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F,
- (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2,
- (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6,
- (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31,
- (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA,
- (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752,
- (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C,
- (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A,
- (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1,
- (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89,
- (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF,
- (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1,
- (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B,
- (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260,
- (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D,
- (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743,
- (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA,
- (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5,
- (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D,
- (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461,
- (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC,
- (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90,
- (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872,
- (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB,
- (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7,
- (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89,
- (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88,
- (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541,
- (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E,
- (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69,
- (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5,
- (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078,
- (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A
-};
-
-/**
-* \par
-* Example code for Q31 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 4096 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to Q31(Fixed point 1.31):
-* round(twiddleCoefQ31(i) * pow(2, 31))
-*
-*/
-const q31_t twiddleCoef_4096_q31[6144] =
-{
- (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621,
- (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3,
- (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216,
- (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F,
- (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64,
- (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F,
- (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F,
- (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1,
- (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17,
- (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4,
- (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182,
- (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96,
- (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553,
- (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6,
- (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790,
- (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3,
- (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840,
- (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C,
- (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B,
- (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF,
- (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518,
- (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C,
- (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152,
- (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261,
- (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23,
- (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE,
- (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596,
- (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1,
- (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7,
- (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A,
- (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494,
- (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77,
- (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C,
- (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89,
- (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC,
- (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE,
- (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226,
- (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805,
- (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B,
- (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE,
- (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD,
- (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389,
- (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F,
- (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865,
- (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654,
- (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92,
- (q31_t)0x7F489EAA, (q31_t)0x0D85D88F, (q31_t)0x7F434563,
- (q31_t)0x0DB7D376, (q31_t)0x7F3DD87C, (q31_t)0x0DE9CC3F,
- (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F32C3D0,
- (q31_t)0x0E4DB75B, (q31_t)0x7F2D1C0E, (q31_t)0x0E7FA99D,
- (q31_t)0x7F2760AF, (q31_t)0x0EB199A3, (q31_t)0x7F2191B4,
- (q31_t)0x0EE38765, (q31_t)0x7F1BAF1E, (q31_t)0x0F1572DC,
- (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0FAF24,
- (q31_t)0x0F7942C6, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B,
- (q31_t)0x7F0360CB, (q31_t)0x0FDD0925, (q31_t)0x7EFD1C3C,
- (q31_t)0x100EE8AD, (q31_t)0x7EF6C418, (q31_t)0x1040C5BB,
- (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE9D913,
- (q31_t)0x10A4784A, (q31_t)0x7EE34635, (q31_t)0x10D64DBC,
- (q31_t)0x7EDC9FC6, (q31_t)0x11082096, (q31_t)0x7ED5E5C6,
- (q31_t)0x1139F0CE, (q31_t)0x7ECF1837, (q31_t)0x116BBE5F,
- (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EC1426F,
- (q31_t)0x11CF516A, (q31_t)0x7EBA3A39, (q31_t)0x120116D4,
- (q31_t)0x7EB31E77, (q31_t)0x1232D978, (q31_t)0x7EABEF2C,
- (q31_t)0x1264994E, (q31_t)0x7EA4AC58, (q31_t)0x1296564D,
- (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E95EC19,
- (q31_t)0x12F9C7AA, (q31_t)0x7E8E6EB1, (q31_t)0x132B7BF9,
- (q31_t)0x7E86DDC5, (q31_t)0x135D2D53, (q31_t)0x7E7F3956,
- (q31_t)0x138EDBB0, (q31_t)0x7E778165, (q31_t)0x13C0870A,
- (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E67D702,
- (q31_t)0x1423D492, (q31_t)0x7E5FE493, (q31_t)0x145576B1,
- (q31_t)0x7E57DEA6, (q31_t)0x148715AD, (q31_t)0x7E4FC53E,
- (q31_t)0x14B8B17F, (q31_t)0x7E47985B, (q31_t)0x14EA4A1F,
- (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E37042A,
- (q31_t)0x154D71AA, (q31_t)0x7E2E9CDF, (q31_t)0x157F0086,
- (q31_t)0x7E26221E, (q31_t)0x15B08C11, (q31_t)0x7E1D93E9,
- (q31_t)0x15E21444, (q31_t)0x7E14F242, (q31_t)0x16139917,
- (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7E03749F,
- (q31_t)0x1676987F, (q31_t)0x7DFA98A7, (q31_t)0x16A81305,
- (q31_t)0x7DF1A942, (q31_t)0x16D98A0C, (q31_t)0x7DE8A670,
- (q31_t)0x170AFD8D, (q31_t)0x7DDF9034, (q31_t)0x173C6D80,
- (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DCD2981,
- (q31_t)0x179F429F, (q31_t)0x7DC3D90D, (q31_t)0x17D0A7BB,
- (q31_t)0x7DBA7534, (q31_t)0x1802092C, (q31_t)0x7DB0FDF7,
- (q31_t)0x183366E8, (q31_t)0x7DA77359, (q31_t)0x1864C0E9,
- (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D9423FB,
- (q31_t)0x18C7699B, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C,
- (q31_t)0x7D808727, (q31_t)0x192A0303, (q31_t)0x7D769BB5,
- (q31_t)0x195B49E9, (q31_t)0x7D6C9CE9, (q31_t)0x198C8CE6,
- (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D58654C,
- (q31_t)0x19EF0706, (q31_t)0x7D4E2C7E, (q31_t)0x1A203E1B,
- (q31_t)0x7D43E05E, (q31_t)0x1A517127, (q31_t)0x7D3980EC,
- (q31_t)0x1A82A025, (q31_t)0x7D2F0E2A, (q31_t)0x1AB3CB0C,
- (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D19EEBE,
- (q31_t)0x1B161479, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF,
- (q31_t)0x7D048228, (q31_t)0x1B784D30, (q31_t)0x7CF9AEF0,
- (q31_t)0x1BA96334, (q31_t)0x7CEEC873, (q31_t)0x1BDA74F5,
- (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CD8C1AD,
- (q31_t)0x1C3C8B8C, (q31_t)0x7CCDA168, (q31_t)0x1C6D9053,
- (q31_t)0x7CC26DE5, (q31_t)0x1C9E90B8, (q31_t)0x7CB72724,
- (q31_t)0x1CCF8CB3, (q31_t)0x7CABCD27, (q31_t)0x1D00843C,
- (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C94DF82,
- (q31_t)0x1D6265DD, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5,
- (q31_t)0x7C7DA504, (q31_t)0x1DC4355D, (q31_t)0x7C71EAF8,
- (q31_t)0x1DF5163F, (q31_t)0x7C661DBB, (q31_t)0x1E25F281,
- (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4E49B6,
- (q31_t)0x1E879D0C, (q31_t)0x7C4242F2, (q31_t)0x1EB86B46,
- (q31_t)0x7C362904, (q31_t)0x1EE934C2, (q31_t)0x7C29FBEE,
- (q31_t)0x1F19F97B, (q31_t)0x7C1DBBB2, (q31_t)0x1F4AB967,
- (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7C0501D1,
- (q31_t)0x1FAC2ABF, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A,
- (q31_t)0x7BEBFB70, (q31_t)0x200D888C, (q31_t)0x7BDF5B94,
- (q31_t)0x203E300D, (q31_t)0x7BD2A89E, (q31_t)0x206ED295,
- (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BB9096A,
- (q31_t)0x20D0089B, (q31_t)0x7BAC1D31, (q31_t)0x21009C0B,
- (q31_t)0x7B9F1DE5, (q31_t)0x21312A65, (q31_t)0x7B920B89,
- (q31_t)0x2161B39F, (q31_t)0x7B84E61E, (q31_t)0x219237B4,
- (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B6A6227,
- (q31_t)0x21F3304E, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5,
- (q31_t)0x7B4F920E, (q31_t)0x225413F8, (q31_t)0x7B420D7A,
- (q31_t)0x22847DDF, (q31_t)0x7B3475E4, (q31_t)0x22B4E274,
- (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B190DBB,
- (q31_t)0x23159B87, (q31_t)0x7B0B3D2C, (q31_t)0x2345EFF7,
- (q31_t)0x7AFD59A3, (q31_t)0x23763EF7, (q31_t)0x7AEF6323,
- (q31_t)0x23A6887E, (q31_t)0x7AE159AE, (q31_t)0x23D6CC86,
- (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AC50DEB,
- (q31_t)0x243743FA, (q31_t)0x7AB6CBA3, (q31_t)0x24677757,
- (q31_t)0x7AA8766E, (q31_t)0x2497A517, (q31_t)0x7A9A0E4F,
- (q31_t)0x24C7CD32, (q31_t)0x7A8B9348, (q31_t)0x24F7EFA1,
- (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A6E648A,
- (q31_t)0x2558235E, (q31_t)0x7A5FB0D8, (q31_t)0x2588349D,
- (q31_t)0x7A50EA46, (q31_t)0x25B84012, (q31_t)0x7A4210D8,
- (q31_t)0x25E845B5, (q31_t)0x7A33248F, (q31_t)0x26184581,
- (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A151377,
- (q31_t)0x26783370, (q31_t)0x7A05EEAD, (q31_t)0x26A82185,
- (q31_t)0x79F6B711, (q31_t)0x26D809A5, (q31_t)0x79E76CA6,
- (q31_t)0x2707EBC6, (q31_t)0x79D80F6F, (q31_t)0x2737C7E3,
- (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79B91CA4,
- (q31_t)0x27976DF1, (q31_t)0x79A98715, (q31_t)0x27C737D2,
- (q31_t)0x7999DEC3, (q31_t)0x27F6FB92, (q31_t)0x798A23B1,
- (q31_t)0x2826B928, (q31_t)0x797A55E0, (q31_t)0x2856708C,
- (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x795A820E,
- (q31_t)0x28B5CCA5, (q31_t)0x794A7C11, (q31_t)0x28E5714A,
- (q31_t)0x793A6360, (q31_t)0x29150FA1, (q31_t)0x792A37FE,
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- (q31_t)0x003243F5, (q31_t)0x7FFFF621, (q31_t)0x00000000,
- (q31_t)0x7FFFFFFF, (q31_t)0xFFCDBC0A, (q31_t)0x7FFFF621,
- (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF69343E,
- (q31_t)0x7FFFA72C, (q31_t)0xFF36F078, (q31_t)0x7FFF6216,
- (q31_t)0xFF04ACD0, (q31_t)0x7FFF0942, (q31_t)0xFED2694F,
- (q31_t)0x7FFE9CB2, (q31_t)0xFEA025FC, (q31_t)0x7FFE1C64,
- (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE3BA001,
- (q31_t)0x7FFCE093, (q31_t)0xFE095D69, (q31_t)0x7FFC250F,
- (q31_t)0xFDD71B1E, (q31_t)0x7FFB55CE, (q31_t)0xFDA4D928,
- (q31_t)0x7FFA72D1, (q31_t)0xFD72978F, (q31_t)0x7FF97C17,
- (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFD0E1594,
- (q31_t)0x7FF7536F, (q31_t)0xFCDBD541, (q31_t)0x7FF62182,
- (q31_t)0xFCA99569, (q31_t)0x7FF4DBD8, (q31_t)0xFC775616,
- (q31_t)0x7FF38273, (q31_t)0xFC45174E, (q31_t)0x7FF21553,
- (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBE09B80,
- (q31_t)0x7FEEFFE1, (q31_t)0xFBAE5E89, (q31_t)0x7FED5790,
- (q31_t)0xFB7C223C, (q31_t)0x7FEB9B85, (q31_t)0xFB49E6A2,
- (q31_t)0x7FE9CBC0, (q31_t)0xFB17ABC2, (q31_t)0x7FE7E840,
- (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFAB3384F,
- (q31_t)0x7FE3E616, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B,
- (q31_t)0xFA4EC820, (q31_t)0x7FDF9508, (q31_t)0xFA1C9156,
- (q31_t)0x7FDD4EEC, (q31_t)0xF9EA5B75, (q31_t)0x7FDAF518,
- (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF985F28A,
- (q31_t)0x7FD6064B, (q31_t)0xF953BF90, (q31_t)0x7FD37152,
- (q31_t)0xF9218D9E, (q31_t)0x7FD0C8A3, (q31_t)0xF8EF5CBB,
- (q31_t)0x7FCE0C3E, (q31_t)0xF8BD2CEF, (q31_t)0x7FCB3C23,
- (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF858D0BA,
- (q31_t)0x7FC560CF, (q31_t)0xF826A461, (q31_t)0x7FC25596,
- (q31_t)0xF7F4793E, (q31_t)0x7FBF36A9, (q31_t)0xF7C24F58,
- (q31_t)0x7FBC040A, (q31_t)0xF79026B8, (q31_t)0x7FB8BDB7,
- (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF72BD967,
- (q31_t)0x7FB1F5FC, (q31_t)0xF6F9B4C5, (q31_t)0x7FAE7494,
- (q31_t)0xF6C79188, (q31_t)0x7FAADF7C, (q31_t)0xF6956FB6,
- (q31_t)0x7FA736B4, (q31_t)0xF6634F58, (q31_t)0x7FA37A3C,
- (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5FF1317,
- (q31_t)0x7F9BC63F, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC,
- (q31_t)0xF59ADD01, (q31_t)0x7F93C38C, (q31_t)0xF568C45A,
- (q31_t)0x7F8FA4AF, (q31_t)0xF536AD55, (q31_t)0x7F8B7226,
- (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4D28451,
- (q31_t)0x7F82D214, (q31_t)0xF4A07260, (q31_t)0x7F7E648B,
- (q31_t)0xF46E6231, (q31_t)0x7F79E35A, (q31_t)0xF43C53CA,
- (q31_t)0x7F754E7F, (q31_t)0xF40A4734, (q31_t)0x7F70A5FD,
- (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3A63398,
- (q31_t)0x7F671A04, (q31_t)0xF3742CA1, (q31_t)0x7F62368F,
- (q31_t)0xF342279A, (q31_t)0x7F5D3F75, (q31_t)0xF310248A,
- (q31_t)0x7F5834B6, (q31_t)0xF2DE2378, (q31_t)0x7F531654,
- (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF27A2770,
- (q31_t)0x7F489EAA, (q31_t)0xF2482C89, (q31_t)0x7F434563,
- (q31_t)0xF21633C0, (q31_t)0x7F3DD87C, (q31_t)0xF1E43D1C,
- (q31_t)0x7F3857F5, (q31_t)0xF1B248A5, (q31_t)0x7F32C3D0,
- (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF14E665C,
- (q31_t)0x7F2760AF, (q31_t)0xF11C789A, (q31_t)0x7F2191B4,
- (q31_t)0xF0EA8D23, (q31_t)0x7F1BAF1E, (q31_t)0xF0B8A401,
- (q31_t)0x7F15B8EE, (q31_t)0xF086BD39, (q31_t)0x7F0FAF24,
- (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xF022F6DA,
- (q31_t)0x7F0360CB, (q31_t)0xEFF11752, (q31_t)0x7EFD1C3C,
- (q31_t)0xEFBF3A44, (q31_t)0x7EF6C418, (q31_t)0xEF8D5FB8,
- (q31_t)0x7EF0585F, (q31_t)0xEF5B87B5, (q31_t)0x7EE9D913,
- (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEF7DF6A,
- (q31_t)0x7EDC9FC6, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6,
- (q31_t)0xEE9441A0, (q31_t)0x7ECF1837, (q31_t)0xEE6276BF,
- (q31_t)0x7EC8371A, (q31_t)0xEE30AE95, (q31_t)0x7EC1426F,
- (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xEDCD2687,
- (q31_t)0x7EB31E77, (q31_t)0xED9B66B2, (q31_t)0x7EABEF2C,
- (q31_t)0xED69A9B2, (q31_t)0x7EA4AC58, (q31_t)0xED37EF91,
- (q31_t)0x7E9D55FC, (q31_t)0xED063855, (q31_t)0x7E95EC19,
- (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xECA2D2AC,
- (q31_t)0x7E86DDC5, (q31_t)0xEC71244F, (q31_t)0x7E7F3956,
- (q31_t)0xEC3F78F5, (q31_t)0x7E778165, (q31_t)0xEC0DD0A8,
- (q31_t)0x7E6FB5F3, (q31_t)0xEBDC2B6D, (q31_t)0x7E67D702,
- (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB78EA52,
- (q31_t)0x7E57DEA6, (q31_t)0xEB474E80, (q31_t)0x7E4FC53E,
- (q31_t)0xEB15B5E0, (q31_t)0x7E47985B, (q31_t)0xEAE4207A,
- (q31_t)0x7E3F57FE, (q31_t)0xEAB28E55, (q31_t)0x7E37042A,
- (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA4F73EE,
- (q31_t)0x7E26221E, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9,
- (q31_t)0xE9EC66E8, (q31_t)0x7E14F242, (q31_t)0xE9BAE57C,
- (q31_t)0x7E0C3D29, (q31_t)0xE9896780, (q31_t)0x7E03749F,
- (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE92675F4,
- (q31_t)0x7DF1A942, (q31_t)0xE8F50273, (q31_t)0x7DE8A670,
- (q31_t)0xE8C3927F, (q31_t)0x7DDF9034, (q31_t)0xE8922621,
- (q31_t)0x7DD6668E, (q31_t)0xE860BD60, (q31_t)0x7DCD2981,
- (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7FDF6D3,
- (q31_t)0x7DBA7534, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7,
- (q31_t)0xE79B3F16, (q31_t)0x7DA77359, (q31_t)0xE769E8D8,
- (q31_t)0x7D9DD55A, (q31_t)0xE7389664, (q31_t)0x7D9423FB,
- (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6D5FCFC,
- (q31_t)0x7D808727, (q31_t)0xE6A4B616, (q31_t)0x7D769BB5,
- (q31_t)0xE6737319, (q31_t)0x7D6C9CE9, (q31_t)0xE642340D,
- (q31_t)0x7D628AC5, (q31_t)0xE610F8F9, (q31_t)0x7D58654C,
- (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE5AE8ED8,
- (q31_t)0x7D43E05E, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC,
- (q31_t)0xE54C34F3, (q31_t)0x7D2F0E2A, (q31_t)0xE51B0E2A,
- (q31_t)0x7D24881A, (q31_t)0xE4E9EB86, (q31_t)0x7D19EEBE,
- (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE487B2CF,
- (q31_t)0x7D048228, (q31_t)0xE4569CCB, (q31_t)0x7CF9AEF0,
- (q31_t)0xE4258B0A, (q31_t)0x7CEEC873, (q31_t)0xE3F47D95,
- (q31_t)0x7CE3CEB1, (q31_t)0xE3C37473, (q31_t)0x7CD8C1AD,
- (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE3616F47,
- (q31_t)0x7CC26DE5, (q31_t)0xE330734C, (q31_t)0x7CB72724,
- (q31_t)0xE2FF7BC3, (q31_t)0x7CABCD27, (q31_t)0xE2CE88B2,
- (q31_t)0x7CA05FF1, (q31_t)0xE29D9A22, (q31_t)0x7C94DF82,
- (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE23BCAA2,
- (q31_t)0x7C7DA504, (q31_t)0xE20AE9C1, (q31_t)0x7C71EAF8,
- (q31_t)0xE1DA0D7E, (q31_t)0x7C661DBB, (q31_t)0xE1A935E1,
- (q31_t)0x7C5A3D4F, (q31_t)0xE17862F3, (q31_t)0x7C4E49B6,
- (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE116CB3D,
- (q31_t)0x7C362904, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE,
- (q31_t)0xE0B54698, (q31_t)0x7C1DBBB2, (q31_t)0xE0848B7F,
- (q31_t)0x7C116853, (q31_t)0xE053D541, (q31_t)0x7C0501D1,
- (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFF27773,
- (q31_t)0x7BEBFB70, (q31_t)0xDFC1CFF2, (q31_t)0x7BDF5B94,
- (q31_t)0xDF912D6A, (q31_t)0x7BD2A89E, (q31_t)0xDF608FE3,
- (q31_t)0x7BC5E28F, (q31_t)0xDF2FF764, (q31_t)0x7BB9096A,
- (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDECED59B,
- (q31_t)0x7B9F1DE5, (q31_t)0xDE9E4C60, (q31_t)0x7B920B89,
- (q31_t)0xDE6DC84B, (q31_t)0x7B84E61E, (q31_t)0xDE3D4963,
- (q31_t)0x7B77ADA8, (q31_t)0xDE0CCFB1, (q31_t)0x7B6A6227,
- (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDDABEC07,
- (q31_t)0x7B4F920E, (q31_t)0xDD7B8220, (q31_t)0x7B420D7A,
- (q31_t)0xDD4B1D8B, (q31_t)0x7B3475E4, (q31_t)0xDD1ABE51,
- (q31_t)0x7B26CB4F, (q31_t)0xDCEA6478, (q31_t)0x7B190DBB,
- (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC89C108,
- (q31_t)0x7AFD59A3, (q31_t)0xDC597781, (q31_t)0x7AEF6323,
- (q31_t)0xDC293379, (q31_t)0x7AE159AE, (q31_t)0xDBF8F4F8,
- (q31_t)0x7AD33D45, (q31_t)0xDBC8BC05, (q31_t)0x7AC50DEB,
- (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB685AE8,
- (q31_t)0x7AA8766E, (q31_t)0xDB3832CD, (q31_t)0x7A9A0E4F,
- (q31_t)0xDB08105E, (q31_t)0x7A8B9348, (q31_t)0xDAD7F3A2,
- (q31_t)0x7A7D055B, (q31_t)0xDAA7DCA1, (q31_t)0x7A6E648A,
- (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA47BFED,
- (q31_t)0x7A50EA46, (q31_t)0xDA17BA4A, (q31_t)0x7A4210D8,
- (q31_t)0xD9E7BA7E, (q31_t)0x7A33248F, (q31_t)0xD9B7C093,
- (q31_t)0x7A24256E, (q31_t)0xD987CC8F, (q31_t)0x7A151377,
- (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD927F65B,
- (q31_t)0x79F6B711, (q31_t)0xD8F81439, (q31_t)0x79E76CA6,
- (q31_t)0xD8C8381C, (q31_t)0x79D80F6F, (q31_t)0xD898620C,
- (q31_t)0x79C89F6D, (q31_t)0xD868920F, (q31_t)0x79B91CA4,
- (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD809046D,
- (q31_t)0x7999DEC3, (q31_t)0xD7D946D7, (q31_t)0x798A23B1,
- (q31_t)0xD7A98F73, (q31_t)0x797A55E0, (q31_t)0xD779DE46,
- (q31_t)0x796A7554, (q31_t)0xD74A335A, (q31_t)0x795A820E,
- (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6EAF05E,
- (q31_t)0x793A6360, (q31_t)0xD6BB585D, (q31_t)0x792A37FE,
- (q31_t)0xD68BC6BA, (q31_t)0x7919F9EB, (q31_t)0xD65C3B7B,
- (q31_t)0x7909A92C, (q31_t)0xD62CB6A7, (q31_t)0x78F945C3,
- (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD5CDC062,
- (q31_t)0x78D846FB, (q31_t)0xD59E4EFE, (q31_t)0x78C7ABA1,
- (q31_t)0xD56EE424, (q31_t)0x78B6FDA8, (q31_t)0xD53F7FDA,
- (q31_t)0x78A63D10, (q31_t)0xD5102227, (q31_t)0x789569DE,
- (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD4B17AA7,
- (q31_t)0x78738BB3, (q31_t)0xD48230E8, (q31_t)0x786280BF,
- (q31_t)0xD452EDDE, (q31_t)0x7851633B, (q31_t)0xD423B190,
- (q31_t)0x78403328, (q31_t)0xD3F47C06, (q31_t)0x782EF08B,
- (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3962559,
- (q31_t)0x780C33B8, (q31_t)0xD3670445, (q31_t)0x77FAB988,
- (q31_t)0xD337EA12, (q31_t)0x77E92CD8, (q31_t)0xD308D6C6,
- (q31_t)0x77D78DAA, (q31_t)0xD2D9CA6A, (q31_t)0x77C5DC01,
- (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD27BC69C,
- (q31_t)0x77A24148, (q31_t)0xD24CCF38, (q31_t)0x7790583D,
- (q31_t)0xD21DDEE1, (q31_t)0x777E5CC3, (q31_t)0xD1EEF59E,
- (q31_t)0x776C4EDB, (q31_t)0xD1C01374, (q31_t)0x775A2E88,
- (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD162648F,
- (q31_t)0x7735B6AE, (q31_t)0xD13397E1, (q31_t)0x77235F2D,
- (q31_t)0xD104D26B, (q31_t)0x7710F54B, (q31_t)0xD0D61433,
- (q31_t)0x76FE790E, (q31_t)0xD0A75D42, (q31_t)0x76EBEA77,
- (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD04A054D,
- (q31_t)0x76C69646, (q31_t)0xD01B6459, (q31_t)0x76B3D0B3,
- (q31_t)0xCFECCAC7, (q31_t)0x76A0F8D2, (q31_t)0xCFBE389F,
- (q31_t)0x768E0EA5, (q31_t)0xCF8FADE8, (q31_t)0x767B1230,
- (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF32AEEB,
- (q31_t)0x7654E279, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C,
- (q31_t)0xCED5CE08, (q31_t)0x762E69C3, (q31_t)0xCEA768F2,
- (q31_t)0x761B1211, (q31_t)0xCE790B78, (q31_t)0x7607A827,
- (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCE1C6776,
- (q31_t)0x75E09DBD, (q31_t)0xCDEE20FC, (q31_t)0x75CCFD42,
- (q31_t)0xCDBFE23A, (q31_t)0x75B94A9C, (q31_t)0xCD91AB38,
- (q31_t)0x75A585CF, (q31_t)0xCD637BFD, (q31_t)0x7591AEDD,
- (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCD0734F8,
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- (q31_t)0xCCAB0D65, (q31_t)0x75419DE6, (q31_t)0xCC7D0577,
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- (q31_t)0x8685AA1F, (q31_t)0x2856708C, (q31_t)0x8675DC4E,
- (q31_t)0x2826B928, (q31_t)0x8666213C, (q31_t)0x27F6FB92,
- (q31_t)0x865678EA, (q31_t)0x27C737D2, (q31_t)0x8646E35B,
- (q31_t)0x27976DF1, (q31_t)0x86376092, (q31_t)0x27679DF4,
- (q31_t)0x8627F090, (q31_t)0x2737C7E3, (q31_t)0x86189359,
- (q31_t)0x2707EBC6, (q31_t)0x860948EE, (q31_t)0x26D809A5,
- (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85EAEC88,
- (q31_t)0x26783370, (q31_t)0x85DBDA91, (q31_t)0x26483F6C,
- (q31_t)0x85CCDB70, (q31_t)0x26184581, (q31_t)0x85BDEF27,
- (q31_t)0x25E845B5, (q31_t)0x85AF15B9, (q31_t)0x25B84012,
- (q31_t)0x85A04F28, (q31_t)0x2588349D, (q31_t)0x85919B75,
- (q31_t)0x2558235E, (q31_t)0x8582FAA4, (q31_t)0x25280C5D,
- (q31_t)0x85746CB7, (q31_t)0x24F7EFA1, (q31_t)0x8565F1B0,
- (q31_t)0x24C7CD32, (q31_t)0x85578991, (q31_t)0x2497A517,
- (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x853AF214,
- (q31_t)0x243743FA, (q31_t)0x852CC2BA, (q31_t)0x24070B07,
- (q31_t)0x851EA652, (q31_t)0x23D6CC86, (q31_t)0x85109CDC,
- (q31_t)0x23A6887E, (q31_t)0x8502A65C, (q31_t)0x23763EF7,
- (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84E6F244,
- (q31_t)0x23159B87, (q31_t)0x84D934B0, (q31_t)0x22E541AE,
- (q31_t)0x84CB8A1B, (q31_t)0x22B4E274, (q31_t)0x84BDF285,
- (q31_t)0x22847DDF, (q31_t)0x84B06DF1, (q31_t)0x225413F8,
- (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84959DD9,
- (q31_t)0x21F3304E, (q31_t)0x84885257, (q31_t)0x21C2B69C,
- (q31_t)0x847B19E1, (q31_t)0x219237B4, (q31_t)0x846DF476,
- (q31_t)0x2161B39F, (q31_t)0x8460E21A, (q31_t)0x21312A65,
- (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x8446F695,
- (q31_t)0x20D0089B, (q31_t)0x843A1D70, (q31_t)0x209F701C,
- (q31_t)0x842D5761, (q31_t)0x206ED295, (q31_t)0x8420A46B,
- (q31_t)0x203E300D, (q31_t)0x8414048F, (q31_t)0x200D888C,
- (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83FAFE2E,
- (q31_t)0x1FAC2ABF, (q31_t)0x83EE97AC, (q31_t)0x1F7B7480,
- (q31_t)0x83E2444D, (q31_t)0x1F4AB967, (q31_t)0x83D60411,
- (q31_t)0x1F19F97B, (q31_t)0x83C9D6FB, (q31_t)0x1EE934C2,
- (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83B1B649,
- (q31_t)0x1E879D0C, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E,
- (q31_t)0x8399E244, (q31_t)0x1E25F281, (q31_t)0x838E1507,
- (q31_t)0x1DF5163F, (q31_t)0x83825AFB, (q31_t)0x1DC4355D,
- (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x836B207D,
- (q31_t)0x1D6265DD, (q31_t)0x835FA00E, (q31_t)0x1D31774D,
- (q31_t)0x835432D8, (q31_t)0x1D00843C, (q31_t)0x8348D8DB,
- (q31_t)0x1CCF8CB3, (q31_t)0x833D921A, (q31_t)0x1C9E90B8,
- (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x83273E52,
- (q31_t)0x1C3C8B8C, (q31_t)0x831C314E, (q31_t)0x1C0B826A,
- (q31_t)0x8311378C, (q31_t)0x1BDA74F5, (q31_t)0x8306510F,
- (q31_t)0x1BA96334, (q31_t)0x82FB7DD8, (q31_t)0x1B784D30,
- (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82E61141,
- (q31_t)0x1B161479, (q31_t)0x82DB77E5, (q31_t)0x1AE4F1D6,
- (q31_t)0x82D0F1D5, (q31_t)0x1AB3CB0C, (q31_t)0x82C67F13,
- (q31_t)0x1A82A025, (q31_t)0x82BC1FA1, (q31_t)0x1A517127,
- (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x82A79AB3,
- (q31_t)0x19EF0706, (q31_t)0x829D753A, (q31_t)0x19BDCBF2,
- (q31_t)0x82936316, (q31_t)0x198C8CE6, (q31_t)0x8289644A,
- (q31_t)0x195B49E9, (q31_t)0x827F78D8, (q31_t)0x192A0303,
- (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x826BDC04,
- (q31_t)0x18C7699B, (q31_t)0x82622AA5, (q31_t)0x18961727,
- (q31_t)0x82588CA6, (q31_t)0x1864C0E9, (q31_t)0x824F0208,
- (q31_t)0x183366E8, (q31_t)0x82458ACB, (q31_t)0x1802092C,
- (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x8232D67E,
- (q31_t)0x179F429F, (q31_t)0x82299971, (q31_t)0x176DD9DE,
- (q31_t)0x82206FCB, (q31_t)0x173C6D80, (q31_t)0x8217598F,
- (q31_t)0x170AFD8D, (q31_t)0x820E56BE, (q31_t)0x16D98A0C,
- (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81FC8B60,
- (q31_t)0x1676987F, (q31_t)0x81F3C2D7, (q31_t)0x16451A83,
- (q31_t)0x81EB0DBD, (q31_t)0x16139917, (q31_t)0x81E26C16,
- (q31_t)0x15E21444, (q31_t)0x81D9DDE1, (q31_t)0x15B08C11,
- (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C8FBD5,
- (q31_t)0x154D71AA, (q31_t)0x81C0A801, (q31_t)0x151BDF85,
- (q31_t)0x81B867A4, (q31_t)0x14EA4A1F, (q31_t)0x81B03AC1,
- (q31_t)0x14B8B17F, (q31_t)0x81A82159, (q31_t)0x148715AD,
- (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x819828FD,
- (q31_t)0x1423D492, (q31_t)0x81904A0C, (q31_t)0x13F22F57,
- (q31_t)0x81887E9A, (q31_t)0x13C0870A, (q31_t)0x8180C6A9,
- (q31_t)0x138EDBB0, (q31_t)0x8179223A, (q31_t)0x135D2D53,
- (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x816A13E6,
- (q31_t)0x12F9C7AA, (q31_t)0x8162AA03, (q31_t)0x12C8106E,
- (q31_t)0x815B53A8, (q31_t)0x1296564D, (q31_t)0x815410D3,
- (q31_t)0x1264994E, (q31_t)0x814CE188, (q31_t)0x1232D978,
- (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x813EBD90,
- (q31_t)0x11CF516A, (q31_t)0x8137C8E6, (q31_t)0x119D8940,
- (q31_t)0x8130E7C8, (q31_t)0x116BBE5F, (q31_t)0x812A1A39,
- (q31_t)0x1139F0CE, (q31_t)0x81236039, (q31_t)0x11082096,
- (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x811626EC,
- (q31_t)0x10A4784A, (q31_t)0x810FA7A0, (q31_t)0x1072A047,
- (q31_t)0x81093BE8, (q31_t)0x1040C5BB, (q31_t)0x8102E3C3,
- (q31_t)0x100EE8AD, (q31_t)0x80FC9F35, (q31_t)0x0FDD0925,
- (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80F050DB,
- (q31_t)0x0F7942C6, (q31_t)0x80EA4712, (q31_t)0x0F475BFE,
- (q31_t)0x80E450E2, (q31_t)0x0F1572DC, (q31_t)0x80DE6E4C,
- (q31_t)0x0EE38765, (q31_t)0x80D89F51, (q31_t)0x0EB199A3,
- (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80CD3C2F,
- (q31_t)0x0E4DB75B, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3,
- (q31_t)0x80C22783, (q31_t)0x0DE9CC3F, (q31_t)0x80BCBA9C,
- (q31_t)0x0DB7D376, (q31_t)0x80B76155, (q31_t)0x0D85D88F,
- (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80ACE9AB,
- (q31_t)0x0D21DC87, (q31_t)0x80A7CB49, (q31_t)0x0CEFDB75,
- (q31_t)0x80A2C08B, (q31_t)0x0CBDD865, (q31_t)0x809DC970,
- (q31_t)0x0C8BD35E, (q31_t)0x8098E5FB, (q31_t)0x0C59CC67,
- (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808F5A02,
- (q31_t)0x0BF5B8CB, (q31_t)0x808AB180, (q31_t)0x0BC3AC35,
- (q31_t)0x80861CA5, (q31_t)0x0B919DCE, (q31_t)0x80819B74,
- (q31_t)0x0B5F8D9F, (q31_t)0x807D2DEB, (q31_t)0x0B2D7BAE,
- (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80748DD9,
- (q31_t)0x0AC952AA, (q31_t)0x80705B50, (q31_t)0x0A973BA5,
- (q31_t)0x806C3C73, (q31_t)0x0A6522FE, (q31_t)0x80683143,
- (q31_t)0x0A3308BC, (q31_t)0x806439C0, (q31_t)0x0A00ECE8,
- (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x805C85C3,
- (q31_t)0x099CB0A7, (q31_t)0x8058C94C, (q31_t)0x096A9049,
- (q31_t)0x80552083, (q31_t)0x09386E77, (q31_t)0x80518B6B,
- (q31_t)0x09064B3A, (q31_t)0x804E0A03, (q31_t)0x08D42698,
- (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x80474248,
- (q31_t)0x086FD947, (q31_t)0x8043FBF6, (q31_t)0x083DB0A7,
- (q31_t)0x8040C956, (q31_t)0x080B86C1, (q31_t)0x803DAA69,
- (q31_t)0x07D95B9E, (q31_t)0x803A9F31, (q31_t)0x07A72F45,
- (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8034C3DC,
- (q31_t)0x0742D310, (q31_t)0x8031F3C1, (q31_t)0x0710A344,
- (q31_t)0x802F375C, (q31_t)0x06DE7261, (q31_t)0x802C8EAD,
- (q31_t)0x06AC406F, (q31_t)0x8029F9B4, (q31_t)0x067A0D75,
- (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80250AE7,
- (q31_t)0x0615A48A, (q31_t)0x8022B113, (q31_t)0x05E36EA9,
- (q31_t)0x80206AF8, (q31_t)0x05B137DF, (q31_t)0x801E3894,
- (q31_t)0x057F0034, (q31_t)0x801C19E9, (q31_t)0x054CC7B0,
- (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x801817BF,
- (q31_t)0x04E8543D, (q31_t)0x80163440, (q31_t)0x04B6195D,
- (q31_t)0x8014647A, (q31_t)0x0483DDC3, (q31_t)0x8012A86F,
- (q31_t)0x0451A176, (q31_t)0x8011001E, (q31_t)0x041F647F,
- (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800DEAAC,
- (q31_t)0x03BAE8B1, (q31_t)0x800C7D8C, (q31_t)0x0388A9E9,
- (q31_t)0x800B2427, (q31_t)0x03566A96, (q31_t)0x8009DE7D,
- (q31_t)0x03242ABF, (q31_t)0x8008AC90, (q31_t)0x02F1EA6B,
- (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x800683E8,
- (q31_t)0x028D6870, (q31_t)0x80058D2E, (q31_t)0x025B26D7,
- (q31_t)0x8004AA31, (q31_t)0x0228E4E1, (q31_t)0x8003DAF0,
- (q31_t)0x01F6A296, (q31_t)0x80031F6C, (q31_t)0x01C45FFE,
- (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001E39B,
- (q31_t)0x015FDA03, (q31_t)0x8001634D, (q31_t)0x012D96B0,
- (q31_t)0x8000F6BD, (q31_t)0x00FB532F, (q31_t)0x80009DE9,
- (q31_t)0x00C90F88, (q31_t)0x800058D3, (q31_t)0x0096CBC1,
- (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x800009DE,
- (q31_t)0x003243F5, (q31_t)0x80000000, (q31_t)0x00000000,
- (q31_t)0x800009DE, (q31_t)0xFFCDBC0A, (q31_t)0x8000277A,
- (q31_t)0xFF9B781D, (q31_t)0x800058D3, (q31_t)0xFF69343E,
- (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8000F6BD,
- (q31_t)0xFF04ACD0, (q31_t)0x8001634D, (q31_t)0xFED2694F,
- (q31_t)0x8001E39B, (q31_t)0xFEA025FC, (q31_t)0x800277A5,
- (q31_t)0xFE6DE2E0, (q31_t)0x80031F6C, (q31_t)0xFE3BA001,
- (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x8004AA31,
- (q31_t)0xFDD71B1E, (q31_t)0x80058D2E, (q31_t)0xFDA4D928,
- (q31_t)0x800683E8, (q31_t)0xFD72978F, (q31_t)0x80078E5E,
- (q31_t)0xFD40565B, (q31_t)0x8008AC90, (q31_t)0xFD0E1594,
- (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800B2427,
- (q31_t)0xFCA99569, (q31_t)0x800C7D8C, (q31_t)0xFC775616,
- (q31_t)0x800DEAAC, (q31_t)0xFC45174E, (q31_t)0x800F6B88,
- (q31_t)0xFC12D919, (q31_t)0x8011001E, (q31_t)0xFBE09B80,
- (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x8014647A,
- (q31_t)0xFB7C223C, (q31_t)0x80163440, (q31_t)0xFB49E6A2,
- (q31_t)0x801817BF, (q31_t)0xFB17ABC2, (q31_t)0x801A0EF7,
- (q31_t)0xFAE571A4, (q31_t)0x801C19E9, (q31_t)0xFAB3384F,
- (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80206AF8,
- (q31_t)0xFA4EC820, (q31_t)0x8022B113, (q31_t)0xFA1C9156,
- (q31_t)0x80250AE7, (q31_t)0xF9EA5B75, (q31_t)0x80277872,
- (q31_t)0xF9B82683, (q31_t)0x8029F9B4, (q31_t)0xF985F28A,
- (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x802F375C,
- (q31_t)0xF9218D9E, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB,
- (q31_t)0x8034C3DC, (q31_t)0xF8BD2CEF, (q31_t)0x8037A7AC,
- (q31_t)0xF88AFE41, (q31_t)0x803A9F31, (q31_t)0xF858D0BA,
- (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8040C956,
- (q31_t)0xF7F4793E, (q31_t)0x8043FBF6, (q31_t)0xF7C24F58,
- (q31_t)0x80474248, (q31_t)0xF79026B8, (q31_t)0x804A9C4D,
- (q31_t)0xF75DFF65, (q31_t)0x804E0A03, (q31_t)0xF72BD967,
- (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x80552083,
- (q31_t)0xF6C79188, (q31_t)0x8058C94C, (q31_t)0xF6956FB6,
- (q31_t)0x805C85C3, (q31_t)0xF6634F58, (q31_t)0x806055EA,
- (q31_t)0xF6313076, (q31_t)0x806439C0, (q31_t)0xF5FF1317,
- (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x806C3C73,
- (q31_t)0xF59ADD01, (q31_t)0x80705B50, (q31_t)0xF568C45A,
- (q31_t)0x80748DD9, (q31_t)0xF536AD55, (q31_t)0x8078D40D,
- (q31_t)0xF50497FA, (q31_t)0x807D2DEB, (q31_t)0xF4D28451,
- (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x80861CA5,
- (q31_t)0xF46E6231, (q31_t)0x808AB180, (q31_t)0xF43C53CA,
- (q31_t)0x808F5A02, (q31_t)0xF40A4734, (q31_t)0x8094162B,
- (q31_t)0xF3D83C76, (q31_t)0x8098E5FB, (q31_t)0xF3A63398,
- (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A2C08B,
- (q31_t)0xF342279A, (q31_t)0x80A7CB49, (q31_t)0xF310248A,
- (q31_t)0x80ACE9AB, (q31_t)0xF2DE2378, (q31_t)0x80B21BAF,
- (q31_t)0xF2AC246D, (q31_t)0x80B76155, (q31_t)0xF27A2770,
- (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C22783,
- (q31_t)0xF21633C0, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C,
- (q31_t)0x80CD3C2F, (q31_t)0xF1B248A5, (q31_t)0x80D2E3F1,
- (q31_t)0xF1805662, (q31_t)0x80D89F51, (q31_t)0xF14E665C,
- (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80E450E2,
- (q31_t)0xF0EA8D23, (q31_t)0x80EA4712, (q31_t)0xF0B8A401,
- (q31_t)0x80F050DB, (q31_t)0xF086BD39, (q31_t)0x80F66E3C,
- (q31_t)0xF054D8D4, (q31_t)0x80FC9F35, (q31_t)0xF022F6DA,
- (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x81093BE8,
- (q31_t)0xEFBF3A44, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8,
- (q31_t)0x811626EC, (q31_t)0xEF5B87B5, (q31_t)0x811CB9CA,
- (q31_t)0xEF29B243, (q31_t)0x81236039, (q31_t)0xEEF7DF6A,
- (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8130E7C8,
- (q31_t)0xEE9441A0, (q31_t)0x8137C8E6, (q31_t)0xEE6276BF,
- (q31_t)0x813EBD90, (q31_t)0xEE30AE95, (q31_t)0x8145C5C6,
- (q31_t)0xEDFEE92B, (q31_t)0x814CE188, (q31_t)0xEDCD2687,
- (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x815B53A8,
- (q31_t)0xED69A9B2, (q31_t)0x8162AA03, (q31_t)0xED37EF91,
- (q31_t)0x816A13E6, (q31_t)0xED063855, (q31_t)0x8171914E,
- (q31_t)0xECD48406, (q31_t)0x8179223A, (q31_t)0xECA2D2AC,
- (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81887E9A,
- (q31_t)0xEC3F78F5, (q31_t)0x81904A0C, (q31_t)0xEC0DD0A8,
- (q31_t)0x819828FD, (q31_t)0xEBDC2B6D, (q31_t)0x81A01B6C,
- (q31_t)0xEBAA894E, (q31_t)0x81A82159, (q31_t)0xEB78EA52,
- (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81B867A4,
- (q31_t)0xEB15B5E0, (q31_t)0x81C0A801, (q31_t)0xEAE4207A,
- (q31_t)0x81C8FBD5, (q31_t)0xEAB28E55, (q31_t)0x81D16320,
- (q31_t)0xEA80FF79, (q31_t)0x81D9DDE1, (q31_t)0xEA4F73EE,
- (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81EB0DBD,
- (q31_t)0xE9EC66E8, (q31_t)0x81F3C2D7, (q31_t)0xE9BAE57C,
- (q31_t)0x81FC8B60, (q31_t)0xE9896780, (q31_t)0x82056758,
- (q31_t)0xE957ECFB, (q31_t)0x820E56BE, (q31_t)0xE92675F4,
- (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82206FCB,
- (q31_t)0xE8C3927F, (q31_t)0x82299971, (q31_t)0xE8922621,
- (q31_t)0x8232D67E, (q31_t)0xE860BD60, (q31_t)0x823C26F2,
- (q31_t)0xE82F5844, (q31_t)0x82458ACB, (q31_t)0xE7FDF6D3,
- (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82588CA6,
- (q31_t)0xE79B3F16, (q31_t)0x82622AA5, (q31_t)0xE769E8D8,
- (q31_t)0x826BDC04, (q31_t)0xE7389664, (q31_t)0x8275A0C0,
- (q31_t)0xE70747C3, (q31_t)0x827F78D8, (q31_t)0xE6D5FCFC,
- (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x82936316,
- (q31_t)0xE6737319, (q31_t)0x829D753A, (q31_t)0xE642340D,
- (q31_t)0x82A79AB3, (q31_t)0xE610F8F9, (q31_t)0x82B1D381,
- (q31_t)0xE5DFC1E4, (q31_t)0x82BC1FA1, (q31_t)0xE5AE8ED8,
- (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82D0F1D5,
- (q31_t)0xE54C34F3, (q31_t)0x82DB77E5, (q31_t)0xE51B0E2A,
- (q31_t)0x82E61141, (q31_t)0xE4E9EB86, (q31_t)0x82F0BDE8,
- (q31_t)0xE4B8CD10, (q31_t)0x82FB7DD8, (q31_t)0xE487B2CF,
- (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x8311378C,
- (q31_t)0xE4258B0A, (q31_t)0x831C314E, (q31_t)0xE3F47D95,
- (q31_t)0x83273E52, (q31_t)0xE3C37473, (q31_t)0x83325E97,
- (q31_t)0xE3926FAC, (q31_t)0x833D921A, (q31_t)0xE3616F47,
- (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835432D8,
- (q31_t)0xE2FF7BC3, (q31_t)0x835FA00E, (q31_t)0xE2CE88B2,
- (q31_t)0x836B207D, (q31_t)0xE29D9A22, (q31_t)0x8376B422,
- (q31_t)0xE26CB01A, (q31_t)0x83825AFB, (q31_t)0xE23BCAA2,
- (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x8399E244,
- (q31_t)0xE1DA0D7E, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1,
- (q31_t)0x83B1B649, (q31_t)0xE17862F3, (q31_t)0x83BDBD0D,
- (q31_t)0xE14794B9, (q31_t)0x83C9D6FB, (q31_t)0xE116CB3D,
- (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83E2444D,
- (q31_t)0xE0B54698, (q31_t)0x83EE97AC, (q31_t)0xE0848B7F,
- (q31_t)0x83FAFE2E, (q31_t)0xE053D541, (q31_t)0x840777CF,
- (q31_t)0xE02323E5, (q31_t)0x8414048F, (q31_t)0xDFF27773,
- (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x842D5761,
- (q31_t)0xDF912D6A, (q31_t)0x843A1D70, (q31_t)0xDF608FE3,
- (q31_t)0x8446F695, (q31_t)0xDF2FF764, (q31_t)0x8453E2CE,
- (q31_t)0xDEFF63F4, (q31_t)0x8460E21A, (q31_t)0xDECED59B,
- (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x847B19E1,
- (q31_t)0xDE6DC84B, (q31_t)0x84885257, (q31_t)0xDE3D4963,
- (q31_t)0x84959DD9, (q31_t)0xDE0CCFB1, (q31_t)0x84A2FC62,
- (q31_t)0xDDDC5B3A, (q31_t)0x84B06DF1, (q31_t)0xDDABEC07,
- (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84CB8A1B,
- (q31_t)0xDD4B1D8B, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51,
- (q31_t)0x84E6F244, (q31_t)0xDCEA6478, (q31_t)0x84F4C2D3,
- (q31_t)0xDCBA1008, (q31_t)0x8502A65C, (q31_t)0xDC89C108,
- (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x851EA652,
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- (q31_t)0x853AF214, (q31_t)0xDBC8BC05, (q31_t)0x8549345C,
- (q31_t)0xDB9888A8, (q31_t)0x85578991, (q31_t)0xDB685AE8,
- (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x85746CB7,
- (q31_t)0xDB08105E, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2,
- (q31_t)0x85919B75, (q31_t)0xDAA7DCA1, (q31_t)0x85A04F28,
- (q31_t)0xDA77CB62, (q31_t)0x85AF15B9, (q31_t)0xDA47BFED,
- (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85CCDB70,
- (q31_t)0xD9E7BA7E, (q31_t)0x85DBDA91, (q31_t)0xD9B7C093,
- (q31_t)0x85EAEC88, (q31_t)0xD987CC8F, (q31_t)0x85FA1152,
- (q31_t)0xD957DE7A, (q31_t)0x860948EE, (q31_t)0xD927F65B,
- (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x8627F090,
- (q31_t)0xD8C8381C, (q31_t)0x86376092, (q31_t)0xD898620C,
- (q31_t)0x8646E35B, (q31_t)0xD868920F, (q31_t)0x865678EA,
- (q31_t)0xD838C82D, (q31_t)0x8666213C, (q31_t)0xD809046D,
- (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x8685AA1F,
- (q31_t)0xD7A98F73, (q31_t)0x86958AAB, (q31_t)0xD779DE46,
- (q31_t)0x86A57DF1, (q31_t)0xD74A335A, (q31_t)0x86B583EE,
- (q31_t)0xD71A8EB5, (q31_t)0x86C59C9F, (q31_t)0xD6EAF05E,
- (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86E60614,
- (q31_t)0xD68BC6BA, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B,
- (q31_t)0x8706BA3C, (q31_t)0xD62CB6A7, (q31_t)0x8717304E,
- (q31_t)0xD5FD3847, (q31_t)0x8727B904, (q31_t)0xD5CDC062,
- (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x87490257,
- (q31_t)0xD56EE424, (q31_t)0x8759C2EF, (q31_t)0xD53F7FDA,
- (q31_t)0x876A9621, (q31_t)0xD5102227, (q31_t)0x877B7BEC,
- (q31_t)0xD4E0CB14, (q31_t)0x878C744C, (q31_t)0xD4B17AA7,
- (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87AE9CC5,
- (q31_t)0xD452EDDE, (q31_t)0x87BFCCD7, (q31_t)0xD423B190,
- (q31_t)0x87D10F75, (q31_t)0xD3F47C06, (q31_t)0x87E2649B,
- (q31_t)0xD3C54D46, (q31_t)0x87F3CC47, (q31_t)0xD3962559,
- (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8816D327,
- (q31_t)0xD337EA12, (q31_t)0x88287255, (q31_t)0xD308D6C6,
- (q31_t)0x883A23FE, (q31_t)0xD2D9CA6A, (q31_t)0x884BE820,
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- (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8881A33C,
- (q31_t)0xD21DDEE1, (q31_t)0x8893B124, (q31_t)0xD1EEF59E,
- (q31_t)0x88A5D177, (q31_t)0xD1C01374, (q31_t)0x88B80431,
- (q31_t)0xD191386D, (q31_t)0x88CA4951, (q31_t)0xD162648F,
- (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x88EF0AB4,
- (q31_t)0xD104D26B, (q31_t)0x890186F1, (q31_t)0xD0D61433,
- (q31_t)0x89141589, (q31_t)0xD0A75D42, (q31_t)0x8926B677,
- (q31_t)0xD078AD9D, (q31_t)0x893969B9, (q31_t)0xD04A054D,
- (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x895F072D,
- (q31_t)0xCFECCAC7, (q31_t)0x8971F15A, (q31_t)0xCFBE389F,
- (q31_t)0x8984EDCF, (q31_t)0xCF8FADE8, (q31_t)0x8997FC89,
- (q31_t)0xCF612AAA, (q31_t)0x89AB1D86, (q31_t)0xCF32AEEB,
- (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89D1963C,
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- (q31_t)0xC9FBE527, (q31_t)0x8C09EB40, (q31_t)0xC9CE5748,
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- (q31_t)0xC7540F10, (q31_t)0x8D50FA59, (q31_t)0xC727016C,
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- (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DC175E0,
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- (q31_t)0xC3A9458F, (q31_t)0x8F34EED8, (q31_t)0xC37CF5B0,
- (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F64983F,
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- (q31_t)0x8F94871D, (q31_t)0xC2CC13C7, (q31_t)0x8FAC988E,
- (q31_t)0xC29FF2D4, (q31_t)0x8FC4BB53, (q31_t)0xC273DB58,
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- (q31_t)0xC21BC8E0, (q31_t)0x900D8B69, (q31_t)0xC1EFCDF2,
- (q31_t)0x9025F352, (q31_t)0xC1C3DC96, (q31_t)0x903E6C7A,
- (q31_t)0xC197F4D3, (q31_t)0x9056F6DF, (q31_t)0xC16C16B0,
- (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90883F4C,
- (q31_t)0xC1147763, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648,
- (q31_t)0x90B9CC7C, (q31_t)0xC0BCFEE7, (q31_t)0x90D2ACD3,
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- (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x911DB4A8,
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- (q31_t)0xB48A90C0, (q31_t)0x989B8E3F, (q31_t)0xB4B330B2,
- (q31_t)0x987DF449, (q31_t)0xB4DBDC42, (q31_t)0x98606A48,
- (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB52D561E,
- (q31_t)0x9825863D, (q31_t)0xB556245E, (q31_t)0x98082C3B,
- (q31_t)0xB57EFE21, (q31_t)0x97EAE241, (q31_t)0xB5A7E362,
- (q31_t)0x97CDA855, (q31_t)0xB5D0D41A, (q31_t)0x97B07E7A,
- (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB622D7D5,
- (q31_t)0x97765B0A, (q31_t)0xB64BEACC, (q31_t)0x9759617E,
- (q31_t)0xB6750921, (q31_t)0x973C7816, (q31_t)0xB69E32CD,
- (q31_t)0x971F9ED6, (q31_t)0xB6C767CA, (q31_t)0x9702D5C2,
- (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB719F39D,
- (q31_t)0x96C97431, (q31_t)0xB7434A67, (q31_t)0x96ACDBBD,
- (q31_t)0xB76CAC68, (q31_t)0x96905387, (q31_t)0xB796199B,
- (q31_t)0x9673DB94, (q31_t)0xB7BF91F8, (q31_t)0x965773E7,
- (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB812A419,
- (q31_t)0x961ED573, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5,
- (q31_t)0xB865E299, (q31_t)0x95E6784F, (q31_t)0xB88F926C,
- (q31_t)0x95CA6246, (q31_t)0xB8B94D44, (q31_t)0x95AE5C9E,
- (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB90CE3E6,
- (q31_t)0x95768282, (q31_t)0xB936BFA3, (q31_t)0x955AAE17,
- (q31_t)0xB960A64B, (q31_t)0x953EEA1E, (q31_t)0xB98A97D8,
- (q31_t)0x9523369B, (q31_t)0xB9B49442, (q31_t)0x95079393,
- (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA08AD94,
- (q31_t)0x94D07F05, (q31_t)0xBA32CA70, (q31_t)0x94B50D87,
- (q31_t)0xBA5CF210, (q31_t)0x9499AC95, (q31_t)0xBA87246C,
- (q31_t)0x947E5C32, (q31_t)0xBAB1617F, (q31_t)0x94631C64,
- (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB05FBB0,
- (q31_t)0x942CCE95, (q31_t)0xBB3058C0, (q31_t)0x9411C09D,
- (q31_t)0xBB5AC06C, (q31_t)0x93F6C34A, (q31_t)0xBB8532AF,
- (q31_t)0x93DBD69F, (q31_t)0xBBAFAF81, (q31_t)0x93C0FAA2,
- (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC04C8BA,
- (q31_t)0x938B74C0, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4,
- (q31_t)0xBC5A0BE1, (q31_t)0x935631C5, (q31_t)0xBC84BD1E,
- (q31_t)0x933BA968, (q31_t)0xBCAF78C3, (q31_t)0x932131D1,
- (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD050F2C,
- (q31_t)0x92EC7505, (q31_t)0xBD2FE9E1, (q31_t)0x92D22FD8,
- (q31_t)0xBD5ACEE5, (q31_t)0x92B7FB82, (q31_t)0xBD85BE2F,
- (q31_t)0x929DD805, (q31_t)0xBDB0B7BA, (q31_t)0x9283C567,
- (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE06C977,
- (q31_t)0x924FD2D6, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB,
- (q31_t)0xBE5D03E5, (q31_t)0x921C23EE, (q31_t)0xBE88304F,
- (q31_t)0x920265E4, (q31_t)0xBEB366D1, (q31_t)0x91E8B8D0,
- (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF09F204,
- (q31_t)0x91B5919A, (q31_t)0xBF3546A8, (q31_t)0x919C1780,
- (q31_t)0xBF60A54A, (q31_t)0x9182AE6C, (q31_t)0xBF8C0DE2,
- (q31_t)0x91695663, (q31_t)0xBFB7806C, (q31_t)0x91500F67,
- (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC00E8335,
- (q31_t)0x911DB4A8, (q31_t)0xC03A1368, (q31_t)0x9104A0ED,
- (q31_t)0xC065AD70, (q31_t)0x90EB9E50, (q31_t)0xC0915147,
- (q31_t)0x90D2ACD3, (q31_t)0xC0BCFEE7, (q31_t)0x90B9CC7C,
- (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1147763,
- (q31_t)0x90883F4C, (q31_t)0xC1404233, (q31_t)0x906F927B,
- (q31_t)0xC16C16B0, (q31_t)0x9056F6DF, (q31_t)0xC197F4D3,
- (q31_t)0x903E6C7A, (q31_t)0xC1C3DC96, (q31_t)0x9025F352,
- (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC21BC8E0,
- (q31_t)0x8FF534C4, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66,
- (q31_t)0xC273DB58, (q31_t)0x8FC4BB53, (q31_t)0xC29FF2D4,
- (q31_t)0x8FAC988E, (q31_t)0xC2CC13C7, (q31_t)0x8F94871D,
- (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC32471F6,
- (q31_t)0x8F64983F, (q31_t)0xC350AF25, (q31_t)0x8F4CBADB,
- (q31_t)0xC37CF5B0, (q31_t)0x8F34EED8, (q31_t)0xC3A9458F,
- (q31_t)0x8F1D343A, (q31_t)0xC3D59EBD, (q31_t)0x8F058B04,
- (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC42E6CE8,
- (q31_t)0x8ED66CE1, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB,
- (q31_t)0xC4875FF8, (q31_t)0x8EA7948C, (q31_t)0xC4B3E746,
- (q31_t)0x8E904298, (q31_t)0xC4E077B8, (q31_t)0x8E790222,
- (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC539B3F0,
- (q31_t)0x8E4AB5BF, (q31_t)0xC5665FA8, (q31_t)0x8E33A9D9,
- (q31_t)0xC593146A, (q31_t)0x8E1CAF80, (q31_t)0xC5BFD22E,
- (q31_t)0x8E05C6B7, (q31_t)0xC5EC98ED, (q31_t)0x8DEEEF82,
- (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC6464144,
- (q31_t)0x8DC175E0, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B,
- (q31_t)0xC6A00D36, (q31_t)0x8D9442B7, (q31_t)0xC6CD0079,
- (q31_t)0x8D7DC399, (q31_t)0xC6F9FC8D, (q31_t)0x8D675623,
- (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7540F10,
- (q31_t)0x8D3AB03F, (q31_t)0xC7812571, (q31_t)0x8D2477D8,
- (q31_t)0xC7AE4489, (q31_t)0x8D0E5127, (q31_t)0xC7DB6C50,
- (q31_t)0x8CF83C30, (q31_t)0xC8089CBF, (q31_t)0x8CE238F6,
- (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC863177B,
- (q31_t)0x8CB667C7, (q31_t)0xC89061BA, (q31_t)0x8CA099D9,
- (q31_t)0xC8BDB485, (q31_t)0x8C8ADDB6, (q31_t)0xC8EB0FD6,
- (q31_t)0x8C753361, (q31_t)0xC91873A5, (q31_t)0x8C5F9ADD,
- (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC97354A3,
- (q31_t)0x8C349F58, (q31_t)0xC9A0D1C4, (q31_t)0x8C1F3C5C,
- (q31_t)0xC9CE5748, (q31_t)0x8C09EB40, (q31_t)0xC9FBE527,
- (q31_t)0x8BF4AC05, (q31_t)0xCA297B5A, (q31_t)0x8BDF7EAF,
- (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCA84C0A2,
- (q31_t)0x8BB559C1, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F,
- (q31_t)0xCAE026E8, (q31_t)0x8B8B7C8F, (q31_t)0xCB0DE658,
- (q31_t)0x8B76A8E4, (q31_t)0xCB3BADF2, (q31_t)0x8B61E732,
- (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCB975589,
- (q31_t)0x8B3899C5, (q31_t)0xCBC53578, (q31_t)0x8B240E10,
- (q31_t)0xCBF31D75, (q31_t)0x8B0F9461, (q31_t)0xCC210D78,
- (q31_t)0x8AFB2CBA, (q31_t)0xCC4F057B, (q31_t)0x8AE6D71F,
- (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCAB0D65,
- (q31_t)0x8ABE6219, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4,
- (q31_t)0xCD0734F8, (q31_t)0x8A963567, (q31_t)0xCD355490,
- (q31_t)0x8A823A35, (q31_t)0xCD637BFD, (q31_t)0x8A6E5122,
- (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDBFE23A,
- (q31_t)0x8A46B563, (q31_t)0xCDEE20FC, (q31_t)0x8A3302BD,
- (q31_t)0xCE1C6776, (q31_t)0x8A1F6242, (q31_t)0xCE4AB5A2,
- (q31_t)0x8A0BD3F5, (q31_t)0xCE790B78, (q31_t)0x89F857D8,
- (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCED5CE08,
- (q31_t)0x89D1963C, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3,
- (q31_t)0xCF32AEEB, (q31_t)0x89AB1D86, (q31_t)0xCF612AAA,
- (q31_t)0x8997FC89, (q31_t)0xCF8FADE8, (q31_t)0x8984EDCF,
- (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xCFECCAC7,
- (q31_t)0x895F072D, (q31_t)0xD01B6459, (q31_t)0x894C2F4C,
- (q31_t)0xD04A054D, (q31_t)0x893969B9, (q31_t)0xD078AD9D,
- (q31_t)0x8926B677, (q31_t)0xD0A75D42, (q31_t)0x89141589,
- (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD104D26B,
- (q31_t)0x88EF0AB4, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3,
- (q31_t)0xD162648F, (q31_t)0x88CA4951, (q31_t)0xD191386D,
- (q31_t)0x88B80431, (q31_t)0xD1C01374, (q31_t)0x88A5D177,
- (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD21DDEE1,
- (q31_t)0x8881A33C, (q31_t)0xD24CCF38, (q31_t)0x886FA7C2,
- (q31_t)0xD27BC69C, (q31_t)0x885DBEB7, (q31_t)0xD2AAC504,
- (q31_t)0x884BE820, (q31_t)0xD2D9CA6A, (q31_t)0x883A23FE,
- (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD337EA12,
- (q31_t)0x8816D327, (q31_t)0xD3670445, (q31_t)0x88054677,
- (q31_t)0xD3962559, (q31_t)0x87F3CC47, (q31_t)0xD3C54D46,
- (q31_t)0x87E2649B, (q31_t)0xD3F47C06, (q31_t)0x87D10F75,
- (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD452EDDE,
- (q31_t)0x87AE9CC5, (q31_t)0xD48230E8, (q31_t)0x879D7F40,
- (q31_t)0xD4B17AA7, (q31_t)0x878C744C, (q31_t)0xD4E0CB14,
- (q31_t)0x877B7BEC, (q31_t)0xD5102227, (q31_t)0x876A9621,
- (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD56EE424,
- (q31_t)0x87490257, (q31_t)0xD59E4EFE, (q31_t)0x8738545E,
- (q31_t)0xD5CDC062, (q31_t)0x8727B904, (q31_t)0xD5FD3847,
- (q31_t)0x8717304E, (q31_t)0xD62CB6A7, (q31_t)0x8706BA3C,
- (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD68BC6BA,
- (q31_t)0x86E60614, (q31_t)0xD6BB585D, (q31_t)0x86D5C802,
- (q31_t)0xD6EAF05E, (q31_t)0x86C59C9F, (q31_t)0xD71A8EB5,
- (q31_t)0x86B583EE, (q31_t)0xD74A335A, (q31_t)0x86A57DF1,
- (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7A98F73,
- (q31_t)0x8685AA1F, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E,
- (q31_t)0xD809046D, (q31_t)0x8666213C, (q31_t)0xD838C82D,
- (q31_t)0x865678EA, (q31_t)0xD868920F, (q31_t)0x8646E35B,
- (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8C8381C,
- (q31_t)0x8627F090, (q31_t)0xD8F81439, (q31_t)0x86189359,
- (q31_t)0xD927F65B, (q31_t)0x860948EE, (q31_t)0xD957DE7A,
- (q31_t)0x85FA1152, (q31_t)0xD987CC8F, (q31_t)0x85EAEC88,
- (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xD9E7BA7E,
- (q31_t)0x85CCDB70, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27,
- (q31_t)0xDA47BFED, (q31_t)0x85AF15B9, (q31_t)0xDA77CB62,
- (q31_t)0x85A04F28, (q31_t)0xDAA7DCA1, (q31_t)0x85919B75,
- (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB08105E,
- (q31_t)0x85746CB7, (q31_t)0xDB3832CD, (q31_t)0x8565F1B0,
- (q31_t)0xDB685AE8, (q31_t)0x85578991, (q31_t)0xDB9888A8,
- (q31_t)0x8549345C, (q31_t)0xDBC8BC05, (q31_t)0x853AF214,
- (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC293379,
- (q31_t)0x851EA652, (q31_t)0xDC597781, (q31_t)0x85109CDC,
- (q31_t)0xDC89C108, (q31_t)0x8502A65C, (q31_t)0xDCBA1008,
- (q31_t)0x84F4C2D3, (q31_t)0xDCEA6478, (q31_t)0x84E6F244,
- (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD4B1D8B,
- (q31_t)0x84CB8A1B, (q31_t)0xDD7B8220, (q31_t)0x84BDF285,
- (q31_t)0xDDABEC07, (q31_t)0x84B06DF1, (q31_t)0xDDDC5B3A,
- (q31_t)0x84A2FC62, (q31_t)0xDE0CCFB1, (q31_t)0x84959DD9,
- (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE6DC84B,
- (q31_t)0x847B19E1, (q31_t)0xDE9E4C60, (q31_t)0x846DF476,
- (q31_t)0xDECED59B, (q31_t)0x8460E21A, (q31_t)0xDEFF63F4,
- (q31_t)0x8453E2CE, (q31_t)0xDF2FF764, (q31_t)0x8446F695,
- (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDF912D6A,
- (q31_t)0x842D5761, (q31_t)0xDFC1CFF2, (q31_t)0x8420A46B,
- (q31_t)0xDFF27773, (q31_t)0x8414048F, (q31_t)0xE02323E5,
- (q31_t)0x840777CF, (q31_t)0xE053D541, (q31_t)0x83FAFE2E,
- (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0B54698,
- (q31_t)0x83E2444D, (q31_t)0xE0E60684, (q31_t)0x83D60411,
- (q31_t)0xE116CB3D, (q31_t)0x83C9D6FB, (q31_t)0xE14794B9,
- (q31_t)0x83BDBD0D, (q31_t)0xE17862F3, (q31_t)0x83B1B649,
- (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE1DA0D7E,
- (q31_t)0x8399E244, (q31_t)0xE20AE9C1, (q31_t)0x838E1507,
- (q31_t)0xE23BCAA2, (q31_t)0x83825AFB, (q31_t)0xE26CB01A,
- (q31_t)0x8376B422, (q31_t)0xE29D9A22, (q31_t)0x836B207D,
- (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE2FF7BC3,
- (q31_t)0x835432D8, (q31_t)0xE330734C, (q31_t)0x8348D8DB,
- (q31_t)0xE3616F47, (q31_t)0x833D921A, (q31_t)0xE3926FAC,
- (q31_t)0x83325E97, (q31_t)0xE3C37473, (q31_t)0x83273E52,
- (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4258B0A,
- (q31_t)0x8311378C, (q31_t)0xE4569CCB, (q31_t)0x8306510F,
- (q31_t)0xE487B2CF, (q31_t)0x82FB7DD8, (q31_t)0xE4B8CD10,
- (q31_t)0x82F0BDE8, (q31_t)0xE4E9EB86, (q31_t)0x82E61141,
- (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE54C34F3,
- (q31_t)0x82D0F1D5, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13,
- (q31_t)0xE5AE8ED8, (q31_t)0x82BC1FA1, (q31_t)0xE5DFC1E4,
- (q31_t)0x82B1D381, (q31_t)0xE610F8F9, (q31_t)0x82A79AB3,
- (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6737319,
- (q31_t)0x82936316, (q31_t)0xE6A4B616, (q31_t)0x8289644A,
- (q31_t)0xE6D5FCFC, (q31_t)0x827F78D8, (q31_t)0xE70747C3,
- (q31_t)0x8275A0C0, (q31_t)0xE7389664, (q31_t)0x826BDC04,
- (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE79B3F16,
- (q31_t)0x82588CA6, (q31_t)0xE7CC9917, (q31_t)0x824F0208,
- (q31_t)0xE7FDF6D3, (q31_t)0x82458ACB, (q31_t)0xE82F5844,
- (q31_t)0x823C26F2, (q31_t)0xE860BD60, (q31_t)0x8232D67E,
- (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8C3927F,
- (q31_t)0x82206FCB, (q31_t)0xE8F50273, (q31_t)0x8217598F,
- (q31_t)0xE92675F4, (q31_t)0x820E56BE, (q31_t)0xE957ECFB,
- (q31_t)0x82056758, (q31_t)0xE9896780, (q31_t)0x81FC8B60,
- (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8,
- (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16,
- (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79,
- (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5,
- (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0,
- (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1,
- (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E,
- (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD,
- (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5,
- (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9,
- (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406,
- (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6,
- (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2,
- (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3,
- (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B,
- (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90,
- (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0,
- (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39,
- (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243,
- (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC,
- (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44,
- (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3,
- (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4,
- (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB,
- (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23,
- (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C,
- (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662,
- (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F,
- (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0,
- (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C,
- (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D,
- (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB,
- (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A,
- (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970,
- (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76,
- (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02,
- (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231,
- (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74,
- (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA,
- (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9,
- (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01,
- (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143,
- (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076,
- (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3,
- (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188,
- (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B,
- (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65,
- (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248,
- (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E,
- (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69,
- (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41,
- (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC,
- (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E,
- (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD,
- (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683,
- (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7,
- (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820,
- (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894,
- (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4,
- (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF,
- (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C,
- (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F,
- (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919,
- (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC,
- (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569,
- (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D,
- (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B,
- (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8,
- (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E,
- (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0,
- (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0,
- (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B,
- (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0,
- (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9,
- (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D,
- (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE
-};
-
-
-
-/*
-* @brief q15 Twiddle factors Table
-*/
-
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 16 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_16_q15[24] = {
- (q15_t)0x7FFF, (q15_t)0x0000,
- (q15_t)0x7641, (q15_t)0x30FB,
- (q15_t)0x5A82, (q15_t)0x5A82,
- (q15_t)0x30FB, (q15_t)0x7641,
- (q15_t)0x0000, (q15_t)0x7FFF,
- (q15_t)0xCF04, (q15_t)0x7641,
- (q15_t)0xA57D, (q15_t)0x5A82,
- (q15_t)0x89BE, (q15_t)0x30FB,
- (q15_t)0x8000, (q15_t)0x0000,
- (q15_t)0x89BE, (q15_t)0xCF04,
- (q15_t)0xA57D, (q15_t)0xA57D,
- (q15_t)0xCF04, (q15_t)0x89BE
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 32 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_32_q15[48] = {
- (q15_t)0x7FFF, (q15_t)0x0000,
- (q15_t)0x7D8A, (q15_t)0x18F8,
- (q15_t)0x7641, (q15_t)0x30FB,
- (q15_t)0x6A6D, (q15_t)0x471C,
- (q15_t)0x5A82, (q15_t)0x5A82,
- (q15_t)0x471C, (q15_t)0x6A6D,
- (q15_t)0x30FB, (q15_t)0x7641,
- (q15_t)0x18F8, (q15_t)0x7D8A,
- (q15_t)0x0000, (q15_t)0x7FFF,
- (q15_t)0xE707, (q15_t)0x7D8A,
- (q15_t)0xCF04, (q15_t)0x7641,
- (q15_t)0xB8E3, (q15_t)0x6A6D,
- (q15_t)0xA57D, (q15_t)0x5A82,
- (q15_t)0x9592, (q15_t)0x471C,
- (q15_t)0x89BE, (q15_t)0x30FB,
- (q15_t)0x8275, (q15_t)0x18F8,
- (q15_t)0x8000, (q15_t)0x0000,
- (q15_t)0x8275, (q15_t)0xE707,
- (q15_t)0x89BE, (q15_t)0xCF04,
- (q15_t)0x9592, (q15_t)0xB8E3,
- (q15_t)0xA57D, (q15_t)0xA57D,
- (q15_t)0xB8E3, (q15_t)0x9592,
- (q15_t)0xCF04, (q15_t)0x89BE,
- (q15_t)0xE707, (q15_t)0x8275
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 64 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_64_q15[96] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 128 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_128_q15[192] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA,
- (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F,
- (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7,
- (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA,
- (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884,
- (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D,
- (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE,
- (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F,
- (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 256 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_256_q15[384] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324,
- (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB,
- (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B,
- (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826,
- (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE,
- (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C,
- (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17,
- (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4,
- (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF,
- (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B,
- (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4,
- (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC,
- (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8,
- (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24,
- (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F,
- (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255,
- (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C,
- (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A,
- (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D,
- (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D,
- (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09,
- (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7,
- (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6,
- (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09,
- (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3,
- (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A,
- (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504,
- (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F,
- (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6,
- (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC,
- (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842,
- (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF,
- (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A,
- (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17,
- (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C,
- (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11,
- (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826,
- (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223,
- (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2,
- (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A,
- (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB,
- (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054,
- (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4,
- (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9,
- (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21,
- (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8,
- (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B,
- (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64,
- (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B,
- (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17,
- (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB,
- (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA,
- (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893,
- (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2,
- (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2,
- (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058,
- (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 512 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_512_q15[768] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192,
- (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6,
- (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9,
- (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B,
- (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139,
- (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455,
- (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82,
- (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93,
- (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F,
- (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8,
- (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3,
- (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98,
- (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E,
- (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D,
- (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824,
- (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2,
- (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8,
- (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073,
- (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325,
- (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869,
- (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB,
- (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81,
- (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB,
- (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269,
- (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA,
- (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D,
- (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D,
- (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7,
- (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3,
- (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1,
- (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF,
- (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD,
- (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD,
- (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A,
- (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9,
- (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96,
- (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023,
- (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E,
- (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307,
- (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F,
- (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9,
- (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA,
- (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909,
- (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05,
- (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF,
- (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5,
- (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89,
- (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6,
- (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F,
- (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5,
- (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38,
- (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87,
- (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2,
- (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9,
- (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD,
- (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9,
- (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2,
- (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38,
- (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5,
- (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F,
- (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39,
- (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89,
- (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5,
- (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05,
- (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909,
- (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA,
- (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5,
- (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F,
- (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307,
- (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023,
- (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96,
- (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9,
- (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C,
- (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD,
- (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD,
- (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1,
- (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3,
- (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7,
- (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964,
- (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D,
- (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA,
- (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB,
- (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81,
- (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB,
- (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD,
- (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325,
- (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073,
- (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8,
- (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2,
- (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824,
- (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D,
- (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87,
- (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98,
- (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3,
- (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8,
- (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6,
- (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F,
- (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93,
- (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D,
- (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455,
- (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139,
- (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB,
- (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9,
- (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6,
- (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D,
- (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49,
- (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826,
- (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4,
- (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6,
- (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA,
- (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D,
- (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C,
- (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60,
- (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957,
- (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C,
- (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367,
- (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91,
- (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2,
- (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB,
- (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247,
- (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C,
- (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA,
- (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796,
- (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504,
- (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E,
- (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96,
- (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35,
- (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2,
- (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462,
- (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238,
- (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C,
- (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10,
- (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22,
- (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842,
- (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5,
- (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306,
- (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169,
- (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61,
- (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8,
- (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0,
- (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926,
- (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805,
- (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6,
- (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510,
- (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A,
- (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376,
- (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229,
- (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0,
- (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A,
- (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078,
- (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D,
- (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016,
- (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 1024 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_1024_q15[1536] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9,
- (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B,
- (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED,
- (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F,
- (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710,
- (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2,
- (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33,
- (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53,
- (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3,
- (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072,
- (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201,
- (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E,
- (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B,
- (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8,
- (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD,
- (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47,
- (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF,
- (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56,
- (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC,
- (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161,
- (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5,
- (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8,
- (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767,
- (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5,
- (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61,
- (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC,
- (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55,
- (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC,
- (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5,
- (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326,
- (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496,
- (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604,
- (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F,
- (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8,
- (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40,
- (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5,
- (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07,
- (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68,
- (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5,
- (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121,
- (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A,
- (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0,
- (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524,
- (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3,
- (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F,
- (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58,
- (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E,
- (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1,
- (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21,
- (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E,
- (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097,
- (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE,
- (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302,
- (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433,
- (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560,
- (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A,
- (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0,
- (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4,
- (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10,
- (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29,
- (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E,
- (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50,
- (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E,
- (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068,
- (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F,
- (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271,
- (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371,
- (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C,
- (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563,
- (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657,
- (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746,
- (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832,
- (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919,
- (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC,
- (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8,
- (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F,
- (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62,
- (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30,
- (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB,
- (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1,
- (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083,
- (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141,
- (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA,
- (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF,
- (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F,
- (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x3604, (q15_t)0x740B,
- (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x3496, (q15_t)0x74B2,
- (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3326, (q15_t)0x7555,
- (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x31B5, (q15_t)0x75F4,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x3041, (q15_t)0x768E,
- (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2ECC, (q15_t)0x7723,
- (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2D55, (q15_t)0x77B4,
- (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2BDC, (q15_t)0x7840,
- (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2A61, (q15_t)0x78C7,
- (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x28E5, (q15_t)0x794A,
- (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x2767, (q15_t)0x79C8,
- (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x25E8, (q15_t)0x7A42,
- (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2467, (q15_t)0x7AB6,
- (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x22E5, (q15_t)0x7B26,
- (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x2161, (q15_t)0x7B92,
- (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x1FDC, (q15_t)0x7BF8,
- (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1E56, (q15_t)0x7C5A,
- (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1CCF, (q15_t)0x7CB7,
- (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1B47, (q15_t)0x7D0F,
- (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x19BD, (q15_t)0x7D62,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1833, (q15_t)0x7DB0,
- (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x16A8, (q15_t)0x7DFA,
- (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x151B, (q15_t)0x7E3F,
- (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x138E, (q15_t)0x7E7F,
- (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1201, (q15_t)0x7EBA,
- (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1072, (q15_t)0x7EF0,
- (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0EE3, (q15_t)0x7F21,
- (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0D53, (q15_t)0x7F4D,
- (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0BC3, (q15_t)0x7F75,
- (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A33, (q15_t)0x7F97,
- (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x08A2, (q15_t)0x7FB5,
- (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0710, (q15_t)0x7FCE,
- (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x057F, (q15_t)0x7FE1,
- (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x03ED, (q15_t)0x7FF0,
- (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x025B, (q15_t)0x7FFA,
- (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x00C9, (q15_t)0x7FFF,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF36, (q15_t)0x7FFF,
- (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFDA4, (q15_t)0x7FFA,
- (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC12, (q15_t)0x7FF0,
- (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFA80, (q15_t)0x7FE1,
- (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF8EF, (q15_t)0x7FCE,
- (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF75D, (q15_t)0x7FB5,
- (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF5CC, (q15_t)0x7F97,
- (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF43C, (q15_t)0x7F75,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF2AC, (q15_t)0x7F4D,
- (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF11C, (q15_t)0x7F21,
- (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEF8D, (q15_t)0x7EF0,
- (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEDFE, (q15_t)0x7EBA,
- (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEC71, (q15_t)0x7E7F,
- (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEAE4, (q15_t)0x7E3F,
- (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE957, (q15_t)0x7DFA,
- (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE7CC, (q15_t)0x7DB0,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE642, (q15_t)0x7D62,
- (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE4B8, (q15_t)0x7D0F,
- (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE330, (q15_t)0x7CB7,
- (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE1A9, (q15_t)0x7C5A,
- (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE023, (q15_t)0x7BF8,
- (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDE9E, (q15_t)0x7B92,
- (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD1A, (q15_t)0x7B26,
- (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDB98, (q15_t)0x7AB6,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA17, (q15_t)0x7A42,
- (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD898, (q15_t)0x79C8,
- (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD71A, (q15_t)0x794A,
- (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD59E, (q15_t)0x78C7,
- (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD423, (q15_t)0x7840,
- (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD2AA, (q15_t)0x77B4,
- (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD133, (q15_t)0x7723,
- (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xCFBE, (q15_t)0x768E,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCE4A, (q15_t)0x75F4,
- (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCCD9, (q15_t)0x7555,
- (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCB69, (q15_t)0x74B2,
- (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xC9FB, (q15_t)0x740B,
- (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC890, (q15_t)0x735F,
- (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC727, (q15_t)0x72AF,
- (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC5BF, (q15_t)0x71FA,
- (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC45A, (q15_t)0x7141,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC2F8, (q15_t)0x7083,
- (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC197, (q15_t)0x6FC1,
- (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC03A, (q15_t)0x6EFB,
- (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBEDE, (q15_t)0x6E30,
- (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBD85, (q15_t)0x6D62,
- (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC2F, (q15_t)0x6C8F,
- (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBADB, (q15_t)0x6BB8,
- (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB98A, (q15_t)0x6ADC,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB83C, (q15_t)0x69FD,
- (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB6F0, (q15_t)0x6919,
- (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5A7, (q15_t)0x6832,
- (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB461, (q15_t)0x6746,
- (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB31E, (q15_t)0x6657,
- (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB1DE, (q15_t)0x6563,
- (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0A1, (q15_t)0x646C,
- (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAF68, (q15_t)0x6371,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE31, (q15_t)0x6271,
- (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xACFD, (q15_t)0x616F,
- (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xABCC, (q15_t)0x6068,
- (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAA9F, (q15_t)0x5F5E,
- (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA975, (q15_t)0x5E50,
- (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA84F, (q15_t)0x5D3E,
- (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA72B, (q15_t)0x5C29,
- (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA60C, (q15_t)0x5B10,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA4EF, (q15_t)0x59F3,
- (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA3D6, (q15_t)0x58D4,
- (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA2C1, (q15_t)0x57B0,
- (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1AF, (q15_t)0x568A,
- (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0A1, (q15_t)0x5560,
- (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9F97, (q15_t)0x5433,
- (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E90, (q15_t)0x5302,
- (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9D8E, (q15_t)0x51CE,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C8E, (q15_t)0x5097,
- (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9B93, (q15_t)0x4F5E,
- (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A9C, (q15_t)0x4E21,
- (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99A8, (q15_t)0x4CE1,
- (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98B9, (q15_t)0x4B9E,
- (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x97CD, (q15_t)0x4A58,
- (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x96E6, (q15_t)0x490F,
- (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9602, (q15_t)0x47C3,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9523, (q15_t)0x4675,
- (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9447, (q15_t)0x4524,
- (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9370, (q15_t)0x43D0,
- (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x929D, (q15_t)0x427A,
- (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x91CF, (q15_t)0x4121,
- (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9104, (q15_t)0x3FC5,
- (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x903E, (q15_t)0x3E68,
- (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8F7C, (q15_t)0x3D07,
- (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EBE, (q15_t)0x3BA5,
- (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E05, (q15_t)0x3A40,
- (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D50, (q15_t)0x38D8,
- (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CA0, (q15_t)0x376F,
- (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BF4, (q15_t)0x3604,
- (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B4D, (q15_t)0x3496,
- (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AAA, (q15_t)0x3326,
- (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A0B, (q15_t)0x31B5,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8971, (q15_t)0x3041,
- (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x88DC, (q15_t)0x2ECC,
- (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x884B, (q15_t)0x2D55,
- (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87BF, (q15_t)0x2BDC,
- (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8738, (q15_t)0x2A61,
- (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86B5, (q15_t)0x28E5,
- (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8637, (q15_t)0x2767,
- (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85BD, (q15_t)0x25E8,
- (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8549, (q15_t)0x2467,
- (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84D9, (q15_t)0x22E5,
- (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x846D, (q15_t)0x2161,
- (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8407, (q15_t)0x1FDC,
- (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83A5, (q15_t)0x1E56,
- (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x8348, (q15_t)0x1CCF,
- (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82F0, (q15_t)0x1B47,
- (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x829D, (q15_t)0x19BD,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x824F, (q15_t)0x1833,
- (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8205, (q15_t)0x16A8,
- (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81C0, (q15_t)0x151B,
- (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8180, (q15_t)0x138E,
- (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8145, (q15_t)0x1201,
- (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x810F, (q15_t)0x1072,
- (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80DE, (q15_t)0x0EE3,
- (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80B2, (q15_t)0x0D53,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x808A, (q15_t)0x0BC3,
- (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8068, (q15_t)0x0A33,
- (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x804A, (q15_t)0x08A2,
- (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8031, (q15_t)0x0710,
- (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x801E, (q15_t)0x057F,
- (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x800F, (q15_t)0x03ED,
- (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8005, (q15_t)0x025B,
- (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8000, (q15_t)0x00C9,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF36,
- (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8005, (q15_t)0xFDA4,
- (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800F, (q15_t)0xFC12,
- (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801E, (q15_t)0xFA80,
- (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8031, (q15_t)0xF8EF,
- (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x804A, (q15_t)0xF75D,
- (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8068, (q15_t)0xF5CC,
- (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x808A, (q15_t)0xF43C,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80B2, (q15_t)0xF2AC,
- (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80DE, (q15_t)0xF11C,
- (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x810F, (q15_t)0xEF8D,
- (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8145, (q15_t)0xEDFE,
- (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8180, (q15_t)0xEC71,
- (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81C0, (q15_t)0xEAE4,
- (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8205, (q15_t)0xE957,
- (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x824F, (q15_t)0xE7CC,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x829D, (q15_t)0xE642,
- (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82F0, (q15_t)0xE4B8,
- (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8348, (q15_t)0xE330,
- (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x83A5, (q15_t)0xE1A9,
- (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x8407, (q15_t)0xE023,
- (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x846D, (q15_t)0xDE9E,
- (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84D9, (q15_t)0xDD1A,
- (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x8549, (q15_t)0xDB98,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85BD, (q15_t)0xDA17,
- (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8637, (q15_t)0xD898,
- (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86B5, (q15_t)0xD71A,
- (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8738, (q15_t)0xD59E,
- (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x87BF, (q15_t)0xD423,
- (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x884B, (q15_t)0xD2AA,
- (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88DC, (q15_t)0xD133,
- (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8971, (q15_t)0xCFBE,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A0B, (q15_t)0xCE4A,
- (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8AAA, (q15_t)0xCCD9,
- (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B4D, (q15_t)0xCB69,
- (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BF4, (q15_t)0xC9FB,
- (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CA0, (q15_t)0xC890,
- (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D50, (q15_t)0xC727,
- (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E05, (q15_t)0xC5BF,
- (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8EBE, (q15_t)0xC45A,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F7C, (q15_t)0xC2F8,
- (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x903E, (q15_t)0xC197,
- (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9104, (q15_t)0xC03A,
- (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x91CF, (q15_t)0xBEDE,
- (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x929D, (q15_t)0xBD85,
- (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9370, (q15_t)0xBC2F,
- (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9447, (q15_t)0xBADB,
- (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x9523, (q15_t)0xB98A,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9602, (q15_t)0xB83C,
- (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96E6, (q15_t)0xB6F0,
- (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x97CD, (q15_t)0xB5A7,
- (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x98B9, (q15_t)0xB461,
- (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x99A8, (q15_t)0xB31E,
- (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A9C, (q15_t)0xB1DE,
- (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B93, (q15_t)0xB0A1,
- (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C8E, (q15_t)0xAF68,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D8E, (q15_t)0xAE31,
- (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E90, (q15_t)0xACFD,
- (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F97, (q15_t)0xABCC,
- (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA0A1, (q15_t)0xAA9F,
- (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975,
- (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F,
- (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B,
- (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF,
- (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6,
- (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1,
- (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF,
- (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1,
- (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97,
- (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90,
- (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E,
- (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93,
- (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C,
- (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8,
- (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9,
- (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD,
- (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6,
- (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523,
- (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447,
- (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370,
- (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D,
- (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF,
- (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104,
- (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E,
- (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE,
- (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05,
- (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50,
- (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0,
- (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4,
- (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D,
- (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA,
- (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971,
- (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC,
- (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B,
- (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF,
- (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738,
- (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5,
- (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637,
- (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549,
- (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9,
- (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D,
- (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407,
- (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5,
- (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348,
- (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0,
- (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F,
- (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205,
- (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0,
- (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180,
- (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145,
- (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F,
- (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE,
- (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A,
- (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068,
- (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A,
- (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031,
- (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E,
- (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F,
- (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005,
- (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 2048 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_2048_q15[3072] = {
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064,
- (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D,
- (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6,
- (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF,
- (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388,
- (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451,
- (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A,
- (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3,
- (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC,
- (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775,
- (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D,
- (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906,
- (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE,
- (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97,
- (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F,
- (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF,
- (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7,
- (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F,
- (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47,
- (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E,
- (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6,
- (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D,
- (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264,
- (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B,
- (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2,
- (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8,
- (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F,
- (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645,
- (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A,
- (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0,
- (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B,
- (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20,
- (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4,
- (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9,
- (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D,
- (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31,
- (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5,
- (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8,
- (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B,
- (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E,
- (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100,
- (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2,
- (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284,
- (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345,
- (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407,
- (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588,
- (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648,
- (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707,
- (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7,
- (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886,
- (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944,
- (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02,
- (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0,
- (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D,
- (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A,
- (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7,
- (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3,
- (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E,
- (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29,
- (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4,
- (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158,
- (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211,
- (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA,
- (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382,
- (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A,
- (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2,
- (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8,
- (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F,
- (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714,
- (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA,
- (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E,
- (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932,
- (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6,
- (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99,
- (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C,
- (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD,
- (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF,
- (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60,
- (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10,
- (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF,
- (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E,
- (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D,
- (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA,
- (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177,
- (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224,
- (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0,
- (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B,
- (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425,
- (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BEE, (q15_t)0x44CF,
- (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B81, (q15_t)0x4578,
- (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B13, (q15_t)0x4621,
- (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AA5, (q15_t)0x46C9,
- (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A35, (q15_t)0x4770,
- (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69C4, (q15_t)0x4816,
- (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6953, (q15_t)0x48BC,
- (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68E0, (q15_t)0x4961,
- (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x686C, (q15_t)0x4A06,
- (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x67F7, (q15_t)0x4AA9,
- (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6782, (q15_t)0x4B4C,
- (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x670B, (q15_t)0x4BEF,
- (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6693, (q15_t)0x4C90,
- (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x661A, (q15_t)0x4D31,
- (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65A0, (q15_t)0x4DD1,
- (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6526, (q15_t)0x4E70,
- (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64AA, (q15_t)0x4F0F,
- (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x642D, (q15_t)0x4FAC,
- (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63B0, (q15_t)0x5049,
- (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6331, (q15_t)0x50E5,
- (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62B2, (q15_t)0x5181,
- (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6231, (q15_t)0x521C,
- (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61B0, (q15_t)0x52B5,
- (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x612D, (q15_t)0x534E,
- (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60AA, (q15_t)0x53E7,
- (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6026, (q15_t)0x547E,
- (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FA0, (q15_t)0x5515,
- (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F1A, (q15_t)0x55AB,
- (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E93, (q15_t)0x5640,
- (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E0B, (q15_t)0x56D4,
- (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D83, (q15_t)0x5767,
- (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5CF9, (q15_t)0x57F9,
- (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C6E, (q15_t)0x588B,
- (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5BE3, (q15_t)0x591C,
- (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B56, (q15_t)0x59AC,
- (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AC9, (q15_t)0x5A3B,
- (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A3B, (q15_t)0x5AC9,
- (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59AC, (q15_t)0x5B56,
- (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x591C, (q15_t)0x5BE3,
- (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x588B, (q15_t)0x5C6E,
- (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57F9, (q15_t)0x5CF9,
- (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x5767, (q15_t)0x5D83,
- (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56D4, (q15_t)0x5E0B,
- (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5640, (q15_t)0x5E93,
- (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55AB, (q15_t)0x5F1A,
- (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x5515, (q15_t)0x5FA0,
- (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x547E, (q15_t)0x6026,
- (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x53E7, (q15_t)0x60AA,
- (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x534E, (q15_t)0x612D,
- (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52B5, (q15_t)0x61B0,
- (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x521C, (q15_t)0x6231,
- (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x5181, (q15_t)0x62B2,
- (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x50E5, (q15_t)0x6331,
- (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5049, (q15_t)0x63B0,
- (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FAC, (q15_t)0x642D,
- (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F0F, (q15_t)0x64AA,
- (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E70, (q15_t)0x6526,
- (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DD1, (q15_t)0x65A0,
- (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D31, (q15_t)0x661A,
- (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4C90, (q15_t)0x6693,
- (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4BEF, (q15_t)0x670B,
- (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B4C, (q15_t)0x6782,
- (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AA9, (q15_t)0x67F7,
- (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A06, (q15_t)0x686C,
- (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4961, (q15_t)0x68E0,
- (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48BC, (q15_t)0x6953,
- (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4816, (q15_t)0x69C4,
- (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x4770, (q15_t)0x6A35,
- (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46C9, (q15_t)0x6AA5,
- (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x4621, (q15_t)0x6B13,
- (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4578, (q15_t)0x6B81,
- (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44CF, (q15_t)0x6BEE,
- (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4425, (q15_t)0x6C59,
- (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x437B, (q15_t)0x6CC4,
- (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42D0, (q15_t)0x6D2D,
- (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x4224, (q15_t)0x6D96,
- (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4177, (q15_t)0x6DFD,
- (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40CA, (q15_t)0x6E63,
- (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x401D, (q15_t)0x6EC9,
- (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F6E, (q15_t)0x6F2D,
- (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EBF, (q15_t)0x6F90,
- (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E10, (q15_t)0x6FF2,
- (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D60, (q15_t)0x7053,
- (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CAF, (q15_t)0x70B3,
- (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BFD, (q15_t)0x7112,
- (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B4C, (q15_t)0x716F,
- (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A99, (q15_t)0x71CC,
- (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x39E6, (q15_t)0x7227,
- (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3932, (q15_t)0x7282,
- (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x387E, (q15_t)0x72DB,
- (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37CA, (q15_t)0x7333,
- (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3714, (q15_t)0x738A,
- (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x365F, (q15_t)0x73E0,
- (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35A8, (q15_t)0x7435,
- (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x34F2, (q15_t)0x7489,
- (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x343A, (q15_t)0x74DB,
- (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3382, (q15_t)0x752D,
- (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32CA, (q15_t)0x757D,
- (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3211, (q15_t)0x75CC,
- (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3158, (q15_t)0x761B,
- (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x309E, (q15_t)0x7668,
- (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x2FE4, (q15_t)0x76B3,
- (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F29, (q15_t)0x76FE,
- (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E6E, (q15_t)0x7747,
- (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DB3, (q15_t)0x7790,
- (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2CF7, (q15_t)0x77D7,
- (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C3A, (q15_t)0x781D,
- (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2B7D, (q15_t)0x7862,
- (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AC0, (q15_t)0x78A6,
- (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A02, (q15_t)0x78E8,
- (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2944, (q15_t)0x792A,
- (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x2886, (q15_t)0x796A,
- (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27C7, (q15_t)0x79A9,
- (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2707, (q15_t)0x79E7,
- (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2648, (q15_t)0x7A24,
- (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x2588, (q15_t)0x7A5F,
- (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24C7, (q15_t)0x7A9A,
- (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2407, (q15_t)0x7AD3,
- (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2345, (q15_t)0x7B0B,
- (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x2284, (q15_t)0x7B42,
- (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21C2, (q15_t)0x7B77,
- (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2100, (q15_t)0x7BAC,
- (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x203E, (q15_t)0x7BDF,
- (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1F7B, (q15_t)0x7C11,
- (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EB8, (q15_t)0x7C42,
- (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1DF5, (q15_t)0x7C71,
- (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D31, (q15_t)0x7CA0,
- (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C6D, (q15_t)0x7CCD,
- (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BA9, (q15_t)0x7CF9,
- (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1AE4, (q15_t)0x7D24,
- (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A20, (q15_t)0x7D4E,
- (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x195B, (q15_t)0x7D76,
- (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1896, (q15_t)0x7D9D,
- (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x17D0, (q15_t)0x7DC3,
- (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x170A, (q15_t)0x7DE8,
- (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1645, (q15_t)0x7E0C,
- (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x157F, (q15_t)0x7E2E,
- (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14B8, (q15_t)0x7E4F,
- (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x13F2, (q15_t)0x7E6F,
- (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x132B, (q15_t)0x7E8E,
- (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1264, (q15_t)0x7EAB,
- (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x119D, (q15_t)0x7EC8,
- (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x10D6, (q15_t)0x7EE3,
- (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x100E, (q15_t)0x7EFD,
- (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F47, (q15_t)0x7F15,
- (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0E7F, (q15_t)0x7F2D,
- (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DB7, (q15_t)0x7F43,
- (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0CEF, (q15_t)0x7F58,
- (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C27, (q15_t)0x7F6B,
- (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B5F, (q15_t)0x7F7E,
- (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A97, (q15_t)0x7F8F,
- (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x09CE, (q15_t)0x7F9F,
- (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0906, (q15_t)0x7FAE,
- (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x083D, (q15_t)0x7FBC,
- (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0775, (q15_t)0x7FC8,
- (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06AC, (q15_t)0x7FD3,
- (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x05E3, (q15_t)0x7FDD,
- (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x051A, (q15_t)0x7FE5,
- (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0451, (q15_t)0x7FED,
- (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x0388, (q15_t)0x7FF3,
- (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02BF, (q15_t)0x7FF8,
- (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x01F6, (q15_t)0x7FFC,
- (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x012D, (q15_t)0x7FFE,
- (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF9B, (q15_t)0x7FFF,
- (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFED2, (q15_t)0x7FFE,
- (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE09, (q15_t)0x7FFC,
- (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD40, (q15_t)0x7FF8,
- (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC77, (q15_t)0x7FF3,
- (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBAE, (q15_t)0x7FED,
- (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFAE5, (q15_t)0x7FE5,
- (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA1C, (q15_t)0x7FDD,
- (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF953, (q15_t)0x7FD3,
- (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF88A, (q15_t)0x7FC8,
- (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7C2, (q15_t)0x7FBC,
- (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF6F9, (q15_t)0x7FAE,
- (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF631, (q15_t)0x7F9F,
- (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF568, (q15_t)0x7F8F,
- (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4A0, (q15_t)0x7F7E,
- (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF3D8, (q15_t)0x7F6B,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF310, (q15_t)0x7F58,
- (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF248, (q15_t)0x7F43,
- (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF180, (q15_t)0x7F2D,
- (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0B8, (q15_t)0x7F15,
- (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEFF1, (q15_t)0x7EFD,
- (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF29, (q15_t)0x7EE3,
- (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE62, (q15_t)0x7EC8,
- (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xED9B, (q15_t)0x7EAB,
- (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xECD4, (q15_t)0x7E8E,
- (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC0D, (q15_t)0x7E6F,
- (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB47, (q15_t)0x7E4F,
- (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEA80, (q15_t)0x7E2E,
- (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9BA, (q15_t)0x7E0C,
- (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE8F5, (q15_t)0x7DE8,
- (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE82F, (q15_t)0x7DC3,
- (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE769, (q15_t)0x7D9D,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6A4, (q15_t)0x7D76,
- (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE5DF, (q15_t)0x7D4E,
- (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE51B, (q15_t)0x7D24,
- (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE456, (q15_t)0x7CF9,
- (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE392, (q15_t)0x7CCD,
- (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2CE, (q15_t)0x7CA0,
- (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE20A, (q15_t)0x7C71,
- (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE147, (q15_t)0x7C42,
- (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE084, (q15_t)0x7C11,
- (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFC1, (q15_t)0x7BDF,
- (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDEFF, (q15_t)0x7BAC,
- (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE3D, (q15_t)0x7B77,
- (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD7B, (q15_t)0x7B42,
- (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCBA, (q15_t)0x7B0B,
- (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDBF8, (q15_t)0x7AD3,
- (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB38, (q15_t)0x7A9A,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA77, (q15_t)0x7A5F,
- (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9B7, (q15_t)0x7A24,
- (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD8F8, (q15_t)0x79E7,
- (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD838, (q15_t)0x79A9,
- (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD779, (q15_t)0x796A,
- (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6BB, (q15_t)0x792A,
- (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD5FD, (q15_t)0x78E8,
- (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD53F, (q15_t)0x78A6,
- (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD482, (q15_t)0x7862,
- (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3C5, (q15_t)0x781D,
- (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD308, (q15_t)0x77D7,
- (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD24C, (q15_t)0x7790,
- (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD191, (q15_t)0x7747,
- (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD0D6, (q15_t)0x76FE,
- (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD01B, (q15_t)0x76B3,
- (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF61, (q15_t)0x7668,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCEA7, (q15_t)0x761B,
- (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCDEE, (q15_t)0x75CC,
- (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD35, (q15_t)0x757D,
- (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCC7D, (q15_t)0x752D,
- (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBC5, (q15_t)0x74DB,
- (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB0D, (q15_t)0x7489,
- (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA57, (q15_t)0x7435,
- (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9A0, (q15_t)0x73E0,
- (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC8EB, (q15_t)0x738A,
- (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC835, (q15_t)0x7333,
- (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC781, (q15_t)0x72DB,
- (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6CD, (q15_t)0x7282,
- (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC619, (q15_t)0x7227,
- (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC566, (q15_t)0x71CC,
- (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4B3, (q15_t)0x716F,
- (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC402, (q15_t)0x7112,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC350, (q15_t)0x70B3,
- (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC29F, (q15_t)0x7053,
- (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC1EF, (q15_t)0x6FF2,
- (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC140, (q15_t)0x6F90,
- (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC091, (q15_t)0x6F2D,
- (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xBFE2, (q15_t)0x6EC9,
- (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF35, (q15_t)0x6E63,
- (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBE88, (q15_t)0x6DFD,
- (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBDDB, (q15_t)0x6D96,
- (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD2F, (q15_t)0x6D2D,
- (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC84, (q15_t)0x6CC4,
- (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBBDA, (q15_t)0x6C59,
- (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB30, (q15_t)0x6BEE,
- (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBA87, (q15_t)0x6B81,
- (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB9DE, (q15_t)0x6B13,
- (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB936, (q15_t)0x6AA5,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB88F, (q15_t)0x6A35,
- (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB7E9, (q15_t)0x69C4,
- (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB743, (q15_t)0x6953,
- (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB69E, (q15_t)0x68E0,
- (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5F9, (q15_t)0x686C,
- (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB556, (q15_t)0x67F7,
- (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4B3, (q15_t)0x6782,
- (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB410, (q15_t)0x670B,
- (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB36F, (q15_t)0x6693,
- (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2CE, (q15_t)0x661A,
- (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB22E, (q15_t)0x65A0,
- (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB18F, (q15_t)0x6526,
- (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0F0, (q15_t)0x64AA,
- (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB053, (q15_t)0x642D,
- (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFB6, (q15_t)0x63B0,
- (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF1A, (q15_t)0x6331,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE7E, (q15_t)0x62B2,
- (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xADE3, (q15_t)0x6231,
- (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD4A, (q15_t)0x61B0,
- (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACB1, (q15_t)0x612D,
- (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC18, (q15_t)0x60AA,
- (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xAB81, (q15_t)0x6026,
- (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAAEA, (q15_t)0x5FA0,
- (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA54, (q15_t)0x5F1A,
- (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9BF, (q15_t)0x5E93,
- (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA92B, (q15_t)0x5E0B,
- (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA898, (q15_t)0x5D83,
- (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA806, (q15_t)0x5CF9,
- (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA774, (q15_t)0x5C6E,
- (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA6E3, (q15_t)0x5BE3,
- (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA653, (q15_t)0x5B56,
- (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5C4, (q15_t)0x5AC9,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA536, (q15_t)0x5A3B,
- (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4A9, (q15_t)0x59AC,
- (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA41C, (q15_t)0x591C,
- (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA391, (q15_t)0x588B,
- (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA306, (q15_t)0x57F9,
- (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA27C, (q15_t)0x5767,
- (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1F4, (q15_t)0x56D4,
- (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA16C, (q15_t)0x5640,
- (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0E5, (q15_t)0x55AB,
- (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA05F, (q15_t)0x5515,
- (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FD9, (q15_t)0x547E,
- (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F55, (q15_t)0x53E7,
- (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9ED2, (q15_t)0x534E,
- (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E4F, (q15_t)0x52B5,
- (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DCE, (q15_t)0x521C,
- (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D4D, (q15_t)0x5181,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CCE, (q15_t)0x50E5,
- (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C4F, (q15_t)0x5049,
- (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BD2, (q15_t)0x4FAC,
- (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B55, (q15_t)0x4F0F,
- (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AD9, (q15_t)0x4E70,
- (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A5F, (q15_t)0x4DD1,
- (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99E5, (q15_t)0x4D31,
- (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x996C, (q15_t)0x4C90,
- (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98F4, (q15_t)0x4BEF,
- (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x987D, (q15_t)0x4B4C,
- (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9808, (q15_t)0x4AA9,
- (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x9793, (q15_t)0x4A06,
- (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x971F, (q15_t)0x4961,
- (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96AC, (q15_t)0x48BC,
- (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x963B, (q15_t)0x4816,
- (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95CA, (q15_t)0x4770,
- (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x955A, (q15_t)0x46C9,
- (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x94EC, (q15_t)0x4621,
- (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x947E, (q15_t)0x4578,
- (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x9411, (q15_t)0x44CF,
- (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93A6, (q15_t)0x4425,
- (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x933B, (q15_t)0x437B,
- (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92D2, (q15_t)0x42D0,
- (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9269, (q15_t)0x4224,
- (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9202, (q15_t)0x4177,
- (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x919C, (q15_t)0x40CA,
- (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9136, (q15_t)0x401D,
- (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90D2, (q15_t)0x3F6E,
- (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x906F, (q15_t)0x3EBF,
- (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x900D, (q15_t)0x3E10,
- (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FAC, (q15_t)0x3D60,
- (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F4C, (q15_t)0x3CAF,
- (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EED, (q15_t)0x3BFD,
- (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8E90, (q15_t)0x3B4C,
- (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E33, (q15_t)0x3A99,
- (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DD8, (q15_t)0x39E6,
- (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D7D, (q15_t)0x3932,
- (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D24, (q15_t)0x387E,
- (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CCC, (q15_t)0x37CA,
- (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C75, (q15_t)0x3714,
- (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C1F, (q15_t)0x365F,
- (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BCA, (q15_t)0x35A8,
- (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B76, (q15_t)0x34F2,
- (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B24, (q15_t)0x343A,
- (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AD2, (q15_t)0x3382,
- (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A82, (q15_t)0x32CA,
- (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A33, (q15_t)0x3211,
- (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89E4, (q15_t)0x3158,
- (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8997, (q15_t)0x309E,
- (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x894C, (q15_t)0x2FE4,
- (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8901, (q15_t)0x2F29,
- (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88B8, (q15_t)0x2E6E,
- (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x886F, (q15_t)0x2DB3,
- (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x8828, (q15_t)0x2CF7,
- (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87E2, (q15_t)0x2C3A,
- (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x879D, (q15_t)0x2B7D,
- (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8759, (q15_t)0x2AC0,
- (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8717, (q15_t)0x2A02,
- (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86D5, (q15_t)0x2944,
- (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x8695, (q15_t)0x2886,
- (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8656, (q15_t)0x27C7,
- (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8618, (q15_t)0x2707,
- (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85DB, (q15_t)0x2648,
- (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85A0, (q15_t)0x2588,
- (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8565, (q15_t)0x24C7,
- (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x852C, (q15_t)0x2407,
- (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84F4, (q15_t)0x2345,
- (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84BD, (q15_t)0x2284,
- (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8488, (q15_t)0x21C2,
- (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8453, (q15_t)0x2100,
- (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8420, (q15_t)0x203E,
- (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83EE, (q15_t)0x1F7B,
- (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83BD, (q15_t)0x1EB8,
- (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x838E, (q15_t)0x1DF5,
- (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x835F, (q15_t)0x1D31,
- (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x8332, (q15_t)0x1C6D,
- (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8306, (q15_t)0x1BA9,
- (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82DB, (q15_t)0x1AE4,
- (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82B1, (q15_t)0x1A20,
- (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8289, (q15_t)0x195B,
- (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8262, (q15_t)0x1896,
- (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x823C, (q15_t)0x17D0,
- (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8217, (q15_t)0x170A,
- (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81F3, (q15_t)0x1645,
- (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D1, (q15_t)0x157F,
- (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B0, (q15_t)0x14B8,
- (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8190, (q15_t)0x13F2,
- (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8171, (q15_t)0x132B,
- (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8154, (q15_t)0x1264,
- (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x8137, (q15_t)0x119D,
- (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x811C, (q15_t)0x10D6,
- (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8102, (q15_t)0x100E,
- (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80EA, (q15_t)0x0F47,
- (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D2, (q15_t)0x0E7F,
- (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80BC, (q15_t)0x0DB7,
- (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80A7, (q15_t)0x0CEF,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8094, (q15_t)0x0C27,
- (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8081, (q15_t)0x0B5F,
- (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8070, (q15_t)0x0A97,
- (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8060, (q15_t)0x09CE,
- (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8051, (q15_t)0x0906,
- (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8043, (q15_t)0x083D,
- (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8037, (q15_t)0x0775,
- (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802C, (q15_t)0x06AC,
- (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8022, (q15_t)0x05E3,
- (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801A, (q15_t)0x051A,
- (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8012, (q15_t)0x0451,
- (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800C, (q15_t)0x0388,
- (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8007, (q15_t)0x02BF,
- (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8003, (q15_t)0x01F6,
- (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x012D,
- (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0064,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF9B,
- (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8001, (q15_t)0xFED2,
- (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE09,
- (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8007, (q15_t)0xFD40,
- (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800C, (q15_t)0xFC77,
- (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8012, (q15_t)0xFBAE,
- (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801A, (q15_t)0xFAE5,
- (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8022, (q15_t)0xFA1C,
- (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x802C, (q15_t)0xF953,
- (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8037, (q15_t)0xF88A,
- (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8043, (q15_t)0xF7C2,
- (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x8051, (q15_t)0xF6F9,
- (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8060, (q15_t)0xF631,
- (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x8070, (q15_t)0xF568,
- (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x8081, (q15_t)0xF4A0,
- (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x8094, (q15_t)0xF3D8,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A7, (q15_t)0xF310,
- (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80BC, (q15_t)0xF248,
- (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80D2, (q15_t)0xF180,
- (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80EA, (q15_t)0xF0B8,
- (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x8102, (q15_t)0xEFF1,
- (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x811C, (q15_t)0xEF29,
- (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8137, (q15_t)0xEE62,
- (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x8154, (q15_t)0xED9B,
- (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8171, (q15_t)0xECD4,
- (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8190, (q15_t)0xEC0D,
- (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81B0, (q15_t)0xEB47,
- (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81D1, (q15_t)0xEA80,
- (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81F3, (q15_t)0xE9BA,
- (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x8217, (q15_t)0xE8F5,
- (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x823C, (q15_t)0xE82F,
- (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8262, (q15_t)0xE769,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8289, (q15_t)0xE6A4,
- (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82B1, (q15_t)0xE5DF,
- (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82DB, (q15_t)0xE51B,
- (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x8306, (q15_t)0xE456,
- (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8332, (q15_t)0xE392,
- (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x835F, (q15_t)0xE2CE,
- (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x838E, (q15_t)0xE20A,
- (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83BD, (q15_t)0xE147,
- (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83EE, (q15_t)0xE084,
- (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8420, (q15_t)0xDFC1,
- (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8453, (q15_t)0xDEFF,
- (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x8488, (q15_t)0xDE3D,
- (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84BD, (q15_t)0xDD7B,
- (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84F4, (q15_t)0xDCBA,
- (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x852C, (q15_t)0xDBF8,
- (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8565, (q15_t)0xDB38,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85A0, (q15_t)0xDA77,
- (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85DB, (q15_t)0xD9B7,
- (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8618, (q15_t)0xD8F8,
- (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8656, (q15_t)0xD838,
- (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8695, (q15_t)0xD779,
- (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86D5, (q15_t)0xD6BB,
- (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8717, (q15_t)0xD5FD,
- (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8759, (q15_t)0xD53F,
- (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x879D, (q15_t)0xD482,
- (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87E2, (q15_t)0xD3C5,
- (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8828, (q15_t)0xD308,
- (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x886F, (q15_t)0xD24C,
- (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88B8, (q15_t)0xD191,
- (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x8901, (q15_t)0xD0D6,
- (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x894C, (q15_t)0xD01B,
- (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8997, (q15_t)0xCF61,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89E4, (q15_t)0xCEA7,
- (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A33, (q15_t)0xCDEE,
- (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A82, (q15_t)0xCD35,
- (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8AD2, (q15_t)0xCC7D,
- (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B24, (q15_t)0xCBC5,
- (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B76, (q15_t)0xCB0D,
- (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BCA, (q15_t)0xCA57,
- (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C1F, (q15_t)0xC9A0,
- (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C75, (q15_t)0xC8EB,
- (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CCC, (q15_t)0xC835,
- (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D24, (q15_t)0xC781,
- (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D7D, (q15_t)0xC6CD,
- (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DD8, (q15_t)0xC619,
- (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E33, (q15_t)0xC566,
- (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E90, (q15_t)0xC4B3,
- (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8EED, (q15_t)0xC402,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F4C, (q15_t)0xC350,
- (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8FAC, (q15_t)0xC29F,
- (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x900D, (q15_t)0xC1EF,
- (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x906F, (q15_t)0xC140,
- (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90D2, (q15_t)0xC091,
- (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x9136, (q15_t)0xBFE2,
- (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x919C, (q15_t)0xBF35,
- (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x9202, (q15_t)0xBE88,
- (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9269, (q15_t)0xBDDB,
- (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92D2, (q15_t)0xBD2F,
- (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x933B, (q15_t)0xBC84,
- (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x93A6, (q15_t)0xBBDA,
- (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9411, (q15_t)0xBB30,
- (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x947E, (q15_t)0xBA87,
- (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94EC, (q15_t)0xB9DE,
- (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x955A, (q15_t)0xB936,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95CA, (q15_t)0xB88F,
- (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x963B, (q15_t)0xB7E9,
- (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96AC, (q15_t)0xB743,
- (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x971F, (q15_t)0xB69E,
- (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9793, (q15_t)0xB5F9,
- (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x9808, (q15_t)0xB556,
- (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x987D, (q15_t)0xB4B3,
- (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98F4, (q15_t)0xB410,
- (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x996C, (q15_t)0xB36F,
- (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99E5, (q15_t)0xB2CE,
- (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A5F, (q15_t)0xB22E,
- (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9AD9, (q15_t)0xB18F,
- (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B55, (q15_t)0xB0F0,
- (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BD2, (q15_t)0xB053,
- (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C4F, (q15_t)0xAFB6,
- (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CCE, (q15_t)0xAF1A,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D4D, (q15_t)0xAE7E,
- (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DCE, (q15_t)0xADE3,
- (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E4F, (q15_t)0xAD4A,
- (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9ED2, (q15_t)0xACB1,
- (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F55, (q15_t)0xAC18,
- (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FD9, (q15_t)0xAB81,
- (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA05F, (q15_t)0xAAEA,
- (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0E5, (q15_t)0xAA54,
- (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA16C, (q15_t)0xA9BF,
- (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1F4, (q15_t)0xA92B,
- (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA27C, (q15_t)0xA898,
- (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA306, (q15_t)0xA806,
- (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA391, (q15_t)0xA774,
- (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA41C, (q15_t)0xA6E3,
- (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4A9, (q15_t)0xA653,
- (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA536, (q15_t)0xA5C4,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5C4, (q15_t)0xA536,
- (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA653, (q15_t)0xA4A9,
- (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6E3, (q15_t)0xA41C,
- (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA774, (q15_t)0xA391,
- (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA806, (q15_t)0xA306,
- (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA898, (q15_t)0xA27C,
- (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA92B, (q15_t)0xA1F4,
- (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA9BF, (q15_t)0xA16C,
- (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA54, (q15_t)0xA0E5,
- (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAEA, (q15_t)0xA05F,
- (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB81, (q15_t)0x9FD9,
- (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xAC18, (q15_t)0x9F55,
- (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACB1, (q15_t)0x9ED2,
- (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD4A, (q15_t)0x9E4F,
- (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADE3, (q15_t)0x9DCE,
- (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE7E, (q15_t)0x9D4D,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF1A, (q15_t)0x9CCE,
- (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAFB6, (q15_t)0x9C4F,
- (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB053, (q15_t)0x9BD2,
- (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0F0, (q15_t)0x9B55,
- (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB18F, (q15_t)0x9AD9,
- (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB22E, (q15_t)0x9A5F,
- (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2CE, (q15_t)0x99E5,
- (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB36F, (q15_t)0x996C,
- (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB410, (q15_t)0x98F4,
- (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB4B3, (q15_t)0x987D,
- (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB556, (q15_t)0x9808,
- (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5F9, (q15_t)0x9793,
- (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB69E, (q15_t)0x971F,
- (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB743, (q15_t)0x96AC,
- (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7E9, (q15_t)0x963B,
- (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB88F, (q15_t)0x95CA,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB936, (q15_t)0x955A,
- (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9DE, (q15_t)0x94EC,
- (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA87, (q15_t)0x947E,
- (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB30, (q15_t)0x9411,
- (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBDA, (q15_t)0x93A6,
- (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC84, (q15_t)0x933B,
- (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD2F, (q15_t)0x92D2,
- (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDDB, (q15_t)0x9269,
- (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE88, (q15_t)0x9202,
- (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF35, (q15_t)0x919C,
- (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFE2, (q15_t)0x9136,
- (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC091, (q15_t)0x90D2,
- (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC140, (q15_t)0x906F,
- (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1EF, (q15_t)0x900D,
- (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC29F, (q15_t)0x8FAC,
- (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC350, (q15_t)0x8F4C,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC402, (q15_t)0x8EED,
- (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC4B3, (q15_t)0x8E90,
- (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC566, (q15_t)0x8E33,
- (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC619, (q15_t)0x8DD8,
- (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6CD, (q15_t)0x8D7D,
- (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC781, (q15_t)0x8D24,
- (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC835, (q15_t)0x8CCC,
- (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8EB, (q15_t)0x8C75,
- (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9A0, (q15_t)0x8C1F,
- (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA57, (q15_t)0x8BCA,
- (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB0D, (q15_t)0x8B76,
- (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCBC5, (q15_t)0x8B24,
- (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC7D, (q15_t)0x8AD2,
- (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD35, (q15_t)0x8A82,
- (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDEE, (q15_t)0x8A33,
- (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCEA7, (q15_t)0x89E4,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF61, (q15_t)0x8997,
- (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xD01B, (q15_t)0x894C,
- (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0D6, (q15_t)0x8901,
- (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD191, (q15_t)0x88B8,
- (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD24C, (q15_t)0x886F,
- (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD308, (q15_t)0x8828,
- (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD3C5, (q15_t)0x87E2,
- (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD482, (q15_t)0x879D,
- (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD53F, (q15_t)0x8759,
- (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5FD, (q15_t)0x8717,
- (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD6BB, (q15_t)0x86D5,
- (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD779, (q15_t)0x8695,
- (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD838, (q15_t)0x8656,
- (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8F8, (q15_t)0x8618,
- (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD9B7, (q15_t)0x85DB,
- (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA77, (q15_t)0x85A0,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB38, (q15_t)0x8565,
- (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBF8, (q15_t)0x852C,
- (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDCBA, (q15_t)0x84F4,
- (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD7B, (q15_t)0x84BD,
- (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE3D, (q15_t)0x8488,
- (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDEFF, (q15_t)0x8453,
- (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDFC1, (q15_t)0x8420,
- (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE084, (q15_t)0x83EE,
- (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE147, (q15_t)0x83BD,
- (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE20A, (q15_t)0x838E,
- (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE2CE, (q15_t)0x835F,
- (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE392, (q15_t)0x8332,
- (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306,
- (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB,
- (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1,
- (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262,
- (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C,
- (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217,
- (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3,
- (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1,
- (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0,
- (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190,
- (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171,
- (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154,
- (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137,
- (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C,
- (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102,
- (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA,
- (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2,
- (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC,
- (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094,
- (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081,
- (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070,
- (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060,
- (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051,
- (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043,
- (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037,
- (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C,
- (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022,
- (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A,
- (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012,
- (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C,
- (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007,
- (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003,
- (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001,
- (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000
-};
-
-/**
-* \par
-* Example code for q15 Twiddle factors Generation::
-* \par
-* for(i = 0; i< 3N/4; i++)
-* {
-* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
-* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
-* }
-* \par
-* where N = 4096 and PI = 3.14159265358979
-* \par
-* Cos and Sin values are interleaved fashion
-* \par
-* Convert Floating point to q15(Fixed point 1.15):
-* round(twiddleCoefq15(i) * pow(2, 15))
-*
-*/
-const q15_t twiddleCoef_4096_q15[6144] =
-{
- (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032,
- (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096,
- (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB,
- (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F,
- (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4,
- (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228,
- (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D,
- (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1,
- (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356,
- (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA,
- (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F,
- (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483,
- (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8,
- (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C,
- (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1,
- (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615,
- (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A,
- (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE,
- (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742,
- (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7,
- (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B,
- (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F,
- (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4,
- (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938,
- (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C,
- (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00,
- (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65,
- (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9,
- (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D,
- (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91,
- (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5,
- (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59,
- (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD,
- (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21,
- (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85,
- (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9,
- (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D,
- (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1,
- (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15,
- (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79,
- (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD,
- (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040,
- (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4,
- (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108,
- (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B,
- (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF,
- (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232,
- (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296,
- (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9,
- (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D,
- (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0,
- (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423,
- (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487,
- (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA,
- (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D,
- (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0,
- (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613,
- (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676,
- (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9,
- (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C,
- (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F,
- (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802,
- (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864,
- (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7,
- (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A,
- (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C,
- (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF,
- (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51,
- (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3,
- (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16,
- (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78,
- (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA,
- (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C,
- (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E,
- (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00,
- (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62,
- (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4,
- (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25,
- (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87,
- (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9,
- (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A,
- (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC,
- (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D,
- (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E,
- (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0,
- (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131,
- (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192,
- (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3,
- (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254,
- (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4,
- (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315,
- (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376,
- (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AE1, (q15_t)0x23D6,
- (q15_t)0x7AD3, (q15_t)0x2407, (q15_t)0x7AC5, (q15_t)0x2437,
- (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7AA8, (q15_t)0x2497,
- (q15_t)0x7A9A, (q15_t)0x24C7, (q15_t)0x7A8B, (q15_t)0x24F7,
- (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A6E, (q15_t)0x2558,
- (q15_t)0x7A5F, (q15_t)0x2588, (q15_t)0x7A50, (q15_t)0x25B8,
- (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A33, (q15_t)0x2618,
- (q15_t)0x7A24, (q15_t)0x2648, (q15_t)0x7A15, (q15_t)0x2678,
- (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79F6, (q15_t)0x26D8,
- (q15_t)0x79E7, (q15_t)0x2707, (q15_t)0x79D8, (q15_t)0x2737,
- (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79B9, (q15_t)0x2797,
- (q15_t)0x79A9, (q15_t)0x27C7, (q15_t)0x7999, (q15_t)0x27F6,
- (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x797A, (q15_t)0x2856,
- (q15_t)0x796A, (q15_t)0x2886, (q15_t)0x795A, (q15_t)0x28B5,
- (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x793A, (q15_t)0x2915,
- (q15_t)0x792A, (q15_t)0x2944, (q15_t)0x7919, (q15_t)0x2974,
- (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78F9, (q15_t)0x29D3,
- (q15_t)0x78E8, (q15_t)0x2A02, (q15_t)0x78D8, (q15_t)0x2A32,
- (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78B6, (q15_t)0x2A91,
- (q15_t)0x78A6, (q15_t)0x2AC0, (q15_t)0x7895, (q15_t)0x2AEF,
- (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7873, (q15_t)0x2B4E,
- (q15_t)0x7862, (q15_t)0x2B7D, (q15_t)0x7851, (q15_t)0x2BAD,
- (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x782E, (q15_t)0x2C0B,
- (q15_t)0x781D, (q15_t)0x2C3A, (q15_t)0x780C, (q15_t)0x2C69,
- (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77E9, (q15_t)0x2CC8,
- (q15_t)0x77D7, (q15_t)0x2CF7, (q15_t)0x77C5, (q15_t)0x2D26,
- (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x77A2, (q15_t)0x2D84,
- (q15_t)0x7790, (q15_t)0x2DB3, (q15_t)0x777E, (q15_t)0x2DE2,
- (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x775A, (q15_t)0x2E3F,
- (q15_t)0x7747, (q15_t)0x2E6E, (q15_t)0x7735, (q15_t)0x2E9D,
- (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x7710, (q15_t)0x2EFB,
- (q15_t)0x76FE, (q15_t)0x2F29, (q15_t)0x76EB, (q15_t)0x2F58,
- (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76C6, (q15_t)0x2FB5,
- (q15_t)0x76B3, (q15_t)0x2FE4, (q15_t)0x76A0, (q15_t)0x3013,
- (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x767B, (q15_t)0x3070,
- (q15_t)0x7668, (q15_t)0x309E, (q15_t)0x7654, (q15_t)0x30CD,
- (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x762E, (q15_t)0x312A,
- (q15_t)0x761B, (q15_t)0x3158, (q15_t)0x7607, (q15_t)0x3186,
- (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75E0, (q15_t)0x31E3,
- (q15_t)0x75CC, (q15_t)0x3211, (q15_t)0x75B9, (q15_t)0x3240,
- (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7591, (q15_t)0x329C,
- (q15_t)0x757D, (q15_t)0x32CA, (q15_t)0x7569, (q15_t)0x32F8,
- (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x7541, (q15_t)0x3354,
- (q15_t)0x752D, (q15_t)0x3382, (q15_t)0x7519, (q15_t)0x33B0,
- (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74F0, (q15_t)0x340C,
- (q15_t)0x74DB, (q15_t)0x343A, (q15_t)0x74C7, (q15_t)0x3468,
- (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x749E, (q15_t)0x34C4,
- (q15_t)0x7489, (q15_t)0x34F2, (q15_t)0x7474, (q15_t)0x351F,
- (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x744A, (q15_t)0x357B,
- (q15_t)0x7435, (q15_t)0x35A8, (q15_t)0x7420, (q15_t)0x35D6,
- (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73F6, (q15_t)0x3631,
- (q15_t)0x73E0, (q15_t)0x365F, (q15_t)0x73CB, (q15_t)0x368C,
- (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x73A0, (q15_t)0x36E7,
- (q15_t)0x738A, (q15_t)0x3714, (q15_t)0x7375, (q15_t)0x3742,
- (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7349, (q15_t)0x379C,
- (q15_t)0x7333, (q15_t)0x37CA, (q15_t)0x731D, (q15_t)0x37F7,
- (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72F1, (q15_t)0x3851,
- (q15_t)0x72DB, (q15_t)0x387E, (q15_t)0x72C5, (q15_t)0x38AB,
- (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7298, (q15_t)0x3906,
- (q15_t)0x7282, (q15_t)0x3932, (q15_t)0x726B, (q15_t)0x395F,
- (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x723E, (q15_t)0x39B9,
- (q15_t)0x7227, (q15_t)0x39E6, (q15_t)0x7211, (q15_t)0x3A13,
- (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71E3, (q15_t)0x3A6C,
- (q15_t)0x71CC, (q15_t)0x3A99, (q15_t)0x71B5, (q15_t)0x3AC6,
- (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7186, (q15_t)0x3B1F,
- (q15_t)0x716F, (q15_t)0x3B4C, (q15_t)0x7158, (q15_t)0x3B78,
- (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7129, (q15_t)0x3BD1,
- (q15_t)0x7112, (q15_t)0x3BFD, (q15_t)0x70FA, (q15_t)0x3C2A,
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- (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B91, (q15_t)0x7F79,
- (q15_t)0x0B5F, (q15_t)0x7F7E, (q15_t)0x0B2D, (q15_t)0x7F82,
- (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0AC9, (q15_t)0x7F8B,
- (q15_t)0x0A97, (q15_t)0x7F8F, (q15_t)0x0A65, (q15_t)0x7F93,
- (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x0A00, (q15_t)0x7F9B,
- (q15_t)0x09CE, (q15_t)0x7F9F, (q15_t)0x099C, (q15_t)0x7FA3,
- (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0938, (q15_t)0x7FAA,
- (q15_t)0x0906, (q15_t)0x7FAE, (q15_t)0x08D4, (q15_t)0x7FB1,
- (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x086F, (q15_t)0x7FB8,
- (q15_t)0x083D, (q15_t)0x7FBC, (q15_t)0x080B, (q15_t)0x7FBF,
- (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x07A7, (q15_t)0x7FC5,
- (q15_t)0x0775, (q15_t)0x7FC8, (q15_t)0x0742, (q15_t)0x7FCB,
- (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06DE, (q15_t)0x7FD0,
- (q15_t)0x06AC, (q15_t)0x7FD3, (q15_t)0x067A, (q15_t)0x7FD6,
- (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0615, (q15_t)0x7FDA,
- (q15_t)0x05E3, (q15_t)0x7FDD, (q15_t)0x05B1, (q15_t)0x7FDF,
- (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x054C, (q15_t)0x7FE3,
- (q15_t)0x051A, (q15_t)0x7FE5, (q15_t)0x04E8, (q15_t)0x7FE7,
- (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0483, (q15_t)0x7FEB,
- (q15_t)0x0451, (q15_t)0x7FED, (q15_t)0x041F, (q15_t)0x7FEE,
- (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x03BA, (q15_t)0x7FF2,
- (q15_t)0x0388, (q15_t)0x7FF3, (q15_t)0x0356, (q15_t)0x7FF4,
- (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02F1, (q15_t)0x7FF7,
- (q15_t)0x02BF, (q15_t)0x7FF8, (q15_t)0x028D, (q15_t)0x7FF9,
- (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x0228, (q15_t)0x7FFB,
- (q15_t)0x01F6, (q15_t)0x7FFC, (q15_t)0x01C4, (q15_t)0x7FFC,
- (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x015F, (q15_t)0x7FFE,
- (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x00FB, (q15_t)0x7FFF,
- (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0096, (q15_t)0x7FFF,
- (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0032, (q15_t)0x7FFF,
- (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFFCD, (q15_t)0x7FFF,
- (q15_t)0xFF9B, (q15_t)0x7FFF, (q15_t)0xFF69, (q15_t)0x7FFF,
- (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFF04, (q15_t)0x7FFF,
- (q15_t)0xFED2, (q15_t)0x7FFE, (q15_t)0xFEA0, (q15_t)0x7FFE,
- (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE3B, (q15_t)0x7FFC,
- (q15_t)0xFE09, (q15_t)0x7FFC, (q15_t)0xFDD7, (q15_t)0x7FFB,
- (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD72, (q15_t)0x7FF9,
- (q15_t)0xFD40, (q15_t)0x7FF8, (q15_t)0xFD0E, (q15_t)0x7FF7,
- (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFCA9, (q15_t)0x7FF4,
- (q15_t)0xFC77, (q15_t)0x7FF3, (q15_t)0xFC45, (q15_t)0x7FF2,
- (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBE0, (q15_t)0x7FEE,
- (q15_t)0xFBAE, (q15_t)0x7FED, (q15_t)0xFB7C, (q15_t)0x7FEB,
- (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFB17, (q15_t)0x7FE7,
- (q15_t)0xFAE5, (q15_t)0x7FE5, (q15_t)0xFAB3, (q15_t)0x7FE3,
- (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA4E, (q15_t)0x7FDF,
- (q15_t)0xFA1C, (q15_t)0x7FDD, (q15_t)0xF9EA, (q15_t)0x7FDA,
- (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF985, (q15_t)0x7FD6,
- (q15_t)0xF953, (q15_t)0x7FD3, (q15_t)0xF921, (q15_t)0x7FD0,
- (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF8BD, (q15_t)0x7FCB,
- (q15_t)0xF88A, (q15_t)0x7FC8, (q15_t)0xF858, (q15_t)0x7FC5,
- (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7F4, (q15_t)0x7FBF,
- (q15_t)0xF7C2, (q15_t)0x7FBC, (q15_t)0xF790, (q15_t)0x7FB8,
- (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF72B, (q15_t)0x7FB1,
- (q15_t)0xF6F9, (q15_t)0x7FAE, (q15_t)0xF6C7, (q15_t)0x7FAA,
- (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF663, (q15_t)0x7FA3,
- (q15_t)0xF631, (q15_t)0x7F9F, (q15_t)0xF5FF, (q15_t)0x7F9B,
- (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF59A, (q15_t)0x7F93,
- (q15_t)0xF568, (q15_t)0x7F8F, (q15_t)0xF536, (q15_t)0x7F8B,
- (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4D2, (q15_t)0x7F82,
- (q15_t)0xF4A0, (q15_t)0x7F7E, (q15_t)0xF46E, (q15_t)0x7F79,
- (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF40A, (q15_t)0x7F70,
- (q15_t)0xF3D8, (q15_t)0x7F6B, (q15_t)0xF3A6, (q15_t)0x7F67,
- (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF342, (q15_t)0x7F5D,
- (q15_t)0xF310, (q15_t)0x7F58, (q15_t)0xF2DE, (q15_t)0x7F53,
- (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF27A, (q15_t)0x7F48,
- (q15_t)0xF248, (q15_t)0x7F43, (q15_t)0xF216, (q15_t)0x7F3D,
- (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF1B2, (q15_t)0x7F32,
- (q15_t)0xF180, (q15_t)0x7F2D, (q15_t)0xF14E, (q15_t)0x7F27,
- (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0EA, (q15_t)0x7F1B,
- (q15_t)0xF0B8, (q15_t)0x7F15, (q15_t)0xF086, (q15_t)0x7F0F,
- (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xF022, (q15_t)0x7F03,
- (q15_t)0xEFF1, (q15_t)0x7EFD, (q15_t)0xEFBF, (q15_t)0x7EF6,
- (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF5B, (q15_t)0x7EE9,
- (q15_t)0xEF29, (q15_t)0x7EE3, (q15_t)0xEEF7, (q15_t)0x7EDC,
- (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE94, (q15_t)0x7ECF,
- (q15_t)0xEE62, (q15_t)0x7EC8, (q15_t)0xEE30, (q15_t)0x7EC1,
- (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xEDCD, (q15_t)0x7EB3,
- (q15_t)0xED9B, (q15_t)0x7EAB, (q15_t)0xED69, (q15_t)0x7EA4,
- (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xED06, (q15_t)0x7E95,
- (q15_t)0xECD4, (q15_t)0x7E8E, (q15_t)0xECA2, (q15_t)0x7E86,
- (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC3F, (q15_t)0x7E77,
- (q15_t)0xEC0D, (q15_t)0x7E6F, (q15_t)0xEBDC, (q15_t)0x7E67,
- (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB78, (q15_t)0x7E57,
- (q15_t)0xEB47, (q15_t)0x7E4F, (q15_t)0xEB15, (q15_t)0x7E47,
- (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEAB2, (q15_t)0x7E37,
- (q15_t)0xEA80, (q15_t)0x7E2E, (q15_t)0xEA4F, (q15_t)0x7E26,
- (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9EC, (q15_t)0x7E14,
- (q15_t)0xE9BA, (q15_t)0x7E0C, (q15_t)0xE989, (q15_t)0x7E03,
- (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE926, (q15_t)0x7DF1,
- (q15_t)0xE8F5, (q15_t)0x7DE8, (q15_t)0xE8C3, (q15_t)0x7DDF,
- (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE860, (q15_t)0x7DCD,
- (q15_t)0xE82F, (q15_t)0x7DC3, (q15_t)0xE7FD, (q15_t)0x7DBA,
- (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE79B, (q15_t)0x7DA7,
- (q15_t)0xE769, (q15_t)0x7D9D, (q15_t)0xE738, (q15_t)0x7D94,
- (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6D5, (q15_t)0x7D80,
- (q15_t)0xE6A4, (q15_t)0x7D76, (q15_t)0xE673, (q15_t)0x7D6C,
- (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE610, (q15_t)0x7D58,
- (q15_t)0xE5DF, (q15_t)0x7D4E, (q15_t)0xE5AE, (q15_t)0x7D43,
- (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE54C, (q15_t)0x7D2F,
- (q15_t)0xE51B, (q15_t)0x7D24, (q15_t)0xE4E9, (q15_t)0x7D19,
- (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE487, (q15_t)0x7D04,
- (q15_t)0xE456, (q15_t)0x7CF9, (q15_t)0xE425, (q15_t)0x7CEE,
- (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE3C3, (q15_t)0x7CD8,
- (q15_t)0xE392, (q15_t)0x7CCD, (q15_t)0xE361, (q15_t)0x7CC2,
- (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2FF, (q15_t)0x7CAB,
- (q15_t)0xE2CE, (q15_t)0x7CA0, (q15_t)0xE29D, (q15_t)0x7C94,
- (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE23B, (q15_t)0x7C7D,
- (q15_t)0xE20A, (q15_t)0x7C71, (q15_t)0xE1DA, (q15_t)0x7C66,
- (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE178, (q15_t)0x7C4E,
- (q15_t)0xE147, (q15_t)0x7C42, (q15_t)0xE116, (q15_t)0x7C36,
- (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE0B5, (q15_t)0x7C1D,
- (q15_t)0xE084, (q15_t)0x7C11, (q15_t)0xE053, (q15_t)0x7C05,
- (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFF2, (q15_t)0x7BEB,
- (q15_t)0xDFC1, (q15_t)0x7BDF, (q15_t)0xDF91, (q15_t)0x7BD2,
- (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDF2F, (q15_t)0x7BB9,
- (q15_t)0xDEFF, (q15_t)0x7BAC, (q15_t)0xDECE, (q15_t)0x7B9F,
- (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE6D, (q15_t)0x7B84,
- (q15_t)0xDE3D, (q15_t)0x7B77, (q15_t)0xDE0C, (q15_t)0x7B6A,
- (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDDAB, (q15_t)0x7B4F,
- (q15_t)0xDD7B, (q15_t)0x7B42, (q15_t)0xDD4B, (q15_t)0x7B34,
- (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCEA, (q15_t)0x7B19,
- (q15_t)0xDCBA, (q15_t)0x7B0B, (q15_t)0xDC89, (q15_t)0x7AFD,
- (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDC29, (q15_t)0x7AE1,
- (q15_t)0xDBF8, (q15_t)0x7AD3, (q15_t)0xDBC8, (q15_t)0x7AC5,
- (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB68, (q15_t)0x7AA8,
- (q15_t)0xDB38, (q15_t)0x7A9A, (q15_t)0xDB08, (q15_t)0x7A8B,
- (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDAA7, (q15_t)0x7A6E,
- (q15_t)0xDA77, (q15_t)0x7A5F, (q15_t)0xDA47, (q15_t)0x7A50,
- (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9E7, (q15_t)0x7A33,
- (q15_t)0xD9B7, (q15_t)0x7A24, (q15_t)0xD987, (q15_t)0x7A15,
- (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD927, (q15_t)0x79F6,
- (q15_t)0xD8F8, (q15_t)0x79E7, (q15_t)0xD8C8, (q15_t)0x79D8,
- (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD868, (q15_t)0x79B9,
- (q15_t)0xD838, (q15_t)0x79A9, (q15_t)0xD809, (q15_t)0x7999,
- (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD7A9, (q15_t)0x797A,
- (q15_t)0xD779, (q15_t)0x796A, (q15_t)0xD74A, (q15_t)0x795A,
- (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6EA, (q15_t)0x793A,
- (q15_t)0xD6BB, (q15_t)0x792A, (q15_t)0xD68B, (q15_t)0x7919,
- (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD62C, (q15_t)0x78F9,
- (q15_t)0xD5FD, (q15_t)0x78E8, (q15_t)0xD5CD, (q15_t)0x78D8,
- (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD56E, (q15_t)0x78B6,
- (q15_t)0xD53F, (q15_t)0x78A6, (q15_t)0xD510, (q15_t)0x7895,
- (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD4B1, (q15_t)0x7873,
- (q15_t)0xD482, (q15_t)0x7862, (q15_t)0xD452, (q15_t)0x7851,
- (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3F4, (q15_t)0x782E,
- (q15_t)0xD3C5, (q15_t)0x781D, (q15_t)0xD396, (q15_t)0x780C,
- (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD337, (q15_t)0x77E9,
- (q15_t)0xD308, (q15_t)0x77D7, (q15_t)0xD2D9, (q15_t)0x77C5,
- (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD27B, (q15_t)0x77A2,
- (q15_t)0xD24C, (q15_t)0x7790, (q15_t)0xD21D, (q15_t)0x777E,
- (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD1C0, (q15_t)0x775A,
- (q15_t)0xD191, (q15_t)0x7747, (q15_t)0xD162, (q15_t)0x7735,
- (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD104, (q15_t)0x7710,
- (q15_t)0xD0D6, (q15_t)0x76FE, (q15_t)0xD0A7, (q15_t)0x76EB,
- (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD04A, (q15_t)0x76C6,
- (q15_t)0xD01B, (q15_t)0x76B3, (q15_t)0xCFEC, (q15_t)0x76A0,
- (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF8F, (q15_t)0x767B,
- (q15_t)0xCF61, (q15_t)0x7668, (q15_t)0xCF32, (q15_t)0x7654,
- (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCED5, (q15_t)0x762E,
- (q15_t)0xCEA7, (q15_t)0x761B, (q15_t)0xCE79, (q15_t)0x7607,
- (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCE1C, (q15_t)0x75E0,
- (q15_t)0xCDEE, (q15_t)0x75CC, (q15_t)0xCDBF, (q15_t)0x75B9,
- (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD63, (q15_t)0x7591,
- (q15_t)0xCD35, (q15_t)0x757D, (q15_t)0xCD07, (q15_t)0x7569,
- (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCCAB, (q15_t)0x7541,
- (q15_t)0xCC7D, (q15_t)0x752D, (q15_t)0xCC4F, (q15_t)0x7519,
- (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBF3, (q15_t)0x74F0,
- (q15_t)0xCBC5, (q15_t)0x74DB, (q15_t)0xCB97, (q15_t)0x74C7,
- (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB3B, (q15_t)0x749E,
- (q15_t)0xCB0D, (q15_t)0x7489, (q15_t)0xCAE0, (q15_t)0x7474,
- (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA84, (q15_t)0x744A,
- (q15_t)0xCA57, (q15_t)0x7435, (q15_t)0xCA29, (q15_t)0x7420,
- (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9CE, (q15_t)0x73F6,
- (q15_t)0xC9A0, (q15_t)0x73E0, (q15_t)0xC973, (q15_t)0x73CB,
- (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC918, (q15_t)0x73A0,
- (q15_t)0xC8EB, (q15_t)0x738A, (q15_t)0xC8BD, (q15_t)0x7375,
- (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC863, (q15_t)0x7349,
- (q15_t)0xC835, (q15_t)0x7333, (q15_t)0xC808, (q15_t)0x731D,
- (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC7AE, (q15_t)0x72F1,
- (q15_t)0xC781, (q15_t)0x72DB, (q15_t)0xC754, (q15_t)0x72C5,
- (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6F9, (q15_t)0x7298,
- (q15_t)0xC6CD, (q15_t)0x7282, (q15_t)0xC6A0, (q15_t)0x726B,
- (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC646, (q15_t)0x723E,
- (q15_t)0xC619, (q15_t)0x7227, (q15_t)0xC5EC, (q15_t)0x7211,
- (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC593, (q15_t)0x71E3,
- (q15_t)0xC566, (q15_t)0x71CC, (q15_t)0xC539, (q15_t)0x71B5,
- (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4E0, (q15_t)0x7186,
- (q15_t)0xC4B3, (q15_t)0x716F, (q15_t)0xC487, (q15_t)0x7158,
- (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC42E, (q15_t)0x7129,
- (q15_t)0xC402, (q15_t)0x7112, (q15_t)0xC3D5, (q15_t)0x70FA,
- (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC37C, (q15_t)0x70CB,
- (q15_t)0xC350, (q15_t)0x70B3, (q15_t)0xC324, (q15_t)0x709B,
- (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC2CC, (q15_t)0x706B,
- (q15_t)0xC29F, (q15_t)0x7053, (q15_t)0xC273, (q15_t)0x703B,
- (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC21B, (q15_t)0x700A,
- (q15_t)0xC1EF, (q15_t)0x6FF2, (q15_t)0xC1C3, (q15_t)0x6FDA,
- (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC16C, (q15_t)0x6FA9,
- (q15_t)0xC140, (q15_t)0x6F90, (q15_t)0xC114, (q15_t)0x6F77,
- (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC0BC, (q15_t)0x6F46,
- (q15_t)0xC091, (q15_t)0x6F2D, (q15_t)0xC065, (q15_t)0x6F14,
- (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xC00E, (q15_t)0x6EE2,
- (q15_t)0xBFE2, (q15_t)0x6EC9, (q15_t)0xBFB7, (q15_t)0x6EAF,
- (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF60, (q15_t)0x6E7D,
- (q15_t)0xBF35, (q15_t)0x6E63, (q15_t)0xBF09, (q15_t)0x6E4A,
- (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBEB3, (q15_t)0x6E17,
- (q15_t)0xBE88, (q15_t)0x6DFD, (q15_t)0xBE5D, (q15_t)0x6DE3,
- (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBE06, (q15_t)0x6DB0,
- (q15_t)0xBDDB, (q15_t)0x6D96, (q15_t)0xBDB0, (q15_t)0x6D7C,
- (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD5A, (q15_t)0x6D48,
- (q15_t)0xBD2F, (q15_t)0x6D2D, (q15_t)0xBD05, (q15_t)0x6D13,
- (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBCAF, (q15_t)0x6CDE,
- (q15_t)0xBC84, (q15_t)0x6CC4, (q15_t)0xBC5A, (q15_t)0x6CA9,
- (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBC04, (q15_t)0x6C74,
- (q15_t)0xBBDA, (q15_t)0x6C59, (q15_t)0xBBAF, (q15_t)0x6C3F,
- (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB5A, (q15_t)0x6C09,
- (q15_t)0xBB30, (q15_t)0x6BEE, (q15_t)0xBB05, (q15_t)0x6BD3,
- (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBAB1, (q15_t)0x6B9C,
- (q15_t)0xBA87, (q15_t)0x6B81, (q15_t)0xBA5C, (q15_t)0x6B66,
- (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xBA08, (q15_t)0x6B2F,
- (q15_t)0xB9DE, (q15_t)0x6B13, (q15_t)0xB9B4, (q15_t)0x6AF8,
- (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB960, (q15_t)0x6AC1,
- (q15_t)0xB936, (q15_t)0x6AA5, (q15_t)0xB90C, (q15_t)0x6A89,
- (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB8B9, (q15_t)0x6A51,
- (q15_t)0xB88F, (q15_t)0x6A35, (q15_t)0xB865, (q15_t)0x6A19,
- (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB812, (q15_t)0x69E1,
- (q15_t)0xB7E9, (q15_t)0x69C4, (q15_t)0xB7BF, (q15_t)0x69A8,
- (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB76C, (q15_t)0x696F,
- (q15_t)0xB743, (q15_t)0x6953, (q15_t)0xB719, (q15_t)0x6936,
- (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB6C7, (q15_t)0x68FD,
- (q15_t)0xB69E, (q15_t)0x68E0, (q15_t)0xB675, (q15_t)0x68C3,
- (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB622, (q15_t)0x6889,
- (q15_t)0xB5F9, (q15_t)0x686C, (q15_t)0xB5D0, (q15_t)0x684F,
- (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB57E, (q15_t)0x6815,
- (q15_t)0xB556, (q15_t)0x67F7, (q15_t)0xB52D, (q15_t)0x67DA,
- (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4DB, (q15_t)0x679F,
- (q15_t)0xB4B3, (q15_t)0x6782, (q15_t)0xB48A, (q15_t)0x6764,
- (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB439, (q15_t)0x6729,
- (q15_t)0xB410, (q15_t)0x670B, (q15_t)0xB3E8, (q15_t)0x66ED,
- (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB397, (q15_t)0x66B1,
- (q15_t)0xB36F, (q15_t)0x6693, (q15_t)0xB347, (q15_t)0x6675,
- (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2F6, (q15_t)0x6639,
- (q15_t)0xB2CE, (q15_t)0x661A, (q15_t)0xB2A6, (q15_t)0x65FC,
- (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB256, (q15_t)0x65BF,
- (q15_t)0xB22E, (q15_t)0x65A0, (q15_t)0xB206, (q15_t)0x6582,
- (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB1B7, (q15_t)0x6545,
- (q15_t)0xB18F, (q15_t)0x6526, (q15_t)0xB167, (q15_t)0x6507,
- (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB118, (q15_t)0x64C9,
- (q15_t)0xB0F0, (q15_t)0x64AA, (q15_t)0xB0C9, (q15_t)0x648B,
- (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB07A, (q15_t)0x644D,
- (q15_t)0xB053, (q15_t)0x642D, (q15_t)0xB02B, (q15_t)0x640E,
- (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFDD, (q15_t)0x63CF,
- (q15_t)0xAFB6, (q15_t)0x63B0, (q15_t)0xAF8F, (q15_t)0x6390,
- (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF40, (q15_t)0x6351,
- (q15_t)0xAF1A, (q15_t)0x6331, (q15_t)0xAEF3, (q15_t)0x6311,
- (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAEA5, (q15_t)0x62D2,
- (q15_t)0xAE7E, (q15_t)0x62B2, (q15_t)0xAE57, (q15_t)0x6292,
- (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xAE0A, (q15_t)0x6251,
- (q15_t)0xADE3, (q15_t)0x6231, (q15_t)0xADBD, (q15_t)0x6211,
- (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD70, (q15_t)0x61D0,
- (q15_t)0xAD4A, (q15_t)0x61B0, (q15_t)0xAD23, (q15_t)0x618F,
- (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACD7, (q15_t)0x614E,
- (q15_t)0xACB1, (q15_t)0x612D, (q15_t)0xAC8A, (q15_t)0x610D,
- (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC3E, (q15_t)0x60CB,
- (q15_t)0xAC18, (q15_t)0x60AA, (q15_t)0xABF2, (q15_t)0x6089,
- (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xABA7, (q15_t)0x6047,
- (q15_t)0xAB81, (q15_t)0x6026, (q15_t)0xAB5B, (q15_t)0x6004,
- (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAB10, (q15_t)0x5FC2,
- (q15_t)0xAAEA, (q15_t)0x5FA0, (q15_t)0xAAC5, (q15_t)0x5F7F,
- (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA7A, (q15_t)0x5F3C,
- (q15_t)0xAA54, (q15_t)0x5F1A, (q15_t)0xAA2F, (q15_t)0x5EF9,
- (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9E5, (q15_t)0x5EB5,
- (q15_t)0xA9BF, (q15_t)0x5E93, (q15_t)0xA99A, (q15_t)0x5E71,
- (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA950, (q15_t)0x5E2D,
- (q15_t)0xA92B, (q15_t)0x5E0B, (q15_t)0xA906, (q15_t)0x5DE9,
- (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA8BD, (q15_t)0x5DA5,
- (q15_t)0xA898, (q15_t)0x5D83, (q15_t)0xA873, (q15_t)0x5D60,
- (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA82A, (q15_t)0x5D1B,
- (q15_t)0xA806, (q15_t)0x5CF9, (q15_t)0xA7E1, (q15_t)0x5CD6,
- (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA798, (q15_t)0x5C91,
- (q15_t)0xA774, (q15_t)0x5C6E, (q15_t)0xA750, (q15_t)0x5C4B,
- (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA707, (q15_t)0x5C06,
- (q15_t)0xA6E3, (q15_t)0x5BE3, (q15_t)0xA6BF, (q15_t)0x5BC0,
- (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA677, (q15_t)0x5B79,
- (q15_t)0xA653, (q15_t)0x5B56, (q15_t)0xA62F, (q15_t)0x5B33,
- (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5E8, (q15_t)0x5AEC,
- (q15_t)0xA5C4, (q15_t)0x5AC9, (q15_t)0xA5A1, (q15_t)0x5AA5,
- (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA55A, (q15_t)0x5A5E,
- (q15_t)0xA536, (q15_t)0x5A3B, (q15_t)0xA513, (q15_t)0x5A17,
- (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4CC, (q15_t)0x59D0,
- (q15_t)0xA4A9, (q15_t)0x59AC, (q15_t)0xA486, (q15_t)0x5988,
- (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA43F, (q15_t)0x5940,
- (q15_t)0xA41C, (q15_t)0x591C, (q15_t)0xA3F9, (q15_t)0x58F8,
- (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA3B4, (q15_t)0x58AF,
- (q15_t)0xA391, (q15_t)0x588B, (q15_t)0xA36E, (q15_t)0x5867,
- (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA329, (q15_t)0x581E,
- (q15_t)0xA306, (q15_t)0x57F9, (q15_t)0xA2E4, (q15_t)0x57D5,
- (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA29F, (q15_t)0x578C,
- (q15_t)0xA27C, (q15_t)0x5767, (q15_t)0xA25A, (q15_t)0x5742,
- (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA216, (q15_t)0x56F9,
- (q15_t)0xA1F4, (q15_t)0x56D4, (q15_t)0xA1D2, (q15_t)0x56AF,
- (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA18E, (q15_t)0x5665,
- (q15_t)0xA16C, (q15_t)0x5640, (q15_t)0xA14A, (q15_t)0x561A,
- (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA106, (q15_t)0x55D0,
- (q15_t)0xA0E5, (q15_t)0x55AB, (q15_t)0xA0C3, (q15_t)0x5585,
- (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA080, (q15_t)0x553A,
- (q15_t)0xA05F, (q15_t)0x5515, (q15_t)0xA03D, (q15_t)0x54EF,
- (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FFB, (q15_t)0x54A4,
- (q15_t)0x9FD9, (q15_t)0x547E, (q15_t)0x9FB8, (q15_t)0x5458,
- (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F76, (q15_t)0x540D,
- (q15_t)0x9F55, (q15_t)0x53E7, (q15_t)0x9F34, (q15_t)0x53C1,
- (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9EF2, (q15_t)0x5375,
- (q15_t)0x9ED2, (q15_t)0x534E, (q15_t)0x9EB1, (q15_t)0x5328,
- (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E70, (q15_t)0x52DC,
- (q15_t)0x9E4F, (q15_t)0x52B5, (q15_t)0x9E2F, (q15_t)0x528F,
- (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DEE, (q15_t)0x5242,
- (q15_t)0x9DCE, (q15_t)0x521C, (q15_t)0x9DAE, (q15_t)0x51F5,
- (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D6D, (q15_t)0x51A8,
- (q15_t)0x9D4D, (q15_t)0x5181, (q15_t)0x9D2D, (q15_t)0x515A,
- (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CEE, (q15_t)0x510C,
- (q15_t)0x9CCE, (q15_t)0x50E5, (q15_t)0x9CAE, (q15_t)0x50BF,
- (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C6F, (q15_t)0x5070,
- (q15_t)0x9C4F, (q15_t)0x5049, (q15_t)0x9C30, (q15_t)0x5022,
- (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BF1, (q15_t)0x4FD4,
- (q15_t)0x9BD2, (q15_t)0x4FAC, (q15_t)0x9BB2, (q15_t)0x4F85,
- (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B74, (q15_t)0x4F36,
- (q15_t)0x9B55, (q15_t)0x4F0F, (q15_t)0x9B36, (q15_t)0x4EE7,
- (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AF8, (q15_t)0x4E98,
- (q15_t)0x9AD9, (q15_t)0x4E70, (q15_t)0x9ABA, (q15_t)0x4E48,
- (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A7D, (q15_t)0x4DF9,
- (q15_t)0x9A5F, (q15_t)0x4DD1, (q15_t)0x9A40, (q15_t)0x4DA9,
- (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x9A03, (q15_t)0x4D59,
- (q15_t)0x99E5, (q15_t)0x4D31, (q15_t)0x99C6, (q15_t)0x4D09,
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- (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x815B, (q15_t)0x1296,
- (q15_t)0x8154, (q15_t)0x1264, (q15_t)0x814C, (q15_t)0x1232,
- (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x813E, (q15_t)0x11CF,
- (q15_t)0x8137, (q15_t)0x119D, (q15_t)0x8130, (q15_t)0x116B,
- (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x8123, (q15_t)0x1108,
- (q15_t)0x811C, (q15_t)0x10D6, (q15_t)0x8116, (q15_t)0x10A4,
- (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8109, (q15_t)0x1040,
- (q15_t)0x8102, (q15_t)0x100E, (q15_t)0x80FC, (q15_t)0x0FDD,
- (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80F0, (q15_t)0x0F79,
- (q15_t)0x80EA, (q15_t)0x0F47, (q15_t)0x80E4, (q15_t)0x0F15,
- (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D8, (q15_t)0x0EB1,
- (q15_t)0x80D2, (q15_t)0x0E7F, (q15_t)0x80CD, (q15_t)0x0E4D,
- (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80C2, (q15_t)0x0DE9,
- (q15_t)0x80BC, (q15_t)0x0DB7, (q15_t)0x80B7, (q15_t)0x0D85,
- (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80AC, (q15_t)0x0D21,
- (q15_t)0x80A7, (q15_t)0x0CEF, (q15_t)0x80A2, (q15_t)0x0CBD,
- (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8098, (q15_t)0x0C59,
- (q15_t)0x8094, (q15_t)0x0C27, (q15_t)0x808F, (q15_t)0x0BF5,
- (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8086, (q15_t)0x0B91,
- (q15_t)0x8081, (q15_t)0x0B5F, (q15_t)0x807D, (q15_t)0x0B2D,
- (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8074, (q15_t)0x0AC9,
- (q15_t)0x8070, (q15_t)0x0A97, (q15_t)0x806C, (q15_t)0x0A65,
- (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8064, (q15_t)0x0A00,
- (q15_t)0x8060, (q15_t)0x09CE, (q15_t)0x805C, (q15_t)0x099C,
- (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8055, (q15_t)0x0938,
- (q15_t)0x8051, (q15_t)0x0906, (q15_t)0x804E, (q15_t)0x08D4,
- (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8047, (q15_t)0x086F,
- (q15_t)0x8043, (q15_t)0x083D, (q15_t)0x8040, (q15_t)0x080B,
- (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x803A, (q15_t)0x07A7,
- (q15_t)0x8037, (q15_t)0x0775, (q15_t)0x8034, (q15_t)0x0742,
- (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802F, (q15_t)0x06DE,
- (q15_t)0x802C, (q15_t)0x06AC, (q15_t)0x8029, (q15_t)0x067A,
- (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8025, (q15_t)0x0615,
- (q15_t)0x8022, (q15_t)0x05E3, (q15_t)0x8020, (q15_t)0x05B1,
- (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801C, (q15_t)0x054C,
- (q15_t)0x801A, (q15_t)0x051A, (q15_t)0x8018, (q15_t)0x04E8,
- (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8014, (q15_t)0x0483,
- (q15_t)0x8012, (q15_t)0x0451, (q15_t)0x8011, (q15_t)0x041F,
- (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800D, (q15_t)0x03BA,
- (q15_t)0x800C, (q15_t)0x0388, (q15_t)0x800B, (q15_t)0x0356,
- (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8008, (q15_t)0x02F1,
- (q15_t)0x8007, (q15_t)0x02BF, (q15_t)0x8006, (q15_t)0x028D,
- (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8004, (q15_t)0x0228,
- (q15_t)0x8003, (q15_t)0x01F6, (q15_t)0x8003, (q15_t)0x01C4,
- (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x015F,
- (q15_t)0x8001, (q15_t)0x012D, (q15_t)0x8000, (q15_t)0x00FB,
- (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0096,
- (q15_t)0x8000, (q15_t)0x0064, (q15_t)0x8000, (q15_t)0x0032,
- (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFFCD,
- (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFF69,
- (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF04,
- (q15_t)0x8001, (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFEA0,
- (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE3B,
- (q15_t)0x8003, (q15_t)0xFE09, (q15_t)0x8004, (q15_t)0xFDD7,
- (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8006, (q15_t)0xFD72,
- (q15_t)0x8007, (q15_t)0xFD40, (q15_t)0x8008, (q15_t)0xFD0E,
- (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800B, (q15_t)0xFCA9,
- (q15_t)0x800C, (q15_t)0xFC77, (q15_t)0x800D, (q15_t)0xFC45,
- (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8011, (q15_t)0xFBE0,
- (q15_t)0x8012, (q15_t)0xFBAE, (q15_t)0x8014, (q15_t)0xFB7C,
- (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x8018, (q15_t)0xFB17,
- (q15_t)0x801A, (q15_t)0xFAE5, (q15_t)0x801C, (q15_t)0xFAB3,
- (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8020, (q15_t)0xFA4E,
- (q15_t)0x8022, (q15_t)0xFA1C, (q15_t)0x8025, (q15_t)0xF9EA,
- (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8029, (q15_t)0xF985,
- (q15_t)0x802C, (q15_t)0xF953, (q15_t)0x802F, (q15_t)0xF921,
- (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8034, (q15_t)0xF8BD,
- (q15_t)0x8037, (q15_t)0xF88A, (q15_t)0x803A, (q15_t)0xF858,
- (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8040, (q15_t)0xF7F4,
- (q15_t)0x8043, (q15_t)0xF7C2, (q15_t)0x8047, (q15_t)0xF790,
- (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x804E, (q15_t)0xF72B,
- (q15_t)0x8051, (q15_t)0xF6F9, (q15_t)0x8055, (q15_t)0xF6C7,
- (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x805C, (q15_t)0xF663,
- (q15_t)0x8060, (q15_t)0xF631, (q15_t)0x8064, (q15_t)0xF5FF,
- (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x806C, (q15_t)0xF59A,
- (q15_t)0x8070, (q15_t)0xF568, (q15_t)0x8074, (q15_t)0xF536,
- (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x807D, (q15_t)0xF4D2,
- (q15_t)0x8081, (q15_t)0xF4A0, (q15_t)0x8086, (q15_t)0xF46E,
- (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x808F, (q15_t)0xF40A,
- (q15_t)0x8094, (q15_t)0xF3D8, (q15_t)0x8098, (q15_t)0xF3A6,
- (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A2, (q15_t)0xF342,
- (q15_t)0x80A7, (q15_t)0xF310, (q15_t)0x80AC, (q15_t)0xF2DE,
- (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80B7, (q15_t)0xF27A,
- (q15_t)0x80BC, (q15_t)0xF248, (q15_t)0x80C2, (q15_t)0xF216,
- (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80CD, (q15_t)0xF1B2,
- (q15_t)0x80D2, (q15_t)0xF180, (q15_t)0x80D8, (q15_t)0xF14E,
- (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80E4, (q15_t)0xF0EA,
- (q15_t)0x80EA, (q15_t)0xF0B8, (q15_t)0x80F0, (q15_t)0xF086,
- (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x80FC, (q15_t)0xF022,
- (q15_t)0x8102, (q15_t)0xEFF1, (q15_t)0x8109, (q15_t)0xEFBF,
- (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x8116, (q15_t)0xEF5B,
- (q15_t)0x811C, (q15_t)0xEF29, (q15_t)0x8123, (q15_t)0xEEF7,
- (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8130, (q15_t)0xEE94,
- (q15_t)0x8137, (q15_t)0xEE62, (q15_t)0x813E, (q15_t)0xEE30,
- (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x814C, (q15_t)0xEDCD,
- (q15_t)0x8154, (q15_t)0xED9B, (q15_t)0x815B, (q15_t)0xED69,
- (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x816A, (q15_t)0xED06,
- (q15_t)0x8171, (q15_t)0xECD4, (q15_t)0x8179, (q15_t)0xECA2,
- (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8188, (q15_t)0xEC3F,
- (q15_t)0x8190, (q15_t)0xEC0D, (q15_t)0x8198, (q15_t)0xEBDC,
- (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81A8, (q15_t)0xEB78,
- (q15_t)0x81B0, (q15_t)0xEB47, (q15_t)0x81B8, (q15_t)0xEB15,
- (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81C8, (q15_t)0xEAB2,
- (q15_t)0x81D1, (q15_t)0xEA80, (q15_t)0x81D9, (q15_t)0xEA4F,
- (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81EB, (q15_t)0xE9EC,
- (q15_t)0x81F3, (q15_t)0xE9BA, (q15_t)0x81FC, (q15_t)0xE989,
- (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x820E, (q15_t)0xE926,
- (q15_t)0x8217, (q15_t)0xE8F5, (q15_t)0x8220, (q15_t)0xE8C3,
- (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x8232, (q15_t)0xE860,
- (q15_t)0x823C, (q15_t)0xE82F, (q15_t)0x8245, (q15_t)0xE7FD,
- (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8258, (q15_t)0xE79B,
- (q15_t)0x8262, (q15_t)0xE769, (q15_t)0x826B, (q15_t)0xE738,
- (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x827F, (q15_t)0xE6D5,
- (q15_t)0x8289, (q15_t)0xE6A4, (q15_t)0x8293, (q15_t)0xE673,
- (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82A7, (q15_t)0xE610,
- (q15_t)0x82B1, (q15_t)0xE5DF, (q15_t)0x82BC, (q15_t)0xE5AE,
- (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82D0, (q15_t)0xE54C,
- (q15_t)0x82DB, (q15_t)0xE51B, (q15_t)0x82E6, (q15_t)0xE4E9,
- (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x82FB, (q15_t)0xE487,
- (q15_t)0x8306, (q15_t)0xE456, (q15_t)0x8311, (q15_t)0xE425,
- (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8327, (q15_t)0xE3C3,
- (q15_t)0x8332, (q15_t)0xE392, (q15_t)0x833D, (q15_t)0xE361,
- (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x8354, (q15_t)0xE2FF,
- (q15_t)0x835F, (q15_t)0xE2CE, (q15_t)0x836B, (q15_t)0xE29D,
- (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x8382, (q15_t)0xE23B,
- (q15_t)0x838E, (q15_t)0xE20A, (q15_t)0x8399, (q15_t)0xE1DA,
- (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83B1, (q15_t)0xE178,
- (q15_t)0x83BD, (q15_t)0xE147, (q15_t)0x83C9, (q15_t)0xE116,
- (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83E2, (q15_t)0xE0B5,
- (q15_t)0x83EE, (q15_t)0xE084, (q15_t)0x83FA, (q15_t)0xE053,
- (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8414, (q15_t)0xDFF2,
- (q15_t)0x8420, (q15_t)0xDFC1, (q15_t)0x842D, (q15_t)0xDF91,
- (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8446, (q15_t)0xDF2F,
- (q15_t)0x8453, (q15_t)0xDEFF, (q15_t)0x8460, (q15_t)0xDECE,
- (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x847B, (q15_t)0xDE6D,
- (q15_t)0x8488, (q15_t)0xDE3D, (q15_t)0x8495, (q15_t)0xDE0C,
- (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84B0, (q15_t)0xDDAB,
- (q15_t)0x84BD, (q15_t)0xDD7B, (q15_t)0x84CB, (q15_t)0xDD4B,
- (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84E6, (q15_t)0xDCEA,
- (q15_t)0x84F4, (q15_t)0xDCBA, (q15_t)0x8502, (q15_t)0xDC89,
- (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x851E, (q15_t)0xDC29,
- (q15_t)0x852C, (q15_t)0xDBF8, (q15_t)0x853A, (q15_t)0xDBC8,
- (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8557, (q15_t)0xDB68,
- (q15_t)0x8565, (q15_t)0xDB38, (q15_t)0x8574, (q15_t)0xDB08,
- (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8591, (q15_t)0xDAA7,
- (q15_t)0x85A0, (q15_t)0xDA77, (q15_t)0x85AF, (q15_t)0xDA47,
- (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85CC, (q15_t)0xD9E7,
- (q15_t)0x85DB, (q15_t)0xD9B7, (q15_t)0x85EA, (q15_t)0xD987,
- (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8609, (q15_t)0xD927,
- (q15_t)0x8618, (q15_t)0xD8F8, (q15_t)0x8627, (q15_t)0xD8C8,
- (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8646, (q15_t)0xD868,
- (q15_t)0x8656, (q15_t)0xD838, (q15_t)0x8666, (q15_t)0xD809,
- (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8685, (q15_t)0xD7A9,
- (q15_t)0x8695, (q15_t)0xD779, (q15_t)0x86A5, (q15_t)0xD74A,
- (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86C5, (q15_t)0xD6EA,
- (q15_t)0x86D5, (q15_t)0xD6BB, (q15_t)0x86E6, (q15_t)0xD68B,
- (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8706, (q15_t)0xD62C,
- (q15_t)0x8717, (q15_t)0xD5FD, (q15_t)0x8727, (q15_t)0xD5CD,
- (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8749, (q15_t)0xD56E,
- (q15_t)0x8759, (q15_t)0xD53F, (q15_t)0x876A, (q15_t)0xD510,
- (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x878C, (q15_t)0xD4B1,
- (q15_t)0x879D, (q15_t)0xD482, (q15_t)0x87AE, (q15_t)0xD452,
- (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87D1, (q15_t)0xD3F4,
- (q15_t)0x87E2, (q15_t)0xD3C5, (q15_t)0x87F3, (q15_t)0xD396,
- (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8816, (q15_t)0xD337,
- (q15_t)0x8828, (q15_t)0xD308, (q15_t)0x883A, (q15_t)0xD2D9,
- (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x885D, (q15_t)0xD27B,
- (q15_t)0x886F, (q15_t)0xD24C, (q15_t)0x8881, (q15_t)0xD21D,
- (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88A5, (q15_t)0xD1C0,
- (q15_t)0x88B8, (q15_t)0xD191, (q15_t)0x88CA, (q15_t)0xD162,
- (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x88EF, (q15_t)0xD104,
- (q15_t)0x8901, (q15_t)0xD0D6, (q15_t)0x8914, (q15_t)0xD0A7,
- (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8939, (q15_t)0xD04A,
- (q15_t)0x894C, (q15_t)0xD01B, (q15_t)0x895F, (q15_t)0xCFEC,
- (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8984, (q15_t)0xCF8F,
- (q15_t)0x8997, (q15_t)0xCF61, (q15_t)0x89AB, (q15_t)0xCF32,
- (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89D1, (q15_t)0xCED5,
- (q15_t)0x89E4, (q15_t)0xCEA7, (q15_t)0x89F8, (q15_t)0xCE79,
- (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A1F, (q15_t)0xCE1C,
- (q15_t)0x8A33, (q15_t)0xCDEE, (q15_t)0x8A46, (q15_t)0xCDBF,
- (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A6E, (q15_t)0xCD63,
- (q15_t)0x8A82, (q15_t)0xCD35, (q15_t)0x8A96, (q15_t)0xCD07,
- (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8ABE, (q15_t)0xCCAB,
- (q15_t)0x8AD2, (q15_t)0xCC7D, (q15_t)0x8AE6, (q15_t)0xCC4F,
- (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B0F, (q15_t)0xCBF3,
- (q15_t)0x8B24, (q15_t)0xCBC5, (q15_t)0x8B38, (q15_t)0xCB97,
- (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B61, (q15_t)0xCB3B,
- (q15_t)0x8B76, (q15_t)0xCB0D, (q15_t)0x8B8B, (q15_t)0xCAE0,
- (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BB5, (q15_t)0xCA84,
- (q15_t)0x8BCA, (q15_t)0xCA57, (q15_t)0x8BDF, (q15_t)0xCA29,
- (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C09, (q15_t)0xC9CE,
- (q15_t)0x8C1F, (q15_t)0xC9A0, (q15_t)0x8C34, (q15_t)0xC973,
- (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C5F, (q15_t)0xC918,
- (q15_t)0x8C75, (q15_t)0xC8EB, (q15_t)0x8C8A, (q15_t)0xC8BD,
- (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CB6, (q15_t)0xC863,
- (q15_t)0x8CCC, (q15_t)0xC835, (q15_t)0x8CE2, (q15_t)0xC808,
- (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D0E, (q15_t)0xC7AE,
- (q15_t)0x8D24, (q15_t)0xC781, (q15_t)0x8D3A, (q15_t)0xC754,
- (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D67, (q15_t)0xC6F9,
- (q15_t)0x8D7D, (q15_t)0xC6CD, (q15_t)0x8D94, (q15_t)0xC6A0,
- (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DC1, (q15_t)0xC646,
- (q15_t)0x8DD8, (q15_t)0xC619, (q15_t)0x8DEE, (q15_t)0xC5EC,
- (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E1C, (q15_t)0xC593,
- (q15_t)0x8E33, (q15_t)0xC566, (q15_t)0x8E4A, (q15_t)0xC539,
- (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E79, (q15_t)0xC4E0,
- (q15_t)0x8E90, (q15_t)0xC4B3, (q15_t)0x8EA7, (q15_t)0xC487,
- (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8ED6, (q15_t)0xC42E,
- (q15_t)0x8EED, (q15_t)0xC402, (q15_t)0x8F05, (q15_t)0xC3D5,
- (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F34, (q15_t)0xC37C,
- (q15_t)0x8F4C, (q15_t)0xC350, (q15_t)0x8F64, (q15_t)0xC324,
- (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8F94, (q15_t)0xC2CC,
- (q15_t)0x8FAC, (q15_t)0xC29F, (q15_t)0x8FC4, (q15_t)0xC273,
- (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x8FF5, (q15_t)0xC21B,
- (q15_t)0x900D, (q15_t)0xC1EF, (q15_t)0x9025, (q15_t)0xC1C3,
- (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x9056, (q15_t)0xC16C,
- (q15_t)0x906F, (q15_t)0xC140, (q15_t)0x9088, (q15_t)0xC114,
- (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90B9, (q15_t)0xC0BC,
- (q15_t)0x90D2, (q15_t)0xC091, (q15_t)0x90EB, (q15_t)0xC065,
- (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x911D, (q15_t)0xC00E,
- (q15_t)0x9136, (q15_t)0xBFE2, (q15_t)0x9150, (q15_t)0xBFB7,
- (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x9182, (q15_t)0xBF60,
- (q15_t)0x919C, (q15_t)0xBF35, (q15_t)0x91B5, (q15_t)0xBF09,
- (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x91E8, (q15_t)0xBEB3,
- (q15_t)0x9202, (q15_t)0xBE88, (q15_t)0x921C, (q15_t)0xBE5D,
- (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x924F, (q15_t)0xBE06,
- (q15_t)0x9269, (q15_t)0xBDDB, (q15_t)0x9283, (q15_t)0xBDB0,
- (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92B7, (q15_t)0xBD5A,
- (q15_t)0x92D2, (q15_t)0xBD2F, (q15_t)0x92EC, (q15_t)0xBD05,
- (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9321, (q15_t)0xBCAF,
- (q15_t)0x933B, (q15_t)0xBC84, (q15_t)0x9356, (q15_t)0xBC5A,
- (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x938B, (q15_t)0xBC04,
- (q15_t)0x93A6, (q15_t)0xBBDA, (q15_t)0x93C0, (q15_t)0xBBAF,
- (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x93F6, (q15_t)0xBB5A,
- (q15_t)0x9411, (q15_t)0xBB30, (q15_t)0x942C, (q15_t)0xBB05,
- (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x9463, (q15_t)0xBAB1,
- (q15_t)0x947E, (q15_t)0xBA87, (q15_t)0x9499, (q15_t)0xBA5C,
- (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94D0, (q15_t)0xBA08,
- (q15_t)0x94EC, (q15_t)0xB9DE, (q15_t)0x9507, (q15_t)0xB9B4,
- (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x953E, (q15_t)0xB960,
- (q15_t)0x955A, (q15_t)0xB936, (q15_t)0x9576, (q15_t)0xB90C,
- (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95AE, (q15_t)0xB8B9,
- (q15_t)0x95CA, (q15_t)0xB88F, (q15_t)0x95E6, (q15_t)0xB865,
- (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x961E, (q15_t)0xB812,
- (q15_t)0x963B, (q15_t)0xB7E9, (q15_t)0x9657, (q15_t)0xB7BF,
- (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x9690, (q15_t)0xB76C,
- (q15_t)0x96AC, (q15_t)0xB743, (q15_t)0x96C9, (q15_t)0xB719,
- (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x9702, (q15_t)0xB6C7,
- (q15_t)0x971F, (q15_t)0xB69E, (q15_t)0x973C, (q15_t)0xB675,
- (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9776, (q15_t)0xB622,
- (q15_t)0x9793, (q15_t)0xB5F9, (q15_t)0x97B0, (q15_t)0xB5D0,
- (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x97EA, (q15_t)0xB57E,
- (q15_t)0x9808, (q15_t)0xB556, (q15_t)0x9825, (q15_t)0xB52D,
- (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB,
- (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A,
- (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439,
- (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8,
- (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397,
- (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347,
- (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6,
- (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6,
- (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256,
- (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206,
- (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7,
- (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167,
- (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118,
- (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9,
- (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A,
- (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B,
- (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD,
- (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F,
- (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40,
- (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3,
- (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5,
- (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57,
- (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A,
- (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD,
- (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70,
- (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23,
- (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7,
- (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A,
- (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E,
- (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2,
- (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7,
- (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B,
- (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA03D, (q15_t)0xAB10,
- (q15_t)0xA05F, (q15_t)0xAAEA, (q15_t)0xA080, (q15_t)0xAAC5,
- (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0C3, (q15_t)0xAA7A,
- (q15_t)0xA0E5, (q15_t)0xAA54, (q15_t)0xA106, (q15_t)0xAA2F,
- (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA14A, (q15_t)0xA9E5,
- (q15_t)0xA16C, (q15_t)0xA9BF, (q15_t)0xA18E, (q15_t)0xA99A,
- (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1D2, (q15_t)0xA950,
- (q15_t)0xA1F4, (q15_t)0xA92B, (q15_t)0xA216, (q15_t)0xA906,
- (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA25A, (q15_t)0xA8BD,
- (q15_t)0xA27C, (q15_t)0xA898, (q15_t)0xA29F, (q15_t)0xA873,
- (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA2E4, (q15_t)0xA82A,
- (q15_t)0xA306, (q15_t)0xA806, (q15_t)0xA329, (q15_t)0xA7E1,
- (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA36E, (q15_t)0xA798,
- (q15_t)0xA391, (q15_t)0xA774, (q15_t)0xA3B4, (q15_t)0xA750,
- (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA3F9, (q15_t)0xA707,
- (q15_t)0xA41C, (q15_t)0xA6E3, (q15_t)0xA43F, (q15_t)0xA6BF,
- (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA486, (q15_t)0xA677,
- (q15_t)0xA4A9, (q15_t)0xA653, (q15_t)0xA4CC, (q15_t)0xA62F,
- (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA513, (q15_t)0xA5E8,
- (q15_t)0xA536, (q15_t)0xA5C4, (q15_t)0xA55A, (q15_t)0xA5A1,
- (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5A1, (q15_t)0xA55A,
- (q15_t)0xA5C4, (q15_t)0xA536, (q15_t)0xA5E8, (q15_t)0xA513,
- (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA62F, (q15_t)0xA4CC,
- (q15_t)0xA653, (q15_t)0xA4A9, (q15_t)0xA677, (q15_t)0xA486,
- (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6BF, (q15_t)0xA43F,
- (q15_t)0xA6E3, (q15_t)0xA41C, (q15_t)0xA707, (q15_t)0xA3F9,
- (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA750, (q15_t)0xA3B4,
- (q15_t)0xA774, (q15_t)0xA391, (q15_t)0xA798, (q15_t)0xA36E,
- (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA7E1, (q15_t)0xA329,
- (q15_t)0xA806, (q15_t)0xA306, (q15_t)0xA82A, (q15_t)0xA2E4,
- (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA873, (q15_t)0xA29F,
- (q15_t)0xA898, (q15_t)0xA27C, (q15_t)0xA8BD, (q15_t)0xA25A,
- (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA906, (q15_t)0xA216,
- (q15_t)0xA92B, (q15_t)0xA1F4, (q15_t)0xA950, (q15_t)0xA1D2,
- (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA99A, (q15_t)0xA18E,
- (q15_t)0xA9BF, (q15_t)0xA16C, (q15_t)0xA9E5, (q15_t)0xA14A,
- (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA2F, (q15_t)0xA106,
- (q15_t)0xAA54, (q15_t)0xA0E5, (q15_t)0xAA7A, (q15_t)0xA0C3,
- (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAC5, (q15_t)0xA080,
- (q15_t)0xAAEA, (q15_t)0xA05F, (q15_t)0xAB10, (q15_t)0xA03D,
- (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB5B, (q15_t)0x9FFB,
- (q15_t)0xAB81, (q15_t)0x9FD9, (q15_t)0xABA7, (q15_t)0x9FB8,
- (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xABF2, (q15_t)0x9F76,
- (q15_t)0xAC18, (q15_t)0x9F55, (q15_t)0xAC3E, (q15_t)0x9F34,
- (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAC8A, (q15_t)0x9EF2,
- (q15_t)0xACB1, (q15_t)0x9ED2, (q15_t)0xACD7, (q15_t)0x9EB1,
- (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD23, (q15_t)0x9E70,
- (q15_t)0xAD4A, (q15_t)0x9E4F, (q15_t)0xAD70, (q15_t)0x9E2F,
- (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADBD, (q15_t)0x9DEE,
- (q15_t)0xADE3, (q15_t)0x9DCE, (q15_t)0xAE0A, (q15_t)0x9DAE,
- (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE57, (q15_t)0x9D6D,
- (q15_t)0xAE7E, (q15_t)0x9D4D, (q15_t)0xAEA5, (q15_t)0x9D2D,
- (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAEF3, (q15_t)0x9CEE,
- (q15_t)0xAF1A, (q15_t)0x9CCE, (q15_t)0xAF40, (q15_t)0x9CAE,
- (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAF8F, (q15_t)0x9C6F,
- (q15_t)0xAFB6, (q15_t)0x9C4F, (q15_t)0xAFDD, (q15_t)0x9C30,
- (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB02B, (q15_t)0x9BF1,
- (q15_t)0xB053, (q15_t)0x9BD2, (q15_t)0xB07A, (q15_t)0x9BB2,
- (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0C9, (q15_t)0x9B74,
- (q15_t)0xB0F0, (q15_t)0x9B55, (q15_t)0xB118, (q15_t)0x9B36,
- (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB167, (q15_t)0x9AF8,
- (q15_t)0xB18F, (q15_t)0x9AD9, (q15_t)0xB1B7, (q15_t)0x9ABA,
- (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB206, (q15_t)0x9A7D,
- (q15_t)0xB22E, (q15_t)0x9A5F, (q15_t)0xB256, (q15_t)0x9A40,
- (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2A6, (q15_t)0x9A03,
- (q15_t)0xB2CE, (q15_t)0x99E5, (q15_t)0xB2F6, (q15_t)0x99C6,
- (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB347, (q15_t)0x998A,
- (q15_t)0xB36F, (q15_t)0x996C, (q15_t)0xB397, (q15_t)0x994E,
- (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB3E8, (q15_t)0x9912,
- (q15_t)0xB410, (q15_t)0x98F4, (q15_t)0xB439, (q15_t)0x98D6,
- (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB48A, (q15_t)0x989B,
- (q15_t)0xB4B3, (q15_t)0x987D, (q15_t)0xB4DB, (q15_t)0x9860,
- (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB52D, (q15_t)0x9825,
- (q15_t)0xB556, (q15_t)0x9808, (q15_t)0xB57E, (q15_t)0x97EA,
- (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5D0, (q15_t)0x97B0,
- (q15_t)0xB5F9, (q15_t)0x9793, (q15_t)0xB622, (q15_t)0x9776,
- (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB675, (q15_t)0x973C,
- (q15_t)0xB69E, (q15_t)0x971F, (q15_t)0xB6C7, (q15_t)0x9702,
- (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB719, (q15_t)0x96C9,
- (q15_t)0xB743, (q15_t)0x96AC, (q15_t)0xB76C, (q15_t)0x9690,
- (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657,
- (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E,
- (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6,
- (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE,
- (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576,
- (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E,
- (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507,
- (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0,
- (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499,
- (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463,
- (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C,
- (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6,
- (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0,
- (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B,
- (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356,
- (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321,
- (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD05, (q15_t)0x92EC,
- (q15_t)0xBD2F, (q15_t)0x92D2, (q15_t)0xBD5A, (q15_t)0x92B7,
- (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDB0, (q15_t)0x9283,
- (q15_t)0xBDDB, (q15_t)0x9269, (q15_t)0xBE06, (q15_t)0x924F,
- (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE5D, (q15_t)0x921C,
- (q15_t)0xBE88, (q15_t)0x9202, (q15_t)0xBEB3, (q15_t)0x91E8,
- (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF09, (q15_t)0x91B5,
- (q15_t)0xBF35, (q15_t)0x919C, (q15_t)0xBF60, (q15_t)0x9182,
- (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFB7, (q15_t)0x9150,
- (q15_t)0xBFE2, (q15_t)0x9136, (q15_t)0xC00E, (q15_t)0x911D,
- (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC065, (q15_t)0x90EB,
- (q15_t)0xC091, (q15_t)0x90D2, (q15_t)0xC0BC, (q15_t)0x90B9,
- (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC114, (q15_t)0x9088,
- (q15_t)0xC140, (q15_t)0x906F, (q15_t)0xC16C, (q15_t)0x9056,
- (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1C3, (q15_t)0x9025,
- (q15_t)0xC1EF, (q15_t)0x900D, (q15_t)0xC21B, (q15_t)0x8FF5,
- (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC273, (q15_t)0x8FC4,
- (q15_t)0xC29F, (q15_t)0x8FAC, (q15_t)0xC2CC, (q15_t)0x8F94,
- (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC324, (q15_t)0x8F64,
- (q15_t)0xC350, (q15_t)0x8F4C, (q15_t)0xC37C, (q15_t)0x8F34,
- (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC3D5, (q15_t)0x8F05,
- (q15_t)0xC402, (q15_t)0x8EED, (q15_t)0xC42E, (q15_t)0x8ED6,
- (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC487, (q15_t)0x8EA7,
- (q15_t)0xC4B3, (q15_t)0x8E90, (q15_t)0xC4E0, (q15_t)0x8E79,
- (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC539, (q15_t)0x8E4A,
- (q15_t)0xC566, (q15_t)0x8E33, (q15_t)0xC593, (q15_t)0x8E1C,
- (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC5EC, (q15_t)0x8DEE,
- (q15_t)0xC619, (q15_t)0x8DD8, (q15_t)0xC646, (q15_t)0x8DC1,
- (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6A0, (q15_t)0x8D94,
- (q15_t)0xC6CD, (q15_t)0x8D7D, (q15_t)0xC6F9, (q15_t)0x8D67,
- (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC754, (q15_t)0x8D3A,
- (q15_t)0xC781, (q15_t)0x8D24, (q15_t)0xC7AE, (q15_t)0x8D0E,
- (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC808, (q15_t)0x8CE2,
- (q15_t)0xC835, (q15_t)0x8CCC, (q15_t)0xC863, (q15_t)0x8CB6,
- (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8BD, (q15_t)0x8C8A,
- (q15_t)0xC8EB, (q15_t)0x8C75, (q15_t)0xC918, (q15_t)0x8C5F,
- (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC973, (q15_t)0x8C34,
- (q15_t)0xC9A0, (q15_t)0x8C1F, (q15_t)0xC9CE, (q15_t)0x8C09,
- (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA29, (q15_t)0x8BDF,
- (q15_t)0xCA57, (q15_t)0x8BCA, (q15_t)0xCA84, (q15_t)0x8BB5,
- (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCAE0, (q15_t)0x8B8B,
- (q15_t)0xCB0D, (q15_t)0x8B76, (q15_t)0xCB3B, (q15_t)0x8B61,
- (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCB97, (q15_t)0x8B38,
- (q15_t)0xCBC5, (q15_t)0x8B24, (q15_t)0xCBF3, (q15_t)0x8B0F,
- (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC4F, (q15_t)0x8AE6,
- (q15_t)0xCC7D, (q15_t)0x8AD2, (q15_t)0xCCAB, (q15_t)0x8ABE,
- (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD07, (q15_t)0x8A96,
- (q15_t)0xCD35, (q15_t)0x8A82, (q15_t)0xCD63, (q15_t)0x8A6E,
- (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDBF, (q15_t)0x8A46,
- (q15_t)0xCDEE, (q15_t)0x8A33, (q15_t)0xCE1C, (q15_t)0x8A1F,
- (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCE79, (q15_t)0x89F8,
- (q15_t)0xCEA7, (q15_t)0x89E4, (q15_t)0xCED5, (q15_t)0x89D1,
- (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF32, (q15_t)0x89AB,
- (q15_t)0xCF61, (q15_t)0x8997, (q15_t)0xCF8F, (q15_t)0x8984,
- (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xCFEC, (q15_t)0x895F,
- (q15_t)0xD01B, (q15_t)0x894C, (q15_t)0xD04A, (q15_t)0x8939,
- (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0A7, (q15_t)0x8914,
- (q15_t)0xD0D6, (q15_t)0x8901, (q15_t)0xD104, (q15_t)0x88EF,
- (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD162, (q15_t)0x88CA,
- (q15_t)0xD191, (q15_t)0x88B8, (q15_t)0xD1C0, (q15_t)0x88A5,
- (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD21D, (q15_t)0x8881,
- (q15_t)0xD24C, (q15_t)0x886F, (q15_t)0xD27B, (q15_t)0x885D,
- (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD2D9, (q15_t)0x883A,
- (q15_t)0xD308, (q15_t)0x8828, (q15_t)0xD337, (q15_t)0x8816,
- (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3,
- (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1,
- (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE,
- (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C,
- (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A,
- (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749,
- (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727,
- (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706,
- (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6,
- (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5,
- (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5,
- (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685,
- (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666,
- (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646,
- (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627,
- (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609,
- (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA,
- (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC,
- (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF,
- (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591,
- (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574,
- (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557,
- (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A,
- (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E,
- (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502,
- (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6,
- (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB,
- (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0,
- (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495,
- (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B,
- (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460,
- (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446,
- (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D,
- (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414,
- (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA,
- (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2,
- (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9,
- (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1,
- (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399,
- (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382,
- (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B,
- (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354,
- (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D,
- (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327,
- (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311,
- (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB,
- (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6,
- (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0,
- (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC,
- (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7,
- (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293,
- (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F,
- (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B,
- (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258,
- (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245,
- (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232,
- (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220,
- (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E,
- (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC,
- (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB,
- (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9,
- (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8,
- (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8,
- (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8,
- (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198,
- (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188,
- (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179,
- (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A,
- (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B,
- (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C,
- (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E,
- (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130,
- (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123,
- (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116,
- (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109,
- (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC,
- (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0,
- (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4,
- (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8,
- (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD,
- (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2,
- (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7,
- (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC,
- (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2,
- (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098,
- (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F,
- (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086,
- (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D,
- (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074,
- (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C,
- (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064,
- (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C,
- (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055,
- (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E,
- (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047,
- (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040,
- (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A,
- (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034,
- (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F,
- (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029,
- (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025,
- (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020,
- (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C,
- (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018,
- (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014,
- (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011,
- (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D,
- (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B,
- (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008,
- (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006,
- (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004,
- (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003,
- (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001,
- (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000,
- (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000,
- (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000
-};
-
-
-/**
-* @} end of CFFT_CIFFT group
-*/
-
-/*
-* @brief Q15 table for reciprocal
-*/
-const q15_t ALIGN4 armRecipTableQ15[64] = {
- 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
- 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
- 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
- 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
- 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
- 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
- 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
- 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
- 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
- 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
- 0x41CC, 0x4146, 0x40C2, 0x4040
-};
-
-/*
-* @brief Q31 table for reciprocal
-*/
-const q31_t armRecipTableQ31[64] = {
- 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
- 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
- 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
- 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
- 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
- 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
- 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
- 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
- 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
- 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
- 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
-};
-
-const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] =
-{
- /* 8x2, size 20 */
- 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
-};
-
-const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] =
-{
- /* 8x4, size 48 */
- 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
- 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
- 152,224, 176,208, 184,232, 216,240, 200,224, 232,240
-};
-
-const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] =
-{
- /* radix 8, size 56 */
- 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200,
- 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400,
- 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480,
- 368,424, 376,488, 440,496
-};
-
-const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] =
-{
- /* 8x2, size 208 */
- 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768,
- 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520,
- 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776,
- 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320,
- 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400,
- 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584,
- 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600,
- 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608,
- 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864,
- 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808,
- 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832,
- 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008,
- 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
-};
-
-const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] =
-{
- /* 8x4, size 440 */
- 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640,
- 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768,
- 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384,
- 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984,
- 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608,
- 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736,
- 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864,
- 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992,
- 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104,
- 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720,
- 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160,
- 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936,
- 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048,
- 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808,
- 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544,
- 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880,
- 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496,
- 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120,
- 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552,
- 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824,
- 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672,
- 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016,
- 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640,
- 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432,
- 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936,
- 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960,
- 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648,
- 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936,
- 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928,
- 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840,
- 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888,
- 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
- 1960,1968, 2008,2032, 1992,2016, 2024,2032
-};
-
-const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] =
-{
- /* radix 8, size 448 */
- 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576,
- 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152,
- 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216,
- 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280,
- 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344,
- 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408,
- 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472,
- 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544,
- 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120,
- 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696,
- 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272,
- 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848,
- 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416,
- 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992,
- 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576,
- 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152,
- 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728,
- 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808,
- 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384,
- 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960,
- 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536,
- 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136,
- 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224,
- 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328,
- 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416,
- 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520,
- 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616,
- 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744,
- 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872,
- 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000,
- 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176,
- 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368,
- 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560,
- 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888,
- 3448,3952, 3512,4016, 3576,4080
-};
-
-const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] =
-{
- /* 8x2, size 1800 */
- 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048,
- 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048,
- 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696,
- 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648,
- 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248,
- 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200,
- 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800,
- 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752,
- 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352,
- 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304,
- 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936,
- 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856,
- 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488,
- 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408,
- 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040,
- 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960,
- 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592,
- 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096,
- 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544,
- 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080,
- 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400,
- 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120,
- 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656,
- 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168,
- 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696,
- 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208,
- 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736,
- 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272,
- 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480,
- 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312,
- 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848,
- 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280,
- 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888,
- 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288,
- 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928,
- 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464,
- 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592,
- 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504,
- 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040,
- 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136,
- 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088,
- 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816,
- 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576,
- 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664,
- 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264,
- 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800,
- 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304,
- 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840,
- 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376,
- 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392,
- 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344,
- 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944,
- 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480,
- 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016,
- 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032,
- 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984,
- 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584,
- 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632,
- 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632,
- 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168,
- 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704,
- 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208,
- 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744,
- 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248,
- 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784,
- 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320,
- 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824,
- 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360,
- 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896,
- 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400,
- 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936,
- 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440,
- 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976,
- 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512,
- 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016,
- 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552,
- 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088,
- 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592,
- 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128,
- 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160,
- 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176,
- 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712,
- 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216,
- 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752,
- 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416,
- 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304,
- 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624,
- 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296,
- 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680,
- 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208,
- 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400,
- 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808,
- 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688,
- 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976,
- 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160,
- 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344,
- 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728,
- 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736,
- 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928,
- 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872,
- 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672,
- 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208,
- 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456,
- 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248,
- 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784,
- 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448,
- 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824,
- 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240,
- 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504,
- 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168,
- 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264,
- 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456,
- 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552,
- 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312,
- 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576,
- 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248,
- 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504,
- 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360,
- 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624,
- 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384,
- 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264,
- 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664,
- 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520,
- 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280,
- 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536,
- 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048,
- 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752,
- 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992,
- 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280,
- 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856,
- 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024,
- 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624,
- 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104,
- 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664,
- 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280,
- 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688,
- 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952,
- 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456,
- 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864,
- 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784,
- 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048,
- 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728,
- 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096,
- 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112,
- 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984,
- 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160,
- 8112,8136, 8120,8168, 8136,8160, 8152,8176
-};
-
-const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] =
-{
- /* 8x2, size 3808 */
- 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024,
- 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824,
- 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752,
- 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680,
- 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576,
- 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376,
- 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304,
- 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232,
- 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048,
- 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928,
- 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856,
- 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784,
- 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712,
- 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480,
- 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408,
- 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336,
- 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264,
- 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064,
- 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960,
- 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792,
- 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496,
- 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328,
- 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032,
- 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928,
- 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856,
- 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560,
- 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392,
- 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096,
- 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240,
- 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600,
- 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432,
- 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136,
- 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968,
- 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640,
- 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392,
- 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176,
- 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008,
- 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712,
- 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096,
- 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712,
- 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480,
- 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248,
- 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080,
- 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784,
- 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248,
- 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288,
- 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128,
- 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824,
- 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656,
- 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328,
- 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400,
- 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864,
- 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280,
- 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400,
- 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168,
- 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904,
- 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552,
- 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440,
- 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272,
- 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976,
- 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288,
- 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480,
- 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168,
- 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016,
- 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848,
- 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520,
- 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440,
- 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056,
- 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320,
- 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592,
- 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208,
- 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096,
- 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592,
- 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632,
- 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472,
- 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168,
- 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360,
- 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672,
- 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240,
- 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208,
- 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624,
- 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208,
- 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448,
- 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744,
- 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328,
- 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280,
- 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216,
- 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784,
- 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600,
- 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320,
- 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480,
- 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856,
- 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368,
- 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360,
- 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248,
- 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896,
- 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632,
- 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400,
- 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520,
- 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936,
- 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400,
- 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472,
- 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256,
- 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976,
- 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640,
- 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512,
- 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520,
- 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048,
- 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408,
- 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552,
- 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288,
- 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088,
- 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672,
- 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592,
- 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560,
- 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128,
- 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440,
- 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664,
- 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328,
- 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168,
- 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712,
- 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704,
- 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592,
- 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240,
- 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416,
- 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240,
- 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296,
- 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776,
- 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680,
- 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280,
- 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568,
- 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816,
- 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448,
- 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352,
- 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336,
- 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856,
- 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720,
- 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392,
- 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600,
- 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928,
- 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488,
- 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432,
- 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368,
- 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968,
- 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752,
- 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472,
- 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608,
- 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008,
- 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488,
- 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544,
- 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376,
- 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048,
- 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760,
- 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584,
- 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640,
- 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120,
- 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528,
- 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624,
- 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408,
- 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160,
- 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792,
- 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664,
- 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680,
- 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200,
- 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560,
- 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736,
- 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320,
- 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448,
- 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760,
- 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464,
- 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392,
- 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576,
- 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896,
- 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688,
- 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432,
- 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736,
- 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968,
- 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376,
- 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472,
- 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424,
- 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008,
- 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536,
- 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512,
- 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736,
- 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048,
- 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728,
- 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584,
- 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248,
- 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408,
- 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112,
- 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040,
- 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616,
- 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640,
- 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664,
- 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688,
- 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616,
- 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312,
- 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336,
- 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392,
- 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656,
- 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408,
- 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192,
- 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584,
- 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760,
- 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208,
- 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816,
- 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664,
- 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816,
- 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328,
- 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296,
- 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400,
- 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480,
- 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304,
- 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912,
- 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296,
- 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360,
- 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464,
- 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440,
- 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344,
- 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800,
- 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464,
- 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968,
- 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368,
- 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440,
- 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488,
- 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528,
- 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400,
- 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440,
- 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552,
- 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056,
- 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424,
- 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760,
- 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008,
- 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408,
- 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648,
- 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120,
- 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440,
- 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656,
- 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552,
- 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160,
- 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720,
- 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760,
- 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672,
- 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624,
- 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728,
- 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736,
- 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608,
- 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512,
- 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760,
- 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296,
- 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664,
- 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712,
- 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816,
- 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824,
- 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696,
- 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832,
- 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544,
- 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584,
- 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496,
- 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688,
- 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920,
- 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344,
- 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576,
- 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400,
- 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448,
- 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696,
- 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816,
- 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344,
- 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976,
- 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416,
- 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496,
- 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488,
- 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536,
- 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592,
- 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736,
- 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664,
- 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064,
- 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464,
- 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816,
- 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768,
- 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576,
- 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592,
- 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536,
- 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664,
- 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616,
- 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704,
- 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728,
- 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488,
- 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384,
- 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560,
- 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392,
- 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528,
- 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464,
- 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304,
- 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632,
- 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808,
- 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704,
- 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832,
- 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712,
- 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848,
- 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600,
- 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640,
- 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728,
- 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,
- 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384,
- 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616,
- 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656,
- 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504,
- 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528,
- 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776,
- 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880,
- 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024,
- 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232,
- 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024,
- 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544,
- 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872,
- 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016,
- 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160,
- 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304,
- 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008,
- 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152,
- 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296,
- 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632,
- 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768,
- 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760,
- 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184,
- 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856,
- 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000,
- 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160,
- 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264,
- 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048,
- 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184,
- 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264,
- 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208,
- 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352,
- 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
- 16328,16352, 16360,16368
-};
-
-const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] =
-{
- /* radix 8, size 4032 */
- 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512,
- 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184,
- 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600,
- 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016,
- 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432,
- 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848,
- 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264,
- 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680,
- 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160,
- 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672,
- 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088,
- 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760,
- 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176,
- 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592,
- 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008,
- 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424,
- 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840,
- 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224,
- 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800,
- 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216,
- 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632,
- 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952,
- 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272,
- 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848,
- 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168,
- 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488,
- 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808,
- 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384,
- 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768,
- 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184,
- 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600,
- 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016,
- 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336,
- 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912,
- 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232,
- 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552,
- 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872,
- 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448,
- 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832,
- 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248,
- 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664,
- 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080,
- 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496,
- 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816,
- 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392,
- 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712,
- 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032,
- 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416,
- 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992,
- 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408,
- 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824,
- 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240,
- 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656,
- 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072,
- 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392,
- 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968,
- 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288,
- 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672,
- 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088,
- 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504,
- 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080,
- 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496,
- 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912,
- 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328,
- 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744,
- 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064,
- 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640,
- 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024,
- 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440,
- 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856,
- 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272,
- 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688,
- 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104,
- 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680,
- 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096,
- 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512,
- 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488,
- 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904,
- 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320,
- 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736,
- 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152,
- 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728,
- 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144,
- 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560,
- 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976,
- 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456,
- 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968,
- 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384,
- 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800,
- 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216,
- 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792,
- 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208,
- 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624,
- 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040,
- 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520,
- 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032,
- 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544,
- 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960,
- 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376,
- 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792,
- 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368,
- 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784,
- 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200,
- 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680,
- 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192,
- 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704,
- 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216,
- 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632,
- 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048,
- 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464,
- 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880,
- 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456,
- 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936,
- 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448,
- 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960,
- 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472,
- 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984,
- 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400,
- 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816,
- 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232,
- 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712,
- 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224,
- 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736,
- 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248,
- 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760,
- 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272,
- 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688,
- 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104,
- 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584,
- 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096,
- 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608,
- 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120,
- 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632,
- 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144,
- 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656,
- 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072,
- 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648,
- 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128,
- 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640,
- 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152,
- 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664,
- 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176,
- 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688,
- 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200,
- 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712,
- 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720,
- 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232,
- 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744,
- 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256,
- 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768,
- 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280,
- 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792,
- 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368,
- 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976,
- 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488,
- 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000,
- 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512,
- 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024,
- 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536,
- 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048,
- 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624,
- 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232,
- 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840,
- 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352,
- 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864,
- 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376,
- 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888,
- 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400,
- 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008,
- 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616,
- 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224,
- 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736,
- 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152,
- 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568,
- 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984,
- 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464,
- 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944,
- 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456,
- 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968,
- 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480,
- 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992,
- 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408,
- 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824,
- 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240,
- 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720,
- 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232,
- 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744,
- 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256,
- 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768,
- 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280,
- 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696,
- 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112,
- 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592,
- 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072,
- 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584,
- 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096,
- 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608,
- 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120,
- 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632,
- 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144,
- 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560,
- 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040,
- 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552,
- 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064,
- 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576,
- 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088,
- 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600,
- 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112,
- 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624,
- 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696,
- 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208,
- 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720,
- 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232,
- 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744,
- 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256,
- 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768,
- 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280,
- 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984,
- 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496,
- 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008,
- 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520,
- 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032,
- 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544,
- 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056,
- 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632,
- 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240,
- 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848,
- 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360,
- 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872,
- 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384,
- 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896,
- 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408,
- 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112,
- 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720,
- 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328,
- 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840,
- 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352,
- 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864,
- 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376,
- 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952,
- 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688,
- 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296,
- 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904,
- 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416,
- 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928,
- 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440,
- 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016,
- 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752,
- 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360,
- 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968,
- 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576,
- 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088,
- 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600,
- 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304,
- 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912,
- 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520,
- 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128,
- 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864,
- 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376,
- 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952,
- 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560,
- 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168,
- 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904,
- 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512,
- 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120,
- 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728,
- 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024,
- 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632,
- 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240,
- 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976,
- 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584,
- 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192,
- 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088,
- 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696,
- 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304,
- 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040,
- 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648,
- 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256,
- 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152,
- 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856,
- 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592,
- 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200,
- 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808,
- 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416,
- 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312,
- 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240,
- 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848,
- 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456,
- 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192,
- 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864,
- 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792,
- 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496,
- 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328,
- 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936,
- 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544,
- 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440,
- 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368,
- 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072,
- 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904,
- 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512,
- 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408,
- 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112,
- 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040,
- 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968,
- 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576,
- 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472,
- 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176,
- 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104,
- 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032,
- 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736,
- 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224,
- 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152,
- 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080,
- 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784,
- 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776,
- 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800,
- 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728,
- 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656,
- 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360,
- 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768,
- 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696,
- 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400,
- 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328,
- 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416,
- 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760,
- 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464,
- 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392,
- 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480,
- 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920,
- 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848,
- 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552,
- 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960,
- 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080,
- 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104,
- 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096,
- 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536,
- 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656,
- 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680,
- 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088,
- 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208,
- 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648,
- 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648,
- 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768,
- 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208,
- 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808,
- 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248,
- 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368,
- 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384,
- 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824,
- 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424,
- 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376,
- 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496,
- 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024,
- 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464,
- 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576,
- 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528,
- 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640,
- 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688,
- 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216,
- 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752,
- 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312,
- 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864,
- 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928,
- 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504,
- 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632,
- 32248,32696
-};
-
-
-const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] =
-{
- /* radix 4, size 12 */
- 8,64, 16,32, 24,96, 40,80, 56,112, 88,104
-};
-
-const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] =
-{
- /* 4x2, size 24 */
- 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144,
- 88,208, 104,176, 120,240, 152,200, 184,232
-};
-
-const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] =
-{
- /* radix 4, size 56 */
- 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352,
- 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432,
- 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472
-};
-
-const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] =
-{
- /* 4x2, size 112 */
- 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192,
- 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608,
- 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912,
- 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624,
- 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968,
- 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984
-};
-
-const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] =
-{
- /* radix 4, size 240 */
- 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640,
- 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320,
- 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960,
- 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672,
- 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376,
- 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040,
- 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912,
- 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488,
- 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456,
- 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520,
- 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928,
- 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832,
- 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816,
- 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976
-};
-
-const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] =
-{
- /* 4x2, size 480 */
- 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280,
- 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640,
- 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944,
- 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648,
- 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216,
- 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960,
- 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616,
- 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184,
- 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976,
- 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400,
- 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784,
- 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064,
- 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344,
- 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728,
- 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152,
- 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920,
- 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024,
- 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376,
- 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480,
- 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696,
- 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824,
- 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312,
- 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464,
- 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912,
- 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624,
- 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008,
- 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072,
- 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928,
- 3512,3800, 3576,4056, 3704,3896, 3832,4024
-};
-
-const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] =
-{
- /* radix 4, size 992 */
- 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608,
- 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352,
- 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864,
- 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176,
- 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688,
- 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528,
- 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040,
- 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088,
- 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696,
- 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392,
- 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904,
- 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360,
- 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544,
- 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008,
- 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080,
- 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688,
- 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432,
- 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944,
- 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304,
- 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696,
- 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536,
- 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048,
- 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168,
- 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776,
- 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960,
- 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320,
- 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784,
- 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624,
- 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112,
- 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184,
- 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368,
- 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832,
- 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264,
- 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728,
- 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008,
- 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224,
- 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664,
- 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944,
- 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352,
- 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792,
- 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072,
- 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168,
- 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400,
- 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936,
- 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784,
- 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552,
- 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208,
- 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792,
- 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000,
- 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848,
- 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664,
- 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176,
- 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384,
- 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256,
- 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512,
- 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192,
- 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496,
- 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368,
- 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112,
- 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720,
- 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312,
- 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080,
- 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504,
- 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888,
- 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680,
- 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808,
- 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512,
- 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736,
- 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056
-};
-
-const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] =
-{
- /* 4x2, size 1984 */
- 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024,
- 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512,
- 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848,
- 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680,
- 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400,
- 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520,
- 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816,
- 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080,
- 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416,
- 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248,
- 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736,
- 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856,
- 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576,
- 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408,
- 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744,
- 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232,
- 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064,
- 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208,
- 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232,
- 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720,
- 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840,
- 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560,
- 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584,
- 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072,
- 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904,
- 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240,
- 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264,
- 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752,
- 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776,
- 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496,
- 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520,
- 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008,
- 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032,
- 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272,
- 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296,
- 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784,
- 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808,
- 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432,
- 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456,
- 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944,
- 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968,
- 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496,
- 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520,
- 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888,
- 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608,
- 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536,
- 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024,
- 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048,
- 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192,
- 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408,
- 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848,
- 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872,
- 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496,
- 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712,
- 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080,
- 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416,
- 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344,
- 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024,
- 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000,
- 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624,
- 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840,
- 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208,
- 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304,
- 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280,
- 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672,
- 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888,
- 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392,
- 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072,
- 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096,
- 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288,
- 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504,
- 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776,
- 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688,
- 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664,
- 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248,
- 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272,
- 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392,
- 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736,
- 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952,
- 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648,
- 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992,
- 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016,
- 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424,
- 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008,
- 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888,
- 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680,
- 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264,
- 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240,
- 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264,
- 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848,
- 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728,
- 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520,
- 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104,
- 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080,
- 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392,
- 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976,
- 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856,
- 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648,
- 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232,
- 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112,
- 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328,
- 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864,
- 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560,
- 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632,
- 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096,
- 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528,
- 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600,
- 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064,
- 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832,
- 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296,
- 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368,
- 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272,
- 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736,
- 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600,
- 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064,
- 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136,
- 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400,
- 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960,
- 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608,
- 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240,
- 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312,
- 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824,
- 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616,
- 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128,
- 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200,
- 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560,
- 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072,
- 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816,
- 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328,
- 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840,
- 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584,
- 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048,
- 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504,
- 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992,
- 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688,
- 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296,
- 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952,
- 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672,
- 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232,
- 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080,
- 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848,
- 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336,
- 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616,
- 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152,
- 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024,
- 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280,
- 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680,
- 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576,
- 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344,
- 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184,
- 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248
-};
-
-const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] =
-{
- /* radix 4, size 4032 */
- 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048,
- 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720,
- 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312,
- 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552,
- 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608,
- 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136,
- 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728,
- 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968,
- 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640,
- 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304,
- 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976,
- 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568,
- 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808,
- 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248,
- 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912,
- 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368,
- 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032,
- 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320,
- 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176,
- 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464,
- 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632,
- 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776,
- 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832,
- 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688,
- 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976,
- 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144,
- 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288,
- 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576,
- 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432,
- 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720,
- 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888,
- 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032,
- 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088,
- 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944,
- 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232,
- 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400,
- 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544,
- 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256,
- 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496,
- 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784,
- 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376,
- 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232,
- 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152,
- 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008,
- 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296,
- 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888,
- 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744,
- 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896,
- 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560,
- 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728,
- 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392,
- 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680,
- 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312,
- 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976,
- 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432,
- 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288,
- 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576,
- 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480,
- 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720,
- 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312,
- 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840,
- 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896,
- 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136,
- 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424,
- 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016,
- 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872,
- 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024,
- 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688,
- 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856,
- 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144,
- 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808,
- 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440,
- 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104,
- 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560,
- 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224,
- 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416,
- 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464,
- 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752,
- 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344,
- 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584,
- 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640,
- 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168,
- 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760,
- 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000,
- 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288,
- 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960,
- 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624,
- 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792,
- 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456,
- 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376,
- 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424,
- 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016,
- 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256,
- 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544,
- 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832,
- 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496,
- 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472,
- 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712,
- 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152,
- 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816,
- 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272,
- 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936,
- 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800,
- 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848,
- 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136,
- 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112,
- 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776,
- 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216,
- 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456,
- 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432,
- 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096,
- 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672,
- 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720,
- 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696,
- 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744,
- 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800,
- 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848,
- 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016,
- 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064,
- 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352,
- 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024,
- 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072,
- 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048,
- 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712,
- 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152,
- 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200,
- 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176,
- 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416,
- 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704,
- 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752,
- 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728,
- 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776,
- 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216,
- 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264,
- 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240,
- 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904,
- 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056,
- 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104,
- 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080,
- 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128,
- 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568,
- 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616,
- 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592,
- 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640,
- 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496,
- 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544,
- 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520,
- 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568,
- 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008,
- 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056,
- 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032,
- 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080,
- 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560,
- 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608,
- 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584,
- 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632,
- 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456,
- 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504,
- 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480,
- 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528,
- 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576,
- 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552,
- 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408,
- 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232,
- 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280,
- 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256,
- 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304,
- 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880,
- 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928,
- 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712,
- 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760,
- 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584,
- 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632,
- 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368,
- 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464,
- 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704,
- 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584,
- 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632,
- 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880,
- 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928,
- 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288,
- 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336,
- 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768,
- 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936,
- 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984,
- 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328,
- 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184,
- 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544,
- 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592,
- 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640,
- 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808,
- 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760,
- 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008,
- 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440,
- 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176,
- 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848,
- 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088,
- 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968,
- 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824,
- 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648,
- 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384,
- 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624,
- 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528,
- 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768,
- 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504,
- 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136,
- 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088,
- 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872,
- 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304,
- 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928,
- 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808,
- 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664,
- 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248,
- 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416,
- 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368,
- 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848,
- 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584,
- 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728,
- 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360,
- 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096,
- 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336,
- 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912,
- 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152,
- 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080,
- 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424,
- 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664,
- 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592,
- 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592,
- 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520,
- 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664,
- 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296,
- 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032,
- 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176,
- 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040,
- 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968,
- 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728,
- 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312,
- 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384,
- 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624,
- 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864,
- 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936,
- 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328,
- 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472,
- 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400,
- 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976,
- 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904,
- 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048,
- 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440,
- 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512,
- 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584,
- 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728,
- 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656,
- 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192,
- 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120,
- 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264,
- 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792,
- 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720,
- 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448,
- 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376,
- 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520,
- 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664,
- 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784,
- 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080,
- 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152,
- 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968,
- 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112,
- 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944,
- 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528,
- 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360,
- 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744,
- 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768,
- 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064,
- 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184,
- 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328,
- 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048,
- 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880,
- 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368,
- 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488,
- 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824,
- 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848,
- 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336,
- 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168,
- 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128,
- 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152,
- 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640,
- 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664,
- 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664,
- 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688,
- 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176,
- 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200,
- 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824,
- 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848,
- 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528,
- 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552,
- 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768,
- 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352,
- 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376,
- 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048,
- 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976,
- 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656,
- 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680,
- 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752,
- 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144,
- 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360,
- 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056,
- 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496,
- 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616,
- 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928,
- 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464,
- 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064,
- 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136,
- 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600,
- 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744,
- 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208,
- 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280,
- 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928,
- 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488,
- 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848,
- 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264,
- 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128,
- 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640,
- 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784,
- 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296,
- 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992,
- 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600,
- 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448,
- 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168,
- 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776,
- 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312,
- 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568,
- 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160,
- 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376,
- 31480,32120, 31736,32632, 32248,32504
-};
-
-/**
-* \par
-* Example code for Floating-point RFFT Twiddle factors Generation:
-* \par
-* TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).'
-* \par
-* Real and Imag values are in interleaved fashion
-*/
-const float32_t twiddleCoef_rfft_32[32] = {
- 0.000000000f, 1.000000000f,
- 0.195090322f, 0.980785280f,
- 0.382683432f, 0.923879533f,
- 0.555570233f, 0.831469612f,
- 0.707106781f, 0.707106781f,
- 0.831469612f, 0.555570233f,
- 0.923879533f, 0.382683432f,
- 0.980785280f, 0.195090322f,
- 1.000000000f, 0.000000000f,
- 0.980785280f, -0.195090322f,
- 0.923879533f, -0.382683432f,
- 0.831469612f, -0.555570233f,
- 0.707106781f, -0.707106781f,
- 0.555570233f, -0.831469612f,
- 0.382683432f, -0.923879533f,
- 0.195090322f, -0.980785280f
-};
-
-const float32_t twiddleCoef_rfft_64[64] = {
- 0.000000000000000f, 1.000000000000000f,
- 0.098017140329561f, 0.995184726672197f,
- 0.195090322016128f, 0.980785280403230f,
- 0.290284677254462f, 0.956940335732209f,
- 0.382683432365090f, 0.923879532511287f,
- 0.471396736825998f, 0.881921264348355f,
- 0.555570233019602f, 0.831469612302545f,
- 0.634393284163645f, 0.773010453362737f,
- 0.707106781186547f, 0.707106781186548f,
- 0.773010453362737f, 0.634393284163645f,
- 0.831469612302545f, 0.555570233019602f,
- 0.881921264348355f, 0.471396736825998f,
- 0.923879532511287f, 0.382683432365090f,
- 0.956940335732209f, 0.290284677254462f,
- 0.980785280403230f, 0.195090322016128f,
- 0.995184726672197f, 0.098017140329561f,
- 1.000000000000000f, 0.000000000000000f,
- 0.995184726672197f, -0.098017140329561f,
- 0.980785280403230f, -0.195090322016128f,
- 0.956940335732209f, -0.290284677254462f,
- 0.923879532511287f, -0.382683432365090f,
- 0.881921264348355f, -0.471396736825998f,
- 0.831469612302545f, -0.555570233019602f,
- 0.773010453362737f, -0.634393284163645f,
- 0.707106781186548f, -0.707106781186547f,
- 0.634393284163645f, -0.773010453362737f,
- 0.555570233019602f, -0.831469612302545f,
- 0.471396736825998f, -0.881921264348355f,
- 0.382683432365090f, -0.923879532511287f,
- 0.290284677254462f, -0.956940335732209f,
- 0.195090322016129f, -0.980785280403230f,
- 0.098017140329561f, -0.995184726672197f
-};
-
-const float32_t twiddleCoef_rfft_128[128] = {
- 0.000000000f, 1.000000000f,
- 0.049067674f, 0.998795456f,
- 0.098017140f, 0.995184727f,
- 0.146730474f, 0.989176510f,
- 0.195090322f, 0.980785280f,
- 0.242980180f, 0.970031253f,
- 0.290284677f, 0.956940336f,
- 0.336889853f, 0.941544065f,
- 0.382683432f, 0.923879533f,
- 0.427555093f, 0.903989293f,
- 0.471396737f, 0.881921264f,
- 0.514102744f, 0.857728610f,
- 0.555570233f, 0.831469612f,
- 0.595699304f, 0.803207531f,
- 0.634393284f, 0.773010453f,
- 0.671558955f, 0.740951125f,
- 0.707106781f, 0.707106781f,
- 0.740951125f, 0.671558955f,
- 0.773010453f, 0.634393284f,
- 0.803207531f, 0.595699304f,
- 0.831469612f, 0.555570233f,
- 0.857728610f, 0.514102744f,
- 0.881921264f, 0.471396737f,
- 0.903989293f, 0.427555093f,
- 0.923879533f, 0.382683432f,
- 0.941544065f, 0.336889853f,
- 0.956940336f, 0.290284677f,
- 0.970031253f, 0.242980180f,
- 0.980785280f, 0.195090322f,
- 0.989176510f, 0.146730474f,
- 0.995184727f, 0.098017140f,
- 0.998795456f, 0.049067674f,
- 1.000000000f, 0.000000000f,
- 0.998795456f, -0.049067674f,
- 0.995184727f, -0.098017140f,
- 0.989176510f, -0.146730474f,
- 0.980785280f, -0.195090322f,
- 0.970031253f, -0.242980180f,
- 0.956940336f, -0.290284677f,
- 0.941544065f, -0.336889853f,
- 0.923879533f, -0.382683432f,
- 0.903989293f, -0.427555093f,
- 0.881921264f, -0.471396737f,
- 0.857728610f, -0.514102744f,
- 0.831469612f, -0.555570233f,
- 0.803207531f, -0.595699304f,
- 0.773010453f, -0.634393284f,
- 0.740951125f, -0.671558955f,
- 0.707106781f, -0.707106781f,
- 0.671558955f, -0.740951125f,
- 0.634393284f, -0.773010453f,
- 0.595699304f, -0.803207531f,
- 0.555570233f, -0.831469612f,
- 0.514102744f, -0.857728610f,
- 0.471396737f, -0.881921264f,
- 0.427555093f, -0.903989293f,
- 0.382683432f, -0.923879533f,
- 0.336889853f, -0.941544065f,
- 0.290284677f, -0.956940336f,
- 0.242980180f, -0.970031253f,
- 0.195090322f, -0.980785280f,
- 0.146730474f, -0.989176510f,
- 0.098017140f, -0.995184727f,
- 0.049067674f, -0.998795456f
-};
-
-const float32_t twiddleCoef_rfft_256[256] = {
- 0.000000000f, 1.000000000f,
- 0.024541229f, 0.999698819f,
- 0.049067674f, 0.998795456f,
- 0.073564564f, 0.997290457f,
- 0.098017140f, 0.995184727f,
- 0.122410675f, 0.992479535f,
- 0.146730474f, 0.989176510f,
- 0.170961889f, 0.985277642f,
- 0.195090322f, 0.980785280f,
- 0.219101240f, 0.975702130f,
- 0.242980180f, 0.970031253f,
- 0.266712757f, 0.963776066f,
- 0.290284677f, 0.956940336f,
- 0.313681740f, 0.949528181f,
- 0.336889853f, 0.941544065f,
- 0.359895037f, 0.932992799f,
- 0.382683432f, 0.923879533f,
- 0.405241314f, 0.914209756f,
- 0.427555093f, 0.903989293f,
- 0.449611330f, 0.893224301f,
- 0.471396737f, 0.881921264f,
- 0.492898192f, 0.870086991f,
- 0.514102744f, 0.857728610f,
- 0.534997620f, 0.844853565f,
- 0.555570233f, 0.831469612f,
- 0.575808191f, 0.817584813f,
- 0.595699304f, 0.803207531f,
- 0.615231591f, 0.788346428f,
- 0.634393284f, 0.773010453f,
- 0.653172843f, 0.757208847f,
- 0.671558955f, 0.740951125f,
- 0.689540545f, 0.724247083f,
- 0.707106781f, 0.707106781f,
- 0.724247083f, 0.689540545f,
- 0.740951125f, 0.671558955f,
- 0.757208847f, 0.653172843f,
- 0.773010453f, 0.634393284f,
- 0.788346428f, 0.615231591f,
- 0.803207531f, 0.595699304f,
- 0.817584813f, 0.575808191f,
- 0.831469612f, 0.555570233f,
- 0.844853565f, 0.534997620f,
- 0.857728610f, 0.514102744f,
- 0.870086991f, 0.492898192f,
- 0.881921264f, 0.471396737f,
- 0.893224301f, 0.449611330f,
- 0.903989293f, 0.427555093f,
- 0.914209756f, 0.405241314f,
- 0.923879533f, 0.382683432f,
- 0.932992799f, 0.359895037f,
- 0.941544065f, 0.336889853f,
- 0.949528181f, 0.313681740f,
- 0.956940336f, 0.290284677f,
- 0.963776066f, 0.266712757f,
- 0.970031253f, 0.242980180f,
- 0.975702130f, 0.219101240f,
- 0.980785280f, 0.195090322f,
- 0.985277642f, 0.170961889f,
- 0.989176510f, 0.146730474f,
- 0.992479535f, 0.122410675f,
- 0.995184727f, 0.098017140f,
- 0.997290457f, 0.073564564f,
- 0.998795456f, 0.049067674f,
- 0.999698819f, 0.024541229f,
- 1.000000000f, 0.000000000f,
- 0.999698819f, -0.024541229f,
- 0.998795456f, -0.049067674f,
- 0.997290457f, -0.073564564f,
- 0.995184727f, -0.098017140f,
- 0.992479535f, -0.122410675f,
- 0.989176510f, -0.146730474f,
- 0.985277642f, -0.170961889f,
- 0.980785280f, -0.195090322f,
- 0.975702130f, -0.219101240f,
- 0.970031253f, -0.242980180f,
- 0.963776066f, -0.266712757f,
- 0.956940336f, -0.290284677f,
- 0.949528181f, -0.313681740f,
- 0.941544065f, -0.336889853f,
- 0.932992799f, -0.359895037f,
- 0.923879533f, -0.382683432f,
- 0.914209756f, -0.405241314f,
- 0.903989293f, -0.427555093f,
- 0.893224301f, -0.449611330f,
- 0.881921264f, -0.471396737f,
- 0.870086991f, -0.492898192f,
- 0.857728610f, -0.514102744f,
- 0.844853565f, -0.534997620f,
- 0.831469612f, -0.555570233f,
- 0.817584813f, -0.575808191f,
- 0.803207531f, -0.595699304f,
- 0.788346428f, -0.615231591f,
- 0.773010453f, -0.634393284f,
- 0.757208847f, -0.653172843f,
- 0.740951125f, -0.671558955f,
- 0.724247083f, -0.689540545f,
- 0.707106781f, -0.707106781f,
- 0.689540545f, -0.724247083f,
- 0.671558955f, -0.740951125f,
- 0.653172843f, -0.757208847f,
- 0.634393284f, -0.773010453f,
- 0.615231591f, -0.788346428f,
- 0.595699304f, -0.803207531f,
- 0.575808191f, -0.817584813f,
- 0.555570233f, -0.831469612f,
- 0.534997620f, -0.844853565f,
- 0.514102744f, -0.857728610f,
- 0.492898192f, -0.870086991f,
- 0.471396737f, -0.881921264f,
- 0.449611330f, -0.893224301f,
- 0.427555093f, -0.903989293f,
- 0.405241314f, -0.914209756f,
- 0.382683432f, -0.923879533f,
- 0.359895037f, -0.932992799f,
- 0.336889853f, -0.941544065f,
- 0.313681740f, -0.949528181f,
- 0.290284677f, -0.956940336f,
- 0.266712757f, -0.963776066f,
- 0.242980180f, -0.970031253f,
- 0.219101240f, -0.975702130f,
- 0.195090322f, -0.980785280f,
- 0.170961889f, -0.985277642f,
- 0.146730474f, -0.989176510f,
- 0.122410675f, -0.992479535f,
- 0.098017140f, -0.995184727f,
- 0.073564564f, -0.997290457f,
- 0.049067674f, -0.998795456f,
- 0.024541229f, -0.999698819f
-};
-
-const float32_t twiddleCoef_rfft_512[512] = {
- 0.000000000f, 1.000000000f,
- 0.012271538f, 0.999924702f,
- 0.024541229f, 0.999698819f,
- 0.036807223f, 0.999322385f,
- 0.049067674f, 0.998795456f,
- 0.061320736f, 0.998118113f,
- 0.073564564f, 0.997290457f,
- 0.085797312f, 0.996312612f,
- 0.098017140f, 0.995184727f,
- 0.110222207f, 0.993906970f,
- 0.122410675f, 0.992479535f,
- 0.134580709f, 0.990902635f,
- 0.146730474f, 0.989176510f,
- 0.158858143f, 0.987301418f,
- 0.170961889f, 0.985277642f,
- 0.183039888f, 0.983105487f,
- 0.195090322f, 0.980785280f,
- 0.207111376f, 0.978317371f,
- 0.219101240f, 0.975702130f,
- 0.231058108f, 0.972939952f,
- 0.242980180f, 0.970031253f,
- 0.254865660f, 0.966976471f,
- 0.266712757f, 0.963776066f,
- 0.278519689f, 0.960430519f,
- 0.290284677f, 0.956940336f,
- 0.302005949f, 0.953306040f,
- 0.313681740f, 0.949528181f,
- 0.325310292f, 0.945607325f,
- 0.336889853f, 0.941544065f,
- 0.348418680f, 0.937339012f,
- 0.359895037f, 0.932992799f,
- 0.371317194f, 0.928506080f,
- 0.382683432f, 0.923879533f,
- 0.393992040f, 0.919113852f,
- 0.405241314f, 0.914209756f,
- 0.416429560f, 0.909167983f,
- 0.427555093f, 0.903989293f,
- 0.438616239f, 0.898674466f,
- 0.449611330f, 0.893224301f,
- 0.460538711f, 0.887639620f,
- 0.471396737f, 0.881921264f,
- 0.482183772f, 0.876070094f,
- 0.492898192f, 0.870086991f,
- 0.503538384f, 0.863972856f,
- 0.514102744f, 0.857728610f,
- 0.524589683f, 0.851355193f,
- 0.534997620f, 0.844853565f,
- 0.545324988f, 0.838224706f,
- 0.555570233f, 0.831469612f,
- 0.565731811f, 0.824589303f,
- 0.575808191f, 0.817584813f,
- 0.585797857f, 0.810457198f,
- 0.595699304f, 0.803207531f,
- 0.605511041f, 0.795836905f,
- 0.615231591f, 0.788346428f,
- 0.624859488f, 0.780737229f,
- 0.634393284f, 0.773010453f,
- 0.643831543f, 0.765167266f,
- 0.653172843f, 0.757208847f,
- 0.662415778f, 0.749136395f,
- 0.671558955f, 0.740951125f,
- 0.680600998f, 0.732654272f,
- 0.689540545f, 0.724247083f,
- 0.698376249f, 0.715730825f,
- 0.707106781f, 0.707106781f,
- 0.715730825f, 0.698376249f,
- 0.724247083f, 0.689540545f,
- 0.732654272f, 0.680600998f,
- 0.740951125f, 0.671558955f,
- 0.749136395f, 0.662415778f,
- 0.757208847f, 0.653172843f,
- 0.765167266f, 0.643831543f,
- 0.773010453f, 0.634393284f,
- 0.780737229f, 0.624859488f,
- 0.788346428f, 0.615231591f,
- 0.795836905f, 0.605511041f,
- 0.803207531f, 0.595699304f,
- 0.810457198f, 0.585797857f,
- 0.817584813f, 0.575808191f,
- 0.824589303f, 0.565731811f,
- 0.831469612f, 0.555570233f,
- 0.838224706f, 0.545324988f,
- 0.844853565f, 0.534997620f,
- 0.851355193f, 0.524589683f,
- 0.857728610f, 0.514102744f,
- 0.863972856f, 0.503538384f,
- 0.870086991f, 0.492898192f,
- 0.876070094f, 0.482183772f,
- 0.881921264f, 0.471396737f,
- 0.887639620f, 0.460538711f,
- 0.893224301f, 0.449611330f,
- 0.898674466f, 0.438616239f,
- 0.903989293f, 0.427555093f,
- 0.909167983f, 0.416429560f,
- 0.914209756f, 0.405241314f,
- 0.919113852f, 0.393992040f,
- 0.923879533f, 0.382683432f,
- 0.928506080f, 0.371317194f,
- 0.932992799f, 0.359895037f,
- 0.937339012f, 0.348418680f,
- 0.941544065f, 0.336889853f,
- 0.945607325f, 0.325310292f,
- 0.949528181f, 0.313681740f,
- 0.953306040f, 0.302005949f,
- 0.956940336f, 0.290284677f,
- 0.960430519f, 0.278519689f,
- 0.963776066f, 0.266712757f,
- 0.966976471f, 0.254865660f,
- 0.970031253f, 0.242980180f,
- 0.972939952f, 0.231058108f,
- 0.975702130f, 0.219101240f,
- 0.978317371f, 0.207111376f,
- 0.980785280f, 0.195090322f,
- 0.983105487f, 0.183039888f,
- 0.985277642f, 0.170961889f,
- 0.987301418f, 0.158858143f,
- 0.989176510f, 0.146730474f,
- 0.990902635f, 0.134580709f,
- 0.992479535f, 0.122410675f,
- 0.993906970f, 0.110222207f,
- 0.995184727f, 0.098017140f,
- 0.996312612f, 0.085797312f,
- 0.997290457f, 0.073564564f,
- 0.998118113f, 0.061320736f,
- 0.998795456f, 0.049067674f,
- 0.999322385f, 0.036807223f,
- 0.999698819f, 0.024541229f,
- 0.999924702f, 0.012271538f,
- 1.000000000f, 0.000000000f,
- 0.999924702f, -0.012271538f,
- 0.999698819f, -0.024541229f,
- 0.999322385f, -0.036807223f,
- 0.998795456f, -0.049067674f,
- 0.998118113f, -0.061320736f,
- 0.997290457f, -0.073564564f,
- 0.996312612f, -0.085797312f,
- 0.995184727f, -0.098017140f,
- 0.993906970f, -0.110222207f,
- 0.992479535f, -0.122410675f,
- 0.990902635f, -0.134580709f,
- 0.989176510f, -0.146730474f,
- 0.987301418f, -0.158858143f,
- 0.985277642f, -0.170961889f,
- 0.983105487f, -0.183039888f,
- 0.980785280f, -0.195090322f,
- 0.978317371f, -0.207111376f,
- 0.975702130f, -0.219101240f,
- 0.972939952f, -0.231058108f,
- 0.970031253f, -0.242980180f,
- 0.966976471f, -0.254865660f,
- 0.963776066f, -0.266712757f,
- 0.960430519f, -0.278519689f,
- 0.956940336f, -0.290284677f,
- 0.953306040f, -0.302005949f,
- 0.949528181f, -0.313681740f,
- 0.945607325f, -0.325310292f,
- 0.941544065f, -0.336889853f,
- 0.937339012f, -0.348418680f,
- 0.932992799f, -0.359895037f,
- 0.928506080f, -0.371317194f,
- 0.923879533f, -0.382683432f,
- 0.919113852f, -0.393992040f,
- 0.914209756f, -0.405241314f,
- 0.909167983f, -0.416429560f,
- 0.903989293f, -0.427555093f,
- 0.898674466f, -0.438616239f,
- 0.893224301f, -0.449611330f,
- 0.887639620f, -0.460538711f,
- 0.881921264f, -0.471396737f,
- 0.876070094f, -0.482183772f,
- 0.870086991f, -0.492898192f,
- 0.863972856f, -0.503538384f,
- 0.857728610f, -0.514102744f,
- 0.851355193f, -0.524589683f,
- 0.844853565f, -0.534997620f,
- 0.838224706f, -0.545324988f,
- 0.831469612f, -0.555570233f,
- 0.824589303f, -0.565731811f,
- 0.817584813f, -0.575808191f,
- 0.810457198f, -0.585797857f,
- 0.803207531f, -0.595699304f,
- 0.795836905f, -0.605511041f,
- 0.788346428f, -0.615231591f,
- 0.780737229f, -0.624859488f,
- 0.773010453f, -0.634393284f,
- 0.765167266f, -0.643831543f,
- 0.757208847f, -0.653172843f,
- 0.749136395f, -0.662415778f,
- 0.740951125f, -0.671558955f,
- 0.732654272f, -0.680600998f,
- 0.724247083f, -0.689540545f,
- 0.715730825f, -0.698376249f,
- 0.707106781f, -0.707106781f,
- 0.698376249f, -0.715730825f,
- 0.689540545f, -0.724247083f,
- 0.680600998f, -0.732654272f,
- 0.671558955f, -0.740951125f,
- 0.662415778f, -0.749136395f,
- 0.653172843f, -0.757208847f,
- 0.643831543f, -0.765167266f,
- 0.634393284f, -0.773010453f,
- 0.624859488f, -0.780737229f,
- 0.615231591f, -0.788346428f,
- 0.605511041f, -0.795836905f,
- 0.595699304f, -0.803207531f,
- 0.585797857f, -0.810457198f,
- 0.575808191f, -0.817584813f,
- 0.565731811f, -0.824589303f,
- 0.555570233f, -0.831469612f,
- 0.545324988f, -0.838224706f,
- 0.534997620f, -0.844853565f,
- 0.524589683f, -0.851355193f,
- 0.514102744f, -0.857728610f,
- 0.503538384f, -0.863972856f,
- 0.492898192f, -0.870086991f,
- 0.482183772f, -0.876070094f,
- 0.471396737f, -0.881921264f,
- 0.460538711f, -0.887639620f,
- 0.449611330f, -0.893224301f,
- 0.438616239f, -0.898674466f,
- 0.427555093f, -0.903989293f,
- 0.416429560f, -0.909167983f,
- 0.405241314f, -0.914209756f,
- 0.393992040f, -0.919113852f,
- 0.382683432f, -0.923879533f,
- 0.371317194f, -0.928506080f,
- 0.359895037f, -0.932992799f,
- 0.348418680f, -0.937339012f,
- 0.336889853f, -0.941544065f,
- 0.325310292f, -0.945607325f,
- 0.313681740f, -0.949528181f,
- 0.302005949f, -0.953306040f,
- 0.290284677f, -0.956940336f,
- 0.278519689f, -0.960430519f,
- 0.266712757f, -0.963776066f,
- 0.254865660f, -0.966976471f,
- 0.242980180f, -0.970031253f,
- 0.231058108f, -0.972939952f,
- 0.219101240f, -0.975702130f,
- 0.207111376f, -0.978317371f,
- 0.195090322f, -0.980785280f,
- 0.183039888f, -0.983105487f,
- 0.170961889f, -0.985277642f,
- 0.158858143f, -0.987301418f,
- 0.146730474f, -0.989176510f,
- 0.134580709f, -0.990902635f,
- 0.122410675f, -0.992479535f,
- 0.110222207f, -0.993906970f,
- 0.098017140f, -0.995184727f,
- 0.085797312f, -0.996312612f,
- 0.073564564f, -0.997290457f,
- 0.061320736f, -0.998118113f,
- 0.049067674f, -0.998795456f,
- 0.036807223f, -0.999322385f,
- 0.024541229f, -0.999698819f,
- 0.012271538f, -0.999924702f
-};
-
-const float32_t twiddleCoef_rfft_1024[1024] = {
- 0.000000000f, 1.000000000f,
- 0.006135885f, 0.999981175f,
- 0.012271538f, 0.999924702f,
- 0.018406730f, 0.999830582f,
- 0.024541229f, 0.999698819f,
- 0.030674803f, 0.999529418f,
- 0.036807223f, 0.999322385f,
- 0.042938257f, 0.999077728f,
- 0.049067674f, 0.998795456f,
- 0.055195244f, 0.998475581f,
- 0.061320736f, 0.998118113f,
- 0.067443920f, 0.997723067f,
- 0.073564564f, 0.997290457f,
- 0.079682438f, 0.996820299f,
- 0.085797312f, 0.996312612f,
- 0.091908956f, 0.995767414f,
- 0.098017140f, 0.995184727f,
- 0.104121634f, 0.994564571f,
- 0.110222207f, 0.993906970f,
- 0.116318631f, 0.993211949f,
- 0.122410675f, 0.992479535f,
- 0.128498111f, 0.991709754f,
- 0.134580709f, 0.990902635f,
- 0.140658239f, 0.990058210f,
- 0.146730474f, 0.989176510f,
- 0.152797185f, 0.988257568f,
- 0.158858143f, 0.987301418f,
- 0.164913120f, 0.986308097f,
- 0.170961889f, 0.985277642f,
- 0.177004220f, 0.984210092f,
- 0.183039888f, 0.983105487f,
- 0.189068664f, 0.981963869f,
- 0.195090322f, 0.980785280f,
- 0.201104635f, 0.979569766f,
- 0.207111376f, 0.978317371f,
- 0.213110320f, 0.977028143f,
- 0.219101240f, 0.975702130f,
- 0.225083911f, 0.974339383f,
- 0.231058108f, 0.972939952f,
- 0.237023606f, 0.971503891f,
- 0.242980180f, 0.970031253f,
- 0.248927606f, 0.968522094f,
- 0.254865660f, 0.966976471f,
- 0.260794118f, 0.965394442f,
- 0.266712757f, 0.963776066f,
- 0.272621355f, 0.962121404f,
- 0.278519689f, 0.960430519f,
- 0.284407537f, 0.958703475f,
- 0.290284677f, 0.956940336f,
- 0.296150888f, 0.955141168f,
- 0.302005949f, 0.953306040f,
- 0.307849640f, 0.951435021f,
- 0.313681740f, 0.949528181f,
- 0.319502031f, 0.947585591f,
- 0.325310292f, 0.945607325f,
- 0.331106306f, 0.943593458f,
- 0.336889853f, 0.941544065f,
- 0.342660717f, 0.939459224f,
- 0.348418680f, 0.937339012f,
- 0.354163525f, 0.935183510f,
- 0.359895037f, 0.932992799f,
- 0.365612998f, 0.930766961f,
- 0.371317194f, 0.928506080f,
- 0.377007410f, 0.926210242f,
- 0.382683432f, 0.923879533f,
- 0.388345047f, 0.921514039f,
- 0.393992040f, 0.919113852f,
- 0.399624200f, 0.916679060f,
- 0.405241314f, 0.914209756f,
- 0.410843171f, 0.911706032f,
- 0.416429560f, 0.909167983f,
- 0.422000271f, 0.906595705f,
- 0.427555093f, 0.903989293f,
- 0.433093819f, 0.901348847f,
- 0.438616239f, 0.898674466f,
- 0.444122145f, 0.895966250f,
- 0.449611330f, 0.893224301f,
- 0.455083587f, 0.890448723f,
- 0.460538711f, 0.887639620f,
- 0.465976496f, 0.884797098f,
- 0.471396737f, 0.881921264f,
- 0.476799230f, 0.879012226f,
- 0.482183772f, 0.876070094f,
- 0.487550160f, 0.873094978f,
- 0.492898192f, 0.870086991f,
- 0.498227667f, 0.867046246f,
- 0.503538384f, 0.863972856f,
- 0.508830143f, 0.860866939f,
- 0.514102744f, 0.857728610f,
- 0.519355990f, 0.854557988f,
- 0.524589683f, 0.851355193f,
- 0.529803625f, 0.848120345f,
- 0.534997620f, 0.844853565f,
- 0.540171473f, 0.841554977f,
- 0.545324988f, 0.838224706f,
- 0.550457973f, 0.834862875f,
- 0.555570233f, 0.831469612f,
- 0.560661576f, 0.828045045f,
- 0.565731811f, 0.824589303f,
- 0.570780746f, 0.821102515f,
- 0.575808191f, 0.817584813f,
- 0.580813958f, 0.814036330f,
- 0.585797857f, 0.810457198f,
- 0.590759702f, 0.806847554f,
- 0.595699304f, 0.803207531f,
- 0.600616479f, 0.799537269f,
- 0.605511041f, 0.795836905f,
- 0.610382806f, 0.792106577f,
- 0.615231591f, 0.788346428f,
- 0.620057212f, 0.784556597f,
- 0.624859488f, 0.780737229f,
- 0.629638239f, 0.776888466f,
- 0.634393284f, 0.773010453f,
- 0.639124445f, 0.769103338f,
- 0.643831543f, 0.765167266f,
- 0.648514401f, 0.761202385f,
- 0.653172843f, 0.757208847f,
- 0.657806693f, 0.753186799f,
- 0.662415778f, 0.749136395f,
- 0.666999922f, 0.745057785f,
- 0.671558955f, 0.740951125f,
- 0.676092704f, 0.736816569f,
- 0.680600998f, 0.732654272f,
- 0.685083668f, 0.728464390f,
- 0.689540545f, 0.724247083f,
- 0.693971461f, 0.720002508f,
- 0.698376249f, 0.715730825f,
- 0.702754744f, 0.711432196f,
- 0.707106781f, 0.707106781f,
- 0.711432196f, 0.702754744f,
- 0.715730825f, 0.698376249f,
- 0.720002508f, 0.693971461f,
- 0.724247083f, 0.689540545f,
- 0.728464390f, 0.685083668f,
- 0.732654272f, 0.680600998f,
- 0.736816569f, 0.676092704f,
- 0.740951125f, 0.671558955f,
- 0.745057785f, 0.666999922f,
- 0.749136395f, 0.662415778f,
- 0.753186799f, 0.657806693f,
- 0.757208847f, 0.653172843f,
- 0.761202385f, 0.648514401f,
- 0.765167266f, 0.643831543f,
- 0.769103338f, 0.639124445f,
- 0.773010453f, 0.634393284f,
- 0.776888466f, 0.629638239f,
- 0.780737229f, 0.624859488f,
- 0.784556597f, 0.620057212f,
- 0.788346428f, 0.615231591f,
- 0.792106577f, 0.610382806f,
- 0.795836905f, 0.605511041f,
- 0.799537269f, 0.600616479f,
- 0.803207531f, 0.595699304f,
- 0.806847554f, 0.590759702f,
- 0.810457198f, 0.585797857f,
- 0.814036330f, 0.580813958f,
- 0.817584813f, 0.575808191f,
- 0.821102515f, 0.570780746f,
- 0.824589303f, 0.565731811f,
- 0.828045045f, 0.560661576f,
- 0.831469612f, 0.555570233f,
- 0.834862875f, 0.550457973f,
- 0.838224706f, 0.545324988f,
- 0.841554977f, 0.540171473f,
- 0.844853565f, 0.534997620f,
- 0.848120345f, 0.529803625f,
- 0.851355193f, 0.524589683f,
- 0.854557988f, 0.519355990f,
- 0.857728610f, 0.514102744f,
- 0.860866939f, 0.508830143f,
- 0.863972856f, 0.503538384f,
- 0.867046246f, 0.498227667f,
- 0.870086991f, 0.492898192f,
- 0.873094978f, 0.487550160f,
- 0.876070094f, 0.482183772f,
- 0.879012226f, 0.476799230f,
- 0.881921264f, 0.471396737f,
- 0.884797098f, 0.465976496f,
- 0.887639620f, 0.460538711f,
- 0.890448723f, 0.455083587f,
- 0.893224301f, 0.449611330f,
- 0.895966250f, 0.444122145f,
- 0.898674466f, 0.438616239f,
- 0.901348847f, 0.433093819f,
- 0.903989293f, 0.427555093f,
- 0.906595705f, 0.422000271f,
- 0.909167983f, 0.416429560f,
- 0.911706032f, 0.410843171f,
- 0.914209756f, 0.405241314f,
- 0.916679060f, 0.399624200f,
- 0.919113852f, 0.393992040f,
- 0.921514039f, 0.388345047f,
- 0.923879533f, 0.382683432f,
- 0.926210242f, 0.377007410f,
- 0.928506080f, 0.371317194f,
- 0.930766961f, 0.365612998f,
- 0.932992799f, 0.359895037f,
- 0.935183510f, 0.354163525f,
- 0.937339012f, 0.348418680f,
- 0.939459224f, 0.342660717f,
- 0.941544065f, 0.336889853f,
- 0.943593458f, 0.331106306f,
- 0.945607325f, 0.325310292f,
- 0.947585591f, 0.319502031f,
- 0.949528181f, 0.313681740f,
- 0.951435021f, 0.307849640f,
- 0.953306040f, 0.302005949f,
- 0.955141168f, 0.296150888f,
- 0.956940336f, 0.290284677f,
- 0.958703475f, 0.284407537f,
- 0.960430519f, 0.278519689f,
- 0.962121404f, 0.272621355f,
- 0.963776066f, 0.266712757f,
- 0.965394442f, 0.260794118f,
- 0.966976471f, 0.254865660f,
- 0.968522094f, 0.248927606f,
- 0.970031253f, 0.242980180f,
- 0.971503891f, 0.237023606f,
- 0.972939952f, 0.231058108f,
- 0.974339383f, 0.225083911f,
- 0.975702130f, 0.219101240f,
- 0.977028143f, 0.213110320f,
- 0.978317371f, 0.207111376f,
- 0.979569766f, 0.201104635f,
- 0.980785280f, 0.195090322f,
- 0.981963869f, 0.189068664f,
- 0.983105487f, 0.183039888f,
- 0.984210092f, 0.177004220f,
- 0.985277642f, 0.170961889f,
- 0.986308097f, 0.164913120f,
- 0.987301418f, 0.158858143f,
- 0.988257568f, 0.152797185f,
- 0.989176510f, 0.146730474f,
- 0.990058210f, 0.140658239f,
- 0.990902635f, 0.134580709f,
- 0.991709754f, 0.128498111f,
- 0.992479535f, 0.122410675f,
- 0.993211949f, 0.116318631f,
- 0.993906970f, 0.110222207f,
- 0.994564571f, 0.104121634f,
- 0.995184727f, 0.098017140f,
- 0.995767414f, 0.091908956f,
- 0.996312612f, 0.085797312f,
- 0.996820299f, 0.079682438f,
- 0.997290457f, 0.073564564f,
- 0.997723067f, 0.067443920f,
- 0.998118113f, 0.061320736f,
- 0.998475581f, 0.055195244f,
- 0.998795456f, 0.049067674f,
- 0.999077728f, 0.042938257f,
- 0.999322385f, 0.036807223f,
- 0.999529418f, 0.030674803f,
- 0.999698819f, 0.024541229f,
- 0.999830582f, 0.018406730f,
- 0.999924702f, 0.012271538f,
- 0.999981175f, 0.006135885f,
- 1.000000000f, 0.000000000f,
- 0.999981175f, -0.006135885f,
- 0.999924702f, -0.012271538f,
- 0.999830582f, -0.018406730f,
- 0.999698819f, -0.024541229f,
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- 0.999322385f, -0.036807223f,
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- 0.998795456f, -0.049067674f,
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- 0.995767414f, -0.091908956f,
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- 0.994564571f, -0.104121634f,
- 0.993906970f, -0.110222207f,
- 0.993211949f, -0.116318631f,
- 0.992479535f, -0.122410675f,
- 0.991709754f, -0.128498111f,
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- 0.773010453f, -0.634393284f,
- 0.769103338f, -0.639124445f,
- 0.765167266f, -0.643831543f,
- 0.761202385f, -0.648514401f,
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- 0.753186799f, -0.657806693f,
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- 0.745057785f, -0.666999922f,
- 0.740951125f, -0.671558955f,
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- 0.702754744f, -0.711432196f,
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- 0.689540545f, -0.724247083f,
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- 0.560661576f, -0.828045045f,
- 0.555570233f, -0.831469612f,
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- 0.545324988f, -0.838224706f,
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- 0.296150888f, -0.955141168f,
- 0.290284677f, -0.956940336f,
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- 0.248927606f, -0.968522094f,
- 0.242980180f, -0.970031253f,
- 0.237023606f, -0.971503891f,
- 0.231058108f, -0.972939952f,
- 0.225083911f, -0.974339383f,
- 0.219101240f, -0.975702130f,
- 0.213110320f, -0.977028143f,
- 0.207111376f, -0.978317371f,
- 0.201104635f, -0.979569766f,
- 0.195090322f, -0.980785280f,
- 0.189068664f, -0.981963869f,
- 0.183039888f, -0.983105487f,
- 0.177004220f, -0.984210092f,
- 0.170961889f, -0.985277642f,
- 0.164913120f, -0.986308097f,
- 0.158858143f, -0.987301418f,
- 0.152797185f, -0.988257568f,
- 0.146730474f, -0.989176510f,
- 0.140658239f, -0.990058210f,
- 0.134580709f, -0.990902635f,
- 0.128498111f, -0.991709754f,
- 0.122410675f, -0.992479535f,
- 0.116318631f, -0.993211949f,
- 0.110222207f, -0.993906970f,
- 0.104121634f, -0.994564571f,
- 0.098017140f, -0.995184727f,
- 0.091908956f, -0.995767414f,
- 0.085797312f, -0.996312612f,
- 0.079682438f, -0.996820299f,
- 0.073564564f, -0.997290457f,
- 0.067443920f, -0.997723067f,
- 0.061320736f, -0.998118113f,
- 0.055195244f, -0.998475581f,
- 0.049067674f, -0.998795456f,
- 0.042938257f, -0.999077728f,
- 0.036807223f, -0.999322385f,
- 0.030674803f, -0.999529418f,
- 0.024541229f, -0.999698819f,
- 0.018406730f, -0.999830582f,
- 0.012271538f, -0.999924702f,
- 0.006135885f, -0.999981175f
-};
-
-const float32_t twiddleCoef_rfft_2048[2048] = {
- 0.000000000f, 1.000000000f,
- 0.003067957f, 0.999995294f,
- 0.006135885f, 0.999981175f,
- 0.009203755f, 0.999957645f,
- 0.012271538f, 0.999924702f,
- 0.015339206f, 0.999882347f,
- 0.018406730f, 0.999830582f,
- 0.021474080f, 0.999769405f,
- 0.024541229f, 0.999698819f,
- 0.027608146f, 0.999618822f,
- 0.030674803f, 0.999529418f,
- 0.033741172f, 0.999430605f,
- 0.036807223f, 0.999322385f,
- 0.039872928f, 0.999204759f,
- 0.042938257f, 0.999077728f,
- 0.046003182f, 0.998941293f,
- 0.049067674f, 0.998795456f,
- 0.052131705f, 0.998640218f,
- 0.055195244f, 0.998475581f,
- 0.058258265f, 0.998301545f,
- 0.061320736f, 0.998118113f,
- 0.064382631f, 0.997925286f,
- 0.067443920f, 0.997723067f,
- 0.070504573f, 0.997511456f,
- 0.073564564f, 0.997290457f,
- 0.076623861f, 0.997060070f,
- 0.079682438f, 0.996820299f,
- 0.082740265f, 0.996571146f,
- 0.085797312f, 0.996312612f,
- 0.088853553f, 0.996044701f,
- 0.091908956f, 0.995767414f,
- 0.094963495f, 0.995480755f,
- 0.098017140f, 0.995184727f,
- 0.101069863f, 0.994879331f,
- 0.104121634f, 0.994564571f,
- 0.107172425f, 0.994240449f,
- 0.110222207f, 0.993906970f,
- 0.113270952f, 0.993564136f,
- 0.116318631f, 0.993211949f,
- 0.119365215f, 0.992850414f,
- 0.122410675f, 0.992479535f,
- 0.125454983f, 0.992099313f,
- 0.128498111f, 0.991709754f,
- 0.131540029f, 0.991310860f,
- 0.134580709f, 0.990902635f,
- 0.137620122f, 0.990485084f,
- 0.140658239f, 0.990058210f,
- 0.143695033f, 0.989622017f,
- 0.146730474f, 0.989176510f,
- 0.149764535f, 0.988721692f,
- 0.152797185f, 0.988257568f,
- 0.155828398f, 0.987784142f,
- 0.158858143f, 0.987301418f,
- 0.161886394f, 0.986809402f,
- 0.164913120f, 0.986308097f,
- 0.167938295f, 0.985797509f,
- 0.170961889f, 0.985277642f,
- 0.173983873f, 0.984748502f,
- 0.177004220f, 0.984210092f,
- 0.180022901f, 0.983662419f,
- 0.183039888f, 0.983105487f,
- 0.186055152f, 0.982539302f,
- 0.189068664f, 0.981963869f,
- 0.192080397f, 0.981379193f,
- 0.195090322f, 0.980785280f,
- 0.198098411f, 0.980182136f,
- 0.201104635f, 0.979569766f,
- 0.204108966f, 0.978948175f,
- 0.207111376f, 0.978317371f,
- 0.210111837f, 0.977677358f,
- 0.213110320f, 0.977028143f,
- 0.216106797f, 0.976369731f,
- 0.219101240f, 0.975702130f,
- 0.222093621f, 0.975025345f,
- 0.225083911f, 0.974339383f,
- 0.228072083f, 0.973644250f,
- 0.231058108f, 0.972939952f,
- 0.234041959f, 0.972226497f,
- 0.237023606f, 0.971503891f,
- 0.240003022f, 0.970772141f,
- 0.242980180f, 0.970031253f,
- 0.245955050f, 0.969281235f,
- 0.248927606f, 0.968522094f,
- 0.251897818f, 0.967753837f,
- 0.254865660f, 0.966976471f,
- 0.257831102f, 0.966190003f,
- 0.260794118f, 0.965394442f,
- 0.263754679f, 0.964589793f,
- 0.266712757f, 0.963776066f,
- 0.269668326f, 0.962953267f,
- 0.272621355f, 0.962121404f,
- 0.275571819f, 0.961280486f,
- 0.278519689f, 0.960430519f,
- 0.281464938f, 0.959571513f,
- 0.284407537f, 0.958703475f,
- 0.287347460f, 0.957826413f,
- 0.290284677f, 0.956940336f,
- 0.293219163f, 0.956045251f,
- 0.296150888f, 0.955141168f,
- 0.299079826f, 0.954228095f,
- 0.302005949f, 0.953306040f,
- 0.304929230f, 0.952375013f,
- 0.307849640f, 0.951435021f,
- 0.310767153f, 0.950486074f,
- 0.313681740f, 0.949528181f,
- 0.316593376f, 0.948561350f,
- 0.319502031f, 0.947585591f,
- 0.322407679f, 0.946600913f,
- 0.325310292f, 0.945607325f,
- 0.328209844f, 0.944604837f,
- 0.331106306f, 0.943593458f,
- 0.333999651f, 0.942573198f,
- 0.336889853f, 0.941544065f,
- 0.339776884f, 0.940506071f,
- 0.342660717f, 0.939459224f,
- 0.345541325f, 0.938403534f,
- 0.348418680f, 0.937339012f,
- 0.351292756f, 0.936265667f,
- 0.354163525f, 0.935183510f,
- 0.357030961f, 0.934092550f,
- 0.359895037f, 0.932992799f,
- 0.362755724f, 0.931884266f,
- 0.365612998f, 0.930766961f,
- 0.368466830f, 0.929640896f,
- 0.371317194f, 0.928506080f,
- 0.374164063f, 0.927362526f,
- 0.377007410f, 0.926210242f,
- 0.379847209f, 0.925049241f,
- 0.382683432f, 0.923879533f,
- 0.385516054f, 0.922701128f,
- 0.388345047f, 0.921514039f,
- 0.391170384f, 0.920318277f,
- 0.393992040f, 0.919113852f,
- 0.396809987f, 0.917900776f,
- 0.399624200f, 0.916679060f,
- 0.402434651f, 0.915448716f,
- 0.405241314f, 0.914209756f,
- 0.408044163f, 0.912962190f,
- 0.410843171f, 0.911706032f,
- 0.413638312f, 0.910441292f,
- 0.416429560f, 0.909167983f,
- 0.419216888f, 0.907886116f,
- 0.422000271f, 0.906595705f,
- 0.424779681f, 0.905296759f,
- 0.427555093f, 0.903989293f,
- 0.430326481f, 0.902673318f,
- 0.433093819f, 0.901348847f,
- 0.435857080f, 0.900015892f,
- 0.438616239f, 0.898674466f,
- 0.441371269f, 0.897324581f,
- 0.444122145f, 0.895966250f,
- 0.446868840f, 0.894599486f,
- 0.449611330f, 0.893224301f,
- 0.452349587f, 0.891840709f,
- 0.455083587f, 0.890448723f,
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- 0.460538711f, 0.887639620f,
- 0.463259784f, 0.886222530f,
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- 0.471396737f, 0.881921264f,
- 0.474100215f, 0.880470889f,
- 0.476799230f, 0.879012226f,
- 0.479493758f, 0.877545290f,
- 0.482183772f, 0.876070094f,
- 0.484869248f, 0.874586652f,
- 0.487550160f, 0.873094978f,
- 0.490226483f, 0.871595087f,
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- 0.547894059f, 0.836547727f,
- 0.550457973f, 0.834862875f,
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- 0.555570233f, 0.831469612f,
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- 0.650846685f, 0.759209189f,
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- 0.753186799f, 0.657806693f,
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-};
-
-const float32_t twiddleCoef_rfft_4096[4096] = {
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- 0.384100195f, -0.923291417f,
- 0.382683432f, -0.923879533f,
- 0.381265769f, -0.924465474f,
- 0.379847209f, -0.925049241f,
- 0.378427755f, -0.925630831f,
- 0.377007410f, -0.926210242f,
- 0.375586178f, -0.926787474f,
- 0.374164063f, -0.927362526f,
- 0.372741067f, -0.927935395f,
- 0.371317194f, -0.928506080f,
- 0.369892447f, -0.929074581f,
- 0.368466830f, -0.929640896f,
- 0.367040346f, -0.930205023f,
- 0.365612998f, -0.930766961f,
- 0.364184790f, -0.931326709f,
- 0.362755724f, -0.931884266f,
- 0.361325806f, -0.932439629f,
- 0.359895037f, -0.932992799f,
- 0.358463421f, -0.933543773f,
- 0.357030961f, -0.934092550f,
- 0.355597662f, -0.934639130f,
- 0.354163525f, -0.935183510f,
- 0.352728556f, -0.935725689f,
- 0.351292756f, -0.936265667f,
- 0.349856130f, -0.936803442f,
- 0.348418680f, -0.937339012f,
- 0.346980411f, -0.937872376f,
- 0.345541325f, -0.938403534f,
- 0.344101426f, -0.938932484f,
- 0.342660717f, -0.939459224f,
- 0.341219202f, -0.939983753f,
- 0.339776884f, -0.940506071f,
- 0.338333767f, -0.941026175f,
- 0.336889853f, -0.941544065f,
- 0.335445147f, -0.942059740f,
- 0.333999651f, -0.942573198f,
- 0.332553370f, -0.943084437f,
- 0.331106306f, -0.943593458f,
- 0.329658463f, -0.944100258f,
- 0.328209844f, -0.944604837f,
- 0.326760452f, -0.945107193f,
- 0.325310292f, -0.945607325f,
- 0.323859367f, -0.946105232f,
- 0.322407679f, -0.946600913f,
- 0.320955232f, -0.947094366f,
- 0.319502031f, -0.947585591f,
- 0.318048077f, -0.948074586f,
- 0.316593376f, -0.948561350f,
- 0.315137929f, -0.949045882f,
- 0.313681740f, -0.949528181f,
- 0.312224814f, -0.950008245f,
- 0.310767153f, -0.950486074f,
- 0.309308760f, -0.950961666f,
- 0.307849640f, -0.951435021f,
- 0.306389795f, -0.951906137f,
- 0.304929230f, -0.952375013f,
- 0.303467947f, -0.952841648f,
- 0.302005949f, -0.953306040f,
- 0.300543241f, -0.953768190f,
- 0.299079826f, -0.954228095f,
- 0.297615707f, -0.954685755f,
- 0.296150888f, -0.955141168f,
- 0.294685372f, -0.955594334f,
- 0.293219163f, -0.956045251f,
- 0.291752263f, -0.956493919f,
- 0.290284677f, -0.956940336f,
- 0.288816408f, -0.957384501f,
- 0.287347460f, -0.957826413f,
- 0.285877835f, -0.958266071f,
- 0.284407537f, -0.958703475f,
- 0.282936570f, -0.959138622f,
- 0.281464938f, -0.959571513f,
- 0.279992643f, -0.960002146f,
- 0.278519689f, -0.960430519f,
- 0.277046080f, -0.960856633f,
- 0.275571819f, -0.961280486f,
- 0.274096910f, -0.961702077f,
- 0.272621355f, -0.962121404f,
- 0.271145160f, -0.962538468f,
- 0.269668326f, -0.962953267f,
- 0.268190857f, -0.963365800f,
- 0.266712757f, -0.963776066f,
- 0.265234030f, -0.964184064f,
- 0.263754679f, -0.964589793f,
- 0.262274707f, -0.964993253f,
- 0.260794118f, -0.965394442f,
- 0.259312915f, -0.965793359f,
- 0.257831102f, -0.966190003f,
- 0.256348682f, -0.966584374f,
- 0.254865660f, -0.966976471f,
- 0.253382037f, -0.967366292f,
- 0.251897818f, -0.967753837f,
- 0.250413007f, -0.968139105f,
- 0.248927606f, -0.968522094f,
- 0.247441619f, -0.968902805f,
- 0.245955050f, -0.969281235f,
- 0.244467903f, -0.969657385f,
- 0.242980180f, -0.970031253f,
- 0.241491885f, -0.970402839f,
- 0.240003022f, -0.970772141f,
- 0.238513595f, -0.971139158f,
- 0.237023606f, -0.971503891f,
- 0.235533059f, -0.971866337f,
- 0.234041959f, -0.972226497f,
- 0.232550307f, -0.972584369f,
- 0.231058108f, -0.972939952f,
- 0.229565366f, -0.973293246f,
- 0.228072083f, -0.973644250f,
- 0.226578264f, -0.973992962f,
- 0.225083911f, -0.974339383f,
- 0.223589029f, -0.974683511f,
- 0.222093621f, -0.975025345f,
- 0.220597690f, -0.975364885f,
- 0.219101240f, -0.975702130f,
- 0.217604275f, -0.976037079f,
- 0.216106797f, -0.976369731f,
- 0.214608811f, -0.976700086f,
- 0.213110320f, -0.977028143f,
- 0.211611327f, -0.977353900f,
- 0.210111837f, -0.977677358f,
- 0.208611852f, -0.977998515f,
- 0.207111376f, -0.978317371f,
- 0.205610413f, -0.978633924f,
- 0.204108966f, -0.978948175f,
- 0.202607039f, -0.979260123f,
- 0.201104635f, -0.979569766f,
- 0.199601758f, -0.979877104f,
- 0.198098411f, -0.980182136f,
- 0.196594598f, -0.980484862f,
- 0.195090322f, -0.980785280f,
- 0.193585587f, -0.981083391f,
- 0.192080397f, -0.981379193f,
- 0.190574755f, -0.981672686f,
- 0.189068664f, -0.981963869f,
- 0.187562129f, -0.982252741f,
- 0.186055152f, -0.982539302f,
- 0.184547737f, -0.982823551f,
- 0.183039888f, -0.983105487f,
- 0.181531608f, -0.983385110f,
- 0.180022901f, -0.983662419f,
- 0.178513771f, -0.983937413f,
- 0.177004220f, -0.984210092f,
- 0.175494253f, -0.984480455f,
- 0.173983873f, -0.984748502f,
- 0.172473084f, -0.985014231f,
- 0.170961889f, -0.985277642f,
- 0.169450291f, -0.985538735f,
- 0.167938295f, -0.985797509f,
- 0.166425904f, -0.986053963f,
- 0.164913120f, -0.986308097f,
- 0.163399949f, -0.986559910f,
- 0.161886394f, -0.986809402f,
- 0.160372457f, -0.987056571f,
- 0.158858143f, -0.987301418f,
- 0.157343456f, -0.987543942f,
- 0.155828398f, -0.987784142f,
- 0.154312973f, -0.988022017f,
- 0.152797185f, -0.988257568f,
- 0.151281038f, -0.988490793f,
- 0.149764535f, -0.988721692f,
- 0.148247679f, -0.988950265f,
- 0.146730474f, -0.989176510f,
- 0.145212925f, -0.989400428f,
- 0.143695033f, -0.989622017f,
- 0.142176804f, -0.989841278f,
- 0.140658239f, -0.990058210f,
- 0.139139344f, -0.990272812f,
- 0.137620122f, -0.990485084f,
- 0.136100575f, -0.990695025f,
- 0.134580709f, -0.990902635f,
- 0.133060525f, -0.991107914f,
- 0.131540029f, -0.991310860f,
- 0.130019223f, -0.991511473f,
- 0.128498111f, -0.991709754f,
- 0.126976696f, -0.991905700f,
- 0.125454983f, -0.992099313f,
- 0.123932975f, -0.992290591f,
- 0.122410675f, -0.992479535f,
- 0.120888087f, -0.992666142f,
- 0.119365215f, -0.992850414f,
- 0.117842062f, -0.993032350f,
- 0.116318631f, -0.993211949f,
- 0.114794927f, -0.993389211f,
- 0.113270952f, -0.993564136f,
- 0.111746711f, -0.993736722f,
- 0.110222207f, -0.993906970f,
- 0.108697444f, -0.994074879f,
- 0.107172425f, -0.994240449f,
- 0.105647154f, -0.994403680f,
- 0.104121634f, -0.994564571f,
- 0.102595869f, -0.994723121f,
- 0.101069863f, -0.994879331f,
- 0.099543619f, -0.995033199f,
- 0.098017140f, -0.995184727f,
- 0.096490431f, -0.995333912f,
- 0.094963495f, -0.995480755f,
- 0.093436336f, -0.995625256f,
- 0.091908956f, -0.995767414f,
- 0.090381361f, -0.995907229f,
- 0.088853553f, -0.996044701f,
- 0.087325535f, -0.996179829f,
- 0.085797312f, -0.996312612f,
- 0.084268888f, -0.996443051f,
- 0.082740265f, -0.996571146f,
- 0.081211447f, -0.996696895f,
- 0.079682438f, -0.996820299f,
- 0.078153242f, -0.996941358f,
- 0.076623861f, -0.997060070f,
- 0.075094301f, -0.997176437f,
- 0.073564564f, -0.997290457f,
- 0.072034653f, -0.997402130f,
- 0.070504573f, -0.997511456f,
- 0.068974328f, -0.997618435f,
- 0.067443920f, -0.997723067f,
- 0.065913353f, -0.997825350f,
- 0.064382631f, -0.997925286f,
- 0.062851758f, -0.998022874f,
- 0.061320736f, -0.998118113f,
- 0.059789571f, -0.998211003f,
- 0.058258265f, -0.998301545f,
- 0.056726821f, -0.998389737f,
- 0.055195244f, -0.998475581f,
- 0.053663538f, -0.998559074f,
- 0.052131705f, -0.998640218f,
- 0.050599749f, -0.998719012f,
- 0.049067674f, -0.998795456f,
- 0.047535484f, -0.998869550f,
- 0.046003182f, -0.998941293f,
- 0.044470772f, -0.999010686f,
- 0.042938257f, -0.999077728f,
- 0.041405641f, -0.999142419f,
- 0.039872928f, -0.999204759f,
- 0.038340120f, -0.999264747f,
- 0.036807223f, -0.999322385f,
- 0.035274239f, -0.999377670f,
- 0.033741172f, -0.999430605f,
- 0.032208025f, -0.999481187f,
- 0.030674803f, -0.999529418f,
- 0.029141509f, -0.999575296f,
- 0.027608146f, -0.999618822f,
- 0.026074718f, -0.999659997f,
- 0.024541229f, -0.999698819f,
- 0.023007681f, -0.999735288f,
- 0.021474080f, -0.999769405f,
- 0.019940429f, -0.999801170f,
- 0.018406730f, -0.999830582f,
- 0.016872988f, -0.999857641f,
- 0.015339206f, -0.999882347f,
- 0.013805389f, -0.999904701f,
- 0.012271538f, -0.999924702f,
- 0.010737659f, -0.999942350f,
- 0.009203755f, -0.999957645f,
- 0.007669829f, -0.999970586f,
- 0.006135885f, -0.999981175f,
- 0.004601926f, -0.999989411f,
- 0.003067957f, -0.999995294f,
- 0.001533980f, -0.999998823f
-};
-
-
-/**
- * \par
- * Example code for the generation of the floating-point sine table:
- *
- * tableSize = 512;
- * for(n = 0; n < (tableSize + 1); n++)
- * {
- * sinTable[n]=sin(2*pi*n/tableSize);
- * }
- * \par
- * where pi value is 3.14159265358979
- */
-
-const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = {
- 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f,
- 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f,
- 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f,
- 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f,
- 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f,
- 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f,
- 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f,
- 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f,
- 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f,
- 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f,
- 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f,
- 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f,
- 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f,
- 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f,
- 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f,
- 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f,
- 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f,
- 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f,
- 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f,
- 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f,
- 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f,
- 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f,
- 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f,
- 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f,
- 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f,
- 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f,
- 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f,
- 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f,
- 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f,
- 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f,
- 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f,
- 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f,
- 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f,
- 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f,
- 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f,
- 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f,
- 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f,
- 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f,
- 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f,
- 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f,
- 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f,
- 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f,
- 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f,
- -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f,
- -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f,
- -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f,
- -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f,
- -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f,
- -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f,
- -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f,
- -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f,
- -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f,
- -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f,
- -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f,
- -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f,
- -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f,
- -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f,
- -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f,
- -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f,
- -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f,
- -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f,
- -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f,
- -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f,
- -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f,
- -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f,
- -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f,
- -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f,
- -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f,
- -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f,
- -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f,
- -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f,
- -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f,
- -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f,
- -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f,
- -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f,
- -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f,
- -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f,
- -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f,
- -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f,
- -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f,
- -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f,
- -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f,
- -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f,
- -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f,
- -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f,
- -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f,
- -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f,
- -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f,
- -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f,
- -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f,
- -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f,
- -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f,
- -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f,
- -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f
-};
-
-/**
- * \par
- * Table values are in Q31 (1.31 fixed-point format) and generation is done in
- * three steps. First, generate sin values in floating point:
- *
- * tableSize = 512;
- * for(n = 0; n < (tableSize + 1); n++)
- * {
- * sinTable[n]= sin(2*pi*n/tableSize);
- * }
- * where pi value is 3.14159265358979
- * \par
- * Second, convert floating-point to Q31 (Fixed point):
- * (sinTable[i] * pow(2, 31))
- * \par
- * Finally, round to the nearest integer value:
- * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
- */
-const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = {
- 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L,
- 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L,
- 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L,
- 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L,
- 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L,
- 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L,
- 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L,
- 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L,
- 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L,
- 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L,
- 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L,
- 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L,
- 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L,
- 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L,
- 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L,
- 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L,
- 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L,
- 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L,
- 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L,
- 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L,
- 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L,
- 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L,
- 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L,
- 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L,
- 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L,
- 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L,
- 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L,
- 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L,
- 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L,
- 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L,
- 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L,
- 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L,
- 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L,
- 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L,
- 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L,
- 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L,
- 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L,
- 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L,
- 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L,
- 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L,
- 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L,
- 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L,
- 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L,
- -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L,
- -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L,
- -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L,
- -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L,
- -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L,
- -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L,
- -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L,
- -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L,
- -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L,
- -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L,
- -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L,
- -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L,
- -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L,
- -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L,
- -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L,
- -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L,
- -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L,
- -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L,
- -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L,
- -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L,
- -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L,
- -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L,
- -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L,
- -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L,
- -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L,
- -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L,
- -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L,
- -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L,
- -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L,
- -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L,
- -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L,
- -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L,
- -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L,
- -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L,
- -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L,
- -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L,
- -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L,
- -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L,
- -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L,
- -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L,
- -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L,
- -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L,
- -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L,
- -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L,
- -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L,
- -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L,
- -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L,
- -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0
-};
-
-/**
- * \par
- * Table values are in Q15 (1.15 fixed-point format) and generation is done in
- * three steps. First, generate sin values in floating point:
- *
- * tableSize = 512;
- * for(n = 0; n < (tableSize + 1); n++)
- * {
- * sinTable[n]= sin(2*pi*n/tableSize);
- * }
- * where pi value is 3.14159265358979
- * \par
- * Second, convert floating-point to Q15 (Fixed point):
- * (sinTable[i] * pow(2, 15))
- * \par
- * Finally, round to the nearest integer value:
- * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
- */
-const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = {
- 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808,
- 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512,
- 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279,
- 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846,
- 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160,
- 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170,
- 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833,
- 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106,
- 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957,
- 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357,
- 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286,
- 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729,
- 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679,
- 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138,
- 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114,
- 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622,
- 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684,
- 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330,
- 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595,
- 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520,
- 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151,
- 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540,
- 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351,
- 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612,
- 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206,
- -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205,
- -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127,
- -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540,
- -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800,
- -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868,
- -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706,
- -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279,
- -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557,
- -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511,
- -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118,
- -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357,
- -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214,
- -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679,
- -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746,
- -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413,
- -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686,
- -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572,
- -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086,
- -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246,
- -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073,
- -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595,
- -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841,
- -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846,
- -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646,
- -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279,
- -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393,
- -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411,
- -2009, -1608, -1206, -804, -402, 0
-};
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c
deleted file mode 100644
index b288a2b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_const_structs.c
- * Description: Constant structs that are initialized for user convenience.
- * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions.
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_const_structs.h"
-
-/* Floating-point structs */
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
- 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
- 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
- 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
- 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
- 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
- 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
- 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
- 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH
-};
-
-const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
- 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH
-};
-
-/* Fixed-point structs */
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
- 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
- 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
- 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
- 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
- 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
- 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
- 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
- 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
- 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
- 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
- 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
- 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
- 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
- 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
- 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
- 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
- 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
-};
-
-const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
- 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
-};
-
-/* Structure for real-value inputs */
-/* Floating-point structs */
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = {
- { 16, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_16_TABLE_LENGTH },
- 32u,
- (float32_t *)twiddleCoef_rfft_32
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = {
- { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH },
- 64u,
- (float32_t *)twiddleCoef_rfft_64
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = {
- { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH },
- 128u,
- (float32_t *)twiddleCoef_rfft_128
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = {
- { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH },
- 256u,
- (float32_t *)twiddleCoef_rfft_256
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = {
- { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH },
- 512u,
- (float32_t *)twiddleCoef_rfft_512
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = {
- { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH },
- 1024u,
- (float32_t *)twiddleCoef_rfft_1024
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = {
- { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH },
- 2048u,
- (float32_t *)twiddleCoef_rfft_2048
-};
-
-const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = {
- { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH },
- 4096u,
- (float32_t *)twiddleCoef_rfft_4096
-};
-
-/* Fixed-point structs */
-/* q31_t */
-extern const q31_t realCoefAQ31[8192];
-extern const q31_t realCoefBQ31[8192];
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = {
- 32u,
- 0,
- 1,
- 256u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len16
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = {
- 64u,
- 0,
- 1,
- 128u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len32
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = {
- 128u,
- 0,
- 1,
- 64u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len64
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = {
- 256u,
- 0,
- 1,
- 32u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len128
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = {
- 512u,
- 0,
- 1,
- 16u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len256
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = {
- 1024u,
- 0,
- 1,
- 8u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len512
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = {
- 2048u,
- 0,
- 1,
- 4u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len1024
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = {
- 4096u,
- 0,
- 1,
- 2u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len2048
-};
-
-const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = {
- 8192u,
- 0,
- 1,
- 1u,
- (q31_t*)realCoefAQ31,
- (q31_t*)realCoefBQ31,
- &arm_cfft_sR_q31_len4096
-};
-
-/* q15_t */
-extern const q15_t realCoefAQ15[8192];
-extern const q15_t realCoefBQ15[8192];
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = {
- 32u,
- 0,
- 1,
- 256u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len16
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = {
- 64u,
- 0,
- 1,
- 128u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len32
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = {
- 128u,
- 0,
- 1,
- 64u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len64
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = {
- 256u,
- 0,
- 1,
- 32u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len128
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = {
- 512u,
- 0,
- 1,
- 16u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len256
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = {
- 1024u,
- 0,
- 1,
- 8u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len512
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = {
- 2048u,
- 0,
- 1,
- 4u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len1024
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = {
- 4096u,
- 0,
- 1,
- 2u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len2048
-};
-
-const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = {
- 8192u,
- 0,
- 1,
- 1u,
- (q15_t*)realCoefAQ15,
- (q15_t*)realCoefBQ15,
- &arm_cfft_sR_q15_len4096
-};
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
deleted file mode 100644
index 955345c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_conj_f32.c
- * Description: Floating-point complex conjugate
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup cmplx_conj Complex Conjugate
- *
- * Conjugates the elements of a complex data vector.
- *
- * The pSrc points to the source data and
- * pDst points to the where the result should be written.
- * numSamples specifies the number of complex samples
- * and the data in each array is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * Each array has a total of 2*numSamples values.
- * The underlying algorithm is used:
- *
- *
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup cmplx_conj
- * @{
- */
-
-/**
- * @brief Floating-point complex conjugate.
- * @param *pSrc points to the input vector
- * @param *pDst points to the output vector
- * @param numSamples number of complex samples in each vector
- * @return none.
- */
-
-void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t inR1, inR2, inR3, inR4;
- float32_t inI1, inI2, inI3, inI4;
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- /* read real input samples */
- inR1 = pSrc[0];
- /* store real samples to destination */
- pDst[0] = inR1;
- inR2 = pSrc[2];
- pDst[2] = inR2;
- inR3 = pSrc[4];
- pDst[4] = inR3;
- inR4 = pSrc[6];
- pDst[6] = inR4;
-
- /* read imaginary input samples */
- inI1 = pSrc[1];
- inI2 = pSrc[3];
-
- /* conjugate input */
- inI1 = -inI1;
-
- /* read imaginary input samples */
- inI3 = pSrc[5];
-
- /* conjugate input */
- inI2 = -inI2;
-
- /* read imaginary input samples */
- inI4 = pSrc[7];
-
- /* conjugate input */
- inI3 = -inI3;
-
- /* store imaginary samples to destination */
- pDst[1] = inI1;
- pDst[3] = inI2;
-
- /* conjugate input */
- inI4 = -inI4;
-
- /* store imaginary samples to destination */
- pDst[5] = inI3;
-
- /* increment source pointer by 8 to process next sampels */
- pSrc += 8u;
-
- /* store imaginary sample to destination */
- pDst[7] = inI4;
-
- /* increment destination pointer by 8 to store next samples */
- pDst += 8u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* realOut + j (imagOut) = realIn + j (-1) imagIn */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- *pDst++ = *pSrc++;
- *pDst++ = -*pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of cmplx_conj group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
deleted file mode 100644
index 77ce9b9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_conj_q15.c
- * Description: Q15 complex conjugate
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_conj
- * @{
- */
-
-/**
- * @brief Q15 complex conjugate.
- * @param *pSrc points to the input vector
- * @param *pDst points to the output vector
- * @param numSamples number of complex samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
- */
-
-void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
- q31_t in1, in2, in3, in4;
- q31_t zero = 0;
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- in1 = *__SIMD32(pSrc)++;
- in2 = *__SIMD32(pSrc)++;
- in3 = *__SIMD32(pSrc)++;
- in4 = *__SIMD32(pSrc)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- in1 = __QASX(zero, in1);
- in2 = __QASX(zero, in2);
- in3 = __QASX(zero, in3);
- in4 = __QASX(zero, in4);
-
-#else
-
- in1 = __QSAX(zero, in1);
- in2 = __QSAX(zero, in2);
- in3 = __QSAX(zero, in3);
- in4 = __QSAX(zero, in4);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
- in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
- in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
- in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
-
- *__SIMD32(pDst)++ = in1;
- *__SIMD32(pDst)++ = in2;
- *__SIMD32(pDst)++ = in3;
- *__SIMD32(pDst)++ = in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- *pDst++ = *pSrc++;
- *pDst++ = __SSAT(-*pSrc++, 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- q15_t in;
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- *pDst++ = *pSrc++;
- in = *pSrc++;
- *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of cmplx_conj group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
deleted file mode 100644
index f9f100c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_conj_q31.c
- * Description: Q31 complex conjugate
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_conj
- * @{
- */
-
-/**
- * @brief Q31 complex conjugate.
- * @param *pSrc points to the input vector
- * @param *pDst points to the output vector
- * @param numSamples number of complex samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
- */
-
-void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples)
-{
- uint32_t blkCnt; /* loop counter */
- q31_t in; /* Input value */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
- q31_t inI1, inI2, inI3, inI4; /* Temporary imaginary variables */
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
- /* read real input sample */
- inR1 = pSrc[0];
- /* store real input sample */
- pDst[0] = inR1;
-
- /* read imaginary input sample */
- inI1 = pSrc[1];
-
- /* read real input sample */
- inR2 = pSrc[2];
- /* store real input sample */
- pDst[2] = inR2;
-
- /* read imaginary input sample */
- inI2 = pSrc[3];
-
- /* negate imaginary input sample */
- inI1 = __QSUB(0, inI1);
-
- /* read real input sample */
- inR3 = pSrc[4];
- /* store real input sample */
- pDst[4] = inR3;
-
- /* read imaginary input sample */
- inI3 = pSrc[5];
-
- /* negate imaginary input sample */
- inI2 = __QSUB(0, inI2);
-
- /* read real input sample */
- inR4 = pSrc[6];
- /* store real input sample */
- pDst[6] = inR4;
-
- /* negate imaginary input sample */
- inI3 = __QSUB(0, inI3);
-
- /* store imaginary input sample */
- inI4 = pSrc[7];
-
- /* store imaginary input samples */
- pDst[1] = inI1;
-
- /* negate imaginary input sample */
- inI4 = __QSUB(0, inI4);
-
- /* store imaginary input samples */
- pDst[3] = inI2;
-
- /* increment source pointer by 8 to proecess next samples */
- pSrc += 8u;
-
- /* store imaginary input samples */
- pDst[5] = inI3;
- pDst[7] = inI4;
-
- /* increment destination pointer by 8 to process next samples */
- pDst += 8u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = numSamples;
-
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
- /* Calculate Complex Conjugate and then store the results in the destination buffer. */
- /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
- *pDst++ = *pSrc++;
- in = *pSrc++;
- *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of cmplx_conj group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
deleted file mode 100644
index 7d8688c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_dot_prod_f32.c
- * Description: Floating-point complex dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup cmplx_dot_prod Complex Dot Product
- *
- * Computes the dot product of two complex vectors.
- * The vectors are multiplied element-by-element and then summed.
- *
- * The pSrcA points to the first complex input vector and
- * pSrcB points to the second complex input vector.
- * numSamples specifies the number of complex samples
- * and the data in each array is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * Each array has a total of 2*numSamples values.
- *
- * The underlying algorithm is used:
- *
- * realResult=0;
- * imagResult=0;
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup cmplx_dot_prod
- * @{
- */
-
-/**
- * @brief Floating-point complex dot product
- * @param *pSrcA points to the first input vector
- * @param *pSrcB points to the second input vector
- * @param numSamples number of complex samples in each vector
- * @param *realResult real part of the result returned here
- * @param *imagResult imaginary part of the result returned here
- * @return none.
- */
-
-void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult)
-{
- float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
- float32_t a0,b0,c0,d0;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples & 0x3u;
-
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Store the real and imaginary results in the destination buffers */
- *realResult = real_sum;
- *imagResult = imag_sum;
-}
-
-/**
- * @} end of cmplx_dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
deleted file mode 100644
index f46a5e5..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_dot_prod_q15.c
- * Description: Processing function for the Q15 Complex Dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_dot_prod
- * @{
- */
-
-/**
- * @brief Q15 complex dot product
- * @param *pSrcA points to the first input vector
- * @param *pSrcB points to the second input vector
- * @param numSamples number of complex samples in each vector
- * @param *realResult real part of the result returned here
- * @param *imagResult imaginary part of the result returned here
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
- * These are accumulated in a 64-bit accumulator with 34.30 precision.
- * As a final step, the accumulators are converted to 8.24 format.
- * The return results realResult and imagResult are in 8.24 format.
- */
-
-void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult)
-{
- q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
- q15_t a0,b0,c0,d0;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
-
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += (q31_t)a0 * c0;
- imag_sum += (q31_t)a0 * d0;
- real_sum -= (q31_t)b0 * d0;
- imag_sum += (q31_t)b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += (q31_t)a0 * c0;
- imag_sum += (q31_t)a0 * d0;
- real_sum -= (q31_t)b0 * d0;
- imag_sum += (q31_t)b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += (q31_t)a0 * c0;
- imag_sum += (q31_t)a0 * d0;
- real_sum -= (q31_t)b0 * d0;
- imag_sum += (q31_t)b0 * c0;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += (q31_t)a0 * c0;
- imag_sum += (q31_t)a0 * d0;
- real_sum -= (q31_t)b0 * d0;
- imag_sum += (q31_t)b0 * c0;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += (q31_t)a0 * c0;
- imag_sum += (q31_t)a0 * d0;
- real_sum -= (q31_t)b0 * d0;
- imag_sum += (q31_t)b0 * c0;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += a0 * c0;
- imag_sum += a0 * d0;
- real_sum -= b0 * d0;
- imag_sum += b0 * c0;
-
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Store the real and imaginary results in 8.24 format */
- /* Convert real data in 34.30 to 8.24 by 6 right shifts */
- *realResult = (q31_t) (real_sum >> 6);
- /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
- *imagResult = (q31_t) (imag_sum >> 6);
-}
-
-/**
- * @} end of cmplx_dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
deleted file mode 100644
index 61818f9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_dot_prod_q31.c
- * Description: Q31 complex dot product
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_dot_prod
- * @{
- */
-
-/**
- * @brief Q31 complex dot product
- * @param *pSrcA points to the first input vector
- * @param *pSrcB points to the second input vector
- * @param numSamples number of complex samples in each vector
- * @param *realResult real part of the result returned here
- * @param *imagResult imaginary part of the result returned here
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
- * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
- * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.
- * The return results realResult and imagResult are in 16.48 format.
- * Input down scaling is not required.
- */
-
-void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult)
-{
- q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
- q31_t a0,b0,c0,d0;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
-
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- a0 = *pSrcA++;
- b0 = *pSrcA++;
- c0 = *pSrcB++;
- d0 = *pSrcB++;
-
- real_sum += ((q63_t)a0 * c0) >> 14;
- imag_sum += ((q63_t)a0 * d0) >> 14;
- real_sum -= ((q63_t)b0 * d0) >> 14;
- imag_sum += ((q63_t)b0 * c0) >> 14;
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Store the real and imaginary results in 16.48 format */
- *realResult = real_sum;
- *imagResult = imag_sum;
-}
-
-/**
- * @} end of cmplx_dot_prod group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
deleted file mode 100644
index 4d34286..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_f32.c
- * Description: Floating-point complex magnitude
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup cmplx_mag Complex Magnitude
- *
- * Computes the magnitude of the elements of a complex data vector.
- *
- * The pSrc points to the source data and
- * pDst points to the where the result should be written.
- * numSamples specifies the number of complex samples
- * in the input array and the data is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * The input array has a total of 2*numSamples values;
- * the output array has a total of numSamples values.
- * The underlying algorithm is used:
- *
- *
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup cmplx_mag
- * @{
- */
-/**
- * @brief Floating-point complex magnitude.
- * @param[in] *pSrc points to complex input buffer
- * @param[out] *pDst points to real output buffer
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- *
- */
-
-
-void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples)
-{
- float32_t realIn, imagIn; /* Temporary variables to hold input values */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
- /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
- realIn = *pSrc++;
- imagIn = *pSrc++;
- /* store the result in the destination buffer. */
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
- realIn = *pSrc++;
- imagIn = *pSrc++;
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
- realIn = *pSrc++;
- imagIn = *pSrc++;
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
- realIn = *pSrc++;
- imagIn = *pSrc++;
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
- realIn = *pSrc++;
- imagIn = *pSrc++;
- /* store the result in the destination buffer. */
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* out = sqrt((real * real) + (imag * imag)) */
- realIn = *pSrc++;
- imagIn = *pSrc++;
- /* store the result in the destination buffer. */
- arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of cmplx_mag group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
deleted file mode 100644
index afbd37e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_q15.c
- * Description: Q15 complex magnitude
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_mag
- * @{
- */
-
-
-/**
- * @brief Q15 complex magnitude
- * @param *pSrc points to the complex input vector
- * @param *pDst points to the real output vector
- * @param numSamples number of complex samples in the input vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
- */
-
-void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples)
-{
- q31_t acc0, acc1; /* Accumulators */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
- q31_t in1, in2, in3, in4;
- q31_t acc2, acc3;
-
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
- /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
- in1 = *__SIMD32(pSrc)++;
- in2 = *__SIMD32(pSrc)++;
- in3 = *__SIMD32(pSrc)++;
- in4 = *__SIMD32(pSrc)++;
-
- acc0 = __SMUAD(in1, in1);
- acc1 = __SMUAD(in2, in2);
- acc2 = __SMUAD(in3, in3);
- acc3 = __SMUAD(in4, in4);
-
- /* store the result in 2.14 format in the destination buffer. */
- arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
- arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
- arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
- arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
- in1 = *__SIMD32(pSrc)++;
- acc0 = __SMUAD(in1, in1);
-
- /* store the result in 2.14 format in the destination buffer. */
- arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
- q15_t real, imag; /* Temporary variables to hold input values */
-
- while (numSamples > 0u)
- {
- /* out = sqrt(real * real + imag * imag) */
- real = *pSrc++;
- imag = *pSrc++;
-
- acc0 = (real * real);
- acc1 = (imag * imag);
-
- /* store the result in 2.14 format in the destination buffer. */
- arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of cmplx_mag group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
deleted file mode 100644
index 29a0559..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_q31.c
- * Description: Q31 complex magnitude
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_mag
- * @{
- */
-
-/**
- * @brief Q31 complex magnitude
- * @param *pSrc points to the complex input vector
- * @param *pDst points to the real output vector
- * @param numSamples number of complex samples in the input vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
- * Input down scaling is not required.
- */
-
-void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples)
-{
- q31_t real, imag; /* Temporary variables to hold input values */
- q31_t acc0, acc1; /* Accumulators */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
- q31_t out1, out2, out3, out4; /* Accumulators */
- q63_t mul1, mul2, mul3, mul4; /* Temporary variables */
-
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* read complex input from source buffer */
- real1 = pSrc[0];
- imag1 = pSrc[1];
- real2 = pSrc[2];
- imag2 = pSrc[3];
-
- /* calculate power of input values */
- mul1 = (q63_t) real1 *real1;
- mul2 = (q63_t) imag1 *imag1;
- mul3 = (q63_t) real2 *real2;
- mul4 = (q63_t) imag2 *imag2;
-
- /* get the result to 3.29 format */
- out1 = (q31_t) (mul1 >> 33);
- out2 = (q31_t) (mul2 >> 33);
- out3 = (q31_t) (mul3 >> 33);
- out4 = (q31_t) (mul4 >> 33);
-
- /* add real and imaginary accumulators */
- out1 = out1 + out2;
- out3 = out3 + out4;
-
- /* read complex input from source buffer */
- real1 = pSrc[4];
- imag1 = pSrc[5];
- real2 = pSrc[6];
- imag2 = pSrc[7];
-
- /* calculate square root */
- arm_sqrt_q31(out1, &pDst[0]);
-
- /* calculate power of input values */
- mul1 = (q63_t) real1 *real1;
-
- /* calculate square root */
- arm_sqrt_q31(out3, &pDst[1]);
-
- /* calculate power of input values */
- mul2 = (q63_t) imag1 *imag1;
- mul3 = (q63_t) real2 *real2;
- mul4 = (q63_t) imag2 *imag2;
-
- /* get the result to 3.29 format */
- out1 = (q31_t) (mul1 >> 33);
- out2 = (q31_t) (mul2 >> 33);
- out3 = (q31_t) (mul3 >> 33);
- out4 = (q31_t) (mul4 >> 33);
-
- /* add real and imaginary accumulators */
- out1 = out1 + out2;
- out3 = out3 + out4;
-
- /* calculate square root */
- arm_sqrt_q31(out1, &pDst[2]);
-
- /* increment destination by 8 to process next samples */
- pSrc += 8u;
-
- /* calculate square root */
- arm_sqrt_q31(out3, &pDst[3]);
-
- /* increment destination by 4 to process next samples */
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 2.30 format in the destination buffer. */
- arm_sqrt_q31(acc0 + acc1, pDst++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of cmplx_mag group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
deleted file mode 100644
index 955d2d6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_squared_f32.c
- * Description: Floating-point complex magnitude squared
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup cmplx_mag_squared Complex Magnitude Squared
- *
- * Computes the magnitude squared of the elements of a complex data vector.
- *
- * The pSrc points to the source data and
- * pDst points to the where the result should be written.
- * numSamples specifies the number of complex samples
- * in the input array and the data is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * The input array has a total of 2*numSamples values;
- * the output array has a total of numSamples values.
- *
- * The underlying algorithm is used:
- *
- *
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup cmplx_mag_squared
- * @{
- */
-
-
-/**
- * @brief Floating-point complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
-void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples)
-{
- float32_t real, imag; /* Temporary variables to store real and imaginary values */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
- float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
- float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
- float32_t mul5, mul6, mul7, mul8; /* Temporary variables */
- float32_t out1, out2, out3, out4; /* Temporary variables to hold output values */
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- /* read real input sample from source buffer */
- real1 = pSrc[0];
- /* read imaginary input sample from source buffer */
- imag1 = pSrc[1];
-
- /* calculate power of real value */
- mul1 = real1 * real1;
-
- /* read real input sample from source buffer */
- real2 = pSrc[2];
-
- /* calculate power of imaginary value */
- mul2 = imag1 * imag1;
-
- /* read imaginary input sample from source buffer */
- imag2 = pSrc[3];
-
- /* calculate power of real value */
- mul3 = real2 * real2;
-
- /* read real input sample from source buffer */
- real3 = pSrc[4];
-
- /* calculate power of imaginary value */
- mul4 = imag2 * imag2;
-
- /* read imaginary input sample from source buffer */
- imag3 = pSrc[5];
-
- /* calculate power of real value */
- mul5 = real3 * real3;
- /* calculate power of imaginary value */
- mul6 = imag3 * imag3;
-
- /* read real input sample from source buffer */
- real4 = pSrc[6];
-
- /* accumulate real and imaginary powers */
- out1 = mul1 + mul2;
-
- /* read imaginary input sample from source buffer */
- imag4 = pSrc[7];
-
- /* accumulate real and imaginary powers */
- out2 = mul3 + mul4;
-
- /* calculate power of real value */
- mul7 = real4 * real4;
- /* calculate power of imaginary value */
- mul8 = imag4 * imag4;
-
- /* store output to destination */
- pDst[0] = out1;
-
- /* accumulate real and imaginary powers */
- out3 = mul5 + mul6;
-
- /* store output to destination */
- pDst[1] = out2;
-
- /* accumulate real and imaginary powers */
- out4 = mul7 + mul8;
-
- /* store output to destination */
- pDst[2] = out3;
-
- /* increment destination pointer by 8 to process next samples */
- pSrc += 8u;
-
- /* store output to destination */
- pDst[3] = out4;
-
- /* increment destination pointer by 4 to process next samples */
- pDst += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- real = *pSrc++;
- imag = *pSrc++;
-
- /* out = (real * real) + (imag * imag) */
- /* store the result in the destination buffer. */
- *pDst++ = (real * real) + (imag * imag);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of cmplx_mag_squared group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
deleted file mode 100644
index bbffef1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_squared_q15.c
- * Description: Q15 complex magnitude squared
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_mag_squared
- * @{
- */
-
-/**
- * @brief Q15 complex magnitude squared
- * @param *pSrc points to the complex input vector
- * @param *pDst points to the real output vector
- * @param numSamples number of complex samples in the input vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
- */
-
-void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples)
-{
- q31_t acc0, acc1; /* Accumulators */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
- q31_t in1, in2, in3, in4;
- q31_t acc2, acc3;
-
- /*loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- in1 = *__SIMD32(pSrc)++;
- in2 = *__SIMD32(pSrc)++;
- in3 = *__SIMD32(pSrc)++;
- in4 = *__SIMD32(pSrc)++;
-
- acc0 = __SMUAD(in1, in1);
- acc1 = __SMUAD(in2, in2);
- acc2 = __SMUAD(in3, in3);
- acc3 = __SMUAD(in4, in4);
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ = (q15_t) (acc0 >> 17);
- *pDst++ = (q15_t) (acc1 >> 17);
- *pDst++ = (q15_t) (acc2 >> 17);
- *pDst++ = (q15_t) (acc3 >> 17);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- in1 = *__SIMD32(pSrc)++;
- acc0 = __SMUAD(in1, in1);
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ = (q15_t) (acc0 >> 17);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
- q15_t real, imag; /* Temporary variables to store real and imaginary values */
-
- while (numSamples > 0u)
- {
- /* out = ((real * real) + (imag * imag)) */
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (real * real);
- acc1 = (imag * imag);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of cmplx_mag_squared group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
deleted file mode 100644
index f39c580..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mag_squared_q31.c
- * Description: Q31 complex magnitude squared
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup cmplx_mag_squared
- * @{
- */
-
-
-/**
- * @brief Q31 complex magnitude squared
- * @param *pSrc points to the complex input vector
- * @param *pDst points to the real output vector
- * @param numSamples number of complex samples in the input vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
- * Input down scaling is not required.
- */
-
-void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples)
-{
- q31_t real, imag; /* Temporary variables to store real and imaginary values */
- q31_t acc0, acc1; /* Accumulators */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counter */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* out = ((real * real) + (imag * imag)) */
- real = *pSrc++;
- imag = *pSrc++;
- acc0 = (q31_t) (((q63_t) real * real) >> 33);
- acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
- /* store the result in 3.29 format in the destination buffer. */
- *pDst++ = acc0 + acc1;
-
- /* Decrement the loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of cmplx_mag_squared group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
deleted file mode 100644
index 7d4204c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_cmplx_f32.c
- * Description: Floating-point complex-by-complex multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
- *
- * Multiplies a complex vector by another complex vector and generates a complex result.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * The parameter numSamples represents the number of complex
- * samples processed. The complex arrays have a total of 2*numSamples
- * real values.
- *
- * The underlying algorithm is used:
- *
- *
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup CmplxByCmplxMult
- * @{
- */
-
-
-/**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
-void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples)
-{
- float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
- uint32_t blkCnt; /* loop counters */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
- float32_t acc1, acc2, acc3, acc4;
-
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a1 = *pSrcA; /* A[2 * i] */
- c1 = *pSrcB; /* B[2 * i] */
-
- b1 = *(pSrcA + 1); /* A[2 * i + 1] */
- acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */
-
- a2 = *(pSrcA + 2); /* A[2 * i + 2] */
- acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */
-
- d1 = *(pSrcB + 1); /* B[2 * i + 1] */
- c2 = *(pSrcB + 2); /* B[2 * i + 2] */
- acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
- d2 = *(pSrcB + 3); /* B[2 * i + 3] */
- acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */
-
- b2 = *(pSrcA + 3); /* A[2 * i + 3] */
- acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
-
- a1 = *(pSrcA + 4); /* A[2 * i + 4] */
- acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */
-
- c1 = *(pSrcB + 4); /* B[2 * i + 4] */
- acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
- *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
- b1 = *(pSrcA + 5); /* A[2 * i + 5] */
- acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
-
- *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
- acc1 = (a1 * c1);
-
- d1 = *(pSrcB + 5);
- acc2 = (b1 * c1);
-
- *(pDst + 2) = acc3;
- *(pDst + 3) = acc4;
-
- a2 = *(pSrcA + 6);
- acc1 -= (b1 * d1);
-
- c2 = *(pSrcB + 6);
- acc2 += (a1 * d1);
-
- b2 = *(pSrcA + 7);
- acc3 = (a2 * c2);
-
- d2 = *(pSrcB + 7);
- acc4 = (b2 * c2);
-
- *(pDst + 4) = acc1;
- pSrcA += 8u;
-
- acc3 -= (b2 * d2);
- acc4 += (a2 * d2);
-
- *(pDst + 5) = acc2;
- pSrcB += 8u;
-
- *(pDst + 6) = acc3;
- *(pDst + 7) = acc4;
-
- pDst += 8u;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a1 = *pSrcA++;
- b1 = *pSrcA++;
- c1 = *pSrcB++;
- d1 = *pSrcB++;
-
- /* store the result in the destination buffer. */
- *pDst++ = (a1 * c1) - (b1 * d1);
- *pDst++ = (a1 * d1) + (b1 * c1);
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of CmplxByCmplxMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
deleted file mode 100644
index 956af1c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_cmplx_q15.c
- * Description: Q15 complex-by-complex multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup CmplxByCmplxMult
- * @{
- */
-
-/**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
- */
-
-void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples)
-{
- q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counters */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
- /* store the result in 3.13 format in the destination buffer. */
- *pDst++ =
- (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
- /* Decrement the blockSize loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of CmplxByCmplxMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
deleted file mode 100644
index 1810213..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_cmplx_q31.c
- * Description: Q31 complex-by-complex multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup CmplxByCmplxMult
- * @{
- */
-
-
-/**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
- * Input down scaling is not required.
- */
-
-void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples)
-{
- q31_t a, b, c, d; /* Temporary variables to store real and imaginary values */
- uint32_t blkCnt; /* loop counters */
- q31_t mul1, mul2, mul3, mul4;
- q31_t out1, out2;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 1u;
-
- /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
- ** a second loop below computes the remaining 1 sample. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x2u;
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
- /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
- a = *pSrcA++;
- b = *pSrcA++;
- c = *pSrcB++;
- d = *pSrcB++;
-
- mul1 = (q31_t) (((q63_t) a * c) >> 32);
- mul2 = (q31_t) (((q63_t) b * d) >> 32);
- mul3 = (q31_t) (((q63_t) a * d) >> 32);
- mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
- mul1 = (mul1 >> 1);
- mul2 = (mul2 >> 1);
- mul3 = (mul3 >> 1);
- mul4 = (mul4 >> 1);
-
- out1 = mul1 - mul2;
- out2 = mul3 + mul4;
-
- /* store the real result in 3.29 format in the destination buffer. */
- *pDst++ = out1;
- /* store the imag result in 3.29 format in the destination buffer. */
- *pDst++ = out2;
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of CmplxByCmplxMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
deleted file mode 100644
index d6cf658..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_real_f32.c
- * Description: Floating-point complex by real multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @defgroup CmplxByRealMult Complex-by-Real Multiplication
- *
- * Multiplies a complex vector by a real vector and generates a complex result.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * The parameter numSamples represents the number of complex
- * samples processed. The complex arrays have a total of 2*numSamples
- * real values while the real array has a total of numSamples
- * real values.
- *
- * The underlying algorithm is used:
- *
- *
- * for(n=0; n
- *
- * There are separate functions for floating-point, Q15, and Q31 data types.
- */
-
-/**
- * @addtogroup CmplxByRealMult
- * @{
- */
-
-
-/**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
-void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples)
-{
- float32_t in; /* Temporary variable to store input value */
- uint32_t blkCnt; /* loop counters */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
- float32_t inA5, inA6, inA7, inA8; /* Temporary variables to hold input data */
- float32_t inB1, inB2, inB3, inB4; /* Temporary variables to hold input data */
- float32_t out1, out2, out3, out4; /* Temporary variables to hold output data */
- float32_t out5, out6, out7, out8; /* Temporary variables to hold output data */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- /* read input from complex input buffer */
- inA1 = pSrcCmplx[0];
- inA2 = pSrcCmplx[1];
- /* read input from real input buffer */
- inB1 = pSrcReal[0];
-
- /* read input from complex input buffer */
- inA3 = pSrcCmplx[2];
-
- /* multiply complex buffer real input with real buffer input */
- out1 = inA1 * inB1;
-
- /* read input from complex input buffer */
- inA4 = pSrcCmplx[3];
-
- /* multiply complex buffer imaginary input with real buffer input */
- out2 = inA2 * inB1;
-
- /* read input from real input buffer */
- inB2 = pSrcReal[1];
- /* read input from complex input buffer */
- inA5 = pSrcCmplx[4];
-
- /* multiply complex buffer real input with real buffer input */
- out3 = inA3 * inB2;
-
- /* read input from complex input buffer */
- inA6 = pSrcCmplx[5];
- /* read input from real input buffer */
- inB3 = pSrcReal[2];
-
- /* multiply complex buffer imaginary input with real buffer input */
- out4 = inA4 * inB2;
-
- /* read input from complex input buffer */
- inA7 = pSrcCmplx[6];
-
- /* multiply complex buffer real input with real buffer input */
- out5 = inA5 * inB3;
-
- /* read input from complex input buffer */
- inA8 = pSrcCmplx[7];
-
- /* multiply complex buffer imaginary input with real buffer input */
- out6 = inA6 * inB3;
-
- /* read input from real input buffer */
- inB4 = pSrcReal[3];
-
- /* store result to destination bufer */
- pCmplxDst[0] = out1;
-
- /* multiply complex buffer real input with real buffer input */
- out7 = inA7 * inB4;
-
- /* store result to destination bufer */
- pCmplxDst[1] = out2;
-
- /* multiply complex buffer imaginary input with real buffer input */
- out8 = inA8 * inB4;
-
- /* store result to destination bufer */
- pCmplxDst[2] = out3;
- pCmplxDst[3] = out4;
- pCmplxDst[4] = out5;
-
- /* incremnet complex input buffer by 8 to process next samples */
- pSrcCmplx += 8u;
-
- /* store result to destination bufer */
- pCmplxDst[5] = out6;
-
- /* increment real input buffer by 4 to process next samples */
- pSrcReal += 4u;
-
- /* store result to destination bufer */
- pCmplxDst[6] = out7;
- pCmplxDst[7] = out8;
-
- /* increment destination buffer by 8 to process next sampels */
- pCmplxDst += 8u;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- in = *pSrcReal++;
- /* store the result in the destination buffer. */
- *pCmplxDst++ = (*pSrcCmplx++) * (in);
- *pCmplxDst++ = (*pSrcCmplx++) * (in);
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of CmplxByRealMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
deleted file mode 100644
index c6d01d2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_real_q15.c
- * Description: Q15 complex by real multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup CmplxByRealMult
- * @{
- */
-
-
-/**
- * @brief Q15 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples)
-{
- q15_t in; /* Temporary variable to store input value */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counters */
- q31_t inA1, inA2; /* Temporary variables to hold input data */
- q31_t inB1; /* Temporary variables to hold input data */
- q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
- q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- /* read complex number both real and imaginary from complex input buffer */
- inA1 = *__SIMD32(pSrcCmplx)++;
- /* read two real values at a time from real input buffer */
- inB1 = *__SIMD32(pSrcReal)++;
- /* read complex number both real and imaginary from complex input buffer */
- inA2 = *__SIMD32(pSrcCmplx)++;
-
- /* multiply complex number with real numbers */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
- mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
- mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
- mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
- mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
- mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
- mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
- mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* saturate the result */
- out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
- out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
- out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
- out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
- /* pack real and imaginary outputs and store them to destination */
- *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
- *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
- inA1 = *__SIMD32(pSrcCmplx)++;
- inB1 = *__SIMD32(pSrcReal)++;
- inA2 = *__SIMD32(pSrcCmplx)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
- mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
- mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
- mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
- mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
- mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
- mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
- mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
- out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
- out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
- out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
- *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
- *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- in = *pSrcReal++;
- /* store the result in the destination buffer. */
- *pCmplxDst++ =
- (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
- *pCmplxDst++ =
- (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* realOut = realA * realB. */
- /* imagOut = imagA * realB. */
- in = *pSrcReal++;
- /* store the result in the destination buffer. */
- *pCmplxDst++ =
- (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
- *pCmplxDst++ =
- (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
- /* Decrement the numSamples loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of CmplxByRealMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
deleted file mode 100644
index 3695965..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mult_real_q31.c
- * Description: Q31 complex by real multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupCmplxMath
- */
-
-/**
- * @addtogroup CmplxByRealMult
- * @{
- */
-
-
-/**
- * @brief Q31 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples)
-{
- q31_t inA1; /* Temporary variable to store input value */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- uint32_t blkCnt; /* loop counters */
- q31_t inA2, inA3, inA4; /* Temporary variables to hold input data */
- q31_t inB1, inB2; /* Temporary variabels to hold input data */
- q31_t out1, out2, out3, out4; /* Temporary variables to hold output data */
-
- /* loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- /* read real input from complex input buffer */
- inA1 = *pSrcCmplx++;
- inA2 = *pSrcCmplx++;
- /* read input from real input bufer */
- inB1 = *pSrcReal++;
- inB2 = *pSrcReal++;
- /* read imaginary input from complex input buffer */
- inA3 = *pSrcCmplx++;
- inA4 = *pSrcCmplx++;
-
- /* multiply complex input with real input */
- out1 = ((q63_t) inA1 * inB1) >> 32;
- out2 = ((q63_t) inA2 * inB1) >> 32;
- out3 = ((q63_t) inA3 * inB2) >> 32;
- out4 = ((q63_t) inA4 * inB2) >> 32;
-
- /* sature the result */
- out1 = __SSAT(out1, 31);
- out2 = __SSAT(out2, 31);
- out3 = __SSAT(out3, 31);
- out4 = __SSAT(out4, 31);
-
- /* get result in 1.31 format */
- out1 = out1 << 1;
- out2 = out2 << 1;
- out3 = out3 << 1;
- out4 = out4 << 1;
-
- /* store the result to destination buffer */
- *pCmplxDst++ = out1;
- *pCmplxDst++ = out2;
- *pCmplxDst++ = out3;
- *pCmplxDst++ = out4;
-
- /* read real input from complex input buffer */
- inA1 = *pSrcCmplx++;
- inA2 = *pSrcCmplx++;
- /* read input from real input bufer */
- inB1 = *pSrcReal++;
- inB2 = *pSrcReal++;
- /* read imaginary input from complex input buffer */
- inA3 = *pSrcCmplx++;
- inA4 = *pSrcCmplx++;
-
- /* multiply complex input with real input */
- out1 = ((q63_t) inA1 * inB1) >> 32;
- out2 = ((q63_t) inA2 * inB1) >> 32;
- out3 = ((q63_t) inA3 * inB2) >> 32;
- out4 = ((q63_t) inA4 * inB2) >> 32;
-
- /* sature the result */
- out1 = __SSAT(out1, 31);
- out2 = __SSAT(out2, 31);
- out3 = __SSAT(out3, 31);
- out4 = __SSAT(out4, 31);
-
- /* get result in 1.31 format */
- out1 = out1 << 1;
- out2 = out2 << 1;
- out3 = out3 << 1;
- out4 = out4 << 1;
-
- /* store the result to destination buffer */
- *pCmplxDst++ = out1;
- *pCmplxDst++ = out2;
- *pCmplxDst++ = out3;
- *pCmplxDst++ = out4;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C[2 * i] = A[2 * i] * B[i]. */
- /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
- /* read real input from complex input buffer */
- inA1 = *pSrcCmplx++;
- inA2 = *pSrcCmplx++;
- /* read input from real input bufer */
- inB1 = *pSrcReal++;
-
- /* multiply complex input with real input */
- out1 = ((q63_t) inA1 * inB1) >> 32;
- out2 = ((q63_t) inA2 * inB1) >> 32;
-
- /* sature the result */
- out1 = __SSAT(out1, 31);
- out2 = __SSAT(out2, 31);
-
- /* get result in 1.31 format */
- out1 = out1 << 1;
- out2 = out2 << 1;
-
- /* store the result to destination buffer */
- *pCmplxDst++ = out1;
- *pCmplxDst++ = out2;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (numSamples > 0u)
- {
- /* realOut = realA * realB. */
- /* imagReal = imagA * realB. */
- inA1 = *pSrcReal++;
- /* store the result in the destination buffer. */
- *pCmplxDst++ =
- (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
- *pCmplxDst++ =
- (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
-
- /* Decrement the numSamples loop counter */
- numSamples--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of CmplxByRealMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
deleted file mode 100644
index 05ea460..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_init_f32.c
- * Description: Floating-point PID Control initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] *S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state & 1 = reset the state.
- * @return none.
- * \par Description:
- * \par
- * The resetStateFlag specifies whether to set state to zero or not. \n
- * The function computes the structure fields: A0, A1 A2
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
- * also sets the state variables to all zeros.
- */
-
-void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag)
-{
-
- /* Derived coefficient A0 */
- S->A0 = S->Kp + S->Ki + S->Kd;
-
- /* Derived coefficient A1 */
- S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
-
- /* Derived coefficient A2 */
- S->A2 = S->Kd;
-
- /* Check whether state needs reset or not */
- if (resetStateFlag)
- {
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(float32_t));
- }
-
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
deleted file mode 100644
index f4169e2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_init_q15.c
- * Description: Q15 PID Control initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
- * @details
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- * \par Description:
- * \par
- * The resetStateFlag specifies whether to set state to zero or not. \n
- * The function computes the structure fields: A0, A1 A2
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
- * also sets the state variables to all zeros.
- */
-
-void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Derived coefficient A0 */
- S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
-
- /* Derived coefficients and pack into A1 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
-
-#else
-
- S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Check whether state needs reset or not */
- if (resetStateFlag)
- {
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(q15_t));
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t temp; /*to store the sum */
-
- /* Derived coefficient A0 */
- temp = S->Kp + S->Ki + S->Kd;
- S->A0 = (q15_t) __SSAT(temp, 16);
-
- /* Derived coefficients and pack into A1 */
- temp = -(S->Kd + S->Kd + S->Kp);
- S->A1 = (q15_t) __SSAT(temp, 16);
- S->A2 = S->Kd;
-
-
-
- /* Check whether state needs reset or not */
- if (resetStateFlag)
- {
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(q15_t));
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
deleted file mode 100644
index 1fe71d6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_init_q31.c
- * Description: Q31 PID Control initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- * \par Description:
- * \par
- * The resetStateFlag specifies whether to set state to zero or not. \n
- * The function computes the structure fields: A0, A1 A2
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
- * also sets the state variables to all zeros.
- */
-
-void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Derived coefficient A0 */
- S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
-
- /* Derived coefficient A1 */
- S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t temp;
-
- /* Derived coefficient A0 */
- temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
- S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
-
- /* Derived coefficient A1 */
- temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
- S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Derived coefficient A2 */
- S->A2 = S->Kd;
-
- /* Check whether state needs reset or not */
- if (resetStateFlag)
- {
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(q31_t));
- }
-
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
deleted file mode 100644
index ad5b179..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_reset_f32.c
- * Description: Floating-point PID Control reset function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
-* @brief Reset function for the floating-point PID Control.
-* @param[in] *S Instance pointer of PID control data structure.
-* @return none.
-* \par Description:
-* The function resets the state buffer to zeros.
-*/
-void arm_pid_reset_f32(
- arm_pid_instance_f32 * S)
-{
-
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(float32_t));
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
deleted file mode 100644
index 52f4acf..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_reset_q15.c
- * Description: Q15 PID Control reset function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
-* @brief Reset function for the Q15 PID Control.
-* @param[in] *S Instance pointer of PID control data structure.
-* @return none.
-* \par Description:
-* The function resets the state buffer to zeros.
-*/
-void arm_pid_reset_q15(
- arm_pid_instance_q15 * S)
-{
- /* Reset state to zero, The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(q15_t));
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
deleted file mode 100644
index d6547ef..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_pid_reset_q31.c
- * Description: Q31 PID Control reset function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
- /**
- * @addtogroup PID
- * @{
- */
-
-/**
-* @brief Reset function for the Q31 PID Control.
-* @param[in] *S Instance pointer of PID control data structure.
-* @return none.
-* \par Description:
-* The function resets the state buffer to zeros.
-*/
-void arm_pid_reset_q31(
- arm_pid_instance_q31 * S)
-{
-
- /* Clear the state buffer. The size will be always 3 samples */
- memset(S->state, 0, 3u * sizeof(q31_t));
-}
-
-/**
- * @} end of PID group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
deleted file mode 100644
index 7ec1b53..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sin_cos_f32.c
- * Description: Sine and Cosine calculation for floating-point values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup SinCos Sine Cosine
- *
- * Computes the trigonometric sine and cosine values using a combination of table lookup
- * and linear interpolation.
- * There are separate functions for Q31 and floating-point data types.
- * The input to the floating-point version is in degrees while the
- * fixed-point Q31 have a scaled input with the range
- * [-1 0.9999] mapping to [-180 +180] degrees.
- *
- * The floating point function also allows values that are out of the usual range. When this happens, the function will
- * take extra time to adjust the input value to the range of [-180 180].
- *
- * The result is accurate to 5 digits after the decimal point.
- *
- * The implementation is based on table lookup using 360 values together with linear interpolation.
- * The steps used are:
- * -# Calculation of the nearest integer table index.
- * -# Compute the fractional portion (fract) of the input.
- * -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
- * -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)).
- * -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
- * -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)).
- */
-
- /**
- * @addtogroup SinCos
- * @{
- */
-
-/**
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cos output.
- * @return none.
- */
-
-void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCosVal)
-{
- float32_t fract, in; /* Temporary variables for input, output */
- uint16_t indexS, indexC; /* Index variable */
- float32_t f1, f2, d1, d2; /* Two nearest output values */
- float32_t findex, Dn, Df, temp;
-
- /* input x is in degrees */
- /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
- in = theta * 0.00277777777778f;
-
- if (in < 0.0f)
- {
- in = -in;
- }
-
- in = in - (int32_t)in;
-
- /* Calculation of index of the table */
- findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
- indexS = ((uint16_t)findex) & 0x1ff;
- indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
-
- /* fractional value calculation */
- fract = findex - (float32_t) indexS;
-
- /* Read two nearest values of input value from the cos & sin tables */
- f1 = sinTable_f32[indexC+0];
- f2 = sinTable_f32[indexC+1];
- d1 = -sinTable_f32[indexS+0];
- d2 = -sinTable_f32[indexS+1];
-
- temp = (1.0f - fract) * f1 + fract * f2;
-
- Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
- Df = f2 - f1; // delta between the values of the functions
-
- temp = Dn *(d1 + d2) - 2 * Df;
- temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn);
- temp = fract * temp + d1 * Dn;
-
- /* Calculation of cosine value */
- *pCosVal = fract * temp + f1;
-
- /* Read two nearest values of input value from the cos & sin tables */
- f1 = sinTable_f32[indexS+0];
- f2 = sinTable_f32[indexS+1];
- d1 = sinTable_f32[indexC+0];
- d2 = sinTable_f32[indexC+1];
-
- temp = (1.0f - fract) * f1 + fract * f2;
-
- Df = f2 - f1; // delta between the values of the functions
- temp = Dn*(d1 + d2) - 2*Df;
- temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
- temp = fract*temp + d1*Dn;
-
- /* Calculation of sine value */
- *pSinVal = fract*temp + f1;
-
- if (theta < 0.0f)
- {
- *pSinVal = -*pSinVal;
- }
-}
-/**
- * @} end of SinCos group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
deleted file mode 100644
index d661830..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sin_cos_q31.c
- * Description: Cosine & Sine calculation for Q31 values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupController
- */
-
- /**
- * @addtogroup SinCos
- * @{
- */
-
-/**
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cosine output.
- * @return none.
- *
- * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
- *
- */
-
-void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal)
-{
- q31_t fract; /* Temporary variables for input, output */
- uint16_t indexS, indexC; /* Index variable */
- q31_t f1, f2, d1, d2; /* Two nearest output values */
- q31_t Dn, Df;
- q63_t temp;
-
- /* Calculate the nearest index */
- indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
- indexC = (indexS + 128) & 0x1ff;
-
- /* Calculation of fractional value */
- fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
-
- /* Read two nearest values of input value from the cos & sin tables */
- f1 = sinTable_q31[indexC+0];
- f2 = sinTable_q31[indexC+1];
- d1 = -sinTable_q31[indexS+0];
- d2 = -sinTable_q31[indexS+1];
-
- Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
- Df = f2 - f1; // delta between the values of the functions
- temp = Dn*((q63_t)d1 + d2);
- temp = temp - ((q63_t)Df << 32);
- temp = (q63_t)fract*(temp >> 31);
- temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
- temp = (q63_t)fract*(temp >> 31);
- temp = temp + (q63_t)d1*Dn;
- temp = (q63_t)fract*(temp >> 31);
-
- /* Calculation of cosine value */
- *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
-
- /* Read two nearest values of input value from the cos & sin tables */
- f1 = sinTable_q31[indexS+0];
- f2 = sinTable_q31[indexS+1];
- d1 = sinTable_q31[indexC+0];
- d2 = sinTable_q31[indexC+1];
-
- Df = f2 - f1; // delta between the values of the functions
- temp = Dn*((q63_t)d1 + d2);
- temp = temp - ((q63_t)Df << 32);
- temp = (q63_t)fract*(temp >> 31);
- temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
- temp = (q63_t)fract*(temp >> 31);
- temp = temp + (q63_t)d1*Dn;
- temp = (q63_t)fract*(temp >> 31);
-
- /* Calculation of sine value */
- *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
-}
-
-/**
- * @} end of SinCos group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
deleted file mode 100644
index e11c47c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cos_f32.c
- * Description: Fast cosine calculation for floating-point values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-/**
- * @ingroup groupFastMath
- */
-
-/**
- * @defgroup cos Cosine
- *
- * Computes the trigonometric cosine function using a combination of table lookup
- * and linear interpolation. There are separate functions for
- * Q15, Q31, and floating-point data types.
- * The input to the floating-point version is in radians while the
- * fixed-point Q15 and Q31 have a scaled input with the range
- * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
- * value of 2*pi wraps around to 0.
- *
- * The implementation is based on table lookup using 256 values together with linear interpolation.
- * The steps used are:
- * -# Calculation of the nearest integer table index
- * -# Compute the fractional portion (fract) of the table index.
- * -# The final result equals (1.0f-fract)*a + fract*b;
- *
- * where
- *
- * b=Table[index+0];
- * c=Table[index+1];
- *
- */
-
- /**
- * @addtogroup cos
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
-
-float32_t arm_cos_f32(
- float32_t x)
-{
- float32_t cosVal, fract, in; /* Temporary variables for input, output */
- uint16_t index; /* Index variable */
- float32_t a, b; /* Two nearest output values */
- int32_t n;
- float32_t findex;
-
- /* input x is in radians */
- /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
- in = x * 0.159154943092f + 0.25f;
-
- /* Calculation of floor value of input */
- n = (int32_t) in;
-
- /* Make negative values towards -infinity */
- if (in < 0.0f)
- {
- n--;
- }
-
- /* Map input value to [0 1] */
- in = in - (float32_t) n;
-
- /* Calculation of index of the table */
- findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
- index = ((uint16_t)findex) & 0x1ff;
-
- /* fractional value calculation */
- fract = findex - (float32_t) index;
-
- /* Read two nearest values of input value from the cos table */
- a = sinTable_f32[index];
- b = sinTable_f32[index+1];
-
- /* Linear interpolation process */
- cosVal = (1.0f-fract)*a + fract*b;
-
- /* Return the output value */
- return (cosVal);
-}
-
-/**
- * @} end of cos group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
deleted file mode 100644
index 7fa2e18..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cos_q15.c
- * Description: Fast cosine calculation for Q15 values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupFastMath
- */
-
- /**
- * @addtogroup cos
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- *
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
- * value in the range [0 2*pi).
- */
-
-q15_t arm_cos_q15(
- q15_t x)
-{
- q15_t cosVal; /* Temporary variables for input, output */
- int32_t index; /* Index variables */
- q15_t a, b; /* Four nearest output values */
- q15_t fract; /* Temporary values for fractional values */
-
- /* add 0.25 (pi/2) to read sine table */
- x = (uint16_t)x + 0x2000;
- if (x < 0)
- { /* convert negative numbers to corresponding positive ones */
- x = (uint16_t)x + 0x8000;
- }
-
- /* Calculate the nearest index */
- index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
-
- /* Calculation of fractional value */
- fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
-
- /* Read two nearest values of input value from the sin table */
- a = sinTable_q15[index];
- b = sinTable_q15[index+1];
-
- /* Linear interpolation process */
- cosVal = (q31_t)(0x8000-fract)*a >> 16;
- cosVal = (q15_t)((((q31_t)cosVal << 16) + ((q31_t)fract*b)) >> 16);
-
- return cosVal << 1;
-}
-
-/**
- * @} end of cos group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
deleted file mode 100644
index fde5368..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cos_q31.c
- * Description: Fast cosine calculation for Q31 values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupFastMath
- */
-
- /**
- * @addtogroup cos
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- *
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
- * value in the range [0 2*pi).
- */
-
-q31_t arm_cos_q31(
- q31_t x)
-{
- q31_t cosVal; /* Temporary variables for input, output */
- int32_t index; /* Index variables */
- q31_t a, b; /* Four nearest output values */
- q31_t fract; /* Temporary values for fractional values */
-
- /* add 0.25 (pi/2) to read sine table */
- x = (uint32_t)x + 0x20000000;
- if (x < 0)
- { /* convert negative numbers to corresponding positive ones */
- x = (uint32_t)x + 0x80000000;
- }
-
- /* Calculate the nearest index */
- index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
-
- /* Calculation of fractional value */
- fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
-
- /* Read two nearest values of input value from the sin table */
- a = sinTable_q31[index];
- b = sinTable_q31[index+1];
-
- /* Linear interpolation process */
- cosVal = (q63_t)(0x80000000-fract)*a >> 32;
- cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
-
- return cosVal << 1;
-}
-
-/**
- * @} end of cos group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
deleted file mode 100644
index f2e3065..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sin_f32.c
- * Description: Fast sine calculation for floating-point values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include
-
-/**
- * @ingroup groupFastMath
- */
-
-/**
- * @defgroup sin Sine
- *
- * Computes the trigonometric sine function using a combination of table lookup
- * and linear interpolation. There are separate functions for
- * Q15, Q31, and floating-point data types.
- * The input to the floating-point version is in radians while the
- * fixed-point Q15 and Q31 have a scaled input with the range
- * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
- * value of 2*pi wraps around to 0.
- *
- * The implementation is based on table lookup using 256 values together with linear interpolation.
- * The steps used are:
- * -# Calculation of the nearest integer table index
- * -# Compute the fractional portion (fract) of the table index.
- * -# The final result equals (1.0f-fract)*a + fract*b;
- *
- * where
- *
- * b=Table[index+0];
- * c=Table[index+1];
- *
- */
-
-/**
- * @addtogroup sin
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
-
-float32_t arm_sin_f32(
- float32_t x)
-{
- float32_t sinVal, fract, in; /* Temporary variables for input, output */
- uint16_t index; /* Index variable */
- float32_t a, b; /* Two nearest output values */
- int32_t n;
- float32_t findex;
-
- /* Special case for small negative inputs */
- if ((x < 0.0f) && (x >= -1.9e-7f)) {
- return x;
- }
-
- /* input x is in radians */
- /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
- in = x * 0.159154943092f;
-
- /* Calculation of floor value of input */
- n = (int32_t) in;
-
- /* Make negative values towards -infinity */
- if (x < 0.0f)
- {
- n--;
- }
-
- /* Map input value to [0 1] */
- in = in - (float32_t) n;
-
- /* Calculation of index of the table */
- findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
-
- index = ((uint16_t)findex) & 0x1ff;
-
- /* fractional value calculation */
- fract = findex - (float32_t) index;
-
- /* Read two nearest values of input value from the sin table */
- a = sinTable_f32[index];
- b = sinTable_f32[index+1];
-
- /* Linear interpolation process */
- sinVal = (1.0f-fract)*a + fract*b;
-
- /* Return the output value */
- return (sinVal);
-}
-
-/**
- * @} end of sin group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
deleted file mode 100644
index 7c8f627..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sin_q15.c
- * Description: Fast sine calculation for Q15 values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupFastMath
- */
-
- /**
- * @addtogroup sin
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- *
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
- */
-
-q15_t arm_sin_q15(
- q15_t x)
-{
- q15_t sinVal; /* Temporary variables for input, output */
- int32_t index; /* Index variables */
- q15_t a, b; /* Four nearest output values */
- q15_t fract; /* Temporary values for fractional values */
-
- /* Calculate the nearest index */
- index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
-
- /* Calculation of fractional value */
- fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
-
- /* Read two nearest values of input value from the sin table */
- a = sinTable_q15[index];
- b = sinTable_q15[index+1];
-
- /* Linear interpolation process */
- sinVal = (q31_t)(0x8000-fract)*a >> 16;
- sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
-
- return sinVal << 1;
-}
-
-/**
- * @} end of sin group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
deleted file mode 100644
index 8d3c7ac..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sin_q31.c
- * Description: Fast sine calculation for Q31 values
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupFastMath
- */
-
- /**
- * @addtogroup sin
- * @{
- */
-
-/**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- *
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
-
-q31_t arm_sin_q31(
- q31_t x)
-{
- q31_t sinVal; /* Temporary variables for input, output */
- int32_t index; /* Index variables */
- q31_t a, b; /* Four nearest output values */
- q31_t fract; /* Temporary values for fractional values */
-
- /* Calculate the nearest index */
- index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
-
- /* Calculation of fractional value */
- fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
-
- /* Read two nearest values of input value from the sin table */
- a = sinTable_q31[index];
- b = sinTable_q31[index+1];
-
- /* Linear interpolation process */
- sinVal = (q63_t)(0x80000000-fract)*a >> 32;
- sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
-
- return sinVal << 1;
-}
-
-/**
- * @} end of sin group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
deleted file mode 100644
index 8487ed3..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sqrt_q15.c
- * Description: Q15 square root function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-
-/**
- * @ingroup groupFastMath
- */
-
-/**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if the input value is positive
- * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
- * negative inputs, the function returns *pOut = 0.
- */
-
-arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut)
-{
- q15_t number, temp1, var1, signBits1, half;
- q31_t bits_val1;
- float32_t temp_float1;
- union
- {
- q31_t fracval;
- float32_t floatval;
- } tempconv;
-
- number = in;
-
- /* If the input is a positive number then compute the signBits. */
- if (number > 0)
- {
- signBits1 = __CLZ(number) - 17;
-
- /* Shift by the number of signBits1 */
- if ((signBits1 % 2) == 0)
- {
- number = number << signBits1;
- }
- else
- {
- number = number << (signBits1 - 1);
- }
-
- /* Calculate half value of the number */
- half = number >> 1;
- /* Store the number for later use */
- temp1 = number;
-
- /* Convert to float */
- temp_float1 = number * 3.051757812500000e-005f;
- /*Store as integer */
- tempconv.floatval = temp_float1;
- bits_val1 = tempconv.fracval;
- /* Subtract the shifted value from the magic number to give intial guess */
- bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */
- /* Store as float */
- tempconv.fracval = bits_val1;
- temp_float1 = tempconv.floatval;
- /* Convert to integer format */
- var1 = (q31_t) (temp_float1 * 16384);
-
- /* 1st iteration */
- var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
- ((q15_t)
- ((((q15_t)
- (((q31_t) var1 * var1) >> 15)) *
- (q31_t) half) >> 15))) >> 15)) << 2;
- /* 2nd iteration */
- var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
- ((q15_t)
- ((((q15_t)
- (((q31_t) var1 * var1) >> 15)) *
- (q31_t) half) >> 15))) >> 15)) << 2;
- /* 3rd iteration */
- var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
- ((q15_t)
- ((((q15_t)
- (((q31_t) var1 * var1) >> 15)) *
- (q31_t) half) >> 15))) >> 15)) << 2;
-
- /* Multiply the inverse square root with the original value */
- var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
-
- /* Shift the output down accordingly */
- if ((signBits1 % 2) == 0)
- {
- var1 = var1 >> (signBits1 / 2);
- }
- else
- {
- var1 = var1 >> ((signBits1 - 1) / 2);
- }
- *pOut = var1;
-
- return (ARM_MATH_SUCCESS);
- }
- /* If the number is a negative number then store zero as its square root value */
- else
- {
- *pOut = 0;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
-}
-
-/**
- * @} end of SQRT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
deleted file mode 100644
index 0deea04..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_sqrt_q31.c
- * Description: Q31 square root function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupFastMath
- */
-
-/**
- * @addtogroup SQRT
- * @{
- */
-
-/**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if the input value is positive
- * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
- * negative inputs, the function returns *pOut = 0.
- */
-
-arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut)
-{
- q31_t number, temp1, bits_val1, var1, signBits1, half;
- float32_t temp_float1;
- union
- {
- q31_t fracval;
- float32_t floatval;
- } tempconv;
-
- number = in;
-
- /* If the input is a positive number then compute the signBits. */
- if (number > 0)
- {
- signBits1 = __CLZ(number) - 1;
-
- /* Shift by the number of signBits1 */
- if ((signBits1 % 2) == 0)
- {
- number = number << signBits1;
- }
- else
- {
- number = number << (signBits1 - 1);
- }
-
- /* Calculate half value of the number */
- half = number >> 1;
- /* Store the number for later use */
- temp1 = number;
-
- /*Convert to float */
- temp_float1 = number * 4.6566128731e-010f;
- /*Store as integer */
- tempconv.floatval = temp_float1;
- bits_val1 = tempconv.fracval;
- /* Subtract the shifted value from the magic number to give intial guess */
- bits_val1 = 0x5f3759df - (bits_val1 >> 1); /* gives initial guess */
- /* Store as float */
- tempconv.fracval = bits_val1;
- temp_float1 = tempconv.floatval;
- /* Convert to integer format */
- var1 = (q31_t) (temp_float1 * 1073741824);
-
- /* 1st iteration */
- var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
- ((q31_t)
- ((((q31_t)
- (((q63_t) var1 * var1) >> 31)) *
- (q63_t) half) >> 31))) >> 31)) << 2;
- /* 2nd iteration */
- var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
- ((q31_t)
- ((((q31_t)
- (((q63_t) var1 * var1) >> 31)) *
- (q63_t) half) >> 31))) >> 31)) << 2;
- /* 3rd iteration */
- var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
- ((q31_t)
- ((((q31_t)
- (((q63_t) var1 * var1) >> 31)) *
- (q63_t) half) >> 31))) >> 31)) << 2;
-
- /* Multiply the inverse square root with the original value */
- var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
-
- /* Shift the output down accordingly */
- if ((signBits1 % 2) == 0)
- {
- var1 = var1 >> (signBits1 / 2);
- }
- else
- {
- var1 = var1 >> ((signBits1 - 1) / 2);
- }
- *pOut = var1;
-
- return (ARM_MATH_SUCCESS);
- }
- /* If the number is a negative number then store zero as its square root value */
- else
- {
- *pOut = 0;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
-}
-
-/**
- * @} end of SQRT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
deleted file mode 100644
index f727409..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_32x64_init_q31.c
- * Description: High precision Q31 Biquad cascade filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1_32x64
- * @{
- */
-
-/**
- * @details
- *
- * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
- * @return none
- *
- * Coefficient and State Ordering:
- *
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState points to state variables array and size of each state variable is 1.63 format.
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
- * The state variables are arranged in the state array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign postShift to be applied to the output */
- S->postShift = postShift;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 4 * numStages */
- memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF1_32x64 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
deleted file mode 100644
index 2a5c123..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_32x64_q31.c
- * Description: High precision Q31 Biquad cascade filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
- *
- * This function implements a high precision Biquad cascade filter which operates on
- * Q31 data values. The filter coefficients are in 1.31 format and the state variables
- * are in 1.63 format. The double precision state variables reduce quantization noise
- * in the filter and provide a cleaner output.
- * These filters are particularly useful when implementing filters in which the
- * singularities are close to the unit circle. This is common for low pass or high
- * pass filters with very low cutoff frequencies.
- *
- * The function operates on blocks of input and output data
- * and each call to the function processes blockSize samples through
- * the filter. pSrc and pDst points to input and output arrays
- * containing blockSize Q31 values.
- *
- * \par Algorithm
- * Each Biquad stage implements a second order filter using the difference equation:
- *
- * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- *
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
- * \image html Biquad.gif "Single Biquad filter stage"
- * Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
- * Pay careful attention to the sign of the feedback coefficients.
- * Some design tools use the difference equation
- *
- * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
- *
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
- *
- * \par
- * Higher order filters are realized as a cascade of second order sections.
- * numStages refers to the number of second order stages used.
- * For example, an 8th order filter would be realized with numStages=4 second order stages.
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
- *
- * \par
- * The pState points to state variables array .
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.
- * The state variables are arranged in the array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- *
- * \par
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values of data in 1.63 format.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- *
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
- *
- * \par Init Function
- * There is also an associated initialization function which performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros before static initialization.
- * For example, to statically initialize the filter instance structure use
- *
- * arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
- *
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.
- * \par Fixed-Point Behavior
- * Care must be taken while using Biquad Cascade 32x64 filter function.
- * Following issues must be considered:
- * - Scaling of coefficients
- * - Filter gain
- * - Overflow and saturation
- *
- * \par
- * Filter coefficients are represented as fractional values and
- * restricted to lie in the range [-1 +1).
- * The processing function has an additional scaling parameter postShift
- * which allows the filter coefficients to exceed the range [+1 -1).
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
- * This essentially scales the filter coefficients by 2^postShift.
- * For example, to realize the coefficients
- *
- * {1.5, -0.8, 1.2, 1.6, -0.9}
- *
- * set the Coefficient array to:
- *
- * {0.75, -0.4, 0.6, 0.8, -0.45}
- *
- * and set postShift=1
- *
- * \par
- * The second thing to keep in mind is the gain through the filter.
- * The frequency response of a Biquad filter is a function of its coefficients.
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
- *
- * \par
- * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
- * This is described in the function specific documentation below.
- */
-
-/**
- * @addtogroup BiquadCascadeDF1_32x64
- * @{
- */
-
-/**
- * @details
-
- * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
- * 1.31 format by discarding the low 32 bits.
- *
- * \par
- * Two related functions are provided in the CMSIS DSP library.
- * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
- * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
- */
-
-void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pIn = pSrc; /* input pointer initialization */
- q31_t *pOut = pDst; /* output pointer initialization */
- q63_t *pState = S->pState; /* state pointer initialization */
- q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
- q63_t acc; /* accumulator */
- q31_t Xn1, Xn2; /* Input Filter state variables */
- q63_t Yn1, Yn2; /* Output Filter state variables */
- q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
- q31_t Xn; /* temporary input */
- int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
- uint32_t sample, stage = S->numStages; /* loop counters */
- q31_t acc_l, acc_h; /* temporary output */
- uint32_t uShift = ((uint32_t) S->postShift + 1u);
- uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = (q31_t) (pState[0]);
- Xn2 = (q31_t) (pState[1]);
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- /* The variable acc hold output value that is being computed and
- * stored in the destination buffer
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) Xn *b0;
-
- /* acc += b1 * x[n-1] */
- acc += (q63_t) Xn1 *b1;
-
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn2 *b2;
-
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn1, a1);
-
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn2, a2);
-
- /* The result is converted to 1.63 , Yn2 variable is reused */
- Yn2 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer in 1.31 format. */
- *pOut = acc_h;
-
- /* Read the second input into Xn2, to reuse the value */
- Xn2 = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc += b1 * x[n-1] */
- acc = (q63_t) Xn *b1;
-
- /* acc = b0 * x[n] */
- acc += (q63_t) Xn2 *b0;
-
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn1 *b2;
-
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn2, a1);
-
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn1, a2);
-
- /* The result is converted to 1.63, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Read the third input into Xn1, to reuse the value */
- Xn1 = *pIn++;
-
- /* The result is converted to 1.31 */
- /* Store the output in the destination buffer. */
- *(pOut + 1u) = acc_h;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) Xn1 *b0;
-
- /* acc += b1 * x[n-1] */
- acc += (q63_t) Xn2 *b1;
-
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn *b2;
-
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn1, a1);
-
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn2, a2);
-
- /* The result is converted to 1.63, Yn2 variable is reused */
- Yn2 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer in 1.31 format. */
- *(pOut + 2u) = acc_h;
-
- /* Read the fourth input into Xn, to reuse the value */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- acc = (q63_t) Xn *b0;
-
- /* acc += b1 * x[n-1] */
- acc += (q63_t) Xn1 *b1;
-
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn2 *b2;
-
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn2, a1);
-
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn1, a2);
-
- /* The result is converted to 1.63, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer in 1.31 format. */
- *(pOut + 3u) = acc_h;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
-
- /* update output pointer */
- pOut += 4u;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- sample = (blockSize & 0x3u);
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) Xn *b0;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) Xn1 *b1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn2 *b2;
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn1, a1);
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn2, a2);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- /* The result is converted to 1.63, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer in 1.31 format. */
- *pOut++ = acc_h;
- /* Yn1 = acc << shift; */
-
- /* Store the output in the destination buffer in 1.31 format. */
-/* *pOut++ = (q31_t) (acc >> (32 - shift)); */
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage output is given as input to the second stage. */
- pIn = pDst;
-
- /* Reset to destination buffer working pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- /* Store the updated state variables back into the pState array */
- *pState++ = (q63_t) Xn1;
- *pState++ = (q63_t) Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* The variable acc hold output value that is being computed and
- * stored in the destination buffer
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- acc = (q63_t) Xn *b0;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) Xn1 *b1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) Xn2 *b2;
- /* acc += a1 * y[n-1] */
- acc += mult32x64(Yn1, a1);
- /* acc += a2 * y[n-2] */
- acc += mult32x64(Yn2, a2);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
-
- /* The result is converted to 1.63, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer in 1.31 format. */
- *pOut++ = acc_h;
-
- /* Yn1 = acc << shift; */
-
- /* Store the output in the destination buffer in 1.31 format. */
- /* *pOut++ = (q31_t) (acc >> (32 - shift)); */
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage output is given as input to the second stage. */
- pIn = pDst;
-
- /* Reset to destination buffer working pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- *pState++ = (q63_t) Xn1;
- *pState++ = (q63_t) Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
- /**
- * @} end of BiquadCascadeDF1_32x64 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
deleted file mode 100644
index 99fce40..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_f32.c
- * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
- *
- * This set of functions implements arbitrary order recursive (IIR) filters.
- * The filters are implemented as a cascade of second order Biquad sections.
- * The functions support Q15, Q31 and floating-point data types.
- * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
- *
- * The functions operate on blocks of input and output data and each call to the function
- * processes blockSize samples through the filter.
- * pSrc points to the array of input data and
- * pDst points to the array of output data.
- * Both arrays contain blockSize values.
- *
- * \par Algorithm
- * Each Biquad stage implements a second order filter using the difference equation:
- *
- * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- *
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
- * \image html Biquad.gif "Single Biquad filter stage"
- * Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
- * Pay careful attention to the sign of the feedback coefficients.
- * Some design tools use the difference equation
- *
- * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
- *
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
- *
- * \par
- * Higher order filters are realized as a cascade of second order sections.
- * numStages refers to the number of second order stages used.
- * For example, an 8th order filter would be realized with numStages=4 second order stages.
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
- *
- * \par
- * The pState points to state variables array.
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
- * The state variables are arranged in the pState array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- *
- * \par
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values.
- * The state variables are updated after each block of data is processed, the coefficients are untouched.
- *
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Init Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros before static initialization.
- * The code below statically initializes each of the 3 different data type filter instance structures
- *
- * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
- * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
- * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
- *
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
- * Following issues must be considered:
- * - Scaling of coefficients
- * - Filter gain
- * - Overflow and saturation
- *
- * \par
- * Scaling of coefficients:
- * Filter coefficients are represented as fractional values and
- * coefficients are restricted to lie in the range [-1 +1).
- * The fixed-point functions have an additional scaling parameter postShift
- * which allow the filter coefficients to exceed the range [+1 -1).
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
- * This essentially scales the filter coefficients by 2^postShift.
- * For example, to realize the coefficients
- *
- * {1.5, -0.8, 1.2, 1.6, -0.9}
- *
- * set the pCoeffs array to:
- *
- * {0.75, -0.4, 0.6, 0.8, -0.45}
- *
- * and set postShift=1
- *
- * \par
- * Filter gain:
- * The frequency response of a Biquad filter is a function of its coefficients.
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
- *
- * \par
- * Overflow and saturation:
- * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- */
-
-void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pIn = pSrc; /* source pointer */
- float32_t *pOut = pDst; /* destination pointer */
- float32_t *pState = S->pState; /* pState pointer */
- float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
- float32_t acc; /* Simulates the accumulator */
- float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
- float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
- float32_t Xn; /* temporary input */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the pState values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- /* The variable acc hold output values that are being computed:
- *
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u)
- {
- /* Read the first input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = Yn2;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
-
- /* Read the second input */
- Xn2 = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = Yn1;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
-
- /* Read the third input */
- Xn1 = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = Yn2;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
-
- /* Read the forth input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = Yn1;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
-
- /* decrement the loop counter */
- sample--;
-
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- sample = blockSize & 0x3u;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = acc;
-
- /* decrement the loop counter */
- sample--;
-
- }
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent numStages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset the output pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the pState values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* The variables acc holds the output value that is computed:
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = acc;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent numStages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset the output pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
- /**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
deleted file mode 100644
index c242cfe..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_fast_q15.c
- * Description: Fast processing function for the Q15 Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @details
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around and distorts the result.
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
- * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.
- *
- * \par
- * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
- * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.
- *
- */
-
-void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pIn = pSrc; /* Source pointer */
- q15_t *pOut = pDst; /* Destination pointer */
- q31_t in; /* Temporary variable to hold input value */
- q31_t out; /* Temporary variable to hold output value */
- q31_t b0; /* Temporary variable to hold bo value */
- q31_t b1, a1; /* Filter coefficients */
- q31_t state_in, state_out; /* Filter state variables */
- q31_t acc; /* Accumulator */
- int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- uint32_t sample, stage = S->numStages; /* Stage loop counter */
-
-
-
- do
- {
-
- /* Read the b0 and 0 coefficients using SIMD */
- b0 = *__SIMD32(pCoeffs)++;
-
- /* Read the b1 and b2 coefficients using SIMD */
- b1 = *__SIMD32(pCoeffs)++;
-
- /* Read the a1 and a2 coefficients using SIMD */
- a1 = *__SIMD32(pCoeffs)++;
-
- /* Read the input state values from the state buffer: x[n-1], x[n-2] */
- state_in = *__SIMD32(pState)++;
-
- /* Read the output state values from the state buffer: y[n-1], y[n-2] */
- state_out = *__SIMD32(pState)--;
-
- /* Apply loop unrolling and compute 2 output values simultaneously. */
- /* The variable acc hold output values that are being computed:
- *
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
- sample = blockSize >> 1u;
-
- /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
- ** a second loop below computes the remaining 1 sample. */
- while (sample > 0u)
- {
-
- /* Read the input */
- in = *__SIMD32(pIn)++;
-
- /* out = b0 * x[n] + 0 * 0 */
- out = __SMUAD(b0, in);
- /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
- acc = __SMLAD(b1, state_in, out);
- /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
- acc = __SMLAD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 and then saturation is applied */
- out = __SSAT((acc >> shift), 16);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
- state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* out = b0 * x[n] + 0 * 0 */
- out = __SMUADX(b0, in);
- /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
- acc = __SMLAD(b1, state_in, out);
- /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
- acc = __SMLAD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 and then saturation is applied */
- out = __SSAT((acc >> shift), 16);
-
-
- /* Store the output in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
- *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in >> 16, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, in, 16);
- state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
- /* Decrement the loop counter */
- sample--;
-
- }
-
- /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
- ** No loop unrolling is used. */
-
- if ((blockSize & 0x1u) != 0u)
- {
- /* Read the input */
- in = *pIn++;
-
- /* out = b0 * x[n] + 0 * 0 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out = __SMUAD(b0, in);
-
-#else
-
- out = __SMUADX(b0, in);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
- acc = __SMLAD(b1, state_in, out);
- /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
- acc = __SMLAD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 and then saturation is applied */
- out = __SSAT((acc >> shift), 16);
-
- /* Store the output in the destination buffer. */
- *pOut++ = (q15_t) out;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, in, 16);
- state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- }
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent (numStages - 1) occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset the output pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the state array */
- *__SIMD32(pState)++ = state_in;
- *__SIMD32(pState)++ = state_out;
-
-
- /* Decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-}
-
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
deleted file mode 100644
index e8ac074..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_fast_q31.c
- * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @details
- *
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
- * These intermediate results are added to a 2.30 accumulator.
- * Finally, the accumulator is saturated and converted to a 1.31 result.
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
- * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
- *
- * \par
- * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
- * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.
- */
-
-void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t acc = 0; /* accumulator */
- q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
- q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
- q31_t *pIn = pSrc; /* input pointer initialization */
- q31_t *pOut = pDst; /* output pointer initialization */
- q31_t *pState = S->pState; /* pState pointer initialization */
- q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
- q31_t Xn; /* temporary input */
- int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- /* The variables acc ... acc3 hold output values that are being computed:
- *
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- /*acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/
- mult_32x32_keep32_R(acc, b1, Xn1);
- /* acc += b1 * x[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b0, Xn);
- /* acc += b[2] * x[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b2, Xn2);
- /* acc += a1 * y[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a1, Yn1);
- /* acc += a2 * y[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a2, Yn2);
-
- /* The result is converted to 1.31 , Yn2 variable is reused */
- Yn2 = acc << shift;
-
- /* Read the second input */
- Xn2 = *(pIn + 1u);
-
- /* Store the output in the destination buffer. */
- *pOut = Yn2;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- /*acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/
- mult_32x32_keep32_R(acc, b0, Xn2);
- /* acc += b1 * x[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b1, Xn);
- /* acc += b[2] * x[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b2, Xn1);
- /* acc += a1 * y[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a1, Yn2);
- /* acc += a2 * y[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a2, Yn1);
-
- /* The result is converted to 1.31, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Read the third input */
- Xn1 = *(pIn + 2u);
-
- /* Store the output in the destination buffer. */
- *(pOut + 1u) = Yn1;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- /*acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/
- mult_32x32_keep32_R(acc, b0, Xn1);
- /* acc += b1 * x[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b1, Xn2);
- /* acc += b[2] * x[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b2, Xn);
- /* acc += a1 * y[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a1, Yn1);
- /* acc += a2 * y[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a2, Yn2);
-
- /* The result is converted to 1.31, Yn2 variable is reused */
- Yn2 = acc << shift;
-
- /* Read the forth input */
- Xn = *(pIn + 3u);
-
- /* Store the output in the destination buffer. */
- *(pOut + 2u) = Yn2;
- pIn += 4u;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
- mult_32x32_keep32_R(acc, b0, Xn);
- /* acc += b1 * x[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b1, Xn1);
- /* acc += b[2] * x[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b2, Xn2);
- /* acc += a1 * y[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a1, Yn2);
- /* acc += a2 * y[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a2, Yn1);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- Xn2 = Xn1;
-
- /* The result is converted to 1.31, Yn1 variable is reused */
- Yn1 = acc << shift;
-
- /* Xn1 = Xn */
- Xn1 = Xn;
-
- /* Store the output in the destination buffer. */
- *(pOut + 3u) = Yn1;
- pOut += 4u;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- sample = (blockSize & 0x3u);
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- /*acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
- mult_32x32_keep32_R(acc, b0, Xn);
- /* acc += b1 * x[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b1, Xn1);
- /* acc += b[2] * x[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, b2, Xn2);
- /* acc += a1 * y[n-1] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a1, Yn1);
- /* acc += a2 * y[n-2] */
- /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
- multAcc_32x32_keep32_R(acc, a2, Yn2);
-
- /* The result is converted to 1.31 */
- acc = acc << shift;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = acc;
-
- /* Store the output in the destination buffer. */
- *pOut++ = acc;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent stages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset to destination pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-}
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
deleted file mode 100644
index d100da0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_init_f32.c
- * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @details
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients array.
- * @param[in] *pState points to the state array.
- * @return none
- *
- *
- * Coefficient and State Ordering:
- *
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- *
- * \par
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState is a pointer to state array.
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
- * The state variables are arranged in the pState array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- *
- */
-
-void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 4 * numStages */
- memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
deleted file mode 100644
index 5ad21c1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_init_q15.c
- * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @details
- *
- * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
- * @return none
- *
- * Coefficient and State Ordering:
- *
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
- *
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 6*numStages values.
- * The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.
- *
- * \par
- * The state variables are stored in the array pState.
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
- * The state variables are arranged in the pState array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign postShift to be applied to the output */
- S->postShift = postShift;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 4 * numStages */
- memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
deleted file mode 100644
index 3cb6925..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_init_q31.c
- * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @details
- *
- * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
- * @return none
- *
- * Coefficient and State Ordering:
- *
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState points to state variables array.
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
- * The state variables are arranged in the pState array as:
- *
- * {x[n-1], x[n-2], y[n-1], y[n-2]}
- *
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
- * The state array has a total length of 4*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign postShift to be applied to the output */
- S->postShift = postShift;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 4 * numStages */
- memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
deleted file mode 100644
index 6a487c4..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_q15.c
- * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.
- * Finally, the result is saturated to 1.15 format.
- *
- * \par
- * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
- */
-
-void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t *pIn = pSrc; /* Source pointer */
- q15_t *pOut = pDst; /* Destination pointer */
- q31_t in; /* Temporary variable to hold input value */
- q31_t out; /* Temporary variable to hold output value */
- q31_t b0; /* Temporary variable to hold bo value */
- q31_t b1, a1; /* Filter coefficients */
- q31_t state_in, state_out; /* Filter state variables */
- q31_t acc_l, acc_h;
- q63_t acc; /* Accumulator */
- int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
- int32_t uShift = (32 - lShift);
-
- do
- {
- /* Read the b0 and 0 coefficients using SIMD */
- b0 = *__SIMD32(pCoeffs)++;
-
- /* Read the b1 and b2 coefficients using SIMD */
- b1 = *__SIMD32(pCoeffs)++;
-
- /* Read the a1 and a2 coefficients using SIMD */
- a1 = *__SIMD32(pCoeffs)++;
-
- /* Read the input state values from the state buffer: x[n-1], x[n-2] */
- state_in = *__SIMD32(pState)++;
-
- /* Read the output state values from the state buffer: y[n-1], y[n-2] */
- state_out = *__SIMD32(pState)--;
-
- /* Apply loop unrolling and compute 2 output values simultaneously. */
- /* The variable acc hold output values that are being computed:
- *
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
- sample = blockSize >> 1u;
-
- /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
- ** a second loop below computes the remaining 1 sample. */
- while (sample > 0u)
- {
-
- /* Read the input */
- in = *__SIMD32(pIn)++;
-
- /* out = b0 * x[n] + 0 * 0 */
- out = __SMUAD(b0, in);
-
- /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
- acc = __SMLALD(b1, state_in, out);
- /* acc += a1 * y[n-1] + a2 * y[n-2] */
- acc = __SMLALD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- out = __SSAT(out, 16);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
- state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* out = b0 * x[n] + 0 * 0 */
- out = __SMUADX(b0, in);
- /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
- acc = __SMLALD(b1, state_in, out);
- /* acc += a1 * y[n-1] + a2 * y[n-2] */
- acc = __SMLALD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- out = __SSAT(out, 16);
-
- /* Store the output in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
- *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in >> 16, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, in, 16);
- state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
- /* Decrement the loop counter */
- sample--;
-
- }
-
- /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
- ** No loop unrolling is used. */
-
- if ((blockSize & 0x1u) != 0u)
- {
- /* Read the input */
- in = *pIn++;
-
- /* out = b0 * x[n] + 0 * 0 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out = __SMUAD(b0, in);
-
-#else
-
- out = __SMUADX(b0, in);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
- acc = __SMLALD(b1, state_in, out);
- /* acc += a1 * y[n-1] + a2 * y[n-2] */
- acc = __SMLALD(a1, state_out, acc);
-
- /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- out = __SSAT(out, 16);
-
- /* Store the output in the destination buffer. */
- *pOut++ = (q15_t) out;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
- /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- state_in = __PKHBT(in, state_in, 16);
- state_out = __PKHBT(out, state_out, 16);
-
-#else
-
- state_in = __PKHBT(state_in >> 16, in, 16);
- state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- }
-
- /* The first stage goes from the input wire to the output wire. */
- /* Subsequent numStages occur in-place in the output wire */
- pIn = pDst;
-
- /* Reset the output pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the state array */
- *__SIMD32(pState)++ = state_in;
- *__SIMD32(pState)++ = state_out;
-
-
- /* Decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t *pIn = pSrc; /* Source pointer */
- q15_t *pOut = pDst; /* Destination pointer */
- q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
- q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
- q15_t Xn; /* temporary input */
- q63_t acc; /* Accumulator */
- int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- pCoeffs++; // skip the 0 coefficient
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* The variables acc holds the output value that is computed:
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- acc = (q31_t) b0 *Xn;
-
- /* acc += b1 * x[n-1] */
- acc += (q31_t) b1 *Xn1;
- /* acc += b[2] * x[n-2] */
- acc += (q31_t) b2 *Xn2;
- /* acc += a1 * y[n-1] */
- acc += (q31_t) a1 *Yn1;
- /* acc += a2 * y[n-2] */
- acc += (q31_t) a2 *Yn2;
-
- /* The result is converted to 1.31 */
- acc = __SSAT((acc >> shift), 16);
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = (q15_t) acc;
-
- /* Store the output in the destination buffer. */
- *pOut++ = (q15_t) acc;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent stages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset to destination pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
deleted file mode 100644
index 90d7ce1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df1_q31.c
- * Description: Processing function for the Q31 Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF1
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 Biquad cascade filter.
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
- * 1.31 format by discarding the low 32 bits.
- *
- * \par
- * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
- */
-
-void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q63_t acc; /* accumulator */
- uint32_t uShift = ((uint32_t) S->postShift + 1u);
- uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
- q31_t *pIn = pSrc; /* input pointer initialization */
- q31_t *pOut = pDst; /* output pointer initialization */
- q31_t *pState = S->pState; /* pState pointer initialization */
- q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
- q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
- q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
- q31_t Xn; /* temporary input */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-
-#if defined (ARM_MATH_DSP)
-
- q31_t acc_l, acc_h; /* temporary output variables */
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- /* The variable acc hold output values that are being computed:
- *
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn2;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn1;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn2;
-
- /* The result is converted to 1.31 , Yn2 variable is reused */
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer. */
- *pOut++ = Yn2;
-
- /* Read the second input */
- Xn2 = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn2;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn1;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn2;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn1;
-
-
- /* The result is converted to 1.31, Yn1 variable is reused */
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
-
- /* Apply shift for lower part of acc and upper part of acc */
- Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer. */
- *pOut++ = Yn1;
-
- /* Read the third input */
- Xn1 = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn1;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn2;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn1;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn2;
-
- /* The result is converted to 1.31, Yn2 variable is reused */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
-
- /* Apply shift for lower part of acc and upper part of acc */
- Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the output in the destination buffer. */
- *pOut++ = Yn2;
-
- /* Read the forth input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn2;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn2;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn1;
-
- /* The result is converted to 1.31, Yn1 variable is reused */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
-
- /* Store the output in the destination buffer. */
- *pOut++ = Yn1;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- sample = (blockSize & 0x3u);
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn;
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn2;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn1;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn2;
-
- /* The result is converted to 1.31 */
- acc = acc >> lShift;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = (q31_t) acc;
-
- /* Store the output in the destination buffer. */
- *pOut++ = (q31_t) acc;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent stages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset to destination pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /* Reading the state values */
- Xn1 = pState[0];
- Xn2 = pState[1];
- Yn1 = pState[2];
- Yn2 = pState[3];
-
- /* The variables acc holds the output value that is computed:
- * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
- */
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn = *pIn++;
-
- /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
- /* acc = b0 * x[n] */
- acc = (q63_t) b0 *Xn;
-
- /* acc += b1 * x[n-1] */
- acc += (q63_t) b1 *Xn1;
- /* acc += b[2] * x[n-2] */
- acc += (q63_t) b2 *Xn2;
- /* acc += a1 * y[n-1] */
- acc += (q63_t) a1 *Yn1;
- /* acc += a2 * y[n-2] */
- acc += (q63_t) a2 *Yn2;
-
- /* The result is converted to 1.31 */
- acc = acc >> lShift;
-
- /* Every time after the output is computed state should be updated. */
- /* The states should be updated as: */
- /* Xn2 = Xn1 */
- /* Xn1 = Xn */
- /* Yn2 = Yn1 */
- /* Yn1 = acc */
- Xn2 = Xn1;
- Xn1 = Xn;
- Yn2 = Yn1;
- Yn1 = (q31_t) acc;
-
- /* Store the output in the destination buffer. */
- *pOut++ = (q31_t) acc;
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* The first stage goes from the input buffer to the output buffer. */
- /* Subsequent stages occur in-place in the output buffer */
- pIn = pDst;
-
- /* Reset to destination pointer */
- pOut = pDst;
-
- /* Store the updated state variables back into the pState array */
- *pState++ = Xn1;
- *pState++ = Xn2;
- *pState++ = Yn1;
- *pState++ = Yn2;
-
- } while (--stage);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-
-
-
-/**
- * @} end of BiquadCascadeDF1 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
deleted file mode 100644
index 92fca88..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df2T_f32.c
- * Description: Processing function for floating-point transposed direct form II Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
-* @ingroup groupFilters
-*/
-
-/**
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
-*
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
-* The filters are implemented as a cascade of second order Biquad sections.
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
-* Only floating-point data is supported.
-*
-* This function operate on blocks of input and output data and each call to the function
-* processes blockSize samples through the filter.
-* pSrc points to the array of input data and
-* pDst points to the array of output data.
-* Both arrays contain blockSize values.
-*
-* \par Algorithm
-* Each Biquad stage implements a second order filter using the difference equation:
-*
-* y[n] = b0 * x[n] + d1
-* d1 = b1 * x[n] + a1 * y[n] + d2
-* d2 = b2 * x[n] + a2 * y[n]
-*
-* where d1 and d2 represent the two state values.
-*
-* \par
-* A Biquad filter using a transposed Direct Form II structure is shown below.
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
-* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
-* Pay careful attention to the sign of the feedback coefficients.
-* Some design tools flip the sign of the feedback coefficients:
-*
-* y[n] = b0 * x[n] + d1;
-* d1 = b1 * x[n] - a1 * y[n] + d2;
-* d2 = b2 * x[n] - a2 * y[n];
-*
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
-*
-* \par
-* Higher order filters are realized as a cascade of second order sections.
-* numStages refers to the number of second order stages used.
-* For example, an 8th order filter would be realized with numStages=4 second order stages.
-* A 9th order filter would be realized with numStages=5 second order stages with the
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
-*
-* \par
-* pState points to the state variable array.
-* Each Biquad stage has 2 state variables d1 and d2.
-* The state variables are arranged in the pState array as:
-*
-* {d11, d12, d21, d22, ...}
-*
-* where d1x refers to the state variables for the first Biquad and
-* d2x refers to the state variables for the second Biquad.
-* The state array has a total length of 2*numStages values.
-* The state variables are updated after each block of data is processed; the coefficients are untouched.
-*
-* \par
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
-* That is why the Direct Form I structure supports Q15 and Q31 data types.
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
-*
-* \par Instance Structure
-* The coefficients and state variables for a filter are stored together in an instance data structure.
-* A separate instance structure must be defined for each filter.
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
-*
-* \par Init Functions
-* There is also an associated initialization function.
-* The initialization function performs following operations:
-* - Sets the values of the internal structure fields.
-* - Zeros out the values in the state buffer.
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
-*
-* \par
-* Use of the initialization function is optional.
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
-* To place an instance structure into a const data section, the instance structure must be manually initialized.
-* Set the values in the state buffer to zeros before static initialization.
-* For example, to statically initialize the instance structure use
-*
-* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
-*
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
-* pCoeffs is the address of the coefficient buffer;
-*
-*/
-
-/**
-* @addtogroup BiquadCascadeDF2T
-* @{
-*/
-
-/**
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-* @param[in] *S points to an instance of the filter data structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[out] *pDst points to the block of output data
-* @param[in] blockSize number of samples to process.
-* @return none.
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_df2T_f32(
-const arm_biquad_cascade_df2T_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-
- float32_t *pIn = pSrc; /* source pointer */
- float32_t *pOut = pDst; /* destination pointer */
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
- float32_t acc1; /* accumulator */
- float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
- float32_t Xn1; /* temporary input */
- float32_t d1, d2; /* state variables */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-#if defined(ARM_MATH_CM7)
-
- float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
- float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
- float32_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
- float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
-
- do
- {
- /* Reading the coefficients */
- b0 = pCoeffs[0];
- b1 = pCoeffs[1];
- b2 = pCoeffs[2];
- a1 = pCoeffs[3];
- /* Apply loop unrolling and compute 16 output values simultaneously. */
- sample = blockSize >> 4u;
- a2 = pCoeffs[4];
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
- pCoeffs += 5u;
-
-
- /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
- ** a second loop below computes the remaining 1 to 15 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the first 2 inputs. 2 cycles */
- Xn1 = pIn[0 ];
- Xn2 = pIn[1 ];
-
- /* Sample 1. 5 cycles */
- Xn3 = pIn[2 ];
- acc1 = b0 * Xn1 + d1;
-
- Xn4 = pIn[3 ];
- d1 = b1 * Xn1 + d2;
-
- Xn5 = pIn[4 ];
- d2 = b2 * Xn1;
-
- Xn6 = pIn[5 ];
- d1 += a1 * acc1;
-
- Xn7 = pIn[6 ];
- d2 += a2 * acc1;
-
- /* Sample 2. 5 cycles */
- Xn8 = pIn[7 ];
- acc2 = b0 * Xn2 + d1;
-
- Xn9 = pIn[8 ];
- d1 = b1 * Xn2 + d2;
-
- Xn10 = pIn[9 ];
- d2 = b2 * Xn2;
-
- Xn11 = pIn[10];
- d1 += a1 * acc2;
-
- Xn12 = pIn[11];
- d2 += a2 * acc2;
-
- /* Sample 3. 5 cycles */
- Xn13 = pIn[12];
- acc3 = b0 * Xn3 + d1;
-
- Xn14 = pIn[13];
- d1 = b1 * Xn3 + d2;
-
- Xn15 = pIn[14];
- d2 = b2 * Xn3;
-
- Xn16 = pIn[15];
- d1 += a1 * acc3;
-
- pIn += 16;
- d2 += a2 * acc3;
-
- /* Sample 4. 5 cycles */
- acc4 = b0 * Xn4 + d1;
- d1 = b1 * Xn4 + d2;
- d2 = b2 * Xn4;
- d1 += a1 * acc4;
- d2 += a2 * acc4;
-
- /* Sample 5. 5 cycles */
- acc5 = b0 * Xn5 + d1;
- d1 = b1 * Xn5 + d2;
- d2 = b2 * Xn5;
- d1 += a1 * acc5;
- d2 += a2 * acc5;
-
- /* Sample 6. 5 cycles */
- acc6 = b0 * Xn6 + d1;
- d1 = b1 * Xn6 + d2;
- d2 = b2 * Xn6;
- d1 += a1 * acc6;
- d2 += a2 * acc6;
-
- /* Sample 7. 5 cycles */
- acc7 = b0 * Xn7 + d1;
- d1 = b1 * Xn7 + d2;
- d2 = b2 * Xn7;
- d1 += a1 * acc7;
- d2 += a2 * acc7;
-
- /* Sample 8. 5 cycles */
- acc8 = b0 * Xn8 + d1;
- d1 = b1 * Xn8 + d2;
- d2 = b2 * Xn8;
- d1 += a1 * acc8;
- d2 += a2 * acc8;
-
- /* Sample 9. 5 cycles */
- acc9 = b0 * Xn9 + d1;
- d1 = b1 * Xn9 + d2;
- d2 = b2 * Xn9;
- d1 += a1 * acc9;
- d2 += a2 * acc9;
-
- /* Sample 10. 5 cycles */
- acc10 = b0 * Xn10 + d1;
- d1 = b1 * Xn10 + d2;
- d2 = b2 * Xn10;
- d1 += a1 * acc10;
- d2 += a2 * acc10;
-
- /* Sample 11. 5 cycles */
- acc11 = b0 * Xn11 + d1;
- d1 = b1 * Xn11 + d2;
- d2 = b2 * Xn11;
- d1 += a1 * acc11;
- d2 += a2 * acc11;
-
- /* Sample 12. 5 cycles */
- acc12 = b0 * Xn12 + d1;
- d1 = b1 * Xn12 + d2;
- d2 = b2 * Xn12;
- d1 += a1 * acc12;
- d2 += a2 * acc12;
-
- /* Sample 13. 5 cycles */
- acc13 = b0 * Xn13 + d1;
- d1 = b1 * Xn13 + d2;
- d2 = b2 * Xn13;
-
- pOut[0 ] = acc1 ;
- d1 += a1 * acc13;
-
- pOut[1 ] = acc2 ;
- d2 += a2 * acc13;
-
- /* Sample 14. 5 cycles */
- pOut[2 ] = acc3 ;
- acc14 = b0 * Xn14 + d1;
-
- pOut[3 ] = acc4 ;
- d1 = b1 * Xn14 + d2;
-
- pOut[4 ] = acc5 ;
- d2 = b2 * Xn14;
-
- pOut[5 ] = acc6 ;
- d1 += a1 * acc14;
-
- pOut[6 ] = acc7 ;
- d2 += a2 * acc14;
-
- /* Sample 15. 5 cycles */
- pOut[7 ] = acc8 ;
- pOut[8 ] = acc9 ;
- acc15 = b0 * Xn15 + d1;
-
- pOut[9 ] = acc10;
- d1 = b1 * Xn15 + d2;
-
- pOut[10] = acc11;
- d2 = b2 * Xn15;
-
- pOut[11] = acc12;
- d1 += a1 * acc15;
-
- pOut[12] = acc13;
- d2 += a2 * acc15;
-
- /* Sample 16. 5 cycles */
- pOut[13] = acc14;
- acc16 = b0 * Xn16 + d1;
-
- pOut[14] = acc15;
- d1 = b1 * Xn16 + d2;
-
- pOut[15] = acc16;
- d2 = b2 * Xn16;
-
- sample--;
- d1 += a1 * acc16;
-
- pOut += 16;
- d2 += a2 * acc16;
- }
-
- sample = blockSize & 0xFu;
- while (sample > 0u) {
- Xn1 = *pIn;
- acc1 = b0 * Xn1 + d1;
-
- pIn++;
- d1 = b1 * Xn1 + d2;
-
- *pOut = acc1;
- d2 = b2 * Xn1;
-
- pOut++;
- d1 += a1 * acc1;
-
- sample--;
- d2 += a2 * acc1;
- }
-
- /* Store the updated state variables back into the state array */
- pState[0] = d1;
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- pState[1] = d2;
- /* decrement the loop counter */
- stage--;
-
- pState += 2u;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- } while (stage > 0u);
-
-#elif defined(ARM_MATH_CM0_FAMILY)
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn1 = *pIn++;
-
- /* y[n] = b0 * x[n] + d1 */
- acc1 = (b0 * Xn1) + d1;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc1;
-
- /* Every time after the output is computed state should be updated. */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
-
- /* d2 = b2 * x[n] + a2 * y[n] */
- d2 = (b2 * Xn1) + (a2 * acc1);
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1;
- *pState++ = d2;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#else
-
- float32_t Xn2, Xn3, Xn4; /* Input State variables */
- float32_t acc2, acc3, acc4; /* accumulator */
-
-
- float32_t p0, p1, p2, p3, p4, A1;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the four inputs */
- Xn1 = pIn[0];
- Xn2 = pIn[1];
- Xn3 = pIn[2];
- Xn4 = pIn[3];
- pIn += 4;
-
- p0 = b0 * Xn1;
- p1 = b1 * Xn1;
- acc1 = p0 + d1;
- p0 = b0 * Xn2;
- p3 = a1 * acc1;
- p2 = b2 * Xn1;
- A1 = p1 + p3;
- p4 = a2 * acc1;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- p1 = b1 * Xn2;
- acc2 = p0 + d1;
- p0 = b0 * Xn3;
- p3 = a1 * acc2;
- p2 = b2 * Xn2;
- A1 = p1 + p3;
- p4 = a2 * acc2;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- p1 = b1 * Xn3;
- acc3 = p0 + d1;
- p0 = b0 * Xn4;
- p3 = a1 * acc3;
- p2 = b2 * Xn3;
- A1 = p1 + p3;
- p4 = a2 * acc3;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- acc4 = p0 + d1;
- p1 = b1 * Xn4;
- p3 = a1 * acc4;
- p2 = b2 * Xn4;
- A1 = p1 + p3;
- p4 = a2 * acc4;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- pOut[0] = acc1;
- pOut[1] = acc2;
- pOut[2] = acc3;
- pOut[3] = acc4;
- pOut += 4;
-
- sample--;
- }
-
- sample = blockSize & 0x3u;
- while (sample > 0u) {
- Xn1 = *pIn++;
-
- p0 = b0 * Xn1;
- p1 = b1 * Xn1;
- acc1 = p0 + d1;
- p3 = a1 * acc1;
- p2 = b2 * Xn1;
- A1 = p1 + p3;
- p4 = a2 * acc1;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- *pOut++ = acc1;
-
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1;
- *pState++ = d2;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#endif
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
deleted file mode 100644
index 2a26525..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df2T_f64.c
- * Description: Processing function for floating-point transposed direct form II Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
-* @ingroup groupFilters
-*/
-
-/**
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
-*
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
-* The filters are implemented as a cascade of second order Biquad sections.
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
-* Only floating-point data is supported.
-*
-* This function operate on blocks of input and output data and each call to the function
-* processes blockSize samples through the filter.
-* pSrc points to the array of input data and
-* pDst points to the array of output data.
-* Both arrays contain blockSize values.
-*
-* \par Algorithm
-* Each Biquad stage implements a second order filter using the difference equation:
-*
-* y[n] = b0 * x[n] + d1
-* d1 = b1 * x[n] + a1 * y[n] + d2
-* d2 = b2 * x[n] + a2 * y[n]
-*
-* where d1 and d2 represent the two state values.
-*
-* \par
-* A Biquad filter using a transposed Direct Form II structure is shown below.
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
-* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
-* Pay careful attention to the sign of the feedback coefficients.
-* Some design tools flip the sign of the feedback coefficients:
-*
-* y[n] = b0 * x[n] + d1;
-* d1 = b1 * x[n] - a1 * y[n] + d2;
-* d2 = b2 * x[n] - a2 * y[n];
-*
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
-*
-* \par
-* Higher order filters are realized as a cascade of second order sections.
-* numStages refers to the number of second order stages used.
-* For example, an 8th order filter would be realized with numStages=4 second order stages.
-* A 9th order filter would be realized with numStages=5 second order stages with the
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
-*
-* \par
-* pState points to the state variable array.
-* Each Biquad stage has 2 state variables d1 and d2.
-* The state variables are arranged in the pState array as:
-*
-* {d11, d12, d21, d22, ...}
-*
-* where d1x refers to the state variables for the first Biquad and
-* d2x refers to the state variables for the second Biquad.
-* The state array has a total length of 2*numStages values.
-* The state variables are updated after each block of data is processed; the coefficients are untouched.
-*
-* \par
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
-* That is why the Direct Form I structure supports Q15 and Q31 data types.
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
-*
-* \par Instance Structure
-* The coefficients and state variables for a filter are stored together in an instance data structure.
-* A separate instance structure must be defined for each filter.
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
-*
-* \par Init Functions
-* There is also an associated initialization function.
-* The initialization function performs following operations:
-* - Sets the values of the internal structure fields.
-* - Zeros out the values in the state buffer.
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
-*
-* \par
-* Use of the initialization function is optional.
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
-* To place an instance structure into a const data section, the instance structure must be manually initialized.
-* Set the values in the state buffer to zeros before static initialization.
-* For example, to statically initialize the instance structure use
-*
-* arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
-*
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
-* pCoeffs is the address of the coefficient buffer;
-*
-*/
-
-/**
-* @addtogroup BiquadCascadeDF2T
-* @{
-*/
-
-/**
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-* @param[in] *S points to an instance of the filter data structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[out] *pDst points to the block of output data
-* @param[in] blockSize number of samples to process.
-* @return none.
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_df2T_f64(
-const arm_biquad_cascade_df2T_instance_f64 * S,
-float64_t * pSrc,
-float64_t * pDst,
-uint32_t blockSize)
-{
-
- float64_t *pIn = pSrc; /* source pointer */
- float64_t *pOut = pDst; /* destination pointer */
- float64_t *pState = S->pState; /* State pointer */
- float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
- float64_t acc1; /* accumulator */
- float64_t b0, b1, b2, a1, a2; /* Filter coefficients */
- float64_t Xn1; /* temporary input */
- float64_t d1, d2; /* state variables */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-#if defined(ARM_MATH_CM7)
-
- float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
- float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
- float64_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
- float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
-
- do
- {
- /* Reading the coefficients */
- b0 = pCoeffs[0];
- b1 = pCoeffs[1];
- b2 = pCoeffs[2];
- a1 = pCoeffs[3];
- /* Apply loop unrolling and compute 16 output values simultaneously. */
- sample = blockSize >> 4u;
- a2 = pCoeffs[4];
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
- pCoeffs += 5u;
-
-
- /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
- ** a second loop below computes the remaining 1 to 15 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the first 2 inputs. 2 cycles */
- Xn1 = pIn[0 ];
- Xn2 = pIn[1 ];
-
- /* Sample 1. 5 cycles */
- Xn3 = pIn[2 ];
- acc1 = b0 * Xn1 + d1;
-
- Xn4 = pIn[3 ];
- d1 = b1 * Xn1 + d2;
-
- Xn5 = pIn[4 ];
- d2 = b2 * Xn1;
-
- Xn6 = pIn[5 ];
- d1 += a1 * acc1;
-
- Xn7 = pIn[6 ];
- d2 += a2 * acc1;
-
- /* Sample 2. 5 cycles */
- Xn8 = pIn[7 ];
- acc2 = b0 * Xn2 + d1;
-
- Xn9 = pIn[8 ];
- d1 = b1 * Xn2 + d2;
-
- Xn10 = pIn[9 ];
- d2 = b2 * Xn2;
-
- Xn11 = pIn[10];
- d1 += a1 * acc2;
-
- Xn12 = pIn[11];
- d2 += a2 * acc2;
-
- /* Sample 3. 5 cycles */
- Xn13 = pIn[12];
- acc3 = b0 * Xn3 + d1;
-
- Xn14 = pIn[13];
- d1 = b1 * Xn3 + d2;
-
- Xn15 = pIn[14];
- d2 = b2 * Xn3;
-
- Xn16 = pIn[15];
- d1 += a1 * acc3;
-
- pIn += 16;
- d2 += a2 * acc3;
-
- /* Sample 4. 5 cycles */
- acc4 = b0 * Xn4 + d1;
- d1 = b1 * Xn4 + d2;
- d2 = b2 * Xn4;
- d1 += a1 * acc4;
- d2 += a2 * acc4;
-
- /* Sample 5. 5 cycles */
- acc5 = b0 * Xn5 + d1;
- d1 = b1 * Xn5 + d2;
- d2 = b2 * Xn5;
- d1 += a1 * acc5;
- d2 += a2 * acc5;
-
- /* Sample 6. 5 cycles */
- acc6 = b0 * Xn6 + d1;
- d1 = b1 * Xn6 + d2;
- d2 = b2 * Xn6;
- d1 += a1 * acc6;
- d2 += a2 * acc6;
-
- /* Sample 7. 5 cycles */
- acc7 = b0 * Xn7 + d1;
- d1 = b1 * Xn7 + d2;
- d2 = b2 * Xn7;
- d1 += a1 * acc7;
- d2 += a2 * acc7;
-
- /* Sample 8. 5 cycles */
- acc8 = b0 * Xn8 + d1;
- d1 = b1 * Xn8 + d2;
- d2 = b2 * Xn8;
- d1 += a1 * acc8;
- d2 += a2 * acc8;
-
- /* Sample 9. 5 cycles */
- acc9 = b0 * Xn9 + d1;
- d1 = b1 * Xn9 + d2;
- d2 = b2 * Xn9;
- d1 += a1 * acc9;
- d2 += a2 * acc9;
-
- /* Sample 10. 5 cycles */
- acc10 = b0 * Xn10 + d1;
- d1 = b1 * Xn10 + d2;
- d2 = b2 * Xn10;
- d1 += a1 * acc10;
- d2 += a2 * acc10;
-
- /* Sample 11. 5 cycles */
- acc11 = b0 * Xn11 + d1;
- d1 = b1 * Xn11 + d2;
- d2 = b2 * Xn11;
- d1 += a1 * acc11;
- d2 += a2 * acc11;
-
- /* Sample 12. 5 cycles */
- acc12 = b0 * Xn12 + d1;
- d1 = b1 * Xn12 + d2;
- d2 = b2 * Xn12;
- d1 += a1 * acc12;
- d2 += a2 * acc12;
-
- /* Sample 13. 5 cycles */
- acc13 = b0 * Xn13 + d1;
- d1 = b1 * Xn13 + d2;
- d2 = b2 * Xn13;
-
- pOut[0 ] = acc1 ;
- d1 += a1 * acc13;
-
- pOut[1 ] = acc2 ;
- d2 += a2 * acc13;
-
- /* Sample 14. 5 cycles */
- pOut[2 ] = acc3 ;
- acc14 = b0 * Xn14 + d1;
-
- pOut[3 ] = acc4 ;
- d1 = b1 * Xn14 + d2;
-
- pOut[4 ] = acc5 ;
- d2 = b2 * Xn14;
-
- pOut[5 ] = acc6 ;
- d1 += a1 * acc14;
-
- pOut[6 ] = acc7 ;
- d2 += a2 * acc14;
-
- /* Sample 15. 5 cycles */
- pOut[7 ] = acc8 ;
- pOut[8 ] = acc9 ;
- acc15 = b0 * Xn15 + d1;
-
- pOut[9 ] = acc10;
- d1 = b1 * Xn15 + d2;
-
- pOut[10] = acc11;
- d2 = b2 * Xn15;
-
- pOut[11] = acc12;
- d1 += a1 * acc15;
-
- pOut[12] = acc13;
- d2 += a2 * acc15;
-
- /* Sample 16. 5 cycles */
- pOut[13] = acc14;
- acc16 = b0 * Xn16 + d1;
-
- pOut[14] = acc15;
- d1 = b1 * Xn16 + d2;
-
- pOut[15] = acc16;
- d2 = b2 * Xn16;
-
- sample--;
- d1 += a1 * acc16;
-
- pOut += 16;
- d2 += a2 * acc16;
- }
-
- sample = blockSize & 0xFu;
- while (sample > 0u) {
- Xn1 = *pIn;
- acc1 = b0 * Xn1 + d1;
-
- pIn++;
- d1 = b1 * Xn1 + d2;
-
- *pOut = acc1;
- d2 = b2 * Xn1;
-
- pOut++;
- d1 += a1 * acc1;
-
- sample--;
- d2 += a2 * acc1;
- }
-
- /* Store the updated state variables back into the state array */
- pState[0] = d1;
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- pState[1] = d2;
- /* decrement the loop counter */
- stage--;
-
- pState += 2u;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- } while (stage > 0u);
-
-#elif defined(ARM_MATH_CM0_FAMILY)
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn1 = *pIn++;
-
- /* y[n] = b0 * x[n] + d1 */
- acc1 = (b0 * Xn1) + d1;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc1;
-
- /* Every time after the output is computed state should be updated. */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
-
- /* d2 = b2 * x[n] + a2 * y[n] */
- d2 = (b2 * Xn1) + (a2 * acc1);
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1;
- *pState++ = d2;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#else
-
- float64_t Xn2, Xn3, Xn4; /* Input State variables */
- float64_t acc2, acc3, acc4; /* accumulator */
-
-
- float64_t p0, p1, p2, p3, p4, A1;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
-
- /*Reading the state values */
- d1 = pState[0];
- d2 = pState[1];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the four inputs */
- Xn1 = pIn[0];
- Xn2 = pIn[1];
- Xn3 = pIn[2];
- Xn4 = pIn[3];
- pIn += 4;
-
- p0 = b0 * Xn1;
- p1 = b1 * Xn1;
- acc1 = p0 + d1;
- p0 = b0 * Xn2;
- p3 = a1 * acc1;
- p2 = b2 * Xn1;
- A1 = p1 + p3;
- p4 = a2 * acc1;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- p1 = b1 * Xn2;
- acc2 = p0 + d1;
- p0 = b0 * Xn3;
- p3 = a1 * acc2;
- p2 = b2 * Xn2;
- A1 = p1 + p3;
- p4 = a2 * acc2;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- p1 = b1 * Xn3;
- acc3 = p0 + d1;
- p0 = b0 * Xn4;
- p3 = a1 * acc3;
- p2 = b2 * Xn3;
- A1 = p1 + p3;
- p4 = a2 * acc3;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- acc4 = p0 + d1;
- p1 = b1 * Xn4;
- p3 = a1 * acc4;
- p2 = b2 * Xn4;
- A1 = p1 + p3;
- p4 = a2 * acc4;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- pOut[0] = acc1;
- pOut[1] = acc2;
- pOut[2] = acc3;
- pOut[3] = acc4;
- pOut += 4;
-
- sample--;
- }
-
- sample = blockSize & 0x3u;
- while (sample > 0u) {
- Xn1 = *pIn++;
-
- p0 = b0 * Xn1;
- p1 = b1 * Xn1;
- acc1 = p0 + d1;
- p3 = a1 * acc1;
- p2 = b2 * Xn1;
- A1 = p1 + p3;
- p4 = a2 * acc1;
- d1 = A1 + d2;
- d2 = p2 + p4;
-
- *pOut++ = acc1;
-
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1;
- *pState++ = d2;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#endif
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
deleted file mode 100644
index 310771f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df2T_init_f32.c
- * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF2T
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- *
- * Coefficient and State Ordering:
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- *
- * \par
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState is a pointer to state array.
- * Each Biquad stage has 2 state variables d1, and d2.
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
- * The state array has a total length of 2*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 2 * numStages */
- memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
deleted file mode 100644
index 545ebce..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_df2T_init_f64.c
- * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF2T
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- *
- * Coefficient and State Ordering:
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- *
- * \par
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState is a pointer to state array.
- * Each Biquad stage has 2 state variables d1, and d2.
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
- * The state array has a total length of 2*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 2 * numStages */
- memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float64_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
deleted file mode 100644
index e4c31be..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
+++ /dev/null
@@ -1,670 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_stereo_df2T_f32.c
- * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
-* @ingroup groupFilters
-*/
-
-/**
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
-*
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
-* The filters are implemented as a cascade of second order Biquad sections.
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
-* Only floating-point data is supported.
-*
-* This function operate on blocks of input and output data and each call to the function
-* processes blockSize samples through the filter.
-* pSrc points to the array of input data and
-* pDst points to the array of output data.
-* Both arrays contain blockSize values.
-*
-* \par Algorithm
-* Each Biquad stage implements a second order filter using the difference equation:
-*
-* y[n] = b0 * x[n] + d1
-* d1 = b1 * x[n] + a1 * y[n] + d2
-* d2 = b2 * x[n] + a2 * y[n]
-*
-* where d1 and d2 represent the two state values.
-*
-* \par
-* A Biquad filter using a transposed Direct Form II structure is shown below.
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
-* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
-* Pay careful attention to the sign of the feedback coefficients.
-* Some design tools flip the sign of the feedback coefficients:
-*
-* y[n] = b0 * x[n] + d1;
-* d1 = b1 * x[n] - a1 * y[n] + d2;
-* d2 = b2 * x[n] - a2 * y[n];
-*
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
-*
-* \par
-* Higher order filters are realized as a cascade of second order sections.
-* numStages refers to the number of second order stages used.
-* For example, an 8th order filter would be realized with numStages=4 second order stages.
-* A 9th order filter would be realized with numStages=5 second order stages with the
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
-*
-* \par
-* pState points to the state variable array.
-* Each Biquad stage has 2 state variables d1 and d2.
-* The state variables are arranged in the pState array as:
-*
-* {d11, d12, d21, d22, ...}
-*
-* where d1x refers to the state variables for the first Biquad and
-* d2x refers to the state variables for the second Biquad.
-* The state array has a total length of 2*numStages values.
-* The state variables are updated after each block of data is processed; the coefficients are untouched.
-*
-* \par
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
-* That is why the Direct Form I structure supports Q15 and Q31 data types.
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
-*
-* \par Instance Structure
-* The coefficients and state variables for a filter are stored together in an instance data structure.
-* A separate instance structure must be defined for each filter.
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
-*
-* \par Init Functions
-* There is also an associated initialization function.
-* The initialization function performs following operations:
-* - Sets the values of the internal structure fields.
-* - Zeros out the values in the state buffer.
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
-*
-* \par
-* Use of the initialization function is optional.
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
-* To place an instance structure into a const data section, the instance structure must be manually initialized.
-* Set the values in the state buffer to zeros before static initialization.
-* For example, to statically initialize the instance structure use
-*
-* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
-*
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
-* pCoeffs is the address of the coefficient buffer;
-*
-*/
-
-/**
-* @addtogroup BiquadCascadeDF2T
-* @{
-*/
-
-/**
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-* @param[in] *S points to an instance of the filter data structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[out] *pDst points to the block of output data
-* @param[in] blockSize number of samples to process.
-* @return none.
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_stereo_df2T_f32(
-const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-
- float32_t *pIn = pSrc; /* source pointer */
- float32_t *pOut = pDst; /* destination pointer */
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
- float32_t acc1a, acc1b; /* accumulator */
- float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
- float32_t Xn1a, Xn1b; /* temporary input */
- float32_t d1a, d2a, d1b, d2b; /* state variables */
- uint32_t sample, stage = S->numStages; /* loop counters */
-
-#if defined(ARM_MATH_CM7)
-
- float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a; /* Input State variables */
- float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b; /* Input State variables */
- float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a; /* Simulates the accumulator */
- float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b; /* Simulates the accumulator */
-
- do
- {
- /* Reading the coefficients */
- b0 = pCoeffs[0];
- b1 = pCoeffs[1];
- b2 = pCoeffs[2];
- a1 = pCoeffs[3];
- /* Apply loop unrolling and compute 8 output values simultaneously. */
- sample = blockSize >> 3u;
- a2 = pCoeffs[4];
-
- /*Reading the state values */
- d1a = pState[0];
- d2a = pState[1];
- d1b = pState[2];
- d2b = pState[3];
-
- pCoeffs += 5u;
-
- /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
- ** a second loop below computes the remaining 1 to 7 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the first 2 inputs. 2 cycles */
- Xn1a = pIn[0 ];
- Xn1b = pIn[1 ];
-
- /* Sample 1. 5 cycles */
- Xn2a = pIn[2 ];
- acc1a = b0 * Xn1a + d1a;
-
- Xn2b = pIn[3 ];
- d1a = b1 * Xn1a + d2a;
-
- Xn3a = pIn[4 ];
- d2a = b2 * Xn1a;
-
- Xn3b = pIn[5 ];
- d1a += a1 * acc1a;
-
- Xn4a = pIn[6 ];
- d2a += a2 * acc1a;
-
- /* Sample 2. 5 cycles */
- Xn4b = pIn[7 ];
- acc1b = b0 * Xn1b + d1b;
-
- Xn5a = pIn[8 ];
- d1b = b1 * Xn1b + d2b;
-
- Xn5b = pIn[9 ];
- d2b = b2 * Xn1b;
-
- Xn6a = pIn[10];
- d1b += a1 * acc1b;
-
- Xn6b = pIn[11];
- d2b += a2 * acc1b;
-
- /* Sample 3. 5 cycles */
- Xn7a = pIn[12];
- acc2a = b0 * Xn2a + d1a;
-
- Xn7b = pIn[13];
- d1a = b1 * Xn2a + d2a;
-
- Xn8a = pIn[14];
- d2a = b2 * Xn2a;
-
- Xn8b = pIn[15];
- d1a += a1 * acc2a;
-
- pIn += 16;
- d2a += a2 * acc2a;
-
- /* Sample 4. 5 cycles */
- acc2b = b0 * Xn2b + d1b;
- d1b = b1 * Xn2b + d2b;
- d2b = b2 * Xn2b;
- d1b += a1 * acc2b;
- d2b += a2 * acc2b;
-
- /* Sample 5. 5 cycles */
- acc3a = b0 * Xn3a + d1a;
- d1a = b1 * Xn3a + d2a;
- d2a = b2 * Xn3a;
- d1a += a1 * acc3a;
- d2a += a2 * acc3a;
-
- /* Sample 6. 5 cycles */
- acc3b = b0 * Xn3b + d1b;
- d1b = b1 * Xn3b + d2b;
- d2b = b2 * Xn3b;
- d1b += a1 * acc3b;
- d2b += a2 * acc3b;
-
- /* Sample 7. 5 cycles */
- acc4a = b0 * Xn4a + d1a;
- d1a = b1 * Xn4a + d2a;
- d2a = b2 * Xn4a;
- d1a += a1 * acc4a;
- d2a += a2 * acc4a;
-
- /* Sample 8. 5 cycles */
- acc4b = b0 * Xn4b + d1b;
- d1b = b1 * Xn4b + d2b;
- d2b = b2 * Xn4b;
- d1b += a1 * acc4b;
- d2b += a2 * acc4b;
-
- /* Sample 9. 5 cycles */
- acc5a = b0 * Xn5a + d1a;
- d1a = b1 * Xn5a + d2a;
- d2a = b2 * Xn5a;
- d1a += a1 * acc5a;
- d2a += a2 * acc5a;
-
- /* Sample 10. 5 cycles */
- acc5b = b0 * Xn5b + d1b;
- d1b = b1 * Xn5b + d2b;
- d2b = b2 * Xn5b;
- d1b += a1 * acc5b;
- d2b += a2 * acc5b;
-
- /* Sample 11. 5 cycles */
- acc6a = b0 * Xn6a + d1a;
- d1a = b1 * Xn6a + d2a;
- d2a = b2 * Xn6a;
- d1a += a1 * acc6a;
- d2a += a2 * acc6a;
-
- /* Sample 12. 5 cycles */
- acc6b = b0 * Xn6b + d1b;
- d1b = b1 * Xn6b + d2b;
- d2b = b2 * Xn6b;
- d1b += a1 * acc6b;
- d2b += a2 * acc6b;
-
- /* Sample 13. 5 cycles */
- acc7a = b0 * Xn7a + d1a;
- d1a = b1 * Xn7a + d2a;
-
- pOut[0 ] = acc1a ;
- d2a = b2 * Xn7a;
-
- pOut[1 ] = acc1b ;
- d1a += a1 * acc7a;
-
- pOut[2 ] = acc2a ;
- d2a += a2 * acc7a;
-
- /* Sample 14. 5 cycles */
- pOut[3 ] = acc2b ;
- acc7b = b0 * Xn7b + d1b;
-
- pOut[4 ] = acc3a ;
- d1b = b1 * Xn7b + d2b;
-
- pOut[5 ] = acc3b ;
- d2b = b2 * Xn7b;
-
- pOut[6 ] = acc4a ;
- d1b += a1 * acc7b;
-
- pOut[7 ] = acc4b ;
- d2b += a2 * acc7b;
-
- /* Sample 15. 5 cycles */
- pOut[8 ] = acc5a ;
- acc8a = b0 * Xn8a + d1a;
-
- pOut[9 ] = acc5b;
- d1a = b1 * Xn8a + d2a;
-
- pOut[10] = acc6a;
- d2a = b2 * Xn8a;
-
- pOut[11] = acc6b;
- d1a += a1 * acc8a;
-
- pOut[12] = acc7a;
- d2a += a2 * acc8a;
-
- /* Sample 16. 5 cycles */
- pOut[13] = acc7b;
- acc8b = b0 * Xn8b + d1b;
-
- pOut[14] = acc8a;
- d1b = b1 * Xn8b + d2b;
-
- pOut[15] = acc8b;
- d2b = b2 * Xn8b;
-
- sample--;
- d1b += a1 * acc8b;
-
- pOut += 16;
- d2b += a2 * acc8b;
- }
-
- sample = blockSize & 0x7u;
- while (sample > 0u) {
- /* Read the input */
- Xn1a = *pIn++; //Channel a
- Xn1b = *pIn++; //Channel b
-
- /* y[n] = b0 * x[n] + d1 */
- acc1a = (b0 * Xn1a) + d1a;
- acc1b = (b0 * Xn1b) + d1b;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc1a;
- *pOut++ = acc1b;
-
- /* Every time after the output is computed state should be updated. */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
- d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
-
- /* d2 = b2 * x[n] + a2 * y[n] */
- d2a = (b2 * Xn1a) + (a2 * acc1a);
- d2b = (b2 * Xn1b) + (a2 * acc1b);
-
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- pState[0] = d1a;
- pState[1] = d2a;
-
- pState[2] = d1b;
- pState[3] = d2b;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
- /* decrement the loop counter */
- stage--;
-
- pState += 4u;
- /*Reset the output working pointer */
- pOut = pDst;
-
- } while (stage > 0u);
-
-#elif defined(ARM_MATH_CM0_FAMILY)
-
- /* Run the below code for Cortex-M0 */
-
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /*Reading the state values */
- d1a = pState[0];
- d2a = pState[1];
- d1b = pState[2];
- d2b = pState[3];
-
-
- sample = blockSize;
-
- while (sample > 0u)
- {
- /* Read the input */
- Xn1a = *pIn++; //Channel a
- Xn1b = *pIn++; //Channel b
-
- /* y[n] = b0 * x[n] + d1 */
- acc1a = (b0 * Xn1a) + d1a;
- acc1b = (b0 * Xn1b) + d1b;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc1a;
- *pOut++ = acc1b;
-
- /* Every time after the output is computed state should be updated. */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
- d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
-
- /* d2 = b2 * x[n] + a2 * y[n] */
- d2a = (b2 * Xn1a) + (a2 * acc1a);
- d2b = (b2 * Xn1b) + (a2 * acc1b);
-
- /* decrement the loop counter */
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1a;
- *pState++ = d2a;
- *pState++ = d1b;
- *pState++ = d2b;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#else
-
- float32_t Xn2a, Xn3a, Xn4a; /* Input State variables */
- float32_t Xn2b, Xn3b, Xn4b; /* Input State variables */
- float32_t acc2a, acc3a, acc4a; /* accumulator */
- float32_t acc2b, acc3b, acc4b; /* accumulator */
- float32_t p0a, p1a, p2a, p3a, p4a, A1a;
- float32_t p0b, p1b, p2b, p3b, p4b, A1b;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- do
- {
- /* Reading the coefficients */
- b0 = *pCoeffs++;
- b1 = *pCoeffs++;
- b2 = *pCoeffs++;
- a1 = *pCoeffs++;
- a2 = *pCoeffs++;
-
- /*Reading the state values */
- d1a = pState[0];
- d2a = pState[1];
- d1b = pState[2];
- d2b = pState[3];
-
- /* Apply loop unrolling and compute 4 output values simultaneously. */
- sample = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (sample > 0u) {
-
- /* y[n] = b0 * x[n] + d1 */
- /* d1 = b1 * x[n] + a1 * y[n] + d2 */
- /* d2 = b2 * x[n] + a2 * y[n] */
-
- /* Read the four inputs */
- Xn1a = pIn[0];
- Xn1b = pIn[1];
- Xn2a = pIn[2];
- Xn2b = pIn[3];
- Xn3a = pIn[4];
- Xn3b = pIn[5];
- Xn4a = pIn[6];
- Xn4b = pIn[7];
- pIn += 8;
-
- p0a = b0 * Xn1a;
- p0b = b0 * Xn1b;
- p1a = b1 * Xn1a;
- p1b = b1 * Xn1b;
- acc1a = p0a + d1a;
- acc1b = p0b + d1b;
- p0a = b0 * Xn2a;
- p0b = b0 * Xn2b;
- p3a = a1 * acc1a;
- p3b = a1 * acc1b;
- p2a = b2 * Xn1a;
- p2b = b2 * Xn1b;
- A1a = p1a + p3a;
- A1b = p1b + p3b;
- p4a = a2 * acc1a;
- p4b = a2 * acc1b;
- d1a = A1a + d2a;
- d1b = A1b + d2b;
- d2a = p2a + p4a;
- d2b = p2b + p4b;
-
- p1a = b1 * Xn2a;
- p1b = b1 * Xn2b;
- acc2a = p0a + d1a;
- acc2b = p0b + d1b;
- p0a = b0 * Xn3a;
- p0b = b0 * Xn3b;
- p3a = a1 * acc2a;
- p3b = a1 * acc2b;
- p2a = b2 * Xn2a;
- p2b = b2 * Xn2b;
- A1a = p1a + p3a;
- A1b = p1b + p3b;
- p4a = a2 * acc2a;
- p4b = a2 * acc2b;
- d1a = A1a + d2a;
- d1b = A1b + d2b;
- d2a = p2a + p4a;
- d2b = p2b + p4b;
-
- p1a = b1 * Xn3a;
- p1b = b1 * Xn3b;
- acc3a = p0a + d1a;
- acc3b = p0b + d1b;
- p0a = b0 * Xn4a;
- p0b = b0 * Xn4b;
- p3a = a1 * acc3a;
- p3b = a1 * acc3b;
- p2a = b2 * Xn3a;
- p2b = b2 * Xn3b;
- A1a = p1a + p3a;
- A1b = p1b + p3b;
- p4a = a2 * acc3a;
- p4b = a2 * acc3b;
- d1a = A1a + d2a;
- d1b = A1b + d2b;
- d2a = p2a + p4a;
- d2b = p2b + p4b;
-
- acc4a = p0a + d1a;
- acc4b = p0b + d1b;
- p1a = b1 * Xn4a;
- p1b = b1 * Xn4b;
- p3a = a1 * acc4a;
- p3b = a1 * acc4b;
- p2a = b2 * Xn4a;
- p2b = b2 * Xn4b;
- A1a = p1a + p3a;
- A1b = p1b + p3b;
- p4a = a2 * acc4a;
- p4b = a2 * acc4b;
- d1a = A1a + d2a;
- d1b = A1b + d2b;
- d2a = p2a + p4a;
- d2b = p2b + p4b;
-
- pOut[0] = acc1a;
- pOut[1] = acc1b;
- pOut[2] = acc2a;
- pOut[3] = acc2b;
- pOut[4] = acc3a;
- pOut[5] = acc3b;
- pOut[6] = acc4a;
- pOut[7] = acc4b;
- pOut += 8;
-
- sample--;
- }
-
- sample = blockSize & 0x3u;
- while (sample > 0u) {
- Xn1a = *pIn++;
- Xn1b = *pIn++;
-
- p0a = b0 * Xn1a;
- p0b = b0 * Xn1b;
- p1a = b1 * Xn1a;
- p1b = b1 * Xn1b;
- acc1a = p0a + d1a;
- acc1b = p0b + d1b;
- p3a = a1 * acc1a;
- p3b = a1 * acc1b;
- p2a = b2 * Xn1a;
- p2b = b2 * Xn1b;
- A1a = p1a + p3a;
- A1b = p1b + p3b;
- p4a = a2 * acc1a;
- p4b = a2 * acc1b;
- d1a = A1a + d2a;
- d1b = A1b + d2b;
- d2a = p2a + p4a;
- d2b = p2b + p4b;
-
- *pOut++ = acc1a;
- *pOut++ = acc1b;
-
- sample--;
- }
-
- /* Store the updated state variables back into the state array */
- *pState++ = d1a;
- *pState++ = d2a;
- *pState++ = d1b;
- *pState++ = d2b;
-
- /* The current stage input is given as the output to the next stage */
- pIn = pDst;
-
- /*Reset the output working pointer */
- pOut = pDst;
-
- /* decrement the loop counter */
- stage--;
-
- } while (stage > 0u);
-
-#endif
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
deleted file mode 100644
index 1dc128e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_biquad_cascade_stereo_df2T_init_f32.c
- * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup BiquadCascadeDF2T
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- *
- * Coefficient and State Ordering:
- * \par
- * The coefficients are stored in the array pCoeffs in the following order:
- *
- * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
- *
- *
- * \par
- * where b1x and a1x are the coefficients for the first stage,
- * b2x and a2x are the coefficients for the second stage,
- * and so on. The pCoeffs array contains a total of 5*numStages values.
- *
- * \par
- * The pState is a pointer to state array.
- * Each Biquad stage has 2 state variables d1, and d2 for each channel.
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
- * The state array has a total length of 2*numStages values.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- */
-
-void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState)
-{
- /* Assign filter stages */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always 4 * numStages */
- memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-}
-
-/**
- * @} end of BiquadCascadeDF2T group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
deleted file mode 100644
index 4112ea3..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
+++ /dev/null
@@ -1,635 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_f32.c
- * Description: Convolution of floating-point sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup Conv Convolution
- *
- * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
- * Convolution is similar to correlation and is frequently used in filtering and data analysis.
- * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
- * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
- *
- * \par Algorithm
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
- * Then the convolution
- *
- *
- * c[n] = a[n] * b[n]
- *
- *
- * \par
- * is defined as
- * \image html ConvolutionEquation.gif
- * \par
- * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.
- * pSrcA points to the first input vector of length srcALen and
- * pSrcB points to the second input vector of length srcBLen.
- * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.
- *
- * \par
- * Conceptually, when two signals a[n] and b[n] are convolved,
- * the signal b[n] slides over a[n].
- * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
- *
- * \par
- * Note that convolution is a commutative operation:
- *
- *
- * a[n] * b[n] = b[n] * a[n].
- *
- *
- * \par
- * This means that switching the A and B arguments to the convolution functions has no effect.
- *
- * Fixed-Point Behavior
- *
- * \par
- * Convolution requires summing up a large number of intermediate products.
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
- * Refer to the function specific documentation below for further details of the particular algorithm used.
- *
- *
- * Fast Versions
- *
- * \par
- * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.
- *
- *
- * Opt Versions
- *
- * \par
- * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
-void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t *pIn1; /* inputA pointer */
- float32_t *pIn2; /* inputB pointer */
- float32_t *pOut = pDst; /* output pointer */
- float32_t *px; /* Intermediate inputA pointer */
- float32_t *py; /* Intermediate inputB pointer */
- float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
- float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counters */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum += *px++ * *py--;
-
- /* x[1] * y[srcBLen - 2] */
- sum += *px++ * *py--;
-
- /* x[2] * y[srcBLen - 3] */
- sum += *px++ * *py--;
-
- /* x[3] * y[srcBLen - 4] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 += x0 * c0;
-
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 += x1 * c0;
-
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 += x2 * c0;
-
- /* acc3 += x[3] * y[srcBLen - 1] */
- acc3 += x3 * c0;
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py--);
-
- /* Read x[4] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 += x1 * c0;
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 += x2 * c0;
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 += x3 * c0;
- /* acc3 += x[4] * y[srcBLen - 2] */
- acc3 += x0 * c0;
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 += x2 * c0;
- /* acc1 += x[3] * y[srcBLen - 2] */
- acc1 += x3 * c0;
- /* acc2 += x[4] * y[srcBLen - 2] */
- acc2 += x0 * c0;
- /* acc3 += x[5] * y[srcBLen - 2] */
- acc3 += x1 * c0;
-
- /* Read y[srcBLen - 4] sample */
- c0 = *(py--);
-
- /* Read x[6] sample */
- x2 = *(px + 3u);
- px += 4u;
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[srcBLen - 4] */
- acc0 += x3 * c0;
- /* acc1 += x[4] * y[srcBLen - 4] */
- acc1 += x0 * c0;
- /* acc2 += x[5] * y[srcBLen - 4] */
- acc2 += x1 * c0;
- /* acc3 += x[6] * y[srcBLen - 4] */
- acc3 += x2 * c0;
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += x0 * c0;
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += x1 * c0;
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += x2 * c0;
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 += x3 * c0;
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc0;
- *pOut++ = acc1;
- *pOut++ = acc2;
- *pOut++ = acc3;
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += *px++ * *py--;
- sum += *px++ * *py--;
- sum += *px++ * *py--;
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t *pIn1 = pSrcA; /* inputA pointer */
- float32_t *pIn2 = pSrcB; /* inputB pointer */
- float32_t sum; /* Accumulator */
- uint32_t i, j; /* loop counters */
-
- /* Loop to calculate convolution for output length number of times */
- for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
- {
- /* Initialize sum with zero to carry out MAC operations */
- sum = 0.0f;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += pIn1[j] * pIn2[i - j];
- }
- }
- /* Store the output in the destination buffer */
- pDst[i] = sum;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
deleted file mode 100644
index 0a213af..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_fast_opt_q15.c
- * Description: Fast Q15 Convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results
- * but provides only a single guard bit. There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
- *
- * \par
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
- */
-
-void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
- q31_t y1, y2; /* State variables */
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- uint32_t tapCnt; /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- q15_t a, b;
-
-#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
-
- /* Copy smaller length input sequence in reverse order into second scratch buffer */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Assuming scratch1 buffer is aligned by 32-bit */
- /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr1, srcALen);
-
- /* Update pointers */
- pScr1 += srcALen;
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- /* First part of the processing with loop unrolling process 4 data points at a time.
- ** a second loop below process for the remaining 1 to 3 samples. */
-
- /* Actual convolution process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x1, y1, acc0);
- acc2 = __SMLAD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLADX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = _SIMD32_OFFSET(pScr1);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x2, y2, acc0);
- acc2 = __SMLAD(x1, y2, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
- acc1 = __SMLADX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y2, acc3);
-
-#else
-
- /* Read four samples from smaller buffer */
- a = *pIn2;
- b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- y1 = __PKHBT(a, b, 16);
-#else
- y1 = __PKHBT(b, a, 16);
-#endif
-
- a = *(pIn2 + 2);
- b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
- y2 = __PKHBT(a, b, 16);
-#else
- y2 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLAD(x1, y1, acc0);
-
- acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- a = *pScr1;
- b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(a, b, 16);
-#else
- x1 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLAD(x2, y2, acc0);
-
- acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- acc1 = __SMLADX(x3, y2, acc1);
-
- a = *(pScr1 + 2);
- b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x2 = __PKHBT(a, b, 16);
-#else
- x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y2, acc3);
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* update scratch pointers */
- pIn2 += 4u;
- pScr1 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- acc0 += (*pScr1++ * *pIn2++);
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
deleted file mode 100644
index 2c5d253..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
+++ /dev/null
@@ -1,1398 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_fast_q15.c
- * Description: Fast Q15 Convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results
- * but provides only a single guard bit. There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
- *
- * \par
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
- */
-
-void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + (count - 1u);
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px+1);
- px+= 2u;
-
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLADX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px+1);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLADX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLADX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLADX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLADX(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px+2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px+3);
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLADX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
-
- /* Read y[srcBLen - 7] */
- c0 = *(py-1);
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px+2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
- *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
-
-#else
-
- *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
- *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = blockSize3 >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
- * with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
- * with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
- q15_t a, b;
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- py++;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + (count - 1u);
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1] samples */
- a = *px++;
- b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *px;
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *px;
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- a = *py;
- b = *(py+1);
- py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLADX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x2 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x3 = __PKHBT(b, a, 16);
-
-#else
-
- x2 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x3 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLADX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLADX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- a = *py;
- b = *(py+1);
- py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLADX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLADX(x3, c0, acc1);
-
- /* Read x[4], x[5], x[6] */
- a = *(px + 2);
- b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *(px + 4);
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *(px + 4);
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLADX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- a = *px;
- b = *(px+1);
- px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- a = *py;
- b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- a = *py;
- b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
-
- /* Read y[srcBLen - 7] */
- c0 = *(py-1);
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- a = *(px+2);
- b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = (q15_t)(acc0 >> 15);
- *pOut++ = (q15_t)(acc1 >> 15);
- *pOut++ = (q15_t)(acc2 >> 15);
- *pOut++ = (q15_t)(acc3 >> 15);
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = blockSize3 >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- py++;
-
- while (k > 0u)
- {
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
deleted file mode 100644
index 6c4920b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_fast_q31.c
- * Description: Fast Q31 Convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.
- * Finally, the accumulator is saturated and converted to a 1.31 result.
- *
- * \par
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signals must be scaled down.
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
- *
- * \par
- * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
- */
-
-void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst)
-{
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[1] * y[srcBLen - 2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[2] * y[srcBLen - 3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[3] * y[srcBLen - 4] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
- /* acc3 += x[3] * y[srcBLen - 1] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py--);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc3 += x[4] * y[srcBLen - 2] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc1 += x[3] * y[srcBLen - 3] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc2 += x[4] * y[srcBLen - 3] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc3 += x[5] * y[srcBLen - 3] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read y[srcBLen - 4] sample */
- c0 = *(py--);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[srcBLen - 4] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc1 += x[4] * y[srcBLen - 4] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc2 += x[5] * y[srcBLen - 4] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc3 += x[6] * y[srcBLen - 4] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = (q31_t) (acc0 << 1);
- *pOut++ = (q31_t) (acc1 << 1);
- *pOut++ = (q31_t) (acc2 << 1);
- *pOut++ = (q31_t) (acc3 << 1);
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
deleted file mode 100644
index 5036b5b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
+++ /dev/null
@@ -1,533 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_opt_q15.c
- * Description: Convolution of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * This approach provides 33 guard bits and there is no risk of overflow.
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
- *
- *
- * \par
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- *
- */
-
-void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
- q63_t acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
- q31_t y1, y2; /* State variables */
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- uint32_t tapCnt; /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- q15_t a, b;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- /* Copy smaller length input sequence in reverse order into second scratch buffer */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Assuming scratch1 buffer is aligned by 32-bit */
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr1, srcALen);
-
- /* Update pointers */
- pScr1 += srcALen;
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- /* First part of the processing with loop unrolling process 4 data points at a time.
- ** a second loop below process for the remaining 1 to 3 samples. */
-
- /* Actual convolution process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- /* multiply and accumlate */
- acc0 = __SMLALD(x1, y1, acc0);
- acc2 = __SMLALD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLALDX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = _SIMD32_OFFSET(pScr1);
-
- /* multiply and accumlate */
- acc0 = __SMLALD(x2, y2, acc0);
- acc2 = __SMLALD(x1, y2, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y1, acc3);
- acc1 = __SMLALDX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y2, acc3);
-
-#else
-
- /* Read four samples from smaller buffer */
- a = *pIn2;
- b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- y1 = __PKHBT(a, b, 16);
-#else
- y1 = __PKHBT(b, a, 16);
-#endif
-
- a = *(pIn2 + 2);
- b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
- y2 = __PKHBT(a, b, 16);
-#else
- y2 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLALD(x1, y1, acc0);
-
- acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLALDX(x3, y1, acc1);
-
- a = *pScr1;
- b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(a, b, 16);
-#else
- x1 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLALD(x2, y2, acc0);
-
- acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y1, acc3);
-
- acc1 = __SMLALDX(x3, y2, acc1);
-
- a = *(pScr1 + 2);
- b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x2 = __PKHBT(a, b, 16);
-#else
- x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- pIn2 += 4u;
- pScr1 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- acc0 += (*pScr1++ * *pIn2++);
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
-
-}
-
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
deleted file mode 100644
index 3d0d705..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
+++ /dev/null
@@ -1,423 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_opt_q7.c
- * Description: Convolution of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
- *
- */
-
-void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
- q15_t x4; /* Temporary input variable */
- q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
- uint32_t j, k, blkCnt, tapCnt; /* loop counter */
- q7_t *px; /* Temporary input1 pointer */
- q15_t *py; /* Temporary input2 pointer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x1, x2, x3, y1; /* Temporary input variables */
- q7_t *pOut = pDst; /* output pointer */
- q7_t out0, out1, out2, out3; /* temporary variables */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2;
-
- /* points to smaller length sequence */
- px = pIn2 + srcBLen - 1;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy (srcALen) samples in scratch buffer */
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* Initialization of pIn2 pointer */
- pIn2 = (q7_t *) py;
-
- pScr2 = py;
-
- /* Actual convolution process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x1, y1, acc0);
- acc2 = __SMLAD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLADX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
- acc0 = __SMLAD(x2, y1, acc0);
-
- acc2 = __SMLAD(x1, y1, acc2);
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- pScr2 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2);
- acc1 += (*pScr1++ * *pScr2);
- acc2 += (*pScr1++ * *pScr2);
- acc3 += (*pScr1++ * *pScr2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
- out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
- out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
- out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
- *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
- acc0 += (*pScr1++ * *pScr2++);
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 1u;
-
- }
-
-}
-
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
deleted file mode 100644
index efd6b1b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
+++ /dev/null
@@ -1,657 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_f32.c
- * Description: Partial convolution of floating-point sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup PartialConv Partial Convolution
- *
- * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
- * Each function has two additional arguments.
- * firstIndex specifies the starting index of the subset of output samples.
- * numPoints is the number of output samples to compute.
- * The function computes the output in the range
- * [firstIndex, ..., firstIndex+numPoints-1].
- * The output array pDst contains numPoints values.
- *
- * The allowable range of output indices is [0 srcALen+srcBLen-2].
- * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
- * Otherwise the functions return ARM_MATH_SUCCESS.
- * \note Refer arm_conv_f32() for details on fixed point behavior.
- *
- *
- * Fast Versions
- *
- * \par
- * Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.
- *
- *
- * Opt Versions
- *
- * \par
- * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
-arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t *pIn1 = pSrcA; /* inputA pointer */
- float32_t *pIn2 = pSrcB; /* inputB pointer */
- float32_t *pOut = pDst; /* output pointer */
- float32_t *px; /* Intermediate inputA pointer */
- float32_t *py; /* Intermediate inputB pointer */
- float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
- float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t j, k, count = 0u, blkCnt, check;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = ((int32_t) check - blockSize3) -
- (blockSize1 + (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + firstIndex;
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum += *px++ * *py--;
-
- /* x[1] * y[srcBLen - 2] */
- sum += *px++ * *py--;
-
- /* x[2] * y[srcBLen - 3] */
- sum += *px++ * *py--;
-
- /* x[3] * y[srcBLen - 4] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc1;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = ((uint32_t) blockSize2 >> 2u);
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 += x0 * c0;
-
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 += x1 * c0;
-
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 += x2 * c0;
-
- /* acc3 += x[3] * y[srcBLen - 1] */
- acc3 += x3 * c0;
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py--);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 += x1 * c0;
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 += x2 * c0;
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 += x3 * c0;
- /* acc3 += x[4] * y[srcBLen - 2] */
- acc3 += x0 * c0;
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 += x2 * c0;
- /* acc1 += x[3] * y[srcBLen - 2] */
- acc1 += x3 * c0;
- /* acc2 += x[4] * y[srcBLen - 2] */
- acc2 += x0 * c0;
- /* acc3 += x[5] * y[srcBLen - 2] */
- acc3 += x1 * c0;
-
- /* Read y[srcBLen - 4] sample */
- c0 = *(py--);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[srcBLen - 4] */
- acc0 += x3 * c0;
- /* acc1 += x[4] * y[srcBLen - 4] */
- acc1 += x0 * c0;
- /* acc2 += x[5] * y[srcBLen - 4] */
- acc2 += x1 * c0;
- /* acc3 += x[6] * y[srcBLen - 4] */
- acc3 += x2 * c0;
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += x0 * c0;
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += x1 * c0;
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += x2 * c0;
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 += x3 * c0;
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = acc0;
- *pOut++ = acc1;
- *pOut++ = acc2;
- *pOut++ = acc3;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += *px++ * *py--;
- sum += *px++ * *py--;
- sum += *px++ * *py--;
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- sum += *px++ * *py--;
-
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum += *px++ * *py--;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t *pIn1 = pSrcA; /* inputA pointer */
- float32_t *pIn2 = pSrcB; /* inputB pointer */
- float32_t sum; /* Accumulator */
- uint32_t i, j; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
- /* Loop to calculate convolution for output length number of values */
- for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0.0f;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations for inputs */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += pIn1[j] * pIn2[i - j];
- }
- }
- /* Store the output in the destination buffer */
- pDst[i] = sum;
- }
- /* set status as ARM_SUCCESS as there are no argument errors */
- status = ARM_MATH_SUCCESS;
- }
- return (status);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
deleted file mode 100644
index c6e4029..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+++ /dev/null
@@ -1,756 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_fast_opt_q15.c
- * Description: Fast Q15 Partial convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q31_t acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
- q31_t y1, y2; /* State variables */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- arm_status status;
-
- uint32_t tapCnt; /* loop count */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
-
- /* Copy smaller length input sequence in reverse order into second scratch buffer */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Assuming scratch1 buffer is aligned by 32-bit */
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr1, srcALen);
-
- /* Update pointers */
- pScr1 += srcALen;
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- pScratch1 += firstIndex;
-
- pOut = pDst + firstIndex;
-
- /* First part of the processing with loop unrolling process 4 data points at a time.
- ** a second loop below process for the remaining 1 to 3 samples. */
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x1, y1, acc0);
- acc2 = __SMLAD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLADX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = _SIMD32_OFFSET(pScr1);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x2, y2, acc0);
-
- acc2 = __SMLAD(x1, y2, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
- acc1 = __SMLADX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y2, acc3);
-
- /* update scratch pointers */
- pIn2 += 4u;
- pScr1 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = numPoints & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read two samples from smaller buffer */
- y1 = *__SIMD32(pIn2)++;
-
- acc0 = __SMLAD(x1, y1, acc0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
- /* Return to application */
- return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q31_t acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- arm_status status; /* Status variable */
- uint32_t tapCnt; /* loop count */
- q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
- q15_t y10, y11; /* Temporary variables to hold srcB buffer */
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- pScratch1 += firstIndex;
-
- pOut = pDst + firstIndex;
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *pScr1++;
- x21 = *pScr1++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read two samples from smaller buffer */
- y10 = *pIn2;
- y11 = *(pIn2 + 1u);
-
- /* multiply and accumlate */
- acc0 += (q31_t) x10 *y10;
- acc0 += (q31_t) x11 *y11;
- acc2 += (q31_t) x20 *y10;
- acc2 += (q31_t) x21 *y11;
-
- /* multiply and accumlate */
- acc1 += (q31_t) x11 *y10;
- acc1 += (q31_t) x20 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1;
- x11 = *(pScr1 + 1u);
-
- /* multiply and accumlate */
- acc3 += (q31_t) x21 *y10;
- acc3 += (q31_t) x10 *y11;
-
- /* Read next two samples from scratch2 buffer */
- y10 = *(pIn2 + 2u);
- y11 = *(pIn2 + 3u);
-
- /* multiply and accumlate */
- acc0 += (q31_t) x20 *y10;
- acc0 += (q31_t) x21 *y11;
- acc2 += (q31_t) x10 *y10;
- acc2 += (q31_t) x11 *y11;
- acc1 += (q31_t) x21 *y10;
- acc1 += (q31_t) x10 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *(pScr1 + 2);
- x21 = *(pScr1 + 3);
-
- /* multiply and accumlate */
- acc3 += (q31_t) x11 *y10;
- acc3 += (q31_t) x20 *y11;
-
- /* update scratch pointers */
- pIn2 += 4u;
- pScr1 += 4u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = __SSAT((acc0 >> 15), 16);
- *pOut++ = __SSAT((acc1 >> 15), 16);
- *pOut++ = __SSAT((acc2 >> 15), 16);
- *pOut++ = __SSAT((acc3 >> 15), 16);
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = numPoints & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read two samples from smaller buffer */
- y10 = *pIn2++;
- y11 = *pIn2++;
-
- /* multiply and accumlate */
- acc0 += (q31_t) x10 *y10;
- acc0 += (q31_t) x11 *y11;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- }
-
- /* Return to application */
- return (status);
-}
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
deleted file mode 100644
index 8f201b1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
+++ /dev/null
@@ -1,1480 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_fast_q15.c
- * Description: Fast Q15 Partial convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
- */
-
-
-arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0;
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >=srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
- (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2 - 1u;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = ((uint32_t) blockSize2 >> 2u);
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px+1);
- px+= 2u;
-
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLADX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px+1);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLADX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLADX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLADX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLADX(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px+2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px+3);
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLADX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
-
- c0 = *(py-1);
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px+2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
- *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
-
-#else
-
- *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
- *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = count >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
- * with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
- * with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum = __SMLAD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#else
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0;
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
- arm_status status; /* status of Partial convolution */
- q15_t a, b;
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >=srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = ((int32_t) check - blockSize3) -
- (blockSize1 + (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- py++;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2 - 1u;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = ((uint32_t) blockSize2 >> 2u);
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1] samples */
- a = *px++;
- b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *px;
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *px;
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- a = *py;
- b = *(py+1);
- py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLADX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x2 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x3 = __PKHBT(b, a, 16);
-
-#else
-
- x2 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x3 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLADX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLADX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- a = *py;
- b = *(py+1);
- py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLADX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLADX(x3, c0, acc1);
-
- /* Read x[4], x[5], x[6] */
- a = *(px + 2);
- b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *(px + 4);
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *(px + 4);
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLADX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- a = *px;
- b = *(px+1);
- px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- a = *py;
- b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- a = *py;
- b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x0, c0, acc0);
- acc1 = __SMLADX(x1, c0, acc1);
- acc2 = __SMLADX(x3, c0, acc2);
- acc3 = __SMLADX(x2, c0, acc3);
-
- /* Read y[srcBLen - 7] */
- c0 = *(py-1);
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- a = *(px+2);
- b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = (q15_t)(acc0 >> 15);
- *pOut++ = (q15_t)(acc1 >> 15);
- *pOut++ = (q15_t)(acc2 >> 15);
- *pOut++ = (q15_t)(acc3 >> 15);
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = count >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- py++;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- sum += ((q31_t) * px++ * *py--);
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (sum >> 15);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
deleted file mode 100644
index 9a4cfeb..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_fast_q31.c
- * Description: Fast Q31 Partial convolution
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * \par
- * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
- */
-
-arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q31_t x0, x1, x2, x3, c0;
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
- (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first loop starts here */
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[1] * y[srcBLen - 2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[2] * y[srcBLen - 3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* x[3] * y[srcBLen - 4] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2 */
- blkCnt = ((uint32_t) blockSize2 >> 2u);
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
- /* acc3 += x[3] * y[srcBLen - 1] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py--);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc3 += x[4] * y[srcBLen - 2] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc1 += x[3] * y[srcBLen - 2] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc2 += x[4] * y[srcBLen - 2] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc3 += x[5] * y[srcBLen - 2] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read y[srcBLen - 4] sample */
- c0 = *(py--);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[srcBLen - 4] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc1 += x[4] * y[srcBLen - 4] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc2 += x[5] * y[srcBLen - 4] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc3 += x[6] * y[srcBLen - 4] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (acc0 << 1);
- *pOut++ = (q31_t) (acc1 << 1);
- *pOut++ = (q31_t) (acc2 << 1);
- *pOut++ = (q31_t) (acc3 << 1);
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py--))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = sum << 1;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
deleted file mode 100644
index bb88ad0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
+++ /dev/null
@@ -1,753 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_opt_q15.c
- * Description: Partial convolution of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, state buffers should be aligned by 32-bit
- *
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- *
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q63_t acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
- q31_t y1, y2; /* State variables */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- arm_status status; /* Status variable */
- uint32_t tapCnt; /* loop count */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr1, srcALen);
-
- /* Update pointers */
- pScr1 += srcALen;
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- pScratch1 += firstIndex;
-
- pOut = pDst + firstIndex;
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- /* multiply and accumlate */
- acc0 = __SMLALD(x1, y1, acc0);
- acc2 = __SMLALD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLALDX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = _SIMD32_OFFSET(pScr1);
-
- /* multiply and accumlate */
- acc0 = __SMLALD(x2, y2, acc0);
- acc2 = __SMLALD(x1, y2, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y1, acc3);
- acc1 = __SMLALDX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y2, acc3);
-
- /* update scratch pointers */
- pIn2 += 4u;
- pScr1 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = numPoints & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read two samples from smaller buffer */
- y1 = *__SIMD32(pIn2)++;
-
- acc0 = __SMLALD(x1, y1, acc0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- }
-
- /* Return to application */
- return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
- q63_t acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- uint32_t j, k, blkCnt; /* loop counter */
- arm_status status; /* Status variable */
- uint32_t tapCnt; /* loop count */
- q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
- q15_t y10, y11; /* Temporary variables to hold srcB buffer */
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2 + srcBLen - 1;
-
- /* points to smaller length sequence */
- px = pIn2;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr2-- = *px++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = *pIn1++;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Initialization of pIn2 pointer */
- pIn2 = py;
-
- pScratch1 += firstIndex;
-
- pOut = pDst + firstIndex;
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *pScr1++;
- x21 = *pScr1++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read two samples from smaller buffer */
- y10 = *pIn2;
- y11 = *(pIn2 + 1u);
-
- /* multiply and accumlate */
- acc0 += (q63_t) x10 *y10;
- acc0 += (q63_t) x11 *y11;
- acc2 += (q63_t) x20 *y10;
- acc2 += (q63_t) x21 *y11;
-
- /* multiply and accumlate */
- acc1 += (q63_t) x11 *y10;
- acc1 += (q63_t) x20 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1;
- x11 = *(pScr1 + 1u);
-
- /* multiply and accumlate */
- acc3 += (q63_t) x21 *y10;
- acc3 += (q63_t) x10 *y11;
-
- /* Read next two samples from scratch2 buffer */
- y10 = *(pIn2 + 2u);
- y11 = *(pIn2 + 3u);
-
- /* multiply and accumlate */
- acc0 += (q63_t) x20 *y10;
- acc0 += (q63_t) x21 *y11;
- acc2 += (q63_t) x10 *y10;
- acc2 += (q63_t) x11 *y11;
- acc1 += (q63_t) x21 *y10;
- acc1 += (q63_t) x10 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *(pScr1 + 2);
- x21 = *(pScr1 + 3);
-
- /* multiply and accumlate */
- acc3 += (q63_t) x11 *y10;
- acc3 += (q63_t) x20 *y11;
-
- /* update scratch pointers */
- pIn2 += 4u;
- pScr1 += 4u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2);
- acc1 += (*pScr1++ * *pIn2);
- acc2 += (*pScr1++ * *pIn2);
- acc3 += (*pScr1++ * *pIn2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = __SSAT((acc0 >> 15), 16);
- *pOut++ = __SSAT((acc1 >> 15), 16);
- *pOut++ = __SSAT((acc2 >> 15), 16);
- *pOut++ = __SSAT((acc3 >> 15), 16);
-
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = numPoints & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read two samples from smaller buffer */
- y10 = *pIn2++;
- y11 = *pIn2++;
-
- /* multiply and accumlate */
- acc0 += (q63_t) x10 *y10;
- acc0 += (q63_t) x11 *y11;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch1 += 1u;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- }
-
- /* Return to application */
- return (status);
-}
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
deleted file mode 100644
index 3505b2f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
+++ /dev/null
@@ -1,791 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_opt_q7.c
- * Description: Partial convolution of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- *
- *
- */
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
- q15_t x4; /* Temporary input variable */
- q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
- uint32_t j, k, blkCnt, tapCnt; /* loop counter */
- q7_t *px; /* Temporary input1 pointer */
- q15_t *py; /* Temporary input2 pointer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t x1, x2, x3, y1; /* Temporary input variables */
- arm_status status;
- q7_t *pOut = pDst; /* output pointer */
- q7_t out0, out1, out2, out3; /* temporary variables */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2;
-
- /* points to smaller length sequence */
- px = pIn2 + srcBLen - 1;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy (srcALen) samples in scratch buffer */
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* Initialization of pIn2 pointer */
- pIn2 = (q7_t *) py;
-
- pScr2 = py;
-
- pOut = pDst + firstIndex;
-
- pScratch1 += firstIndex;
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x1, y1, acc0);
- acc2 = __SMLAD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLADX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
- acc0 = __SMLAD(x2, y1, acc0);
-
- acc2 = __SMLAD(x1, y1, acc2);
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- pScr2 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2);
- acc1 += (*pScr1++ * *pScr2);
- acc2 += (*pScr1++ * *pScr2);
- acc3 += (*pScr1++ * *pScr2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
- out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
- out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
- out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
- *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 4u;
-
- }
-
- blkCnt = (numPoints) & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read two samples from smaller buffer */
- y1 = *__SIMD32(pScr2)++;
-
- acc0 = __SMLAD(x1, y1, acc0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 1u;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
-
- }
-
- return (status);
-
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
-
- q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
- q15_t x4; /* Temporary input variable */
- q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
- uint32_t j, k, blkCnt, tapCnt; /* loop counter */
- q7_t *px; /* Temporary input1 pointer */
- q15_t *py; /* Temporary input2 pointer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulator */
- arm_status status;
- q7_t *pOut = pDst; /* output pointer */
- q15_t x10, x11, x20, x21; /* Temporary input variables */
- q15_t y10, y11; /* Temporary input variables */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* pointer to take end of scratch2 buffer */
- pScr2 = pScratch2;
-
- /* points to smaller length sequence */
- px = pIn2 + srcBLen - 1;
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * px--;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Initialze temporary scratch pointer */
- pScr1 = pScratch1;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy (srcALen) samples in scratch buffer */
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Temporary pointer for scratch2 */
- py = pScratch2;
-
- /* Initialization of pIn2 pointer */
- pIn2 = (q7_t *) py;
-
- pScr2 = py;
-
- pOut = pDst + firstIndex;
-
- pScratch1 += firstIndex;
-
- /* Actual convolution process starts here */
- blkCnt = (numPoints) >> 2;
-
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *pScr1++;
- x21 = *pScr1++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y10 = *pScr2;
- y11 = *(pScr2 + 1u);
-
- /* multiply and accumlate */
- acc0 += (q31_t) x10 *y10;
- acc0 += (q31_t) x11 *y11;
- acc2 += (q31_t) x20 *y10;
- acc2 += (q31_t) x21 *y11;
-
-
- acc1 += (q31_t) x11 *y10;
- acc1 += (q31_t) x20 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1;
- x11 = *(pScr1 + 1u);
-
- /* multiply and accumlate */
- acc3 += (q31_t) x21 *y10;
- acc3 += (q31_t) x10 *y11;
-
- /* Read next two samples from scratch2 buffer */
- y10 = *(pScr2 + 2u);
- y11 = *(pScr2 + 3u);
-
- /* multiply and accumlate */
- acc0 += (q31_t) x20 *y10;
- acc0 += (q31_t) x21 *y11;
- acc2 += (q31_t) x10 *y10;
- acc2 += (q31_t) x11 *y11;
- acc1 += (q31_t) x21 *y10;
- acc1 += (q31_t) x10 *y11;
-
- /* Read next two samples from scratch1 buffer */
- x20 = *(pScr1 + 2);
- x21 = *(pScr1 + 3);
-
- /* multiply and accumlate */
- acc3 += (q31_t) x11 *y10;
- acc3 += (q31_t) x20 *y11;
-
- /* update scratch pointers */
-
- pScr1 += 4u;
- pScr2 += 4u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2);
- acc1 += (*pScr1++ * *pScr2);
- acc2 += (*pScr1++ * *pScr2);
- acc3 += (*pScr1++ * *pScr2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 4u;
-
- }
-
- blkCnt = (numPoints) & 0x3;
-
- /* Calculate convolution for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- /* Read next two samples from scratch1 buffer */
- x10 = *pScr1++;
- x11 = *pScr1++;
-
- /* Read two samples from smaller buffer */
- y10 = *pScr2++;
- y11 = *pScr2++;
-
- /* multiply and accumlate */
- acc0 += (q31_t) x10 *y10;
- acc0 += (q31_t) x11 *y11;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 1u;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- }
-
- return (status);
-
-}
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
deleted file mode 100644
index 4f39fe8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_q15.c
- * Description: Partial convolution of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- * \par
- * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
- *
- */
-
-arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
-
-
-#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
- (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2 - 1u;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px+1);
- px+= 2u;
-
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLALDX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLALDX(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px+1);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLALDX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLALDX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLALDX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLALDX(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px+2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px+3);
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLALDX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLALDX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALDX(x1, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x0, c0, acc0);
- acc1 = __SMLALDX(x1, c0, acc1);
- acc2 = __SMLALDX(x3, c0, acc2);
- acc3 = __SMLALDX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x0, c0, acc0);
- acc1 = __SMLALDX(x1, c0, acc1);
- acc2 = __SMLALDX(x3, c0, acc2);
- acc3 = __SMLALDX(x2, c0, acc3);
-
- c0 = *(py-1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px+2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x1, c0, acc0);
- acc1 = __SMLALD(x2, c0, acc1);
- acc2 = __SMLALDX(x2, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = count >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
- * with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
- * with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t *pIn1 = pSrcA; /* inputA pointer */
- q15_t *pIn2 = pSrcB; /* inputB pointer */
- q63_t sum; /* Accumulator */
- uint32_t i, j; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
- /* Loop to calculate convolution for output length number of values */
- for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
- }
- /* set status as ARM_SUCCESS as there are no argument errors */
- status = ARM_MATH_SUCCESS;
- }
- return (status);
-
-#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
-
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
deleted file mode 100644
index 161ab2d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_q31.c
- * Description: Partial convolution of Q31 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- */
-
-arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q63_t sum, acc0, acc1, acc2; /* Accumulator */
- q31_t x0, x1, x2, c0;
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
- arm_status status; /* status of Partial convolution */
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
- (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first loop starts here */
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum += (q63_t) * px++ * (*py--);
- /* x[1] * y[srcBLen - 2] */
- sum += (q63_t) * px++ * (*py--);
- /* x[2] * y[srcBLen - 3] */
- sum += (q63_t) * px++ * (*py--);
- /* x[3] * y[srcBLen - 4] */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blkCnt */
-
- blkCnt = blockSize2 / 3;
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
-
- /* read x[0], x[1] samples */
- x0 = *(px++);
- x1 = *(px++);
-
- /* Apply loop unrolling and compute 3 MACs simultaneously. */
- k = srcBLen / 3;
-
- /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 2 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py);
-
- /* Read x[2] sample */
- x2 = *(px);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 += (q63_t) x0 *c0;
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 += (q63_t) x1 *c0;
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 += (q63_t) x2 *c0;
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py - 1u);
-
- /* Read x[3] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 += (q63_t) x1 *c0;
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 += (q63_t) x2 *c0;
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 += (q63_t) x0 *c0;
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py - 2u);
-
- /* Read x[4] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 += (q63_t) x2 *c0;
- /* acc1 += x[3] * y[srcBLen - 2] */
- acc1 += (q63_t) x0 *c0;
- /* acc2 += x[4] * y[srcBLen - 2] */
- acc2 += (q63_t) x1 *c0;
-
-
- px += 3u;
-
- py -= 3u;
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen - (3 * (srcBLen / 3));
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += (q63_t) x0 *c0;
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += (q63_t) x1 *c0;
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += (q63_t) x2 *c0;
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (acc0 >> 31);
- *pOut++ = (q31_t) (acc1 >> 31);
- *pOut++ = (q31_t) (acc2 >> 31);
-
- /* Increment the pointer pIn1 index, count by 3 */
- count += 3u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t *pIn1 = pSrcA; /* inputA pointer */
- q31_t *pIn2 = pSrcB; /* inputB pointer */
- q63_t sum; /* Accumulator */
- uint32_t i, j; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
- /* Loop to calculate convolution for output length number of values */
- for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q31_t) (sum >> 31u);
- }
- /* set status as ARM_SUCCESS as there are no argument errors */
- status = ARM_MATH_SUCCESS;
- }
- return (status);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
deleted file mode 100644
index b418688..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_partial_q7.c
- * Description: Partial convolution of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup PartialConv
- * @{
- */
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- *
- * \par
- * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
- *
- */
-
-arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t *pIn1; /* inputA pointer */
- q7_t *pIn2; /* inputB pointer */
- q7_t *pOut = pDst; /* output pointer */
- q7_t *px; /* Intermediate inputA pointer */
- q7_t *py; /* Intermediate inputB pointer */
- q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t input1, input2;
- q15_t in1, in2;
- q7_t x0, x1, x2, x3, c0, c1;
- uint32_t j, k, count, check, blkCnt;
- int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
- arm_status status;
-
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_MATH_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* Conditions to check which loopCounter holds
- * the first and last indices of the output samples to be calculated. */
- check = firstIndex + numPoints;
- blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
- blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
- blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
- blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
- (int32_t) numPoints) : 0;
- blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
- (int32_t) firstIndex);
- blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* Set the output pointer to point to the firstIndex
- * of the output sample to be calculated. */
- pOut = pDst + firstIndex;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed.
- Since the partial convolution starts from from firstIndex
- Number of Macs to be performed is firstIndex + 1 */
- count = 1u + firstIndex;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + firstIndex;
- py = pSrc2;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] , x[1] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 1] , y[srcBLen - 2] */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* x[0] * y[srcBLen - 1] */
- /* x[1] * y[srcBLen - 2] */
- sum = __SMLAD(input1, input2, sum);
-
- /* x[2] , x[3] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 3] , y[srcBLen - 4] */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* x[2] * y[srcBLen - 3] */
- /* x[3] * y[srcBLen - 4] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = ++pSrc2;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
- {
- px = pIn1 + firstIndex - srcBLen + 1;
- }
- else
- {
- px = pIn1;
- }
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = ((uint32_t) blockSize2 >> 2u);
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
- /* Read y[srcBLen - 2] sample */
- c1 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* x[0] and x[1] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[1] and x[2] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
- /* Read y[srcBLen - 4] sample */
- c1 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[4] and x[5] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* x[5] and x[6] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += ((q31_t) x0 * c0);
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += ((q31_t) x1 * c0);
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += ((q31_t) x2 * c0);
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 += ((q31_t) x3 * c0);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
- *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
- *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
- *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
-
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = (uint32_t) blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum += ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q7_t *pIn1 = pSrcA; /* inputA pointer */
- q7_t *pIn2 = pSrcB; /* inputB pointer */
- q31_t sum; /* Accumulator */
- uint32_t i, j; /* loop counters */
- arm_status status; /* status of Partial convolution */
-
- /* Check for range of output samples to be calculated */
- if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
- {
- /* Set status as ARM_ARGUMENT_ERROR */
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
- /* Loop to calculate convolution for output length number of values */
- for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
- }
- /* set status as ARM_SUCCESS as there are no argument errors */
- status = ARM_MATH_SUCCESS;
- }
- return (status);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of PartialConv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
deleted file mode 100644
index a95c29d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
+++ /dev/null
@@ -1,722 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_q15.c
- * Description: Convolution of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * This approach provides 33 guard bits and there is no risk of overflow.
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
- *
- * \par
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- * \par
- * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
- *
- */
-
-void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations less than 4 */
- /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
- /* The first part of the stage starts here */
- while ((count < 4u) && (blockSize1 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over number of MAC operations between
- * inputA samples and inputB samples */
- k = count;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* The second part of the stage starts here */
- /* The internal loop, over count, is unrolled by 4 */
- /* To, read the last two inputB samples using SIMD:
- * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
- py = py - 1;
-
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + (count - 1u);
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is the index by which the pointer pIn1 to be incremented */
- count = 0u;
-
-
- /* --------------------
- * Stage2 process
- * -------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- py = py - 1u;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px+1);
- px+= 2u;
-
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the last two inputB samples using SIMD:
- * y[srcBLen - 1] and y[srcBLen - 2] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLALDX(x0, c0, acc0);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLALDX(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px+1);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLALDX(x2, c0, acc2);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLALDX(x3, c0, acc3);
-
- /* Read y[srcBLen - 3] and y[srcBLen - 4] */
- c0 = *__SIMD32(py)--;
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLALDX(x2, c0, acc0);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLALDX(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px+2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px+3);
- px += 4u;
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLALDX(x0, c0, acc2);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLALDX(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[srcBLen - 5] */
- c0 = *(py+1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALDX(x1, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x0, c0, acc0);
- acc1 = __SMLALDX(x1, c0, acc1);
- acc2 = __SMLALDX(x3, c0, acc2);
- acc3 = __SMLALDX(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[srcBLen - 5], y[srcBLen - 6] */
- c0 = _SIMD32_OFFSET(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px+1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x0, c0, acc0);
- acc1 = __SMLALDX(x1, c0, acc1);
- acc2 = __SMLALDX(x3, c0, acc2);
- acc3 = __SMLALDX(x2, c0, acc3);
-
- c0 = *(py-1);
-
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px+2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x1, c0, acc0);
- acc1 = __SMLALD(x2, c0, acc1);
- acc2 = __SMLALDX(x2, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
-
- /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
- *__SIMD32(pOut)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) ((q31_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- blockSize3 = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- pIn2 = pSrc2 - 1u;
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- /* For loop unrolling by 4, this stage is divided into two. */
- /* First part of this stage computes the MAC operations greater than 4 */
- /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
- /* The first part of the stage starts here */
- j = blockSize3 >> 2u;
-
- while ((j > 0u) && (blockSize3 > 0u))
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
- * with y[srcBLen - 1], y[srcBLen - 2] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
- /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
- * with y[srcBLen - 3], y[srcBLen - 4] respectively */
- sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* For the next MAC operations, the pointer py is used without SIMD
- * So, py is incremented by 1 */
- py = py + 1u;
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the loop counter */
- blockSize3--;
-
- j--;
- }
-
- /* The second part of the stage starts here */
- /* SIMD is not used for the next MAC operations,
- * so pointer py is updated to read only one sample at a time */
- py = py + 1u;
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen-1] * y[srcBLen-1] */
- sum = __SMLALD(*px++, *py--, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- q15_t *pIn1 = pSrcA; /* input pointer */
- q15_t *pIn2 = pSrcB; /* coefficient pointer */
- q63_t sum; /* Accumulator */
- uint32_t i, j; /* loop counter */
-
- /* Loop to calculate output of convolution for output length number of times */
- for (i = 0; i < (srcALen + srcBLen - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += (q31_t) pIn1[j] * (pIn2[i - j]);
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
- }
-
-#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
deleted file mode 100644
index e902d9b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_q31.c
- * Description: Convolution of Q31 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
- *
- * \par
- * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- */
-
-void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q63_t sum; /* Accumulator */
- q63_t acc0, acc1, acc2; /* Accumulator */
- q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (q31_t *) pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = (q31_t *) pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 1] */
- sum += (q63_t) * px++ * (*py--);
- /* x[1] * y[srcBLen - 2] */
- sum += (q63_t) * px++ * (*py--);
- /* x[2] * y[srcBLen - 3] */
- sum += (q63_t) * px++ * (*py--);
- /* x[3] * y[srcBLen - 4] */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll by 3 */
- blkCnt = blockSize2 / 3;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
-
- /* Apply loop unrolling and compute 3 MACs simultaneously. */
- k = srcBLen / 3;
-
- /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 2 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py);
-
- /* Read x[3] sample */
- x2 = *(px);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[0] * y[srcBLen - 1] */
- acc0 += ((q63_t) x0 * c0);
- /* acc1 += x[1] * y[srcBLen - 1] */
- acc1 += ((q63_t) x1 * c0);
- /* acc2 += x[2] * y[srcBLen - 1] */
- acc2 += ((q63_t) x2 * c0);
-
- /* Read y[srcBLen - 2] sample */
- c0 = *(py - 1u);
-
- /* Read x[4] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[srcBLen - 2] */
- acc0 += ((q63_t) x1 * c0);
- /* acc1 += x[2] * y[srcBLen - 2] */
- acc1 += ((q63_t) x2 * c0);
- /* acc2 += x[3] * y[srcBLen - 2] */
- acc2 += ((q63_t) x0 * c0);
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py - 2u);
-
- /* Read x[5] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[srcBLen - 3] */
- acc0 += ((q63_t) x2 * c0);
- /* acc1 += x[3] * y[srcBLen - 2] */
- acc1 += ((q63_t) x0 * c0);
- /* acc2 += x[4] * y[srcBLen - 2] */
- acc2 += ((q63_t) x1 * c0);
-
- /* update scratch pointers */
- px += 3u;
- py -= 3u;
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen - (3 * (srcBLen / 3));
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += ((q63_t) x0 * c0);
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += ((q63_t) x1 * c0);
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += ((q63_t) x2 * c0);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut++ = (q31_t) (acc0 >> 31);
- *pOut++ = (q31_t) (acc1 >> 31);
- *pOut++ = (q31_t) (acc2 >> 31);
-
- /* Increment the pointer pIn1 index, count by 3 */
- count += 3u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- sum += (q63_t) * px++ * (*py--);
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum += (q63_t) * px++ * (*py--);
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- sum += (q63_t) * px++ * (*py--);
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q31_t) (sum >> 31);
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t *pIn1 = pSrcA; /* input pointer */
- q31_t *pIn2 = pSrcB; /* coefficient pointer */
- q63_t sum; /* Accumulator */
- uint32_t i, j; /* loop counter */
-
- /* Loop to calculate output of convolution for output length number of times */
- for (i = 0; i < (srcALen + srcBLen - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q31_t) (sum >> 31u);
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
deleted file mode 100644
index 8e7805e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
+++ /dev/null
@@ -1,678 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_conv_q7.c
- * Description: Convolution of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Conv
- * @{
- */
-
-/**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
- *
- * \par
- * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
- *
- */
-
-void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t *pIn1; /* inputA pointer */
- q7_t *pIn2; /* inputB pointer */
- q7_t *pOut = pDst; /* output pointer */
- q7_t *px; /* Intermediate inputA pointer */
- q7_t *py; /* Intermediate inputB pointer */
- q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
- q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
- q31_t input1, input2; /* Temporary input variables */
- q15_t in1, in2; /* Temporary input variables */
- uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
- }
-
- /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
- /* The function is internally
- * divided into three stages according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first stage of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second stage of the algorithm, srcBLen number of multiplications are done.
- * In the third stage of the algorithm, the multiplications decrease by one
- * for every iteration. */
-
- /* The algorithm is implemented in three stages.
- The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = (srcALen - srcBLen) + 1u;
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[0]
- * sum = x[0] * y[1] + x[1] * y[0]
- * ....
- * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] , x[1] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* y[srcBLen - 1] , y[srcBLen - 2] */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* x[0] * y[srcBLen - 1] */
- /* x[1] * y[srcBLen - 2] */
- sum = __SMLAD(input1, input2, sum);
-
- /* x[2] , x[3] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* y[srcBLen - 3] , y[srcBLen - 4] */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* x[2] * y[srcBLen - 3] */
- /* x[3] * y[srcBLen - 4] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q15_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pIn2 + count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
- * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[srcBLen - 1] sample */
- c0 = *(py--);
- /* Read y[srcBLen - 2] sample */
- c1 = *(py--);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* x[0] and x[1] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[1] and x[2] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- /* Read y[srcBLen - 3] sample */
- c0 = *(py--);
- /* Read y[srcBLen - 4] sample */
- c1 = *(py--);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[4] and x[5] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* x[5] and x[6] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[srcBLen - 5] sample */
- c0 = *(py--);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[srcBLen - 5] */
- acc0 += ((q15_t) x0 * c0);
- /* acc1 += x[5] * y[srcBLen - 5] */
- acc1 += ((q15_t) x1 * c0);
- /* acc2 += x[6] * y[srcBLen - 5] */
- acc2 += ((q15_t) x2 * c0);
- /* acc3 += x[7] * y[srcBLen - 5] */
- acc3 += ((q15_t) x3 * c0);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
- *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
-
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q15_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* srcBLen number of MACS should be performed */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q15_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
- * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
- * ....
- * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
- * sum += x[srcALen-1] * y[srcBLen-1]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The blockSize3 variable holds the number of MAC operations performed */
-
- /* Working pointer of inputA */
- pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
- px = pSrc1;
-
- /* Working pointer of inputB */
- pSrc2 = pIn2 + (srcBLen - 1u);
- py = pSrc2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = blockSize3 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
- /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
- in1 = (q15_t) * py--;
- in2 = (q15_t) * py--;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
- /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
- /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = blockSize3 % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q15_t) * px++ * *py--);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pSrc2;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q7_t *pIn1 = pSrcA; /* input pointer */
- q7_t *pIn2 = pSrcB; /* coefficient pointer */
- q31_t sum; /* Accumulator */
- uint32_t i, j; /* loop counter */
-
- /* Loop to calculate output of convolution for output length number of times */
- for (i = 0; i < (srcALen + srcBLen - 1); i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0; j <= i; j++)
- {
- /* Check the array limitations */
- if (((i - j) < srcBLen) && (j < srcALen))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += (q15_t) pIn1[j] * (pIn2[i - j]);
- }
- }
-
- /* Store the output in the destination buffer */
- pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Conv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
deleted file mode 100644
index 32099d1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
+++ /dev/null
@@ -1,727 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_f32.c
- * Description: Correlation of floating-point sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup Corr Correlation
- *
- * Correlation is a mathematical operation that is similar to convolution.
- * As with convolution, correlation uses two signals to produce a third signal.
- * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
- * Correlation is commonly used to measure the similarity between two signals.
- * It has applications in pattern recognition, cryptanalysis, and searching.
- * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
- * Fast versions of the Q15 and Q31 functions are also provided.
- *
- * \par Algorithm
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
- * The convolution of the two signals is denoted by
- *
- * c[n] = a[n] * b[n]
- *
- * In correlation, one of the signals is flipped in time
- *
- * c[n] = a[n] * b[-n]
- *
- *
- * \par
- * and this is mathematically defined as
- * \image html CorrelateEquation.gif
- * \par
- * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.
- * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).
- * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.
- *
- * Note
- * \par
- * The pDst should be initialized to all zeros before being used.
- *
- * Fixed-Point Behavior
- * \par
- * Correlation requires summing up a large number of intermediate products.
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
- * Refer to the function specific documentation below for further details of the particular algorithm used.
- *
- *
- * Fast Versions
- *
- * \par
- * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.
- *
- *
- * Opt Versions
- *
- * \par
- * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-/**
- * @brief Correlation of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
-void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t *pIn1; /* inputA pointer */
- float32_t *pIn2; /* inputB pointer */
- float32_t *pOut = pDst; /* output pointer */
- float32_t *px; /* Intermediate inputA pointer */
- float32_t *py; /* Intermediate inputB pointer */
- float32_t *pSrc1; /* Intermediate pointers */
- float32_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counters */
- int32_t inc = 1; /* Destination address modifier */
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we assume zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcA;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcB;
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding has to be done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- //while (j > 0u)
- //{
- // /* Zero is stored in the destination buffer */
- // *pOut++ = 0.0f;
-
- // /* Decrement the loop counter */
- // j--;
- //}
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = pSrcB;
-
- /* Initialization of inputB pointer */
- pIn2 = pSrcA;
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] */
- sum += *px++ * *py++;
- /* x[1] * y[srcBLen - 3] */
- sum += *px++ * *py++;
- /* x[2] * y[srcBLen - 2] */
- sum += *px++ * *py++;
- /* x[3] * y[srcBLen - 1] */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- /* x[0] * y[srcBLen - 1] */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[0] sample */
- c0 = *(py++);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[0] */
- acc0 += x0 * c0;
- /* acc1 += x[1] * y[0] */
- acc1 += x1 * c0;
- /* acc2 += x[2] * y[0] */
- acc2 += x2 * c0;
- /* acc3 += x[3] * y[0] */
- acc3 += x3 * c0;
-
- /* Read y[1] sample */
- c0 = *(py++);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[1] * y[1] */
- acc0 += x1 * c0;
- /* acc1 += x[2] * y[1] */
- acc1 += x2 * c0;
- /* acc2 += x[3] * y[1] */
- acc2 += x3 * c0;
- /* acc3 += x[4] * y[1] */
- acc3 += x0 * c0;
-
- /* Read y[2] sample */
- c0 = *(py++);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[2] */
- acc0 += x2 * c0;
- /* acc1 += x[3] * y[2] */
- acc1 += x3 * c0;
- /* acc2 += x[4] * y[2] */
- acc2 += x0 * c0;
- /* acc3 += x[5] * y[2] */
- acc3 += x1 * c0;
-
- /* Read y[3] sample */
- c0 = *(py++);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[3] */
- acc0 += x3 * c0;
- /* acc1 += x[4] * y[3] */
- acc1 += x0 * c0;
- /* acc2 += x[5] * y[3] */
- acc2 += x1 * c0;
- /* acc3 += x[6] * y[3] */
- acc3 += x2 * c0;
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[4] sample */
- c0 = *(py++);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[4] */
- acc0 += x0 * c0;
- /* acc1 += x[5] * y[4] */
- acc1 += x1 * c0;
- /* acc2 += x[6] * y[4] */
- acc2 += x2 * c0;
- /* acc3 += x[7] * y[4] */
- acc3 += x3 * c0;
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = acc0;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = acc1;
- pOut += inc;
-
- *pOut = acc2;
- pOut += inc;
-
- *pOut = acc3;
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += *px++ * *py++;
- sum += *px++ * *py++;
- sum += *px++ * *py++;
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0.0f;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen - srcBLen + 4] * y[3] */
- sum += *px++ * *py++;
- /* sum += x[srcALen - srcBLen + 3] * y[2] */
- sum += *px++ * *py++;
- /* sum += x[srcALen - srcBLen + 2] * y[1] */
- sum += *px++ * *py++;
- /* sum += x[srcALen - srcBLen + 1] * y[0] */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += *px++ * *py++;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t *pIn1 = pSrcA; /* inputA pointer */
- float32_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
- float32_t sum; /* Accumulator */
- uint32_t i = 0u, j; /* loop counters */
- uint32_t inv = 0u; /* Reverse order flag */
- uint32_t tot = 0u; /* Length */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and a varaible, inv is set to 1 */
- /* If lengths are not equal then zero pad has to be done to make the two
- * inputs of same length. But to improve the performance, we assume zeroes
- * in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * starting of the output buffer */
- /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * ending of the output buffer */
- /* Once the zero padding is done the remaining of the output is calcualted
- * using convolution but with the shorter signal time shifted. */
-
- /* Calculate the length of the remaining sequence */
- tot = ((srcALen + srcBLen) - 2u);
-
- if (srcALen > srcBLen)
- {
- /* Calculating the number of zeros to be padded to the output */
- j = srcALen - srcBLen;
-
- /* Initialise the pointer after zero padding */
- pDst += j;
- }
-
- else if (srcALen < srcBLen)
- {
- /* Initialization to inputB pointer */
- pIn1 = pSrcB;
-
- /* Initialization to the end of inputA pointer */
- pIn2 = pSrcA + (srcALen - 1u);
-
- /* Initialisation of the pointer after zero padding */
- pDst = pDst + tot;
-
- /* Swapping the lengths */
- j = srcALen;
- srcALen = srcBLen;
- srcBLen = j;
-
- /* Setting the reverse flag */
- inv = 1;
-
- }
-
- /* Loop to calculate convolution for output length number of times */
- for (i = 0u; i <= tot; i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0.0f;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += pIn1[j] * pIn2[-((int32_t) i - j)];
- }
- }
- /* Store the output in the destination buffer */
- if (inv == 1)
- *pDst-- = sum;
- else
- *pDst++ = sum;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
deleted file mode 100644
index 578a076..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
+++ /dev/null
@@ -1,500 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_fast_opt_q15.c
- * Description: Fast Q15 Correlation
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- *
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch buffers should be aligned by 32-bit
- *
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
- *
- * \par
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
- */
-
-void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch)
-{
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *py; /* Intermediate inputB pointer */
- q31_t x1, x2, x3; /* temporary variables for holding input and coefficient values */
- uint32_t j, blkCnt, outBlockSize; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
- uint32_t tapCnt;
- q31_t y1, y2;
- q15_t *pScr; /* Intermediate pointers */
- q15_t *pOut = pDst; /* output pointer */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- q15_t a, b;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- pScr = pScratch;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr, srcALen);
-
- /* Update pointers */
- pScr += srcALen;
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- j = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (j > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- j = srcALen % 0x4u;
-
- while (j > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr++ = *pIn1++;
-
- /* Decrement the loop counter */
- j--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr, (srcBLen - 1u));
-
- /* Update pointer */
- pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
- j = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (j > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr++ = 0;
- *pScr++ = 0;
- *pScr++ = 0;
- *pScr++ = 0;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- j = (srcBLen - 1u) % 0x4u;
-
- while (j > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr++ = 0;
-
- /* Decrement the loop counter */
- j--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Temporary pointer for scratch2 */
- py = pIn2;
-
-
- /* Actual correlation process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr = pScratch;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read four samples from scratch1 buffer */
- x1 = *__SIMD32(pScr)++;
-
- /* Read next four samples from scratch1 buffer */
- x2 = *__SIMD32(pScr)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- acc0 = __SMLAD(x1, y1, acc0);
-
- acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- x1 = _SIMD32_OFFSET(pScr);
-
- acc0 = __SMLAD(x2, y2, acc0);
-
- acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- acc1 = __SMLADX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y2, acc3);
-#else
-
- /* Read four samples from smaller buffer */
- a = *pIn2;
- b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- y1 = __PKHBT(a, b, 16);
-#else
- y1 = __PKHBT(b, a, 16);
-#endif
-
- a = *(pIn2 + 2);
- b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
- y2 = __PKHBT(a, b, 16);
-#else
- y2 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLAD(x1, y1, acc0);
-
- acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- a = *pScr;
- b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(a, b, 16);
-#else
- x1 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLAD(x2, y2, acc0);
-
- acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- acc1 = __SMLADX(x3, y2, acc1);
-
- a = *(pScr + 2);
- b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x2 = __PKHBT(a, b, 16);
-#else
- x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y2, acc3);
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- pIn2 += 4u;
-
- pScr += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr++ * *pIn2);
- acc1 += (*pScr++ * *pIn2);
- acc2 += (*pScr++ * *pIn2);
- acc3 += (*pScr++ * *pIn2++);
-
- pScr -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut = (__SSAT(acc0 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc1 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc2 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc3 >> 15u, 16));
- pOut += inc;
-
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate correlation for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr = pScratch;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- acc0 += (*pScr++ * *pIn2++);
- acc0 += (*pScr++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
-
- *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- pOut += inc;
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch += 1u;
-
- }
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
deleted file mode 100644
index 0f21473..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
+++ /dev/null
@@ -1,1307 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_fast_q15.c
- * Description: Fast Q15 Correlation
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
- *
- * \par
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
- */
-
-void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first loop starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
- sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
- /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
- sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum = __SMLAD(*px++, *py++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px + 1);
- px += 2u;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the first two inputB samples using SIMD:
- * y[0] and y[1] */
- c0 = *__SIMD32(py)++;
-
- /* acc0 += x[0] * y[0] + x[1] * y[1] */
- acc0 = __SMLAD(x0, c0, acc0);
-
- /* acc1 += x[1] * y[0] + x[2] * y[1] */
- acc1 = __SMLAD(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px + 1);
-
- /* acc2 += x[2] * y[0] + x[3] * y[1] */
- acc2 = __SMLAD(x2, c0, acc2);
-
- /* acc3 += x[3] * y[0] + x[4] * y[1] */
- acc3 = __SMLAD(x3, c0, acc3);
-
- /* Read y[2] and y[3] */
- c0 = *__SIMD32(py)++;
-
- /* acc0 += x[2] * y[2] + x[3] * y[3] */
- acc0 = __SMLAD(x2, c0, acc0);
-
- /* acc1 += x[3] * y[2] + x[4] * y[3] */
- acc1 = __SMLAD(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px + 2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px + 3);
- px += 4u;
-
- /* acc2 += x[4] * y[2] + x[5] * y[3] */
- acc2 = __SMLAD(x0, c0, acc2);
-
- /* acc3 += x[5] * y[2] + x[6] * y[3] */
- acc3 = __SMLAD(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[4] */
- c0 = *py;
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[4], y[5] */
- c0 = *__SIMD32(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px + 1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLAD(x3, c0, acc2);
- acc3 = __SMLAD(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[4], y[5] */
- c0 = *__SIMD32(py)++;
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px + 1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLAD(x3, c0, acc2);
- acc3 = __SMLAD(x2, c0, acc3);
-
- c0 = (*py);
- /* Read y[6] */
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px + 2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (acc0 >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q15_t) (acc1 >> 15);
- pOut += inc;
-
- *pOut = (q15_t) (acc2 >> 15);
- pOut += inc;
-
- *pOut = (q15_t) (acc3 >> 15);
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
- sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
- /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
- sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLAD(*px++, *py++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
- q15_t a, b;
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first loop starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 2u;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the first two inputB samples using SIMD:
- * y[0] and y[1] */
- a = *py;
- b = *(py + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[0] * y[0] + x[1] * y[1] */
- acc0 = __SMLAD(x0, c0, acc0);
-
- /* acc1 += x[1] * y[0] + x[2] * y[1] */
- acc1 = __SMLAD(x1, c0, acc1);
-
- /* Read x[2], x[3], x[4] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x2 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x3 = __PKHBT(b, a, 16);
-
-#else
-
- x2 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x3 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc2 += x[2] * y[0] + x[3] * y[1] */
- acc2 = __SMLAD(x2, c0, acc2);
-
- /* acc3 += x[3] * y[0] + x[4] * y[1] */
- acc3 = __SMLAD(x3, c0, acc3);
-
- /* Read y[2] and y[3] */
- a = *(py + 2);
- b = *(py + 3);
-
- py += 4u;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* acc0 += x[2] * y[2] + x[3] * y[3] */
- acc0 = __SMLAD(x2, c0, acc0);
-
- /* acc1 += x[3] * y[2] + x[4] * y[3] */
- acc1 = __SMLAD(x3, c0, acc1);
-
- /* Read x[4], x[5], x[6] */
- a = *(px + 2);
- b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x0 = __PKHBT(a, b, 16);
- a = *(px + 4);
- x1 = __PKHBT(b, a, 16);
-
-#else
-
- x0 = __PKHBT(b, a, 16);
- a = *(px + 4);
- x1 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 4u;
-
- /* acc2 += x[4] * y[2] + x[5] * y[3] */
- acc2 = __SMLAD(x0, c0, acc2);
-
- /* acc3 += x[5] * y[2] + x[6] * y[3] */
- acc3 = __SMLAD(x1, c0, acc3);
-
- } while (--k);
-
- /* For the next MAC operations, SIMD is not used
- * So, the 16 bit pointer if inputB, py is updated */
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[4] */
- c0 = *py;
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7] */
- a = *px;
- b = *(px + 1);
-
- px++;;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLADX(x1, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[4], y[5] */
- a = *py;
- b = *(py + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLAD(x3, c0, acc2);
- acc3 = __SMLAD(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[4], y[5] */
- a = *py;
- b = *(py + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- c0 = __PKHBT(a, b, 16);
-
-#else
-
- c0 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- py += 2u;
-
- /* Read x[7], x[8], x[9] */
- a = *px;
- b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
- a = *(px + 2);
- x2 = __PKHBT(b, a, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
- a = *(px + 2);
- x2 = __PKHBT(a, b, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
- acc2 = __SMLAD(x3, c0, acc2);
- acc3 = __SMLAD(x2, c0, acc3);
-
- c0 = (*py);
- /* Read y[6] */
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
-
- /* Read x[10] */
- b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- x3 = __PKHBT(a, b, 16);
-
-#else
-
- x3 = __PKHBT(b, a, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLADX(x1, c0, acc0);
- acc1 = __SMLAD(x2, c0, acc1);
- acc2 = __SMLADX(x2, c0, acc2);
- acc3 = __SMLADX(x3, c0, acc3);
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (acc0 >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q15_t) (acc1 >> 15);
- pOut += inc;
-
- *pOut = (q15_t) (acc2 >> 15);
- pOut += inc;
-
- *pOut = (q15_t) (acc3 >> 15);
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q31_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (sum >> 15);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
deleted file mode 100644
index b0b8b8f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_fast_q31.c
- * Description: Fast Q31 Correlation
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.
- * Finally, the accumulator is saturated and converted to a 1.31 result.
- *
- * \par
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signals must be scaled down.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.
- *
- * \par
- * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
- */
-
-void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst)
-{
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1; /* Intermediate pointers */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* x[1] * y[srcBLen - 3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* x[2] * y[srcBLen - 2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* x[3] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum << 1;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[0] sample */
- c0 = *(py++);
-
- /* Read x[3] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[0] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc1 += x[1] * y[0] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc2 += x[2] * y[0] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc3 += x[3] * y[0] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Read y[1] sample */
- c0 = *(py++);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[1] * y[1] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc1 += x[2] * y[1] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc2 += x[3] * y[1] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc3 += x[4] * y[1] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read y[2] sample */
- c0 = *(py++);
-
- /* Read x[5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[2] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc1 += x[3] * y[2] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc2 += x[4] * y[2] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc3 += x[5] * y[2] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read y[3] sample */
- c0 = *(py++);
-
- /* Read x[6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[3] * y[3] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
- /* acc1 += x[4] * y[3] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc2 += x[5] * y[3] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc3 += x[6] * y[3] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[4] sample */
- c0 = *(py++);
-
- /* Read x[7] sample */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[4] */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- /* acc1 += x[5] * y[4] */
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
- /* acc2 += x[6] * y[4] */
- acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
- /* acc3 += x[7] * y[4] */
- acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (acc0 << 1);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q31_t) (acc1 << 1);
- pOut += inc;
-
- *pOut = (q31_t) (acc2 << 1);
- pOut += inc;
-
- *pOut = (q31_t) (acc3 << 1);
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 4 */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum << 1;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum << 1;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen - srcBLen + 4] * y[3] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* sum += x[srcALen - srcBLen + 3] * y[2] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* sum += x[srcALen - srcBLen + 2] * y[1] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
- /* sum += x[srcALen - srcBLen + 1] * y[0] */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = (q31_t) ((((q63_t) sum << 32) +
- ((q63_t) * px++ * (*py++))) >> 32);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = sum << 1;
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
deleted file mode 100644
index bced1cc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
+++ /dev/null
@@ -1,501 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_opt_q15.c
- * Description: Correlation of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch buffers should be aligned by 32-bit
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * This approach provides 33 guard bits and there is no risk of overflow.
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
- *
- * \par
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- *
- */
-
-
-void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch)
-{
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q63_t acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *py; /* Intermediate inputB pointer */
- q31_t x1, x2, x3; /* temporary variables for holding input1 and input2 values */
- uint32_t j, blkCnt, outBlockSize; /* loop counter */
- int32_t inc = 1; /* output pointer increment */
- uint32_t tapCnt;
- q31_t y1, y2;
- q15_t *pScr; /* Intermediate pointers */
- q15_t *pOut = pDst; /* output pointer */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- q15_t a, b;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- pScr = pScratch;
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Copy (srcALen) samples in scratch buffer */
- arm_copy_q15(pIn1, pScr, srcALen);
-
- /* Update pointers */
- //pIn1 += srcALen;
- pScr += srcALen;
-
-#else
-
- /* Apply loop unrolling and do 4 Copies simultaneously. */
- j = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (j > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
- *pScr++ = *pIn1++;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- j = srcALen % 0x4u;
-
- while (j > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr++ = *pIn1++;
-
- /* Decrement the loop counter */
- j--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr, (srcBLen - 1u));
-
- /* Update pointer */
- pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
- j = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (j > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr++ = 0;
- *pScr++ = 0;
- *pScr++ = 0;
- *pScr++ = 0;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- j = (srcBLen - 1u) % 0x4u;
-
- while (j > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr++ = 0;
-
- /* Decrement the loop counter */
- j--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Temporary pointer for scratch2 */
- py = pIn2;
-
-
- /* Actual correlation process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr = pScratch;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read four samples from scratch1 buffer */
- x1 = *__SIMD32(pScr)++;
-
- /* Read next four samples from scratch1 buffer */
- x2 = *__SIMD32(pScr)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pIn2);
- y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
- acc0 = __SMLALD(x1, y1, acc0);
-
- acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLALDX(x3, y1, acc1);
-
- x1 = _SIMD32_OFFSET(pScr);
-
- acc0 = __SMLALD(x2, y2, acc0);
-
- acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y1, acc3);
-
- acc1 = __SMLALDX(x3, y2, acc1);
-
- x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y2, acc3);
-
-#else
-
- /* Read four samples from smaller buffer */
- a = *pIn2;
- b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- y1 = __PKHBT(a, b, 16);
-#else
- y1 = __PKHBT(b, a, 16);
-#endif
-
- a = *(pIn2 + 2);
- b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
- y2 = __PKHBT(a, b, 16);
-#else
- y2 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLALD(x1, y1, acc0);
-
- acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc1 = __SMLALDX(x3, y1, acc1);
-
- a = *pScr;
- b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(a, b, 16);
-#else
- x1 = __PKHBT(b, a, 16);
-#endif
-
- acc0 = __SMLALD(x2, y2, acc0);
-
- acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y1, acc3);
-
- acc1 = __SMLALDX(x3, y2, acc1);
-
- a = *(pScr + 2);
- b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x2 = __PKHBT(a, b, 16);
-#else
- x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- pIn2 += 4u;
-
- pScr += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr++ * *pIn2);
- acc1 += (*pScr++ * *pIn2);
- acc2 += (*pScr++ * *pIn2);
- acc3 += (*pScr++ * *pIn2++);
-
- pScr -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
-
- /* Store the results in the accumulators in the destination buffer. */
- *pOut = (__SSAT(acc0 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc1 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc2 >> 15u, 16));
- pOut += inc;
- *pOut = (__SSAT(acc3 >> 15u, 16));
- pOut += inc;
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate correlation for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr = pScratch;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
-
- acc0 += (*pScr++ * *pIn2++);
- acc0 += (*pScr++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr++ * *pIn2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- pOut += inc;
-
- /* Initialization of inputB pointer */
- pIn2 = py;
-
- pScratch += 1u;
-
- }
-
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
deleted file mode 100644
index 9674939..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_opt_q7.c
- * Description: Correlation of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- *
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
- *
- *
- */
-
-
-
-void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2)
-{
- q7_t *pOut = pDst; /* output pointer */
- q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
- q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
- q7_t *pIn1; /* inputA pointer */
- q7_t *pIn2; /* inputB pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- uint32_t j, k = 0u, blkCnt; /* loop counter */
- int32_t inc = 1; /* output pointer increment */
- uint32_t outBlockSize; /* loop counter */
- q15_t x4; /* Temporary input variable */
- uint32_t tapCnt; /* loop counter */
- q31_t x1, x2, x3, y1; /* Temporary input variables */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
-
- /* Copy (srcBLen) samples in scratch buffer */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * pIn2++;
- *pScr2++ = x4;
- x4 = (q15_t) * pIn2++;
- *pScr2++ = x4;
- x4 = (q15_t) * pIn2++;
- *pScr2++ = x4;
- x4 = (q15_t) * pIn2++;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * pIn2++;
- *pScr2++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Fill (srcBLen - 1u) zeros in scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update temporary scratch pointer */
- pScr1 += (srcBLen - 1u);
-
- /* Copy (srcALen) samples in scratch buffer */
- k = srcALen >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = srcALen % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- x4 = (q15_t) * pIn1++;
- *pScr1++ = x4;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
- arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
- /* Update pointer */
- pScr1 += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
- k = (srcBLen - 1u) >> 2u;
-
- /* First part of the processing with loop unrolling copies 4 data points at a time.
- ** a second loop below copies for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* copy second buffer in reversal manner */
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, copy remaining samples here.
- ** No loop unrolling is used. */
- k = (srcBLen - 1u) % 0x4u;
-
- while (k > 0u)
- {
- /* copy second buffer in reversal manner for remaining samples */
- *pScr1++ = 0;
-
- /* Decrement the loop counter */
- k--;
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Temporary pointer for second sequence */
- py = pScratch2;
-
- /* Initialization of pScr2 pointer */
- pScr2 = pScratch2;
-
- /* Actual correlation process starts here */
- blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Read two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* Read next two samples from scratch1 buffer */
- x2 = *__SIMD32(pScr1)++;
-
- tapCnt = (srcBLen) >> 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2);
-
- /* multiply and accumlate */
- acc0 = __SMLAD(x1, y1, acc0);
- acc2 = __SMLAD(x2, y1, acc2);
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- /* multiply and accumlate */
- acc1 = __SMLADX(x3, y1, acc1);
-
- /* Read next two samples from scratch1 buffer */
- x1 = *__SIMD32(pScr1)++;
-
- /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x1, x2, 0);
-#else
- x3 = __PKHBT(x2, x1, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- /* Read four samples from smaller buffer */
- y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
- acc0 = __SMLAD(x2, y1, acc0);
-
- acc2 = __SMLAD(x1, y1, acc2);
-
- acc1 = __SMLADX(x3, y1, acc1);
-
- x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
- x3 = __PKHBT(x2, x1, 0);
-#else
- x3 = __PKHBT(x1, x2, 0);
-#endif
-
- acc3 = __SMLADX(x3, y1, acc3);
-
- pScr2 += 4u;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-
- /* Update scratch pointer for remaining samples of smaller length sequence */
- pScr1 -= 4u;
-
-
- /* apply same above for remaining samples of smaller length sequence */
- tapCnt = (srcBLen) & 3u;
-
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2);
- acc1 += (*pScr1++ * *pScr2);
- acc2 += (*pScr1++ * *pScr2);
- acc3 += (*pScr1++ * *pScr2++);
-
- pScr1 -= 3u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
- pOut += inc;
- *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
- pOut += inc;
- *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
- pOut += inc;
- *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
- pOut += inc;
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 4u;
-
- }
-
-
- blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
- /* Calculate correlation for remaining samples of Bigger length sequence */
- while (blkCnt > 0)
- {
- /* Initialze temporary scratch pointer as scratch1 */
- pScr1 = pScratch1;
-
- /* Clear Accumlators */
- acc0 = 0;
-
- tapCnt = (srcBLen) >> 1u;
-
- while (tapCnt > 0u)
- {
- acc0 += (*pScr1++ * *pScr2++);
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (srcBLen) & 1u;
-
- /* apply same above for remaining samples of smaller length sequence */
- while (tapCnt > 0u)
- {
-
- /* accumlate the results */
- acc0 += (*pScr1++ * *pScr2++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- blkCnt--;
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
- pOut += inc;
-
- /* Initialization of inputB pointer */
- pScr2 = py;
-
- pScratch1 += 1u;
-
- }
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c
deleted file mode 100644
index 1812d37..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_q15.c
- * Description: Correlation of Q15 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * This approach provides 33 guard bits and there is no risk of overflow.
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
- *
- * \par
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- * \par
- * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
- *
- */
-
-void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t *pIn1; /* inputA pointer */
- q15_t *pIn2; /* inputB pointer */
- q15_t *pOut = pDst; /* output pointer */
- q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *px; /* Intermediate inputA pointer */
- q15_t *py; /* Intermediate inputB pointer */
- q15_t *pSrc1; /* Intermediate pointers */
- q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first loop starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
- sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
- /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
- sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum = __SMLALD(*px++, *py++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT((sum >> 15), 16));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1] samples */
- x0 = *__SIMD32(px);
- /* read x[1], x[2] samples */
- x1 = _SIMD32_OFFSET(px + 1);
- px += 2u;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read the first two inputB samples using SIMD:
- * y[0] and y[1] */
- c0 = *__SIMD32(py)++;
-
- /* acc0 += x[0] * y[0] + x[1] * y[1] */
- acc0 = __SMLALD(x0, c0, acc0);
-
- /* acc1 += x[1] * y[0] + x[2] * y[1] */
- acc1 = __SMLALD(x1, c0, acc1);
-
- /* Read x[2], x[3] */
- x2 = *__SIMD32(px);
-
- /* Read x[3], x[4] */
- x3 = _SIMD32_OFFSET(px + 1);
-
- /* acc2 += x[2] * y[0] + x[3] * y[1] */
- acc2 = __SMLALD(x2, c0, acc2);
-
- /* acc3 += x[3] * y[0] + x[4] * y[1] */
- acc3 = __SMLALD(x3, c0, acc3);
-
- /* Read y[2] and y[3] */
- c0 = *__SIMD32(py)++;
-
- /* acc0 += x[2] * y[2] + x[3] * y[3] */
- acc0 = __SMLALD(x2, c0, acc0);
-
- /* acc1 += x[3] * y[2] + x[4] * y[3] */
- acc1 = __SMLALD(x3, c0, acc1);
-
- /* Read x[4], x[5] */
- x0 = _SIMD32_OFFSET(px + 2);
-
- /* Read x[5], x[6] */
- x1 = _SIMD32_OFFSET(px + 3);
-
- px += 4u;
-
- /* acc2 += x[4] * y[2] + x[5] * y[3] */
- acc2 = __SMLALD(x0, c0, acc2);
-
- /* acc3 += x[5] * y[2] + x[6] * y[3] */
- acc3 = __SMLALD(x1, c0, acc3);
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- if (k == 1u)
- {
- /* Read y[4] */
- c0 = *py;
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-
-#else
-
- c0 = c0 & 0x0000FFFF;
-
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
- /* Read x[7] */
- x3 = *__SIMD32(px);
- px++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALDX(x1, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
- if (k == 2u)
- {
- /* Read y[4], y[5] */
- c0 = *__SIMD32(py);
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px + 1);
- px += 2u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALD(x3, c0, acc2);
- acc3 = __SMLALD(x2, c0, acc3);
- }
-
- if (k == 3u)
- {
- /* Read y[4], y[5] */
- c0 = *__SIMD32(py)++;
-
- /* Read x[7], x[8] */
- x3 = *__SIMD32(px);
-
- /* Read x[9] */
- x2 = _SIMD32_OFFSET(px + 1);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALD(x3, c0, acc2);
- acc3 = __SMLALD(x2, c0, acc3);
-
- c0 = (*py);
-
- /* Read y[6] */
-#ifdef ARM_MATH_BIG_ENDIAN
-
- c0 = c0 << 16u;
-#else
-
- c0 = c0 & 0x0000FFFF;
-#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
- /* Read x[10] */
- x3 = _SIMD32_OFFSET(px + 2);
- px += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALDX(x1, c0, acc0);
- acc1 = __SMLALD(x2, c0, acc1);
- acc2 = __SMLALDX(x2, c0, acc2);
- acc3 = __SMLALDX(x3, c0, acc3);
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
- pOut += inc;
-
- *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
- pOut += inc;
-
- *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
- pOut += inc;
-
- /* Increment the count by 4 as 4 output values are computed */
- count += 4u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q63_t) * px++ * *py++);
- sum += ((q63_t) * px++ * *py++);
- sum += ((q63_t) * px++ * *py++);
- sum += ((q63_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q63_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT(sum >> 15, 16));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment count by 1, as one output value is computed */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q63_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT(sum >> 15, 16));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
- sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
- /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
- sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum = __SMLALD(*px++, *py++, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q15_t) (__SSAT((sum >> 15), 16));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- q15_t *pIn1 = pSrcA; /* inputA pointer */
- q15_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
- q63_t sum; /* Accumulators */
- uint32_t i = 0u, j; /* loop counters */
- uint32_t inv = 0u; /* Reverse order flag */
- uint32_t tot = 0u; /* Length */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and a varaible, inv is set to 1 */
- /* If lengths are not equal then zero pad has to be done to make the two
- * inputs of same length. But to improve the performance, we include zeroes
- * in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * starting of the output buffer */
- /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * ending of the output buffer */
- /* Once the zero padding is done the remaining of the output is calcualted
- * using convolution but with the shorter signal time shifted. */
-
- /* Calculate the length of the remaining sequence */
- tot = ((srcALen + srcBLen) - 2u);
-
- if (srcALen > srcBLen)
- {
- /* Calculating the number of zeros to be padded to the output */
- j = srcALen - srcBLen;
-
- /* Initialise the pointer after zero padding */
- pDst += j;
- }
-
- else if (srcALen < srcBLen)
- {
- /* Initialization to inputB pointer */
- pIn1 = pSrcB;
-
- /* Initialization to the end of inputA pointer */
- pIn2 = pSrcA + (srcALen - 1u);
-
- /* Initialisation of the pointer after zero padding */
- pDst = pDst + tot;
-
- /* Swapping the lengths */
- j = srcALen;
- srcALen = srcBLen;
- srcBLen = j;
-
- /* Setting the reverse flag */
- inv = 1;
-
- }
-
- /* Loop to calculate convolution for output length number of times */
- for (i = 0u; i <= tot; i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
- }
- }
- /* Store the output in the destination buffer */
- if (inv == 1)
- *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
- else
- *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
- }
-
-#endif /* #if (defined(ARM_MATH_CM7) || defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c
deleted file mode 100644
index ddf689c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_q31.c
- * Description: Correlation of Q31 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * There is no saturation on intermediate additions.
- * Thus, if the accumulator overflows it wraps around and distorts the result.
- * The input signals should be scaled down to avoid intermediate overflows.
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
- *
- * \par
- * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- */
-
-void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t *pIn1; /* inputA pointer */
- q31_t *pIn2; /* inputB pointer */
- q31_t *pOut = pDst; /* output pointer */
- q31_t *px; /* Intermediate inputA pointer */
- q31_t *py; /* Intermediate inputB pointer */
- q31_t *pSrc1; /* Intermediate pointers */
- q63_t sum, acc0, acc1, acc2; /* Accumulators */
- q31_t x0, x1, x2, c0; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1; /* Destination address modifier */
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] * y[srcBLen - 4] */
- sum += (q63_t) * px++ * (*py++);
- /* x[1] * y[srcBLen - 3] */
- sum += (q63_t) * px++ * (*py++);
- /* x[2] * y[srcBLen - 2] */
- sum += (q63_t) * px++ * (*py++);
- /* x[3] * y[srcBLen - 1] */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (sum >> 31);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll by 3 */
- blkCnt = blockSize2 / 3;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
-
- /* read x[0], x[1] samples */
- x0 = *(px++);
- x1 = *(px++);
-
- /* Apply loop unrolling and compute 3 MACs simultaneously. */
- k = srcBLen / 3;
-
- /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 2 samples. */
- do
- {
- /* Read y[0] sample */
- c0 = *(py);
-
- /* Read x[2] sample */
- x2 = *(px);
-
- /* Perform the multiply-accumulate */
- /* acc0 += x[0] * y[0] */
- acc0 += ((q63_t) x0 * c0);
- /* acc1 += x[1] * y[0] */
- acc1 += ((q63_t) x1 * c0);
- /* acc2 += x[2] * y[0] */
- acc2 += ((q63_t) x2 * c0);
-
- /* Read y[1] sample */
- c0 = *(py + 1u);
-
- /* Read x[3] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[1] * y[1] */
- acc0 += ((q63_t) x1 * c0);
- /* acc1 += x[2] * y[1] */
- acc1 += ((q63_t) x2 * c0);
- /* acc2 += x[3] * y[1] */
- acc2 += ((q63_t) x0 * c0);
-
- /* Read y[2] sample */
- c0 = *(py + 2u);
-
- /* Read x[4] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[2] * y[2] */
- acc0 += ((q63_t) x2 * c0);
- /* acc1 += x[3] * y[2] */
- acc1 += ((q63_t) x0 * c0);
- /* acc2 += x[4] * y[2] */
- acc2 += ((q63_t) x1 * c0);
-
- /* update scratch pointers */
- px += 3u;
- py += 3u;
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen - (3 * (srcBLen / 3));
-
- while (k > 0u)
- {
- /* Read y[4] sample */
- c0 = *(py++);
-
- /* Read x[7] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[4] */
- acc0 += ((q63_t) x0 * c0);
- /* acc1 += x[5] * y[4] */
- acc1 += ((q63_t) x1 * c0);
- /* acc2 += x[6] * y[4] */
- acc2 += ((q63_t) x2 * c0);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (acc0 >> 31);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q31_t) (acc1 >> 31);
- pOut += inc;
-
- *pOut = (q31_t) (acc2 >> 31);
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 3 */
- count += 3u;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) * px++ * (*py++);
- sum += (q63_t) * px++ * (*py++);
- sum += (q63_t) * px++ * (*py++);
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (sum >> 31);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (sum >> 31);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* sum += x[srcALen - srcBLen + 4] * y[3] */
- sum += (q63_t) * px++ * (*py++);
- /* sum += x[srcALen - srcBLen + 3] * y[2] */
- sum += (q63_t) * px++ * (*py++);
- /* sum += x[srcALen - srcBLen + 2] * y[1] */
- sum += (q63_t) * px++ * (*py++);
- /* sum += x[srcALen - srcBLen + 1] * y[0] */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += (q63_t) * px++ * (*py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q31_t) (sum >> 31);
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t *pIn1 = pSrcA; /* inputA pointer */
- q31_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
- q63_t sum; /* Accumulators */
- uint32_t i = 0u, j; /* loop counters */
- uint32_t inv = 0u; /* Reverse order flag */
- uint32_t tot = 0u; /* Length */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and a varaible, inv is set to 1 */
- /* If lengths are not equal then zero pad has to be done to make the two
- * inputs of same length. But to improve the performance, we include zeroes
- * in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * starting of the output buffer */
- /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * ending of the output buffer */
- /* Once the zero padding is done the remaining of the output is calcualted
- * using correlation but with the shorter signal time shifted. */
-
- /* Calculate the length of the remaining sequence */
- tot = ((srcALen + srcBLen) - 2u);
-
- if (srcALen > srcBLen)
- {
- /* Calculating the number of zeros to be padded to the output */
- j = srcALen - srcBLen;
-
- /* Initialise the pointer after zero padding */
- pDst += j;
- }
-
- else if (srcALen < srcBLen)
- {
- /* Initialization to inputB pointer */
- pIn1 = pSrcB;
-
- /* Initialization to the end of inputA pointer */
- pIn2 = pSrcA + (srcALen - 1u);
-
- /* Initialisation of the pointer after zero padding */
- pDst = pDst + tot;
-
- /* Swapping the lengths */
- j = srcALen;
- srcALen = srcBLen;
- srcBLen = j;
-
- /* Setting the reverse flag */
- inv = 1;
-
- }
-
- /* Loop to calculate correlation for output length number of times */
- for (i = 0u; i <= tot; i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to correlation equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
- }
- }
- /* Store the output in the destination buffer */
- if (inv == 1)
- *pDst-- = (q31_t) (sum >> 31u);
- else
- *pDst++ = (q31_t) (sum >> 31u);
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
deleted file mode 100644
index 1d4deee..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
+++ /dev/null
@@ -1,778 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_correlate_q7.c
- * Description: Correlation of Q7 sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup Corr
- * @{
- */
-
-/**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
- *
- * \par
- * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
- *
- */
-
-void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t *pIn1; /* inputA pointer */
- q7_t *pIn2; /* inputB pointer */
- q7_t *pOut = pDst; /* output pointer */
- q7_t *px; /* Intermediate inputA pointer */
- q7_t *py; /* Intermediate inputB pointer */
- q7_t *pSrc1; /* Intermediate pointers */
- q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
- q31_t input1, input2; /* temporary variables */
- q15_t in1, in2; /* temporary variables */
- q7_t x0, x1, x2, x3, c0, c1; /* temporary variables for holding input and coefficient values */
- uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
- int32_t inc = 1;
-
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and the destination pointer modifier, inc is set to -1 */
- /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
- /* But to improve the performance,
- * we include zeroes in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
- /* If srcALen < srcBLen,
- * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
- if (srcALen >= srcBLen)
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcA);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcB);
-
- /* Number of output samples is calculated */
- outBlockSize = (2u * srcALen) - 1u;
-
- /* When srcALen > srcBLen, zero padding is done to srcB
- * to make their lengths equal.
- * Instead, (outBlockSize - (srcALen + srcBLen - 1))
- * number of output samples are made zero */
- j = outBlockSize - (srcALen + (srcBLen - 1u));
-
- /* Updating the pointer position to non zero value */
- pOut += j;
-
- }
- else
- {
- /* Initialization of inputA pointer */
- pIn1 = (pSrcB);
-
- /* Initialization of inputB pointer */
- pIn2 = (pSrcA);
-
- /* srcBLen is always considered as shorter or equal to srcALen */
- j = srcBLen;
- srcBLen = srcALen;
- srcALen = j;
-
- /* CORR(x, y) = Reverse order(CORR(y, x)) */
- /* Hence set the destination pointer to point to the last output sample */
- pOut = pDst + ((srcALen + srcBLen) - 2u);
-
- /* Destination address modifier is set to -1 */
- inc = -1;
-
- }
-
- /* The function is internally
- * divided into three parts according to the number of multiplications that has to be
- * taken place between inputA samples and inputB samples. In the first part of the
- * algorithm, the multiplications increase by one for every iteration.
- * In the second part of the algorithm, srcBLen number of multiplications are done.
- * In the third part of the algorithm, the multiplications decrease by one
- * for every iteration.*/
- /* The algorithm is implemented in three stages.
- * The loop counters of each stage is initiated here. */
- blockSize1 = srcBLen - 1u;
- blockSize2 = srcALen - (srcBLen - 1u);
- blockSize3 = blockSize1;
-
- /* --------------------------
- * Initializations of stage1
- * -------------------------*/
-
- /* sum = x[0] * y[srcBlen - 1]
- * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
- * ....
- * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
- */
-
- /* In this stage the MAC operations are increased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = 1u;
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- pSrc1 = pIn2 + (srcBLen - 1u);
- py = pSrc1;
-
- /* ------------------------
- * Stage1 process
- * ----------------------*/
-
- /* The first stage starts here */
- while (blockSize1 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[0] , x[1] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 4] , y[srcBLen - 3] */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* x[0] * y[srcBLen - 4] */
- /* x[1] * y[srcBLen - 3] */
- sum = __SMLAD(input1, input2, sum);
-
- /* x[2] , x[3] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[srcBLen - 2] , y[srcBLen - 1] */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* x[2] * y[srcBLen - 2] */
- /* x[3] * y[srcBLen - 1] */
- sum = __SMLAD(input1, input2, sum);
-
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- /* x[0] * y[srcBLen - 1] */
- sum += (q31_t) ((q15_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(sum >> 7, 8));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- py = pSrc1 - count;
- px = pIn1;
-
- /* Increment the MAC count */
- count++;
-
- /* Decrement the loop counter */
- blockSize1--;
- }
-
- /* --------------------------
- * Initializations of stage2
- * ------------------------*/
-
- /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
- * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
- * ....
- * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- */
-
- /* Working pointer of inputA */
- px = pIn1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* count is index by which the pointer pIn1 to be incremented */
- count = 0u;
-
- /* -------------------
- * Stage2 process
- * ------------------*/
-
- /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
- * So, to loop unroll over blockSize2,
- * srcBLen should be greater than or equal to 4 */
- if (srcBLen >= 4u)
- {
- /* Loop unroll over blockSize2, by 4 */
- blkCnt = blockSize2 >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* read x[0], x[1], x[2] samples */
- x0 = *px++;
- x1 = *px++;
- x2 = *px++;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- do
- {
- /* Read y[0] sample */
- c0 = *py++;
- /* Read y[1] sample */
- c1 = *py++;
-
- /* Read x[3] sample */
- x3 = *px++;
-
- /* x[0] and x[1] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[0] and y[1] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc0 += x[0] * y[0] + x[1] * y[1] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[1] and x[2] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc1 += x[1] * y[0] + x[2] * y[1] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc2 += x[2] * y[0] + x[3] * y[1] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[4] sample */
- x0 = *(px++);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc3 += x[3] * y[0] + x[4] * y[1] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- /* Read y[2] sample */
- c0 = *py++;
- /* Read y[3] sample */
- c1 = *py++;
-
- /* Read x[5] sample */
- x1 = *px++;
-
- /* x[2] and x[3] are packed */
- in1 = (q15_t) x2;
- in2 = (q15_t) x3;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[2] and y[3] are packed */
- in1 = (q15_t) c0;
- in2 = (q15_t) c1;
-
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc0 += x[2] * y[2] + x[3] * y[3] */
- acc0 = __SMLAD(input1, input2, acc0);
-
- /* x[3] and x[4] are packed */
- in1 = (q15_t) x3;
- in2 = (q15_t) x0;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc1 += x[3] * y[2] + x[4] * y[3] */
- acc1 = __SMLAD(input1, input2, acc1);
-
- /* x[4] and x[5] are packed */
- in1 = (q15_t) x0;
- in2 = (q15_t) x1;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc2 += x[4] * y[2] + x[5] * y[3] */
- acc2 = __SMLAD(input1, input2, acc2);
-
- /* Read x[6] sample */
- x2 = *px++;
-
- /* x[5] and x[6] are packed */
- in1 = (q15_t) x1;
- in2 = (q15_t) x2;
-
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* acc3 += x[5] * y[2] + x[6] * y[3] */
- acc3 = __SMLAD(input1, input2, acc3);
-
- } while (--k);
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Read y[4] sample */
- c0 = *py++;
-
- /* Read x[7] sample */
- x3 = *px++;
-
- /* Perform the multiply-accumulates */
- /* acc0 += x[4] * y[4] */
- acc0 += ((q15_t) x0 * c0);
- /* acc1 += x[5] * y[4] */
- acc1 += ((q15_t) x1 * c0);
- /* acc2 += x[6] * y[4] */
- acc2 += ((q15_t) x2 * c0);
- /* acc3 += x[7] * y[4] */
- acc3 += ((q15_t) x3 * c0);
-
- /* Reuse the present samples for the next MAC */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
- pOut += inc;
-
- *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
- pOut += inc;
-
- *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
- pOut += inc;
-
- count += 4u;
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize2 % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = srcBLen >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Reading two inputs of SrcA buffer and packing */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Reading two inputs of SrcB buffer and packing */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* Perform the multiply-accumulates */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = srcBLen % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q15_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(sum >> 7, 8));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the pointer pIn1 index, count by 1 */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
- else
- {
- /* If the srcBLen is not a multiple of 4,
- * the blockSize2 loop cannot be unrolled by 4 */
- blkCnt = blockSize2;
-
- while (blkCnt > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Loop over srcBLen */
- k = srcBLen;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += ((q15_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(sum >> 7, 8));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Increment the MAC count */
- count++;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = pIn1 + count;
- py = pIn2;
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
- }
-
- /* --------------------------
- * Initializations of stage3
- * -------------------------*/
-
- /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
- * ....
- * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
- * sum += x[srcALen-1] * y[0]
- */
-
- /* In this stage the MAC operations are decreased by 1 for every iteration.
- The count variable holds the number of MAC operations performed */
- count = srcBLen - 1u;
-
- /* Working pointer of inputA */
- pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
- px = pSrc1;
-
- /* Working pointer of inputB */
- py = pIn2;
-
- /* -------------------
- * Stage3 process
- * ------------------*/
-
- while (blockSize3 > 0u)
- {
- /* Accumulator is made zero for every iteration */
- sum = 0;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- k = count >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
- ** a second loop below computes MACs for the remaining 1 to 3 samples. */
- while (k > 0u)
- {
- /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[0] , y[1] */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* sum += x[srcALen - srcBLen + 1] * y[0] */
- /* sum += x[srcALen - srcBLen + 2] * y[1] */
- sum = __SMLAD(input1, input2, sum);
-
- /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
- in1 = (q15_t) * px++;
- in2 = (q15_t) * px++;
- input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* y[2] , y[3] */
- in1 = (q15_t) * py++;
- in2 = (q15_t) * py++;
- input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
- /* sum += x[srcALen - srcBLen + 3] * y[2] */
- /* sum += x[srcALen - srcBLen + 4] * y[3] */
- sum = __SMLAD(input1, input2, sum);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* If the count is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- k = count % 0x4u;
-
- while (k > 0u)
- {
- /* Perform the multiply-accumulates */
- sum += ((q15_t) * px++ * *py++);
-
- /* Decrement the loop counter */
- k--;
- }
-
- /* Store the result in the accumulator in the destination buffer. */
- *pOut = (q7_t) (__SSAT(sum >> 7, 8));
- /* Destination pointer is updated according to the address modifier, inc */
- pOut += inc;
-
- /* Update the inputA and inputB pointers for next MAC calculation */
- px = ++pSrc1;
- py = pIn2;
-
- /* Decrement the MAC count */
- count--;
-
- /* Decrement the loop counter */
- blockSize3--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- q7_t *pIn1 = pSrcA; /* inputA pointer */
- q7_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
- q31_t sum; /* Accumulator */
- uint32_t i = 0u, j; /* loop counters */
- uint32_t inv = 0u; /* Reverse order flag */
- uint32_t tot = 0u; /* Length */
-
- /* The algorithm implementation is based on the lengths of the inputs. */
- /* srcB is always made to slide across srcA. */
- /* So srcBLen is always considered as shorter or equal to srcALen */
- /* But CORR(x, y) is reverse of CORR(y, x) */
- /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
- /* and a varaible, inv is set to 1 */
- /* If lengths are not equal then zero pad has to be done to make the two
- * inputs of same length. But to improve the performance, we include zeroes
- * in the output instead of zero padding either of the the inputs*/
- /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * starting of the output buffer */
- /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
- * ending of the output buffer */
- /* Once the zero padding is done the remaining of the output is calcualted
- * using convolution but with the shorter signal time shifted. */
-
- /* Calculate the length of the remaining sequence */
- tot = ((srcALen + srcBLen) - 2u);
-
- if (srcALen > srcBLen)
- {
- /* Calculating the number of zeros to be padded to the output */
- j = srcALen - srcBLen;
-
- /* Initialise the pointer after zero padding */
- pDst += j;
- }
-
- else if (srcALen < srcBLen)
- {
- /* Initialization to inputB pointer */
- pIn1 = pSrcB;
-
- /* Initialization to the end of inputA pointer */
- pIn2 = pSrcA + (srcALen - 1u);
-
- /* Initialisation of the pointer after zero padding */
- pDst = pDst + tot;
-
- /* Swapping the lengths */
- j = srcALen;
- srcALen = srcBLen;
- srcBLen = j;
-
- /* Setting the reverse flag */
- inv = 1;
-
- }
-
- /* Loop to calculate convolution for output length number of times */
- for (i = 0u; i <= tot; i++)
- {
- /* Initialize sum with zero to carry on MAC operations */
- sum = 0;
-
- /* Loop to perform MAC operations according to convolution equation */
- for (j = 0u; j <= i; j++)
- {
- /* Check the array limitations */
- if ((((i - j) < srcBLen) && (j < srcALen)))
- {
- /* z[i] += x[i-j] * y[j] */
- sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
- }
- }
- /* Store the output in the destination buffer */
- if (inv == 1)
- *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
- else
- *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of Corr group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
deleted file mode 100644
index 57eb35b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
+++ /dev/null
@@ -1,512 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_f32.c
- * Description: FIR decimation for floating-point sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
- *
- * These functions combine an FIR filter together with a decimator.
- * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
- * Conceptually, the functions are equivalent to the block diagram below:
- * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
- * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized
- * cutoff frequency of 1/M in order to prevent aliasing distortion.
- * The user of the function is responsible for providing the filter coefficients.
- *
- * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
- * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the
- * samples output by the decimator are computed.
- * The functions operate on blocks of input and output data.
- * pSrc points to an array of blockSize input values and
- * pDst points to an array of blockSize/M output values.
- * In order to have an integer number of output samples blockSize
- * must always be a multiple of the decimation factor M.
- *
- * The library provides separate functions for Q15, Q31 and floating-point data types.
- *
- * \par Algorithm:
- * The FIR portion of the algorithm uses the standard form filter:
- *
- * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
- *
- * where, b[n] are the filter coefficients.
- * \par
- * The pCoeffs points to a coefficient array of size numTaps.
- * Coefficients are stored in time reversed order.
- * \par
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to a state array of size numTaps + blockSize - 1.
- * Samples in the state buffer are stored in the order:
- * \par
- *
- * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
- *
- * The state variables are updated after each block of data is processed, the coefficients are untouched.
- *
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * - Checks to make sure that the size of the input is a multiple of the decimation factor.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * The code below statically initializes each of the 3 different data type filter instance structures
- *
- *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
- *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
- *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
- *
- * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;
- * pCoeffs is the address of the coefficient buffer;
- * pState is the address of the state buffer.
- * Be sure to set the values in the state buffer to zeros when doing static initialization.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
-void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- float32_t sum0; /* Accumulator */
- float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-#if defined (ARM_MATH_DSP)
-
- uint32_t blkCntN4;
- float32_t *px0, *px1, *px2, *px3;
- float32_t acc0, acc1, acc2, acc3;
- float32_t x1, x2, x3;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize / 4;
- blkCntN4 = outBlockSize - (4 * blkCnt);
-
- while (blkCnt > 0u)
- {
- /* Copy 4 * decimation factor number of new input samples into the state buffer */
- i = 4 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
-
- /* Initialize state pointer for all the samples */
- px0 = pState;
- px1 = pState + S->M;
- px2 = pState + 2 * S->M;
- px3 = pState + 3 * S->M;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
-
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-1] sample for acc0 */
- x0 = *(px0++);
- /* Read x[n-numTaps-1] sample for acc1 */
- x1 = *(px1++);
- /* Read x[n-numTaps-1] sample for acc2 */
- x2 = *(px2++);
- /* Read x[n-numTaps-1] sample for acc3 */
- x3 = *(px3++);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
- x0 = *(px0++);
- x1 = *(px1++);
- x2 = *(px2++);
- x3 = *(px3++);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
- x0 = *(px0++);
- x1 = *(px1++);
- x2 = *(px2++);
- x3 = *(px3++);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
- x0 = *(px0++);
- x1 = *(px1++);
- x2 = *(px2++);
- x3 = *(px3++);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch state variables for acc0, acc1, acc2, acc3 */
- x0 = *(px0++);
- x1 = *(px1++);
- x2 = *(px2++);
- x3 = *(px3++);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + 4 * S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = acc0;
- *pDst++ = acc1;
- *pDst++ = acc2;
- *pDst++ = acc3;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- while (blkCntN4 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- sum0 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-1] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-2] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = sum0;
-
- /* Decrement the loop counter */
- blkCntN4--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- sum0 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = sum0;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Copy numTaps number of values */
- i = (numTaps - 1u);
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
deleted file mode 100644
index 2270a3f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
+++ /dev/null
@@ -1,586 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_fast_q15.c
- * Description: Fast Q15 FIR Decimator
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, state buffers should be aligned by 32-bit
- *
- * Scaling and Overflow Behavior:
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around and distorts the result.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
- *
- * \par
- * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
- * Both the slow and the fast versions use the same instance structure.
- * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer coefficient buffer */
- q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
- q31_t sum0; /* Accumulators */
- q31_t acc0, acc1;
- q15_t *px0, *px1;
- uint32_t blkCntN3;
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize / 2;
- blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = 2 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- px0 = pState;
-
- px1 = pState + S->M;
-
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
- x0 = *__SIMD32(px0)++;
-
- x1 = *__SIMD32(px1)++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLAD(x0, c0, acc0);
-
- acc1 = __SMLAD(x1, c0, acc1);
-
- /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
- x0 = *__SIMD32(px0)++;
-
- x1 = *__SIMD32(px1)++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLAD(x0, c0, acc0);
-
- acc1 = __SMLAD(x1, c0, acc1);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px0++;
-
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLAD(x0, c0, acc0);
- acc1 = __SMLAD(x1, c0, acc1);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M * 2;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
- *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-
- while (blkCntN3 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /*Set sum to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
- x0 = *__SIMD32(px)++;
-
- /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
- c1 = *__SIMD32(pb)++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLAD(x0, c0, sum0);
-
- /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
- x0 = *__SIMD32(px)++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLAD(x0, c1, sum0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLAD(x0, c0, sum0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCntN3--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-#else
-
-
-void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer coefficient buffer */
- q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
- q31_t sum0; /* Accumulators */
- q31_t acc0, acc1;
- q15_t *px0, *px1;
- uint32_t blkCntN3;
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize / 2;
- blkCntN3 = outBlockSize - (2 * blkCnt);
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = 2 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- px0 = pState;
-
- px1 = pState + S->M;
-
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-2] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-3] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-4] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M * 2;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
-
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
- *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- while (blkCntN3 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /*Set sum to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-1] and sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-2] and sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-3] sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-4] sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCntN3--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
deleted file mode 100644
index 58f1c04..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_fast_q31.c
- * Description: Fast Q31 FIR Decimator
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
- * These intermediate results are added to a 2.30 accumulator.
- * Finally, the accumulator is saturated and converted to a 1.31 result.
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
- *
- * \par
- * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
- * Both the slow and the fast versions use the same instance structure.
- * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.
- */
-
-void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
- q31_t *px; /* Temporary pointers for state buffer */
- q31_t *pb; /* Temporary pointers for coefficient buffer */
- q31_t sum0; /* Accumulator */
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
- uint32_t blkCntN2;
- q31_t x1;
- q31_t acc0, acc1;
- q31_t *px0, *px1;
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
-
- blkCnt = outBlockSize / 2;
- blkCntN2 = outBlockSize - (2 * blkCnt);
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = 2 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- px0 = pState;
- px1 = pState + S->M;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb);
-
- /* Read x[n-numTaps-1] for sample 0 sample 1 */
- x0 = *(px0);
- x1 = *(px1);
-
- /* Perform the multiply-accumulate */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb + 1u);
-
- /* Read x[n-numTaps-2] for sample 0 sample 1 */
- x0 = *(px0 + 1u);
- x1 = *(px1 + 1u);
-
- /* Perform the multiply-accumulate */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb + 2u);
-
- /* Read x[n-numTaps-3] for sample 0 sample 1 */
- x0 = *(px0 + 2u);
- x1 = *(px1 + 2u);
- pb += 4u;
-
- /* Perform the multiply-accumulate */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb - 1u);
-
- /* Read x[n-numTaps-4] for sample 0 sample 1 */
- x0 = *(px0 + 3u);
- x1 = *(px1 + 3u);
-
-
- /* Perform the multiply-accumulate */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* update state pointers */
- px0 += 4u;
- px1 += 4u;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x0 = *(px0++);
- x1 = *(px1++);
-
- /* Perform the multiply-accumulate */
- acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
- acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M * 2;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (acc0 << 1);
- *pDst++ = (q31_t) (acc1 << 1);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- while (blkCntN2 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-1] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-2] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (sum0 << 1);
-
- /* Decrement the loop counter */
- blkCntN2--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
deleted file mode 100644
index c1fc0f2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_init_f32.c
- * Description: Floating-point FIR Decimator initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().
- * M is the decimation factor.
- */
-
-arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
- /* The size of the input block must be a multiple of the decimation factor */
- if ((blockSize % M) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Decimation Factor */
- S->M = M;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
deleted file mode 100644
index f920175..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_init_q15.c
- * Description: Initialization function for the Q15 FIR Decimator
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples
- * to the call arm_fir_decimate_q15().
- * M is the decimation factor.
- */
-
-arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize)
-{
-
- arm_status status;
-
- /* The size of the input block must be a multiple of the decimation factor */
- if ((blockSize % M) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear the state buffer. The size of buffer is always (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Decimation factor */
- S->M = M;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
deleted file mode 100644
index 0490b3f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_init_q31.c
- * Description: Initialization function for Q31 FIR Decimation filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().
- * M is the decimation factor.
- */
-
-arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
- /* The size of the input block must be a multiple of the decimation factor */
- if ((blockSize % M) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Decimation factor */
- S->M = M;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
deleted file mode 100644
index fa472b4..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
+++ /dev/null
@@ -1,684 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_q15.c
- * Description: Q15 FIR Decimator
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the location where the output result is written.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- *
- * \par
- * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- */
-
-#if defined (ARM_MATH_DSP)
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer coefficient buffer */
- q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
- q63_t sum0; /* Accumulators */
- q63_t acc0, acc1;
- q15_t *px0, *px1;
- uint32_t blkCntN3;
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize / 2;
- blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = 2 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- px0 = pState;
-
- px1 = pState + S->M;
-
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
- x0 = *__SIMD32(px0)++;
-
- x1 = *__SIMD32(px1)++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLALD(x0, c0, acc0);
-
- acc1 = __SMLALD(x1, c0, acc1);
-
- /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
- x0 = *__SIMD32(px0)++;
-
- x1 = *__SIMD32(px1)++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLALD(x0, c0, acc0);
-
- acc1 = __SMLALD(x1, c0, acc1);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px0++;
-
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 = __SMLALD(x0, c0, acc0);
- acc1 = __SMLALD(x1, c0, acc1);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M * 2;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
- *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-
- while (blkCntN3 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /*Set sum to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
- x0 = *__SIMD32(px)++;
-
- /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
- c1 = *__SIMD32(pb)++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLALD(x0, c0, sum0);
-
- /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
- x0 = *__SIMD32(px)++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLALD(x0, c1, sum0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 = __SMLALD(x0, c0, sum0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCntN3--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-#else
-
-
-void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer coefficient buffer */
- q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
- q63_t sum0; /* Accumulators */
- q63_t acc0, acc1;
- q15_t *px0, *px1;
- uint32_t blkCntN3;
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize / 2;
- blkCntN3 = outBlockSize - (2 * blkCnt);
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = 2 * S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- px0 = pState;
-
- px1 = pState + S->M;
-
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-2] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-3] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-4] for sample 0 and sample 1 */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px0++;
- x1 = *px1++;
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M * 2;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
-
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
- *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- while (blkCntN3 > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /*Set sum to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the Read b[numTaps-1] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-1] and sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-2] and sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *pb++;
-
- /* Read x[n-numTaps-3] sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *pb++;
-
- /* Read x[n-numTaps-4] sample */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* Store filter output, smlad returns the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCntN3--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#else
-
-
-void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer coefficient buffer */
- q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
- q63_t sum0; /* Accumulators */
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
-
-/* Run the below code for Cortex-M0 */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /*Set sum to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += (q31_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /*Store filter output , smlad will return the values in 2.14 format */
- /* so downsacle by 15 to get output in 1.15 */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = numTaps - 1u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-
-}
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
deleted file mode 100644
index 4e4d4d1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_decimate_q31.c
- * Description: Q31 FIR Decimator
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_decimate
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- *
- * \par
- * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- */
-
-void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
- q31_t *px; /* Temporary pointers for state buffer */
- q31_t *pb; /* Temporary pointers for coefficient buffer */
- q63_t sum0; /* Accumulator */
- uint32_t numTaps = S->numTaps; /* Number of taps */
- uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-1] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-2] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (sum0 >> 31);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = (numTaps - 1u) % 0x04u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Total number of output samples to be computed */
- blkCnt = outBlockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy decimation factor number of new input samples into the state buffer */
- i = S->M;
-
- do
- {
- *pStateCurnt++ = *pSrc++;
-
- } while (--i);
-
- /* Set accumulator to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = pCoeffs;
-
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *pb++;
-
- /* Fetch 1 state variable */
- x0 = *px++;
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by the decimation factor
- * to process the next group of decimation factor number samples */
- pState = pState + S->M;
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (sum0 >> 31);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = numTaps - 1u;
-
- /* copy data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_decimate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c
deleted file mode 100644
index 34c1902..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c
+++ /dev/null
@@ -1,985 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_f32.c
- * Description: Floating-point FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
-* @ingroup groupFilters
-*/
-
-/**
-* @defgroup FIR Finite Impulse Response (FIR) Filters
-*
-* This set of functions implements Finite Impulse Response (FIR) filters
-* for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided.
-* The functions operate on blocks of input and output data and each call to the function processes
-* blockSize samples through the filter. pSrc and
-* pDst points to input and output arrays containing blockSize values.
-*
-* \par Algorithm:
-* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.
-* Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].
-*
-* y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
-*
-* \par
-* \image html FIR.gif "Finite Impulse Response filter"
-* \par
-* pCoeffs points to a coefficient array of size numTaps.
-* Coefficients are stored in time reversed order.
-* \par
-*
-* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
-*
-* \par
-* pState points to a state array of size numTaps + blockSize - 1.
-* Samples in the state buffer are stored in the following order.
-* \par
-*
-* {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
-*
-* \par
-* Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.
-* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,
-* to be avoided and yields a significant speed improvement.
-* The state variables are updated after each block of data is processed; the coefficients are untouched.
-* \par Instance Structure
-* The coefficients and state variables for a filter are stored together in an instance data structure.
-* A separate instance structure must be defined for each filter.
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
-* There are separate instance structure declarations for each of the 4 supported data types.
-*
-* \par Initialization Functions
-* There is also an associated initialization function for each data type.
-* The initialization function performs the following operations:
-* - Sets the values of the internal structure fields.
-* - Zeros out the values in the state buffer.
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
-*
-* \par
-* Use of the initialization function is optional.
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
-* To place an instance structure into a const data section, the instance structure must be manually initialized.
-* Set the values in the state buffer to zeros before static initialization.
-* The code below statically initializes each of the 4 different data type filter instance structures
-*
-*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
-*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
-*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
-*arm_fir_instance_q7 S = {numTaps, pState, pCoeffs};
-*
-*
-* where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
-* pCoeffs is the address of the coefficient buffer.
-*
-* \par Fixed-Point Behavior
-* Care must be taken when using the fixed-point versions of the FIR filter functions.
-* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-* Refer to the function specific documentation below for usage guidelines.
-*/
-
-/**
-* @addtogroup FIR
-* @{
-*/
-
-/**
-*
-* @param[in] *S points to an instance of the floating-point FIR filter structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[out] *pDst points to the block of output data.
-* @param[in] blockSize number of samples to process per call.
-* @return none.
-*
-*/
-
-#if defined(ARM_MATH_CM7)
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
- float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 8 output values simultaneously.
- * The variables acc0 ... acc7 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
- blkCnt = blockSize >> 3;
-
- /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
- ** a second loop below computes the remaining 1 to 7 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Set all accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
- acc4 = 0.0f;
- acc5 = 0.0f;
- acc6 = 0.0f;
- acc7 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* This is separated from the others to avoid
- * a call to __aeabi_memmove which would be slower
- */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
- x0 = *px++;
- x1 = *px++;
- x2 = *px++;
- x3 = *px++;
- x4 = *px++;
- x5 = *px++;
- x6 = *px++;
-
- /* Loop unrolling. Process 8 taps at a time. */
- tapCnt = numTaps >> 3u;
-
- /* Loop over the number of taps. Unroll by a factor of 8.
- ** Repeat until we've computed numTaps-8 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample */
- x7 = *(px++);
-
- /* acc0 += b[numTaps-1] * x[n-numTaps] */
- acc0 += x0 * c0;
-
- /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
- acc1 += x1 * c0;
-
- /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
- acc2 += x2 * c0;
-
- /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
- acc3 += x3 * c0;
-
- /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
- acc4 += x4 * c0;
-
- /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
- acc5 += x5 * c0;
-
- /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
- acc6 += x6 * c0;
-
- /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
- acc7 += x7 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px++);
-
- /* Perform the multiply-accumulate */
- acc0 += x1 * c0;
- acc1 += x2 * c0;
- acc2 += x3 * c0;
- acc3 += x4 * c0;
- acc4 += x5 * c0;
- acc5 += x6 * c0;
- acc6 += x7 * c0;
- acc7 += x0 * c0;
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-5] sample */
- x1 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x2 * c0;
- acc1 += x3 * c0;
- acc2 += x4 * c0;
- acc3 += x5 * c0;
- acc4 += x6 * c0;
- acc5 += x7 * c0;
- acc6 += x0 * c0;
- acc7 += x1 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x3 * c0;
- acc1 += x4 * c0;
- acc2 += x5 * c0;
- acc3 += x6 * c0;
- acc4 += x7 * c0;
- acc5 += x0 * c0;
- acc6 += x1 * c0;
- acc7 += x2 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x3 = *(px++);
- /* Perform the multiply-accumulates */
- acc0 += x4 * c0;
- acc1 += x5 * c0;
- acc2 += x6 * c0;
- acc3 += x7 * c0;
- acc4 += x0 * c0;
- acc5 += x1 * c0;
- acc6 += x2 * c0;
- acc7 += x3 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x4 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x5 * c0;
- acc1 += x6 * c0;
- acc2 += x7 * c0;
- acc3 += x0 * c0;
- acc4 += x1 * c0;
- acc5 += x2 * c0;
- acc6 += x3 * c0;
- acc7 += x4 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x5 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x6 * c0;
- acc1 += x7 * c0;
- acc2 += x0 * c0;
- acc3 += x1 * c0;
- acc4 += x2 * c0;
- acc5 += x3 * c0;
- acc6 += x4 * c0;
- acc7 += x5 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x6 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x7 * c0;
- acc1 += x0 * c0;
- acc2 += x1 * c0;
- acc3 += x2 * c0;
- acc4 += x3 * c0;
- acc5 += x4 * c0;
- acc6 += x5 * c0;
- acc7 += x6 * c0;
-
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 8, compute the remaining filter taps */
- tapCnt = numTaps % 0x8u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x7 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
- acc4 += x4 * c0;
- acc5 += x5 * c0;
- acc6 += x6 * c0;
- acc7 += x7 * c0;
-
- /* Reuse the present sample states for next sample */
- x0 = x1;
- x1 = x2;
- x2 = x3;
- x3 = x4;
- x4 = x5;
- x5 = x6;
- x6 = x7;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by 8 to process the next group of 8 samples */
- pState = pState + 8;
-
- /* The results in the 8 accumulators, store in the destination buffer. */
- *pDst++ = acc0;
- *pDst++ = acc1;
- *pDst++ = acc2;
- *pDst++ = acc3;
- *pDst++ = acc4;
- *pDst++ = acc5;
- *pDst++ = acc6;
- *pDst++ = acc7;
-
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x8u;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = (pCoeffs);
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- acc0 += *px++ * *pb++;
- i--;
-
- } while (i > 0u);
-
- /* The result is store in the destination buffer. */
- *pDst++ = acc0;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-#elif defined(ARM_MATH_CM0_FAMILY)
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
-
- /* Run the below code for Cortex-M0 */
-
- float32_t acc;
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Initialize blkCnt with blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = pCoeffs;
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
- acc += *px++ * *pb++;
- i--;
-
- } while (i > 0u);
-
- /* The result is store in the destination buffer. */
- *pDst++ = acc;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Copy numTaps number of values */
- tapCnt = numTaps - 1u;
-
- /* Copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-#else
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
- float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
- float32_t p0,p1,p2,p3,p4,p5,p6,p7; /* Temporary product values */
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 8 output values simultaneously.
- * The variables acc0 ... acc7 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
- blkCnt = blockSize >> 3;
-
- /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
- ** a second loop below computes the remaining 1 to 7 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Set all accumulators to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
- acc4 = 0.0f;
- acc5 = 0.0f;
- acc6 = 0.0f;
- acc7 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* This is separated from the others to avoid
- * a call to __aeabi_memmove which would be slower
- */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
- x0 = *px++;
- x1 = *px++;
- x2 = *px++;
- x3 = *px++;
- x4 = *px++;
- x5 = *px++;
- x6 = *px++;
-
- /* Loop unrolling. Process 8 taps at a time. */
- tapCnt = numTaps >> 3u;
-
- /* Loop over the number of taps. Unroll by a factor of 8.
- ** Repeat until we've computed numTaps-8 coefficients. */
- while (tapCnt > 0u)
- {
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-3] sample */
- x7 = *(px++);
-
- /* acc0 += b[numTaps-1] * x[n-numTaps] */
- p0 = x0 * c0;
-
- /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
- p1 = x1 * c0;
-
- /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
- p2 = x2 * c0;
-
- /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
- p3 = x3 * c0;
-
- /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
- p4 = x4 * c0;
-
- /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
- p5 = x5 * c0;
-
- /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
- p6 = x6 * c0;
-
- /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
- p7 = x7 * c0;
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
-
- /* Perform the multiply-accumulate */
- p0 = x1 * c0;
- p1 = x2 * c0;
- p2 = x3 * c0;
- p3 = x4 * c0;
- p4 = x5 * c0;
- p5 = x6 * c0;
- p6 = x7 * c0;
- p7 = x0 * c0;
-
- /* Read the b[numTaps-3] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-5] sample */
- x1 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x2 * c0;
- p1 = x3 * c0;
- p2 = x4 * c0;
- p3 = x5 * c0;
- p4 = x6 * c0;
- p5 = x7 * c0;
- p6 = x0 * c0;
- p7 = x1 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x2 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x3 * c0;
- p1 = x4 * c0;
- p2 = x5 * c0;
- p3 = x6 * c0;
- p4 = x7 * c0;
- p5 = x0 * c0;
- p6 = x1 * c0;
- p7 = x2 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x3 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x4 * c0;
- p1 = x5 * c0;
- p2 = x6 * c0;
- p3 = x7 * c0;
- p4 = x0 * c0;
- p5 = x1 * c0;
- p6 = x2 * c0;
- p7 = x3 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x4 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x5 * c0;
- p1 = x6 * c0;
- p2 = x7 * c0;
- p3 = x0 * c0;
- p4 = x1 * c0;
- p5 = x2 * c0;
- p6 = x3 * c0;
- p7 = x4 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x5 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x6 * c0;
- p1 = x7 * c0;
- p2 = x0 * c0;
- p3 = x1 * c0;
- p4 = x2 * c0;
- p5 = x3 * c0;
- p6 = x4 * c0;
- p7 = x5 * c0;
-
- /* Read the b[numTaps-4] coefficient */
- c0 = *(pb++);
-
- /* Read x[n-numTaps-6] sample */
- x6 = *(px++);
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Perform the multiply-accumulates */
- p0 = x7 * c0;
- p1 = x0 * c0;
- p2 = x1 * c0;
- p3 = x2 * c0;
- p4 = x3 * c0;
- p5 = x4 * c0;
- p6 = x5 * c0;
- p7 = x6 * c0;
-
- tapCnt--;
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
- }
-
- /* If the filter length is not a multiple of 8, compute the remaining filter taps */
- tapCnt = numTaps % 0x8u;
-
- while (tapCnt > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x7 = *(px++);
-
- /* Perform the multiply-accumulates */
- p0 = x0 * c0;
- p1 = x1 * c0;
- p2 = x2 * c0;
- p3 = x3 * c0;
- p4 = x4 * c0;
- p5 = x5 * c0;
- p6 = x6 * c0;
- p7 = x7 * c0;
-
- /* Reuse the present sample states for next sample */
- x0 = x1;
- x1 = x2;
- x2 = x3;
- x3 = x4;
- x4 = x5;
- x5 = x6;
- x6 = x7;
-
- acc0 += p0;
- acc1 += p1;
- acc2 += p2;
- acc3 += p3;
- acc4 += p4;
- acc5 += p5;
- acc6 += p6;
- acc7 += p7;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance the state pointer by 8 to process the next group of 8 samples */
- pState = pState + 8;
-
- /* The results in the 8 accumulators, store in the destination buffer. */
- *pDst++ = acc0;
- *pDst++ = acc1;
- *pDst++ = acc2;
- *pDst++ = acc3;
- *pDst++ = acc4;
- *pDst++ = acc5;
- *pDst++ = acc6;
- *pDst++ = acc7;
-
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x8u;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0.0f;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = (pCoeffs);
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- acc0 += *px++ * *pb++;
- i--;
-
- } while (i > 0u);
-
- /* The result is store in the destination buffer. */
- *pDst++ = acc0;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-#endif
-
-/**
-* @} end of FIR group
-*/
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
deleted file mode 100644
index f85bebd..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_fast_q15.c
- * Description: Q15 Fast FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @param[in] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * This fast version uses a 32-bit accumulator with 2.30 format.
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around and distorts the result.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
- *
- * \par
- * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
- * Use the function arm_fir_init_q15() to initialize the filter structure.
- */
-
-void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *pb; /* Temporary pointer for coefficient buffer */
- q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
- q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
- uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
-
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
-
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer.
- ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
- px = pState;
-
- /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
- pb = pCoeffs;
-
- /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
- x0 = *__SIMD32(px)++;
-
- /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
- x2 = *__SIMD32(px)++;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0)
- {
- /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
- acc0 = __SMLAD(x0, c0, acc0);
-
- /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
- acc2 = __SMLAD(x2, c0, acc2);
-
- /* pack x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* Read state x[n-N-4], x[n-N-5] */
- x0 = _SIMD32_OFFSET(px);
-
- /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- /* pack x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x0, x2, 0);
-#else
- x1 = __PKHBT(x2, x0, 0);
-#endif
-
- /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- /* Read coefficients b[N-2], b[N-3] */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
- acc0 = __SMLAD(x2, c0, acc0);
-
- /* Read state x[n-N-6], x[n-N-7] with offset */
- x2 = _SIMD32_OFFSET(px + 2u);
-
- /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
- acc2 = __SMLAD(x0, c0, acc2);
-
- /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
- acc1 = __SMLADX(x1, c0, acc1);
-
- /* pack x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
- acc3 = __SMLADX(x1, c0, acc3);
-
- /* Update state pointer for next state reading */
- px += 4u;
-
- /* Decrement tap count */
- tapCnt--;
-
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps.
- ** This is always be 2 taps since the filter length is even. */
- if ((numTaps & 0x3u) != 0u)
- {
-
- /* Read last two coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLAD(x0, c0, acc0);
- acc2 = __SMLAD(x2, c0, acc2);
-
- /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* Read last state variables */
- x0 = *__SIMD32(px);
-
- /* Perform the multiply-accumulates */
- acc1 = __SMLADX(x1, c0, acc1);
-
- /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x0, x2, 0);
-#else
- x1 = __PKHBT(x2, x0, 0);
-#endif
-
- /* Perform the multiply-accumulates */
- acc3 = __SMLADX(x1, c0, acc3);
- }
-
- /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
- while (blkCnt > 0u)
- {
- /* Copy two samples into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Use SIMD to hold states and coefficients */
- px = pState;
- pb = pCoeffs;
-
- tapCnt = numTaps >> 1u;
-
- do
- {
-
- acc0 += (q31_t) * px++ * *pb++;
- acc0 += (q31_t) * px++ * *pb++;
-
- tapCnt--;
- }
- while (tapCnt > 0u);
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Calculation of count for copying integer writes */
- tapCnt = (numTaps - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- tapCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* copy remaining data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
deleted file mode 100644
index d2d9dc9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_fast_q31.c
- * Description: Processing function for the Q31 Fast FIR filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @param[in] *S points to an instance of the Q31 structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- *
- * \par
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
- * These intermediate results are added to a 2.30 accumulator.
- * Finally, the accumulator is saturated and converted to a 1.31 result.
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
- *
- * \par
- * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure.
- * Use the function arm_fir_init_q31() to initialize the filter structure.
- */
-
-IAR_ONLY_LOW_OPTIMIZATION_ENTER
-void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t x0, x1, x2, x3; /* Temporary variables to hold state */
- q31_t c0; /* Temporary variable to hold coefficient value */
- q31_t *px; /* Temporary pointer for state */
- q31_t *pb; /* Temporary pointer for coefficient buffer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Read the first three samples from the state buffer:
- * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
- i = tapCnt;
-
- while (i > 0u)
- {
- /* Read the b[numTaps] coefficient */
- c0 = *pb;
-
- /* Read x[n-numTaps-3] sample */
- x3 = *px;
-
- /* acc0 += b[numTaps] * x[n-numTaps] */
- multAcc_32x32_keep32_R(acc0, x0, c0);
-
- /* acc1 += b[numTaps] * x[n-numTaps-1] */
- multAcc_32x32_keep32_R(acc1, x1, c0);
-
- /* acc2 += b[numTaps] * x[n-numTaps-2] */
- multAcc_32x32_keep32_R(acc2, x2, c0);
-
- /* acc3 += b[numTaps] * x[n-numTaps-3] */
- multAcc_32x32_keep32_R(acc3, x3, c0);
-
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb + 1u);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulates */
- multAcc_32x32_keep32_R(acc0, x1, c0);
- multAcc_32x32_keep32_R(acc1, x2, c0);
- multAcc_32x32_keep32_R(acc2, x3, c0);
- multAcc_32x32_keep32_R(acc3, x0, c0);
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb + 2u);
-
- /* Read x[n-numTaps-5] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- multAcc_32x32_keep32_R(acc0, x2, c0);
- multAcc_32x32_keep32_R(acc1, x3, c0);
- multAcc_32x32_keep32_R(acc2, x0, c0);
- multAcc_32x32_keep32_R(acc3, x1, c0);
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *(pb + 3u);
-
- /* Read x[n-numTaps-6] sample */
- x2 = *(px + 3u);
-
- /* Perform the multiply-accumulates */
- multAcc_32x32_keep32_R(acc0, x3, c0);
- multAcc_32x32_keep32_R(acc1, x0, c0);
- multAcc_32x32_keep32_R(acc2, x1, c0);
- multAcc_32x32_keep32_R(acc3, x2, c0);
-
- /* update coefficient pointer */
- pb += 4u;
- px += 4u;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
- i = numTaps - (tapCnt * 4u);
- while (i > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- multAcc_32x32_keep32_R(acc0, x0, c0);
- multAcc_32x32_keep32_R(acc1, x1, c0);
- multAcc_32x32_keep32_R(acc2, x2, c0);
- multAcc_32x32_keep32_R(acc3, x3, c0);
-
- /* Reuse the present sample states for next sample */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 4;
-
- /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31
- ** Then store the 4 outputs in the destination buffer. */
- *pDst++ = (q31_t) (acc0 << 1);
- *pDst++ = (q31_t) (acc1 << 1);
- *pDst++ = (q31_t) (acc2 << 1);
- *pDst++ = (q31_t) (acc3 << 1);
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 4u;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = (pCoeffs);
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
- i--;
- } while (i > 0u);
-
- /* The result is in 2.30 format. Convert to 1.31
- ** Then store the output in the destination buffer. */
- *pDst++ = (q31_t) (acc0 << 1);
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u);
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-}
-IAR_ONLY_LOW_OPTIMIZATION_EXIT
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c
deleted file mode 100644
index efb4388..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_init_f32.c
- * Description: Floating-point FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @details
- *
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed per call.
- * @return none.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().
- */
-
-void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c
deleted file mode 100644
index e5a8507..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_init_q15.c
- * Description: Q15 FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] *pCoeffs points to the filter coefficients buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize is number of samples processed per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if
- * numTaps is not greater than or equal to 4 and even.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * Note that numTaps must be even and greater than or equal to 4.
- * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.
- * For example, to implement a filter with numTaps=3 and coefficients
- *
- * {0.3, -0.8, 0.3}
- *
- * set numTaps=4 and use the coefficients:
- *
- * {0.3, -0.8, 0.3, 0}.
- *
- * Similarly, to implement a two point filter
- *
- * {0.3, -0.3}
- *
- * set numTaps=4 and use the coefficients:
- *
- * {0.3, -0.3, 0, 0}.
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().
- */
-
-arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* The Number of filter coefficients in the filter must be even and at least 4 */
- if (numTaps & 0x1u)
- {
- status = ARM_MATH_ARGUMENT_ERROR;
- }
- else
- {
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear the state buffer. The size is always (blockSize + numTaps ) */
- memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- status = ARM_MATH_SUCCESS;
-
- return (status);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c
deleted file mode 100644
index bd31ea9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_init_q31.c
- * Description: Q31 FIR filter initialization function.
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @details
- *
- * @param[in,out] *S points to an instance of the Q31 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed per call.
- * @return none.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().
- */
-
-void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
- memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
deleted file mode 100644
index 7da3da3..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_init_q7.c
- * Description: Q7 FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-/**
- * @param[in,out] *S points to an instance of the Q7 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed per call.
- * @return none
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to the array of state variables.
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().
- */
-
-void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize)
-{
-
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
deleted file mode 100644
index 2a3828a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_f32.c
- * Description: Floating-point FIR interpolation sequences
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
- *
- * These functions combine an upsampler (zero stuffer) and an FIR filter.
- * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
- * Conceptually, the functions are equivalent to the block diagram below:
- * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
- * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized
- * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.
- * The user of the function is responsible for providing the filter coefficients.
- *
- * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
- * The upsampler inserts L-1 zeros between each sample.
- * Instead of multiplying by these zero values, the FIR filter is designed to skip them.
- * This leads to an efficient implementation without any wasted effort.
- * The functions operate on blocks of input and output data.
- * pSrc points to an array of blockSize input values and
- * pDst points to an array of blockSize*L output values.
- *
- * The library provides separate functions for Q15, Q31, and floating-point data types.
- *
- * \par Algorithm:
- * The functions use a polyphase filter structure:
- *
- * y[n] = b[0] * x[n] + b[L] * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
- * y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
- * ...
- * y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
- *
- * This approach is more efficient than straightforward upsample-then-filter algorithms.
- * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.
- * \par
- * pCoeffs points to a coefficient array of size numTaps.
- * numTaps must be a multiple of the interpolation factor L and this is checked by the
- * initialization functions.
- * Internally, the function divides the FIR filter's impulse response into shorter filters of length
- * phaseLength=numTaps/L.
- * Coefficients are stored in time reversed order.
- * \par
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to a state array of size blockSize + phaseLength - 1.
- * Samples in the state buffer are stored in the order:
- * \par
- *
- * {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
- *
- * The state variables are updated after each block of data is processed, the coefficients are untouched.
- *
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * The code below statically initializes each of the 3 different data type filter instance structures
- *
- * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
- * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
- * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
- *
- * where L is the interpolation factor; phaseLength=numTaps/L is the
- * length of each of the shorter FIR filters used internally,
- * pCoeffs is the address of the coefficient buffer;
- * pState is the address of the state buffer.
- * Be sure to set the values in the state buffer to zeros when doing static initialization.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-/**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
- float32_t sum0; /* Accumulators */
- float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t i, blkCnt, j; /* Loop counters */
- uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
- float32_t acc0, acc1, acc2, acc3;
- float32_t x1, x2, x3;
- uint32_t blkCntN4;
- float32_t c1, c2, c3;
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (phaseLen - 1u);
-
- /* Initialise blkCnt */
- blkCnt = blockSize / 4;
- blkCntN4 = blockSize - (4 * blkCnt);
-
- /* Samples loop unrolled by 4 */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = (S->L);
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- acc0 = 0.0f;
- acc1 = 0.0f;
- acc2 = 0.0f;
- acc3 = 0.0f;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2u;
-
- x0 = *(ptr1++);
- x1 = *(ptr1++);
- x2 = *(ptr1++);
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x3 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Read the coefficient */
- c1 = *(ptr2 + S->L);
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += x1 * c1;
- acc1 += x2 * c1;
- acc2 += x3 * c1;
- acc3 += x0 * c1;
-
- /* Read the coefficient */
- c2 = *(ptr2 + S->L * 2);
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += x2 * c2;
- acc1 += x3 * c2;
- acc2 += x0 * c2;
- acc3 += x1 * c2;
-
- /* Read the coefficient */
- c3 = *(ptr2 + S->L * 3);
-
- /* Read the input sample */
- x2 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += x3 * c3;
- acc1 += x0 * c3;
- acc2 += x1 * c3;
- acc3 += x2 * c3;
-
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += 4 * S->L;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen % 0x4u;
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x3 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += x0 * c0;
- acc1 += x1 * c0;
- acc2 += x2 * c0;
- acc3 += x3 * c0;
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* update states for next sample processing */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst = acc0;
- *(pDst + S->L) = acc1;
- *(pDst + 2 * S->L) = acc2;
- *(pDst + 3 * S->L) = acc3;
-
- pDst++;
-
- /* Increment the address modifier index of coefficient buffer */
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 4;
-
- pDst += S->L * 3;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
-
- while (blkCntN4 > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum0 = 0.0f;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2u;
- while (tapCnt > 0u)
- {
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += x0 * c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum0 += *(ptr1++) * (*ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = sum0;
-
- /* Increment the address modifier index of coefficient buffer */
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCntN4--;
- }
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (phaseLen - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (phaseLen - 1u) % 0x04u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
-
-
- float32_t sum; /* Accumulator */
- uint32_t i, blkCnt; /* Loop counters */
- uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
-
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (phaseLen - 1u);
-
- /* Total number of intput samples */
- blkCnt = blockSize;
-
- /* Loop over the blockSize. */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum = 0.0f;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (i - 1u);
-
- /* Loop over the polyPhase length */
- tapCnt = phaseLen;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += *ptr1++ * *ptr2;
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = sum;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = phaseLen - 1u;
-
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
deleted file mode 100644
index 77dcdaa..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_init_f32.c
- * Description: Floating-point FIR interpolator initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
- *
- * The length of the filter numTaps must be a multiple of the interpolation factor L.
- * \par
- * pState points to the array of state variables.
- * pState is of length (numTaps/L)+blockSize-1 words
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().
- */
-
-arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
- /* The filter length must be a multiple of the interpolation factor */
- if ((numTaps % L) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign Interpolation factor */
- S->L = L;
-
- /* Assign polyPhaseLength */
- S->phaseLength = numTaps / L;
-
- /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
- memset(pState, 0,
- (blockSize +
- ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
deleted file mode 100644
index 17e0c1f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_init_q15.c
- * Description: Q15 FIR interpolator initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-/**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
- *
- * The length of the filter numTaps must be a multiple of the interpolation factor L.
- * \par
- * pState points to the array of state variables.
- * pState is of length (numTaps/L)+blockSize-1 words
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().
- */
-
-arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
- /* The filter length must be a multiple of the interpolation factor */
- if ((numTaps % L) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign Interpolation factor */
- S->L = L;
-
- /* Assign polyPhaseLength */
- S->phaseLength = numTaps / L;
-
- /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
- memset(pState, 0,
- (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
deleted file mode 100644
index 94e1bd2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_init_q31.c
- * Description: Q31 FIR interpolator initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-
-/**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
- *
- * The length of the filter numTaps must be a multiple of the interpolation factor L.
- * \par
- * pState points to the array of state variables.
- * pState is of length (numTaps/L)+blockSize-1 words
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().
- */
-
-arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize)
-{
- arm_status status;
-
- /* The filter length must be a multiple of the interpolation factor */
- if ((numTaps % L) != 0u)
- {
- /* Set status as ARM_MATH_LENGTH_ERROR */
- status = ARM_MATH_LENGTH_ERROR;
- }
- else
- {
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign Interpolation factor */
- S->L = L;
-
- /* Assign polyPhaseLength */
- S->phaseLength = numTaps / L;
-
- /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
- memset(pState, 0,
- (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- status = ARM_MATH_SUCCESS;
- }
-
- return (status);
-
-}
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
deleted file mode 100644
index 0a87df8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_q15.c
- * Description: Q15 FIR interpolation
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
- q63_t sum0; /* Accumulators */
- q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t i, blkCnt, j, tapCnt; /* Loop counters */
- uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
- uint32_t blkCntN2;
- q63_t acc0, acc1;
- q15_t x1;
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
- /* Initialise blkCnt */
- blkCnt = blockSize / 2;
- blkCntN2 = blockSize - (2 * blkCnt);
-
- /* Samples loop unrolled by 2 */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = (S->L);
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2u;
-
- x0 = *(ptr1++);
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L);
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x1 *c0;
- acc1 += (q63_t) x0 *c0;
-
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L * 2);
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L * 3);
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x1 *c0;
- acc1 += (q63_t) x0 *c0;
-
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += 4 * S->L;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen % 0x4u;
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* update states for next sample processing */
- x0 = x1;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
- *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
-
- pDst++;
-
- /* Increment the address modifier index of coefficient buffer */
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 2;
-
- pDst += S->L;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blkCntN2;
-
- /* Loop over the blockSize. */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2;
- while (tapCnt > 0u)
- {
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen & 0x3u;
-
- while (tapCnt > 0u)
- {
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = ((uint32_t) phaseLen - 1u) >> 2u;
-
- /* copy data */
- while (i > 0u)
- {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- i--;
- }
-
- i = ((uint32_t) phaseLen - 1u) % 0x04u;
-
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-}
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
- q63_t sum; /* Accumulator */
- q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t i, blkCnt, tapCnt; /* Loop counters */
- uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
-
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (phaseLen - 1u);
-
- /* Total number of intput samples */
- blkCnt = blockSize;
-
- /* Loop over the blockSize. */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (i - 1u);
-
- /* Loop over the polyPhase length */
- tapCnt = (uint32_t) phaseLen;
-
- while (tapCnt > 0u)
- {
- /* Read the coefficient */
- c0 = *ptr2;
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *ptr1++;
-
- /* Perform the multiply-accumulate */
- sum += ((q31_t) x0 * c0);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Store the result after converting to 1.15 format in the destination buffer */
- *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- i = (uint32_t) phaseLen - 1u;
-
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
deleted file mode 100644
index aa9801e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_interpolate_q31.c
- * Description: Q31 FIR interpolation
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Interpolate
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] *S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).
- * since numTaps/L additions occur per output sample.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
- q63_t sum0; /* Accumulators */
- q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t i, blkCnt, j; /* Loop counters */
- uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
-
- uint32_t blkCntN2;
- q63_t acc0, acc1;
- q31_t x1;
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
- /* Initialise blkCnt */
- blkCnt = blockSize / 2;
- blkCntN2 = blockSize - (2 * blkCnt);
-
- /* Samples loop unrolled by 2 */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = (S->L);
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- acc0 = 0;
- acc1 = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2u;
-
- x0 = *(ptr1++);
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L);
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x1 *c0;
- acc1 += (q63_t) x0 *c0;
-
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L * 2);
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2 + S->L * 3);
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x1 *c0;
- acc1 += (q63_t) x0 *c0;
-
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += 4 * S->L;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen % 0x4u;
-
- while (tapCnt > 0u)
- {
-
- /* Read the input sample */
- x1 = *(ptr1++);
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Perform the multiply-accumulate */
- acc0 += (q63_t) x0 *c0;
- acc1 += (q63_t) x1 *c0;
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* update states for next sample processing */
- x0 = x1;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst = (q31_t) (acc0 >> 31);
- *(pDst + S->L) = (q31_t) (acc1 >> 31);
-
-
- pDst++;
-
- /* Increment the address modifier index of coefficient buffer */
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 2;
-
- pDst += S->L;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blkCntN2;
-
- /* Loop over the blockSize. */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Address modifier index of coefficient buffer */
- j = 1u;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum0 = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (S->L - j);
-
- /* Loop over the polyPhase length. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
- tapCnt = phaseLen >> 2;
- while (tapCnt > 0u)
- {
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Upsampling is done by stuffing L-1 zeros between each sample.
- * So instead of multiplying zeros with coefficients,
- * Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = phaseLen & 0x3u;
-
- while (tapCnt > 0u)
- {
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *(ptr1++);
-
- /* Perform the multiply-accumulate */
- sum0 += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (sum0 >> 31);
-
- /* Increment the address modifier index of coefficient buffer */
- j++;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (phaseLen - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- tapCnt = (phaseLen - 1u) % 0x04u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-
-#else
-
-void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
-
- /* Run the below code for Cortex-M0 */
-
- q63_t sum; /* Accumulator */
- q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
- uint32_t i, blkCnt; /* Loop counters */
- uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
-
-
- /* S->pState buffer contains previous frame (phaseLen - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
- /* Total number of intput samples */
- blkCnt = blockSize;
-
- /* Loop over the blockSize. */
- while (blkCnt > 0u)
- {
- /* Copy new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Loop over the Interpolation factor. */
- i = S->L;
-
- while (i > 0u)
- {
- /* Set accumulator to zero */
- sum = 0;
-
- /* Initialize state pointer */
- ptr1 = pState;
-
- /* Initialize coefficient pointer */
- ptr2 = pCoeffs + (i - 1u);
-
- tapCnt = phaseLen;
-
- while (tapCnt > 0u)
- {
- /* Read the coefficient */
- c0 = *(ptr2);
-
- /* Increment the coefficient pointer by interpolation factor times. */
- ptr2 += S->L;
-
- /* Read the input sample */
- x0 = *ptr1++;
-
- /* Perform the multiply-accumulate */
- sum += (q63_t) x0 *c0;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is in the accumulator, store in the destination buffer. */
- *pDst++ = (q31_t) (sum >> 31);
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 1
- * to process the next group of interpolation factor number samples */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = phaseLen - 1u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /**
- * @} end of FIR_Interpolate group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
deleted file mode 100644
index 5ac8417..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_f32.c
- * Description: Processing function for the floating-point FIR Lattice filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
- *
- * This set of functions implements Finite Impulse Response (FIR) lattice filters
- * for Q15, Q31 and floating-point data types. Lattice filters are used in a
- * variety of adaptive filter applications. The filter structure is feedforward and
- * the net impulse response is finite length.
- * The functions operate on blocks
- * of input and output data and each call to the function processes
- * blockSize samples through the filter. pSrc and
- * pDst point to input and output arrays containing blockSize values.
- *
- * \par Algorithm:
- * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
- * The following difference equation is implemented:
- *
- * f0[n] = g0[n] = x[n]
- * fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
- * gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
- * y[n] = fM[n]
- *
- * \par
- * pCoeffs points to tha array of reflection coefficients of size numStages.
- * Reflection Coefficients are stored in the following order.
- * \par
- *
- * {k1, k2, ..., kM}
- *
- * where M is number of stages
- * \par
- * pState points to a state array of size numStages.
- * The state variables (g values) hold previous inputs and are stored in the following order.
- *
- * {g0[n], g1[n], g2[n] ...gM-1[n]}
- *
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
- *
- *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
- *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
- *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
- *
- * \par
- * where numStages is the number of stages in the filter; pState is the address of the state buffer;
- * pCoeffs is the address of the coefficient buffer.
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *px; /* temporary state pointer */
- float32_t *pk; /* temporary coefficient pointer */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t fcurr1, fnext1, gcurr1, gnext1; /* temporary variables for first sample in loop unrolling */
- float32_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
- float32_t fcurr3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
- float32_t fcurr4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
- uint32_t numStages = S->numStages; /* Number of stages in the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
-
- gcurr1 = 0.0f;
- pState = &S->pState[0];
-
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
- /* Read two samples from input buffer */
- /* f0(n) = x(n) */
- fcurr1 = *pSrc++;
- fcurr2 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* Read g0(n-1) from state */
- gcurr1 = *px;
-
- /* Process first sample for first tap */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (fcurr1 * (*pk)) + gcurr1;
-
- /* Process second sample for first tap */
- /* for sample 2 processing */
- fnext2 = fcurr2 + ((*pk) * fcurr1);
- gnext2 = (fcurr2 * (*pk)) + fcurr1;
-
- /* Read next two samples from input buffer */
- /* f0(n+2) = x(n+2) */
- fcurr3 = *pSrc++;
- fcurr4 = *pSrc++;
-
- /* Copy only last input samples into the state buffer
- which will be used for next four samples processing */
- *px++ = fcurr4;
-
- /* Process third sample for first tap */
- fnext3 = fcurr3 + ((*pk) * fcurr2);
- gnext3 = (fcurr3 * (*pk)) + fcurr2;
-
- /* Process fourth sample for first tap */
- fnext4 = fcurr4 + ((*pk) * fcurr3);
- gnext4 = (fcurr4 * (*pk++)) + fcurr3;
-
- /* Update of f values for next coefficient set processing */
- fcurr1 = fnext1;
- fcurr2 = fnext2;
- fcurr3 = fnext3;
- fcurr4 = fnext4;
-
- /* Loop unrolling. Process 4 taps at a time . */
- stageCnt = (numStages - 1u) >> 2u;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numStages-3 coefficients. */
-
- /* Process 2nd, 3rd, 4th and 5th taps ... here */
- while (stageCnt > 0u)
- {
- /* Read g1(n-1), g3(n-1) .... from state */
- gcurr1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext4;
-
- /* Process first sample for 2nd, 6th .. tap */
- /* Sample processing for K2, K6.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- /* Process second sample for 2nd, 6th .. tap */
- /* for sample 2 processing */
- fnext2 = fcurr2 + ((*pk) * gnext1);
- /* Process third sample for 2nd, 6th .. tap */
- fnext3 = fcurr3 + ((*pk) * gnext2);
- /* Process fourth sample for 2nd, 6th .. tap */
- fnext4 = fcurr4 + ((*pk) * gnext3);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- /* Calculation of state values for next stage */
- gnext4 = (fcurr4 * (*pk)) + gnext3;
- gnext3 = (fcurr3 * (*pk)) + gnext2;
- gnext2 = (fcurr2 * (*pk)) + gnext1;
- gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-
- /* Read g2(n-1), g4(n-1) .... from state */
- gcurr1 = *px;
-
- /* save g2(n) in state buffer */
- *px++ = gnext4;
-
- /* Sample processing for K3, K7.... */
- /* Process first sample for 3rd, 7th .. tap */
- /* f3(n) = f2(n) + K3 * g2(n-1) */
- fcurr1 = fnext1 + ((*pk) * gcurr1);
- /* Process second sample for 3rd, 7th .. tap */
- fcurr2 = fnext2 + ((*pk) * gnext1);
- /* Process third sample for 3rd, 7th .. tap */
- fcurr3 = fnext3 + ((*pk) * gnext2);
- /* Process fourth sample for 3rd, 7th .. tap */
- fcurr4 = fnext4 + ((*pk) * gnext3);
-
- /* Calculation of state values for next stage */
- /* g3(n) = f2(n) * K3 + g2(n-1) */
- gnext4 = (fnext4 * (*pk)) + gnext3;
- gnext3 = (fnext3 * (*pk)) + gnext2;
- gnext2 = (fnext2 * (*pk)) + gnext1;
- gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
-
- /* Read g1(n-1), g3(n-1) .... from state */
- gcurr1 = *px;
-
- /* save g3(n) in state buffer */
- *px++ = gnext4;
-
- /* Sample processing for K4, K8.... */
- /* Process first sample for 4th, 8th .. tap */
- /* f4(n) = f3(n) + K4 * g3(n-1) */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- /* Process second sample for 4th, 8th .. tap */
- /* for sample 2 processing */
- fnext2 = fcurr2 + ((*pk) * gnext1);
- /* Process third sample for 4th, 8th .. tap */
- fnext3 = fcurr3 + ((*pk) * gnext2);
- /* Process fourth sample for 4th, 8th .. tap */
- fnext4 = fcurr4 + ((*pk) * gnext3);
-
- /* g4(n) = f3(n) * K4 + g3(n-1) */
- /* Calculation of state values for next stage */
- gnext4 = (fcurr4 * (*pk)) + gnext3;
- gnext3 = (fcurr3 * (*pk)) + gnext2;
- gnext2 = (fcurr2 * (*pk)) + gnext1;
- gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
- /* Read g2(n-1), g4(n-1) .... from state */
- gcurr1 = *px;
-
- /* save g4(n) in state buffer */
- *px++ = gnext4;
-
- /* Sample processing for K5, K9.... */
- /* Process first sample for 5th, 9th .. tap */
- /* f5(n) = f4(n) + K5 * g4(n-1) */
- fcurr1 = fnext1 + ((*pk) * gcurr1);
- /* Process second sample for 5th, 9th .. tap */
- fcurr2 = fnext2 + ((*pk) * gnext1);
- /* Process third sample for 5th, 9th .. tap */
- fcurr3 = fnext3 + ((*pk) * gnext2);
- /* Process fourth sample for 5th, 9th .. tap */
- fcurr4 = fnext4 + ((*pk) * gnext3);
-
- /* Calculation of state values for next stage */
- /* g5(n) = f4(n) * K5 + g4(n-1) */
- gnext4 = (fnext4 * (*pk)) + gnext3;
- gnext3 = (fnext3 * (*pk)) + gnext2;
- gnext2 = (fnext2 * (*pk)) + gnext1;
- gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
- stageCnt--;
- }
-
- /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
- stageCnt = (numStages - 1u) % 0x4u;
-
- while (stageCnt > 0u)
- {
- gcurr1 = *px;
-
- /* save g value in state buffer */
- *px++ = gnext4;
-
- /* Process four samples for last three taps here */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- fnext2 = fcurr2 + ((*pk) * gnext1);
- fnext3 = fcurr3 + ((*pk) * gnext2);
- fnext4 = fcurr4 + ((*pk) * gnext3);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext4 = (fcurr4 * (*pk)) + gnext3;
- gnext3 = (fcurr3 * (*pk)) + gnext2;
- gnext2 = (fcurr2 * (*pk)) + gnext1;
- gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
- /* Update of f values for next coefficient set processing */
- fcurr1 = fnext1;
- fcurr2 = fnext2;
- fcurr3 = fnext3;
- fcurr4 = fnext4;
-
- stageCnt--;
-
- }
-
- /* The results in the 4 accumulators, store in the destination buffer. */
- /* y(n) = fN(n) */
- *pDst++ = fcurr1;
- *pDst++ = fcurr2;
- *pDst++ = fcurr3;
- *pDst++ = fcurr4;
-
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurr1 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g2(n) from state buffer */
- gcurr1 = *px;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
- /* save g1(n) in state buffer */
- *px++ = fcurr1;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* read g2(n) from state buffer */
- gcurr1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext1;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext1 = fcurr1 + ((*pk) * gcurr1);
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = fcurr1;
-
- blkCnt--;
-
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */
- uint32_t numStages = S->numStages; /* Length of the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
-
- pState = &S->pState[0];
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = pCoeffs;
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g0(n-1) from state buffer */
- gcurr = *px;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext = fcurr + ((*pk) * gcurr);
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext = (fcurr * (*pk++)) + gcurr;
-
- /* save f0(n) in state buffer */
- *px++ = fcurr;
-
- /* f1(n) is saved in fcurr
- for next stage processing */
- fcurr = fnext;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* read g2(n) from state buffer */
- gcurr = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext = fcurr + ((*pk) * gcurr);
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext = (fcurr * (*pk++)) + gcurr;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr = fnext;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = fcurr;
-
- blkCnt--;
-
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
deleted file mode 100644
index 2e31a15..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_init_f32.c
- * Description: Floating-point FIR Lattice filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
-void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always numStages */
- memset(pState, 0, (numStages) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
deleted file mode 100644
index ab5afd6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_init_q15.c
- * Description: Q15 FIR Lattice filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
-void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always numStages */
- memset(pState, 0, (numStages) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
deleted file mode 100644
index 4dc30cc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_init_q31.c
- * Description: Q31 FIR lattice filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
-void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always numStages */
- memset(pState, 0, (numStages) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
deleted file mode 100644
index 8095eca..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_q15.c
- * Description: Q15 FIR lattice filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
-
-/**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *px; /* temporary state pointer */
- q15_t *pk; /* temporary coefficient pointer */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
- q31_t fcurnt2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
- q31_t fcurnt3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
- q31_t fcurnt4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
- uint32_t numStages = S->numStages; /* Number of stages in the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
-
- pState = &S->pState[0];
-
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
- /* Read two samples from input buffer */
- /* f0(n) = x(n) */
- fcurnt1 = *pSrc++;
- fcurnt2 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* Read g0(n-1) from state */
- gcurnt1 = *px;
-
- /* Process first sample for first tap */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
- /* Process second sample for first tap */
- /* for sample 2 processing */
- fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
- fnext2 = __SSAT(fnext2, 16);
-
- gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
- gnext2 = __SSAT(gnext2, 16);
-
-
- /* Read next two samples from input buffer */
- /* f0(n+2) = x(n+2) */
- fcurnt3 = *pSrc++;
- fcurnt4 = *pSrc++;
-
- /* Copy only last input samples into the state buffer
- which is used for next four samples processing */
- *px++ = (q15_t) fcurnt4;
-
- /* Process third sample for first tap */
- fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
- fnext3 = __SSAT(fnext3, 16);
- gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
- gnext3 = __SSAT(gnext3, 16);
-
- /* Process fourth sample for first tap */
- fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
- fnext4 = __SSAT(fnext4, 16);
- gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
- gnext4 = __SSAT(gnext4, 16);
-
- /* Update of f values for next coefficient set processing */
- fcurnt1 = fnext1;
- fcurnt2 = fnext2;
- fcurnt3 = fnext3;
- fcurnt4 = fnext4;
-
-
- /* Loop unrolling. Process 4 taps at a time . */
- stageCnt = (numStages - 1u) >> 2;
-
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numStages-3 coefficients. */
-
- /* Process 2nd, 3rd, 4th and 5th taps ... here */
- while (stageCnt > 0u)
- {
- /* Read g1(n-1), g3(n-1) .... from state */
- gcurnt1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = (q15_t) gnext4;
-
- /* Process first sample for 2nd, 6th .. tap */
- /* Sample processing for K2, K6.... */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
-
-
- /* Process second sample for 2nd, 6th .. tap */
- /* for sample 2 processing */
- fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
- fnext2 = __SSAT(fnext2, 16);
- /* Process third sample for 2nd, 6th .. tap */
- fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
- fnext3 = __SSAT(fnext3, 16);
- /* Process fourth sample for 2nd, 6th .. tap */
- /* fnext4 = fcurnt4 + (*pk) * gnext3; */
- fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
- fnext4 = __SSAT(fnext4, 16);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- /* Calculation of state values for next stage */
- gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
- gnext4 = __SSAT(gnext4, 16);
- gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
- gnext3 = __SSAT(gnext3, 16);
-
- gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
- gnext2 = __SSAT(gnext2, 16);
-
- gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
-
- /* Read g2(n-1), g4(n-1) .... from state */
- gcurnt1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = (q15_t) gnext4;
-
- /* Sample processing for K3, K7.... */
- /* Process first sample for 3rd, 7th .. tap */
- /* f3(n) = f2(n) + K3 * g2(n-1) */
- fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
- fcurnt1 = __SSAT(fcurnt1, 16);
-
- /* Process second sample for 3rd, 7th .. tap */
- fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
- fcurnt2 = __SSAT(fcurnt2, 16);
-
- /* Process third sample for 3rd, 7th .. tap */
- fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
- fcurnt3 = __SSAT(fcurnt3, 16);
-
- /* Process fourth sample for 3rd, 7th .. tap */
- fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
- fcurnt4 = __SSAT(fcurnt4, 16);
-
- /* Calculation of state values for next stage */
- /* g3(n) = f2(n) * K3 + g2(n-1) */
- gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
- gnext4 = __SSAT(gnext4, 16);
-
- gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
- gnext3 = __SSAT(gnext3, 16);
-
- gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
- gnext2 = __SSAT(gnext2, 16);
-
- gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
- /* Read g1(n-1), g3(n-1) .... from state */
- gcurnt1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = (q15_t) gnext4;
-
- /* Sample processing for K4, K8.... */
- /* Process first sample for 4th, 8th .. tap */
- /* f4(n) = f3(n) + K4 * g3(n-1) */
- fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
-
- /* Process second sample for 4th, 8th .. tap */
- /* for sample 2 processing */
- fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
- fnext2 = __SSAT(fnext2, 16);
-
- /* Process third sample for 4th, 8th .. tap */
- fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
- fnext3 = __SSAT(fnext3, 16);
-
- /* Process fourth sample for 4th, 8th .. tap */
- fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
- fnext4 = __SSAT(fnext4, 16);
-
- /* g4(n) = f3(n) * K4 + g3(n-1) */
- /* Calculation of state values for next stage */
- gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
- gnext4 = __SSAT(gnext4, 16);
-
- gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
- gnext3 = __SSAT(gnext3, 16);
-
- gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
- gnext2 = __SSAT(gnext2, 16);
- gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
-
- /* Read g2(n-1), g4(n-1) .... from state */
- gcurnt1 = *px;
-
- /* save g4(n) in state buffer */
- *px++ = (q15_t) gnext4;
-
- /* Sample processing for K5, K9.... */
- /* Process first sample for 5th, 9th .. tap */
- /* f5(n) = f4(n) + K5 * g4(n-1) */
- fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
- fcurnt1 = __SSAT(fcurnt1, 16);
-
- /* Process second sample for 5th, 9th .. tap */
- fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
- fcurnt2 = __SSAT(fcurnt2, 16);
-
- /* Process third sample for 5th, 9th .. tap */
- fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
- fcurnt3 = __SSAT(fcurnt3, 16);
-
- /* Process fourth sample for 5th, 9th .. tap */
- fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
- fcurnt4 = __SSAT(fcurnt4, 16);
-
- /* Calculation of state values for next stage */
- /* g5(n) = f4(n) * K5 + g4(n-1) */
- gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
- gnext4 = __SSAT(gnext4, 16);
- gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
- gnext3 = __SSAT(gnext3, 16);
- gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
- gnext2 = __SSAT(gnext2, 16);
- gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
- stageCnt--;
- }
-
- /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
- stageCnt = (numStages - 1u) % 0x4u;
-
- while (stageCnt > 0u)
- {
- gcurnt1 = *px;
-
- /* save g value in state buffer */
- *px++ = (q15_t) gnext4;
-
- /* Process four samples for last three taps here */
- fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
- fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
- fnext2 = __SSAT(fnext2, 16);
-
- fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
- fnext3 = __SSAT(fnext3, 16);
-
- fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
- fnext4 = __SSAT(fnext4, 16);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
- gnext4 = __SSAT(gnext4, 16);
- gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
- gnext3 = __SSAT(gnext3, 16);
- gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
- gnext2 = __SSAT(gnext2, 16);
- gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
- /* Update of f values for next coefficient set processing */
- fcurnt1 = fnext1;
- fcurnt2 = fnext2;
- fcurnt3 = fnext3;
- fcurnt4 = fnext4;
-
- stageCnt--;
-
- }
-
- /* The results in the 4 accumulators, store in the destination buffer. */
- /* y(n) = fN(n) */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
- *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
-
-#else
-
- *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
- *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurnt1 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g2(n) from state buffer */
- gcurnt1 = *px;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
-
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
- /* save g1(n) in state buffer */
- *px++ = (q15_t) fcurnt1;
-
- /* f1(n) is saved in fcurnt1
- for next stage processing */
- fcurnt1 = fnext1;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* read g2(n) from state buffer */
- gcurnt1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = (q15_t) gnext1;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
- fnext1 = __SSAT(fnext1, 16);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
- gnext1 = __SSAT(gnext1, 16);
-
-
- /* f1(n) is saved in fcurnt1
- for next stage processing */
- fcurnt1 = fnext1;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = __SSAT(fcurnt1, 16);
-
-
- blkCnt--;
-
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */
- uint32_t numStages = S->numStages; /* Length of the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
-
- pState = &S->pState[0];
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurnt = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g0(n-1) from state buffer */
- gcurnt = *px;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
- fnext = __SSAT(fnext, 16);
-
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
- gnext = __SSAT(gnext, 16);
-
- /* save f0(n) in state buffer */
- *px++ = (q15_t) fcurnt;
-
- /* f1(n) is saved in fcurnt
- for next stage processing */
- fcurnt = fnext;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* read g1(n-1) from state buffer */
- gcurnt = *px;
-
- /* save g0(n-1) in state buffer */
- *px++ = (q15_t) gnext;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
- fnext = __SSAT(fnext, 16);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
- gnext = __SSAT(gnext, 16);
-
-
- /* f1(n) is saved in fcurnt
- for next stage processing */
- fcurnt = fnext;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = __SSAT(fcurnt, 16);
-
-
- blkCnt--;
-
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
deleted file mode 100644
index fa05b6b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_lattice_q31.c
- * Description: Q31 FIR lattice filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Lattice
- * @{
- */
-
-
-/**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
- */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *px; /* temporary state pointer */
- q31_t *pk; /* temporary coefficient pointer */
- q31_t fcurr1, fnext1, gcurr1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
- q31_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
- uint32_t numStages = S->numStages; /* Length of the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
- q31_t k;
-
- pState = &S->pState[0];
-
- blkCnt = blockSize >> 1u;
-
- /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
- a second loop below computes the remaining 1 sample. */
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurr1 = *pSrc++;
-
- /* f0(n) = x(n) */
- fcurr2 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g0(n - 1) from state buffer */
- gcurr1 = *px;
-
- /* Read the reflection coefficient */
- k = *pk++;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
- fnext1 = fcurr1 + (fnext1 << 1u);
- gnext1 = gcurr1 + (gnext1 << 1u);
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
- fnext2 = fcurr2 + (fnext2 << 1u);
- gnext2 = fcurr1 + (gnext2 << 1u);
-
- /* save g1(n) in state buffer */
- *px++ = fcurr2;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
- fcurr2 = fnext2;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
-
- /* Read the reflection coefficient */
- k = *pk++;
-
- /* read g2(n) from state buffer */
- gcurr1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext2;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
- fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
-
- fnext1 = fcurr1 + (fnext1 << 1u);
- fnext2 = fcurr2 + (fnext2 << 1u);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
- gnext2 = gnext1 + (gnext2 << 1u);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
- gnext1 = gcurr1 + (gnext1 << 1u);
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
- fcurr2 = fnext2;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = fcurr1;
- *pDst++ = fcurr2;
-
- blkCnt--;
-
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x2u;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurr1 = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g0(n - 1) from state buffer */
- gcurr1 = *px;
-
- /* Read the reflection coefficient */
- k = *pk++;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
- fnext1 = fcurr1 + (fnext1 << 1u);
-
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
- gnext1 = gcurr1 + (gnext1 << 1u);
-
- /* save g1(n) in state buffer */
- *px++ = fcurr1;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* Read the reflection coefficient */
- k = *pk++;
-
- /* read g2(n) from state buffer */
- gcurr1 = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext1;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
- fnext1 = fcurr1 + (fnext1 << 1u);
-
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
- gnext1 = gcurr1 + (gnext1 << 1u);
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr1 = fnext1;
-
- stageCnt--;
-
- }
-
-
- /* y(n) = fN(n) */
- *pDst++ = fcurr1;
-
- blkCnt--;
-
- }
-
-
-}
-
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *px; /* temporary state pointer */
- q31_t *pk; /* temporary coefficient pointer */
- q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */
- uint32_t numStages = S->numStages; /* Length of the filter */
- uint32_t blkCnt, stageCnt; /* temporary variables for counts */
-
- pState = &S->pState[0];
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* f0(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize coeff pointer */
- pk = (pCoeffs);
-
- /* Initialize state pointer */
- px = pState;
-
- /* read g0(n-1) from state buffer */
- gcurr = *px;
-
- /* for sample 1 processing */
- /* f1(n) = f0(n) + K1 * g0(n-1) */
- fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
- /* g1(n) = f0(n) * K1 + g0(n-1) */
- gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
- /* save g1(n) in state buffer */
- *px++ = fcurr;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr = fnext;
-
- stageCnt = (numStages - 1u);
-
- /* stage loop */
- while (stageCnt > 0u)
- {
- /* read g2(n) from state buffer */
- gcurr = *px;
-
- /* save g1(n) in state buffer */
- *px++ = gnext;
-
- /* Sample processing for K2, K3.... */
- /* f2(n) = f1(n) + K2 * g1(n-1) */
- fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
- /* g2(n) = f1(n) * K2 + g1(n-1) */
- gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
-
- /* f1(n) is saved in fcurr1
- for next stage processing */
- fcurr = fnext;
-
- stageCnt--;
-
- }
-
- /* y(n) = fN(n) */
- *pDst++ = fcurr;
-
- blkCnt--;
-
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-/**
- * @} end of FIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c
deleted file mode 100644
index c065c37..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_q15.c
- * Description: Q15 FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] *S points to an instance of the Q15 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, state buffers should be aligned by 32-bit
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- *
- * \par
- * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.
- */
-
-#if defined (ARM_MATH_DSP)
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-
-void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px1; /* Temporary q15 pointer for state buffer */
- q15_t *pb; /* Temporary pointer for coefficient buffer */
- q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold SIMD state and coefficient values */
- q63_t acc0, acc1, acc2, acc3; /* Accumulators */
- uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
-
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
-
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer.
- ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Initialize state pointer of type q15 */
- px1 = pState;
-
- /* Initialize coeff pointer of type q31 */
- pb = pCoeffs;
-
- /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
- x0 = _SIMD32_OFFSET(px1);
-
- /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
- x1 = _SIMD32_OFFSET(px1 + 1u);
-
- px1 += 2u;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-4 coefficients. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
- /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
- acc0 = __SMLALD(x0, c0, acc0);
-
- /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
- acc1 = __SMLALD(x1, c0, acc1);
-
- /* Read state x[n-N-2], x[n-N-3] */
- x2 = _SIMD32_OFFSET(px1);
-
- /* Read state x[n-N-3], x[n-N-4] */
- x3 = _SIMD32_OFFSET(px1 + 1u);
-
- /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
- acc2 = __SMLALD(x2, c0, acc2);
-
- /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
- acc3 = __SMLALD(x3, c0, acc3);
-
- /* Read coefficients b[N-2], b[N-3] */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
- acc0 = __SMLALD(x2, c0, acc0);
-
- /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
- acc1 = __SMLALD(x3, c0, acc1);
-
- /* Read state x[n-N-4], x[n-N-5] */
- x0 = _SIMD32_OFFSET(px1 + 2u);
-
- /* Read state x[n-N-5], x[n-N-6] */
- x1 = _SIMD32_OFFSET(px1 + 3u);
-
- /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
- acc2 = __SMLALD(x0, c0, acc2);
-
- /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
- acc3 = __SMLALD(x1, c0, acc3);
-
- px1 += 4u;
-
- tapCnt--;
-
- }
-
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps.
- ** This is always be 2 taps since the filter length is even. */
- if ((numTaps & 0x3u) != 0u)
- {
- /* Read 2 coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Fetch 4 state variables */
- x2 = _SIMD32_OFFSET(px1);
-
- x3 = _SIMD32_OFFSET(px1 + 1u);
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
-
- px1 += 2u;
-
- acc1 = __SMLALD(x1, c0, acc1);
- acc2 = __SMLALD(x2, c0, acc2);
- acc3 = __SMLALD(x3, c0, acc3);
- }
-
- /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
- while (blkCnt > 0u)
- {
- /* Copy two samples into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Initialize state pointer of type q15 */
- px1 = pState;
-
- /* Initialize coeff pointer of type q31 */
- pb = pCoeffs;
-
- tapCnt = numTaps >> 1;
-
- do
- {
-
- c0 = *__SIMD32(pb)++;
- x0 = *__SIMD32(px1)++;
-
- acc0 = __SMLALD(x0, c0, acc0);
- tapCnt--;
- }
- while (tapCnt > 0u);
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Calculation of count for copying integer writes */
- tapCnt = (numTaps - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
-
- /* Copy state values to start of state buffer */
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
- tapCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* copy remaining data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-#else /* UNALIGNED_SUPPORT_DISABLE */
-
-void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q63_t acc0, acc1, acc2, acc3; /* Accumulators */
- q15_t *pb; /* Temporary pointer for coefficient buffer */
- q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
- q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
- uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
-
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
-
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer.
- ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
- px = pState;
-
- /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
- pb = pCoeffs;
-
- /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
- x0 = *__SIMD32(px)++;
-
- /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
- x2 = *__SIMD32(px)++;
-
- /* Loop over the number of taps. Unroll by a factor of 4.
- ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0)
- {
- /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
- acc0 = __SMLALD(x0, c0, acc0);
-
- /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
- acc2 = __SMLALD(x2, c0, acc2);
-
- /* pack x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* Read state x[n-N-4], x[n-N-5] */
- x0 = _SIMD32_OFFSET(px);
-
- /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
- acc1 = __SMLALDX(x1, c0, acc1);
-
- /* pack x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x0, x2, 0);
-#else
- x1 = __PKHBT(x2, x0, 0);
-#endif
-
- /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
- acc3 = __SMLALDX(x1, c0, acc3);
-
- /* Read coefficients b[N-2], b[N-3] */
- c0 = *__SIMD32(pb)++;
-
- /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
- acc0 = __SMLALD(x2, c0, acc0);
-
- /* Read state x[n-N-6], x[n-N-7] with offset */
- x2 = _SIMD32_OFFSET(px + 2u);
-
- /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
- acc2 = __SMLALD(x0, c0, acc2);
-
- /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
- acc1 = __SMLALDX(x1, c0, acc1);
-
- /* pack x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
- acc3 = __SMLALDX(x1, c0, acc3);
-
- /* Update state pointer for next state reading */
- px += 4u;
-
- /* Decrement tap count */
- tapCnt--;
-
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps.
- ** This is always be 2 taps since the filter length is even. */
- if ((numTaps & 0x3u) != 0u)
- {
-
- /* Read last two coefficients */
- c0 = *__SIMD32(pb)++;
-
- /* Perform the multiply-accumulates */
- acc0 = __SMLALD(x0, c0, acc0);
- acc2 = __SMLALD(x2, c0, acc2);
-
- /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x2, x0, 0);
-#else
- x1 = __PKHBT(x0, x2, 0);
-#endif
-
- /* Read last state variables */
- x0 = *__SIMD32(px);
-
- /* Perform the multiply-accumulates */
- acc1 = __SMLALDX(x1, c0, acc1);
-
- /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
- x1 = __PKHBT(x0, x2, 0);
-#else
- x1 = __PKHBT(x2, x0, 0);
-#endif
-
- /* Perform the multiply-accumulates */
- acc3 = __SMLALDX(x1, c0, acc3);
- }
-
- /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
- *__SIMD32(pDst)++ =
- __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
- while (blkCnt > 0u)
- {
- /* Copy two samples into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Use SIMD to hold states and coefficients */
- px = pState;
- pb = pCoeffs;
-
- tapCnt = numTaps >> 1u;
-
- do
- {
- acc0 += (q31_t) * px++ * *pb++;
- acc0 += (q31_t) * px++ * *pb++;
- tapCnt--;
- }
- while (tapCnt > 0u);
-
- /* The result is in 2.30 format. Convert to 1.15 with saturation.
- ** Then store the output in the destination buffer. */
- *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Calculation of count for copying integer writes */
- tapCnt = (numTaps - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- tapCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* copy remaining data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#else /* ARM_MATH_CM0_FAMILY */
-
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
-
-
-
- q15_t *px; /* Temporary pointer for state buffer */
- q15_t *pb; /* Temporary pointer for coefficient buffer */
- q63_t acc; /* Accumulator */
- uint32_t numTaps = S->numTaps; /* Number of nTaps in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Initialize blkCnt with blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = pCoeffs;
-
- tapCnt = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
- acc += (q31_t) * px++ * *pb++;
- tapCnt--;
- } while (tapCnt > 0u);
-
- /* The result is in 2.30 format. Convert to 1.15
- ** Then store the output in the destination buffer. */
- *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Copy numTaps number of values */
- tapCnt = (numTaps - 1u);
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c
deleted file mode 100644
index ec4c917..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_q31.c
- * Description: Q31 FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @param[in] *S points to an instance of the Q31 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
- * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
- *
- * \par
- * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
- */
-
-void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t x0, x1, x2; /* Temporary variables to hold state */
- q31_t c0; /* Temporary variable to hold coefficient value */
- q31_t *px; /* Temporary pointer for state */
- q31_t *pb; /* Temporary pointer for coefficient buffer */
- q63_t acc0, acc1, acc2; /* Accumulators */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt, tapCntN3; /* Loop counters */
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
- blkCnt = blockSize / 3;
- blockSize = blockSize - (3 * blkCnt);
-
- tapCnt = numTaps / 3;
- tapCntN3 = numTaps - (3 * tapCnt);
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy three new input samples into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Read the first two samples from the state buffer:
- * x[n-numTaps], x[n-numTaps-1] */
- x0 = *(px++);
- x1 = *(px++);
-
- /* Loop unrolling. Process 3 taps at a time. */
- i = tapCnt;
-
- while (i > 0u)
- {
- /* Read the b[numTaps] coefficient */
- c0 = *pb;
-
- /* Read x[n-numTaps-2] sample */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q63_t) x0 * c0);
- acc1 += ((q63_t) x1 * c0);
- acc2 += ((q63_t) x2 * c0);
-
- /* Read the coefficient and state */
- c0 = *(pb + 1u);
- x0 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q63_t) x1 * c0);
- acc1 += ((q63_t) x2 * c0);
- acc2 += ((q63_t) x0 * c0);
-
- /* Read the coefficient and state */
- c0 = *(pb + 2u);
- x1 = *(px++);
-
- /* update coefficient pointer */
- pb += 3u;
-
- /* Perform the multiply-accumulates */
- acc0 += ((q63_t) x2 * c0);
- acc1 += ((q63_t) x0 * c0);
- acc2 += ((q63_t) x1 * c0);
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* If the filter length is not a multiple of 3, compute the remaining filter taps */
-
- i = tapCntN3;
-
- while (i > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x2 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q63_t) x0 * c0);
- acc1 += ((q63_t) x1 * c0);
- acc2 += ((q63_t) x2 * c0);
-
- /* Reuse the present sample states for next sample */
- x0 = x1;
- x1 = x2;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 3 to process the next group of 3 samples */
- pState = pState + 3;
-
- /* The results in the 3 accumulators are in 2.30 format. Convert to 1.31
- ** Then store the 3 outputs in the destination buffer. */
- *pDst++ = (q31_t) (acc0 >> 31u);
- *pDst++ = (q31_t) (acc1 >> 31u);
- *pDst++ = (q31_t) (acc2 >> 31u);
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 3, compute any remaining output samples here.
- ** No loop unrolling is used. */
-
- while (blockSize > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = (pCoeffs);
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- acc0 += (q63_t) * (px++) * (*(pb++));
- i--;
- } while (i > 0u);
-
- /* The result is in 2.62 format. Convert to 1.31
- ** Then store the output in the destination buffer. */
- *pDst++ = (q31_t) (acc0 >> 31u);
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the samples loop counter */
- blockSize--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- q31_t *px; /* Temporary pointer for state */
- q31_t *pb; /* Temporary pointer for coefficient buffer */
- q63_t acc; /* Accumulator */
- uint32_t numTaps = S->numTaps; /* Length of the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
-
- /* S->pState buffer contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Initialize blkCnt with blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = pCoeffs;
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
- acc += (q63_t) * px++ * *pb++;
- i--;
- } while (i > 0u);
-
- /* The result is in 2.62 format. Convert to 1.31
- ** Then store the output in the destination buffer. */
- *pDst++ = (q31_t) (acc >> 31u);
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- /* Copy numTaps number of values */
- tapCnt = numTaps - 1u;
-
- /* Copy the data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
deleted file mode 100644
index 34fa268..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_q7.c
- * Description: Q7 FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR
- * @{
- */
-
-/**
- * @param[in] *S points to an instance of the Q7 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * The accumulator is converted to 18.7 format by discarding the low 7 bits.
- * Finally, the result is truncated to 1.7 format.
- */
-
-void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t *pState = S->pState; /* State pointer */
- q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q7_t *pStateCurnt; /* Points to the current sample of the state */
- q7_t x0, x1, x2, x3; /* Temporary variables to hold state */
- q7_t c0; /* Temporary variable to hold coefficient value */
- q7_t *px; /* Temporary pointer for state */
- q7_t *pb; /* Temporary pointer for coefficient buffer */
- q31_t acc0, acc1, acc2, acc3; /* Accumulators */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t i, tapCnt, blkCnt; /* Loop counters */
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Apply loop unrolling and compute 4 output values simultaneously.
- * The variables acc0 ... acc3 hold output values that are being computed:
- *
- * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
- * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
- * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
- * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
- */
- blkCnt = blockSize >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Copy four new input samples into the state buffer */
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
- *pStateCurnt++ = *pSrc++;
-
- /* Set all accumulators to zero */
- acc0 = 0;
- acc1 = 0;
- acc2 = 0;
- acc3 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Read the first three samples from the state buffer:
- * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
- x0 = *(px++);
- x1 = *(px++);
- x2 = *(px++);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
- i = tapCnt;
-
- while (i > 0u)
- {
- /* Read the b[numTaps] coefficient */
- c0 = *pb;
-
- /* Read x[n-numTaps-3] sample */
- x3 = *px;
-
- /* acc0 += b[numTaps] * x[n-numTaps] */
- acc0 += ((q15_t) x0 * c0);
-
- /* acc1 += b[numTaps] * x[n-numTaps-1] */
- acc1 += ((q15_t) x1 * c0);
-
- /* acc2 += b[numTaps] * x[n-numTaps-2] */
- acc2 += ((q15_t) x2 * c0);
-
- /* acc3 += b[numTaps] * x[n-numTaps-3] */
- acc3 += ((q15_t) x3 * c0);
-
- /* Read the b[numTaps-1] coefficient */
- c0 = *(pb + 1u);
-
- /* Read x[n-numTaps-4] sample */
- x0 = *(px + 1u);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q15_t) x1 * c0);
- acc1 += ((q15_t) x2 * c0);
- acc2 += ((q15_t) x3 * c0);
- acc3 += ((q15_t) x0 * c0);
-
- /* Read the b[numTaps-2] coefficient */
- c0 = *(pb + 2u);
-
- /* Read x[n-numTaps-5] sample */
- x1 = *(px + 2u);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q15_t) x2 * c0);
- acc1 += ((q15_t) x3 * c0);
- acc2 += ((q15_t) x0 * c0);
- acc3 += ((q15_t) x1 * c0);
-
- /* Read the b[numTaps-3] coefficients */
- c0 = *(pb + 3u);
-
- /* Read x[n-numTaps-6] sample */
- x2 = *(px + 3u);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q15_t) x3 * c0);
- acc1 += ((q15_t) x0 * c0);
- acc2 += ((q15_t) x1 * c0);
- acc3 += ((q15_t) x2 * c0);
-
- /* update coefficient pointer */
- pb += 4u;
- px += 4u;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
- i = numTaps - (tapCnt * 4u);
- while (i > 0u)
- {
- /* Read coefficients */
- c0 = *(pb++);
-
- /* Fetch 1 state variable */
- x3 = *(px++);
-
- /* Perform the multiply-accumulates */
- acc0 += ((q15_t) x0 * c0);
- acc1 += ((q15_t) x1 * c0);
- acc2 += ((q15_t) x2 * c0);
- acc3 += ((q15_t) x3 * c0);
-
- /* Reuse the present sample states for next sample */
- x0 = x1;
- x1 = x2;
- x2 = x3;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 4;
-
- /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31
- ** Then store the 4 outputs in the destination buffer. */
- acc0 = __SSAT((acc0 >> 7u), 8);
- *pDst++ = acc0;
- acc1 = __SSAT((acc1 >> 7u), 8);
- *pDst++ = acc1;
- acc2 = __SSAT((acc2 >> 7u), 8);
- *pDst++ = acc2;
- acc3 = __SSAT((acc3 >> 7u), 8);
- *pDst++ = acc3;
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 4u;
-
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set the accumulator to zero */
- acc0 = 0;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize Coefficient pointer */
- pb = (pCoeffs);
-
- i = numTaps;
-
- /* Perform the multiply-accumulates */
- do
- {
- acc0 += (q15_t) * (px++) * (*(pb++));
- i--;
- } while (i > 0u);
-
- /* The result is in 2.14 format. Convert to 1.7
- ** Then store the output in the destination buffer. */
- *pDst++ = __SSAT((acc0 >> 7u), 8);
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the samples loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
- uint32_t i, blkCnt; /* Loop counters */
- q7_t *pState = S->pState; /* State pointer */
- q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q7_t *px, *pb; /* Temporary pointers to state and coeff */
- q31_t acc = 0; /* Accumlator */
- q7_t *pStateCurnt; /* Points to the current sample of the state */
-
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = S->pState + (numTaps - 1u);
-
- /* Initialize blkCnt with blockSize */
- blkCnt = blockSize;
-
- /* Perform filtering upto BlockSize - BlockSize%4 */
- while (blkCnt > 0u)
- {
- /* Copy one sample at a time into state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Set accumulator to zero */
- acc = 0;
-
- /* Initialize state pointer of type q7 */
- px = pState;
-
- /* Initialize coeff pointer of type q7 */
- pb = pCoeffs;
-
-
- i = numTaps;
-
- while (i > 0u)
- {
- /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
- acc += (q15_t) * px++ * *pb++;
- i--;
- }
-
- /* Store the 1.7 format filter output in destination buffer */
- *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
-
- /* Advance the state pointer by 1 to process the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete.
- ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
- ** This prepares the state buffer for the next function call. */
-
-
- /* Points to the start of the state buffer */
- pStateCurnt = S->pState;
-
-
- /* Copy numTaps number of values */
- i = (numTaps - 1u);
-
- /* Copy q7_t data */
- while (i > 0u)
- {
- *pStateCurnt++ = *pState++;
- i--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
deleted file mode 100644
index a8ca452..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_f32.c
- * Description: Floating-point sparse FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
- *
- * This group of functions implements sparse FIR filters.
- * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
- * Sparse filters are used for simulating reflections in communications and audio applications.
- *
- * There are separate functions for Q7, Q15, Q31, and floating-point data types.
- * The functions operate on blocks of input and output data and each call to the function processes
- * blockSize samples through the filter. pSrc and
- * pDst points to input and output arrays respectively containing blockSize values.
- *
- * \par Algorithm:
- * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.
- * This is in addition to the coefficient array b.
- * The implementation essentially skips the multiplications by zero and leads to an efficient realization.
- *
- * y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
- *
- * \par
- * \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients"
- * \par
- * pCoeffs points to a coefficient array of size numTaps;
- * pTapDelay points to an array of nonzero indices and is also of size numTaps;
- * pState points to a state array of size maxDelay + blockSize, where
- * maxDelay is the largest offset value that is ever used in the pTapDelay array.
- * Some of the processing functions also require temporary working buffers.
- *
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
- * There are separate instance structure declarations for each of the 4 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros before static initialization.
- * The code below statically initializes each of the 4 different data type filter instance structures
- *
- *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
- *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
- *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
- *arm_fir_sparse_instance_q7 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
- *
- * \par
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
-void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize)
-{
-
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *px; /* Scratch buffer pointer */
- float32_t *py = pState; /* Temporary pointers for state buffer */
- float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
- float32_t *pOut; /* Destination pointer */
- int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
- uint32_t delaySize = S->maxDelay + blockSize; /* state length */
- uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- int32_t readIndex; /* Read index of the state buffer */
- uint32_t tapCnt, blkCnt; /* loop counters */
- float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
-
-
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
- (int32_t *) pSrc, 1, blockSize);
-
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer */
- px = pb;
-
- /* Working pointer for destination buffer */
- pOut = pDst;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 Multiplications at a time. */
- blkCnt = blockSize >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in destination buffer */
- *pOut++ = *px++ * coeff;
- *pOut++ = *px++ * coeff;
- *pOut++ = *px++ * coeff;
- *pOut++ = *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in destination buffer */
- *pOut++ = *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer */
- px = pb;
-
- /* Working pointer for destination buffer */
- pOut = pDst;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex -
- (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer */
- px = pb;
-
- /* Working pointer for destination buffer */
- pOut = pDst;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in destination buffer */
- *pOut++ = *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer */
- px = pb;
-
- /* Working pointer for destination buffer */
- pOut = pDst;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex =
- ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer */
- px = pb;
-
- /* Working pointer for destination buffer */
- pOut = pDst;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pOut++ += *px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
deleted file mode 100644
index 98ddfaf..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_init_f32.c
- * Description: Floating-point sparse FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- *
- * Description:
- * \par
- * pCoeffs holds the filter coefficients and has length numTaps.
- * pState holds the filter's state variables and must be of length
- * maxDelay + blockSize, where maxDelay
- * is the maximum number of delay line values.
- * blockSize is the
- * number of samples processed by the arm_fir_sparse_f32() function.
- */
-
-void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign TapDelay pointer */
- S->pTapDelay = pTapDelay;
-
- /* Assign MaxDelay */
- S->maxDelay = maxDelay;
-
- /* reset the stateIndex to 0 */
- S->stateIndex = 0u;
-
- /* Clear state buffer and size is always maxDelay + blockSize */
- memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
deleted file mode 100644
index d918561..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_init_q15.c
- * Description: Q15 sparse FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- *
- * Description:
- * \par
- * pCoeffs holds the filter coefficients and has length numTaps.
- * pState holds the filter's state variables and must be of length
- * maxDelay + blockSize, where maxDelay
- * is the maximum number of delay line values.
- * blockSize is the
- * number of words processed by arm_fir_sparse_q15() function.
- */
-
-void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign TapDelay pointer */
- S->pTapDelay = pTapDelay;
-
- /* Assign MaxDelay */
- S->maxDelay = maxDelay;
-
- /* reset the stateIndex to 0 */
- S->stateIndex = 0u;
-
- /* Clear state buffer and size is always maxDelay + blockSize */
- memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
deleted file mode 100644
index 391b933..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_init_q31.c
- * Description: Q31 sparse FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- *
- * Description:
- * \par
- * pCoeffs holds the filter coefficients and has length numTaps.
- * pState holds the filter's state variables and must be of length
- * maxDelay + blockSize, where maxDelay
- * is the maximum number of delay line values.
- * blockSize is the number of words processed by arm_fir_sparse_q31() function.
- */
-
-void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign TapDelay pointer */
- S->pTapDelay = pTapDelay;
-
- /* Assign MaxDelay */
- S->maxDelay = maxDelay;
-
- /* reset the stateIndex to 0 */
- S->stateIndex = 0u;
-
- /* Clear state buffer and size is always maxDelay + blockSize */
- memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
deleted file mode 100644
index bb47262..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_init_q7.c
- * Description: Q7 sparse FIR filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- *
- * Description:
- * \par
- * pCoeffs holds the filter coefficients and has length numTaps.
- * pState holds the filter's state variables and must be of length
- * maxDelay + blockSize, where maxDelay
- * is the maximum number of delay line values.
- * blockSize is the
- * number of samples processed by the arm_fir_sparse_q7() function.
- */
-
-void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Assign TapDelay pointer */
- S->pTapDelay = pTapDelay;
-
- /* Assign MaxDelay */
- S->maxDelay = maxDelay;
-
- /* reset the stateIndex to 0 */
- S->stateIndex = 0u;
-
- /* Clear state buffer and size is always maxDelay + blockSize */
- memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
deleted file mode 100644
index 81dbab5..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_q15.c
- * Description: Q15 sparse FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
- * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
- * If the accumulator result overflows it will wrap around rather than saturate.
- * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
- */
-
-
-void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize)
-{
-
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pIn = pSrc; /* Working pointer for input */
- q15_t *pOut = pDst; /* Working pointer for output */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *px; /* Temporary pointers for scratch buffer */
- q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
- q15_t *py = pState; /* Temporary pointers for state buffer */
- int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
- uint32_t delaySize = S->maxDelay + blockSize; /* state length */
- uint16_t numTaps = S->numTaps; /* Filter order */
- int32_t readIndex; /* Read index of the state buffer */
- uint32_t tapCnt, blkCnt; /* loop counters */
- q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
- q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in1, in2; /* Temporary variables */
-
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
- /* Loop over the number of taps. */
- tapCnt = numTaps;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 multiplications at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* All the output values are in pScratchOut buffer.
- Convert them into 1.15 format, saturate and store in the destination buffer. */
- /* Loop over the blockSize. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- in1 = *pScr2++;
- in2 = *pScr2++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
- 16);
-
-#else
- *__SIMD32(pOut)++ =
- __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
- 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- in1 = *pScr2++;
-
- in2 = *pScr2++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pOut)++ =
- __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
- 16);
-
-#else
-
- *__SIMD32(pOut)++ =
- __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
- 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-
- blkCnt--;
-
- }
-
- /* If the blockSize is not a multiple of 4,
- remaining samples are processed in the below loop */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
- /* Loop over the number of taps. */
- tapCnt = numTaps;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q15(py, delaySize, &readIndex, 1,
- pb, pb, blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- *pScratchOut++ += (q31_t) * px++ * coeff;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* All the output values are in pScratchOut buffer.
- Convert them into 1.15 format, saturate and store in the destination buffer. */
- /* Loop over the blockSize. */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
deleted file mode 100644
index c6759f5..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_q31.c
- * Description: Q31 sparse FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The 1.31 x 1.31 multiplications are truncated to 2.30 format.
- * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
- * If the accumulator result overflows, it wraps around rather than saturate.
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
- */
-
-void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize)
-{
-
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *px; /* Scratch buffer pointer */
- q31_t *py = pState; /* Temporary pointers for state buffer */
- q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
- q31_t *pOut; /* Destination pointer */
- q63_t out; /* Temporary output variable */
- int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
- uint32_t delaySize = S->maxDelay + blockSize; /* state length */
- uint16_t numTaps = S->numTaps; /* Filter order */
- int32_t readIndex; /* Read index of the state buffer */
- uint32_t tapCnt, blkCnt; /* loop counters */
- q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
- q31_t in;
-
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
- (int32_t *) pSrc, 1, blockSize);
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pOut = pDst;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 Multiplications at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in the destination buffer */
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in the destination buffer */
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pOut = pDst;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pOut = pDst;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Working output pointer is updated */
- pOut = pDst;
-
- /* Output is converted into 1.31 format. */
- /* Loop over the blockSize. Unroll by a factor of 4.
- * process 4 output samples at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- in = *pOut << 1;
- *pOut++ = in;
- in = *pOut << 1;
- *pOut++ = in;
- in = *pOut << 1;
- *pOut++ = in;
- in = *pOut << 1;
- *pOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * process the remaining output samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- in = *pOut << 1;
- *pOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiplications and store in the destination buffer */
- *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pOut = pDst;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
- (int32_t *) pb, (int32_t *) pb, blockSize, 1,
- blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pOut = pDst;
-
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- out = *pOut;
- out += ((q63_t) * px++ * coeff) >> 32;
- *pOut++ = (q31_t) (out);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Working output pointer is updated */
- pOut = pDst;
-
- /* Output is converted into 1.31 format. */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- in = *pOut << 1;
- *pOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
deleted file mode 100644
index 6119477..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fir_sparse_q7.c
- * Description: Q7 sparse FIR filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup FIR_Sparse
- * @{
- */
-
-
-/**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * The accumulator is then converted to 18.7 format by discarding the low 7 bits.
- * Finally, the result is truncated to 1.7 format.
- */
-
-void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize)
-{
-
- q7_t *pState = S->pState; /* State pointer */
- q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q7_t *px; /* Scratch buffer pointer */
- q7_t *py = pState; /* Temporary pointers for state buffer */
- q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
- q7_t *pOut = pDst; /* Destination pointer */
- int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
- uint32_t delaySize = S->maxDelay + blockSize; /* state length */
- uint16_t numTaps = S->numTaps; /* Filter order */
- int32_t readIndex; /* Read index of the state buffer */
- uint32_t tapCnt, blkCnt; /* loop counters */
- q7_t coeff = *pCoeffs++; /* Read the coefficient value */
- q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
- q31_t in;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t in1, in2, in3, in4;
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
- blockSize);
-
- /* Loop over the number of taps. */
- tapCnt = numTaps;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 multiplications at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex -
- (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize. Unroll by a factor of 4.
- * Compute 4 MACS at a time. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- * compute the remaining samples */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* All the output values are in pScratchOut buffer.
- Convert them into 1.15 format, saturate and store in the destination buffer. */
- /* Loop over the blockSize. */
- blkCnt = blockSize >> 2;
-
- while (blkCnt > 0u)
- {
- in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
- in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
- in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
- in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
- *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4,
- remaining samples are processed in the below loop */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* BlockSize of Input samples are copied into the state buffer */
- /* StateIndex points to the starting position to write in the state buffer */
- arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
- blockSize);
-
- /* Loop over the number of taps. */
- tapCnt = numTaps;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform multiplication and store in the scratch buffer */
- *pScratchOut++ = ((q31_t) * px++ * coeff);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Loop over the number of taps. */
- tapCnt = (uint32_t) numTaps - 2u;
-
- while (tapCnt > 0u)
- {
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Load the coefficient value and
- * increment the coefficient buffer for the next set of state values */
- coeff = *pCoeffs++;
-
- /* Read Index, from where the state buffer should be read, is calculated. */
- readIndex =
- ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
- /* Wraparound of readIndex */
- if (readIndex < 0)
- {
- readIndex += (int32_t) delaySize;
- }
-
- /* Decrement the tap loop counter */
- tapCnt--;
- }
-
- /* Compute last tap without the final read of pTapDelay */
-
- /* Working pointer for state buffer is updated */
- py = pState;
-
- /* blockSize samples are read from the state buffer */
- arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
- (int32_t) blockSize, 1, blockSize);
-
- /* Working pointer for the scratch buffer of state values */
- px = pb;
-
- /* Working pointer for scratch buffer of output values */
- pScratchOut = pScr2;
-
- /* Loop over the blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Perform Multiply-Accumulate */
- in = *pScratchOut + ((q31_t) * px++ * coeff);
- *pScratchOut++ = in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* All the output values are in pScratchOut buffer.
- Convert them into 1.15 format, saturate and store in the destination buffer. */
- /* Loop over the blockSize. */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
- /* Decrement the blockSize loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of FIR_Sparse group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
deleted file mode 100644
index 68b4a8b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_f32.c
- * Description: Floating-point IIR Lattice filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
- *
- * This set of functions implements lattice filters
- * for Q15, Q31 and floating-point data types. Lattice filters are used in a
- * variety of adaptive filter applications. The filter structure has feedforward and
- * feedback components and the net impulse response is infinite length.
- * The functions operate on blocks
- * of input and output data and each call to the function processes
- * blockSize samples through the filter. pSrc and
- * pDst point to input and output arrays containing blockSize values.
-
- * \par Algorithm:
- * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
- *
- * fN(n) = x(n)
- * fm-1(n) = fm(n) - km * gm-1(n-1) for m = N, N-1, ...1
- * gm(n) = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1
- * y(n) = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
- *
- * \par
- * pkCoeffs points to array of reflection coefficients of size numStages.
- * Reflection coefficients are stored in time-reversed order.
- * \par
- *
- * {kN, kN-1, ....k1}
- *
- * pvCoeffs points to the array of ladder coefficients of size (numStages+1).
- * Ladder coefficients are stored in time-reversed order.
- * \par
- *
- * {vN, vN-1, ...v0}
- *
- * pState points to a state array of size numStages + blockSize.
- * The state variables shown in the figure above (the g values) are stored in the pState array.
- * The state variables are updated after each block of data is processed; the coefficients are untouched.
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter.
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
- *
- *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
- *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
- *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
- *
- * \par
- * where numStages is the number of stages in the filter; pState points to the state buffer array;
- * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
-/**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t fnext1, gcurr1, gnext; /* Temporary variables for lattice stages */
- float32_t acc; /* Accumlator */
- uint32_t blkCnt, tapCnt; /* temporary variables for counts */
- float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
- uint32_t numStages = S->numStages; /* number of stages */
- float32_t *pState; /* State pointer */
- float32_t *pStateCurnt; /* State current pointer */
- float32_t k1, k2;
- float32_t v1, v2, v3, v4;
- float32_t gcurr2;
- float32_t fnext2;
-
- /* initialise loop count */
- blkCnt = blockSize;
-
- /* initialise state pointer */
- pState = &S->pState[0];
-
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fnext2 = *pSrc++;
-
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
-
- /* Set accumulator to zero */
- acc = 0.0;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = (numStages) >> 2;
-
- while (tapCnt > 0u)
- {
- /* Read gN-1(n-1) from state buffer */
- gcurr1 = *px1;
-
- /* read reflection coefficient kN */
- k1 = *pk;
-
- /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
- fnext1 = fnext2 - (k1 * gcurr1);
-
- /* read ladder coefficient vN */
- v1 = *pv;
-
- /* read next reflection coefficient kN-1 */
- k2 = *(pk + 1u);
-
- /* Read gN-2(n-1) from state buffer */
- gcurr2 = *(px1 + 1u);
-
- /* read next ladder coefficient vN-1 */
- v2 = *(pv + 1u);
-
- /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
- fnext2 = fnext1 - (k2 * gcurr2);
-
- /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
- gnext = gcurr1 + (k1 * fnext1);
-
- /* read reflection coefficient kN-2 */
- k1 = *(pk + 2u);
-
- /* write gN(n) into state for next sample processing */
- *px2++ = gnext;
-
- /* Read gN-3(n-1) from state buffer */
- gcurr1 = *(px1 + 2u);
-
- /* y(n) += gN(n) * vN */
- acc += (gnext * v1);
-
- /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
- fnext1 = fnext2 - (k1 * gcurr1);
-
- /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
- gnext = gcurr2 + (k2 * fnext2);
-
- /* Read gN-4(n-1) from state buffer */
- gcurr2 = *(px1 + 3u);
-
- /* y(n) += gN-1(n) * vN-1 */
- acc += (gnext * v2);
-
- /* read reflection coefficient kN-3 */
- k2 = *(pk + 3u);
-
- /* write gN-1(n) into state for next sample processing */
- *px2++ = gnext;
-
- /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
- fnext2 = fnext1 - (k2 * gcurr2);
-
- /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
- gnext = gcurr1 + (k1 * fnext1);
-
- /* read ladder coefficient vN-2 */
- v3 = *(pv + 2u);
-
- /* y(n) += gN-2(n) * vN-2 */
- acc += (gnext * v3);
-
- /* write gN-2(n) into state for next sample processing */
- *px2++ = gnext;
-
- /* update pointer */
- pk += 4u;
-
- /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
- gnext = (fnext2 * k2) + gcurr2;
-
- /* read next ladder coefficient vN-3 */
- v4 = *(pv + 3u);
-
- /* y(n) += gN-4(n) * vN-4 */
- acc += (gnext * v4);
-
- /* write gN-3(n) into state for next sample processing */
- *px2++ = gnext;
-
- /* update pointers */
- px1 += 4u;
- pv += 4u;
-
- tapCnt--;
-
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = (numStages) % 0x4u;
-
- while (tapCnt > 0u)
- {
- gcurr1 = *px1++;
- /* Process sample for last taps */
- fnext1 = fnext2 - ((*pk) * gcurr1);
- gnext = (fnext1 * (*pk++)) + gcurr1;
- /* Output samples for last taps */
- acc += (gnext * (*pv++));
- *px2++ = gnext;
- fnext2 = fnext1;
-
- tapCnt--;
-
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (fnext2 * (*pv));
-
- *px2++ = fnext2;
-
- /* write out into pDst */
- *pDst++ = acc;
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 1u;
-
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
-
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- tapCnt = numStages >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
-
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numStages) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-}
-
-#else
-
-void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */
- float32_t acc; /* Accumlator */
- uint32_t blkCnt, tapCnt; /* temporary variables for counts */
- float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
- uint32_t numStages = S->numStages; /* number of stages */
- float32_t *pState; /* State pointer */
- float32_t *pStateCurnt; /* State current pointer */
-
-
- /* Run the below code for Cortex-M0 */
-
- blkCnt = blockSize;
-
- pState = &S->pState[0];
-
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
- /* Set accumulator to zero */
- acc = 0.0f;
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
-
- /* Process sample for numStages */
- tapCnt = numStages;
-
- while (tapCnt > 0u)
- {
- gcurr = *px1++;
- /* Process sample for last taps */
- fnext = fcurr - ((*pk) * gcurr);
- gnext = (fnext * (*pk++)) + gcurr;
-
- /* Output samples for last taps */
- acc += (gnext * (*pv++));
- *px2++ = gnext;
- fcurr = fnext;
-
- /* Decrementing loop counter */
- tapCnt--;
-
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (fnext * (*pv));
-
- *px2++ = fnext;
-
- /* write out into pDst */
- *pDst++ = acc;
-
- /* Advance the state pointer by 1 to process the next group of samples */
- pState = pState + 1u;
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
-
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- tapCnt = numStages;
-
- /* Copy the data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-}
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
-/**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
deleted file mode 100644
index 530c7ff..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_init_f32.c
- * Description: Floating-point IIR lattice filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign reflection coefficient pointer */
- S->pkCoeffs = pkCoeffs;
-
- /* Assign ladder coefficient pointer */
- S->pvCoeffs = pvCoeffs;
-
- /* Clear state buffer and size is always blockSize + numStages */
- memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-
-}
-
- /**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
deleted file mode 100644
index 9b991f8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_init_q15.c
- * Description: Q15 IIR lattice filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
- /**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign reflection coefficient pointer */
- S->pkCoeffs = pkCoeffs;
-
- /* Assign ladder coefficient pointer */
- S->pvCoeffs = pvCoeffs;
-
- /* Clear state buffer and size is always blockSize + numStages */
- memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-
-}
-
-/**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
deleted file mode 100644
index 1543206..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_init_q31.c
- * Description: Initialization function for the Q31 IIR lattice filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numStages = numStages;
-
- /* Assign reflection coefficient pointer */
- S->pkCoeffs = pkCoeffs;
-
- /* Assign ladder coefficient pointer */
- S->pvCoeffs = pvCoeffs;
-
- /* Clear state buffer and size is always blockSize + numStages */
- memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
-
-}
-
-/**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
deleted file mode 100644
index 57e5794..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_q15.c
- * Description: Q15 IIR lattice filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-
-void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t fcurr, fnext, gcurr = 0, gnext; /* Temporary variables for lattice stages */
- q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
- uint32_t stgCnt; /* Temporary variables for counts */
- q63_t acc; /* Accumlator */
- uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
- q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
- uint32_t numStages = S->numStages; /* number of stages */
- q15_t *pState; /* State pointer */
- q15_t *pStateCurnt; /* State current pointer */
- q15_t out; /* Temporary variable for output */
- q31_t v; /* Temporary variable for ladder coefficient */
-#ifdef UNALIGNED_SUPPORT_DISABLE
- q15_t v1, v2;
-#endif
-
-
- blkCnt = blockSize;
-
- pState = &S->pState[0];
-
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
- /* Set accumulator to zero */
- acc = 0;
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
-
- /* Process sample for first tap */
- gcurr = *px1++;
- /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
- fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
- fnext = __SSAT(fnext, 16);
- /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
- gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
- gnext = __SSAT(gnext, 16);
- /* write gN(n) into state for next sample processing */
- *px2++ = (q15_t) gnext;
- /* y(n) += gN(n) * vN */
- acc += (q31_t) ((gnext * (*pv++)));
-
-
- /* Update f values for next coefficient processing */
- fcurr = fnext;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = (numStages - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
-
- /* Process sample for 2nd, 6th ...taps */
- /* Read gN-2(n-1) from state buffer */
- gcurr = *px1++;
- /* Process sample for 2nd, 6th .. taps */
- /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
- fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
- fnext = __SSAT(fnext, 16);
- /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
- gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
- gnext1 = (q15_t) __SSAT(gnext, 16);
- /* write gN-1(n) into state */
- *px2++ = (q15_t) gnext1;
-
-
- /* Process sample for 3nd, 7th ...taps */
- /* Read gN-3(n-1) from state */
- gcurr = *px1++;
- /* Process sample for 3rd, 7th .. taps */
- /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
- fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
- fcurr = __SSAT(fcurr, 16);
- /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
- gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
- gnext2 = (q15_t) __SSAT(gnext, 16);
- /* write gN-2(n) into state */
- *px2++ = (q15_t) gnext2;
-
- /* Read vN-1 and vN-2 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- v = *__SIMD32(pv)++;
-
-#else
-
- v1 = *pv++;
- v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- v = __PKHBT(v1, v2, 16);
-
-#else
-
- v = __PKHBT(v2, v1, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
- /* Pack gN-1(n) and gN-2(n) */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
- gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* y(n) += gN-1(n) * vN-1 */
- /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
- /* y(n) += gN-2(n) * vN-2 */
- /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
- acc = __SMLALD(gnext, v, acc);
-
-
- /* Process sample for 4th, 8th ...taps */
- /* Read gN-4(n-1) from state */
- gcurr = *px1++;
- /* Process sample for 4th, 8th .. taps */
- /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
- fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
- fnext = __SSAT(fnext, 16);
- /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
- gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
- gnext1 = (q15_t) __SSAT(gnext, 16);
- /* write gN-3(n) for the next sample process */
- *px2++ = (q15_t) gnext1;
-
-
- /* Process sample for 5th, 9th ...taps */
- /* Read gN-5(n-1) from state */
- gcurr = *px1++;
- /* Process sample for 5th, 9th .. taps */
- /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
- fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
- fcurr = __SSAT(fcurr, 16);
- /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
- gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
- gnext2 = (q15_t) __SSAT(gnext, 16);
- /* write gN-4(n) for the next sample process */
- *px2++ = (q15_t) gnext2;
-
- /* Read vN-3 and vN-4 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- v = *__SIMD32(pv)++;
-
-#else
-
- v1 = *pv++;
- v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- v = __PKHBT(v1, v2, 16);
-
-#else
-
- v = __PKHBT(v2, v1, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
- /* Pack gN-3(n) and gN-4(n) */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
- gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* y(n) += gN-4(n) * vN-4 */
- /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
- /* y(n) += gN-3(n) * vN-3 */
- /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
- acc = __SMLALD(gnext, v, acc);
-
- tapCnt--;
-
- }
-
- fnext = fcurr;
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = (numStages - 1u) % 0x4u;
-
- while (tapCnt > 0u)
- {
- gcurr = *px1++;
- /* Process sample for last taps */
- fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
- fnext = __SSAT(fnext, 16);
- gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
- gnext = __SSAT(gnext, 16);
- /* Output samples for last taps */
- acc += (q31_t) (((q31_t) gnext * (*pv++)));
- *px2++ = (q15_t) gnext;
- fcurr = fnext;
-
- tapCnt--;
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (q31_t) (((q31_t) fnext * (*pv++)));
-
- out = (q15_t) __SSAT(acc >> 15, 16);
- *px2++ = (q15_t) fnext;
-
- /* write out into pDst */
- *pDst++ = out;
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 1u;
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- stgCnt = (numStages >> 2u);
-
- /* copy data */
- while (stgCnt > 0u)
- {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- stgCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- stgCnt = (numStages) % 0x4u;
-
- /* copy data */
- while (stgCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- stgCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
- uint32_t stgCnt; /* Temporary variables for counts */
- q63_t acc; /* Accumlator */
- uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
- q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
- uint32_t numStages = S->numStages; /* number of stages */
- q15_t *pState; /* State pointer */
- q15_t *pStateCurnt; /* State current pointer */
- q15_t out; /* Temporary variable for output */
-
-
- blkCnt = blockSize;
-
- pState = &S->pState[0];
-
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
- /* Set accumulator to zero */
- acc = 0;
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
- tapCnt = numStages;
-
- while (tapCnt > 0u)
- {
- gcurr = *px1++;
- /* Process sample */
- /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
- fnext = fcurr - ((gcurr * (*pk)) >> 15);
- fnext = __SSAT(fnext, 16);
- /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
- gnext = ((fnext * (*pk++)) >> 15) + gcurr;
- gnext = __SSAT(gnext, 16);
- /* Output samples */
- /* y(n) += gN(n) * vN */
- acc += (q31_t) ((gnext * (*pv++)));
- /* write gN(n) into state for next sample processing */
- *px2++ = (q15_t) gnext;
- /* Update f values for next coefficient processing */
- fcurr = fnext;
-
- tapCnt--;
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (q31_t) ((fnext * (*pv++)));
-
- out = (q15_t) __SSAT(acc >> 15, 16);
- *px2++ = (q15_t) fnext;
-
- /* write out into pDst */
- *pDst++ = out;
-
- /* Advance the state pointer by 1 to process the next group of samples */
- pState = pState + 1u;
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- stgCnt = numStages;
-
- /* copy data */
- while (stgCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- stgCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
-
-
-/**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
deleted file mode 100644
index c2922af..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_iir_lattice_q31.c
- * Description: Q31 IIR lattice filter processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup IIR_Lattice
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
- * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
- */
-
-void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
- q63_t acc; /* Accumlator */
- uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
- q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
- uint32_t numStages = S->numStages; /* number of stages */
- q31_t *pState; /* State pointer */
- q31_t *pStateCurnt; /* State current pointer */
-
- blkCnt = blockSize;
-
- pState = &S->pState[0];
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
- /* Set accumulator to zero */
- acc = 0;
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
-
- /* Process sample for first tap */
- gcurr = *px1++;
- /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
- fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
- /* write gN-1(n-1) into state for next sample processing */
- *px2++ = gnext;
- /* y(n) += gN(n) * vN */
- acc += ((q63_t) gnext * *pv++);
-
- /* Update f values for next coefficient processing */
- fcurr = fnext;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = (numStages - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
-
- /* Process sample for 2nd, 6th .. taps */
- /* Read gN-2(n-1) from state buffer */
- gcurr = *px1++;
- /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
- fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
- /* y(n) += gN-1(n) * vN-1 */
- /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
- acc += ((q63_t) gnext * *pv++);
- /* write gN-1(n) into state for next sample processing */
- *px2++ = gnext;
-
- /* Process sample for 3nd, 7th ...taps */
- /* Read gN-3(n-1) from state buffer */
- gcurr = *px1++;
- /* Process sample for 3rd, 7th .. taps */
- /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
- fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
- /* y(n) += gN-2(n) * vN-2 */
- /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
- acc += ((q63_t) gnext * *pv++);
- /* write gN-2(n) into state for next sample processing */
- *px2++ = gnext;
-
-
- /* Process sample for 4th, 8th ...taps */
- /* Read gN-4(n-1) from state buffer */
- gcurr = *px1++;
- /* Process sample for 4th, 8th .. taps */
- /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
- fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
- /* y(n) += gN-3(n) * vN-3 */
- /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
- acc += ((q63_t) gnext * *pv++);
- /* write gN-3(n) into state for next sample processing */
- *px2++ = gnext;
-
-
- /* Process sample for 5th, 9th ...taps */
- /* Read gN-5(n-1) from state buffer */
- gcurr = *px1++;
- /* Process sample for 5th, 9th .. taps */
- /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
- fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
- /* y(n) += gN-4(n) * vN-4 */
- /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
- acc += ((q63_t) gnext * *pv++);
- /* write gN-4(n) into state for next sample processing */
- *px2++ = gnext;
-
- tapCnt--;
-
- }
-
- fnext = fcurr;
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = (numStages - 1u) % 0x4u;
-
- while (tapCnt > 0u)
- {
- gcurr = *px1++;
- /* Process sample for last taps */
- fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
- gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
- /* Output samples for last taps */
- acc += ((q63_t) gnext * *pv++);
- *px2++ = gnext;
- fcurr = fnext;
-
- tapCnt--;
-
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (q63_t) fnext *(
- *pv++);
-
- *px2++ = fnext;
-
- /* write out into pDst */
- *pDst++ = (q31_t) (acc >> 31u);
-
- /* Advance the state pointer by 4 to process the next group of 4 samples */
- pState = pState + 1u;
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
-
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- tapCnt = numStages >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
-
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numStages) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- };
-
-#else
-
- /* Run the below code for Cortex-M0 */
- /* Sample processing */
- while (blkCnt > 0u)
- {
- /* Read Sample from input buffer */
- /* fN(n) = x(n) */
- fcurr = *pSrc++;
-
- /* Initialize state read pointer */
- px1 = pState;
- /* Initialize state write pointer */
- px2 = pState;
- /* Set accumulator to zero */
- acc = 0;
- /* Initialize Ladder coeff pointer */
- pv = &S->pvCoeffs[0];
- /* Initialize Reflection coeff pointer */
- pk = &S->pkCoeffs[0];
-
- tapCnt = numStages;
-
- while (tapCnt > 0u)
- {
- gcurr = *px1++;
- /* Process sample */
- /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
- fnext =
- clip_q63_to_q31(((q63_t) fcurr -
- ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
- /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
- gnext =
- clip_q63_to_q31(((q63_t) gcurr +
- ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
- /* Output samples */
- /* y(n) += gN(n) * vN */
- acc += ((q63_t) gnext * *pv++);
- /* write gN-1(n-1) into state for next sample processing */
- *px2++ = gnext;
- /* Update f values for next coefficient processing */
- fcurr = fnext;
-
- tapCnt--;
- }
-
- /* y(n) += g0(n) * v0 */
- acc += (q63_t) fnext *(
- *pv++);
-
- *px2++ = fnext;
-
- /* write out into pDst */
- *pDst++ = (q31_t) (acc >> 31u);
-
- /* Advance the state pointer by 1 to process the next group of samples */
- pState = pState + 1u;
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy last S->numStages samples to start of the buffer
- for the preperation of next frame process */
-
- /* Points to the start of the state buffer */
- pStateCurnt = &S->pState[0];
- pState = &S->pState[blockSize];
-
- tapCnt = numStages;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
-
-
-/**
- * @} end of IIR_Lattice group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
deleted file mode 100644
index 329d64f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_f32.c
- * Description: Processing function for the floating-point LMS filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup LMS Least Mean Square (LMS) Filters
- *
- * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
- * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
- * Adaptive filters are often used in communication systems, equalizers, and noise removal.
- * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
- * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
- *
- * An LMS filter consists of two components as shown below.
- * The first component is a standard transversal or FIR filter.
- * The second component is a coefficient update mechanism.
- * The LMS filter has two input signals.
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
- * This "error signal" tends towards zero as the filter adapts.
- * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
- * \image html LMS.gif "Internal structure of the Least Mean Square filter"
- *
- * The functions operate on blocks of data and each call to the function processes
- * blockSize samples through the filter.
- * pSrc points to input signal, pRef points to reference signal,
- * pOut points to output signal and pErr points to error signal.
- * All arrays contain blockSize values.
- *
- * The functions operate on a block-by-block basis.
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
- *
- * \par Algorithm:
- * The output signal y[n] is computed by a standard FIR filter:
- *
- * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
- *
- *
- * \par
- * The error signal equals the difference between the reference signal d[n] and the filter output:
- *
- * e[n] = d[n] - y[n].
- *
- *
- * \par
- * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:
- *
- * b[k] = b[k] + e[n] * mu * x[n-k], for k=0, 1, ..., numTaps-1
- *
- * where mu is the step size and controls the rate of coefficient convergence.
- *\par
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.
- * Coefficients are stored in time reversed order.
- * \par
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to a state array of size numTaps + blockSize - 1.
- * Samples in the state buffer are stored in the order:
- * \par
- *
- * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
- *
- * \par
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
- * to be avoided and yields a significant speed improvement.
- * The state variables are updated after each block of data is processed.
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter and
- * coefficient and state arrays cannot be shared among instances.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
- *
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Set the values in the state buffer to zeros before static initialization.
- * The code below statically initializes each of the 3 different data type filter instance structures
- *
- * arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
- * arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
- * arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
- *
- * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
- * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.
- *
- * \par Fixed-Point Behavior:
- * Care must be taken when using the Q15 and Q31 versions of the LMS filter.
- * The following issues must be considered:
- * - Scaling of coefficients
- * - Overflow and saturation
- *
- * \par Scaling of Coefficients:
- * Filter coefficients are represented as fractional values and
- * coefficients are restricted to lie in the range [-1 +1).
- * The fixed-point functions have an additional scaling parameter postShift.
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
- * This essentially scales the filter coefficients by 2^postShift and
- * allows the filter coefficients to exceed the range [+1 -1).
- * The value of postShift is set by the user based on the expected gain through the system being modeled.
- *
- * \par Overflow and Saturation:
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
- * described separately as part of the function specific documentation below.
- */
-
-/**
- * @addtogroup LMS
- * @{
- */
-
-/**
- * @details
- * This function operates on floating-point data types.
- *
- * @brief Processing function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- float32_t mu = S->mu; /* Adaptive factor */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- float32_t sum, e, d; /* accumulator, error, reference data sample */
- float32_t w = 0.0f; /* weight factor */
-
- e = 0.0f;
- d = 0.0f;
-
- /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- blkCnt = blockSize;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Set the accumulator to zero */
- sum = 0.0f;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result in the accumulator, store in the destination buffer. */
- *pOut++ = sum;
-
- /* Compute and store error */
- d = (float32_t) (*pRef++);
- e = d - sum;
- *pErr++ = e;
-
- /* Calculation of Weighting factor for the updating filter coefficients */
- w = e * mu;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb = *pb + (w * (*px++));
- pb++;
-
- *pb = *pb + (w * (*px++));
- pb++;
-
- *pb = *pb + (w * (*px++));
- pb++;
-
- *pb = *pb + (w * (*px++));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb = *pb + (w * (*px++));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Loop unrolling for (numTaps - 1u) samples copy */
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Set the accumulator to zero */
- sum = 0.0f;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result is stored in the destination buffer. */
- *pOut++ = sum;
-
- /* Compute and store error */
- d = (float32_t) (*pRef++);
- e = d - sum;
- *pErr++ = e;
-
- /* Weighting factor for the LMS version */
- w = e * mu;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb = *pb + (w * (*px++));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- * start of the state buffer. This prepares the state buffer for the
- * next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Copy (numTaps - 1u) samples */
- tapCnt = (numTaps - 1u);
-
- /* Copy the data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
deleted file mode 100644
index 9fc87f1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_init_f32.c
- * Description: Floating-point LMS filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup LMS
- * @{
- */
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-/**
- * \par Description:
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * The initial filter coefficients serve as a starting point for the adaptive filter.
- * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().
- */
-
-void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps */
- memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
deleted file mode 100644
index cdc154d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_init_q15.c
- * Description: Q15 LMS filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS
- * @{
- */
-
-/**
-* @brief Initialization function for the Q15 LMS filter.
-* @param[in] *S points to an instance of the Q15 LMS filter structure.
-* @param[in] numTaps number of filter coefficients.
-* @param[in] *pCoeffs points to the coefficient buffer.
-* @param[in] *pState points to the state buffer.
-* @param[in] mu step size that controls filter coefficient updates.
-* @param[in] blockSize number of samples to process.
-* @param[in] postShift bit shift applied to coefficients.
-* @return none.
-*
-* \par Description:
-* pCoeffs points to the array of filter coefficients stored in time reversed order:
-*
-* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
-*
-* The initial filter coefficients serve as a starting point for the adaptive filter.
-* pState points to the array of state variables and size of array is
-* numTaps+blockSize-1 samples, where blockSize is the number of
-* input samples processed by each call to arm_lms_q15().
-*/
-
-void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps - 1 */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-
- /* Assign postShift value to be applied */
- S->postShift = postShift;
-
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
deleted file mode 100644
index 0972875..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_init_q31.c
- * Description: Q31 LMS filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS
- * @{
- */
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- *
- * \par Description:
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * The initial filter coefficients serve as a starting point for the adaptive filter.
- * pState points to an array of length numTaps+blockSize-1 samples,
- * where blockSize is the number of input samples processed by each call to
- * arm_lms_q31().
- */
-
-void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps - 1 */
- memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-
- /* Assign postShift value to be applied */
- S->postShift = postShift;
-
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
deleted file mode 100644
index 41ecee5..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_f32.c
- * Description: Processing function for the floating-point Normalised LMS
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @defgroup LMS_NORM Normalized LMS Filters
- *
- * This set of functions implements a commonly used adaptive filter.
- * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
- * factor which increases the adaptation rate of the filter.
- * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
- *
- * A normalized least mean square (NLMS) filter consists of two components as shown below.
- * The first component is a standard transversal or FIR filter.
- * The second component is a coefficient update mechanism.
- * The NLMS filter has two input signals.
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
- * This "error signal" tends towards zero as the filter adapts.
- * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
- * \image html LMS.gif "Internal structure of the NLMS adaptive filter"
- *
- * The functions operate on blocks of data and each call to the function processes
- * blockSize samples through the filter.
- * pSrc points to input signal, pRef points to reference signal,
- * pOut points to output signal and pErr points to error signal.
- * All arrays contain blockSize values.
- *
- * The functions operate on a block-by-block basis.
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
- *
- * \par Algorithm:
- * The output signal y[n] is computed by a standard FIR filter:
- *
- * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
- *
- *
- * \par
- * The error signal equals the difference between the reference signal d[n] and the filter output:
- *
- * e[n] = d[n] - y[n].
- *
- *
- * \par
- * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
- *
- * E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
- *
- * The filter coefficients b[k] are then updated on a sample-by-sample basis:
- *
- * b[k] = b[k] + e[n] * (mu/E) * x[n-k], for k=0, 1, ..., numTaps-1
- *
- * where mu is the step size and controls the rate of coefficient convergence.
- *\par
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.
- * Coefficients are stored in time reversed order.
- * \par
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * \par
- * pState points to a state array of size numTaps + blockSize - 1.
- * Samples in the state buffer are stored in the order:
- * \par
- *
- * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
- *
- * \par
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
- * to be avoided and yields a significant speed improvement.
- * The state variables are updated after each block of data is processed.
- * \par Instance Structure
- * The coefficients and state variables for a filter are stored together in an instance data structure.
- * A separate instance structure must be defined for each filter and
- * coefficient and state arrays cannot be shared among instances.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Zeros out the values in the state buffer.
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
- * For Q7, Q15, and Q31 the following fields must also be initialized;
- * recipTable, postShift
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- * \par Fixed-Point Behavior:
- * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
- * The following issues must be considered:
- * - Scaling of coefficients
- * - Overflow and saturation
- *
- * \par Scaling of Coefficients:
- * Filter coefficients are represented as fractional values and
- * coefficients are restricted to lie in the range [-1 +1).
- * The fixed-point functions have an additional scaling parameter postShift.
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
- * This essentially scales the filter coefficients by 2^postShift and
- * allows the filter coefficients to exceed the range [+1 -1).
- * The value of postShift is set by the user based on the expected gain through the system being modeled.
- *
- * \par Overflow and Saturation:
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
- * described separately as part of the function specific documentation below.
- */
-
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
-void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize)
-{
- float32_t *pState = S->pState; /* State pointer */
- float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- float32_t *pStateCurnt; /* Points to the current sample of the state */
- float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- float32_t mu = S->mu; /* Adaptive factor */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- float32_t energy; /* Energy of the input */
- float32_t sum, e, d; /* accumulator, error, reference data sample */
- float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
-
- /* Initializations of error, difference, Coefficient update */
- e = 0.0f;
- d = 0.0f;
- w = 0.0f;
-
- energy = S->energy;
- x0 = S->x0;
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy -= x0 * x0;
- energy += in * in;
-
- /* Set the accumulator to zero */
- sum = 0.0f;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result in the accumulator, store in the destination buffer. */
- *pOut++ = sum;
-
- /* Compute and store error */
- d = (float32_t) (*pRef++);
- e = d - sum;
- *pErr++ = e;
-
- /* Calculation of Weighting factor for updating filter coefficients */
- /* epsilon value 0.000000119209289f */
- w = (e * mu) / (energy + 0.000000119209289f);
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb += w * (*px++);
- pb++;
-
- *pb += w * (*px++);
- pb++;
-
- *pb += w * (*px++);
- pb++;
-
- *pb += w * (*px++);
- pb++;
-
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb += w * (*px++);
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- S->energy = energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Loop unrolling for (numTaps - 1u)/4 samples copy */
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy -= x0 * x0;
- energy += in * in;
-
- /* Set the accumulator to zero */
- sum = 0.0f;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- sum += (*px++) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* The result in the accumulator is stored in the destination buffer. */
- *pOut++ = sum;
-
- /* Compute and store error */
- d = (float32_t) (*pRef++);
- e = d - sum;
- *pErr++ = e;
-
- /* Calculation of Weighting factor for updating filter coefficients */
- /* epsilon value 0.000000119209289f */
- w = (e * mu) / (energy + 0.000000119209289f);
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCcoeffs pointer */
- pb = pCoeffs;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- *pb += w * (*px++);
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- S->energy = energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Copy (numTaps - 1u) samples */
- tapCnt = (numTaps - 1u);
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
deleted file mode 100644
index 7dd8f91..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_init_f32.c
- * Description: Floating-point NLMS filter initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * \par Description:
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * The initial filter coefficients serve as a starting point for the adaptive filter.
- * pState points to an array of length numTaps+blockSize-1 samples,
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().
- */
-
-void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps - 1 */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-
- /* Initialise Energy to zero */
- S->energy = 0.0f;
-
- /* Initialise x0 to zero */
- S->x0 = 0.0f;
-
-}
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
deleted file mode 100644
index 5f2acb3..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_init_q15.c
- * Description: Q15 NLMS initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * The initial filter coefficients serve as a starting point for the adaptive filter.
- * pState points to the array of state variables and size of array is
- * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed
- * by each call to arm_lms_norm_q15().
- */
-
-void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps - 1 */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
- /* Assign post Shift value applied to coefficients */
- S->postShift = postShift;
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-
- /* Initialize reciprocal pointer table */
- S->recipTable = (q15_t *) armRecipTableQ15;
-
- /* Initialise Energy to zero */
- S->energy = 0;
-
- /* Initialise x0 to zero */
- S->x0 = 0;
-
-}
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
deleted file mode 100644
index a6dc990..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_init_q31.c
- * Description: Q31 NLMS initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- *
- * Description:
- * \par
- * pCoeffs points to the array of filter coefficients stored in time reversed order:
- *
- * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
- *
- * The initial filter coefficients serve as a starting point for the adaptive filter.
- * pState points to an array of length numTaps+blockSize-1 samples,
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().
- */
-
-void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift)
-{
- /* Assign filter taps */
- S->numTaps = numTaps;
-
- /* Assign coefficient pointer */
- S->pCoeffs = pCoeffs;
-
- /* Clear state buffer and size is always blockSize + numTaps - 1 */
- memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
- /* Assign post Shift value applied to coefficients */
- S->postShift = postShift;
-
- /* Assign state pointer */
- S->pState = pState;
-
- /* Assign Step size value */
- S->mu = mu;
-
- /* Initialize reciprocal pointer table */
- S->recipTable = (q31_t *) armRecipTableQ31;
-
- /* Initialise Energy to zero */
- S->energy = 0;
-
- /* Initialise x0 to zero */
- S->x0 = 0;
-
-}
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
deleted file mode 100644
index a3c0d8d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_q15.c
- * Description: Q15 NLMS filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
-/**
-* @brief Processing function for Q15 normalized LMS filter.
-* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[in] *pRef points to the block of reference data.
-* @param[out] *pOut points to the block of output data.
-* @param[out] *pErr points to the block of error data.
-* @param[in] blockSize number of samples to process.
-* @return none.
-*
-* Scaling and Overflow Behavior:
-* \par
-* The function is implemented using a 64-bit internal accumulator.
-* Both coefficients and state variables are represented in 1.15 format and
-* multiplications yield a 2.30 result. The 2.30 intermediate results are
-* accumulated in a 64-bit accumulator in 34.30 format.
-* There is no risk of internal overflow with this approach and the full
-* precision of intermediate multiplications is preserved. After all additions
-* have been performed, the accumulator is truncated to 34.15 format by
-* discarding low 15 bits. Lastly, the accumulator is saturated to yield a
-* result in 1.15 format.
-*
-* \par
-* In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
-*
- */
-
-void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- q15_t mu = S->mu; /* Adaptive factor */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- q31_t energy; /* Energy of the input */
- q63_t acc; /* Accumulator */
- q15_t e = 0, d = 0; /* error, reference data sample */
- q15_t w = 0, in; /* weight factor and state */
- q15_t x0; /* temporary variable to hold input sample */
- //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
- q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
- q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
- q31_t coef; /* Teporary variable for coefficient */
- q31_t acc_l, acc_h;
- int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
- int32_t uShift = (32 - lShift);
-
- energy = S->energy;
- x0 = S->x0;
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy -= (((q31_t) x0 * (x0)) >> 15);
- energy += (((q31_t) in * (in)) >> 15);
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
-
- /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
- acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
- acc += (((q31_t) * px++ * (*pb++)));
- acc += (((q31_t) * px++ * (*pb++)));
- acc += (((q31_t) * px++ * (*pb++)));
- acc += (((q31_t) * px++ * (*pb++)));
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += (((q31_t) * px++ * (*pb++)));
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Converting the result to 1.15 format and saturate the output */
- acc = __SSAT(acc, 16u);
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q15_t) acc;
-
- /* Compute and store error */
- d = *pRef++;
- e = d - (q15_t) acc;
- *pErr++ = e;
-
- /* Calculation of 1/energy */
- postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
- &oneByEnergy, S->recipTable);
-
- /* Calculation of e * mu value */
- errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
- /* Calculation of (e * mu) * (1/energy) value */
- acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
- /* Weighting factor for the normalized version */
- w = (q15_t) __SSAT((q31_t) acc, 16);
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Read the sample from state buffer */
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Save energy and x0 values for the next frame */
- S->energy = (q15_t) energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Calculation of count for copying integer writes */
- tapCnt = (numTaps - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
-#endif
-
- tapCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy -= (((q31_t) x0 * (x0)) >> 15);
- energy += (((q31_t) in * (in)) >> 15);
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += (((q31_t) * px++ * (*pb++)));
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Converting the result to 1.15 format and saturate the output */
- acc = __SSAT(acc, 16u);
-
- /* Converting the result to 1.15 format */
- //acc = __SSAT((acc >> (16u - shift)), 16u);
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q15_t) acc;
-
- /* Compute and store error */
- d = *pRef++;
- e = d - (q15_t) acc;
- *pErr++ = e;
-
- /* Calculation of 1/energy */
- postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
- &oneByEnergy, S->recipTable);
-
- /* Calculation of e * mu value */
- errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
- /* Calculation of (e * mu) * (1/energy) value */
- acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
- /* Weighting factor for the normalized version */
- w = (q15_t) __SSAT((q31_t) acc, 16);
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = *pb + (((q31_t) w * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Read the sample from state buffer */
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Save energy and x0 values for the next frame */
- S->energy = (q15_t) energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* copy (numTaps - 1u) data */
- tapCnt = (numTaps - 1u);
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
deleted file mode 100644
index 247d5ab..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_norm_q31.c
- * Description: Processing function for the Q31 NLMS filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS_NORM
- * @{
- */
-
-/**
-* @brief Processing function for Q31 normalized LMS filter.
-* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-* @param[in] *pSrc points to the block of input data.
-* @param[in] *pRef points to the block of reference data.
-* @param[out] *pOut points to the block of output data.
-* @param[out] *pErr points to the block of error data.
-* @param[in] blockSize number of samples to process.
-* @return none.
-*
-* Scaling and Overflow Behavior:
-* \par
-* The function is implemented using an internal 64-bit accumulator.
-* The accumulator has a 2.62 format and maintains full precision of the intermediate
-* multiplication results but provides only a single guard bit.
-* Thus, if the accumulator result overflows it wraps around rather than clip.
-* In order to avoid overflows completely the input signal must be scaled down by
-* log2(numTaps) bits. The reference signal should not be scaled down.
-* After all multiply-accumulates are performed, the 2.62 accumulator is shifted
-* and saturated to 1.31 format to yield the final result.
-* The output signal and error signal are in 1.31 format.
-*
-* \par
-* In this filter, filter coefficients are updated for each sample and the
-* updation of filter cofficients are saturted.
-*
-*/
-
-void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
- q31_t mu = S->mu; /* Adaptive factor */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- q63_t energy; /* Energy of the input */
- q63_t acc; /* Accumulator */
- q31_t e = 0, d = 0; /* error, reference data sample */
- q31_t w = 0, in; /* weight factor and state */
- q31_t x0; /* temporary variable to hold input sample */
-// uint32_t shift = 32u - ((uint32_t) S->postShift + 1u); /* Shift to be applied to the output */
- q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
- q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
- q31_t coef; /* Temporary variable for coef */
- q31_t acc_l, acc_h; /* temporary input */
- uint32_t uShift = ((uint32_t) S->postShift + 1u);
- uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
-
- energy = S->energy;
- x0 = S->x0;
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- while (blkCnt > 0u)
- {
-
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy = (q31_t) ((((q63_t) energy << 32) -
- (((q63_t) x0 * x0) << 1)) >> 32);
- energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += ((q63_t) (*px++)) * (*pb++);
- acc += ((q63_t) (*px++)) * (*pb++);
- acc += ((q63_t) (*px++)) * (*pb++);
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Converting the result to 1.31 format */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q31_t) acc;
-
- /* Compute and store error */
- d = *pRef++;
- e = d - (q31_t) acc;
- *pErr++ = e;
-
- /* Calculates the reciprocal of energy */
- postShift = arm_recip_q31(energy + DELTA_Q31,
- &oneByEnergy, &S->recipTable[0]);
-
- /* Calculation of product of (e * mu) */
- errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
- /* Weighting factor for the normalized version */
- w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
-
- /* coef is in 2.30 format */
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- /* get coef in 1.31 format by left shifting */
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- /* update coefficient buffer to next coefficient */
- pb++;
-
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Read the sample from state buffer */
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Save energy and x0 values for the next frame */
- S->energy = (q31_t) energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Loop unrolling for (numTaps - 1u) samples copy */
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (blkCnt > 0u)
- {
-
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Read the sample from input buffer */
- in = *pSrc++;
-
- /* Update the energy calculation */
- energy =
- (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
- energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Converting the result to 1.31 format */
- /* Converting the result to 1.31 format */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-
- //acc = (q31_t) (acc >> shift);
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q31_t) acc;
-
- /* Compute and store error */
- d = *pRef++;
- e = d - (q31_t) acc;
- *pErr++ = e;
-
- /* Calculates the reciprocal of energy */
- postShift =
- arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
-
- /* Calculation of product of (e * mu) */
- errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
- /* Weighting factor for the normalized version */
- w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize coeff pointer */
- pb = (pCoeffs);
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- /* coef is in 2.30 format */
- coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
- /* get coef in 1.31 format by left shifting */
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- /* update coefficient buffer to next coefficient */
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Read the sample from state buffer */
- x0 = *pState;
-
- /* Advance state pointer by 1 for the next sample */
- pState = pState + 1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Save energy and x0 values for the next frame */
- S->energy = (q31_t) energy;
- S->x0 = x0;
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- start of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Loop for (numTaps - 1u) samples copy */
- tapCnt = (numTaps - 1u);
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of LMS_NORM group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
deleted file mode 100644
index 323e0cf..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_q15.c
- * Description: Processing function for the Q15 LMS filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS
- * @{
- */
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * \par Scaling and Overflow Behavior:
- * The function is implemented using a 64-bit internal accumulator.
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- *
- * \par
- * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
- *
- */
-
-void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize)
-{
- q15_t *pState = S->pState; /* State pointer */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q15_t *pStateCurnt; /* Points to the current sample of the state */
- q15_t mu = S->mu; /* Adaptive factor */
- q15_t *px; /* Temporary pointer for state */
- q15_t *pb; /* Temporary pointer for coefficient buffer */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- q63_t acc; /* Accumulator */
- q15_t e = 0; /* error of data sample */
- q15_t alpha; /* Intermediate constant for taps update */
- q31_t coef; /* Teporary variable for coefficient */
- q31_t acc_l, acc_h;
- int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
- int32_t uShift = (32 - lShift);
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Initializing blkCnt with blockSize */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2u;
-
- while (tapCnt > 0u)
- {
- /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
- /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
- acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
- acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
- acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
- acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
- acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Converting the result to 1.15 format and saturate the output */
- acc = __SSAT(acc, 16);
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q15_t) acc;
-
- /* Compute and store error */
- e = *pRef++ - (q15_t) acc;
-
- *pErr++ = (q15_t) e;
-
- /* Compute alpha i.e. intermediate constant for taps update */
- alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
- /* Initialize state pointer */
- /* Advance state pointer by 1 for the next sample */
- px = pState++;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2u;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Calculation of count for copying integer writes */
- tapCnt = (numTaps - 1u) >> 2;
-
- while (tapCnt > 0u)
- {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
- *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-#else
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-#endif
-
- tapCnt--;
-
- }
-
- /* Calculation of count for remaining q15_t data */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += (q63_t) ((q31_t) (*px++) * (*pb++));
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- /* Apply shift for lower part of acc and upper part of acc */
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Converting the result to 1.15 format and saturate the output */
- acc = __SSAT(acc, 16);
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q15_t) acc;
-
- /* Compute and store error */
- e = *pRef++ - (q15_t) acc;
-
- *pErr++ = (q15_t) e;
-
- /* Compute alpha i.e. intermediate constant for taps update */
- alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
- /* Initialize pState pointer */
- /* Advance state pointer by 1 for the next sample */
- px = pState++;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
- *pb++ = (q15_t) __SSAT((coef), 16);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
-
- }
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- start of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Copy (numTaps - 1u) samples */
- tapCnt = (numTaps - 1u);
-
- /* Copy the data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
deleted file mode 100644
index 682e3c8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_lms_q31.c
- * Description: Processing function for the Q31 LMS filter
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-/**
- * @ingroup groupFilters
- */
-
-/**
- * @addtogroup LMS
- * @{
- */
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- *
- * \par Scaling and Overflow Behavior:
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate
- * multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clips.
- * In order to avoid overflows completely the input signal must be scaled down by
- * log2(numTaps) bits.
- * The reference signal should not be scaled down.
- * After all multiply-accumulates are performed, the 2.62 accumulator is shifted
- * and saturated to 1.31 format to yield the final result.
- * The output signal and error signal are in 1.31 format.
- *
- * \par
- * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
- */
-
-void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize)
-{
- q31_t *pState = S->pState; /* State pointer */
- uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
- q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
- q31_t *pStateCurnt; /* Points to the current sample of the state */
- q31_t mu = S->mu; /* Adaptive factor */
- q31_t *px; /* Temporary pointer for state */
- q31_t *pb; /* Temporary pointer for coefficient buffer */
- uint32_t tapCnt, blkCnt; /* Loop counters */
- q63_t acc; /* Accumulator */
- q31_t e = 0; /* error of data sample */
- q31_t alpha; /* Intermediate constant for taps update */
- q31_t coef; /* Temporary variable for coef */
- q31_t acc_l, acc_h; /* temporary input */
- uint32_t uShift = ((uint32_t) S->postShift + 1u);
- uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
-
- /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
- /* pStateCurnt points to the location where the new input data should be written */
- pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
- /* Initializing blkCnt with blockSize */
- blkCnt = blockSize;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize state pointer */
- px = pState;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- /* acc += b[N] * x[n-N] */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* acc += b[N-1] * x[n-N-1] */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* acc += b[N-2] * x[n-N-2] */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* acc += b[N-3] * x[n-N-3] */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Converting the result to 1.31 format */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- /* Store the result from accumulator into the destination buffer. */
- *pOut++ = (q31_t) acc;
-
- /* Compute and store error */
- e = *pRef++ - (q31_t) acc;
-
- *pErr++ = (q31_t) e;
-
- /* Compute alpha i.e. intermediate constant for taps update */
- alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
- /* Initialize state pointer */
- /* Advance state pointer by 1 for the next sample */
- px = pState++;
-
- /* Initialize coefficient pointer */
- pb = pCoeffs;
-
- /* Loop unrolling. Process 4 taps at a time. */
- tapCnt = numTaps >> 2;
-
- /* Update filter coefficients */
- while (tapCnt > 0u)
- {
- /* coef is in 2.30 format */
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- /* get coef in 1.31 format by left shifting */
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- /* update coefficient buffer to next coefficient */
- pb++;
-
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* If the filter length is not a multiple of 4, compute the remaining filter taps */
- tapCnt = numTaps % 0x4u;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- satrt of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Loop unrolling for (numTaps - 1u) samples copy */
- tapCnt = (numTaps - 1u) >> 2u;
-
- /* copy data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Calculate remaining number of copies */
- tapCnt = (numTaps - 1u) % 0x4u;
-
- /* Copy the remaining q31_t data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- while (blkCnt > 0u)
- {
- /* Copy the new input sample into the state buffer */
- *pStateCurnt++ = *pSrc++;
-
- /* Initialize pState pointer */
- px = pState;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Set the accumulator to zero */
- acc = 0;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- acc += ((q63_t) (*px++)) * (*pb++);
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Converting the result to 1.31 format */
- /* Store the result from accumulator into the destination buffer. */
- /* Calc lower part of acc */
- acc_l = acc & 0xffffffff;
-
- /* Calc upper part of acc */
- acc_h = (acc >> 32) & 0xffffffff;
-
- acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
- *pOut++ = (q31_t) acc;
-
- /* Compute and store error */
- e = *pRef++ - (q31_t) acc;
-
- *pErr++ = (q31_t) e;
-
- /* Weighting factor for the LMS version */
- alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
- /* Initialize pState pointer */
- /* Advance state pointer by 1 for the next sample */
- px = pState++;
-
- /* Initialize pCoeffs pointer */
- pb = pCoeffs;
-
- /* Loop over numTaps number of values */
- tapCnt = numTaps;
-
- while (tapCnt > 0u)
- {
- /* Perform the multiply-accumulate */
- coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
- *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
- pb++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Processing is complete. Now copy the last numTaps - 1 samples to the
- start of the state buffer. This prepares the state buffer for the
- next function call. */
-
- /* Points to the start of the pState buffer */
- pStateCurnt = S->pState;
-
- /* Copy (numTaps - 1u) samples */
- tapCnt = (numTaps - 1u);
-
- /* Copy the data */
- while (tapCnt > 0u)
- {
- *pStateCurnt++ = *pState++;
-
- /* Decrement the loop counter */
- tapCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of LMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c
deleted file mode 100644
index b49eda2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_add_f32.c
- * Description: Floating-point matrix addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixAdd Matrix Addition
- *
- * Adds two matrices.
- * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"
- *
- * The functions check to make sure that
- * pSrcA, pSrcB, and pDst have the same
- * number of rows and columns.
- */
-
-/**
- * @addtogroup MatrixAdd
- * @{
- */
-
-
-/**
- * @brief Floating-point matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
-
-#if defined (ARM_MATH_DSP)
-
- float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
-
-#endif // #if defined (ARM_MATH_DSP)
-
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif
- {
-
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Loop unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add and then store the results in the destination buffer. */
- /* Read values from source A */
- inA1 = pIn1[0];
-
- /* Read values from source B */
- inB1 = pIn2[0];
-
- /* Read values from source A */
- inA2 = pIn1[1];
-
- /* out = sourceA + sourceB */
- out1 = inA1 + inB1;
-
- /* Read values from source B */
- inB2 = pIn2[1];
-
- /* Read values from source A */
- inA1 = pIn1[2];
-
- /* out = sourceA + sourceB */
- out2 = inA2 + inB2;
-
- /* Read values from source B */
- inB1 = pIn2[2];
-
- /* Store result in destination */
- pOut[0] = out1;
- pOut[1] = out2;
-
- /* Read values from source A */
- inA2 = pIn1[3];
-
- /* Read values from source B */
- inB2 = pIn2[3];
-
- /* out = sourceA + sourceB */
- out1 = inA1 + inB1;
-
- /* out = sourceA + sourceB */
- out2 = inA2 + inB2;
-
- /* Store result in destination */
- pOut[2] = out1;
-
- /* Store result in destination */
- pOut[3] = out2;
-
-
- /* update pointers to process next sampels */
- pIn1 += 4u;
- pIn2 += 4u;
- pOut += 4u;
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add and then store the results in the destination buffer. */
- *pOut++ = (*pIn1++) + (*pIn2++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c
deleted file mode 100644
index f00fc64..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_add_q15.c
- * Description: Q15 matrix addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixAdd
- * @{
- */
-
-/**
- * @brief Q15 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst)
-{
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
- q15_t *pOut = pDst->pData; /* output data matrix pointer */
- uint16_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop unrolling */
- blkCnt = (uint32_t) numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add, Saturate and then store the results in the destination buffer. */
- *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
- *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = (uint32_t) numSamples % 0x4u;
-
- /* q15 pointers of input and output are initialized */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add, Saturate and then store the results in the destination buffer. */
- *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = (uint32_t) numSamples;
-
-
- /* q15 pointers of input and output are initialized */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add, Saturate and then store the results in the destination buffer. */
- *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c
deleted file mode 100644
index d7f3d34..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_add_q31.c
- * Description: Q31 matrix addition
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixAdd
- * @{
- */
-
-/**
- * @brief Q31 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- q31_t inA1, inB1; /* temporary variables */
-
-#if defined (ARM_MATH_DSP)
-
- q31_t inA2, inB2; /* temporary variables */
- q31_t out1, out2; /* temporary variables */
-
-#endif // #if defined (ARM_MATH_DSP)
-
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop Unrolling */
- blkCnt = numSamples >> 2u;
-
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add, saturate and then store the results in the destination buffer. */
- /* Read values from source A */
- inA1 = pIn1[0];
-
- /* Read values from source B */
- inB1 = pIn2[0];
-
- /* Read values from source A */
- inA2 = pIn1[1];
-
- /* Add and saturate */
- out1 = __QADD(inA1, inB1);
-
- /* Read values from source B */
- inB2 = pIn2[1];
-
- /* Read values from source A */
- inA1 = pIn1[2];
-
- /* Add and saturate */
- out2 = __QADD(inA2, inB2);
-
- /* Read values from source B */
- inB1 = pIn2[2];
-
- /* Store result in destination */
- pOut[0] = out1;
- pOut[1] = out2;
-
- /* Read values from source A */
- inA2 = pIn1[3];
-
- /* Read values from source B */
- inB2 = pIn2[3];
-
- /* Add and saturate */
- out1 = __QADD(inA1, inB1);
- out2 = __QADD(inA2, inB2);
-
- /* Store result in destination */
- pOut[2] = out1;
- pOut[3] = out2;
-
- /* update pointers to process next sampels */
- pIn1 += 4u;
- pIn2 += 4u;
- pOut += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) + B(m,n) */
- /* Add, saturate and then store the results in the destination buffer. */
- inA1 = *pIn1++;
- inB1 = *pIn2++;
-
- inA1 = __QADD(inA1, inB1);
-
- /* Decrement the loop counter */
- blkCnt--;
-
- *pOut++ = inA1;
-
- }
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixAdd group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
deleted file mode 100644
index 4f4cd3e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_cmplx_mult_f32.c
- * Description: Floating-point matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup CmplxMatrixMult Complex Matrix Multiplication
- *
- * Complex Matrix multiplication is only defined if the number of columns of the
- * first matrix equals the number of rows of the second matrix.
- * Multiplying an M x N matrix with an N x P matrix results
- * in an M x P matrix.
- * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
- * pSrcA and pSrcB are equal; and (2) that the size of the output
- * matrix equals the outer dimensions of pSrcA and pSrcB.
- */
-
-
-/**
- * @addtogroup CmplxMatrixMult
- * @{
- */
-
-/**
- * @brief Floating-point Complex matrix multiplication.
- * @param[in] *pSrcA points to the first input complex matrix structure
- * @param[in] *pSrcB points to the second input complex matrix structure
- * @param[out] *pDst points to output complex matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
- float32_t *px; /* Temporary output data matrix pointer */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- float32_t sumReal1, sumImag1; /* accumulator */
- float32_t a0, b0, c0, d0;
- float32_t a1, b1, c1, d1;
- float32_t sumReal2, sumImag2; /* accumulator */
-
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
-
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + 2 * i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- j = 0u;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sumReal1 = 0.0f;
- sumImag1 = 0.0f;
-
- sumReal2 = 0.0f;
- sumImag2 = 0.0f;
-
- /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
- pIn1 = pInA;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
-
- /* Reading real part of complex matrix A */
- a0 = *pIn1;
-
- /* Reading real part of complex matrix B */
- c0 = *pIn2;
-
- /* Reading imaginary part of complex matrix A */
- b0 = *(pIn1 + 1u);
-
- /* Reading imaginary part of complex matrix B */
- d0 = *(pIn2 + 1u);
-
- sumReal1 += a0 * c0;
- sumImag1 += b0 * c0;
-
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- sumReal2 -= b0 * d0;
- sumImag2 += a0 * d0;
-
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
- a1 = *pIn1;
- c1 = *pIn2;
-
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- sumReal1 += a1 * c1;
- sumImag1 += b1 * c1;
-
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- sumReal2 -= b1 * d1;
- sumImag2 += a1 * d1;
-
- a0 = *pIn1;
- c0 = *pIn2;
-
- b0 = *(pIn1 + 1u);
- d0 = *(pIn2 + 1u);
-
- sumReal1 += a0 * c0;
- sumImag1 += b0 * c0;
-
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- sumReal2 -= b0 * d0;
- sumImag2 += a0 * d0;
-
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
- a1 = *pIn1;
- c1 = *pIn2;
-
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- sumReal1 += a1 * c1;
- sumImag1 += b1 * c1;
-
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- sumReal2 -= b1 * d1;
- sumImag2 += a1 * d1;
-
- /* Decrement the loop count */
- colCnt--;
- }
-
- /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- colCnt = numColsA % 0x4u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- a1 = *pIn1;
- c1 = *pIn2;
-
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- sumReal1 += a1 * c1;
- sumImag1 += b1 * c1;
-
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- sumReal2 -= b1 * d1;
- sumImag2 += a1 * d1;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- sumReal1 += sumReal2;
- sumImag1 += sumImag2;
-
- /* Store the result in the destination buffer */
- *px++ = sumReal1;
- *px++ = sumImag1;
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- j++;
- pIn2 = pSrcB->pData + 2u * j;
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
- /* Update the pointer pInA to point to the starting address of the next row */
- i = i + numColsB;
- pInA = pInA + 2 * numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
deleted file mode 100644
index a805e60..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cmplx_mat_mult_q15.c
- * Description: Q15 complex matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup CmplxMatrixMult
- * @{
- */
-
-
-/**
- * @brief Q15 Complex matrix multiplication
- * @param[in] *pSrcA points to the first input complex matrix structure
- * @param[in] *pSrcB points to the second input complex matrix structure
- * @param[out] *pDst points to output complex matrix structure
- * @param[in] *pScratch points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * \par Conditions for optimum performance
- * Input, output and state buffers should be aligned by 32-bit
- *
- * \par Restrictions
- * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
- * In this case input, output, scratch buffers should be aligned by 32-bit
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator. The inputs to the
- * multiplications are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate
- * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
- * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
- * truncated to 34.15 format by discarding the low 15 bits and then saturated to
- * 1.15 format.
- *
- * \par
- * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function.
- *
- */
-
-
-
-
-arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch)
-{
- /* accumulator */
- q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
- q15_t *px; /* Temporary output data matrix pointer */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
- uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
- q63_t sumReal, sumImag;
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
- q15_t in; /* Temporary variable to hold the input value */
- q15_t a, b, c, d;
-#else
- q31_t in; /* Temporary variable to hold the input value */
- q31_t prod1, prod2;
- q31_t pSourceA, pSourceB;
-#endif
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif
- {
- /* Matrix transpose */
- do
- {
- /* Apply loop unrolling and exchange the columns with row elements */
- col = numColsB >> 2;
-
- /* The pointer px is set to starting address of the column being processed */
- px = pSrcBT + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (col > 0u)
- {
-#ifdef UNALIGNED_SUPPORT_DISABLE
- /* Read two elements from the row */
- in = *pInB++;
- *px = in;
- in = *pInB++;
- px[1] = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Read two elements from the row */
- in = *pInB++;
- *px = in;
- in = *pInB++;
- px[1] = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Read two elements from the row */
- in = *pInB++;
- *px = in;
- in = *pInB++;
- px[1] = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Read two elements from the row */
- in = *pInB++;
- *px = in;
- in = *pInB++;
- px[1] = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- col = numColsB % 0x4u;
-
- while (col > 0u)
- {
- /* Read two elements from the row */
- in = *pInB++;
- *px = in;
- in = *pInB++;
- px[1] = in;
-#else
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- *__SIMD32(px) = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- *__SIMD32(px) = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- *__SIMD32(px) = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- *__SIMD32(px) = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- col = numColsB % 0x4u;
-
- while (col > 0u)
- {
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- *__SIMD32(px) = in;
-#endif
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB * 2;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- i = i + 2u;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* Reset the variables for the usage in the following multiplication process */
- row = numRowsA;
- i = 0u;
- px = pDst->pData;
-
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the transposed pSrcB data */
- pInB = pSrcBT;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sumReal = 0;
- sumImag = 0;
-
- /* Apply loop unrolling and compute 2 MACs simultaneously. */
- colCnt = numColsA >> 1;
-
- /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
- pInA = pSrcA->pData + i * 2;
-
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- /* read real and imag values from pSrcA buffer */
- a = *pInA;
- b = *(pInA + 1u);
- /* read real and imag values from pSrcB buffer */
- c = *pInB;
- d = *(pInB + 1u);
-
- /* Multiply and Accumlates */
- sumReal += (q31_t) a *c;
- sumImag += (q31_t) a *d;
- sumReal -= (q31_t) b *d;
- sumImag += (q31_t) b *c;
-
- /* read next real and imag values from pSrcA buffer */
- a = *(pInA + 2u);
- b = *(pInA + 3u);
- /* read next real and imag values from pSrcB buffer */
- c = *(pInB + 2u);
- d = *(pInB + 3u);
-
- /* update pointer */
- pInA += 4u;
-
- /* Multiply and Accumlates */
- sumReal += (q31_t) a *c;
- sumImag += (q31_t) a *d;
- sumReal -= (q31_t) b *d;
- sumImag += (q31_t) b *c;
- /* update pointer */
- pInB += 4u;
-#else
- /* read real and imag values from pSrcA and pSrcB buffer */
- pSourceA = *__SIMD32(pInA)++;
- pSourceB = *__SIMD32(pInB)++;
-
- /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
- prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
- prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
- prod2 = __SMUADX(pSourceA, pSourceB);
- sumReal += (q63_t) prod1;
- sumImag += (q63_t) prod2;
-
- /* read real and imag values from pSrcA and pSrcB buffer */
- pSourceA = *__SIMD32(pInA)++;
- pSourceB = *__SIMD32(pInB)++;
-
- /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
- prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
- prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
- prod2 = __SMUADX(pSourceA, pSourceB);
- sumReal += (q63_t) prod1;
- sumImag += (q63_t) prod2;
-
-#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* process odd column samples */
- if ((numColsA & 0x1u) > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
- /* read real and imag values from pSrcA and pSrcB buffer */
- a = *pInA++;
- b = *pInA++;
- c = *pInB++;
- d = *pInB++;
-
- /* Multiply and Accumlates */
- sumReal += (q31_t) a *c;
- sumImag += (q31_t) a *d;
- sumReal -= (q31_t) b *d;
- sumImag += (q31_t) b *c;
-
-#else
- /* read real and imag values from pSrcA and pSrcB buffer */
- pSourceA = *__SIMD32(pInA)++;
- pSourceB = *__SIMD32(pInB)++;
-
- /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
- prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
- prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
- prod2 = __SMUADX(pSourceA, pSourceB);
- sumReal += (q63_t) prod1;
- sumImag += (q63_t) prod2;
-
-#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
-
- }
-
- /* Saturate and store the result in the destination buffer */
-
- *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
- *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
- i = i + numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
deleted file mode 100644
index c1ecf4e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_cmplx_mult_q31.c
- * Description: Floating-point matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup CmplxMatrixMult
- * @{
- */
-
-/**
- * @brief Q31 Complex matrix multiplication
- * @param[in] *pSrcA points to the first input complex matrix structure
- * @param[in] *pSrcB points to the second input complex matrix structure
- * @param[out] *pDst points to output complex matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate
- * multiplication results but provides only a single guard bit. There is no saturation
- * on intermediate additions. Thus, if the accumulator overflows it wraps around and
- * distorts the result. The input signals should be scaled down to avoid intermediate
- * overflows. The input is thus scaled down by log2(numColsA) bits
- * to avoid overflows, as a total of numColsA additions are performed internally.
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
- *
- *
- */
-
-arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- q31_t *px; /* Temporary output data matrix pointer */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- q63_t sumReal1, sumImag1; /* accumulator */
- q31_t a0, b0, c0, d0;
- q31_t a1, b1, c1, d1;
-
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
-
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + 2 * i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- j = 0u;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sumReal1 = 0.0;
- sumImag1 = 0.0;
-
- /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
- pIn1 = pInA;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
-
- /* Reading real part of complex matrix A */
- a0 = *pIn1;
-
- /* Reading real part of complex matrix B */
- c0 = *pIn2;
-
- /* Reading imaginary part of complex matrix A */
- b0 = *(pIn1 + 1u);
-
- /* Reading imaginary part of complex matrix B */
- d0 = *(pIn2 + 1u);
-
- /* Multiply and Accumlates */
- sumReal1 += (q63_t) a0 *c0;
- sumImag1 += (q63_t) b0 *c0;
-
- /* update pointers */
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- /* Multiply and Accumlates */
- sumReal1 -= (q63_t) b0 *d0;
- sumImag1 += (q63_t) a0 *d0;
-
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
- /* read real and imag values from pSrcA and pSrcB buffer */
- a1 = *pIn1;
- c1 = *pIn2;
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- /* Multiply and Accumlates */
- sumReal1 += (q63_t) a1 *c1;
- sumImag1 += (q63_t) b1 *c1;
-
- /* update pointers */
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- /* Multiply and Accumlates */
- sumReal1 -= (q63_t) b1 *d1;
- sumImag1 += (q63_t) a1 *d1;
-
- a0 = *pIn1;
- c0 = *pIn2;
-
- b0 = *(pIn1 + 1u);
- d0 = *(pIn2 + 1u);
-
- /* Multiply and Accumlates */
- sumReal1 += (q63_t) a0 *c0;
- sumImag1 += (q63_t) b0 *c0;
-
- /* update pointers */
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- /* Multiply and Accumlates */
- sumReal1 -= (q63_t) b0 *d0;
- sumImag1 += (q63_t) a0 *d0;
-
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
- a1 = *pIn1;
- c1 = *pIn2;
-
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- /* Multiply and Accumlates */
- sumReal1 += (q63_t) a1 *c1;
- sumImag1 += (q63_t) b1 *c1;
-
- /* update pointers */
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- /* Multiply and Accumlates */
- sumReal1 -= (q63_t) b1 *d1;
- sumImag1 += (q63_t) a1 *d1;
-
- /* Decrement the loop count */
- colCnt--;
- }
-
- /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- colCnt = numColsA % 0x4u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- a1 = *pIn1;
- c1 = *pIn2;
-
- b1 = *(pIn1 + 1u);
- d1 = *(pIn2 + 1u);
-
- /* Multiply and Accumlates */
- sumReal1 += (q63_t) a1 *c1;
- sumImag1 += (q63_t) b1 *c1;
-
- /* update pointers */
- pIn1 += 2u;
- pIn2 += 2 * numColsB;
-
- /* Multiply and Accumlates */
- sumReal1 -= (q63_t) b1 *d1;
- sumImag1 += (q63_t) a1 *d1;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Store the result in the destination buffer */
- *px++ = (q31_t) clip_q63_to_q31(sumReal1 >> 31);
- *px++ = (q31_t) clip_q63_to_q31(sumImag1 >> 31);
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- j++;
- pIn2 = pSrcB->pData + 2u * j;
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
- /* Update the pointer pInA to point to the starting address of the next row */
- i = i + numColsB;
- pInA = pInA + 2 * numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c
deleted file mode 100644
index 783f7be..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_init_f32.c
- * Description: Floating-point matrix initialization
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixInit Matrix Initialization
- *
- * Initializes the underlying matrix data structure.
- * The functions set the numRows,
- * numCols, and pData fields
- * of the matrix data structure.
- */
-
-/**
- * @addtogroup MatrixInit
- * @{
- */
-
-/**
- * @brief Floating-point matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
-void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData)
-{
- /* Assign Number of Rows */
- S->numRows = nRows;
-
- /* Assign Number of Columns */
- S->numCols = nColumns;
-
- /* Assign Data pointer */
- S->pData = pData;
-}
-
-/**
- * @} end of MatrixInit group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c
deleted file mode 100644
index 08da19f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_init_q15.c
- * Description: Q15 matrix initialization
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixInit
- * @{
- */
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
-void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData)
-{
- /* Assign Number of Rows */
- S->numRows = nRows;
-
- /* Assign Number of Columns */
- S->numCols = nColumns;
-
- /* Assign Data pointer */
- S->pData = pData;
-}
-
-/**
- * @} end of MatrixInit group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c
deleted file mode 100644
index 22e6f6d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_init_q31.c
- * Description: Q31 matrix initialization
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixInit Matrix Initialization
- *
- */
-
-/**
- * @addtogroup MatrixInit
- * @{
- */
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
-void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData)
-{
- /* Assign Number of Rows */
- S->numRows = nRows;
-
- /* Assign Number of Columns */
- S->numCols = nColumns;
-
- /* Assign Data pointer */
- S->pData = pData;
-}
-
-/**
- * @} end of MatrixInit group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c
deleted file mode 100644
index 1d760c9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_inverse_f32.c
- * Description: Floating-point matrix inverse
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixInv Matrix Inverse
- *
- * Computes the inverse of a matrix.
- *
- * The inverse is defined only if the input matrix is square and non-singular (the determinant
- * is non-zero). The function checks that the input and output matrices are square and of the
- * same size.
- *
- * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
- * inversion of floating-point matrices.
- *
- * \par Algorithm
- * The Gauss-Jordan method is used to find the inverse.
- * The algorithm performs a sequence of elementary row-operations until it
- * reduces the input matrix to an identity matrix. Applying the same sequence
- * of elementary row-operations to an identity matrix yields the inverse matrix.
- * If the input matrix is singular, then the algorithm terminates and returns error status
- * ARM_MATH_SINGULAR.
- * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
- */
-
-/**
- * @addtogroup MatrixInv
- * @{
- */
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in] *pSrc points to input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns
- * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
- * of the output matrix does not match the size of the input matrix.
- * If the input matrix is found to be singular (non-invertible), then the function returns
- * ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS.
- */
-
-arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn = pSrc->pData; /* input data matrix pointer */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
- float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
- float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */
- float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
- uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
- uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
-
-#if defined (ARM_MATH_DSP)
- float32_t maxC; /* maximum value in the column */
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t Xchg, in = 0.0f, in1; /* Temporary input values */
- uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
- arm_status status; /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
- || (pSrc->numRows != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
-
- /*--------------------------------------------------------------------------------------------------------------
- * Matrix Inverse can be solved using elementary row operations.
- *
- * Gauss-Jordan Method:
- *
- * 1. First combine the identity matrix and the input matrix separated by a bar to form an
- * augmented matrix as follows:
- * _ _ _ _
- * | a11 a12 | 1 0 | | X11 X12 |
- * | | | = | |
- * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
- *
- * 2. In our implementation, pDst Matrix is used as identity matrix.
- *
- * 3. Begin with the first row. Let i = 1.
- *
- * 4. Check to see if the pivot for column i is the greatest of the column.
- * The pivot is the element of the main diagonal that is on the current row.
- * For instance, if working with row i, then the pivot element is aii.
- * If the pivot is not the most significant of the columns, exchange that row with a row
- * below it that does contain the most significant value in column i. If the most
- * significant value of the column is zero, then an inverse to that matrix does not exist.
- * The most significant value of the column is the absolute maximum.
- *
- * 5. Divide every element of row i by the pivot.
- *
- * 6. For every row below and row i, replace that row with the sum of that row and
- * a multiple of row i so that each new element in column i below row i is zero.
- *
- * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
- * for every element below and above the main diagonal.
- *
- * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
- * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
- *----------------------------------------------------------------------------------------------------------------*/
-
- /* Working pointer for destination matrix */
- pOutT1 = pOut;
-
- /* Loop over the number of rows */
- rowCnt = numRows;
-
- /* Making the destination matrix as identity matrix */
- while (rowCnt > 0u)
- {
- /* Writing all zeroes in lower triangle of the destination matrix */
- j = numRows - rowCnt;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Writing all ones in the diagonal of the destination matrix */
- *pOutT1++ = 1.0f;
-
- /* Writing all zeroes in upper triangle of the destination matrix */
- j = rowCnt - 1u;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Decrement the loop counter */
- rowCnt--;
- }
-
- /* Loop over the number of columns of the input matrix.
- All the elements in each column are processed by the row operations */
- loopCnt = numCols;
-
- /* Index modifier to navigate through the columns */
- l = 0u;
-
- while (loopCnt > 0u)
- {
- /* Check if the pivot element is zero..
- * If it is zero then interchange the row with non zero row below.
- * If there is no non zero element to replace in the rows below,
- * then the matrix is Singular. */
-
- /* Working pointer for the input matrix that points
- * to the pivot element of the particular row */
- pInT1 = pIn + (l * numCols);
-
- /* Working pointer for the destination matrix that points
- * to the pivot element of the particular row */
- pOutT1 = pOut + (l * numCols);
-
- /* Temporary variable to hold the pivot value */
- in = *pInT1;
-
- /* Grab the most significant value from column l */
- maxC = 0;
- for (i = l; i < numRows; i++)
- {
- maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
- pInT1 += numCols;
- }
-
- /* Update the status if the matrix is singular */
- if (maxC == 0.0f)
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Restore pInT1 */
- pInT1 = pIn;
-
- /* Destination pointer modifier */
- k = 1u;
-
- /* Check if the pivot element is the most significant of the column */
- if ( (in > 0.0f ? in : -in) != maxC)
- {
- /* Loop over the number rows present below */
- i = numRows - (l + 1u);
-
- while (i > 0u)
- {
- /* Update the input and destination pointers */
- pInT2 = pInT1 + (numCols * l);
- pOutT2 = pOutT1 + (numCols * k);
-
- /* Look for the most significant element to
- * replace in the rows below */
- if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
- {
- /* Loop over number of columns
- * to the right of the pilot element */
- j = numCols - l;
-
- while (j > 0u)
- {
- /* Exchange the row elements of the input matrix */
- Xchg = *pInT2;
- *pInT2++ = *pInT1;
- *pInT1++ = Xchg;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over number of columns of the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Exchange the row elements of the destination matrix */
- Xchg = *pOutT2;
- *pOutT2++ = *pOutT1;
- *pOutT1++ = Xchg;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Flag to indicate whether exchange is done or not */
- flag = 1u;
-
- /* Break after exchange is done */
- break;
- }
-
- /* Update the destination pointer modifier */
- k++;
-
- /* Decrement the loop counter */
- i--;
- }
- }
-
- /* Update the status if the matrix is singular */
- if ((flag != 1u) && (in == 0.0f))
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Points to the pivot row of input and destination matrices */
- pPivotRowIn = pIn + (l * numCols);
- pPivotRowDst = pOut + (l * numCols);
-
- /* Temporary pointers to the pivot row pointers */
- pInT1 = pPivotRowIn;
- pInT2 = pPivotRowDst;
-
- /* Pivot element of the row */
- in = *pPivotRowIn;
-
- /* Loop over number of columns
- * to the right of the pilot element */
- j = (numCols - l);
-
- while (j > 0u)
- {
- /* Divide each element of the row of the input matrix
- * by the pivot element */
- in1 = *pInT1;
- *pInT1++ = in1 / in;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over number of columns of the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Divide each element of the row of the destination matrix
- * by the pivot element */
- in1 = *pInT2;
- *pInT2++ = in1 / in;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Replace the rows with the sum of that row and a multiple of row i
- * so that each new element in column i above row i is zero.*/
-
- /* Temporary pointers for input and destination matrices */
- pInT1 = pIn;
- pInT2 = pOut;
-
- /* index used to check for pivot element */
- i = 0u;
-
- /* Loop over number of rows */
- /* to be replaced by the sum of that row and a multiple of row i */
- k = numRows;
-
- while (k > 0u)
- {
- /* Check for the pivot element */
- if (i == l)
- {
- /* If the processing element is the pivot element,
- only the columns to the right are to be processed */
- pInT1 += numCols - l;
-
- pInT2 += numCols;
- }
- else
- {
- /* Element of the reference row */
- in = *pInT1;
-
- /* Working pointers for input and destination pivot rows */
- pPRT_in = pPivotRowIn;
- pPRT_pDst = pPivotRowDst;
-
- /* Loop over the number of columns to the right of the pivot element,
- to replace the elements in the input matrix */
- j = (numCols - l);
-
- while (j > 0u)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- in1 = *pInT1;
- *pInT1++ = in1 - (in * *pPRT_in++);
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over the number of columns to
- replace the elements in the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- in1 = *pInT2;
- *pInT2++ = in1 - (in * *pPRT_pDst++);
-
- /* Decrement the loop counter */
- j--;
- }
-
- }
-
- /* Increment the temporary input pointer */
- pInT1 = pInT1 + l;
-
- /* Decrement the loop counter */
- k--;
-
- /* Increment the pivot index */
- i++;
- }
-
- /* Increment the input pointer */
- pIn++;
-
- /* Decrement the loop counter */
- loopCnt--;
-
- /* Increment the index modifier */
- l++;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t Xchg, in = 0.0f; /* Temporary input values */
- uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
- arm_status status; /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
- || (pSrc->numRows != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
- {
-
- /*--------------------------------------------------------------------------------------------------------------
- * Matrix Inverse can be solved using elementary row operations.
- *
- * Gauss-Jordan Method:
- *
- * 1. First combine the identity matrix and the input matrix separated by a bar to form an
- * augmented matrix as follows:
- * _ _ _ _ _ _ _ _
- * | | a11 a12 | | | 1 0 | | | X11 X12 |
- * | | | | | | | = | |
- * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
- *
- * 2. In our implementation, pDst Matrix is used as identity matrix.
- *
- * 3. Begin with the first row. Let i = 1.
- *
- * 4. Check to see if the pivot for row i is zero.
- * The pivot is the element of the main diagonal that is on the current row.
- * For instance, if working with row i, then the pivot element is aii.
- * If the pivot is zero, exchange that row with a row below it that does not
- * contain a zero in column i. If this is not possible, then an inverse
- * to that matrix does not exist.
- *
- * 5. Divide every element of row i by the pivot.
- *
- * 6. For every row below and row i, replace that row with the sum of that row and
- * a multiple of row i so that each new element in column i below row i is zero.
- *
- * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
- * for every element below and above the main diagonal.
- *
- * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
- * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
- *----------------------------------------------------------------------------------------------------------------*/
-
- /* Working pointer for destination matrix */
- pOutT1 = pOut;
-
- /* Loop over the number of rows */
- rowCnt = numRows;
-
- /* Making the destination matrix as identity matrix */
- while (rowCnt > 0u)
- {
- /* Writing all zeroes in lower triangle of the destination matrix */
- j = numRows - rowCnt;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Writing all ones in the diagonal of the destination matrix */
- *pOutT1++ = 1.0f;
-
- /* Writing all zeroes in upper triangle of the destination matrix */
- j = rowCnt - 1u;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Decrement the loop counter */
- rowCnt--;
- }
-
- /* Loop over the number of columns of the input matrix.
- All the elements in each column are processed by the row operations */
- loopCnt = numCols;
-
- /* Index modifier to navigate through the columns */
- l = 0u;
- //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
- while (loopCnt > 0u)
- {
- /* Check if the pivot element is zero..
- * If it is zero then interchange the row with non zero row below.
- * If there is no non zero element to replace in the rows below,
- * then the matrix is Singular. */
-
- /* Working pointer for the input matrix that points
- * to the pivot element of the particular row */
- pInT1 = pIn + (l * numCols);
-
- /* Working pointer for the destination matrix that points
- * to the pivot element of the particular row */
- pOutT1 = pOut + (l * numCols);
-
- /* Temporary variable to hold the pivot value */
- in = *pInT1;
-
- /* Destination pointer modifier */
- k = 1u;
-
- /* Check if the pivot element is zero */
- if (*pInT1 == 0.0f)
- {
- /* Loop over the number rows present below */
- for (i = (l + 1u); i < numRows; i++)
- {
- /* Update the input and destination pointers */
- pInT2 = pInT1 + (numCols * l);
- pOutT2 = pOutT1 + (numCols * k);
-
- /* Check if there is a non zero pivot element to
- * replace in the rows below */
- if (*pInT2 != 0.0f)
- {
- /* Loop over number of columns
- * to the right of the pilot element */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Exchange the row elements of the input matrix */
- Xchg = *pInT2;
- *pInT2++ = *pInT1;
- *pInT1++ = Xchg;
- }
-
- for (j = 0u; j < numCols; j++)
- {
- Xchg = *pOutT2;
- *pOutT2++ = *pOutT1;
- *pOutT1++ = Xchg;
- }
-
- /* Flag to indicate whether exchange is done or not */
- flag = 1u;
-
- /* Break after exchange is done */
- break;
- }
-
- /* Update the destination pointer modifier */
- k++;
- }
- }
-
- /* Update the status if the matrix is singular */
- if ((flag != 1u) && (in == 0.0f))
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Points to the pivot row of input and destination matrices */
- pPivotRowIn = pIn + (l * numCols);
- pPivotRowDst = pOut + (l * numCols);
-
- /* Temporary pointers to the pivot row pointers */
- pInT1 = pPivotRowIn;
- pOutT1 = pPivotRowDst;
-
- /* Pivot element of the row */
- in = *(pIn + (l * numCols));
-
- /* Loop over number of columns
- * to the right of the pilot element */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Divide each element of the row of the input matrix
- * by the pivot element */
- *pInT1 = *pInT1 / in;
- pInT1++;
- }
- for (j = 0u; j < numCols; j++)
- {
- /* Divide each element of the row of the destination matrix
- * by the pivot element */
- *pOutT1 = *pOutT1 / in;
- pOutT1++;
- }
-
- /* Replace the rows with the sum of that row and a multiple of row i
- * so that each new element in column i above row i is zero.*/
-
- /* Temporary pointers for input and destination matrices */
- pInT1 = pIn;
- pOutT1 = pOut;
-
- for (i = 0u; i < numRows; i++)
- {
- /* Check for the pivot element */
- if (i == l)
- {
- /* If the processing element is the pivot element,
- only the columns to the right are to be processed */
- pInT1 += numCols - l;
- pOutT1 += numCols;
- }
- else
- {
- /* Element of the reference row */
- in = *pInT1;
-
- /* Working pointers for input and destination pivot rows */
- pPRT_in = pPivotRowIn;
- pPRT_pDst = pPivotRowDst;
-
- /* Loop over the number of columns to the right of the pivot element,
- to replace the elements in the input matrix */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- *pInT1 = *pInT1 - (in * *pPRT_in++);
- pInT1++;
- }
- /* Loop over the number of columns to
- replace the elements in the destination matrix */
- for (j = 0u; j < numCols; j++)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
- pOutT1++;
- }
-
- }
- /* Increment the temporary input pointer */
- pInT1 = pInT1 + l;
- }
- /* Increment the input pointer */
- pIn++;
-
- /* Decrement the loop counter */
- loopCnt--;
- /* Increment the index modifier */
- l++;
- }
-
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- if ((flag != 1u) && (in == 0.0f))
- {
- pIn = pSrc->pData;
- for (i = 0; i < numRows * numCols; i++)
- {
- if (pIn[i] != 0.0f)
- break;
- }
-
- if (i == numRows * numCols)
- status = ARM_MATH_SINGULAR;
- }
- }
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixInv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
deleted file mode 100644
index f1b6788..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_inverse_f64.c
- * Description: Floating-point matrix inverse
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixInv Matrix Inverse
- *
- * Computes the inverse of a matrix.
- *
- * The inverse is defined only if the input matrix is square and non-singular (the determinant
- * is non-zero). The function checks that the input and output matrices are square and of the
- * same size.
- *
- * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
- * inversion of floating-point matrices.
- *
- * \par Algorithm
- * The Gauss-Jordan method is used to find the inverse.
- * The algorithm performs a sequence of elementary row-operations until it
- * reduces the input matrix to an identity matrix. Applying the same sequence
- * of elementary row-operations to an identity matrix yields the inverse matrix.
- * If the input matrix is singular, then the algorithm terminates and returns error status
- * ARM_MATH_SINGULAR.
- * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
- */
-
-/**
- * @addtogroup MatrixInv
- * @{
- */
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in] *pSrc points to input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns
- * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
- * of the output matrix does not match the size of the input matrix.
- * If the input matrix is found to be singular (non-invertible), then the function returns
- * ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS.
- */
-
-arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * pSrc,
- arm_matrix_instance_f64 * pDst)
-{
- float64_t *pIn = pSrc->pData; /* input data matrix pointer */
- float64_t *pOut = pDst->pData; /* output data matrix pointer */
- float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
- float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */
- float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
- uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
- uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
-
-#if defined (ARM_MATH_DSP)
- float64_t maxC; /* maximum value in the column */
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float64_t Xchg, in = 0.0f, in1; /* Temporary input values */
- uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
- arm_status status; /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
- || (pSrc->numRows != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
-
- /*--------------------------------------------------------------------------------------------------------------
- * Matrix Inverse can be solved using elementary row operations.
- *
- * Gauss-Jordan Method:
- *
- * 1. First combine the identity matrix and the input matrix separated by a bar to form an
- * augmented matrix as follows:
- * _ _ _ _
- * | a11 a12 | 1 0 | | X11 X12 |
- * | | | = | |
- * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
- *
- * 2. In our implementation, pDst Matrix is used as identity matrix.
- *
- * 3. Begin with the first row. Let i = 1.
- *
- * 4. Check to see if the pivot for column i is the greatest of the column.
- * The pivot is the element of the main diagonal that is on the current row.
- * For instance, if working with row i, then the pivot element is aii.
- * If the pivot is not the most significant of the columns, exchange that row with a row
- * below it that does contain the most significant value in column i. If the most
- * significant value of the column is zero, then an inverse to that matrix does not exist.
- * The most significant value of the column is the absolute maximum.
- *
- * 5. Divide every element of row i by the pivot.
- *
- * 6. For every row below and row i, replace that row with the sum of that row and
- * a multiple of row i so that each new element in column i below row i is zero.
- *
- * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
- * for every element below and above the main diagonal.
- *
- * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
- * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
- *----------------------------------------------------------------------------------------------------------------*/
-
- /* Working pointer for destination matrix */
- pOutT1 = pOut;
-
- /* Loop over the number of rows */
- rowCnt = numRows;
-
- /* Making the destination matrix as identity matrix */
- while (rowCnt > 0u)
- {
- /* Writing all zeroes in lower triangle of the destination matrix */
- j = numRows - rowCnt;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Writing all ones in the diagonal of the destination matrix */
- *pOutT1++ = 1.0f;
-
- /* Writing all zeroes in upper triangle of the destination matrix */
- j = rowCnt - 1u;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Decrement the loop counter */
- rowCnt--;
- }
-
- /* Loop over the number of columns of the input matrix.
- All the elements in each column are processed by the row operations */
- loopCnt = numCols;
-
- /* Index modifier to navigate through the columns */
- l = 0u;
-
- while (loopCnt > 0u)
- {
- /* Check if the pivot element is zero..
- * If it is zero then interchange the row with non zero row below.
- * If there is no non zero element to replace in the rows below,
- * then the matrix is Singular. */
-
- /* Working pointer for the input matrix that points
- * to the pivot element of the particular row */
- pInT1 = pIn + (l * numCols);
-
- /* Working pointer for the destination matrix that points
- * to the pivot element of the particular row */
- pOutT1 = pOut + (l * numCols);
-
- /* Temporary variable to hold the pivot value */
- in = *pInT1;
-
- /* Grab the most significant value from column l */
- maxC = 0;
- for (i = l; i < numRows; i++)
- {
- maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
- pInT1 += numCols;
- }
-
- /* Update the status if the matrix is singular */
- if (maxC == 0.0f)
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Restore pInT1 */
- pInT1 = pIn;
-
- /* Destination pointer modifier */
- k = 1u;
-
- /* Check if the pivot element is the most significant of the column */
- if ( (in > 0.0f ? in : -in) != maxC)
- {
- /* Loop over the number rows present below */
- i = numRows - (l + 1u);
-
- while (i > 0u)
- {
- /* Update the input and destination pointers */
- pInT2 = pInT1 + (numCols * l);
- pOutT2 = pOutT1 + (numCols * k);
-
- /* Look for the most significant element to
- * replace in the rows below */
- if ((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
- {
- /* Loop over number of columns
- * to the right of the pilot element */
- j = numCols - l;
-
- while (j > 0u)
- {
- /* Exchange the row elements of the input matrix */
- Xchg = *pInT2;
- *pInT2++ = *pInT1;
- *pInT1++ = Xchg;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over number of columns of the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Exchange the row elements of the destination matrix */
- Xchg = *pOutT2;
- *pOutT2++ = *pOutT1;
- *pOutT1++ = Xchg;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Flag to indicate whether exchange is done or not */
- flag = 1u;
-
- /* Break after exchange is done */
- break;
- }
-
- /* Update the destination pointer modifier */
- k++;
-
- /* Decrement the loop counter */
- i--;
- }
- }
-
- /* Update the status if the matrix is singular */
- if ((flag != 1u) && (in == 0.0f))
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Points to the pivot row of input and destination matrices */
- pPivotRowIn = pIn + (l * numCols);
- pPivotRowDst = pOut + (l * numCols);
-
- /* Temporary pointers to the pivot row pointers */
- pInT1 = pPivotRowIn;
- pInT2 = pPivotRowDst;
-
- /* Pivot element of the row */
- in = *pPivotRowIn;
-
- /* Loop over number of columns
- * to the right of the pilot element */
- j = (numCols - l);
-
- while (j > 0u)
- {
- /* Divide each element of the row of the input matrix
- * by the pivot element */
- in1 = *pInT1;
- *pInT1++ = in1 / in;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over number of columns of the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Divide each element of the row of the destination matrix
- * by the pivot element */
- in1 = *pInT2;
- *pInT2++ = in1 / in;
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Replace the rows with the sum of that row and a multiple of row i
- * so that each new element in column i above row i is zero.*/
-
- /* Temporary pointers for input and destination matrices */
- pInT1 = pIn;
- pInT2 = pOut;
-
- /* index used to check for pivot element */
- i = 0u;
-
- /* Loop over number of rows */
- /* to be replaced by the sum of that row and a multiple of row i */
- k = numRows;
-
- while (k > 0u)
- {
- /* Check for the pivot element */
- if (i == l)
- {
- /* If the processing element is the pivot element,
- only the columns to the right are to be processed */
- pInT1 += numCols - l;
-
- pInT2 += numCols;
- }
- else
- {
- /* Element of the reference row */
- in = *pInT1;
-
- /* Working pointers for input and destination pivot rows */
- pPRT_in = pPivotRowIn;
- pPRT_pDst = pPivotRowDst;
-
- /* Loop over the number of columns to the right of the pivot element,
- to replace the elements in the input matrix */
- j = (numCols - l);
-
- while (j > 0u)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- in1 = *pInT1;
- *pInT1++ = in1 - (in * *pPRT_in++);
-
- /* Decrement the loop counter */
- j--;
- }
-
- /* Loop over the number of columns to
- replace the elements in the destination matrix */
- j = numCols;
-
- while (j > 0u)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- in1 = *pInT2;
- *pInT2++ = in1 - (in * *pPRT_pDst++);
-
- /* Decrement the loop counter */
- j--;
- }
-
- }
-
- /* Increment the temporary input pointer */
- pInT1 = pInT1 + l;
-
- /* Decrement the loop counter */
- k--;
-
- /* Increment the pivot index */
- i++;
- }
-
- /* Increment the input pointer */
- pIn++;
-
- /* Decrement the loop counter */
- loopCnt--;
-
- /* Increment the index modifier */
- l++;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float64_t Xchg, in = 0.0f; /* Temporary input values */
- uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
- arm_status status; /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
- || (pSrc->numRows != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
- {
-
- /*--------------------------------------------------------------------------------------------------------------
- * Matrix Inverse can be solved using elementary row operations.
- *
- * Gauss-Jordan Method:
- *
- * 1. First combine the identity matrix and the input matrix separated by a bar to form an
- * augmented matrix as follows:
- * _ _ _ _ _ _ _ _
- * | | a11 a12 | | | 1 0 | | | X11 X12 |
- * | | | | | | | = | |
- * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
- *
- * 2. In our implementation, pDst Matrix is used as identity matrix.
- *
- * 3. Begin with the first row. Let i = 1.
- *
- * 4. Check to see if the pivot for row i is zero.
- * The pivot is the element of the main diagonal that is on the current row.
- * For instance, if working with row i, then the pivot element is aii.
- * If the pivot is zero, exchange that row with a row below it that does not
- * contain a zero in column i. If this is not possible, then an inverse
- * to that matrix does not exist.
- *
- * 5. Divide every element of row i by the pivot.
- *
- * 6. For every row below and row i, replace that row with the sum of that row and
- * a multiple of row i so that each new element in column i below row i is zero.
- *
- * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
- * for every element below and above the main diagonal.
- *
- * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
- * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
- *----------------------------------------------------------------------------------------------------------------*/
-
- /* Working pointer for destination matrix */
- pOutT1 = pOut;
-
- /* Loop over the number of rows */
- rowCnt = numRows;
-
- /* Making the destination matrix as identity matrix */
- while (rowCnt > 0u)
- {
- /* Writing all zeroes in lower triangle of the destination matrix */
- j = numRows - rowCnt;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Writing all ones in the diagonal of the destination matrix */
- *pOutT1++ = 1.0f;
-
- /* Writing all zeroes in upper triangle of the destination matrix */
- j = rowCnt - 1u;
- while (j > 0u)
- {
- *pOutT1++ = 0.0f;
- j--;
- }
-
- /* Decrement the loop counter */
- rowCnt--;
- }
-
- /* Loop over the number of columns of the input matrix.
- All the elements in each column are processed by the row operations */
- loopCnt = numCols;
-
- /* Index modifier to navigate through the columns */
- l = 0u;
- //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
- while (loopCnt > 0u)
- {
- /* Check if the pivot element is zero..
- * If it is zero then interchange the row with non zero row below.
- * If there is no non zero element to replace in the rows below,
- * then the matrix is Singular. */
-
- /* Working pointer for the input matrix that points
- * to the pivot element of the particular row */
- pInT1 = pIn + (l * numCols);
-
- /* Working pointer for the destination matrix that points
- * to the pivot element of the particular row */
- pOutT1 = pOut + (l * numCols);
-
- /* Temporary variable to hold the pivot value */
- in = *pInT1;
-
- /* Destination pointer modifier */
- k = 1u;
-
- /* Check if the pivot element is zero */
- if (*pInT1 == 0.0f)
- {
- /* Loop over the number rows present below */
- for (i = (l + 1u); i < numRows; i++)
- {
- /* Update the input and destination pointers */
- pInT2 = pInT1 + (numCols * l);
- pOutT2 = pOutT1 + (numCols * k);
-
- /* Check if there is a non zero pivot element to
- * replace in the rows below */
- if (*pInT2 != 0.0f)
- {
- /* Loop over number of columns
- * to the right of the pilot element */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Exchange the row elements of the input matrix */
- Xchg = *pInT2;
- *pInT2++ = *pInT1;
- *pInT1++ = Xchg;
- }
-
- for (j = 0u; j < numCols; j++)
- {
- Xchg = *pOutT2;
- *pOutT2++ = *pOutT1;
- *pOutT1++ = Xchg;
- }
-
- /* Flag to indicate whether exchange is done or not */
- flag = 1u;
-
- /* Break after exchange is done */
- break;
- }
-
- /* Update the destination pointer modifier */
- k++;
- }
- }
-
- /* Update the status if the matrix is singular */
- if ((flag != 1u) && (in == 0.0f))
- {
- return ARM_MATH_SINGULAR;
- }
-
- /* Points to the pivot row of input and destination matrices */
- pPivotRowIn = pIn + (l * numCols);
- pPivotRowDst = pOut + (l * numCols);
-
- /* Temporary pointers to the pivot row pointers */
- pInT1 = pPivotRowIn;
- pOutT1 = pPivotRowDst;
-
- /* Pivot element of the row */
- in = *(pIn + (l * numCols));
-
- /* Loop over number of columns
- * to the right of the pilot element */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Divide each element of the row of the input matrix
- * by the pivot element */
- *pInT1 = *pInT1 / in;
- pInT1++;
- }
- for (j = 0u; j < numCols; j++)
- {
- /* Divide each element of the row of the destination matrix
- * by the pivot element */
- *pOutT1 = *pOutT1 / in;
- pOutT1++;
- }
-
- /* Replace the rows with the sum of that row and a multiple of row i
- * so that each new element in column i above row i is zero.*/
-
- /* Temporary pointers for input and destination matrices */
- pInT1 = pIn;
- pOutT1 = pOut;
-
- for (i = 0u; i < numRows; i++)
- {
- /* Check for the pivot element */
- if (i == l)
- {
- /* If the processing element is the pivot element,
- only the columns to the right are to be processed */
- pInT1 += numCols - l;
- pOutT1 += numCols;
- }
- else
- {
- /* Element of the reference row */
- in = *pInT1;
-
- /* Working pointers for input and destination pivot rows */
- pPRT_in = pPivotRowIn;
- pPRT_pDst = pPivotRowDst;
-
- /* Loop over the number of columns to the right of the pivot element,
- to replace the elements in the input matrix */
- for (j = 0u; j < (numCols - l); j++)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- *pInT1 = *pInT1 - (in * *pPRT_in++);
- pInT1++;
- }
- /* Loop over the number of columns to
- replace the elements in the destination matrix */
- for (j = 0u; j < numCols; j++)
- {
- /* Replace the element by the sum of that row
- and a multiple of the reference row */
- *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
- pOutT1++;
- }
-
- }
- /* Increment the temporary input pointer */
- pInT1 = pInT1 + l;
- }
- /* Increment the input pointer */
- pIn++;
-
- /* Decrement the loop counter */
- loopCnt--;
- /* Increment the index modifier */
- l++;
- }
-
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
-
- if ((flag != 1u) && (in == 0.0f))
- {
- pIn = pSrc->pData;
- for (i = 0; i < numRows * numCols; i++)
- {
- if (pIn[i] != 0.0f)
- break;
- }
-
- if (i == numRows * numCols)
- status = ARM_MATH_SINGULAR;
- }
- }
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixInv group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c
deleted file mode 100644
index abe2180..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_mult_f32.c
- * Description: Floating-point matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixMult Matrix Multiplication
- *
- * Multiplies two matrices.
- *
- * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"
-
- * Matrix multiplication is only defined if the number of columns of the
- * first matrix equals the number of rows of the second matrix.
- * Multiplying an M x N matrix with an N x P matrix results
- * in an M x P matrix.
- * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
- * pSrcA and pSrcB are equal; and (2) that the size of the output
- * matrix equals the outer dimensions of pSrcA and pSrcB.
- */
-
-
-/**
- * @addtogroup MatrixMult
- * @{
- */
-
-/**
- * @brief Floating-point matrix multiplication.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
- float32_t *px; /* Temporary output data matrix pointer */
- float32_t sum; /* Accumulator */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t in1, in2, in3, in4;
- uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
-
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- j = 0u;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0.0f;
-
- /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
- pIn1 = pInA;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- colCnt = numColsA >> 2u;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- in3 = *pIn2;
- pIn2 += numColsB;
- in1 = pIn1[0];
- in2 = pIn1[1];
- sum += in1 * in3;
- in4 = *pIn2;
- pIn2 += numColsB;
- sum += in2 * in4;
-
- in3 = *pIn2;
- pIn2 += numColsB;
- in1 = pIn1[2];
- in2 = pIn1[3];
- sum += in1 * in3;
- in4 = *pIn2;
- pIn2 += numColsB;
- sum += in2 * in4;
- pIn1 += 4u;
-
- /* Decrement the loop count */
- colCnt--;
- }
-
- /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
- ** No loop unrolling is used. */
- colCnt = numColsA % 0x4u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- sum += *pIn1++ * (*pIn2);
- pIn2 += numColsB;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Store the result in the destination buffer */
- *px++ = sum;
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- j++;
- pIn2 = pSrcB->pData + j;
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */
- uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
-
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pInA with each column in pInB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0.0f;
-
- /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
- pIn1 = pInA;
-
- /* Matrix A columns number of MAC operations are to be performed */
- colCnt = numColsA;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- sum += *pIn1++ * (*pIn2);
- pIn2 += numColsB;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Store the result in the destination buffer */
- *px++ = sum;
-
- /* Decrement the column loop counter */
- col--;
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- pIn2 = pInB + (numColsB - col);
-
- } while (col > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Update the pointer pInA to point to the starting address of the next row */
- i = i + numColsB;
- pInA = pInA + numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
deleted file mode 100644
index 728bd50..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_mult_fast_q15.c
- * Description: Q15 matrix multiplication (fast variant)
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixMult
- * @{
- */
-
-
-/**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The difference between the function arm_mat_mult_q15() and this fast variant is that
- * the fast variant use a 32-bit rather than a 64-bit accumulator.
- * The result of each 1.15 x 1.15 multiplication is truncated to
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
- * format. Finally, the accumulator is saturated and converted to a 1.15 result.
- *
- * \par
- * The fast version has the same overflow behavior as the standard version but provides
- * less precision since it discards the low 16 bits of each multiplication result.
- * In order to avoid overflows completely the input signals must be scaled down.
- * Scale down one of the input matrices by log2(numColsA) bits to
- * avoid overflows, as a total of numColsA additions are computed internally for each
- * output element.
- *
- * \par
- * See arm_mat_mult_q15() for a slower implementation of this function
- * which uses 64-bit accumulation to provide higher precision.
- */
-
-arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState)
-{
- q31_t sum; /* accumulator */
- q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
- q15_t *px; /* Temporary output data matrix pointer */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
- uint32_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- q31_t in; /* Temporary variable to hold the input value */
- q31_t inA1, inA2, inB1, inB2;
- q31_t sum2, sum3, sum4;
- q15_t *pInA2, *pInB2, *px2;
- uint32_t j = 0;
-
-#else
-
- q15_t in; /* Temporary variable to hold the input value */
- q15_t inA1, inA2, inB1, inB2;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif
- {
- /* Matrix transpose */
- do
- {
- /* Apply loop unrolling and exchange the columns with row elements */
- col = numColsB >> 2;
-
- /* The pointer px is set to starting address of the column being processed */
- px = pSrcBT + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (col > 0u)
- {
-#ifndef UNALIGNED_SUPPORT_DISABLE
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) in;
-
-#else
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *px = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) in;
-
-#else
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *px = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-#else
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- col = numColsB % 0x4u;
-
- while (col > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pInB++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- i++;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* Reset the variables for the usage in the following multiplication process */
- row = numRowsA;
- i = 0u;
- px = pDst->pData;
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
- /* Process two rows from matrix A at a time and output two rows at a time */
- row = row >> 1;
- px2 = px + numColsB;
-#endif
-
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- while (row > 0u)
- {
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the transposed pSrcB data */
- pInB = pSrcBT;
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
- /* Process two (transposed) columns from matrix B at a time */
- col = col >> 1;
- j = 0;
-#endif
-
- /* column loop */
- while (col > 0u)
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Initiate the pointer pInA to point to the starting address of the column being processed */
- pInA = pSrcA->pData + i;
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
- sum2 = 0;
- sum3 = 0;
- sum4 = 0;
- pInB = pSrcBT + j;
- pInA2 = pInA + numColsA;
- pInB2 = pInB + numRowsB;
-
- /* Read in two elements at once - alows dual MAC instruction */
- colCnt = numColsA >> 1;
-#else
- colCnt = numColsA >> 2;
-#endif
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- inA1 = *__SIMD32(pInA)++;
- inB1 = *__SIMD32(pInB)++;
- inA2 = *__SIMD32(pInA2)++;
- inB2 = *__SIMD32(pInB2)++;
-
- sum = __SMLAD(inA1, inB1, sum);
- sum2 = __SMLAD(inA1, inB2, sum2);
- sum3 = __SMLAD(inA2, inB1, sum3);
- sum4 = __SMLAD(inA2, inB2, sum4);
-
-#else
-
- inA1 = *pInA;
- inB1 = *pInB;
- sum += inA1 * inB1;
-
- inA2 = pInA[1];
- inB2 = pInB[1];
- sum += inA2 * inB2;
-
- inA1 = pInA[2];
- inB1 = pInB[2];
- sum += inA1 * inB1;
-
- inA2 = pInA[3];
- inB2 = pInB[3];
- sum += inA2 * inB2;
-
- pInA += 4;
- pInB += 4;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* process odd column samples */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- if (numColsA & 1u) {
- inA1 = *pInA++;
- inB1 = *pInB++;
- inA2 = *pInA2++;
- inB2 = *pInB2++;
- sum += inA1 * inB1;
- sum2 += inA1 * inB2;
- sum3 += inA2 * inB1;
- sum4 += inA2 * inB2;
- }
-#else
- colCnt = numColsA % 0x4u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- sum += (q31_t) (*pInA++) * (*pInB++);
-
- colCnt--;
- }
-#endif
-
- /* Saturate and store the result in the destination buffer */
- *px++ = (q15_t) (sum >> 15);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
- *px++ = (q15_t) (sum2 >> 15);
- *px2++ = (q15_t) (sum3 >> 15);
- *px2++ = (q15_t) (sum4 >> 15);
- j += numRowsB * 2;
-#endif
-
- /* Decrement the column loop counter */
- col--;
-
- }
-
- i = i + numColsA;
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
- i = i + numColsA;
- px = px2 + (numColsB & 1u);
- px2 = px + numColsB;
-#endif
-
- /* Decrement the row loop counter */
- row--;
-
- }
-
- /* Compute any remaining odd row/column below */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Compute remaining output column */
- if (numColsB & 1u) {
-
- /* Avoid redundant computation of last element */
- row = numRowsA & (~0x1);
-
- /* Point to remaining unfilled column in output matrix */
- px = pDst->pData+numColsB-1;
- pInA = pSrcA->pData;
-
- /* row loop */
- while (row > 0)
- {
-
- /* point to last column in matrix B */
- pInB = pSrcBT + numRowsB*(numColsB-1);
-
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Compute 4 columns at once */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- inA1 = *__SIMD32(pInA)++;
- inA2 = *__SIMD32(pInA)++;
- inB1 = *__SIMD32(pInB)++;
- inB2 = *__SIMD32(pInB)++;
-
- sum = __SMLAD(inA1, inB1, sum);
- sum = __SMLAD(inA2, inB2, sum);
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- colCnt = numColsA & 3u;
- while (colCnt > 0u) {
- sum += (q31_t) (*pInA++) * (*pInB++);
- colCnt--;
- }
-
- /* Store the result in the destination buffer */
- *px = (q15_t) (sum >> 15);
- px += numColsB;
-
- /* Decrement the row loop counter */
- row--;
- }
- }
-
- /* Compute remaining output row */
- if (numRowsA & 1u) {
-
- /* point to last row in output matrix */
- px = pDst->pData+(numColsB)*(numRowsA-1);
-
- pInB = pSrcBT;
- col = numColsB;
- i = 0u;
-
- /* col loop */
- while (col > 0)
- {
-
- /* point to last row in matrix A */
- pInA = pSrcA->pData + (numRowsA-1)*numColsA;
-
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Compute 4 columns at once */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- inA1 = *__SIMD32(pInA)++;
- inA2 = *__SIMD32(pInA)++;
- inB1 = *__SIMD32(pInB)++;
- inB2 = *__SIMD32(pInB)++;
-
- sum = __SMLAD(inA1, inB1, sum);
- sum = __SMLAD(inA2, inB2, sum);
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- colCnt = numColsA & 3u;
- while (colCnt > 0u) {
- sum += (q31_t) (*pInA++) * (*pInB++);
- colCnt--;
- }
-
- /* Store the result in the destination buffer */
- *px++ = (q15_t) (sum >> 15);
-
- /* Decrement the col loop counter */
- col--;
- }
- }
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
deleted file mode 100644
index 35e7adb..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_mult_fast_q31.c
- * Description: Q31 matrix multiplication (fast variant)
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixMult
- * @{
- */
-
-/**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The difference between the function arm_mat_mult_q31() and this fast variant is that
- * the fast variant use a 32-bit rather than a 64-bit accumulator.
- * The result of each 1.31 x 1.31 multiplication is truncated to
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
- * format. Finally, the accumulator is saturated and converted to a 1.31 result.
- *
- * \par
- * The fast version has the same overflow behavior as the standard version but provides
- * less precision since it discards the low 32 bits of each multiplication result.
- * In order to avoid overflows completely the input signals must be scaled down.
- * Scale down one of the input matrices by log2(numColsA) bits to
- * avoid overflows, as a total of numColsA additions are computed internally for each
- * output element.
- *
- * \par
- * See arm_mat_mult_q31() for a slower implementation of this function
- * which uses 64-bit accumulation to provide higher precision.
- */
-
-arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */
- q31_t *px; /* Temporary output data matrix pointer */
- q31_t sum; /* Accumulator */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- uint32_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
- q31_t inA1, inB1;
-
-#if defined (ARM_MATH_DSP)
-
- q31_t sum2, sum3, sum4;
- q31_t inA2, inB2;
- q31_t *pInA2;
- q31_t *px2;
-
-#endif
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
-
- px = pDst->pData;
-
-#if defined (ARM_MATH_DSP)
- row = row >> 1;
- px2 = px + numColsB;
-#endif
-
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- while (row > 0u)
- {
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pInB = pSrcB->pData;
-
- j = 0u;
-
-#if defined (ARM_MATH_DSP)
- col = col >> 1;
-#endif
-
- /* column loop */
- while (col > 0u)
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Initiate data pointers */
- pInA = pSrcA->pData + i;
- pInB = pSrcB->pData + j;
-
-#if defined (ARM_MATH_DSP)
- sum2 = 0;
- sum3 = 0;
- sum4 = 0;
- pInA2 = pInA + numColsA;
- colCnt = numColsA;
-#else
- colCnt = numColsA >> 2;
-#endif
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
-
-#if defined (ARM_MATH_DSP)
- inA1 = *pInA++;
- inB1 = pInB[0];
- inA2 = *pInA2++;
- inB2 = pInB[1];
- pInB += numColsB;
-
- sum = __SMMLA(inA1, inB1, sum);
- sum2 = __SMMLA(inA1, inB2, sum2);
- sum3 = __SMMLA(inA2, inB1, sum3);
- sum4 = __SMMLA(inA2, inB2, sum4);
-#else
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- /* Perform the multiply-accumulates */
- inB1 = *pInB;
- pInB += numColsB;
- inA1 = pInA[0];
- sum = __SMMLA(inA1, inB1, sum);
-
- inB1 = *pInB;
- pInB += numColsB;
- inA1 = pInA[1];
- sum = __SMMLA(inA1, inB1, sum);
-
- inB1 = *pInB;
- pInB += numColsB;
- inA1 = pInA[2];
- sum = __SMMLA(inA1, inB1, sum);
-
- inB1 = *pInB;
- pInB += numColsB;
- inA1 = pInA[3];
- sum = __SMMLA(inA1, inB1, sum);
-
- pInA += 4u;
-#endif
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
-#ifdef ARM_MATH_CM0_FAMILY
- /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here. */
- colCnt = numColsA % 0x4u;
- while (colCnt > 0u)
- {
- sum = __SMMLA(*pInA++, *pInB, sum);
- pInB += numColsB;
- colCnt--;
- }
- j++;
-#endif
-
- /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
- *px++ = sum << 1;
-
-#if defined (ARM_MATH_DSP)
- *px++ = sum2 << 1;
- *px2++ = sum3 << 1;
- *px2++ = sum4 << 1;
- j += 2;
-#endif
-
- /* Decrement the column loop counter */
- col--;
-
- }
-
- i = i + numColsA;
-
-#if defined (ARM_MATH_DSP)
- i = i + numColsA;
- px = px2 + (numColsB & 1u);
- px2 = px + numColsB;
-#endif
-
- /* Decrement the row loop counter */
- row--;
-
- }
-
- /* Compute any remaining odd row/column below */
-
-#if defined (ARM_MATH_DSP)
-
- /* Compute remaining output column */
- if (numColsB & 1u) {
-
- /* Avoid redundant computation of last element */
- row = numRowsA & (~0x1);
-
- /* Point to remaining unfilled column in output matrix */
- px = pDst->pData+numColsB-1;
- pInA = pSrcA->pData;
-
- /* row loop */
- while (row > 0)
- {
-
- /* point to last column in matrix B */
- pInB = pSrcB->pData + numColsB-1;
-
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Compute 4 columns at once */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- inA1 = *pInA++;
- inA2 = *pInA++;
- inB1 = *pInB;
- pInB += numColsB;
- inB2 = *pInB;
- pInB += numColsB;
- sum = __SMMLA(inA1, inB1, sum);
- sum = __SMMLA(inA2, inB2, sum);
-
- inA1 = *pInA++;
- inA2 = *pInA++;
- inB1 = *pInB;
- pInB += numColsB;
- inB2 = *pInB;
- pInB += numColsB;
- sum = __SMMLA(inA1, inB1, sum);
- sum = __SMMLA(inA2, inB2, sum);
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- colCnt = numColsA & 3u;
- while (colCnt > 0u) {
- sum = __SMMLA(*pInA++, *pInB, sum);
- pInB += numColsB;
- colCnt--;
- }
-
- /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
- *px = sum << 1;
- px += numColsB;
-
- /* Decrement the row loop counter */
- row--;
- }
- }
-
- /* Compute remaining output row */
- if (numRowsA & 1u) {
-
- /* point to last row in output matrix */
- px = pDst->pData+(numColsB)*(numRowsA-1);
-
- col = numColsB;
- i = 0u;
-
- /* col loop */
- while (col > 0)
- {
-
- /* point to last row in matrix A */
- pInA = pSrcA->pData + (numRowsA-1)*numColsA;
- pInB = pSrcB->pData + i;
-
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Compute 4 columns at once */
- colCnt = numColsA >> 2;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- inA1 = *pInA++;
- inA2 = *pInA++;
- inB1 = *pInB;
- pInB += numColsB;
- inB2 = *pInB;
- pInB += numColsB;
- sum = __SMMLA(inA1, inB1, sum);
- sum = __SMMLA(inA2, inB2, sum);
-
- inA1 = *pInA++;
- inA2 = *pInA++;
- inB1 = *pInB;
- pInB += numColsB;
- inB2 = *pInB;
- pInB += numColsB;
- sum = __SMMLA(inA1, inB1, sum);
- sum = __SMMLA(inA2, inB2, sum);
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- colCnt = numColsA & 3u;
- while (colCnt > 0u) {
- sum = __SMMLA(*pInA++, *pInB, sum);
- pInB += numColsB;
- colCnt--;
- }
-
- /* Saturate and store the result in the destination buffer */
- *px++ = sum << 1;
- i++;
-
- /* Decrement the col loop counter */
- col--;
- }
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c
deleted file mode 100644
index c22aea9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_mult_q15.c
- * Description: Q15 matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixMult
- * @{
- */
-
-
-/**
- * @brief Q15 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results (Unused)
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator. The inputs to the
- * multiplications are in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate
- * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
- * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
- * truncated to 34.15 format by discarding the low 15 bits and then saturated to
- * 1.15 format.
- *
- * \par
- * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
- *
- */
-
-arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState)
-{
- q63_t sum; /* accumulator */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
- q15_t *px; /* Temporary output data matrix pointer */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
- uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- q31_t in; /* Temporary variable to hold the input value */
- q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
-
-#else
-
- q15_t in; /* Temporary variable to hold the input value */
- q15_t inA1, inB1, inA2, inB2;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
- {
- /* Matrix transpose */
- do
- {
- /* Apply loop unrolling and exchange the columns with row elements */
- col = numColsB >> 2;
-
- /* The pointer px is set to starting address of the column being processed */
- px = pSrcBT + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (col > 0u)
- {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) in;
-
-#else
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *px = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read two elements from the row */
- in = *__SIMD32(pInB)++;
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) in;
-
-#else
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *px = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
-#else
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Read one element from the row */
- in = *pInB++;
-
- /* Store one element in the destination */
- *px = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the column loop counter */
- col--;
- }
-
- /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- col = numColsB % 0x4u;
-
- while (col > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pInB++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += numRowsB;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- i++;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* Reset the variables for the usage in the following multiplication process */
- row = numRowsA;
- i = 0u;
- px = pDst->pData;
-
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the transposed pSrcB data */
- pInB = pSrcBT;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Apply loop unrolling and compute 2 MACs simultaneously. */
- colCnt = numColsA >> 2;
-
- /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
- pInA = pSrcA->pData + i;
-
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* read real and imag values from pSrcA and pSrcB buffer */
- pSourceA1 = *__SIMD32(pInA)++;
- pSourceB1 = *__SIMD32(pInB)++;
-
- pSourceA2 = *__SIMD32(pInA)++;
- pSourceB2 = *__SIMD32(pInB)++;
-
- /* Multiply and Accumlates */
- sum = __SMLALD(pSourceA1, pSourceB1, sum);
- sum = __SMLALD(pSourceA2, pSourceB2, sum);
-
-#else
- /* read real and imag values from pSrcA and pSrcB buffer */
- inA1 = *pInA++;
- inB1 = *pInB++;
- inA2 = *pInA++;
- /* Multiply and Accumlates */
- sum += inA1 * inB1;
- inB2 = *pInB++;
-
- inA1 = *pInA++;
- inB1 = *pInB++;
- /* Multiply and Accumlates */
- sum += inA2 * inB2;
- inA2 = *pInA++;
- inB2 = *pInB++;
-
- /* Multiply and Accumlates */
- sum += inA1 * inB1;
- sum += inA2 * inB2;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* process remaining column samples */
- colCnt = numColsA & 3u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- sum += *pInA++ * *pInB++;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Saturate and store the result in the destination buffer */
- *px = (q15_t) (__SSAT((sum >> 15), 16));
- px++;
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
- i = i + numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- q15_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
- q15_t *pOut = pDst->pData; /* output data matrix pointer */
- q15_t *px; /* Temporary output data matrix pointer */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
- pIn1 = pInA;
-
- /* Matrix A columns number of MAC operations are to be performed */
- colCnt = numColsA;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- /* Perform the multiply-accumulates */
- sum += (q31_t) * pIn1++ * *pIn2;
- pIn2 += numColsB;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
- /* Saturate and store the result in the destination buffer */
- *px++ = (q15_t) __SSAT((sum >> 15), 16);
-
- /* Decrement the column loop counter */
- col--;
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- pIn2 = pInB + (numColsB - col);
-
- } while (col > 0u);
-
- /* Update the pointer pSrcA to point to the starting address of the next row */
- i = i + numColsB;
- pInA = pInA + numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c
deleted file mode 100644
index 8a90fdc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_mult_q31.c
- * Description: Q31 matrix multiplication
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixMult
- * @{
- */
-
-/**
- * @brief Q31 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate
- * multiplication results but provides only a single guard bit. There is no saturation
- * on intermediate additions. Thus, if the accumulator overflows it wraps around and
- * distorts the result. The input signals should be scaled down to avoid intermediate
- * overflows. The input is thus scaled down by log2(numColsA) bits
- * to avoid overflows, as a total of numColsA additions are performed internally.
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
- *
- * \par
- * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
- *
- */
-
-arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- q31_t *px; /* Temporary output data matrix pointer */
- q63_t sum; /* Accumulator */
- uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
- uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
- uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
- q31_t a0, a1, a2, a3, b0, b1, b2, b3;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- j = 0u;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Initiate the pointer pIn1 to point to the starting address of pInA */
- pIn1 = pInA;
-
- /* Apply loop unrolling and compute 4 MACs simultaneously. */
- colCnt = numColsA >> 2;
-
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- /* Perform the multiply-accumulates */
- b0 = *pIn2;
- pIn2 += numColsB;
-
- a0 = *pIn1++;
- a1 = *pIn1++;
-
- b1 = *pIn2;
- pIn2 += numColsB;
- b2 = *pIn2;
- pIn2 += numColsB;
-
- sum += (q63_t) a0 *b0;
- sum += (q63_t) a1 *b1;
-
- a2 = *pIn1++;
- a3 = *pIn1++;
-
- b3 = *pIn2;
- pIn2 += numColsB;
-
- sum += (q63_t) a2 *b2;
- sum += (q63_t) a3 *b3;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- colCnt = numColsA % 0x4u;
-
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- /* Perform the multiply-accumulates */
- sum += (q63_t) * pIn1++ * *pIn2;
- pIn2 += numColsB;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
- *px++ = (q31_t) (sum >> 31);
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- j++;
- pIn2 = (pSrcB->pData) + j;
-
- /* Decrement the column loop counter */
- col--;
-
- } while (col > 0u);
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */
- uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
- arm_status status; /* status of matrix multiplication */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numCols != pSrcB->numRows) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
- /* row loop */
- do
- {
- /* Output pointer is set to starting address of the row being processed */
- px = pOut + i;
-
- /* For every row wise process, the column loop counter is to be initiated */
- col = numColsB;
-
- /* For every row wise process, the pIn2 pointer is set
- ** to the starting address of the pSrcB data */
- pIn2 = pSrcB->pData;
-
- /* column loop */
- do
- {
- /* Set the variable sum, that acts as accumulator, to zero */
- sum = 0;
-
- /* Initiate the pointer pIn1 to point to the starting address of pInA */
- pIn1 = pInA;
-
- /* Matrix A columns number of MAC operations are to be performed */
- colCnt = numColsA;
-
- /* matrix multiplication */
- while (colCnt > 0u)
- {
- /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
- /* Perform the multiply-accumulates */
- sum += (q63_t) * pIn1++ * *pIn2;
- pIn2 += numColsB;
-
- /* Decrement the loop counter */
- colCnt--;
- }
-
- /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
- *px++ = (q31_t) clip_q63_to_q31(sum >> 31);
-
- /* Decrement the column loop counter */
- col--;
-
- /* Update the pointer pIn2 to point to the starting address of the next column */
- pIn2 = pInB + (numColsB - col);
-
- } while (col > 0u);
-
-#endif
-
- /* Update the pointer pInA to point to the starting address of the next row */
- i = i + numColsB;
- pInA = pInA + numColsA;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixMult group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c
deleted file mode 100644
index 8e304dd..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_scale_f32.c
- * Description: Multiplies a floating-point matrix by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixScale Matrix Scale
- *
- * Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the
- * matrix by the scalar. For example:
- * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"
- *
- * The function checks to make sure that the input and output matrices are of the same size.
- *
- * In the fixed-point Q15 and Q31 functions, scale is represented by
- * a fractional multiplication scaleFract and an arithmetic shift shift.
- * The shift allows the gain of the scaling operation to exceed 1.0.
- * The overall scale factor applied to the fixed-point data is
- *
- * scale = scaleFract * 2^shift.
- *
- */
-
-/**
- * @addtogroup MatrixScale
- * @{
- */
-
-/**
- * @brief Floating-point matrix scaling.
- * @param[in] *pSrc points to input matrix structure
- * @param[in] scale scale factor to be applied
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- */
-
-arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn = pSrc->pData; /* input data matrix pointer */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix scaling */
-
-#if defined (ARM_MATH_DSP)
-
- float32_t in1, in2, in3, in4; /* temporary variables */
- float32_t out1, out2, out3, out4; /* temporary variables */
-
-#endif // #if defined (ARM_MATH_DSP)
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop Unrolling */
- blkCnt = numSamples >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * scale */
- /* Scaling and results are stored in the destination buffer. */
- in1 = pIn[0];
- in2 = pIn[1];
- in3 = pIn[2];
- in4 = pIn[3];
-
- out1 = in1 * scale;
- out2 = in2 * scale;
- out3 = in3 * scale;
- out4 = in4 * scale;
-
-
- pOut[0] = out1;
- pOut[1] = out2;
- pOut[2] = out3;
- pOut[3] = out4;
-
- /* update pointers to process next sampels */
- pIn += 4u;
- pOut += 4u;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * scale */
- /* The results are stored in the destination buffer. */
- *pOut++ = (*pIn++) * scale;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixScale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c
deleted file mode 100644
index 357a397..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_scale_q15.c
- * Description: Multiplies a Q15 matrix by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixScale
- * @{
- */
-
-/**
- * @brief Q15 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The input data *pSrc and scaleFract are in 1.15 format.
- * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
- */
-
-arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst)
-{
- q15_t *pIn = pSrc->pData; /* input data matrix pointer */
- q15_t *pOut = pDst->pData; /* output data matrix pointer */
- uint32_t numSamples; /* total number of elements in the matrix */
- int32_t totShift = 15 - shift; /* total shift to apply after scaling */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix scaling */
-
-#if defined (ARM_MATH_DSP)
-
- q15_t in1, in2, in3, in4;
- q31_t out1, out2, out3, out4;
- q31_t inA1, inA2;
-
-#endif // #if defined (ARM_MATH_DSP)
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch */
- if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif // #ifdef ARM_MATH_MATRIX_CHECK
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- /* Loop Unrolling */
- blkCnt = numSamples >> 2;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * k */
- /* Scale, saturate and then store the results in the destination buffer. */
- /* Reading 2 inputs from memory */
- inA1 = _SIMD32_OFFSET(pIn);
- inA2 = _SIMD32_OFFSET(pIn + 2);
-
- /* C = A * scale */
- /* Scale the inputs and then store the 2 results in the destination buffer
- * in single cycle by packing the outputs */
- out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
- out2 = (q31_t) ((q15_t) inA1 * scaleFract);
- out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
- out4 = (q31_t) ((q15_t) inA2 * scaleFract);
-
- out1 = out1 >> totShift;
- inA1 = _SIMD32_OFFSET(pIn + 4);
- out2 = out2 >> totShift;
- inA2 = _SIMD32_OFFSET(pIn + 6);
- out3 = out3 >> totShift;
- out4 = out4 >> totShift;
-
- in1 = (q15_t) (__SSAT(out1, 16));
- in2 = (q15_t) (__SSAT(out2, 16));
- in3 = (q15_t) (__SSAT(out3, 16));
- in4 = (q15_t) (__SSAT(out4, 16));
-
- _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
- _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
-
- /* update pointers to process next sampels */
- pIn += 4u;
- pOut += 4u;
-
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * k */
- /* Scale, saturate and then store the results in the destination buffer. */
- *pOut++ =
- (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixScale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c
deleted file mode 100644
index 9af0491..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_scale_q31.c
- * Description: Multiplies a Q31 matrix by a scalar
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixScale
- * @{
- */
-
-/**
- * @brief Q31 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The input data *pSrc and scaleFract are in 1.31 format.
- * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
- */
-
-arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn = pSrc->pData; /* input data matrix pointer */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- uint32_t numSamples; /* total number of elements in the matrix */
- int32_t totShift = shift + 1; /* shift to apply after scaling */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix scaling */
- q31_t in1, in2, out1; /* temporary variabels */
-
-#if defined (ARM_MATH_DSP)
-
- q31_t in3, in4, out2, out3, out4; /* temporary variables */
-
-#endif // #ifndef ARM_MAT_CM0
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch */
- if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif // #ifdef ARM_MATH_MATRIX_CHECK
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * k */
- /* Read values from input */
- in1 = *pIn;
- in2 = *(pIn + 1);
- in3 = *(pIn + 2);
- in4 = *(pIn + 3);
-
- /* multiply input with scaler value */
- in1 = ((q63_t) in1 * scaleFract) >> 32;
- in2 = ((q63_t) in2 * scaleFract) >> 32;
- in3 = ((q63_t) in3 * scaleFract) >> 32;
- in4 = ((q63_t) in4 * scaleFract) >> 32;
-
- /* apply shifting */
- out1 = in1 << totShift;
- out2 = in2 << totShift;
-
- /* saturate the results. */
- if (in1 != (out1 >> totShift))
- out1 = 0x7FFFFFFF ^ (in1 >> 31);
-
- if (in2 != (out2 >> totShift))
- out2 = 0x7FFFFFFF ^ (in2 >> 31);
-
- out3 = in3 << totShift;
- out4 = in4 << totShift;
-
- *pOut = out1;
- *(pOut + 1) = out2;
-
- if (in3 != (out3 >> totShift))
- out3 = 0x7FFFFFFF ^ (in3 >> 31);
-
- if (in4 != (out4 >> totShift))
- out4 = 0x7FFFFFFF ^ (in4 >> 31);
-
-
- *(pOut + 2) = out3;
- *(pOut + 3) = out4;
-
- /* update pointers to process next sampels */
- pIn += 4u;
- pOut += 4u;
-
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) * k */
- /* Scale, saturate and then store the results in the destination buffer. */
- in1 = *pIn++;
-
- in2 = ((q63_t) in1 * scaleFract) >> 32;
-
- out1 = in2 << totShift;
-
- if (in2 != (out1 >> totShift))
- out1 = 0x7FFFFFFF ^ (in2 >> 31);
-
- *pOut++ = out1;
-
- /* Decrement the numSamples loop counter */
- blkCnt--;
- }
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixScale group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c
deleted file mode 100644
index 048d578..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_sub_f32.c
- * Description: Floating-point matrix subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @defgroup MatrixSub Matrix Subtraction
- *
- * Subtract two matrices.
- * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"
- *
- * The functions check to make sure that
- * pSrcA, pSrcB, and pDst have the same
- * number of rows and columns.
- */
-
-/**
- * @addtogroup MatrixSub
- * @{
- */
-
-/**
- * @brief Floating-point matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
-
-#if defined (ARM_MATH_DSP)
-
- float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
-
-#endif // #if defined (ARM_MATH_DSP)
-
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix subtraction */
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract and then store the results in the destination buffer. */
- /* Read values from source A */
- inA1 = pIn1[0];
-
- /* Read values from source B */
- inB1 = pIn2[0];
-
- /* Read values from source A */
- inA2 = pIn1[1];
-
- /* out = sourceA - sourceB */
- out1 = inA1 - inB1;
-
- /* Read values from source B */
- inB2 = pIn2[1];
-
- /* Read values from source A */
- inA1 = pIn1[2];
-
- /* out = sourceA - sourceB */
- out2 = inA2 - inB2;
-
- /* Read values from source B */
- inB1 = pIn2[2];
-
- /* Store result in destination */
- pOut[0] = out1;
- pOut[1] = out2;
-
- /* Read values from source A */
- inA2 = pIn1[3];
-
- /* Read values from source B */
- inB2 = pIn2[3];
-
- /* out = sourceA - sourceB */
- out1 = inA1 - inB1;
-
-
- /* out = sourceA - sourceB */
- out2 = inA2 - inB2;
-
- /* Store result in destination */
- pOut[2] = out1;
-
- /* Store result in destination */
- pOut[3] = out2;
-
-
- /* update pointers to process next sampels */
- pIn1 += 4u;
- pIn2 += 4u;
- pOut += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract and then store the results in the destination buffer. */
- *pOut++ = (*pIn1++) - (*pIn2++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c
deleted file mode 100644
index ebf5671..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_sub_q15.c
- * Description: Q15 Matrix subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixSub
- * @{
- */
-
-/**
- * @brief Q15 matrix subtraction.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- */
-
-arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst)
-{
- q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
- q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
- q15_t *pOut = pDst->pData; /* output data matrix pointer */
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix subtraction */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Apply loop unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract, Saturate and then store the results in the destination buffer. */
- *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
- *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract and then store the results in the destination buffer. */
- *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract and then store the results in the destination buffer. */
- *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c
deleted file mode 100644
index d3ab00c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_sub_q31.c
- * Description: Q31 matrix subtraction
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixSub
- * @{
- */
-
-/**
- * @brief Q31 matrix subtraction.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
- */
-
-
-arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
- q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- q31_t inA1, inB1; /* temporary variables */
-
-#if defined (ARM_MATH_DSP)
-
- q31_t inA2, inB2; /* temporary variables */
- q31_t out1, out2; /* temporary variables */
-
-#endif // #if defined (ARM_MATH_DSP)
-
- uint32_t numSamples; /* total number of elements in the matrix */
- uint32_t blkCnt; /* loop counters */
- arm_status status; /* status of matrix subtraction */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
- /* Check for matrix mismatch condition */
- if ((pSrcA->numRows != pSrcB->numRows) ||
- (pSrcA->numCols != pSrcB->numCols) ||
- (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif
- {
- /* Total number of samples in the input matrix */
- numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Loop Unrolling */
- blkCnt = numSamples >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract, saturate and then store the results in the destination buffer. */
- /* Read values from source A */
- inA1 = pIn1[0];
-
- /* Read values from source B */
- inB1 = pIn2[0];
-
- /* Read values from source A */
- inA2 = pIn1[1];
-
- /* Subtract and saturate */
- out1 = __QSUB(inA1, inB1);
-
- /* Read values from source B */
- inB2 = pIn2[1];
-
- /* Read values from source A */
- inA1 = pIn1[2];
-
- /* Subtract and saturate */
- out2 = __QSUB(inA2, inB2);
-
- /* Read values from source B */
- inB1 = pIn2[2];
-
- /* Store result in destination */
- pOut[0] = out1;
- pOut[1] = out2;
-
- /* Read values from source A */
- inA2 = pIn1[3];
-
- /* Read values from source B */
- inB2 = pIn2[3];
-
- /* Subtract and saturate */
- out1 = __QSUB(inA1, inB1);
-
- /* Subtract and saturate */
- out2 = __QSUB(inA2, inB2);
-
- /* Store result in destination */
- pOut[2] = out1;
- pOut[3] = out2;
-
- /* update pointers to process next samples */
- pIn1 += 4u;
- pIn2 += 4u;
- pOut += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = numSamples % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initialize blkCnt with number of samples */
- blkCnt = numSamples;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C(m,n) = A(m,n) - B(m,n) */
- /* Subtract, saturate and then store the results in the destination buffer. */
- inA1 = *pIn1++;
- inB1 = *pIn2++;
-
- inA1 = __QSUB(inA1, inB1);
-
- *pOut++ = inA1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixSub group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c
deleted file mode 100644
index 95021ab..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_trans_f32.c
- * Description: Floating-point matrix transpose
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @defgroup MatrixTrans Matrix Transpose
- *
- * Tranposes a matrix.
- * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.
- * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixTrans
- * @{
- */
-
-/**
- * @brief Floating-point matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-
-arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst)
-{
- float32_t *pIn = pSrc->pData; /* input data matrix pointer */
- float32_t *pOut = pDst->pData; /* output data matrix pointer */
- float32_t *px; /* Temporary output data matrix pointer */
- uint16_t nRows = pSrc->numRows; /* number of rows */
- uint16_t nColumns = pSrc->numCols; /* number of columns */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
- arm_status status; /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
- /* Loop Unrolling */
- blkCnt = nColumns >> 2;
-
- /* The pointer px is set to starting address of the column being processed */
- px = pOut + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u) /* column loop */
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- blkCnt--;
- }
-
- /* Perform matrix transpose for last 3 samples here. */
- blkCnt = nColumns % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- uint16_t col, i = 0u, row = nRows; /* loop counters */
- arm_status status; /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
- /* The pointer px is set to starting address of the column being processed */
- px = pOut + i;
-
- /* Initialize column loop counter */
- col = nColumns;
-
- while (col > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- col--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- i++;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u); /* row loop end */
-
- /* Set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixTrans group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c
deleted file mode 100644
index 16993d0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_trans_q15.c
- * Description: Q15 matrix transpose
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixTrans
- * @{
- */
-
-/*
- * @brief Q15 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst)
-{
- q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */
- q15_t *pOut = pDst->pData; /* output data matrix pointer */
- uint16_t nRows = pSrc->numRows; /* number of nRows */
- uint16_t nColumns = pSrc->numCols; /* number of nColumns */
- uint16_t col, row = nRows, i = 0u; /* row and column loop counters */
- arm_status status; /* status of matrix transpose */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- q31_t in; /* variable to hold temporary output */
-
-#else
-
- q15_t in;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
-
- /* Apply loop unrolling and exchange the columns with row elements */
- col = nColumns >> 2u;
-
- /* The pointer pOut is set to starting address of the column being processed */
- pOut = pDst->pData + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (col > 0u)
- {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
- /* Read two elements from the row */
- in = *__SIMD32(pSrcA)++;
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *pOut = (q15_t) in;
-
-#else
-
- *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer pOut to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *pOut = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer pOut to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Read two elements from the row */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- in = *__SIMD32(pSrcA)++;
-
-#else
-
- in = *__SIMD32(pSrcA)++;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *pOut = (q15_t) in;
-
-#else
-
- *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Update the pointer pOut to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
- *pOut = (q15_t) in;
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
-#else
- /* Read one element from the row */
- in = *pSrcA++;
-
- /* Store one element in the destination */
- *pOut = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Read one element from the row */
- in = *pSrcA++;
-
- /* Store one element in the destination */
- *pOut = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Read one element from the row */
- in = *pSrcA++;
-
- /* Store one element in the destination */
- *pOut = in;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Read one element from the row */
- in = *pSrcA++;
-
- /* Store one element in the destination */
- *pOut = in;
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /* Update the pointer pOut to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- /* Perform matrix transpose for last 3 samples here. */
- col = nColumns % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
- /* The pointer pOut is set to starting address of the column being processed */
- pOut = pDst->pData + i;
-
- /* Initialize column loop counter */
- col = nColumns;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (col > 0u)
- {
- /* Read and store the input element in the destination */
- *pOut = *pSrcA++;
-
- /* Update the pointer pOut to point to the next row of the transposed matrix */
- pOut += nRows;
-
- /* Decrement the column loop counter */
- col--;
- }
-
- i++;
-
- /* Decrement the row loop counter */
- row--;
-
- } while (row > 0u);
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixTrans group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c
deleted file mode 100644
index 152fb63..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mat_trans_q31.c
- * Description: Q31 matrix transpose
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupMatrix
- */
-
-/**
- * @addtogroup MatrixTrans
- * @{
- */
-
-/*
- * @brief Q31 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-
-arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst)
-{
- q31_t *pIn = pSrc->pData; /* input data matrix pointer */
- q31_t *pOut = pDst->pData; /* output data matrix pointer */
- q31_t *px; /* Temporary output data matrix pointer */
- uint16_t nRows = pSrc->numRows; /* number of nRows */
- uint16_t nColumns = pSrc->numCols; /* number of nColumns */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
- arm_status status; /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
- /* Apply loop unrolling and exchange the columns with row elements */
- blkCnt = nColumns >> 2u;
-
- /* The pointer px is set to starting address of the column being processed */
- px = pOut + i;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- blkCnt--;
- }
-
- /* Perform matrix transpose for last 3 samples here. */
- blkCnt = nColumns % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- blkCnt--;
- }
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- uint16_t col, i = 0u, row = nRows; /* loop counters */
- arm_status status; /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
- /* Check for matrix mismatch condition */
- if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
- {
- /* Set status as ARM_MATH_SIZE_MISMATCH */
- status = ARM_MATH_SIZE_MISMATCH;
- }
- else
-#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
-
- {
- /* Matrix transpose by exchanging the rows with columns */
- /* row loop */
- do
- {
- /* The pointer px is set to starting address of the column being processed */
- px = pOut + i;
-
- /* Initialize column loop counter */
- col = nColumns;
-
- while (col > 0u)
- {
- /* Read and store the input element in the destination */
- *px = *pIn++;
-
- /* Update the pointer px to point to the next row of the transposed matrix */
- px += nRows;
-
- /* Decrement the column loop counter */
- col--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- i++;
-
- /* Decrement the row loop counter */
- row--;
-
- }
- while (row > 0u); /* row loop end */
-
- /* set status as ARM_MATH_SUCCESS */
- status = ARM_MATH_SUCCESS;
- }
-
- /* Return to application */
- return (status);
-}
-
-/**
- * @} end of MatrixTrans group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
deleted file mode 100644
index cf2cff6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_max_f32.c
- * Description: Maximum value of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup Max Maximum
- *
- * Computes the maximum value of an array of data.
- * The function returns both the maximum value and its position within the array.
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup Max
- * @{
- */
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
-void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- float32_t maxVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and it's index */
- out = maxVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the maximum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Max group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
deleted file mode 100644
index 812ecdb..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_max_q15.c
- * Description: Maximum value of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup Max
- * @{
- */
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
-void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q15_t maxVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and it's index */
- out = maxVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the maximum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Max group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
deleted file mode 100644
index dbd4b69..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_max_q31.c
- * Description: Maximum value of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup Max
- * @{
- */
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
-void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q31_t maxVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and it's index */
- out = maxVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the maximum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Max group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
deleted file mode 100644
index dda61ad..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_max_q7.c
- * Description: Maximum value of a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup Max
- * @{
- */
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
-void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
- maxVal2 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and its index */
- out = maxVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the maximum value */
- if (out < maxVal2)
- {
- /* Update the maximum value and its index */
- out = maxVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q7_t maxVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize maxVal to the next consecutive values one by one */
- maxVal1 = *pSrc++;
-
- /* compare for the maximum value */
- if (out < maxVal1)
- {
- /* Update the maximum value and it's index */
- out = maxVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the maximum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Max group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
deleted file mode 100644
index 98f643f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mean_f32.c
- * Description: Mean value of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup mean Mean
- *
- * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
- * The underlying algorithm is used:
- *
- *
- * Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
- *
- *
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup mean
- * @{
- */
-
-
-/**
- * @brief Mean value of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult mean value returned here
- * @return none.
- */
-
-void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult)
-{
- float32_t sum = 0.0f; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- sum += in1;
- sum += in2;
- sum += in3;
- sum += in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- sum += *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
- /* Store the result to the destination */
- *pResult = sum / (float32_t) blockSize;
-}
-
-/**
- * @} end of mean group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
deleted file mode 100644
index 6c6335a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mean_q15.c
- * Description: Mean value of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup mean
- * @{
- */
-
-
-/**
- * @brief Mean value of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult mean value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * The input is represented in 1.15 format and is accumulated in a 32-bit
- * accumulator in 17.15 format.
- * There is no risk of internal overflow with this approach, and the
- * full precision of intermediate result is preserved.
- * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.
- *
- */
-
-void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult)
-{
- q31_t sum = 0; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- sum += *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
- /* Store the result to the destination */
- *pResult = (q15_t) (sum / (q31_t)blockSize);
-}
-
-/**
- * @} end of mean group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
deleted file mode 100644
index 2d8f468..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mean_q31.c
- * Description: Mean value of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup mean
- * @{
- */
-
-
-/**
- * @brief Mean value of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult mean value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *\par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.31 format and is accumulated in a 64-bit
- * accumulator in 33.31 format.
- * There is no risk of internal overflow with this approach, and the
- * full precision of intermediate result is preserved.
- * Finally, the accumulator is truncated to yield a result of 1.31 format.
- *
- */
-
-void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult)
-{
- q63_t sum = 0; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- sum += in1;
- sum += in2;
- sum += in3;
- sum += in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- sum += *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
- /* Store the result to the destination */
- *pResult = (q31_t) (sum / (int32_t) blockSize);
-}
-
-/**
- * @} end of mean group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
deleted file mode 100644
index efee11d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_mean_q7.c
- * Description: Mean value of a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup mean
- * @{
- */
-
-
-/**
- * @brief Mean value of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult mean value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * The input is represented in 1.7 format and is accumulated in a 32-bit
- * accumulator in 25.7 format.
- * There is no risk of internal overflow with this approach, and the
- * full precision of intermediate result is preserved.
- * Finally, the accumulator is truncated to yield a result of 1.7 format.
- *
- */
-
-void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult)
-{
- q31_t sum = 0; /* Temporary result storage */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- in = *__SIMD32(pSrc)++;
-
- sum += ((in << 24u) >> 24u);
- sum += ((in << 16u) >> 24u);
- sum += ((in << 8u) >> 24u);
- sum += (in >> 24u);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- sum += *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
- /* Store the result to the destination */
- *pResult = (q7_t) (sum / (int32_t) blockSize);
-}
-
-/**
- * @} end of mean group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
deleted file mode 100644
index 4acf8fc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_min_f32.c
- * Description: Minimum value of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup Min Minimum
- *
- * Computes the minimum value of an array of data.
- * The function returns both the minimum value and its position within the array.
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup Min
- * @{
- */
-
-
-/**
- * @brief Minimum value of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult minimum value returned here
- * @param[out] *pIndex index of minimum value returned here
- * @return none.
- */
-
-void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- float32_t minVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and it's index */
- out = minVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the minimum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Min group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
deleted file mode 100644
index 639787a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_min_q15.c
- * Description: Minimum value of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-
-/**
- * @addtogroup Min
- * @{
- */
-
-
-/**
- * @brief Minimum value of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult minimum value returned here
- * @param[out] *pIndex index of minimum value returned here
- * @return none.
- */
-
-void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q15_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q15_t minVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and it's index */
- out = minVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the minimum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Min group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
deleted file mode 100644
index eb9e0c5..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_min_q31.c
- * Description: Minimum value of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-
-/**
- * @addtogroup Min
- * @{
- */
-
-
-/**
- * @brief Minimum value of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult minimum value returned here
- * @param[out] *pIndex index of minimum value returned here
- * @return none.
- */
-
-void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q31_t minVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and it's index */
- out = minVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the minimum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Min group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
deleted file mode 100644
index 41892f1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_min_q7.c
- * Description: Minimum value of a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-
-/**
- * @addtogroup Min
- * @{
- */
-
-
-/**
- * @brief Minimum value of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult minimum value returned here
- * @param[out] *pIndex index of minimum value returned here
- * @return none.
- */
-
-void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex)
-{
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q7_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex, count; /* loop counter */
-
- /* Initialise the count value. */
- count = 0u;
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- /* Loop unrolling */
- blkCnt = (blockSize - 1u) >> 2u;
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 1u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 2u;
- }
-
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
- minVal2 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and its index */
- out = minVal1;
- outIndex = count + 3u;
- }
-
- /* compare for the minimum value */
- if (out > minVal2)
- {
- /* Update the minimum value and its index */
- out = minVal2;
- outIndex = count + 4u;
- }
-
- count += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* if (blockSize - 1u) is not multiple of 4 */
- blkCnt = (blockSize - 1u) % 4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q7_t minVal1, out; /* Temporary variables to store the output value. */
- uint32_t blkCnt, outIndex; /* loop counter */
-
- /* Initialise the index value to zero. */
- outIndex = 0u;
- /* Load first input value that act as reference value for comparision */
- out = *pSrc++;
-
- blkCnt = (blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* Initialize minVal to the next consecutive values one by one */
- minVal1 = *pSrc++;
-
- /* compare for the minimum value */
- if (out > minVal1)
- {
- /* Update the minimum value and it's index */
- out = minVal1;
- outIndex = blockSize - blkCnt;
- }
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the minimum value and it's index into destination pointers */
- *pResult = out;
- *pIndex = outIndex;
-}
-
-/**
- * @} end of Min group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
deleted file mode 100644
index c7de37c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_power_f32.c
- * Description: Sum of the squares of the elements of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup power Power
- *
- * Calculates the sum of the squares of the elements in the input vector.
- * The underlying algorithm is used:
- *
- *
- * Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
- *
- *
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup power
- * @{
- */
-
-
-/**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult sum of the squares value returned here
- * @return none.
- *
- */
-
-
-void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult)
-{
- float32_t sum = 0.0f; /* accumulator */
- float32_t in; /* Temporary variable to store input value */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* compute power and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the result to the destination */
- *pResult = sum;
-}
-
-/**
- * @} end of power group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
deleted file mode 100644
index 19a56c0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_power_q15.c
- * Description: Sum of the squares of the elements of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup power
- * @{
- */
-
-/**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult sum of the squares value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.15 format.
- * Intermediate multiplication yields a 2.30 format, and this
- * result is added without saturation to a 64-bit accumulator in 34.30 format.
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the return result is in 34.30 format.
- *
- */
-
-void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult)
-{
- q63_t sum = 0; /* Temporary result storage */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in32; /* Temporary variable to store input value */
- q15_t in16; /* Temporary variable to store input value */
- uint32_t blkCnt; /* loop counter */
-
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in32 = *__SIMD32(pSrc)++;
- sum = __SMLALD(in32, in32, sum);
- in32 = *__SIMD32(pSrc)++;
- sum = __SMLALD(in32, in32, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in16 = *pSrc++;
- sum = __SMLALD(in16, in16, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q15_t in; /* Temporary variable to store input value */
- uint32_t blkCnt; /* loop counter */
-
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += ((q31_t) in * in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Store the results in 34.30 format */
- *pResult = sum;
-}
-
-/**
- * @} end of power group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
deleted file mode 100644
index 9197377..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_power_q31.c
- * Description: Sum of the squares of the elements of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup power
- * @{
- */
-
-/**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult sum of the squares value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.31 format.
- * Intermediate multiplication yields a 2.62 format, and this
- * result is truncated to 2.48 format by discarding the lower 14 bits.
- * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
- * With 15 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the return result is in 16.48 format.
- *
- */
-
-void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult)
-{
- q63_t sum = 0; /* Temporary result storage */
- q31_t in;
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
- in = *pSrc++;
- sum += ((q63_t) in * in) >> 14u;
-
- in = *pSrc++;
- sum += ((q63_t) in * in) >> 14u;
-
- in = *pSrc++;
- sum += ((q63_t) in * in) >> 14u;
-
- in = *pSrc++;
- sum += ((q63_t) in * in) >> 14u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += ((q63_t) in * in) >> 14u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the results in 16.48 format */
- *pResult = sum;
-}
-
-/**
- * @} end of power group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
deleted file mode 100644
index 246f84e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_power_q7.c
- * Description: Sum of the squares of the elements of a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup power
- * @{
- */
-
-/**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult sum of the squares value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 32-bit internal accumulator.
- * The input is represented in 1.7 format.
- * Intermediate multiplication yields a 2.14 format, and this
- * result is added without saturation to an accumulator in 18.14 format.
- * With 17 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the return result is in 18.14 format.
- *
- */
-
-void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult)
-{
- q31_t sum = 0; /* Temporary result storage */
- q7_t in; /* Temporary variable to store input */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t input1; /* Temporary variable to store packed input */
- q31_t in1, in2; /* Temporary variables to store input */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* Reading two inputs of pSrc vector and packing */
- input1 = *__SIMD32(pSrc)++;
-
- in1 = __SXTB16(__ROR(input1, 8));
- in2 = __SXTB16(input1);
-
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* calculate power and accumulate to accumulator */
- sum = __SMLAD(in1, in1, sum);
- sum = __SMLAD(in2, in2, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute Power and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += ((q15_t) in * in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Store the result in 18.14 format */
- *pResult = sum;
-}
-
-/**
- * @} end of power group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
deleted file mode 100644
index 1e1bb90..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rms_f32.c
- * Description: Root mean square value of an array of F32 type
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup RMS Root mean square (RMS)
- *
- *
- * Calculates the Root Mean Sqaure of the elements in the input vector.
- * The underlying algorithm is used:
- *
- *
- * Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
- *
- *
- * There are separate functions for floating point, Q31, and Q15 data types.
- */
-
-/**
- * @addtogroup RMS
- * @{
- */
-
-
-/**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult rms value returned here
- * @return none.
- *
- */
-
-void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult)
-{
- float32_t sum = 0.0f; /* Accumulator */
- float32_t in; /* Tempoprary variable to store input value */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute sum of the squares and then store the result in a temporary variable, sum */
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
- in = *pSrc++;
- sum += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute sum of the squares and then store the results in a temporary variable, sum */
- in = *pSrc++;
- sum += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Rms and store the result in the destination */
- arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
-}
-
-/**
- * @} end of RMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
deleted file mode 100644
index acdd96b..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rms_q15.c
- * Description: Root Mean Square of the elements of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup RMS
- * @{
- */
-
-/**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult rms value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.15 format.
- * Intermediate multiplication yields a 2.30 format, and this
- * result is added without saturation to a 64-bit accumulator in 34.30 format.
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
- * 15 bits, and then saturated to yield a result in 1.15 format.
- *
- */
-
-void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult)
-{
- q63_t sum = 0; /* accumulator */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in; /* temporary variable to store the input value */
- q15_t in1; /* temporary variable to store the input value */
- uint32_t blkCnt; /* loop counter */
-
- /* loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute sum of the squares and then store the results in a temporary variable, sum */
- in = *__SIMD32(pSrc)++;
- sum = __SMLALD(in, in, sum);
- in = *__SIMD32(pSrc)++;
- sum = __SMLALD(in, in, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute sum of the squares and then store the results in a temporary variable, sum */
- in1 = *pSrc++;
- sum = __SMLALD(in1, in1, sum);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Truncating and saturating the accumulator to 1.15 format */
- /* Store the result in the destination */
- arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
-
-#else
- /* Run the below code for Cortex-M0 */
-
- q15_t in; /* temporary variable to store the input value */
- uint32_t blkCnt; /* loop counter */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute sum of the squares and then store the results in a temporary variable, sum */
- in = *pSrc++;
- sum += ((q31_t) in * in);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Truncating and saturating the accumulator to 1.15 format */
- /* Store the result in the destination */
- arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of RMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
deleted file mode 100644
index 7115d15..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rms_q31.c
- * Description: Root Mean Square of the elements of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup RMS
- * @{
- */
-
-
-/**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult rms value returned here
- * @return none.
- *
- * @details
- * Scaling and Overflow Behavior:
- *
- *\par
- * The function is implemented using an internal 64-bit accumulator.
- * The input is represented in 1.31 format, and intermediate multiplication
- * yields a 2.62 format.
- * The accumulator maintains full precision of the intermediate multiplication results,
- * but provides only a single guard bit.
- * There is no saturation on intermediate additions.
- * If the accumulator overflows, it wraps around and distorts the result.
- * In order to avoid overflows completely, the input signal must be scaled down by
- * log2(blockSize) bits, as a total of blockSize additions are performed internally.
- * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
- *
- */
-
-void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult)
-{
- q63_t sum = 0; /* accumulator */
- q31_t in; /* Temporary variable to store the input */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t in1, in2, in3, in4; /* Temporary input variables */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
- ** a second loop below computes the remaining 1 to 7 samples. */
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute sum of the squares and then store the result in a temporary variable, sum */
- /* read two samples from source buffer */
- in1 = pSrc[0];
- in2 = pSrc[1];
-
- /* calculate power and accumulate to accumulator */
- sum += (q63_t) in1 *in1;
- sum += (q63_t) in2 *in2;
-
- /* read two samples from source buffer */
- in3 = pSrc[2];
- in4 = pSrc[3];
-
- /* calculate power and accumulate to accumulator */
- sum += (q63_t) in3 *in3;
- sum += (q63_t) in4 *in4;
-
-
- /* update source buffer to process next samples */
- pSrc += 4u;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
- /* Compute sum of the squares and then store the results in a temporary variable, sum */
- in = *pSrc++;
- sum += (q63_t) in *in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
- /* Compute Rms and store the result in the destination vector */
- arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
-}
-
-/**
- * @} end of RMS group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
deleted file mode 100644
index f782ed6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_std_f32.c
- * Description: Standard deviation of the elements of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup STD Standard deviation
- *
- * Calculates the standard deviation of the elements in the input vector.
- * The underlying algorithm is used:
- *
- *
- * Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
- *
- * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
- *
- * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
- *
- *
- * There are separate functions for floating point, Q31, and Q15 data types.
- */
-
-/**
- * @addtogroup STD
- * @{
- */
-
-
-/**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult standard deviation value returned here
- * @return none.
- */
-
-void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult)
-{
- float32_t sum = 0.0f; /* Temporary result storage */
- float32_t sumOfSquares = 0.0f; /* Sum of squares */
- float32_t in; /* input value */
- uint32_t blkCnt; /* loop counter */
-#if defined (ARM_MATH_DSP)
- float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */
-#else
- float32_t squareOfSum; /* Square of Sum */
- float32_t var; /* Temporary varaince storage */
-#endif
-
- if (blockSize == 1u)
- {
- *pResult = 0;
- return;
- }
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += in;
- sumOfSquares += in * in;
- in = *pSrc++;
- sum += in;
- sumOfSquares += in * in;
- in = *pSrc++;
- sum += in;
- sumOfSquares += in * in;
- in = *pSrc++;
- sum += in;
- sumOfSquares += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++;
- sum += in;
- sumOfSquares += in * in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
-
- /* Compute mean of all input values */
- mean = sum / (float32_t) blockSize;
-
- /* Compute square of mean */
- squareOfMean = (mean * mean) * (((float32_t) blockSize) /
- ((float32_t) blockSize - 1.0f));
-
- /* Compute standard deviation and then store the result to the destination */
- arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sumOfSquares. */
- in = *pSrc++;
- sumOfSquares += in * in;
-
- /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
- /* Compute Sum of the input samples
- * and then store the result in a temporary variable, sum. */
- sum += in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute the square of sum */
- squareOfSum = ((sum * sum) / (float32_t) blockSize);
-
- /* Compute the variance */
- var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
-
- /* Compute standard deviation and then store the result to the destination */
- arm_sqrt_f32(var, pResult);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-/**
- * @} end of STD group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
deleted file mode 100644
index fe4e602..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_std_q15.c
- * Description: Standard deviation of an array of Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup STD
- * @{
- */
-
-/**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult standard deviation value returned here
- * @return none.
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.15 format.
- * Intermediate multiplication yields a 2.30 format, and this
- * result is added without saturation to a 64-bit accumulator in 34.30 format.
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
- * 15 bits, and then saturated to yield a result in 1.15 format.
- */
-
-void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult)
-{
- q31_t sum = 0; /* Accumulator */
- q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
- uint32_t blkCnt; /* loop counter */
- q63_t sumOfSquares = 0; /* Accumulator */
-#if defined (ARM_MATH_DSP)
- q31_t in; /* input value */
- q15_t in1; /* input value */
-#else
- q15_t in; /* input value */
-#endif
-
- if (blockSize == 1u)
- {
- *pResult = 0;
- return;
- }
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
- sumOfSquares = __SMLALD(in, in, sumOfSquares);
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
- sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in1 = *pSrc++;
- sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
- sum += in1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1u));
-
- /* Compute square of mean */
- squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1u)));
-
- /* mean of the squares minus the square of the mean. */
- /* Compute standard deviation and store the result to the destination */
- arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15u, 16u), pResult);
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sumOfSquares. */
- in = *pSrc++;
- sumOfSquares += (in * in);
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- /* Compute sum of all input values and then store the result in a temporary variable, sum. */
- sum += in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1u));
-
- /* Compute square of mean */
- squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1u)));
-
- /* mean of the squares minus the square of the mean. */
- /* Compute standard deviation and store the result to the destination */
- arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15u, 16u), pResult);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-/**
- * @} end of STD group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
deleted file mode 100644
index a88fc83..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_std_q31.c
- * Description: Standard deviation of an array of Q31 type.
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup STD
- * @{
- */
-
-/**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult standard deviation value returned here
- * @return none.
- * @details
- * Scaling and Overflow Behavior:
- *
- *\par
- * The function is implemented using an internal 64-bit accumulator.
- * The input is represented in 1.31 format, which is then downshifted by 8 bits
- * which yields 1.23, and intermediate multiplication yields a 2.46 format.
- * The accumulator maintains full precision of the intermediate multiplication results,
- * but provides only a 16 guard bits.
- * There is no saturation on intermediate additions.
- * If the accumulator overflows it wraps around and distorts the result.
- * In order to avoid overflows completely the input signal must be scaled down by
- * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
- * After division, internal variables should be Q18.46
- * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
- *
- */
-
-void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult)
-{
- q63_t sum = 0; /* Accumulator */
- q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
- q31_t in; /* input value */
- uint32_t blkCnt; /* loop counter */
- q63_t sumOfSquares = 0; /* Accumulator */
-
- if (blockSize == 1u)
- {
- *pResult = 0;
- return;
- }
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1u);
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sumOfSquares. */
- in = *pSrc++ >> 8u;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- /* Compute sum of all input values and then store the result in a temporary variable, sum. */
- sum += in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Compute square of mean */
- squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
-
- /* Compute standard deviation and then store the result to the destination */
- arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15u, pResult);
-}
-
-/**
- * @} end of STD group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
deleted file mode 100644
index e43f80c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_var_f32.c
- * Description: Variance of the elements of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @defgroup variance Variance
- *
- * Calculates the variance of the elements in the input vector.
- * The underlying algorithm used is the direct method sometimes referred to as the two-pass method:
- *
- *
- * Result = sum(element - meanOfElements)^2) / numElement - 1
- *
- * where, meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
- *
- *
- *
- * There are separate functions for floating point, Q31, and Q15 data types.
- */
-
-/**
- * @addtogroup variance
- * @{
- */
-
-
-/**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult variance value returned here
- * @return none.
- */
-
-void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult)
-{
- float32_t fMean, fValue;
- uint32_t blkCnt; /* loop counter */
- float32_t * pInput = pSrc;
- float32_t sum = 0.0f;
- float32_t fSum = 0.0f;
- #if defined(ARM_MATH_DSP)
- float32_t in1, in2, in3, in4;
- #endif
-
- if (blockSize <= 1u)
- {
- *pResult = 0;
- return;
- }
-
- #if defined(ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M7 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- in1 = *pInput++;
- in2 = *pInput++;
- in3 = *pInput++;
- in4 = *pInput++;
-
- sum += in1;
- sum += in2;
- sum += in3;
- sum += in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- #else
- /* Run the below code for Cortex-M0 or Cortex-M3 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- #endif
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- sum += *pInput++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
- fMean = sum / (float32_t) blockSize;
-
- pInput = pSrc;
-
- #if defined(ARM_MATH_DSP)
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- fValue = *pInput++ - fMean;
- fSum += fValue * fValue;
- fValue = *pInput++ - fMean;
- fSum += fValue * fValue;
- fValue = *pInput++ - fMean;
- fSum += fValue * fValue;
- fValue = *pInput++ - fMean;
- fSum += fValue * fValue;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- blkCnt = blockSize % 0x4u;
- #else
- /* Run the below code for Cortex-M0 or Cortex-M3 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
- #endif
-
- while (blkCnt > 0u)
- {
- fValue = *pInput++ - fMean;
- fSum += fValue * fValue;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Variance */
- *pResult = fSum / (float32_t)(blockSize - 1.0f);
-}
-
-/**
- * @} end of variance group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
deleted file mode 100644
index 4b2c267..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_var_q15.c
- * Description: Variance of an array of Q15 type
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup variance
- * @{
- */
-
-/**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult variance value returned here
- * @return none.
- * @details
- * Scaling and Overflow Behavior:
- *
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * The input is represented in 1.15 format.
- * Intermediate multiplication yields a 2.30 format, and this
- * result is added without saturation to a 64-bit accumulator in 34.30 format.
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the
- * full precision of the intermediate multiplication is preserved.
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
- * 15 bits, and then saturated to yield a result in 1.15 format.
- */
-
-void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult)
-{
- q31_t sum = 0; /* Accumulator */
- q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
- uint32_t blkCnt; /* loop counter */
- q63_t sumOfSquares = 0; /* Accumulator */
-#if defined (ARM_MATH_DSP)
- q31_t in; /* input value */
- q15_t in1; /* input value */
-#else
- q15_t in; /* input value */
-#endif
-
- if (blockSize == 1u)
- {
- *pResult = 0;
- return;
- }
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
- sumOfSquares = __SMLALD(in, in, sumOfSquares);
- in = *__SIMD32(pSrc)++;
- sum += ((in << 16u) >> 16u);
- sum += (in >> 16u);
- sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in1 = *pSrc++;
- sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
- sum += in1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1u));
-
- /* Compute square of mean */
- squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1u)));
-
- /* mean of the squares minus the square of the mean. */
- *pResult = (meanOfSquares - squareOfMean) >> 15u;
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sumOfSquares. */
- in = *pSrc++;
- sumOfSquares += (in * in);
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- /* Compute sum of all input values and then store the result in a temporary variable, sum. */
- sum += in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1u));
-
- /* Compute square of mean */
- squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1u)));
-
- /* mean of the squares minus the square of the mean. */
- *pResult = (meanOfSquares - squareOfMean) >> 15;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-/**
- * @} end of variance group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
deleted file mode 100644
index 1a23ee1..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_var_q31.c
- * Description: Variance of an array of Q31 type
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupStats
- */
-
-/**
- * @addtogroup variance
- * @{
- */
-
-/**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult variance value returned here
- * @return none.
- * @details
- * Scaling and Overflow Behavior:
- *
- *\par
- * The function is implemented using an internal 64-bit accumulator.
- * The input is represented in 1.31 format, which is then downshifted by 8 bits
- * which yields 1.23, and intermediate multiplication yields a 2.46 format.
- * The accumulator maintains full precision of the intermediate multiplication results,
- * but provides only a 16 guard bits.
- * There is no saturation on intermediate additions.
- * If the accumulator overflows it wraps around and distorts the result.
- * In order to avoid overflows completely the input signal must be scaled down by
- * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
- * After division, internal variables should be Q18.46
- * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
- *
- */
-
-void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult)
-{
- q63_t sum = 0; /* Accumulator */
- q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
- q31_t in; /* input value */
- uint32_t blkCnt; /* loop counter */
- q63_t sumOfSquares = 0; /* Accumulator */
-
- if (blockSize == 1u)
- {
- *pResult = 0;
- return;
- }
-
-#if defined (ARM_MATH_DSP)
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sum. */
- in = *pSrc++ >> 8u;
- sum += in;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1u);
-
-#else
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
- /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
- /* Compute Sum of squares of the input samples
- * and then store the result in a temporary variable, sumOfSquares. */
- in = *pSrc++ >> 8u;
- sumOfSquares += ((q63_t) (in) * (in));
-
- /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
- /* Compute sum of all input values and then store the result in a temporary variable, sum. */
- sum += in;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* Compute Mean of squares of the input samples
- * and then store the result in a temporary variable, meanOfSquares. */
- meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- /* Compute square of mean */
- squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
-
- /* Compute standard deviation and then store the result to the destination */
- *pResult = (meanOfSquares - squareOfMean) >> 15u;
-}
-
-/**
- * @} end of variance group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
deleted file mode 100644
index 328696d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_copy_f32.c
- * Description: Copies the elements of a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup copy Vector Copy
- *
- * Copies sample by sample from source vector to destination vector.
- *
- *
- * pDst[n] = pSrc[n]; 0 <= n < blockSize.
- *
- *
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup copy
- * @{
- */
-
-/**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] *pSrc points to input vector
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- */
-
-
-void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the results in the destination buffer */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- *pDst++ = in1;
- *pDst++ = in2;
- *pDst++ = in3;
- *pDst++ = in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the results in the destination buffer */
- *pDst++ = *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicCopy group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
deleted file mode 100644
index f0d0159..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_copy_q15.c
- * Description: Copies the elements of a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup copy
- * @{
- */
-/**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] *pSrc points to input vector
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- */
-
-void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Read two inputs */
- *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
- *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the value in the destination buffer */
- *pDst++ = *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicCopy group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
deleted file mode 100644
index 50d5aac..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_copy_q31.c
- * Description: Copies the elements of a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup copy
- * @{
- */
-
-/**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] *pSrc points to input vector
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- */
-
-void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the values in the destination buffer */
- in1 = *pSrc++;
- in2 = *pSrc++;
- in3 = *pSrc++;
- in4 = *pSrc++;
-
- *pDst++ = in1;
- *pDst++ = in2;
- *pDst++ = in3;
- *pDst++ = in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the value in the destination buffer */
- *pDst++ = *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicCopy group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
deleted file mode 100644
index 040ef1e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_copy_q7.c
- * Description: Copies the elements of a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup copy
- * @{
- */
-
-/**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] *pSrc points to input vector
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- */
-
-void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the results in the destination buffer */
- /* 4 samples are copied and stored at a time using SIMD */
- *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = A */
- /* Copy and then store the results in the destination buffer */
- *pDst++ = *pSrc++;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of BasicCopy group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
deleted file mode 100644
index a26a6dc..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fill_f32.c
- * Description: Fills a constant value into a floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup Fill Vector Fill
- *
- * Fills the destination vector with a constant value.
- *
- *
- * pDst[n] = value; 0 <= n < blockSize.
- *
- *
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.
- */
-
-/**
- * @addtogroup Fill
- * @{
- */
-
-/**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the output vector
- * @return none.
- *
- */
-
-
-void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- float32_t in1 = value;
- float32_t in2 = value;
- float32_t in3 = value;
- float32_t in4 = value;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = in1;
- *pDst++ = in2;
- *pDst++ = in3;
- *pDst++ = in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = value;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of Fill group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
deleted file mode 100644
index 324a346..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fill_q15.c
- * Description: Fills a constant value into a Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup Fill
- * @{
- */
-
-/**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the output vector
- * @return none.
- *
- */
-
-void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t packedValue; /* value packed to 32 bits */
-
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Packing two 16 bit values to 32 bit value in order to use SIMD */
- packedValue = __PKHBT(value, value, 16u);
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *__SIMD32(pDst)++ = packedValue;
- *__SIMD32(pDst)++ = packedValue;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = value;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of Fill group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
deleted file mode 100644
index 18de639..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fill_q31.c
- * Description: Fills a constant value into a Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup Fill
- * @{
- */
-
-/**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the output vector
- * @return none.
- *
- */
-
-void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1 = value;
- q31_t in2 = value;
- q31_t in3 = value;
- q31_t in4 = value;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = in1;
- *pDst++ = in2;
- *pDst++ = in3;
- *pDst++ = in4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = value;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of Fill group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
deleted file mode 100644
index 9f1ccd0..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_fill_q7.c
- * Description: Fills a constant value into a Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup Fill
- * @{
- */
-
-/**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst points to output vector
- * @param[in] blockSize length of the output vector
- * @return none.
- *
- */
-
-void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize)
-{
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t packedValue; /* value packed to 32 bits */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* Packing four 8 bit values to 32 bit value in order to use SIMD */
- packedValue = __PACKq7(value, value, value, value);
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *__SIMD32(pDst)++ = packedValue;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = value */
- /* Fill the value in the destination buffer */
- *pDst++ = value;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of Fill group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
deleted file mode 100644
index 69fb1e2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_float_to_q15.c
- * Description: Converts the elements of the floating-point vector to Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup float_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- * \par
- * The equation used for the conversion process is:
- *
- * pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
- *
- * \par Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
- * \note
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
- * defined in the preprocessor section of project options.
- *
- */
-
-
-void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
- float32_t in;
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 32768.0f);
- in += in > 0 ? 0.5f : -0.5f;
- *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
- /* C = A * 32768 */
- /* convert from float to q15 and then store the results in the destination buffer */
- *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of float_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
deleted file mode 100644
index bbba335..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_float_to_q31.c
- * Description: Converts the elements of the floating-point vector to Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup float_to_x Convert 32-bit floating point value
- */
-
-/**
- * @addtogroup float_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- *\par Description:
- * \par
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
- *
- * Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
- *
- * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro
- * defined in the preprocessor section of project options.
- */
-
-
-void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
- float32_t in;
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
-
- /* C = A * 32768 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
- /* C = A * 2147483648 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
-
- /* C = A * 2147483648 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
- /* C = A * 2147483648 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
-
- /* C = A * 2147483648 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 2147483648.0f);
- in += in > 0 ? 0.5f : -0.5f;
- *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
- /* C = A * 2147483648 */
- /* convert from float to Q31 and then store the results in the destination buffer */
- *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of float_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
deleted file mode 100644
index 6a232a8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_float_to_q7.c
- * Description: Converts the elements of the floating-point vector to Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup float_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- *\par Description:
- * \par
- * The equation used for the conversion process is:
- *
- * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
- *
- * \par Scaling and Overflow Behavior:
- * \par
- * The function uses saturating arithmetic.
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
- * \note
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
- * defined in the preprocessor section of project options.
- */
-
-
-void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- float32_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
- float32_t in;
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 128);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
- in = *pIn++;
- in = (in * 128);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
- in = *pIn++;
- in = (in * 128);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
- in = *pIn++;
- in = (in * 128);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
- *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
- *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
- *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
- while (blkCnt > 0u)
- {
-
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 128);
- in += in > 0.0f ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
- while (blkCnt > 0u)
- {
-#ifdef ARM_MATH_ROUNDING
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- in = *pIn++;
- in = (in * 128.0f);
- in += in > 0 ? 0.5f : -0.5f;
- *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
-
-#else
-
- /* C = A * 128 */
- /* convert from float to q7 and then store the results in the destination buffer */
- *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /* #ifdef ARM_MATH_ROUNDING */
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of float_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
deleted file mode 100644
index 5394a4c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q15_to_float.c
- * Description: Converts the elements of the Q15 vector to floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup q15_to_x Convert 16-bit Integer value
- */
-
-/**
- * @addtogroup q15_to_x
- * @{
- */
-
-
-
-
-/**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] *pSrc points to the Q15 input vector
- * @param[out] *pDst points to the floating-point output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 32768 */
- /* convert from q15 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 32768.0f);
- *pDst++ = ((float32_t) * pIn++ / 32768.0f);
- *pDst++ = ((float32_t) * pIn++ / 32768.0f);
- *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 32768 */
- /* convert from q15 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of q15_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
deleted file mode 100644
index f6ba787..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q15_to_q31.c
- * Description: Converts the elements of the Q15 vector to Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q15_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] *pSrc points to the Q15 input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2;
- q31_t out1, out2, out3, out4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q31_t)A << 16 */
- /* convert from q15 to q31 and then store the results in the destination buffer */
- in1 = *__SIMD32(pIn)++;
- in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* extract lower 16 bits to 32 bit result */
- out1 = in1 << 16u;
- /* extract upper 16 bits to 32 bit result */
- out2 = in1 & 0xFFFF0000;
- /* extract lower 16 bits to 32 bit result */
- out3 = in2 << 16u;
- /* extract upper 16 bits to 32 bit result */
- out4 = in2 & 0xFFFF0000;
-
-#else
-
- /* extract upper 16 bits to 32 bit result */
- out1 = in1 & 0xFFFF0000;
- /* extract lower 16 bits to 32 bit result */
- out2 = in1 << 16u;
- /* extract upper 16 bits to 32 bit result */
- out3 = in2 & 0xFFFF0000;
- /* extract lower 16 bits to 32 bit result */
- out4 = in2 << 16u;
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- *pDst++ = out1;
- *pDst++ = out2;
- *pDst++ = out3;
- *pDst++ = out4;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q31_t)A << 16 */
- /* convert from q15 to q31 and then store the results in the destination buffer */
- *pDst++ = (q31_t) * pIn++ << 16;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q15_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
deleted file mode 100644
index 6f19eec..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q15_to_q7.c
- * Description: Converts the elements of the Q15 vector to Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q15_to_x
- * @{
- */
-
-
-/**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] *pSrc points to the Q15 input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- q15_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2;
- q31_t out1, out2;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q7_t) A >> 8 */
- /* convert from q15 to q7 and then store the results in the destination buffer */
- in1 = *__SIMD32(pIn)++;
- in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __PKHTB(in2, in1, 16);
- out2 = __PKHBT(in2, in1, 16);
-
-#else
-
- out1 = __PKHTB(in1, in2, 16);
- out2 = __PKHBT(in1, in2, 16);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- /* rotate packed value by 24 */
- out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
-
- /* anding with 0xff00ff00 to get two 8 bit values */
- out1 = out1 & 0xFF00FF00;
- /* anding with 0x00ff00ff to get two 8 bit values */
- out2 = out2 & 0x00FF00FF;
-
- /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
- out1 = out1 | out2;
-
- /* store 4 samples at a time to destiantion buffer */
- *__SIMD32(pDst)++ = out1;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q7_t) A >> 8 */
- /* convert from q15 to q7 and then store the results in the destination buffer */
- *pDst++ = (q7_t) (*pIn++ >> 8);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q15_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
deleted file mode 100644
index 5a0360a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q31_to_float.c
- * Description: Converts the elements of the Q31 vector to floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup q31_to_x Convert 32-bit Integer value
- */
-
-/**
- * @addtogroup q31_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] *pSrc points to the Q31 input vector
- * @param[out] *pDst points to the floating-point output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 2147483648 */
- /* convert from q31 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
- *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
- *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
- *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 2147483648 */
- /* convert from q31 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of q31_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
deleted file mode 100644
index c2d1faf..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q31_to_q15.c
- * Description: Converts the elements of the Q31 vector to Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q31_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] *pSrc points to the Q31 input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
- q31_t out1, out2;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q15_t) A >> 16 */
- /* convert from q31 to q15 and then store the results in the destination buffer */
- in1 = *pIn++;
- in2 = *pIn++;
- in3 = *pIn++;
- in4 = *pIn++;
-
- /* pack two higher 16-bit values from two 32-bit values */
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __PKHTB(in2, in1, 16);
- out2 = __PKHTB(in4, in3, 16);
-
-#else
-
- out1 = __PKHTB(in1, in2, 16);
- out2 = __PKHTB(in3, in4, 16);
-
-#endif // #ifdef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst)++ = out1;
- *__SIMD32(pDst)++ = out2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q15_t) A >> 16 */
- /* convert from q31 to q15 and then store the results in the destination buffer */
- *pDst++ = (q15_t) (*pIn++ >> 16);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q31_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
deleted file mode 100644
index 04d328d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q31_to_q7.c
- * Description: Converts the elements of the Q31 vector to Q7 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q31_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] *pSrc points to the Q31 input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize)
-{
- q31_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- q31_t in1, in2, in3, in4;
- q7_t out1, out2, out3, out4;
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q7_t) A >> 24 */
- /* convert from q31 to q7 and then store the results in the destination buffer */
- in1 = *pIn++;
- in2 = *pIn++;
- in3 = *pIn++;
- in4 = *pIn++;
-
- out1 = (q7_t) (in1 >> 24);
- out2 = (q7_t) (in2 >> 24);
- out3 = (q7_t) (in3 >> 24);
- out4 = (q7_t) (in4 >> 24);
-
- *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q7_t) A >> 24 */
- /* convert from q31 to q7 and then store the results in the destination buffer */
- *pDst++ = (q7_t) (*pIn++ >> 24);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q31_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
deleted file mode 100644
index 9238ba2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q7_to_float.c
- * Description: Converts the elements of the Q7 vector to floating-point vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @defgroup q7_to_x Convert 8-bit Integer value
- */
-
-/**
- * @addtogroup q7_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] *pSrc points to the Q7 input vector
- * @param[out] *pDst points to the floating-point output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize)
-{
- q7_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 128 */
- /* convert from q7 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 128.0f);
- *pDst++ = ((float32_t) * pIn++ / 128.0f);
- *pDst++ = ((float32_t) * pIn++ / 128.0f);
- *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (float32_t) A / 128 */
- /* convert from q7 to float and then store the results in the destination buffer */
- *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-}
-
-/**
- * @} end of q7_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
deleted file mode 100644
index 4651ee9..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q7_to_q15.c
- * Description: Converts the elements of the Q7 vector to Q15 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q7_to_x
- * @{
- */
-
-
-
-
-/**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] *pSrc points to the Q7 input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize)
-{
- q7_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
- q31_t in;
- q31_t in1, in2;
- q31_t out1, out2;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q15_t) A << 8 */
- /* convert from q7 to q15 and then store the results in the destination buffer */
- in = *__SIMD32(pIn)++;
-
- /* rotatate in by 8 and extend two q7_t values to q15_t values */
- in1 = __SXTB16(__ROR(in, 8));
-
- /* extend remainig two q7_t values to q15_t values */
- in2 = __SXTB16(in);
-
- in1 = in1 << 8u;
- in2 = in2 << 8u;
-
- in1 = in1 & 0xFF00FF00;
- in2 = in2 & 0xFF00FF00;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out2 = __PKHTB(in1, in2, 16);
- out1 = __PKHBT(in2, in1, 16);
-
-#else
-
- out1 = __PKHTB(in1, in2, 16);
- out2 = __PKHBT(in2, in1, 16);
-
-#endif
-
- *__SIMD32(pDst)++ = out1;
- *__SIMD32(pDst)++ = out2;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q15_t) A << 8 */
- /* convert from q7 to q15 and then store the results in the destination buffer */
- *pDst++ = (q15_t) * pIn++ << 8;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q7_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
deleted file mode 100644
index 6fafc8f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_q7_to_q31.c
- * Description: Converts the elements of the Q7 vector to Q31 vector
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupSupport
- */
-
-/**
- * @addtogroup q7_to_x
- * @{
- */
-
-/**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] *pSrc points to the Q7 input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- *
- * \par Description:
- *
- * The equation used for the conversion process is:
- *
- *
- * pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
- *
- *
- */
-
-
-void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize)
-{
- q7_t *pIn = pSrc; /* Src pointer */
- uint32_t blkCnt; /* loop counter */
-
-#if defined (ARM_MATH_DSP)
-
- q31_t in;
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /*loop Unrolling */
- blkCnt = blockSize >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- while (blkCnt > 0u)
- {
- /* C = (q31_t) A << 24 */
- /* convert from q7 to q31 and then store the results in the destination buffer */
- in = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *pDst++ = (__ROR(in, 8)) & 0xFF000000;
- *pDst++ = (__ROR(in, 16)) & 0xFF000000;
- *pDst++ = (__ROR(in, 24)) & 0xFF000000;
- *pDst++ = (in & 0xFF000000);
-
-#else
-
- *pDst++ = (in & 0xFF000000);
- *pDst++ = (__ROR(in, 24)) & 0xFF000000;
- *pDst++ = (__ROR(in, 16)) & 0xFF000000;
- *pDst++ = (__ROR(in, 8)) & 0xFF000000;
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- blkCnt = blockSize % 0x4u;
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Loop over blockSize number of values */
- blkCnt = blockSize;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
- while (blkCnt > 0u)
- {
- /* C = (q31_t) A << 24 */
- /* convert from q7 to q31 and then store the results in the destination buffer */
- *pDst++ = (q31_t) * pIn++ << 24;
-
- /* Decrement the loop counter */
- blkCnt--;
- }
-
-}
-
-/**
- * @} end of q7_to_x group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c
deleted file mode 100644
index 206e409..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_bitreversal.c
- * Description: Bitreversal functions
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/*
-* @brief In-place bit reversal function.
-* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
-* @param[in] fftSize length of the FFT.
-* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
-* @param[in] *pBitRevTab points to the bit reversal table.
-* @return none.
-*/
-
-void arm_bitreversal_f32(
-float32_t * pSrc,
-uint16_t fftSize,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab)
-{
- uint16_t fftLenBy2, fftLenBy2p1;
- uint16_t i, j;
- float32_t in;
-
- /* Initializations */
- j = 0u;
- fftLenBy2 = fftSize >> 1u;
- fftLenBy2p1 = (fftSize >> 1u) + 1u;
-
- /* Bit Reversal Implementation */
- for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
- {
- if (i < j)
- {
- /* pSrc[i] <-> pSrc[j]; */
- in = pSrc[2u * i];
- pSrc[2u * i] = pSrc[2u * j];
- pSrc[2u * j] = in;
-
- /* pSrc[i+1u] <-> pSrc[j+1u] */
- in = pSrc[(2u * i) + 1u];
- pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
- pSrc[(2u * j) + 1u] = in;
-
- /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
- in = pSrc[2u * (i + fftLenBy2p1)];
- pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
- pSrc[2u * (j + fftLenBy2p1)] = in;
-
- /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
- in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
- pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
- pSrc[(2u * (j + fftLenBy2p1)) + 1u];
- pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
- }
-
- /* pSrc[i+1u] <-> pSrc[j+1u] */
- in = pSrc[2u * (i + 1u)];
- pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
- pSrc[2u * (j + fftLenBy2)] = in;
-
- /* pSrc[i+2u] <-> pSrc[j+2u] */
- in = pSrc[(2u * (i + 1u)) + 1u];
- pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
- pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
- /* Reading the index for the bit reversal */
- j = *pBitRevTab;
-
- /* Updating the bit reversal index depending on the fft length */
- pBitRevTab += bitRevFactor;
- }
-}
-
-
-
-/*
-* @brief In-place bit reversal function.
-* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
-* @param[in] fftLen length of the FFT.
-* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-* @param[in] *pBitRevTab points to bit reversal table.
-* @return none.
-*/
-
-void arm_bitreversal_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTable)
-{
- uint32_t fftLenBy2, fftLenBy2p1, i, j;
- q31_t in;
-
- /* Initializations */
- j = 0u;
- fftLenBy2 = fftLen / 2u;
- fftLenBy2p1 = (fftLen / 2u) + 1u;
-
- /* Bit Reversal Implementation */
- for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
- {
- if (i < j)
- {
- /* pSrc[i] <-> pSrc[j]; */
- in = pSrc[2u * i];
- pSrc[2u * i] = pSrc[2u * j];
- pSrc[2u * j] = in;
-
- /* pSrc[i+1u] <-> pSrc[j+1u] */
- in = pSrc[(2u * i) + 1u];
- pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
- pSrc[(2u * j) + 1u] = in;
-
- /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
- in = pSrc[2u * (i + fftLenBy2p1)];
- pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
- pSrc[2u * (j + fftLenBy2p1)] = in;
-
- /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
- in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
- pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
- pSrc[(2u * (j + fftLenBy2p1)) + 1u];
- pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
- }
-
- /* pSrc[i+1u] <-> pSrc[j+1u] */
- in = pSrc[2u * (i + 1u)];
- pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
- pSrc[2u * (j + fftLenBy2)] = in;
-
- /* pSrc[i+2u] <-> pSrc[j+2u] */
- in = pSrc[(2u * (i + 1u)) + 1u];
- pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
- pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
- /* Reading the index for the bit reversal */
- j = *pBitRevTable;
-
- /* Updating the bit reversal index depending on the fft length */
- pBitRevTable += bitRevFactor;
- }
-}
-
-
-
-/*
- * @brief In-place bit reversal function.
- * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
- * @param[in] *pBitRevTab points to bit reversal table.
- * @return none.
-*/
-
-void arm_bitreversal_q15(
-q15_t * pSrc16,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab)
-{
- q31_t *pSrc = (q31_t *) pSrc16;
- q31_t in;
- uint32_t fftLenBy2, fftLenBy2p1;
- uint32_t i, j;
-
- /* Initializations */
- j = 0u;
- fftLenBy2 = fftLen / 2u;
- fftLenBy2p1 = (fftLen / 2u) + 1u;
-
- /* Bit Reversal Implementation */
- for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
- {
- if (i < j)
- {
- /* pSrc[i] <-> pSrc[j]; */
- /* pSrc[i+1u] <-> pSrc[j+1u] */
- in = pSrc[i];
- pSrc[i] = pSrc[j];
- pSrc[j] = in;
-
- /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */
- /* pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
- in = pSrc[i + fftLenBy2p1];
- pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
- pSrc[j + fftLenBy2p1] = in;
- }
-
- /* pSrc[i+1u] <-> pSrc[j+fftLenBy2]; */
- /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1u] */
- in = pSrc[i + 1u];
- pSrc[i + 1u] = pSrc[j + fftLenBy2];
- pSrc[j + fftLenBy2] = in;
-
- /* Reading the index for the bit reversal */
- j = *pBitRevTab;
-
- /* Updating the bit reversal index depending on the fft length */
- pBitRevTab += bitRevFactor;
- }
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
deleted file mode 100644
index f16b473..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_f32.c
- * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-extern void arm_radix8_butterfly_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- const float32_t * pCoef,
- uint16_t twidCoefModifier);
-
-extern void arm_bitreversal_32(
- uint32_t * pSrc,
- const uint16_t bitRevLen,
- const uint16_t * pBitRevTable);
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
-* @defgroup ComplexFFT Complex FFT Functions
-*
-* \par
-* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
-* Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster
-* than the DFT, especially for long lengths.
-* The algorithms described in this section
-* operate on complex data. A separate set of functions is devoted to handling
-* of real sequences.
-* \par
-* There are separate algorithms for handling floating-point, Q15, and Q31 data
-* types. The algorithms available for each data type are described next.
-* \par
-* The FFT functions operate in-place. That is, the array holding the input data
-* will also be used to hold the corresponding result. The input data is complex
-* and contains 2*fftLen interleaved values as shown below.
-* {real[0], imag[0], real[1], imag[1],..}
-* The FFT result will be contained in the same array and the frequency domain
-* values will have the same interleaving.
-*
-* \par Floating-point
-* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8
-* stages are performed along with a single radix-2 or radix-4 stage, as needed.
-* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
-* a different twiddle factor table.
-* \par
-* The function uses the standard FFT definition and output values may grow by a
-* factor of fftLen when computing the forward transform. The
-* inverse transform includes a scale of 1/fftLen as part of the
-* calculation and this matches the textbook definition of the inverse FFT.
-* \par
-* Pre-initialized data structures containing twiddle factors and bit reversal
-* tables are provided and defined in arm_const_structs.h. Include
-* this header in your function and then pass one of the constant structures as
-* an argument to arm_cfft_f32. For example:
-* \par
-* arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)
-* \par
-* computes a 64-point inverse complex FFT including bit reversal.
-* The data structures are treated as constant data and not modified during the
-* calculation. The same data structure can be reused for multiple transforms
-* including mixing forward and inverse transforms.
-* \par
-* Earlier releases of the library provided separate radix-2 and radix-4
-* algorithms that operated on floating-point data. These functions are still
-* provided but are deprecated. The older functions are slower and less general
-* than the new functions.
-* \par
-* An example of initialization of the constants for the arm_cfft_f32 function follows:
-* \code
-* const static arm_cfft_instance_f32 *S;
-* ...
-* switch (length) {
-* case 16:
-* S = &arm_cfft_sR_f32_len16;
-* break;
-* case 32:
-* S = &arm_cfft_sR_f32_len32;
-* break;
-* case 64:
-* S = &arm_cfft_sR_f32_len64;
-* break;
-* case 128:
-* S = &arm_cfft_sR_f32_len128;
-* break;
-* case 256:
-* S = &arm_cfft_sR_f32_len256;
-* break;
-* case 512:
-* S = &arm_cfft_sR_f32_len512;
-* break;
-* case 1024:
-* S = &arm_cfft_sR_f32_len1024;
-* break;
-* case 2048:
-* S = &arm_cfft_sR_f32_len2048;
-* break;
-* case 4096:
-* S = &arm_cfft_sR_f32_len4096;
-* break;
-* }
-* \endcode
-* \par Q15 and Q31
-* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4
-* stages are performed along with a single radix-2 stage, as needed.
-* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
-* a different twiddle factor table.
-* \par
-* The function uses the standard FFT definition and output values may grow by a
-* factor of fftLen when computing the forward transform. The
-* inverse transform includes a scale of 1/fftLen as part of the
-* calculation and this matches the textbook definition of the inverse FFT.
-* \par
-* Pre-initialized data structures containing twiddle factors and bit reversal
-* tables are provided and defined in arm_const_structs.h. Include
-* this header in your function and then pass one of the constant structures as
-* an argument to arm_cfft_q31. For example:
-* \par
-* arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)
-* \par
-* computes a 64-point inverse complex FFT including bit reversal.
-* The data structures are treated as constant data and not modified during the
-* calculation. The same data structure can be reused for multiple transforms
-* including mixing forward and inverse transforms.
-* \par
-* Earlier releases of the library provided separate radix-2 and radix-4
-* algorithms that operated on floating-point data. These functions are still
-* provided but are deprecated. The older functions are slower and less general
-* than the new functions.
-* \par
-* An example of initialization of the constants for the arm_cfft_q31 function follows:
-* \code
-* const static arm_cfft_instance_q31 *S;
-* ...
-* switch (length) {
-* case 16:
-* S = &arm_cfft_sR_q31_len16;
-* break;
-* case 32:
-* S = &arm_cfft_sR_q31_len32;
-* break;
-* case 64:
-* S = &arm_cfft_sR_q31_len64;
-* break;
-* case 128:
-* S = &arm_cfft_sR_q31_len128;
-* break;
-* case 256:
-* S = &arm_cfft_sR_q31_len256;
-* break;
-* case 512:
-* S = &arm_cfft_sR_q31_len512;
-* break;
-* case 1024:
-* S = &arm_cfft_sR_q31_len1024;
-* break;
-* case 2048:
-* S = &arm_cfft_sR_q31_len2048;
-* break;
-* case 4096:
-* S = &arm_cfft_sR_q31_len4096;
-* break;
-* }
-* \endcode
-*
-*/
-
-void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1)
-{
- uint32_t L = S->fftLen;
- float32_t * pCol1, * pCol2, * pMid1, * pMid2;
- float32_t * p2 = p1 + L;
- const float32_t * tw = (float32_t *) S->pTwiddle;
- float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
- float32_t m0, m1, m2, m3;
- uint32_t l;
-
- pCol1 = p1;
- pCol2 = p2;
-
- // Define new length
- L >>= 1;
- // Initialize mid pointers
- pMid1 = p1 + L;
- pMid2 = p2 + L;
-
- // do two dot Fourier transform
- for ( l = L >> 2; l > 0; l-- )
- {
- t1[0] = p1[0];
- t1[1] = p1[1];
- t1[2] = p1[2];
- t1[3] = p1[3];
-
- t2[0] = p2[0];
- t2[1] = p2[1];
- t2[2] = p2[2];
- t2[3] = p2[3];
-
- t3[0] = pMid1[0];
- t3[1] = pMid1[1];
- t3[2] = pMid1[2];
- t3[3] = pMid1[3];
-
- t4[0] = pMid2[0];
- t4[1] = pMid2[1];
- t4[2] = pMid2[2];
- t4[3] = pMid2[3];
-
- *p1++ = t1[0] + t2[0];
- *p1++ = t1[1] + t2[1];
- *p1++ = t1[2] + t2[2];
- *p1++ = t1[3] + t2[3]; // col 1
-
- t2[0] = t1[0] - t2[0];
- t2[1] = t1[1] - t2[1];
- t2[2] = t1[2] - t2[2];
- t2[3] = t1[3] - t2[3]; // for col 2
-
- *pMid1++ = t3[0] + t4[0];
- *pMid1++ = t3[1] + t4[1];
- *pMid1++ = t3[2] + t4[2];
- *pMid1++ = t3[3] + t4[3]; // col 1
-
- t4[0] = t4[0] - t3[0];
- t4[1] = t4[1] - t3[1];
- t4[2] = t4[2] - t3[2];
- t4[3] = t4[3] - t3[3]; // for col 2
-
- twR = *tw++;
- twI = *tw++;
-
- // multiply by twiddle factors
- m0 = t2[0] * twR;
- m1 = t2[1] * twI;
- m2 = t2[1] * twR;
- m3 = t2[0] * twI;
-
- // R = R * Tr - I * Ti
- *p2++ = m0 + m1;
- // I = I * Tr + R * Ti
- *p2++ = m2 - m3;
-
- // use vertical symmetry
- // 0.9988 - 0.0491i <==> -0.0491 - 0.9988i
- m0 = t4[0] * twI;
- m1 = t4[1] * twR;
- m2 = t4[1] * twI;
- m3 = t4[0] * twR;
-
- *pMid2++ = m0 - m1;
- *pMid2++ = m2 + m3;
-
- twR = *tw++;
- twI = *tw++;
-
- m0 = t2[2] * twR;
- m1 = t2[3] * twI;
- m2 = t2[3] * twR;
- m3 = t2[2] * twI;
-
- *p2++ = m0 + m1;
- *p2++ = m2 - m3;
-
- m0 = t4[2] * twI;
- m1 = t4[3] * twR;
- m2 = t4[3] * twI;
- m3 = t4[2] * twR;
-
- *pMid2++ = m0 - m1;
- *pMid2++ = m2 + m3;
- }
-
- // first col
- arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
- // second col
- arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
-}
-
-void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1)
-{
- uint32_t L = S->fftLen >> 1;
- float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
- const float32_t *tw2, *tw3, *tw4;
- float32_t * p2 = p1 + L;
- float32_t * p3 = p2 + L;
- float32_t * p4 = p3 + L;
- float32_t t2[4], t3[4], t4[4], twR, twI;
- float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
- float32_t m0, m1, m2, m3;
- uint32_t l, twMod2, twMod3, twMod4;
-
- pCol1 = p1; // points to real values by default
- pCol2 = p2;
- pCol3 = p3;
- pCol4 = p4;
- pEnd1 = p2 - 1; // points to imaginary values by default
- pEnd2 = p3 - 1;
- pEnd3 = p4 - 1;
- pEnd4 = pEnd3 + L;
-
- tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
-
- L >>= 1;
-
- // do four dot Fourier transform
-
- twMod2 = 2;
- twMod3 = 4;
- twMod4 = 6;
-
- // TOP
- p1ap3_0 = p1[0] + p3[0];
- p1sp3_0 = p1[0] - p3[0];
- p1ap3_1 = p1[1] + p3[1];
- p1sp3_1 = p1[1] - p3[1];
-
- // col 2
- t2[0] = p1sp3_0 + p2[1] - p4[1];
- t2[1] = p1sp3_1 - p2[0] + p4[0];
- // col 3
- t3[0] = p1ap3_0 - p2[0] - p4[0];
- t3[1] = p1ap3_1 - p2[1] - p4[1];
- // col 4
- t4[0] = p1sp3_0 - p2[1] + p4[1];
- t4[1] = p1sp3_1 + p2[0] - p4[0];
- // col 1
- *p1++ = p1ap3_0 + p2[0] + p4[0];
- *p1++ = p1ap3_1 + p2[1] + p4[1];
-
- // Twiddle factors are ones
- *p2++ = t2[0];
- *p2++ = t2[1];
- *p3++ = t3[0];
- *p3++ = t3[1];
- *p4++ = t4[0];
- *p4++ = t4[1];
-
- tw2 += twMod2;
- tw3 += twMod3;
- tw4 += twMod4;
-
- for (l = (L - 2) >> 1; l > 0; l-- )
- {
- // TOP
- p1ap3_0 = p1[0] + p3[0];
- p1sp3_0 = p1[0] - p3[0];
- p1ap3_1 = p1[1] + p3[1];
- p1sp3_1 = p1[1] - p3[1];
- // col 2
- t2[0] = p1sp3_0 + p2[1] - p4[1];
- t2[1] = p1sp3_1 - p2[0] + p4[0];
- // col 3
- t3[0] = p1ap3_0 - p2[0] - p4[0];
- t3[1] = p1ap3_1 - p2[1] - p4[1];
- // col 4
- t4[0] = p1sp3_0 - p2[1] + p4[1];
- t4[1] = p1sp3_1 + p2[0] - p4[0];
- // col 1 - top
- *p1++ = p1ap3_0 + p2[0] + p4[0];
- *p1++ = p1ap3_1 + p2[1] + p4[1];
-
- // BOTTOM
- p1ap3_1 = pEnd1[-1] + pEnd3[-1];
- p1sp3_1 = pEnd1[-1] - pEnd3[-1];
- p1ap3_0 = pEnd1[0] + pEnd3[0];
- p1sp3_0 = pEnd1[0] - pEnd3[0];
- // col 2
- t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1;
- t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
- // col 3
- t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
- t3[3] = p1ap3_0 - pEnd2[0] - pEnd4[0];
- // col 4
- t4[2] = pEnd2[0] - pEnd4[0] - p1sp3_1;
- t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
- // col 1 - Bottom
- *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
- *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
-
- // COL 2
- // read twiddle factors
- twR = *tw2++;
- twI = *tw2++;
- // multiply by twiddle factors
- // let Z1 = a + i(b), Z2 = c + i(d)
- // => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d)
-
- // Top
- m0 = t2[0] * twR;
- m1 = t2[1] * twI;
- m2 = t2[1] * twR;
- m3 = t2[0] * twI;
-
- *p2++ = m0 + m1;
- *p2++ = m2 - m3;
- // use vertical symmetry col 2
- // 0.9997 - 0.0245i <==> 0.0245 - 0.9997i
- // Bottom
- m0 = t2[3] * twI;
- m1 = t2[2] * twR;
- m2 = t2[2] * twI;
- m3 = t2[3] * twR;
-
- *pEnd2-- = m0 - m1;
- *pEnd2-- = m2 + m3;
-
- // COL 3
- twR = tw3[0];
- twI = tw3[1];
- tw3 += twMod3;
- // Top
- m0 = t3[0] * twR;
- m1 = t3[1] * twI;
- m2 = t3[1] * twR;
- m3 = t3[0] * twI;
-
- *p3++ = m0 + m1;
- *p3++ = m2 - m3;
- // use vertical symmetry col 3
- // 0.9988 - 0.0491i <==> -0.9988 - 0.0491i
- // Bottom
- m0 = -t3[3] * twR;
- m1 = t3[2] * twI;
- m2 = t3[2] * twR;
- m3 = t3[3] * twI;
-
- *pEnd3-- = m0 - m1;
- *pEnd3-- = m3 - m2;
-
- // COL 4
- twR = tw4[0];
- twI = tw4[1];
- tw4 += twMod4;
- // Top
- m0 = t4[0] * twR;
- m1 = t4[1] * twI;
- m2 = t4[1] * twR;
- m3 = t4[0] * twI;
-
- *p4++ = m0 + m1;
- *p4++ = m2 - m3;
- // use vertical symmetry col 4
- // 0.9973 - 0.0736i <==> -0.0736 + 0.9973i
- // Bottom
- m0 = t4[3] * twI;
- m1 = t4[2] * twR;
- m2 = t4[2] * twI;
- m3 = t4[3] * twR;
-
- *pEnd4-- = m0 - m1;
- *pEnd4-- = m2 + m3;
- }
-
- //MIDDLE
- // Twiddle factors are
- // 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i
- p1ap3_0 = p1[0] + p3[0];
- p1sp3_0 = p1[0] - p3[0];
- p1ap3_1 = p1[1] + p3[1];
- p1sp3_1 = p1[1] - p3[1];
-
- // col 2
- t2[0] = p1sp3_0 + p2[1] - p4[1];
- t2[1] = p1sp3_1 - p2[0] + p4[0];
- // col 3
- t3[0] = p1ap3_0 - p2[0] - p4[0];
- t3[1] = p1ap3_1 - p2[1] - p4[1];
- // col 4
- t4[0] = p1sp3_0 - p2[1] + p4[1];
- t4[1] = p1sp3_1 + p2[0] - p4[0];
- // col 1 - Top
- *p1++ = p1ap3_0 + p2[0] + p4[0];
- *p1++ = p1ap3_1 + p2[1] + p4[1];
-
- // COL 2
- twR = tw2[0];
- twI = tw2[1];
-
- m0 = t2[0] * twR;
- m1 = t2[1] * twI;
- m2 = t2[1] * twR;
- m3 = t2[0] * twI;
-
- *p2++ = m0 + m1;
- *p2++ = m2 - m3;
- // COL 3
- twR = tw3[0];
- twI = tw3[1];
-
- m0 = t3[0] * twR;
- m1 = t3[1] * twI;
- m2 = t3[1] * twR;
- m3 = t3[0] * twI;
-
- *p3++ = m0 + m1;
- *p3++ = m2 - m3;
- // COL 4
- twR = tw4[0];
- twI = tw4[1];
-
- m0 = t4[0] * twR;
- m1 = t4[1] * twI;
- m2 = t4[1] * twR;
- m3 = t4[0] * twI;
-
- *p4++ = m0 + m1;
- *p4++ = m2 - m3;
-
- // first col
- arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
- // second col
- arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
- // third col
- arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
- // fourth col
- arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
-}
-
-/**
-* @addtogroup ComplexFFT
-* @{
-*/
-
-/**
-* @details
-* @brief Processing function for the floating-point complex FFT.
-* @param[in] *S points to an instance of the floating-point CFFT structure.
-* @param[in, out] *p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return none.
-*/
-
-void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- uint32_t L = S->fftLen, l;
- float32_t invL, * pSrc;
-
- if (ifftFlag == 1u)
- {
- /* Conjugate input data */
- pSrc = p1 + 1;
- for(l=0; lpTwiddle, 1);
- break;
- }
-
- if ( bitReverseFlag )
- arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
-
- if (ifftFlag == 1u)
- {
- invL = 1.0f/(float32_t)L;
- /* Conjugate and scale output data */
- pSrc = p1;
- for(l=0; l2*fftLen. Processing occurs in-place.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return none.
-*/
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- uint32_t L = S->fftLen;
-
- if (ifftFlag == 1u)
- {
- switch (L)
- {
- case 16:
- case 64:
- case 256:
- case 1024:
- case 4096:
- arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
- break;
-
- case 32:
- case 128:
- case 512:
- case 2048:
- arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle );
- break;
- }
- }
- else
- {
- switch (L)
- {
- case 16:
- case 64:
- case 256:
- case 1024:
- case 4096:
- arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
- break;
-
- case 32:
- case 128:
- case 512:
- case 2048:
- arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle );
- break;
- }
- }
-
- if ( bitReverseFlag )
- arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);
-}
-
-/**
-* @} end of ComplexFFT group
-*/
-
-void arm_cfft_radix4by2_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- const q15_t * pCoef)
-{
- uint32_t i;
- uint32_t n2;
- q15_t p0, p1, p2, p3;
-#if defined (ARM_MATH_DSP)
- q31_t T, S, R;
- q31_t coeff, out1, out2;
- const q15_t *pC = pCoef;
- q15_t *pSi = pSrc;
- q15_t *pSl = pSrc + fftLen;
-#else
- uint32_t ia, l;
- q15_t xt, yt, cosVal, sinVal;
-#endif
-
- n2 = fftLen >> 1;
-
-#if defined (ARM_MATH_DSP)
-
- for (i = n2; i > 0; i--)
- {
- coeff = _SIMD32_OFFSET(pC);
- pC += 2;
-
- T = _SIMD32_OFFSET(pSi);
- T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
-
- S = _SIMD32_OFFSET(pSl);
- S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
- pSi += 2;
-
- #ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(coeff, R) >> 16;
- out2 = __SMUSDX(coeff, R);
-
- #else
-
- out1 = __SMUSDX(R, coeff) >> 16u;
- out2 = __SMUAD(coeff, R);
-
- #endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSl) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSl += 2;
- }
-
-#else // #if defined (ARM_MATH_DSP)
-
- ia = 0;
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia++;
-
- l = i + n2;
-
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
- }
-
-#endif // #if defined (ARM_MATH_DSP)
-
- // first col
- arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2u);
- // second col
- arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
-
- for (i = 0; i < fftLen >> 1; i++)
- {
- p0 = pSrc[4*i+0];
- p1 = pSrc[4*i+1];
- p2 = pSrc[4*i+2];
- p3 = pSrc[4*i+3];
-
- p0 <<= 1;
- p1 <<= 1;
- p2 <<= 1;
- p3 <<= 1;
-
- pSrc[4*i+0] = p0;
- pSrc[4*i+1] = p1;
- pSrc[4*i+2] = p2;
- pSrc[4*i+3] = p3;
- }
-}
-
-void arm_cfft_radix4by2_inverse_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- const q15_t * pCoef)
-{
- uint32_t i;
- uint32_t n2;
- q15_t p0, p1, p2, p3;
-#if defined (ARM_MATH_DSP)
- q31_t T, S, R;
- q31_t coeff, out1, out2;
- const q15_t *pC = pCoef;
- q15_t *pSi = pSrc;
- q15_t *pSl = pSrc + fftLen;
-#else
- uint32_t ia, l;
- q15_t xt, yt, cosVal, sinVal;
-#endif
-
- n2 = fftLen >> 1;
-
-#if defined (ARM_MATH_DSP)
-
- for (i = n2; i > 0; i--)
- {
- coeff = _SIMD32_OFFSET(pC);
- pC += 2;
-
- T = _SIMD32_OFFSET(pSi);
- T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
-
- S = _SIMD32_OFFSET(pSl);
- S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
- pSi += 2;
-
- #ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(coeff, R) >> 16;
- out2 = __SMUADX(coeff, R);
- #else
-
- out1 = __SMUADX(R, coeff) >> 16u;
- out2 = __SMUSD(__QSUB(0, coeff), R);
-
- #endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSl) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSl += 2;
- }
-
-#else // #if defined (ARM_MATH_DSP)
-
- ia = 0;
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia++;
-
- l = i + n2;
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
- }
-
-#endif // #if defined (ARM_MATH_DSP)
-
- // first col
- arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2u);
- // second col
- arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
-
- for (i = 0; i < fftLen >> 1; i++)
- {
- p0 = pSrc[4*i+0];
- p1 = pSrc[4*i+1];
- p2 = pSrc[4*i+2];
- p3 = pSrc[4*i+3];
-
- p0 <<= 1;
- p1 <<= 1;
- p2 <<= 1;
- p3 <<= 1;
-
- pSrc[4*i+0] = p0;
- pSrc[4*i+1] = p1;
- pSrc[4*i+2] = p2;
- pSrc[4*i+3] = p3;
- }
-}
-
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c
deleted file mode 100644
index 6c1f070..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_q31.c
- * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-extern void arm_radix4_butterfly_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier);
-
-extern void arm_radix4_butterfly_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier);
-
-extern void arm_bitreversal_32(
- uint32_t * pSrc,
- const uint16_t bitRevLen,
- const uint16_t * pBitRevTable);
-
-void arm_cfft_radix4by2_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- const q31_t * pCoef);
-
-void arm_cfft_radix4by2_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- const q31_t * pCoef);
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
-* @addtogroup ComplexFFT
-* @{
-*/
-
-/**
-* @details
-* @brief Processing function for the fixed-point complex FFT in Q31 format.
-* @param[in] *S points to an instance of the fixed-point CFFT structure.
-* @param[in, out] *p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return none.
-*/
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- uint32_t L = S->fftLen;
-
- if (ifftFlag == 1u)
- {
- switch (L)
- {
- case 16:
- case 64:
- case 256:
- case 1024:
- case 4096:
- arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 );
- break;
-
- case 32:
- case 128:
- case 512:
- case 2048:
- arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle );
- break;
- }
- }
- else
- {
- switch (L)
- {
- case 16:
- case 64:
- case 256:
- case 1024:
- case 4096:
- arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 );
- break;
-
- case 32:
- case 128:
- case 512:
- case 2048:
- arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle );
- break;
- }
- }
-
- if ( bitReverseFlag )
- arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
-}
-
-/**
-* @} end of ComplexFFT group
-*/
-
-void arm_cfft_radix4by2_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- const q31_t * pCoef)
-{
- uint32_t i, l;
- uint32_t n2, ia;
- q31_t xt, yt, cosVal, sinVal;
- q31_t p0, p1;
-
- n2 = fftLen >> 1;
- ia = 0;
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[2*ia];
- sinVal = pCoef[2*ia + 1];
- ia++;
-
- l = i + n2;
- xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
- pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
-
- yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multAcc_32x32_keep32_R(p0, yt, sinVal);
- multSub_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0 << 1;
- pSrc[2u * l + 1u] = p1 << 1;
-
- }
-
- // first col
- arm_radix4_butterfly_q31( pSrc, n2, (q31_t*)pCoef, 2u);
- // second col
- arm_radix4_butterfly_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
-
- for (i = 0; i < fftLen >> 1; i++)
- {
- p0 = pSrc[4*i+0];
- p1 = pSrc[4*i+1];
- xt = pSrc[4*i+2];
- yt = pSrc[4*i+3];
-
- p0 <<= 1;
- p1 <<= 1;
- xt <<= 1;
- yt <<= 1;
-
- pSrc[4*i+0] = p0;
- pSrc[4*i+1] = p1;
- pSrc[4*i+2] = xt;
- pSrc[4*i+3] = yt;
- }
-
-}
-
-void arm_cfft_radix4by2_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- const q31_t * pCoef)
-{
- uint32_t i, l;
- uint32_t n2, ia;
- q31_t xt, yt, cosVal, sinVal;
- q31_t p0, p1;
-
- n2 = fftLen >> 1;
- ia = 0;
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[2*ia];
- sinVal = pCoef[2*ia + 1];
- ia++;
-
- l = i + n2;
- xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
- pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
-
- yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multSub_32x32_keep32_R(p0, yt, sinVal);
- multAcc_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0 << 1;
- pSrc[2u * l + 1u] = p1 << 1;
-
- }
-
- // first col
- arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2u);
- // second col
- arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
-
- for (i = 0; i < fftLen >> 1; i++)
- {
- p0 = pSrc[4*i+0];
- p1 = pSrc[4*i+1];
- xt = pSrc[4*i+2];
- yt = pSrc[4*i+3];
-
- p0 <<= 1;
- p1 <<= 1;
- xt <<= 1;
- yt <<= 1;
-
- pSrc[4*i+0] = p0;
- pSrc[4*i+1] = p1;
- pSrc[4*i+2] = xt;
- pSrc[4*i+3] = yt;
- }
-}
-
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
deleted file mode 100644
index d880deb..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
+++ /dev/null
@@ -1,472 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_f32.c
- * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier,
- float32_t onebyfftLen);
-
-extern void arm_bitreversal_f32(
- float32_t * pSrc,
- uint16_t fftSize,
- uint16_t bitRevFactor,
- uint16_t * pBitRevTab);
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
-* @addtogroup ComplexFFT
-* @{
-*/
-
-/**
-* @details
-* @brief Radix-2 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in] *S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
-* @return none.
-*/
-
-void arm_cfft_radix2_f32(
-const arm_cfft_radix2_instance_f32 * S,
-float32_t * pSrc)
-{
-
- if (S->ifftFlag == 1u)
- {
- /* Complex IFFT radix-2 */
- arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
- S->twidCoefModifier, S->onebyfftLen);
- }
- else
- {
- /* Complex FFT radix-2 */
- arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
- S->twidCoefModifier);
- }
-
- if (S->bitReverseFlag == 1u)
- {
- /* Bit Reversal */
- arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
- }
-
-}
-
-
-/**
-* @} end of ComplexFFT group
-*/
-
-
-
-/* ----------------------------------------------------------------------
-** Internal helper function used by the FFTs
-** ------------------------------------------------------------------- */
-
-/*
-* @brief Core function for the floating-point CFFT butterfly process.
-* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
-* @param[in] fftLen length of the FFT.
-* @param[in] *pCoef points to the twiddle coefficient buffer.
-* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-*/
-
-void arm_radix2_butterfly_f32(
-float32_t * pSrc,
-uint32_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
- uint32_t i, j, k, l;
- uint32_t n1, n2, ia;
- float32_t xt, yt, cosVal, sinVal;
- float32_t p0, p1, p2, p3;
- float32_t a0, a1;
-
-#if defined (ARM_MATH_DSP)
-
- /* Initializations for the first stage */
- n2 = fftLen >> 1;
- ia = 0;
- i = 0;
-
- // loop for groups
- for (k = n2; k > 0; k--)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
-
- /* Twiddle coefficients index modifier */
- ia += twidCoefModifier;
-
- /* index calculation for the input as, */
- /* pSrc[i + 0], pSrc[i + fftLen/1] */
- l = i + n2;
-
- /* Butterfly implementation */
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 + p1;
- pSrc[2 * l + 1] = p2 - p3;
-
- i++;
- } // groups loop end
-
- twidCoefModifier <<= 1u;
-
- // loop for stage
- for (k = n2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- j = 0;
- do
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia += twidCoefModifier;
-
- // loop for butterfly
- i = j;
- do
- {
- l = i + n2;
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 + p1;
- pSrc[2 * l + 1] = p2 - p3;
-
- i += n1;
- } while ( i < fftLen ); // butterfly loop end
- j++;
- } while ( j < n2); // groups loop end
- twidCoefModifier <<= 1u;
- } // stages loop end
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += 2)
- {
- a0 = pSrc[2 * i] + pSrc[2 * i + 2];
- xt = pSrc[2 * i] - pSrc[2 * i + 2];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
- a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
- pSrc[2 * i + 2] = xt;
- pSrc[2 * i + 3] = yt;
- } // groups loop end
-
-#else
-
- n2 = fftLen;
-
- // loop for stage
- for (k = fftLen; k > 1; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- j = 0;
- do
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia += twidCoefModifier;
-
- // loop for butterfly
- i = j;
- do
- {
- l = i + n2;
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 + p1;
- pSrc[2 * l + 1] = p2 - p3;
-
- i += n1;
- } while (i < fftLen);
- j++;
- } while (j < n2);
- twidCoefModifier <<= 1u;
- }
-
-#endif // #if defined (ARM_MATH_DSP)
-
-}
-
-
-void arm_radix2_butterfly_inverse_f32(
-float32_t * pSrc,
-uint32_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier,
-float32_t onebyfftLen)
-{
-
- uint32_t i, j, k, l;
- uint32_t n1, n2, ia;
- float32_t xt, yt, cosVal, sinVal;
- float32_t p0, p1, p2, p3;
- float32_t a0, a1;
-
-#if defined (ARM_MATH_DSP)
-
- n2 = fftLen >> 1;
- ia = 0;
-
- // loop for groups
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia += twidCoefModifier;
-
- l = i + n2;
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 - p1;
- pSrc[2 * l + 1] = p2 + p3;
- } // groups loop end
-
- twidCoefModifier <<= 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- j = 0;
- do
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia += twidCoefModifier;
-
- // loop for butterfly
- i = j;
- do
- {
- l = i + n2;
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 - p1;
- pSrc[2 * l + 1] = p2 + p3;
-
- i += n1;
- } while ( i < fftLen ); // butterfly loop end
- j++;
- } while (j < n2); // groups loop end
-
- twidCoefModifier <<= 1u;
- } // stages loop end
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += 2)
- {
- a0 = pSrc[2 * i] + pSrc[2 * i + 2];
- xt = pSrc[2 * i] - pSrc[2 * i + 2];
-
- a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
- yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
-
- p0 = a0 * onebyfftLen;
- p2 = xt * onebyfftLen;
- p1 = a1 * onebyfftLen;
- p3 = yt * onebyfftLen;
-
- pSrc[2 * i] = p0;
- pSrc[2 * i + 1] = p1;
- pSrc[2 * i + 2] = p2;
- pSrc[2 * i + 3] = p3;
- } // butterfly loop end
-
-#else
-
- n2 = fftLen;
-
- // loop for stage
- for (k = fftLen; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- j = 0;
- do
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- i = j;
- do
- {
- l = i + n2;
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
- p0 = xt * cosVal;
- p1 = yt * sinVal;
- p2 = yt * cosVal;
- p3 = xt * sinVal;
-
- pSrc[2 * i] = a0;
- pSrc[2 * i + 1] = a1;
-
- pSrc[2 * l] = p0 - p1;
- pSrc[2 * l + 1] = p2 + p3;
-
- i += n1;
- } while ( i < fftLen ); // butterfly loop end
- j++;
- } while ( j < n2 ); // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += n1)
- {
- l = i + n2;
-
- a0 = pSrc[2 * i] + pSrc[2 * l];
- xt = pSrc[2 * i] - pSrc[2 * l];
-
- a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-
- p0 = a0 * onebyfftLen;
- p2 = xt * onebyfftLen;
- p1 = a1 * onebyfftLen;
- p3 = yt * onebyfftLen;
-
- pSrc[2 * i] = p0;
- pSrc[2u * l] = p2;
-
- pSrc[2 * i + 1] = p1;
- pSrc[2u * l + 1u] = p3;
- } // butterfly loop end
-
-#endif // #if defined (ARM_MATH_DSP)
-
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
deleted file mode 100644
index 4b965eb..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_init_f32.c
- * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
-* @brief Initialization function for the floating-point CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialise the FFT length */
- S->fftLen = fftLen;
-
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (float32_t *) twiddleCoef;
-
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
-
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (S->fftLen)
- {
-
- case 4096u:
- /* Initializations of structure parameters for 4096 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.000244140625;
- break;
-
- case 2048u:
- /* Initializations of structure parameters for 2048 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 2u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 2u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.00048828125;
- break;
-
- case 1024u:
- /* Initializations of structure parameters for 1024 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 4u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 4u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.0009765625f;
- break;
-
- case 512u:
- /* Initializations of structure parameters for 512 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 8u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 8u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.001953125;
- break;
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
- S->onebyfftLen = 0.00390625f;
- break;
-
- case 128u:
- /* Initializations of structure parameters for 128 point FFT */
- S->twidCoefModifier = 32u;
- S->bitRevFactor = 32u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
- S->onebyfftLen = 0.0078125;
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
- S->onebyfftLen = 0.015625f;
- break;
-
- case 32u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 128u;
- S->bitRevFactor = 128u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
- S->onebyfftLen = 0.03125;
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
- S->onebyfftLen = 0.0625f;
- break;
-
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
deleted file mode 100644
index 42bf40a..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_init_q15.c
- * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
-* @brief Initialization function for the Q15 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
-* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-
-arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialise the FFT length */
- S->fftLen = fftLen;
-
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (S->fftLen)
- {
- case 4096u:
- /* Initializations of structure parameters for 4096 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
-
- break;
-
- case 2048u:
- /* Initializations of structure parameters for 2048 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 2u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 2u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-
- break;
-
- case 1024u:
- /* Initializations of structure parameters for 1024 point FFT */
- S->twidCoefModifier = 4u;
- S->bitRevFactor = 4u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
- break;
-
- case 512u:
- /* Initializations of structure parameters for 512 point FFT */
- S->twidCoefModifier = 8u;
- S->bitRevFactor = 8u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-
- break;
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
- break;
-
- case 128u:
- /* Initializations of structure parameters for 128 point FFT */
- S->twidCoefModifier = 32u;
- S->bitRevFactor = 32u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
- break;
-
- case 32u:
- /* Initializations of structure parameters for 32 point FFT */
- S->twidCoefModifier = 128u;
- S->bitRevFactor = 128u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
- break;
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
deleted file mode 100644
index 6005e9c..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_init_q31.c
- * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-
-/**
-*
-* @brief Initialization function for the Q31 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-
-arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialise the FFT length */
- S->fftLen = fftLen;
-
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of Instance structure depending on the FFT length */
- switch (S->fftLen)
- {
- /* Initializations of structure parameters for 4096 point FFT */
- case 4096u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
- break;
-
- /* Initializations of structure parameters for 2048 point FFT */
- case 2048u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 2u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 2u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
- break;
-
- /* Initializations of structure parameters for 1024 point FFT */
- case 1024u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 4u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 4u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
- break;
-
- /* Initializations of structure parameters for 512 point FFT */
- case 512u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 8u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 8u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
- break;
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
- break;
-
- case 128u:
- /* Initializations of structure parameters for 128 point FFT */
- S->twidCoefModifier = 32u;
- S->bitRevFactor = 32u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
- break;
-
- case 32u:
- /* Initializations of structure parameters for 32 point FFT */
- S->twidCoefModifier = 128u;
- S->bitRevFactor = 128u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
- break;
-
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c
deleted file mode 100644
index 2e737fd..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_q15.c
- * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pCoef,
- uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pCoef,
- uint16_t twidCoefModifier);
-
-void arm_bitreversal_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t * pBitRevTab);
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
- * @details
- * @brief Processing function for the fixed-point CFFT/CIFFT.
- * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
- * @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
- * @return none.
- */
-
-void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc)
-{
-
- if (S->ifftFlag == 1u)
- {
- arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
- S->pTwiddle, S->twidCoefModifier);
- }
- else
- {
- arm_radix2_butterfly_q15(pSrc, S->fftLen,
- S->pTwiddle, S->twidCoefModifier);
- }
-
- arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**
- * @} end of ComplexFFT group
- */
-
-void arm_radix2_butterfly_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pCoef,
- uint16_t twidCoefModifier)
-{
-#if defined (ARM_MATH_DSP)
-
- unsigned i, j, k, l;
- unsigned n1, n2, ia;
- q15_t in;
- q31_t T, S, R;
- q31_t coeff, out1, out2;
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (i = 0; i < n2; i++)
- {
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
- in = ((int16_t) (T & 0xFFFF)) >> 1;
- T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
- in = ((int16_t) (S & 0xFFFF)) >> 1;
- S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(coeff, R) >> 16;
- out2 = __SMUSDX(coeff, R);
-
-#else
-
- out1 = __SMUSDX(R, coeff) >> 16u;
- out2 = __SMUAD(coeff, R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- i++;
- l++;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
- in = ((int16_t) (T & 0xFFFF)) >> 1;
- T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
- in = ((int16_t) (S & 0xFFFF)) >> 1;
- S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(coeff, R) >> 16;
- out2 = __SMUSDX(coeff, R);
-
-#else
-
- out1 = __SMUSDX(R, coeff) >> 16u;
- out2 = __SMUAD(coeff, R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(coeff, R) >> 16;
- out2 = __SMUSDX(coeff, R);
-
-#else
-
- out1 = __SMUSDX(R, coeff) >> 16u;
- out2 = __SMUAD(coeff, R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- i += n1;
-
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(coeff, R) >> 16;
- out2 = __SMUSDX(coeff, R);
-
-#else
-
- out1 = __SMUSDX(R, coeff) >> 16u;
- out2 = __SMUAD(coeff, R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += n1)
- {
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
- i += n1;
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
- } // groups loop end
-
-
-#else
-
- unsigned i, j, k, l;
- unsigned n1, n2, ia;
- q15_t xt, yt, cosVal, sinVal;
-
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
-#endif // #if defined (ARM_MATH_DSP)
-
-}
-
-
-void arm_radix2_butterfly_inverse_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pCoef,
- uint16_t twidCoefModifier)
-{
-#if defined (ARM_MATH_DSP)
-
- unsigned i, j, k, l;
- unsigned n1, n2, ia;
- q15_t in;
- q31_t T, S, R;
- q31_t coeff, out1, out2;
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (i = 0; i < n2; i++)
- {
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
- in = ((int16_t) (T & 0xFFFF)) >> 1;
- T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
- in = ((int16_t) (S & 0xFFFF)) >> 1;
- S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(coeff, R) >> 16;
- out2 = __SMUADX(coeff, R);
-#else
-
- out1 = __SMUADX(R, coeff) >> 16u;
- out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- i++;
- l++;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
- in = ((int16_t) (T & 0xFFFF)) >> 1;
- T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
- in = ((int16_t) (S & 0xFFFF)) >> 1;
- S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(coeff, R) >> 16;
- out2 = __SMUADX(coeff, R);
-#else
-
- out1 = __SMUADX(R, coeff) >> 16u;
- out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(coeff, R) >> 16;
- out2 = __SMUADX(coeff, R);
-
-#else
-
- out1 = __SMUADX(R, coeff) >> 16u;
- out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- i += n1;
-
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(coeff, R) >> 16;
- out2 = __SMUADX(coeff, R);
-#else
-
- out1 = __SMUADX(R, coeff) >> 16u;
- out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif // #ifndef ARM_MATH_BIG_ENDIAN
-
- _SIMD32_OFFSET(pSrc + (2u * l)) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
-
- T = _SIMD32_OFFSET(pSrc + (2 * i));
-
- S = _SIMD32_OFFSET(pSrc + (2 * l));
-
- R = __QSUB16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
- _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
-#else
-
-
- unsigned i, j, k, l;
- unsigned n1, n2, ia;
- q15_t xt, yt, cosVal, sinVal;
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
- pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
- ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
- pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
- ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
-
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- } // groups loop end
-
-
-#endif // #if defined (ARM_MATH_DSP)
-
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c
deleted file mode 100644
index e43dd32..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix2_q31.c
- * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint16_t twidCoefModifier);
-
-void arm_bitreversal_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t * pBitRevTab);
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
-* @addtogroup ComplexFFT
-* @{
-*/
-
-/**
-* @details
-* @brief Processing function for the fixed-point CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
-* @return none.
-*/
-
-void arm_cfft_radix2_q31(
-const arm_cfft_radix2_instance_q31 * S,
-q31_t * pSrc)
-{
-
- if (S->ifftFlag == 1u)
- {
- arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
- S->pTwiddle, S->twidCoefModifier);
- }
- else
- {
- arm_radix2_butterfly_q31(pSrc, S->fftLen,
- S->pTwiddle, S->twidCoefModifier);
- }
-
- arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**
-* @} end of ComplexFFT group
-*/
-
-void arm_radix2_butterfly_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
- unsigned i, j, k, l, m;
- unsigned n1, n2, ia;
- q31_t xt, yt, cosVal, sinVal;
- q31_t p0, p1;
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- l = i + n2;
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multAcc_32x32_keep32_R(p0, yt, sinVal);
- multSub_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0;
- pSrc[2u * l + 1u] = p1;
-
- } // groups loop end
-
- twidCoefModifier <<= 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- i = j;
- m = fftLen / n1;
- do
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multAcc_32x32_keep32_R(p0, yt, sinVal);
- multSub_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0;
- pSrc[2u * l + 1u] = p1;
- i += n1;
- m--;
- } while ( m > 0); // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier <<= 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- i += n1;
- l = i + n2;
-
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- } // butterfly loop end
-
-}
-
-
-void arm_radix2_butterfly_inverse_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
- unsigned i, j, k, l;
- unsigned n1, n2, ia;
- q31_t xt, yt, cosVal, sinVal;
- q31_t p0, p1;
-
- //N = fftLen;
- n2 = fftLen;
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (i = 0; i < n2; i++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- l = i + n2;
- xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
- pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
- yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
- pSrc[2 * i + 1] =
- ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multSub_32x32_keep32_R(p0, yt, sinVal);
- multAcc_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0;
- pSrc[2u * l + 1u] = p1;
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
-
- // loop for stage
- for (k = fftLen / 2; k > 2; k = k >> 1)
- {
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- // loop for groups
- for (j = 0; j < n2; j++)
- {
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = j; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
- mult_32x32_keep32_R(p0, xt, cosVal);
- mult_32x32_keep32_R(p1, yt, cosVal);
- multSub_32x32_keep32_R(p0, yt, sinVal);
- multAcc_32x32_keep32_R(p1, xt, sinVal);
-
- pSrc[2u * l] = p0;
- pSrc[2u * l + 1u] = p1;
- } // butterfly loop end
-
- } // groups loop end
-
- twidCoefModifier = twidCoefModifier << 1u;
- } // stages loop end
-
- n1 = n2;
- n2 = n2 >> 1;
- ia = 0;
-
- cosVal = pCoef[ia * 2];
- sinVal = pCoef[(ia * 2) + 1];
- ia = ia + twidCoefModifier;
-
- // loop for butterfly
- for (i = 0; i < fftLen; i += n1)
- {
- l = i + n2;
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- i += n1;
- l = i + n2;
-
- xt = pSrc[2 * i] - pSrc[2 * l];
- pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
- yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
- pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
- pSrc[2u * l] = xt;
-
- pSrc[2u * l + 1u] = yt;
-
- } // butterfly loop end
-
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
deleted file mode 100644
index 00bc097..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
+++ /dev/null
@@ -1,1209 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_f32.c
- * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-extern void arm_bitreversal_f32(
-float32_t * pSrc,
-uint16_t fftSize,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab);
-
-void arm_radix4_butterfly_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier);
-
-void arm_radix4_butterfly_inverse_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier,
-float32_t onebyfftLen);
-
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
-* @addtogroup ComplexFFT
-* @{
-*/
-
-/**
-* @details
-* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
-* @return none.
-*/
-
-void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc)
-{
- if (S->ifftFlag == 1u)
- {
- /* Complex IFFT radix-4 */
- arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen);
- }
- else
- {
- /* Complex FFT radix-4 */
- arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
- }
-
- if (S->bitReverseFlag == 1u)
- {
- /* Bit Reversal */
- arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
- }
-
-}
-
-/**
-* @} end of ComplexFFT group
-*/
-
-/* ----------------------------------------------------------------------
- * Internal helper function used by the FFTs
- * ---------------------------------------------------------------------- */
-
-/*
-* @brief Core function for the floating-point CFFT butterfly process.
-* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
-* @param[in] fftLen length of the FFT.
-* @param[in] *pCoef points to the twiddle coefficient buffer.
-* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-*/
-
-void arm_radix4_butterfly_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
- float32_t co1, co2, co3, si1, si2, si3;
- uint32_t ia1, ia2, ia3;
- uint32_t i0, i1, i2, i3;
- uint32_t n1, n2, j, k;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
- float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
- Ybminusd;
- float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
- float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
- float32_t *ptr1;
- float32_t p0,p1,p2,p3,p4,p5;
- float32_t a0,a1,a2,a3,a4,a5,a6,a7;
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
- i0 = 0u;
- ia1 = 0u;
-
- j = n2;
-
- /* Calculation of first stage */
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- xaIn = pSrc[(2u * i0)];
- yaIn = pSrc[(2u * i0) + 1u];
-
- xbIn = pSrc[(2u * i1)];
- ybIn = pSrc[(2u * i1) + 1u];
-
- xcIn = pSrc[(2u * i2)];
- ycIn = pSrc[(2u * i2) + 1u];
-
- xdIn = pSrc[(2u * i3)];
- ydIn = pSrc[(2u * i3) + 1u];
-
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
- /* xb - xd */
- Xbminusd = xbIn - xdIn;
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
- /* yb - yd */
- Ybminusd = ybIn - ydIn;
-
- /* xa' = xa + xb + xc + xd */
- pSrc[(2u * i0)] = Xaplusc + Xbplusd;
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
- /* (xa - xc) + (yb - yd) */
- Xb12C_out = (Xaminusc + Ybminusd);
- /* (ya - yc) + (xb - xd) */
- Yb12C_out = (Yaminusc - Xbminusd);
- /* (xa + xc) - (xb + xd) */
- Xc12C_out = (Xaplusc - Xbplusd);
- /* (ya + yc) - (yb + yd) */
- Yc12C_out = (Yaplusc - Ybplusd);
- /* (xa - xc) - (yb - yd) */
- Xd12C_out = (Xaminusc - Ybminusd);
- /* (ya - yc) + (xb - xd) */
- Yd12C_out = (Xbminusd + Yaminusc);
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* index calculation for the coefficients */
- ia3 = ia2 + ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- Xb12_out = Xb12C_out * co1;
- Yb12_out = Yb12C_out * co1;
- Xc12_out = Xc12C_out * co2;
- Yc12_out = Yc12C_out * co2;
- Xd12_out = Xd12C_out * co3;
- Yd12_out = Yd12C_out * co3;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- //Xb12_out -= Yb12C_out * si1;
- p0 = Yb12C_out * si1;
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- //Yb12_out += Xb12C_out * si1;
- p1 = Xb12C_out * si1;
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- //Xc12_out -= Yc12C_out * si2;
- p2 = Yc12C_out * si2;
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- //Yc12_out += Xc12C_out * si2;
- p3 = Xc12C_out * si2;
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- //Xd12_out -= Yd12C_out * si3;
- p4 = Yd12C_out * si3;
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- //Yd12_out += Xd12C_out * si3;
- p5 = Xd12C_out * si3;
-
- Xb12_out += p0;
- Yb12_out -= p1;
- Xc12_out += p2;
- Yc12_out -= p3;
- Xd12_out += p4;
- Yd12_out -= p5;
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = Xc12_out;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = Yc12_out;
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = Xb12_out;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = Yb12_out;
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = Xd12_out;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = Yd12_out;
-
- /* Twiddle coefficients index modifier */
- ia1 += twidCoefModifier;
-
- /* Updating input index */
- i0++;
-
- }
- while (--j);
-
- twidCoefModifier <<= 2u;
-
- /* Calculation of second stage to excluding last stage */
- for (k = fftLen >> 2u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* Calculation of first stage */
- j = 0;
- do
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* Twiddle coefficients index modifier */
- ia1 += twidCoefModifier;
-
- i0 = j;
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- xaIn = pSrc[(2u * i0)];
- yaIn = pSrc[(2u * i0) + 1u];
-
- xbIn = pSrc[(2u * i1)];
- ybIn = pSrc[(2u * i1) + 1u];
-
- xcIn = pSrc[(2u * i2)];
- ycIn = pSrc[(2u * i2) + 1u];
-
- xdIn = pSrc[(2u * i3)];
- ydIn = pSrc[(2u * i3) + 1u];
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
- /* (xb - xd) */
- Xbminusd = xbIn - xdIn;
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
- /* (yb - yd) */
- Ybminusd = ybIn - ydIn;
-
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* (xa - xc) + (yb - yd) */
- Xb12C_out = (Xaminusc + Ybminusd);
- /* (ya - yc) - (xb - xd) */
- Yb12C_out = (Yaminusc - Xbminusd);
- /* xa + xc -(xb + xd) */
- Xc12C_out = (Xaplusc - Xbplusd);
- /* (ya + yc) - (yb + yd) */
- Yc12C_out = (Yaplusc - Ybplusd);
- /* (xa - xc) - (yb - yd) */
- Xd12C_out = (Xaminusc - Ybminusd);
- /* (ya - yc) + (xb - xd) */
- Yd12C_out = (Xbminusd + Yaminusc);
-
- pSrc[(2u * i0)] = Xaplusc + Xbplusd;
- pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
- Xb12_out = Xb12C_out * co1;
- Yb12_out = Yb12C_out * co1;
- Xc12_out = Xc12C_out * co2;
- Yc12_out = Yc12C_out * co2;
- Xd12_out = Xd12C_out * co3;
- Yd12_out = Yd12C_out * co3;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- //Xb12_out -= Yb12C_out * si1;
- p0 = Yb12C_out * si1;
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- //Yb12_out += Xb12C_out * si1;
- p1 = Xb12C_out * si1;
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- //Xc12_out -= Yc12C_out * si2;
- p2 = Yc12C_out * si2;
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- //Yc12_out += Xc12C_out * si2;
- p3 = Xc12C_out * si2;
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- //Xd12_out -= Yd12C_out * si3;
- p4 = Yd12C_out * si3;
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- //Yd12_out += Xd12C_out * si3;
- p5 = Xd12C_out * si3;
-
- Xb12_out += p0;
- Yb12_out -= p1;
- Xc12_out += p2;
- Yc12_out -= p3;
- Xd12_out += p4;
- Yd12_out -= p5;
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = Xc12_out;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = Yc12_out;
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = Xb12_out;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = Yb12_out;
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = Xd12_out;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = Yd12_out;
-
- i0 += n1;
- } while (i0 < fftLen);
- j++;
- } while (j <= (n2 - 1u));
- twidCoefModifier <<= 2u;
- }
-
- j = fftLen >> 2;
- ptr1 = &pSrc[0];
-
- /* Calculations of last stage */
- do
- {
- xaIn = ptr1[0];
- yaIn = ptr1[1];
- xbIn = ptr1[2];
- ybIn = ptr1[3];
- xcIn = ptr1[4];
- ycIn = ptr1[5];
- xdIn = ptr1[6];
- ydIn = ptr1[7];
-
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
-
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
-
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
-
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
-
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* (xb-xd) */
- Xbminusd = xbIn - xdIn;
-
- /* (yb-yd) */
- Ybminusd = ybIn - ydIn;
-
- /* xa' = xa + xb + xc + xd */
- a0 = (Xaplusc + Xbplusd);
- /* ya' = ya + yb + yc + yd */
- a1 = (Yaplusc + Ybplusd);
- /* xc' = (xa-xb+xc-xd) */
- a2 = (Xaplusc - Xbplusd);
- /* yc' = (ya-yb+yc-yd) */
- a3 = (Yaplusc - Ybplusd);
- /* xb' = (xa+yb-xc-yd) */
- a4 = (Xaminusc + Ybminusd);
- /* yb' = (ya-xb-yc+xd) */
- a5 = (Yaminusc - Xbminusd);
- /* xd' = (xa-yb-xc+yd)) */
- a6 = (Xaminusc - Ybminusd);
- /* yd' = (ya+xb-yc-xd) */
- a7 = (Xbminusd + Yaminusc);
-
- ptr1[0] = a0;
- ptr1[1] = a1;
- ptr1[2] = a2;
- ptr1[3] = a3;
- ptr1[4] = a4;
- ptr1[5] = a5;
- ptr1[6] = a6;
- ptr1[7] = a7;
-
- /* increment pointer by 8 */
- ptr1 += 8u;
- } while (--j);
-
-#else
-
- float32_t t1, t2, r1, r2, s1, s2;
-
- /* Run the below code for Cortex-M0 */
-
- /* Initializations for the fft calculation */
- n2 = fftLen;
- n1 = n2;
- for (k = fftLen; k > 1u; k >>= 2u)
- {
- /* Initializations for the fft calculation */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* FFT Calculation */
- j = 0;
- do
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- i0 = j;
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* xa + xc */
- r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
- /* xa - xc */
- r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
- /* ya + yc */
- s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
- /* ya - yc */
- s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
- /* xb + xd */
- t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = r1 + t1;
-
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
-
- /* yb + yd */
- t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = s1 + t2;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
- /* (xb - xd) */
- t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
-
- /* (xa - xc) + (yb - yd) */
- r1 = r2 + t1;
-
- /* (xa - xc) - (yb - yd) */
- r2 = r2 - t1;
-
- /* (ya - yc) - (xb - xd) */
- s1 = s2 - t2;
-
- /* (ya - yc) + (xb - xd) */
- s2 = s2 + t2;
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
-
- i0 += n1;
- } while ( i0 < fftLen);
- j++;
- } while (j <= (n2 - 1u));
- twidCoefModifier <<= 2u;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/*
-* @brief Core function for the floating-point CIFFT butterfly process.
-* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
-* @param[in] fftLen length of the FFT.
-* @param[in] *pCoef points to twiddle coefficient buffer.
-* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @param[in] onebyfftLen value of 1/fftLen.
-* @return none.
-*/
-
-void arm_radix4_butterfly_inverse_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier,
-float32_t onebyfftLen)
-{
- float32_t co1, co2, co3, si1, si2, si3;
- uint32_t ia1, ia2, ia3;
- uint32_t i0, i1, i2, i3;
- uint32_t n1, n2, j, k;
-
-#if defined (ARM_MATH_DSP)
-
- float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
- float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
- Ybminusd;
- float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
- float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
- float32_t *ptr1;
- float32_t p0,p1,p2,p3,p4,p5,p6,p7;
- float32_t a0,a1,a2,a3,a4,a5,a6,a7;
-
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
- i0 = 0u;
- ia1 = 0u;
-
- j = n2;
-
- /* Calculation of first stage */
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Butterfly implementation */
- xaIn = pSrc[(2u * i0)];
- yaIn = pSrc[(2u * i0) + 1u];
-
- xcIn = pSrc[(2u * i2)];
- ycIn = pSrc[(2u * i2) + 1u];
-
- xbIn = pSrc[(2u * i1)];
- ybIn = pSrc[(2u * i1) + 1u];
-
- xdIn = pSrc[(2u * i3)];
- ydIn = pSrc[(2u * i3) + 1u];
-
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
- /* xb - xd */
- Xbminusd = xbIn - xdIn;
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
- /* yb - yd */
- Ybminusd = ybIn - ydIn;
-
- /* xa' = xa + xb + xc + xd */
- pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
- /* (xa - xc) - (yb - yd) */
- Xb12C_out = (Xaminusc - Ybminusd);
- /* (ya - yc) + (xb - xd) */
- Yb12C_out = (Yaminusc + Xbminusd);
- /* (xa + xc) - (xb + xd) */
- Xc12C_out = (Xaplusc - Xbplusd);
- /* (ya + yc) - (yb + yd) */
- Yc12C_out = (Yaplusc - Ybplusd);
- /* (xa - xc) + (yb - yd) */
- Xd12C_out = (Xaminusc + Ybminusd);
- /* (ya - yc) - (xb - xd) */
- Yd12C_out = (Yaminusc - Xbminusd);
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* index calculation for the coefficients */
- ia3 = ia2 + ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- Xb12_out = Xb12C_out * co1;
- Yb12_out = Yb12C_out * co1;
- Xc12_out = Xc12C_out * co2;
- Yc12_out = Yc12C_out * co2;
- Xd12_out = Xd12C_out * co3;
- Yd12_out = Yd12C_out * co3;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- //Xb12_out -= Yb12C_out * si1;
- p0 = Yb12C_out * si1;
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- //Yb12_out += Xb12C_out * si1;
- p1 = Xb12C_out * si1;
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- //Xc12_out -= Yc12C_out * si2;
- p2 = Yc12C_out * si2;
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- //Yc12_out += Xc12C_out * si2;
- p3 = Xc12C_out * si2;
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- //Xd12_out -= Yd12C_out * si3;
- p4 = Yd12C_out * si3;
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- //Yd12_out += Xd12C_out * si3;
- p5 = Xd12C_out * si3;
-
- Xb12_out -= p0;
- Yb12_out += p1;
- Xc12_out -= p2;
- Yc12_out += p3;
- Xd12_out -= p4;
- Yd12_out += p5;
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = Xc12_out;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = Yc12_out;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = Xb12_out;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = Yb12_out;
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = Xd12_out;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = Yd12_out;
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- /* Updating input index */
- i0 = i0 + 1u;
-
- } while (--j);
-
- twidCoefModifier <<= 2u;
-
- /* Calculation of second stage to excluding last stage */
- for (k = fftLen >> 2u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* Calculation of first stage */
- j = 0;
- do
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- i0 = j;
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- xaIn = pSrc[(2u * i0)];
- yaIn = pSrc[(2u * i0) + 1u];
-
- xbIn = pSrc[(2u * i1)];
- ybIn = pSrc[(2u * i1) + 1u];
-
- xcIn = pSrc[(2u * i2)];
- ycIn = pSrc[(2u * i2) + 1u];
-
- xdIn = pSrc[(2u * i3)];
- ydIn = pSrc[(2u * i3) + 1u];
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
- /* (xb - xd) */
- Xbminusd = xbIn - xdIn;
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
- /* (yb - yd) */
- Ybminusd = ybIn - ydIn;
-
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* (xa - xc) - (yb - yd) */
- Xb12C_out = (Xaminusc - Ybminusd);
- /* (ya - yc) + (xb - xd) */
- Yb12C_out = (Yaminusc + Xbminusd);
- /* xa + xc -(xb + xd) */
- Xc12C_out = (Xaplusc - Xbplusd);
- /* (ya + yc) - (yb + yd) */
- Yc12C_out = (Yaplusc - Ybplusd);
- /* (xa - xc) + (yb - yd) */
- Xd12C_out = (Xaminusc + Ybminusd);
- /* (ya - yc) - (xb - xd) */
- Yd12C_out = (Yaminusc - Xbminusd);
-
- pSrc[(2u * i0)] = Xaplusc + Xbplusd;
- pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
- Xb12_out = Xb12C_out * co1;
- Yb12_out = Yb12C_out * co1;
- Xc12_out = Xc12C_out * co2;
- Yc12_out = Yc12C_out * co2;
- Xd12_out = Xd12C_out * co3;
- Yd12_out = Yd12C_out * co3;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- //Xb12_out -= Yb12C_out * si1;
- p0 = Yb12C_out * si1;
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- //Yb12_out += Xb12C_out * si1;
- p1 = Xb12C_out * si1;
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- //Xc12_out -= Yc12C_out * si2;
- p2 = Yc12C_out * si2;
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- //Yc12_out += Xc12C_out * si2;
- p3 = Xc12C_out * si2;
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- //Xd12_out -= Yd12C_out * si3;
- p4 = Yd12C_out * si3;
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- //Yd12_out += Xd12C_out * si3;
- p5 = Xd12C_out * si3;
-
- Xb12_out -= p0;
- Yb12_out += p1;
- Xc12_out -= p2;
- Yc12_out += p3;
- Xd12_out -= p4;
- Yd12_out += p5;
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = Xc12_out;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = Yc12_out;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = Xb12_out;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = Yb12_out;
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = Xd12_out;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = Yd12_out;
-
- i0 += n1;
- } while (i0 < fftLen);
- j++;
- } while (j <= (n2 - 1u));
- twidCoefModifier <<= 2u;
- }
- /* Initializations of last stage */
-
- j = fftLen >> 2;
- ptr1 = &pSrc[0];
-
- /* Calculations of last stage */
- do
- {
- xaIn = ptr1[0];
- yaIn = ptr1[1];
- xbIn = ptr1[2];
- ybIn = ptr1[3];
- xcIn = ptr1[4];
- ycIn = ptr1[5];
- xdIn = ptr1[6];
- ydIn = ptr1[7];
-
- /* Butterfly implementation */
- /* xa + xc */
- Xaplusc = xaIn + xcIn;
-
- /* xa - xc */
- Xaminusc = xaIn - xcIn;
-
- /* ya + yc */
- Yaplusc = yaIn + ycIn;
-
- /* ya - yc */
- Yaminusc = yaIn - ycIn;
-
- /* xb + xd */
- Xbplusd = xbIn + xdIn;
-
- /* yb + yd */
- Ybplusd = ybIn + ydIn;
-
- /* (xb-xd) */
- Xbminusd = xbIn - xdIn;
-
- /* (yb-yd) */
- Ybminusd = ybIn - ydIn;
-
- /* xa' = (xa+xb+xc+xd) * onebyfftLen */
- a0 = (Xaplusc + Xbplusd);
- /* ya' = (ya+yb+yc+yd) * onebyfftLen */
- a1 = (Yaplusc + Ybplusd);
- /* xc' = (xa-xb+xc-xd) * onebyfftLen */
- a2 = (Xaplusc - Xbplusd);
- /* yc' = (ya-yb+yc-yd) * onebyfftLen */
- a3 = (Yaplusc - Ybplusd);
- /* xb' = (xa-yb-xc+yd) * onebyfftLen */
- a4 = (Xaminusc - Ybminusd);
- /* yb' = (ya+xb-yc-xd) * onebyfftLen */
- a5 = (Yaminusc + Xbminusd);
- /* xd' = (xa-yb-xc+yd) * onebyfftLen */
- a6 = (Xaminusc + Ybminusd);
- /* yd' = (ya-xb-yc+xd) * onebyfftLen */
- a7 = (Yaminusc - Xbminusd);
-
- p0 = a0 * onebyfftLen;
- p1 = a1 * onebyfftLen;
- p2 = a2 * onebyfftLen;
- p3 = a3 * onebyfftLen;
- p4 = a4 * onebyfftLen;
- p5 = a5 * onebyfftLen;
- p6 = a6 * onebyfftLen;
- p7 = a7 * onebyfftLen;
-
- /* xa' = (xa+xb+xc+xd) * onebyfftLen */
- ptr1[0] = p0;
- /* ya' = (ya+yb+yc+yd) * onebyfftLen */
- ptr1[1] = p1;
- /* xc' = (xa-xb+xc-xd) * onebyfftLen */
- ptr1[2] = p2;
- /* yc' = (ya-yb+yc-yd) * onebyfftLen */
- ptr1[3] = p3;
- /* xb' = (xa-yb-xc+yd) * onebyfftLen */
- ptr1[4] = p4;
- /* yb' = (ya+xb-yc-xd) * onebyfftLen */
- ptr1[5] = p5;
- /* xd' = (xa-yb-xc+yd) * onebyfftLen */
- ptr1[6] = p6;
- /* yd' = (ya-xb-yc+xd) * onebyfftLen */
- ptr1[7] = p7;
-
- /* increment source pointer by 8 for next calculations */
- ptr1 = ptr1 + 8u;
-
- } while (--j);
-
-#else
-
- float32_t t1, t2, r1, r2, s1, s2;
-
- /* Run the below code for Cortex-M0 */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* Calculation of first stage */
- for (k = fftLen; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* Calculation of first stage */
- j = 0;
- do
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- i0 = j;
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* xa + xc */
- r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
- /* xa - xc */
- r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
- /* ya + yc */
- s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
- /* ya - yc */
- s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
- /* xb + xd */
- t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = r1 + t1;
-
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
-
- /* yb + yd */
- t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = s1 + t2;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
- /* (xb - xd) */
- t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
-
- /* (xa - xc) - (yb - yd) */
- r1 = r2 - t1;
-
- /* (xa - xc) + (yb - yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb - xd) */
- s1 = s2 + t2;
-
- /* (ya - yc) - (xb - xd) */
- s2 = s2 - t2;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
-
- i0 += n1;
- } while ( i0 < fftLen);
- j++;
- } while (j <= (n2 - 1u));
- twidCoefModifier <<= 2u;
- }
- /* Initializations of last stage */
- n1 = n2;
- n2 >>= 2u;
-
- /* Calculations of last stage */
- for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = pSrc[2u * i0] + pSrc[2u * i2];
-
- /* xa - xc */
- r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
- /* ya + yc */
- s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
- /* ya - yc */
- s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
- /* xc + xd */
- t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
-
- /* (xa + xb) - (xc + xd) */
- r1 = r1 - t1;
-
- /* yb + yd */
- t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb-yd) */
- t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
- /* (xb-xd) */
- t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = r1 * onebyfftLen;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
-
- /* (xa - xc) - (yb-yd) */
- r1 = r2 - t1;
-
- /* (xa - xc) + (yb-yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb-xd) */
- s1 = s2 + t2;
-
- /* (ya - yc) - (xb-xd) */
- s2 = s2 - t2;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = r1 * onebyfftLen;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = r2 * onebyfftLen;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
- }
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
deleted file mode 100644
index 3979cab..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_init_f32.c
- * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
-* @brief Initialization function for the floating-point CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-
-arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialise the FFT length */
- S->fftLen = fftLen;
-
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (float32_t *) twiddleCoef;
-
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
-
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (S->fftLen)
- {
-
- case 4096u:
- /* Initializations of structure parameters for 4096 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.000244140625;
- break;
-
- case 1024u:
- /* Initializations of structure parameters for 1024 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 4u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 4u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
- /* Initialise the 1/fftLen Value */
- S->onebyfftLen = 0.0009765625f;
- break;
-
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
- S->onebyfftLen = 0.00390625f;
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
- S->onebyfftLen = 0.015625f;
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
- S->onebyfftLen = 0.0625f;
- break;
-
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
deleted file mode 100644
index 0407319..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_init_q15.c
- * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-
-/**
-* @brief Initialization function for the Q15 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
-* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-
-arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
- /* Initialise the FFT length */
- S->fftLen = fftLen;
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (S->fftLen)
- {
- case 4096u:
- /* Initializations of structure parameters for 4096 point FFT */
-
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
-
- break;
-
- case 1024u:
- /* Initializations of structure parameters for 1024 point FFT */
- S->twidCoefModifier = 4u;
- S->bitRevFactor = 4u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
- break;
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
- break;
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
deleted file mode 100644
index 8d0cfd2..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_init_q31.c
- * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
-*
-* @brief Initialization function for the Q31 CFFT/CIFFT.
-* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
-* @param[in] fftLen length of the FFT.
-* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-
-arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
- /* Initialise the FFT length */
- S->fftLen = fftLen;
- /* Initialise the Twiddle coefficient pointer */
- S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
- /* Initialise the Flag for selection of CFFT or CIFFT */
- S->ifftFlag = ifftFlag;
- /* Initialise the Flag for calculation Bit reversal or not */
- S->bitReverseFlag = bitReverseFlag;
-
- /* Initializations of Instance structure depending on the FFT length */
- switch (S->fftLen)
- {
- /* Initializations of structure parameters for 4096 point FFT */
- case 4096u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 1u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 1u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) armBitRevTable;
- break;
-
- /* Initializations of structure parameters for 1024 point FFT */
- case 1024u:
- /* Initialise the twiddle coef modifier value */
- S->twidCoefModifier = 4u;
- /* Initialise the bit reversal table modifier */
- S->bitRevFactor = 4u;
- /* Initialise the bit reversal table pointer */
- S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
- break;
-
- case 256u:
- /* Initializations of structure parameters for 256 point FFT */
- S->twidCoefModifier = 16u;
- S->bitRevFactor = 16u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
- break;
-
- case 64u:
- /* Initializations of structure parameters for 64 point FFT */
- S->twidCoefModifier = 64u;
- S->bitRevFactor = 64u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
- break;
-
- case 16u:
- /* Initializations of structure parameters for 16 point FFT */
- S->twidCoefModifier = 256u;
- S->bitRevFactor = 256u;
- S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
- break;
-
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of ComplexFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c
deleted file mode 100644
index eb65261..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c
+++ /dev/null
@@ -1,1910 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_q15.c
- * Description: This file has function definition of Radix-4 FFT & IFFT function and
- * In-place bit reversal using bit reversal table
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-
-void arm_radix4_butterfly_q15(
- q15_t * pSrc16,
- uint32_t fftLen,
- q15_t * pCoef16,
- uint32_t twidCoefModifier);
-
-void arm_radix4_butterfly_inverse_q15(
- q15_t * pSrc16,
- uint32_t fftLen,
- q15_t * pCoef16,
- uint32_t twidCoefModifier);
-
-void arm_bitreversal_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t * pBitRevTab);
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-
-/**
- * @details
- * @brief Processing function for the Q15 CFFT/CIFFT.
- * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
- * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
- * @return none.
- *
- * \par Input and output formats:
- * \par
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
- * Hence the output format is different for different FFT sizes.
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
- * \par
- * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"
- * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"
- */
-
-void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc)
-{
- if (S->ifftFlag == 1u)
- {
- /* Complex IFFT radix-4 */
- arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
- }
- else
- {
- /* Complex FFT radix-4 */
- arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
- }
-
- if (S->bitReverseFlag == 1u)
- {
- /* Bit Reversal */
- arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
- }
-
-}
-
-/**
- * @} end of ComplexFFT group
- */
-
-/*
-* Radix-4 FFT algorithm used is :
-*
-* Input real and imaginary data:
-* x(n) = xa + j * ya
-* x(n+N/4 ) = xb + j * yb
-* x(n+N/2 ) = xc + j * yc
-* x(n+3N 4) = xd + j * yd
-*
-*
-* Output real and imaginary data:
-* x(4r) = xa'+ j * ya'
-* x(4r+1) = xb'+ j * yb'
-* x(4r+2) = xc'+ j * yc'
-* x(4r+3) = xd'+ j * yd'
-*
-*
-* Twiddle factors for radix-4 FFT:
-* Wn = co1 + j * (- si1)
-* W2n = co2 + j * (- si2)
-* W3n = co3 + j * (- si3)
-
-* The real and imaginary output values for the radix-4 butterfly are
-* xa' = xa + xb + xc + xd
-* ya' = ya + yb + yc + yd
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
-*
-*/
-
-/**
- * @brief Core function for the Q15 CFFT butterfly process.
- * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef16 points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-void arm_radix4_butterfly_q15(
- q15_t * pSrc16,
- uint32_t fftLen,
- q15_t * pCoef16,
- uint32_t twidCoefModifier)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t R, S, T, U;
- q31_t C1, C2, C3, out1, out2;
- uint32_t n1, n2, ic, i0, j, k;
-
- q15_t *ptr1;
- q15_t *pSi0;
- q15_t *pSi1;
- q15_t *pSi2;
- q15_t *pSi3;
-
- q31_t xaya, xbyb, xcyc, xdyd;
-
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- /* Index for twiddle coefficient */
- ic = 0u;
-
- /* Index for input read and output write */
- j = n2;
-
- pSi0 = pSrc16;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- /* Input is in 1.15(q15) format */
-
- /* start of first stage process */
- do
- {
- /* Butterfly implementation */
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T = _SIMD32_OFFSET(pSi0);
- T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
- T = __SHADD16(T, 0); // it turns out doing this twice is 2 cycles, the alternative takes 3 cycles
- //in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles
- //T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
- /* Read yc (real), xc(imag) input */
- S = _SIMD32_OFFSET(pSi2);
- S = __SHADD16(S, 0);
- S = __SHADD16(S, 0);
-
- /* R = packed((ya + yc), (xa + xc) ) */
- R = __QADD16(T, S);
-
- /* S = packed((ya - yc), (xa - xc) ) */
- S = __QSUB16(T, S);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
- T = __SHADD16(T, 0);
- T = __SHADD16(T, 0);
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
- U = __SHADD16(U, 0);
- U = __SHADD16(U, 0);
-
- /* T = packed((yb + yd), (xb + xd) ) */
- T = __QADD16(T, U);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
- pSi0 += 2;
-
- /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
- R = __QSUB16(R, T);
-
- /* co2 & si2 are read from SIMD Coefficient pointer */
- C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- out1 = __SMUAD(C2, R) >> 16u;
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = __SMUSDX(C2, R);
-
-#else
-
- /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out1 = __SMUSDX(R, C2) >> 16u;
- /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- out2 = __SMUAD(C2, R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Reading i0+fftLen/4 */
- /* T = packed(yb, xb) */
- T = _SIMD32_OFFSET(pSi1);
- T = __SHADD16(T, 0);
- T = __SHADD16(T, 0);
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* writing output(xc', yc') in little endian format */
- _SIMD32_OFFSET(pSi1) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi1 += 2;
-
- /* Butterfly calculations */
- /* U = packed(yd, xd) */
- U = _SIMD32_OFFSET(pSi3);
- U = __SHADD16(U, 0);
- U = __SHADD16(U, 0);
-
- /* T = packed(yb-yd, xb-xd) */
- T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __QASX(S, T);
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __QSAX(S, T);
-
-#else
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __QSAX(S, T);
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __QASX(S, T);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* co1 & si1 are read from SIMD Coefficient pointer */
- C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
- /* Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- out1 = __SMUAD(C1, S) >> 16u;
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- out2 = __SMUSDX(C1, S);
-
-#else
-
- /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- out1 = __SMUSDX(S, C1) >> 16u;
- /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- out2 = __SMUAD(C1, S);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* writing output(xb', yb') in little endian format */
- _SIMD32_OFFSET(pSi2) =
- ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
- pSi2 += 2;
-
-
- /* co3 & si3 are read from SIMD Coefficient pointer */
- C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
- /* Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- out1 = __SMUAD(C3, R) >> 16u;
- /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- out2 = __SMUSDX(C3, R);
-
-#else
-
- /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- out1 = __SMUSDX(R, C3) >> 16u;
- /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- out2 = __SMUAD(C3, R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* writing output(xd', yd') in little endian format */
- _SIMD32_OFFSET(pSi3) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi3 += 2;
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- } while (--j);
- /* data is in 4.11(q11) format */
-
- /* end of first stage process */
-
-
- /* start of middle stage process */
-
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
-
- /* Calculation of Middle stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the middle stage */
- n1 = n2;
- n2 >>= 2u;
- ic = 0u;
-
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
- C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
- C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- pSi0 = pSrc16 + 2 * j;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- /* Butterfly implementation */
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T = _SIMD32_OFFSET(pSi0);
-
- /* Read yc (real), xc(imag) input */
- S = _SIMD32_OFFSET(pSi2);
-
- /* R = packed( (ya + yc), (xa + xc)) */
- R = __QADD16(T, S);
-
- /* S = packed((ya - yc), (xa - xc)) */
- S = __QSUB16(T, S);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
-
- /* T = packed( (yb + yd), (xb + xd)) */
- T = __QADD16(T, U);
-
- /* writing the butterfly processed i0 sample */
-
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- out1 = __SHADD16(R, T);
- out1 = __SHADD16(out1, 0);
- _SIMD32_OFFSET(pSi0) = out1;
- pSi0 += 2 * n1;
-
- /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
- R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
- out1 = __SMUAD(C2, R) >> 16u;
-
- /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = __SMUSDX(C2, R);
-
-#else
-
- /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out1 = __SMUSDX(R, C2) >> 16u;
-
- /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
- out2 = __SMUAD(C2, R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Reading i0+3fftLen/4 */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- _SIMD32_OFFSET(pSi1) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi1 += 2 * n1;
-
- /* Butterfly calculations */
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
-
- /* T = packed(yb-yd, xb-xd) */
- T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __SHASX(S, T);
-
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __SHSAX(S, T);
-
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = __SMUAD(C1, S) >> 16u;
- out2 = __SMUSDX(C1, S);
-
-#else
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __SHSAX(S, T);
-
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __SHASX(S, T);
-
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = __SMUSDX(S, C1) >> 16u;
- out2 = __SMUAD(C1, S);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- _SIMD32_OFFSET(pSi2) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi2 += 2 * n1;
-
- /* Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUAD(C3, R) >> 16u;
- out2 = __SMUSDX(C3, R);
-
-#else
-
- out1 = __SMUSDX(R, C3) >> 16u;
- out2 = __SMUAD(C3, R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- _SIMD32_OFFSET(pSi3) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi3 += 2 * n1;
- }
- }
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
- }
- /* end of middle stage process */
-
-
- /* data is in 10.6(q6) format for the 1024 point */
- /* data is in 8.8(q8) format for the 256 point */
- /* data is in 6.10(q10) format for the 64 point */
- /* data is in 4.12(q12) format for the 16 point */
-
- /* Initializations for the last stage */
- j = fftLen >> 2;
-
- ptr1 = &pSrc16[0];
-
- /* start of last stage process */
-
- /* Butterfly implementation */
- do
- {
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD32(ptr1)++;
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD32(ptr1)++;
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD32(ptr1)++;
-
- /* Read xd (real), yd(imag) input */
- xdyd = *__SIMD32(ptr1)++;
-
- /* R = packed((ya + yc), (xa + xc)) */
- R = __QADD16(xaya, xcyc);
-
- /* T = packed((yb + yd), (xb + xd)) */
- T = __QADD16(xbyb, xdyd);
-
- /* pointer updation for writing */
- ptr1 = ptr1 - 8u;
-
-
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
- /* T = packed((yb + yd), (xb + xd)) */
- T = __QADD16(xbyb, xdyd);
-
- /* xc' = (xa-xb+xc-xd) */
- /* yc' = (ya-yb+yc-yd) */
- *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
- /* S = packed((ya - yc), (xa - xc)) */
- S = __QSUB16(xaya, xcyc);
-
- /* Read yd (real), xd(imag) input */
- /* T = packed( (yb - yd), (xb - xd)) */
- U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xb' = (xa+yb-xc-yd) */
- /* yb' = (ya-xb-yc+xd) */
- *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
- /* xd' = (xa-yb-xc+yd) */
- /* yd' = (ya+xb-yc-xd) */
- *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-#else
-
- /* xb' = (xa+yb-xc-yd) */
- /* yb' = (ya-xb-yc+xd) */
- *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
- /* xd' = (xa-yb-xc+yd) */
- /* yd' = (ya+xb-yc-xd) */
- *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- } while (--j);
-
- /* end of last stage process */
-
- /* output is in 11.5(q5) format for the 1024 point */
- /* output is in 9.7(q7) format for the 256 point */
- /* output is in 7.9(q9) format for the 64 point */
- /* output is in 5.11(q11) format for the 16 point */
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t R0, R1, S0, S1, T0, T1, U0, U1;
- q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
- uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- /* Index for twiddle coefficient */
- ic = 0u;
-
- /* Index for input read and output write */
- i0 = 0u;
- j = n2;
-
- /* Input is in 1.15(q15) format */
-
- /* start of first stage process */
- do
- {
- /* Butterfly implementation */
-
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
-
- /* input is down scale by 4 to avoid overflow */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u] >> 2u;
- T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
-
- /* input is down scale by 4 to avoid overflow */
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u] >> 2u;
- S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
- /* R0 = (ya + yc) */
- R0 = __SSAT(T0 + S0, 16u);
- /* R1 = (xa + xc) */
- R1 = __SSAT(T1 + S1, 16u);
-
- /* S0 = (ya - yc) */
- S0 = __SSAT(T0 - S0, 16);
- /* S1 = (xa - xc) */
- S1 = __SSAT(T1 - S1, 16);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* input is down scale by 4 to avoid overflow */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u] >> 2u;
- T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
- /* input is down scale by 4 to avoid overflow */
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u] >> 2u;
- U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
-
- /* T0 = (yb + yd) */
- T0 = __SSAT(T0 + U0, 16u);
- /* T1 = (xb + xd) */
- T1 = __SSAT(T1 + U1, 16u);
-
- /* writing the butterfly processed i0 sample */
- /* ya' = ya + yb + yc + yd */
- /* xa' = xa + xb + xc + xd */
- pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
- pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
- /* R0 = (ya + yc) - (yb + yd) */
- /* R1 = (xa + xc) - (xb + xd) */
- R0 = __SSAT(R0 - T0, 16u);
- R1 = __SSAT(R1 - T1, 16u);
-
- /* co2 & si2 are read from Coefficient pointer */
- Co2 = pCoef16[2u * ic * 2u];
- Si2 = pCoef16[(2u * ic * 2u) + 1];
-
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
- /* Reading i0+fftLen/4 */
- /* input is down scale by 4 to avoid overflow */
- /* T0 = yb, T1 = xb */
- T0 = pSrc16[i1 * 2u] >> 2;
- T1 = pSrc16[(i1 * 2u) + 1] >> 2;
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* writing output(xc', yc') in little endian format */
- pSrc16[i1 * 2u] = out1;
- pSrc16[(i1 * 2u) + 1] = out2;
-
- /* Butterfly calculations */
- /* input is down scale by 4 to avoid overflow */
- /* U0 = yd, U1 = xd */
- U0 = pSrc16[i3 * 2u] >> 2;
- U1 = pSrc16[(i3 * 2u) + 1] >> 2;
- /* T0 = yb-yd */
- T0 = __SSAT(T0 - U0, 16);
- /* T1 = xb-xd */
- T1 = __SSAT(T1 - U1, 16);
-
- /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */
- R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
- R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
-
- /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
- S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16u);
- S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16u);
-
- /* co1 & si1 are read from Coefficient pointer */
- Co1 = pCoef16[ic * 2u];
- Si1 = pCoef16[(ic * 2u) + 1];
- /* Butterfly process for the i0+fftLen/2 sample */
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16);
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16);
-
- /* writing output(xb', yb') in little endian format */
- pSrc16[i2 * 2u] = out1;
- pSrc16[(i2 * 2u) + 1] = out2;
-
- /* Co3 & si3 are read from Coefficient pointer */
- Co3 = pCoef16[3u * (ic * 2u)];
- Si3 = pCoef16[(3u * (ic * 2u)) + 1];
- /* Butterfly process for the i0+3fftLen/4 sample */
- /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
- out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
- /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
- out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
- /* writing output(xd', yd') in little endian format */
- pSrc16[i3 * 2u] = out1;
- pSrc16[(i3 * 2u) + 1] = out2;
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- /* Updating input index */
- i0 = i0 + 1u;
-
- } while (--j);
- /* data is in 4.11(q11) format */
-
- /* end of first stage process */
-
-
- /* start of middle stage process */
-
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
-
- /* Calculation of Middle stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the middle stage */
- n1 = n2;
- n2 >>= 2u;
- ic = 0u;
-
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- Co1 = pCoef16[ic * 2u];
- Si1 = pCoef16[(ic * 2u) + 1u];
- Co2 = pCoef16[2u * (ic * 2u)];
- Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
- Co3 = pCoef16[3u * (ic * 2u)];
- Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- /* Butterfly implementation */
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u];
- T1 = pSrc16[(i0 * 2u) + 1u];
-
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u];
- S1 = pSrc16[(i2 * 2u) + 1u];
-
- /* R0 = (ya + yc), R1 = (xa + xc) */
- R0 = __SSAT(T0 + S0, 16);
- R1 = __SSAT(T1 + S1, 16);
-
- /* S0 = (ya - yc), S1 =(xa - xc) */
- S0 = __SSAT(T0 - S0, 16);
- S1 = __SSAT(T1 - S1, 16);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
-
- /* T0 = (yb + yd), T1 = (xb + xd) */
- T0 = __SSAT(T0 + U0, 16);
- T1 = __SSAT(T1 + U1, 16);
-
- /* writing the butterfly processed i0 sample */
-
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
- out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
- pSrc16[i0 * 2u] = out1;
- pSrc16[(2u * i0) + 1u] = out2;
-
- /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
- R0 = (R0 >> 1u) - (T0 >> 1u);
- R1 = (R1 >> 1u) - (T1 >> 1u);
-
- /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
- out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
-
- /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
- /* Reading i0+3fftLen/4 */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- pSrc16[i1 * 2u] = out1;
- pSrc16[(i1 * 2u) + 1u] = out2;
-
- /* Butterfly calculations */
-
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
- /* T0 = yb-yd, T1 = xb-xd */
- T0 = __SSAT(T0 - U0, 16);
- T1 = __SSAT(T1 - U1, 16);
-
- /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
- R0 = (S0 >> 1u) - (T1 >> 1u);
- R1 = (S1 >> 1u) + (T0 >> 1u);
-
- /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
- S0 = (S0 >> 1u) + (T1 >> 1u);
- S1 = (S1 >> 1u) - (T0 >> 1u);
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16u);
-
- out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16u);
-
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- pSrc16[i2 * 2u] = out1;
- pSrc16[(i2 * 2u) + 1u] = out2;
-
- /* Butterfly process for the i0+3fftLen/4 sample */
- out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
-
- out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
- /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
- /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
- pSrc16[i3 * 2u] = out1;
- pSrc16[(i3 * 2u) + 1u] = out2;
- }
- }
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
- }
- /* end of middle stage process */
-
-
- /* data is in 10.6(q6) format for the 1024 point */
- /* data is in 8.8(q8) format for the 256 point */
- /* data is in 6.10(q10) format for the 64 point */
- /* data is in 4.12(q12) format for the 16 point */
-
- /* Initializations for the last stage */
- n1 = n2;
- n2 >>= 2u;
-
- /* start of last stage process */
-
- /* Butterfly implementation */
- for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u];
- T1 = pSrc16[(i0 * 2u) + 1u];
-
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u];
- S1 = pSrc16[(i2 * 2u) + 1u];
-
- /* R0 = (ya + yc), R1 = (xa + xc) */
- R0 = __SSAT(T0 + S0, 16u);
- R1 = __SSAT(T1 + S1, 16u);
-
- /* S0 = (ya - yc), S1 = (xa - xc) */
- S0 = __SSAT(T0 - S0, 16u);
- S1 = __SSAT(T1 - S1, 16u);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
- /* T0 = (yb + yd), T1 = (xb + xd)) */
- T0 = __SSAT(T0 + U0, 16u);
- T1 = __SSAT(T1 + U1, 16u);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
- pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
- /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
- R0 = (R0 >> 1u) - (T0 >> 1u);
- R1 = (R1 >> 1u) - (T1 >> 1u);
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd) */
- /* yc' = (ya-yb+yc-yd) */
- pSrc16[i1 * 2u] = R0;
- pSrc16[(i1 * 2u) + 1u] = R1;
-
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
- /* T0 = (yb - yd), T1 = (xb - xd) */
- T0 = __SSAT(T0 - U0, 16u);
- T1 = __SSAT(T1 - U1, 16u);
-
- /* writing the butterfly processed i0 + fftLen/2 sample */
- /* xb' = (xa+yb-xc-yd) */
- /* yb' = (ya-xb-yc+xd) */
- pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
- pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
-
- /* writing the butterfly processed i0 + 3fftLen/4 sample */
- /* xd' = (xa-yb-xc+yd) */
- /* yd' = (ya+xb-yc-xd) */
- pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
- pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
- }
-
- /* end of last stage process */
-
- /* output is in 11.5(q5) format for the 1024 point */
- /* output is in 9.7(q7) format for the 256 point */
- /* output is in 7.9(q9) format for the 64 point */
- /* output is in 5.11(q11) format for the 16 point */
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-
-/**
- * @brief Core function for the Q15 CIFFT butterfly process.
- * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef16 points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-/*
-* Radix-4 IFFT algorithm used is :
-*
-* CIFFT uses same twiddle coefficients as CFFT function
-* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
-*
-*
-* IFFT is implemented with following changes in equations from FFT
-*
-* Input real and imaginary data:
-* x(n) = xa + j * ya
-* x(n+N/4 ) = xb + j * yb
-* x(n+N/2 ) = xc + j * yc
-* x(n+3N 4) = xd + j * yd
-*
-*
-* Output real and imaginary data:
-* x(4r) = xa'+ j * ya'
-* x(4r+1) = xb'+ j * yb'
-* x(4r+2) = xc'+ j * yc'
-* x(4r+3) = xd'+ j * yd'
-*
-*
-* Twiddle factors for radix-4 IFFT:
-* Wn = co1 + j * (si1)
-* W2n = co2 + j * (si2)
-* W3n = co3 + j * (si3)
-
-* The real and imaginary output values for the radix-4 butterfly are
-* xa' = xa + xb + xc + xd
-* ya' = ya + yb + yc + yd
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
-*
-*/
-
-void arm_radix4_butterfly_inverse_q15(
- q15_t * pSrc16,
- uint32_t fftLen,
- q15_t * pCoef16,
- uint32_t twidCoefModifier)
-{
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- q31_t R, S, T, U;
- q31_t C1, C2, C3, out1, out2;
- uint32_t n1, n2, ic, i0, j, k;
-
- q15_t *ptr1;
- q15_t *pSi0;
- q15_t *pSi1;
- q15_t *pSi2;
- q15_t *pSi3;
-
- q31_t xaya, xbyb, xcyc, xdyd;
-
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- /* Index for twiddle coefficient */
- ic = 0u;
-
- /* Index for input read and output write */
- j = n2;
-
- pSi0 = pSrc16;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- /* Input is in 1.15(q15) format */
-
- /* start of first stage process */
- do
- {
- /* Butterfly implementation */
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T = _SIMD32_OFFSET(pSi0);
- T = __SHADD16(T, 0);
- T = __SHADD16(T, 0);
-
- /* Read yc (real), xc(imag) input */
- S = _SIMD32_OFFSET(pSi2);
- S = __SHADD16(S, 0);
- S = __SHADD16(S, 0);
-
- /* R = packed((ya + yc), (xa + xc) ) */
- R = __QADD16(T, S);
-
- /* S = packed((ya - yc), (xa - xc) ) */
- S = __QSUB16(T, S);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
- T = __SHADD16(T, 0);
- T = __SHADD16(T, 0);
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
- U = __SHADD16(U, 0);
- U = __SHADD16(U, 0);
-
- /* T = packed((yb + yd), (xb + xd) ) */
- T = __QADD16(T, U);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
- pSi0 += 2;
-
- /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
- R = __QSUB16(R, T);
-
- /* co2 & si2 are read from SIMD Coefficient pointer */
- C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- out1 = __SMUSD(C2, R) >> 16u;
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = __SMUADX(C2, R);
-
-#else
-
- /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out1 = __SMUADX(C2, R) >> 16u;
- /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Reading i0+fftLen/4 */
- /* T = packed(yb, xb) */
- T = _SIMD32_OFFSET(pSi1);
- T = __SHADD16(T, 0);
- T = __SHADD16(T, 0);
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* writing output(xc', yc') in little endian format */
- _SIMD32_OFFSET(pSi1) =
- (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi1 += 2;
-
- /* Butterfly calculations */
- /* U = packed(yd, xd) */
- U = _SIMD32_OFFSET(pSi3);
- U = __SHADD16(U, 0);
- U = __SHADD16(U, 0);
-
- /* T = packed(yb-yd, xb-xd) */
- T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __QSAX(S, T);
- /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */
- S = __QASX(S, T);
-
-#else
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __QASX(S, T);
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __QSAX(S, T);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* co1 & si1 are read from SIMD Coefficient pointer */
- C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
- /* Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- out1 = __SMUSD(C1, S) >> 16u;
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- out2 = __SMUADX(C1, S);
-
-#else
-
- /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- out1 = __SMUADX(C1, S) >> 16u;
- /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* writing output(xb', yb') in little endian format */
- _SIMD32_OFFSET(pSi2) =
- ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
- pSi2 += 2;
-
-
- /* co3 & si3 are read from SIMD Coefficient pointer */
- C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
- /* Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- out1 = __SMUSD(C3, R) >> 16u;
- /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- out2 = __SMUADX(C3, R);
-
-#else
-
- /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- out1 = __SMUADX(C3, R) >> 16u;
- /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* writing output(xd', yd') in little endian format */
- _SIMD32_OFFSET(pSi3) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi3 += 2;
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- } while (--j);
- /* data is in 4.11(q11) format */
-
- /* end of first stage process */
-
-
- /* start of middle stage process */
-
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
-
- /* Calculation of Middle stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the middle stage */
- n1 = n2;
- n2 >>= 2u;
- ic = 0u;
-
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
- C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
- C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- pSi0 = pSrc16 + 2 * j;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- /* Butterfly implementation */
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T = _SIMD32_OFFSET(pSi0);
-
- /* Read yc (real), xc(imag) input */
- S = _SIMD32_OFFSET(pSi2);
-
- /* R = packed( (ya + yc), (xa + xc)) */
- R = __QADD16(T, S);
-
- /* S = packed((ya - yc), (xa - xc)) */
- S = __QSUB16(T, S);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
-
- /* T = packed( (yb + yd), (xb + xd)) */
- T = __QADD16(T, U);
-
- /* writing the butterfly processed i0 sample */
-
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- out1 = __SHADD16(R, T);
- out1 = __SHADD16(out1, 0);
- _SIMD32_OFFSET(pSi0) = out1;
- pSi0 += 2 * n1;
-
- /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
- R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
- out1 = __SMUSD(C2, R) >> 16u;
-
- /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out2 = __SMUADX(C2, R);
-
-#else
-
- /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- out1 = __SMUADX(R, C2) >> 16u;
-
- /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
- out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* Reading i0+3fftLen/4 */
- /* Read yb (real), xb(imag) input */
- T = _SIMD32_OFFSET(pSi1);
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
- /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
- _SIMD32_OFFSET(pSi1) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi1 += 2 * n1;
-
- /* Butterfly calculations */
-
- /* Read yd (real), xd(imag) input */
- U = _SIMD32_OFFSET(pSi3);
-
- /* T = packed(yb-yd, xb-xd) */
- T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __SHSAX(S, T);
-
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __SHASX(S, T);
-
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = __SMUSD(C1, S) >> 16u;
- out2 = __SMUADX(C1, S);
-
-#else
-
- /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
- R = __SHASX(S, T);
-
- /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
- S = __SHSAX(S, T);
-
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = __SMUADX(S, C1) >> 16u;
- out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
- /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
- _SIMD32_OFFSET(pSi2) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi2 += 2 * n1;
-
- /* Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- out1 = __SMUSD(C3, R) >> 16u;
- out2 = __SMUADX(C3, R);
-
-#else
-
- out1 = __SMUADX(C3, R) >> 16u;
- out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
- /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
- _SIMD32_OFFSET(pSi3) =
- ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
- pSi3 += 2 * n1;
- }
- }
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
- }
- /* end of middle stage process */
-
- /* data is in 10.6(q6) format for the 1024 point */
- /* data is in 8.8(q8) format for the 256 point */
- /* data is in 6.10(q10) format for the 64 point */
- /* data is in 4.12(q12) format for the 16 point */
-
- /* Initializations for the last stage */
- j = fftLen >> 2;
-
- ptr1 = &pSrc16[0];
-
- /* start of last stage process */
-
- /* Butterfly implementation */
- do
- {
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD32(ptr1)++;
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD32(ptr1)++;
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD32(ptr1)++;
-
- /* Read xd (real), yd(imag) input */
- xdyd = *__SIMD32(ptr1)++;
-
- /* R = packed((ya + yc), (xa + xc)) */
- R = __QADD16(xaya, xcyc);
-
- /* T = packed((yb + yd), (xb + xd)) */
- T = __QADD16(xbyb, xdyd);
-
- /* pointer updation for writing */
- ptr1 = ptr1 - 8u;
-
-
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
- /* T = packed((yb + yd), (xb + xd)) */
- T = __QADD16(xbyb, xdyd);
-
- /* xc' = (xa-xb+xc-xd) */
- /* yc' = (ya-yb+yc-yd) */
- *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
- /* S = packed((ya - yc), (xa - xc)) */
- S = __QSUB16(xaya, xcyc);
-
- /* Read yd (real), xd(imag) input */
- /* T = packed( (yb - yd), (xb - xd)) */
- U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* xb' = (xa+yb-xc-yd) */
- /* yb' = (ya-xb-yc+xd) */
- *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
- /* xd' = (xa-yb-xc+yd) */
- /* yd' = (ya+xb-yc-xd) */
- *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#else
-
- /* xb' = (xa+yb-xc-yd) */
- /* yb' = (ya-xb-yc+xd) */
- *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
- /* xd' = (xa-yb-xc+yd) */
- /* yd' = (ya+xb-yc-xd) */
- *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- } while (--j);
-
- /* end of last stage process */
-
- /* output is in 11.5(q5) format for the 1024 point */
- /* output is in 9.7(q7) format for the 256 point */
- /* output is in 7.9(q9) format for the 64 point */
- /* output is in 5.11(q11) format for the 16 point */
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- q15_t R0, R1, S0, S1, T0, T1, U0, U1;
- q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
- uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
-
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- /* Index for twiddle coefficient */
- ic = 0u;
-
- /* Index for input read and output write */
- i0 = 0u;
-
- j = n2;
-
- /* Input is in 1.15(q15) format */
-
- /* Start of first stage process */
- do
- {
- /* Butterfly implementation */
-
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* input is down scale by 4 to avoid overflow */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u] >> 2u;
- T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
- /* input is down scale by 4 to avoid overflow */
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u] >> 2u;
- S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
- /* R0 = (ya + yc), R1 = (xa + xc) */
- R0 = __SSAT(T0 + S0, 16u);
- R1 = __SSAT(T1 + S1, 16u);
- /* S0 = (ya - yc), S1 = (xa - xc) */
- S0 = __SSAT(T0 - S0, 16u);
- S1 = __SSAT(T1 - S1, 16u);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* input is down scale by 4 to avoid overflow */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u] >> 2u;
- T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
- /* Read yd (real), xd(imag) input */
- /* input is down scale by 4 to avoid overflow */
- U0 = pSrc16[i3 * 2u] >> 2u;
- U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
- /* T0 = (yb + yd), T1 = (xb + xd) */
- T0 = __SSAT(T0 + U0, 16u);
- T1 = __SSAT(T1 + U1, 16u);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
- pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
- /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
- R0 = __SSAT(R0 - T0, 16u);
- R1 = __SSAT(R1 - T1, 16u);
- /* co2 & si2 are read from Coefficient pointer */
- Co2 = pCoef16[2u * ic * 2u];
- Si2 = pCoef16[(2u * ic * 2u) + 1u];
- /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
- out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16u);
- /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
- out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16u);
-
- /* Reading i0+fftLen/4 */
- /* input is down scale by 4 to avoid overflow */
- /* T0 = yb, T1 = xb */
- T0 = pSrc16[i1 * 2u] >> 2u;
- T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* writing output(xc', yc') in little endian format */
- pSrc16[i1 * 2u] = out1;
- pSrc16[(i1 * 2u) + 1u] = out2;
-
- /* Butterfly calculations */
- /* input is down scale by 4 to avoid overflow */
- /* U0 = yd, U1 = xd) */
- U0 = pSrc16[i3 * 2u] >> 2u;
- U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
- /* T0 = yb-yd, T1 = xb-xd) */
- T0 = __SSAT(T0 - U0, 16u);
- T1 = __SSAT(T1 - U1, 16u);
- /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
- R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16);
- R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16);
- /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
- S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
- S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
-
- /* co1 & si1 are read from Coefficient pointer */
- Co1 = pCoef16[ic * 2u];
- Si1 = pCoef16[(ic * 2u) + 1u];
- /* Butterfly process for the i0+fftLen/2 sample */
- /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
- out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
- /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
- out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
- /* writing output(xb', yb') in little endian format */
- pSrc16[i2 * 2u] = out1;
- pSrc16[(i2 * 2u) + 1u] = out2;
-
- /* Co3 & si3 are read from Coefficient pointer */
- Co3 = pCoef16[3u * ic * 2u];
- Si3 = pCoef16[(3u * ic * 2u) + 1u];
- /* Butterfly process for the i0+3fftLen/4 sample */
- /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
- out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
- /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
- out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
- /* writing output(xd', yd') in little endian format */
- pSrc16[i3 * 2u] = out1;
- pSrc16[(i3 * 2u) + 1u] = out2;
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- /* Updating input index */
- i0 = i0 + 1u;
-
- } while (--j);
-
- /* End of first stage process */
-
- /* data is in 4.11(q11) format */
-
-
- /* Start of Middle stage process */
-
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
-
- /* Calculation of Middle stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the middle stage */
- n1 = n2;
- n2 >>= 2u;
- ic = 0u;
-
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- Co1 = pCoef16[ic * 2u];
- Si1 = pCoef16[(ic * 2u) + 1u];
- Co2 = pCoef16[2u * ic * 2u];
- Si2 = pCoef16[2u * ic * 2u + 1u];
- Co3 = pCoef16[3u * ic * 2u];
- Si3 = pCoef16[(3u * ic * 2u) + 1u];
-
- /* Twiddle coefficients index modifier */
- ic = ic + twidCoefModifier;
-
- /* Butterfly implementation */
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u];
- T1 = pSrc16[(i0 * 2u) + 1u];
-
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u];
- S1 = pSrc16[(i2 * 2u) + 1u];
-
-
- /* R0 = (ya + yc), R1 = (xa + xc) */
- R0 = __SSAT(T0 + S0, 16u);
- R1 = __SSAT(T1 + S1, 16u);
- /* S0 = (ya - yc), S1 = (xa - xc) */
- S0 = __SSAT(T0 - S0, 16u);
- S1 = __SSAT(T1 - S1, 16u);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
- /* T0 = (yb + yd), T1 = (xb + xd) */
- T0 = __SSAT(T0 + U0, 16u);
- T1 = __SSAT(T1 + U1, 16u);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
- pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
- /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
- R0 = (R0 >> 1u) - (T0 >> 1u);
- R1 = (R1 >> 1u) - (T1 >> 1u);
-
- /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
- out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16);
- /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
- out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16);
-
- /* Reading i0+3fftLen/4 */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
- /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
- pSrc16[i1 * 2u] = out1;
- pSrc16[(i1 * 2u) + 1u] = out2;
-
- /* Butterfly calculations */
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
- /* T0 = yb-yd, T1 = xb-xd) */
- T0 = __SSAT(T0 - U0, 16u);
- T1 = __SSAT(T1 - U1, 16u);
-
- /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
- R0 = (S0 >> 1u) + (T1 >> 1u);
- R1 = (S1 >> 1u) - (T0 >> 1u);
-
- /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
- S0 = (S0 >> 1u) - (T1 >> 1u);
- S1 = (S1 >> 1u) + (T0 >> 1u);
-
- /* Butterfly process for the i0+fftLen/2 sample */
- out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
- out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
- /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
- /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
- pSrc16[i2 * 2u] = out1;
- pSrc16[(i2 * 2u) + 1u] = out2;
-
- /* Butterfly process for the i0+3fftLen/4 sample */
- out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
-
- out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
- /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
- /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
- pSrc16[i3 * 2u] = out1;
- pSrc16[(i3 * 2u) + 1u] = out2;
-
-
- }
- }
- /* Twiddle coefficients index modifier */
- twidCoefModifier <<= 2u;
- }
- /* End of Middle stages process */
-
-
- /* data is in 10.6(q6) format for the 1024 point */
- /* data is in 8.8(q8) format for the 256 point */
- /* data is in 6.10(q10) format for the 64 point */
- /* data is in 4.12(q12) format for the 16 point */
-
- /* start of last stage process */
-
-
- /* Initializations for the last stage */
- n1 = n2;
- n2 >>= 2u;
-
- /* Butterfly implementation */
- for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Reading i0, i0+fftLen/2 inputs */
- /* Read ya (real), xa(imag) input */
- T0 = pSrc16[i0 * 2u];
- T1 = pSrc16[(i0 * 2u) + 1u];
- /* Read yc (real), xc(imag) input */
- S0 = pSrc16[i2 * 2u];
- S1 = pSrc16[(i2 * 2u) + 1u];
-
- /* R0 = (ya + yc), R1 = (xa + xc) */
- R0 = __SSAT(T0 + S0, 16u);
- R1 = __SSAT(T1 + S1, 16u);
- /* S0 = (ya - yc), S1 = (xa - xc) */
- S0 = __SSAT(T0 - S0, 16u);
- S1 = __SSAT(T1 - S1, 16u);
-
- /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
-
- /* T0 = (yb + yd), T1 = (xb + xd) */
- T0 = __SSAT(T0 + U0, 16u);
- T1 = __SSAT(T1 + U1, 16u);
-
- /* writing the butterfly processed i0 sample */
- /* xa' = xa + xb + xc + xd */
- /* ya' = ya + yb + yc + yd */
- pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
- pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
- /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
- R0 = (R0 >> 1u) - (T0 >> 1u);
- R1 = (R1 >> 1u) - (T1 >> 1u);
-
- /* Read yb (real), xb(imag) input */
- T0 = pSrc16[i1 * 2u];
- T1 = pSrc16[(i1 * 2u) + 1u];
-
- /* writing the butterfly processed i0 + fftLen/4 sample */
- /* xc' = (xa-xb+xc-xd) */
- /* yc' = (ya-yb+yc-yd) */
- pSrc16[i1 * 2u] = R0;
- pSrc16[(i1 * 2u) + 1u] = R1;
-
- /* Read yd (real), xd(imag) input */
- U0 = pSrc16[i3 * 2u];
- U1 = pSrc16[(i3 * 2u) + 1u];
- /* T0 = (yb - yd), T1 = (xb - xd) */
- T0 = __SSAT(T0 - U0, 16u);
- T1 = __SSAT(T1 - U1, 16u);
-
- /* writing the butterfly processed i0 + fftLen/2 sample */
- /* xb' = (xa-yb-xc+yd) */
- /* yb' = (ya+xb-yc-xd) */
- pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
- pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
-
- /* writing the butterfly processed i0 + 3fftLen/4 sample */
- /* xd' = (xa+yb-xc-yd) */
- /* yd' = (ya-xb-yc+xd) */
- pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
- pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
- }
- /* end of last stage process */
-
- /* output is in 11.5(q5) format for the 1024 point */
- /* output is in 9.7(q7) format for the 256 point */
- /* output is in 7.9(q9) format for the 64 point */
- /* output is in 5.11(q11) format for the 16 point */
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c
deleted file mode 100644
index 7296312..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c
+++ /dev/null
@@ -1,1389 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix4_q31.c
- * Description: This file has function definition of Radix-4 FFT & IFFT function and
- * In-place bit reversal using bit reversal table
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-void arm_radix4_butterfly_inverse_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint32_t twidCoefModifier);
-
-void arm_radix4_butterfly_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint32_t twidCoefModifier);
-
-void arm_bitreversal_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab);
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup ComplexFFT
- * @{
- */
-
-/**
- * @details
- * @brief Processing function for the Q31 CFFT/CIFFT.
- * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
- * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
- * @return none.
- *
- * \par Input and output formats:
- * \par
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
- * Hence the output format is different for different FFT sizes.
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
- * \par
- * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"
- * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"
- *
- */
-
-void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc)
-{
- if (S->ifftFlag == 1u)
- {
- /* Complex IFFT radix-4 */
- arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
- }
- else
- {
- /* Complex FFT radix-4 */
- arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
- }
-
- if (S->bitReverseFlag == 1u)
- {
- /* Bit Reversal */
- arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
- }
-
-}
-
-/**
- * @} end of ComplexFFT group
- */
-
-/*
-* Radix-4 FFT algorithm used is :
-*
-* Input real and imaginary data:
-* x(n) = xa + j * ya
-* x(n+N/4 ) = xb + j * yb
-* x(n+N/2 ) = xc + j * yc
-* x(n+3N 4) = xd + j * yd
-*
-*
-* Output real and imaginary data:
-* x(4r) = xa'+ j * ya'
-* x(4r+1) = xb'+ j * yb'
-* x(4r+2) = xc'+ j * yc'
-* x(4r+3) = xd'+ j * yd'
-*
-*
-* Twiddle factors for radix-4 FFT:
-* Wn = co1 + j * (- si1)
-* W2n = co2 + j * (- si2)
-* W3n = co3 + j * (- si3)
-*
-* Butterfly implementation:
-* xa' = xa + xb + xc + xd
-* ya' = ya + yb + yc + yd
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
-*
-*/
-
-/**
- * @brief Core function for the Q31 CFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-void arm_radix4_butterfly_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier)
-{
-#if defined(ARM_MATH_CM7)
- uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
- q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-
- q31_t xa, xb, xc, xd;
- q31_t ya, yb, yc, yd;
- q31_t xa_out, xb_out, xc_out, xd_out;
- q31_t ya_out, yb_out, yc_out, yd_out;
-
- q31_t *ptr1;
- q63_t xaya, xbyb, xcyc, xdyd;
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
-
- /* start of first stage process */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
- /* n2 = fftLen/4 */
- n2 >>= 2u;
- i0 = 0u;
- ia1 = 0u;
-
- j = n2;
-
- /* Calculation of first stage */
- do
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
- /* xa - xc */
- r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
- /* xb + xd */
- t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
- /* ya + yc */
- s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
- /* ya - yc */
- s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = (r1 + t1);
- /* (xa + xc) - (xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
-
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = (s1 + t2);
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* yb - yd */
- t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
- /* xb - xd */
- t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
- /* index calculation for the coefficients */
- ia2 = 2u * ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
- ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
- ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
- /* (xa - xc) + (yb - yd) */
- r1 = r2 + t1;
- /* (xa - xc) - (yb - yd) */
- r2 = r2 - t1;
-
- /* (ya - yc) - (xb - xd) */
- s1 = s2 - t2;
- /* (ya - yc) + (xb - xd) */
- s2 = s2 + t2;
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
- ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
- ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
- /* index calculation for the coefficients */
- ia3 = 3u * ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
- ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
- ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- /* Updating input index */
- i0 = i0 + 1u;
-
- } while (--j);
-
- /* end of first stage process */
-
- /* data is in 5.27(q27) format */
-
-
- /* start of Middle stages process */
-
-
- /* each stage in middle stages provides two down scaling of the input */
-
- twidCoefModifier <<= 2u;
-
-
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* Calculation of first stage */
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = pSrc[2u * i0] + pSrc[2u * i2];
- /* xa - xc */
- r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
- /* ya + yc */
- s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
- /* ya - yc */
- s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
- /* xb + xd */
- t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = (r1 + t1) >> 2u;
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
-
- /* yb + yd */
- t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
- /* (xb - xd) */
- t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
- ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
- ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
-
- /* (xa - xc) + (yb - yd) */
- r1 = r2 + t1;
- /* (xa - xc) - (yb - yd) */
- r2 = r2 - t1;
-
- /* (ya - yc) - (xb - xd) */
- s1 = s2 - t2;
- /* (ya - yc) + (xb - xd) */
- s2 = s2 + t2;
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
- ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
- ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
- ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
- ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
- }
- }
- twidCoefModifier <<= 2u;
- }
-#else
- uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
- q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-
- q31_t xa, xb, xc, xd;
- q31_t ya, yb, yc, yd;
- q31_t xa_out, xb_out, xc_out, xd_out;
- q31_t ya_out, yb_out, yc_out, yd_out;
-
- q31_t *ptr1;
- q31_t *pSi0;
- q31_t *pSi1;
- q31_t *pSi2;
- q31_t *pSi3;
- q63_t xaya, xbyb, xcyc, xdyd;
- /* Total process is divided into three stages */
-
- /* process first stage, middle stages, & last stage */
-
-
- /* start of first stage process */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- ia1 = 0u;
-
- j = n2;
-
- pSi0 = pSrc;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- /* Calculation of first stage */
- do
- {
- /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
- /* xa - xc */
- r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
-
- /* xb + xd */
- t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
-
- /* ya + yc */
- s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
- /* ya - yc */
- s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
-
- /* xa' = xa + xb + xc + xd */
- *pSi0++ = (r1 + t1);
- /* (xa + xc) - (xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
-
- /* ya' = ya + yb + yc + yd */
- *pSi0++ = (s1 + t2);
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* yb - yd */
- t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
- /* xb - xd */
- t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
-
- /* index calculation for the coefficients */
- ia2 = 2u * ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
- ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
- ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
- /* (xa - xc) + (yb - yd) */
- r1 = r2 + t1;
- /* (xa - xc) - (yb - yd) */
- r2 = r2 - t1;
-
- /* (ya - yc) - (xb - xd) */
- s1 = s2 - t2;
- /* (ya - yc) + (xb - xd) */
- s2 = s2 + t2;
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
- ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
- ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
- /* index calculation for the coefficients */
- ia3 = 3u * ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
- ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
- ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- } while (--j);
-
- /* end of first stage process */
-
- /* data is in 5.27(q27) format */
-
-
- /* start of Middle stages process */
-
-
- /* each stage in middle stages provides two down scaling of the input */
-
- twidCoefModifier <<= 2u;
-
-
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- /* Calculation of first stage */
- for (j = 0u; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- pSi0 = pSrc + 2 * j;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* Butterfly implementation */
- /* xa + xc */
- r1 = pSi0[0] + pSi2[0];
-
- /* xa - xc */
- r2 = pSi0[0] - pSi2[0];
-
-
- /* ya + yc */
- s1 = pSi0[1] + pSi2[1];
-
- /* ya - yc */
- s2 = pSi0[1] - pSi2[1];
-
-
- /* xb + xd */
- t1 = pSi1[0] + pSi3[0];
-
-
- /* xa' = xa + xb + xc + xd */
- pSi0[0] = (r1 + t1) >> 2u;
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
-
- /* yb + yd */
- t2 = pSi1[1] + pSi3[1];
-
- /* ya' = ya + yb + yc + yd */
- pSi0[1] = (s1 + t2) >> 2u;
- pSi0 += 2 * n1;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSi1[1] - pSi3[1];
-
- /* (xb - xd) */
- t2 = pSi1[0] - pSi3[0];
-
-
- /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
- pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
- ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
- pSi1[1] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
- ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
- pSi1 += 2 * n1;
-
- /* (xa - xc) + (yb - yd) */
- r1 = r2 + t1;
- /* (xa - xc) - (yb - yd) */
- r2 = r2 - t1;
-
- /* (ya - yc) - (xb - xd) */
- s1 = s2 - t2;
- /* (ya - yc) + (xb - xd) */
- s2 = s2 + t2;
-
- /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
- pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
- ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
- pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
- ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
- pSi2 += 2 * n1;
-
- /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
- pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
- ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
- pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
- ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
- pSi3 += 2 * n1;
- }
- }
- twidCoefModifier <<= 2u;
- }
-#endif
-
- /* End of Middle stages process */
-
- /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
- /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
- /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
- /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
- /* start of Last stage process */
- /* Initializations for the last stage */
- j = fftLen >> 2;
- ptr1 = &pSrc[0];
-
- /* Calculations of last stage */
- do
- {
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD64(ptr1)++;
- xa = (q31_t) xaya;
- ya = (q31_t) (xaya >> 32);
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD64(ptr1)++;
- xb = (q31_t) xbyb;
- yb = (q31_t) (xbyb >> 32);
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD64(ptr1)++;
- xc = (q31_t) xcyc;
- yc = (q31_t) (xcyc >> 32);
-
- /* Read xc (real), yc(imag) input */
- xdyd = *__SIMD64(ptr1)++;
- xd = (q31_t) xdyd;
- yd = (q31_t) (xdyd >> 32);
-
-#else
-
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD64(ptr1)++;
- ya = (q31_t) xaya;
- xa = (q31_t) (xaya >> 32);
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD64(ptr1)++;
- yb = (q31_t) xbyb;
- xb = (q31_t) (xbyb >> 32);
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD64(ptr1)++;
- yc = (q31_t) xcyc;
- xc = (q31_t) (xcyc >> 32);
-
- /* Read xc (real), yc(imag) input */
- xdyd = *__SIMD64(ptr1)++;
- yd = (q31_t) xdyd;
- xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
- /* xa' = xa + xb + xc + xd */
- xa_out = xa + xb + xc + xd;
-
- /* ya' = ya + yb + yc + yd */
- ya_out = ya + yb + yc + yd;
-
- /* pointer updation for writing */
- ptr1 = ptr1 - 8u;
-
- /* writing xa' and ya' */
- *ptr1++ = xa_out;
- *ptr1++ = ya_out;
-
- xc_out = (xa - xb + xc - xd);
- yc_out = (ya - yb + yc - yd);
-
- /* writing xc' and yc' */
- *ptr1++ = xc_out;
- *ptr1++ = yc_out;
-
- xb_out = (xa + yb - xc - yd);
- yb_out = (ya - xb - yc + xd);
-
- /* writing xb' and yb' */
- *ptr1++ = xb_out;
- *ptr1++ = yb_out;
-
- xd_out = (xa - yb - xc + yd);
- yd_out = (ya + xb - yc - xd);
-
- /* writing xd' and yd' */
- *ptr1++ = xd_out;
- *ptr1++ = yd_out;
-
-
- } while (--j);
-
- /* output is in 11.21(q21) format for the 1024 point */
- /* output is in 9.23(q23) format for the 256 point */
- /* output is in 7.25(q25) format for the 64 point */
- /* output is in 5.27(q27) format for the 16 point */
-
- /* End of last stage process */
-
-}
-
-
-/**
- * @brief Core function for the Q31 CIFFT butterfly process.
- * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
- * @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
- * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-
-/*
-* Radix-4 IFFT algorithm used is :
-*
-* CIFFT uses same twiddle coefficients as CFFT Function
-* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
-*
-*
-* IFFT is implemented with following changes in equations from FFT
-*
-* Input real and imaginary data:
-* x(n) = xa + j * ya
-* x(n+N/4 ) = xb + j * yb
-* x(n+N/2 ) = xc + j * yc
-* x(n+3N 4) = xd + j * yd
-*
-*
-* Output real and imaginary data:
-* x(4r) = xa'+ j * ya'
-* x(4r+1) = xb'+ j * yb'
-* x(4r+2) = xc'+ j * yc'
-* x(4r+3) = xd'+ j * yd'
-*
-*
-* Twiddle factors for radix-4 IFFT:
-* Wn = co1 + j * (si1)
-* W2n = co2 + j * (si2)
-* W3n = co3 + j * (si3)
-
-* The real and imaginary output values for the radix-4 butterfly are
-* xa' = xa + xb + xc + xd
-* ya' = ya + yb + yc + yd
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
-*
-*/
-
-void arm_radix4_butterfly_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier)
-{
-#if defined(ARM_MATH_CM7)
- uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
- q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
- q31_t xa, xb, xc, xd;
- q31_t ya, yb, yc, yd;
- q31_t xa_out, xb_out, xc_out, xd_out;
- q31_t ya_out, yb_out, yc_out, yd_out;
-
- q31_t *ptr1;
- q63_t xaya, xbyb, xcyc, xdyd;
-
- /* input is be 1.31(q31) format for all FFT sizes */
- /* Total process is divided into three stages */
- /* process first stage, middle stages, & last stage */
-
- /* Start of first stage process */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
- /* n2 = fftLen/4 */
- n2 >>= 2u;
- i0 = 0u;
- ia1 = 0u;
-
- j = n2;
-
- do
- {
-
- /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
- /* xa - xc */
- r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
- /* xb + xd */
- t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
- /* ya + yc */
- s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
- /* ya - yc */
- s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = (r1 + t1);
- /* (xa + xc) - (xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = (s1 + t2);
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* yb - yd */
- t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
- /* xb - xd */
- t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
- /* index calculation for the coefficients */
- ia2 = 2u * ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
- ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
- ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
- /* (xa - xc) - (yb - yd) */
- r1 = r2 - t1;
- /* (xa - xc) + (yb - yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb - xd) */
- s1 = s2 + t2;
- /* (ya - yc) - (xb - xd) */
- s2 = s2 - t2;
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
- ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
- ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
- /* index calculation for the coefficients */
- ia3 = 3u * ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
- ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
- ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- /* Updating input index */
- i0 = i0 + 1u;
-
- } while (--j);
-
- /* data is in 5.27(q27) format */
- /* each stage provides two down scaling of the input */
-
-
- /* Start of Middle stages process */
-
- twidCoefModifier <<= 2u;
-
- /* Calculation of second stage to excluding last stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- for (j = 0; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* index calculation for the input as, */
- /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
- i1 = i0 + n2;
- i2 = i1 + n2;
- i3 = i2 + n2;
-
- /* Butterfly implementation */
- /* xa + xc */
- r1 = pSrc[2u * i0] + pSrc[2u * i2];
- /* xa - xc */
- r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
- /* ya + yc */
- s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
- /* ya - yc */
- s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
- /* xb + xd */
- t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
- /* xa' = xa + xb + xc + xd */
- pSrc[2u * i0] = (r1 + t1) >> 2u;
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
- /* ya' = ya + yb + yc + yd */
- pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
- /* (xb - xd) */
- t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
- ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSrc[(2u * i1) + 1u] =
- (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
- ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
-
- /* (xa - xc) - (yb - yd) */
- r1 = r2 - t1;
- /* (xa - xc) + (yb - yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb - xd) */
- s1 = s2 + t2;
- /* (ya - yc) - (xb - xd) */
- s2 = s2 - t2;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
- ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
- ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
- ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
- ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
- }
- }
- twidCoefModifier <<= 2u;
- }
-#else
- uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
- q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
- q31_t xa, xb, xc, xd;
- q31_t ya, yb, yc, yd;
- q31_t xa_out, xb_out, xc_out, xd_out;
- q31_t ya_out, yb_out, yc_out, yd_out;
-
- q31_t *ptr1;
- q31_t *pSi0;
- q31_t *pSi1;
- q31_t *pSi2;
- q31_t *pSi3;
- q63_t xaya, xbyb, xcyc, xdyd;
-
- /* input is be 1.31(q31) format for all FFT sizes */
- /* Total process is divided into three stages */
- /* process first stage, middle stages, & last stage */
-
- /* Start of first stage process */
-
- /* Initializations for the first stage */
- n2 = fftLen;
- n1 = n2;
- /* n2 = fftLen/4 */
- n2 >>= 2u;
-
- ia1 = 0u;
-
- j = n2;
-
- pSi0 = pSrc;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- do
- {
- /* Butterfly implementation */
- /* xa + xc */
- r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
- /* xa - xc */
- r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
-
- /* xb + xd */
- t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
-
- /* ya + yc */
- s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
- /* ya - yc */
- s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
-
- /* xa' = xa + xb + xc + xd */
- *pSi0++ = (r1 + t1);
- /* (xa + xc) - (xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
- /* ya' = ya + yb + yc + yd */
- *pSi0++ = (s1 + t2);
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* yb - yd */
- t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
- /* xb - xd */
- t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
-
- /* index calculation for the coefficients */
- ia2 = 2u * ia1;
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
- ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
- ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
- /* (xa - xc) - (yb - yd) */
- r1 = r2 - t1;
- /* (xa - xc) + (yb - yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb - xd) */
- s1 = s2 + t2;
- /* (ya - yc) - (xb - xd) */
- s2 = s2 - t2;
-
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
- ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
- ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
- /* index calculation for the coefficients */
- ia3 = 3u * ia1;
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
- ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
- ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- } while (--j);
-
- /* data is in 5.27(q27) format */
- /* each stage provides two down scaling of the input */
-
-
- /* Start of Middle stages process */
-
- twidCoefModifier <<= 2u;
-
- /* Calculation of second stage to excluding last stage */
- for (k = fftLen / 4u; k > 4u; k >>= 2u)
- {
- /* Initializations for the first stage */
- n1 = n2;
- n2 >>= 2u;
- ia1 = 0u;
-
- for (j = 0; j <= (n2 - 1u); j++)
- {
- /* index calculation for the coefficients */
- ia2 = ia1 + ia1;
- ia3 = ia2 + ia1;
- co1 = pCoef[ia1 * 2u];
- si1 = pCoef[(ia1 * 2u) + 1u];
- co2 = pCoef[ia2 * 2u];
- si2 = pCoef[(ia2 * 2u) + 1u];
- co3 = pCoef[ia3 * 2u];
- si3 = pCoef[(ia3 * 2u) + 1u];
- /* Twiddle coefficients index modifier */
- ia1 = ia1 + twidCoefModifier;
-
- pSi0 = pSrc + 2 * j;
- pSi1 = pSi0 + 2 * n2;
- pSi2 = pSi1 + 2 * n2;
- pSi3 = pSi2 + 2 * n2;
-
- for (i0 = j; i0 < fftLen; i0 += n1)
- {
- /* Butterfly implementation */
- /* xa + xc */
- r1 = pSi0[0] + pSi2[0];
-
- /* xa - xc */
- r2 = pSi0[0] - pSi2[0];
-
-
- /* ya + yc */
- s1 = pSi0[1] + pSi2[1];
-
- /* ya - yc */
- s2 = pSi0[1] - pSi2[1];
-
-
- /* xb + xd */
- t1 = pSi1[0] + pSi3[0];
-
-
- /* xa' = xa + xb + xc + xd */
- pSi0[0] = (r1 + t1) >> 2u;
- /* xa + xc -(xb + xd) */
- r1 = r1 - t1;
- /* yb + yd */
- t2 = pSi1[1] + pSi3[1];
-
- /* ya' = ya + yb + yc + yd */
- pSi0[1] = (s1 + t2) >> 2u;
- pSi0 += 2 * n1;
-
- /* (ya + yc) - (yb + yd) */
- s1 = s1 - t2;
-
- /* (yb - yd) */
- t1 = pSi1[1] - pSi3[1];
-
- /* (xb - xd) */
- t2 = pSi1[0] - pSi3[0];
-
-
- /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
- pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
- ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
-
- /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
- pSi1[1] =
-
- (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
- ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
- pSi1 += 2 * n1;
-
- /* (xa - xc) - (yb - yd) */
- r1 = r2 - t1;
- /* (xa - xc) + (yb - yd) */
- r2 = r2 + t1;
-
- /* (ya - yc) + (xb - xd) */
- s1 = s2 + t2;
- /* (ya - yc) - (xb - xd) */
- s2 = s2 - t2;
-
- /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
- pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
- ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
- /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
- pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
- ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
- pSi2 += 2 * n1;
-
- /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
- pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
- ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
- /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
- pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
- ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
- pSi3 += 2 * n1;
- }
- }
- twidCoefModifier <<= 2u;
- }
-#endif
-
- /* End of Middle stages process */
-
- /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
- /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
- /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
- /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
- /* Start of last stage process */
-
-
- /* Initializations for the last stage */
- j = fftLen >> 2;
- ptr1 = &pSrc[0];
-
- /* Calculations of last stage */
- do
- {
-#ifndef ARM_MATH_BIG_ENDIAN
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD64(ptr1)++;
- xa = (q31_t) xaya;
- ya = (q31_t) (xaya >> 32);
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD64(ptr1)++;
- xb = (q31_t) xbyb;
- yb = (q31_t) (xbyb >> 32);
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD64(ptr1)++;
- xc = (q31_t) xcyc;
- yc = (q31_t) (xcyc >> 32);
-
- /* Read xc (real), yc(imag) input */
- xdyd = *__SIMD64(ptr1)++;
- xd = (q31_t) xdyd;
- yd = (q31_t) (xdyd >> 32);
-
-#else
-
- /* Read xa (real), ya(imag) input */
- xaya = *__SIMD64(ptr1)++;
- ya = (q31_t) xaya;
- xa = (q31_t) (xaya >> 32);
-
- /* Read xb (real), yb(imag) input */
- xbyb = *__SIMD64(ptr1)++;
- yb = (q31_t) xbyb;
- xb = (q31_t) (xbyb >> 32);
-
- /* Read xc (real), yc(imag) input */
- xcyc = *__SIMD64(ptr1)++;
- yc = (q31_t) xcyc;
- xc = (q31_t) (xcyc >> 32);
-
- /* Read xc (real), yc(imag) input */
- xdyd = *__SIMD64(ptr1)++;
- yd = (q31_t) xdyd;
- xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
- /* xa' = xa + xb + xc + xd */
- xa_out = xa + xb + xc + xd;
-
- /* ya' = ya + yb + yc + yd */
- ya_out = ya + yb + yc + yd;
-
- /* pointer updation for writing */
- ptr1 = ptr1 - 8u;
-
- /* writing xa' and ya' */
- *ptr1++ = xa_out;
- *ptr1++ = ya_out;
-
- xc_out = (xa - xb + xc - xd);
- yc_out = (ya - yb + yc - yd);
-
- /* writing xc' and yc' */
- *ptr1++ = xc_out;
- *ptr1++ = yc_out;
-
- xb_out = (xa - yb - xc + yd);
- yb_out = (ya + xb - yc - xd);
-
- /* writing xb' and yb' */
- *ptr1++ = xb_out;
- *ptr1++ = yb_out;
-
- xd_out = (xa + yb - xc - yd);
- yd_out = (ya - xb - yc + xd);
-
- /* writing xd' and yd' */
- *ptr1++ = xd_out;
- *ptr1++ = yd_out;
-
- } while (--j);
-
- /* output is in 11.21(q21) format for the 1024 point */
- /* output is in 9.23(q23) format for the 256 point */
- /* output is in 7.25(q25) format for the 64 point */
- /* output is in 5.27(q27) format for the 16 point */
-
- /* End of last stage process */
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
deleted file mode 100644
index b70ab38..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_radix8_f32.c
- * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-
-/* ----------------------------------------------------------------------
- * Internal helper function used by the FFTs
- * -------------------------------------------------------------------- */
-
-/*
-* @brief Core function for the floating-point CFFT butterfly process.
-* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
-* @param[in] fftLen length of the FFT.
-* @param[in] *pCoef points to the twiddle coefficient buffer.
-* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-*/
-
-void arm_radix8_butterfly_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-const float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
- uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
- uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
- uint32_t id;
- uint32_t n1, n2, j;
-
- float32_t r1, r2, r3, r4, r5, r6, r7, r8;
- float32_t t1, t2;
- float32_t s1, s2, s3, s4, s5, s6, s7, s8;
- float32_t p1, p2, p3, p4;
- float32_t co2, co3, co4, co5, co6, co7, co8;
- float32_t si2, si3, si4, si5, si6, si7, si8;
- const float32_t C81 = 0.70710678118f;
-
- n2 = fftLen;
-
- do
- {
- n1 = n2;
- n2 = n2 >> 3;
- i1 = 0;
-
- do
- {
- i2 = i1 + n2;
- i3 = i2 + n2;
- i4 = i3 + n2;
- i5 = i4 + n2;
- i6 = i5 + n2;
- i7 = i6 + n2;
- i8 = i7 + n2;
- r1 = pSrc[2 * i1] + pSrc[2 * i5];
- r5 = pSrc[2 * i1] - pSrc[2 * i5];
- r2 = pSrc[2 * i2] + pSrc[2 * i6];
- r6 = pSrc[2 * i2] - pSrc[2 * i6];
- r3 = pSrc[2 * i3] + pSrc[2 * i7];
- r7 = pSrc[2 * i3] - pSrc[2 * i7];
- r4 = pSrc[2 * i4] + pSrc[2 * i8];
- r8 = pSrc[2 * i4] - pSrc[2 * i8];
- t1 = r1 - r3;
- r1 = r1 + r3;
- r3 = r2 - r4;
- r2 = r2 + r4;
- pSrc[2 * i1] = r1 + r2;
- pSrc[2 * i5] = r1 - r2;
- r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
- s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
- r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
- s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
- s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
- s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
- r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
- s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
- t2 = r1 - s3;
- r1 = r1 + s3;
- s3 = r2 - r4;
- r2 = r2 + r4;
- pSrc[2 * i1 + 1] = r1 + r2;
- pSrc[2 * i5 + 1] = r1 - r2;
- pSrc[2 * i3] = t1 + s3;
- pSrc[2 * i7] = t1 - s3;
- pSrc[2 * i3 + 1] = t2 - r3;
- pSrc[2 * i7 + 1] = t2 + r3;
- r1 = (r6 - r8) * C81;
- r6 = (r6 + r8) * C81;
- r2 = (s6 - s8) * C81;
- s6 = (s6 + s8) * C81;
- t1 = r5 - r1;
- r5 = r5 + r1;
- r8 = r7 - r6;
- r7 = r7 + r6;
- t2 = s5 - r2;
- s5 = s5 + r2;
- s8 = s7 - s6;
- s7 = s7 + s6;
- pSrc[2 * i2] = r5 + s7;
- pSrc[2 * i8] = r5 - s7;
- pSrc[2 * i6] = t1 + s8;
- pSrc[2 * i4] = t1 - s8;
- pSrc[2 * i2 + 1] = s5 - r7;
- pSrc[2 * i8 + 1] = s5 + r7;
- pSrc[2 * i6 + 1] = t2 - r8;
- pSrc[2 * i4 + 1] = t2 + r8;
-
- i1 += n1;
- } while (i1 < fftLen);
-
- if (n2 < 8)
- break;
-
- ia1 = 0;
- j = 1;
-
- do
- {
- /* index calculation for the coefficients */
- id = ia1 + twidCoefModifier;
- ia1 = id;
- ia2 = ia1 + id;
- ia3 = ia2 + id;
- ia4 = ia3 + id;
- ia5 = ia4 + id;
- ia6 = ia5 + id;
- ia7 = ia6 + id;
-
- co2 = pCoef[2 * ia1];
- co3 = pCoef[2 * ia2];
- co4 = pCoef[2 * ia3];
- co5 = pCoef[2 * ia4];
- co6 = pCoef[2 * ia5];
- co7 = pCoef[2 * ia6];
- co8 = pCoef[2 * ia7];
- si2 = pCoef[2 * ia1 + 1];
- si3 = pCoef[2 * ia2 + 1];
- si4 = pCoef[2 * ia3 + 1];
- si5 = pCoef[2 * ia4 + 1];
- si6 = pCoef[2 * ia5 + 1];
- si7 = pCoef[2 * ia6 + 1];
- si8 = pCoef[2 * ia7 + 1];
-
- i1 = j;
-
- do
- {
- /* index calculation for the input */
- i2 = i1 + n2;
- i3 = i2 + n2;
- i4 = i3 + n2;
- i5 = i4 + n2;
- i6 = i5 + n2;
- i7 = i6 + n2;
- i8 = i7 + n2;
- r1 = pSrc[2 * i1] + pSrc[2 * i5];
- r5 = pSrc[2 * i1] - pSrc[2 * i5];
- r2 = pSrc[2 * i2] + pSrc[2 * i6];
- r6 = pSrc[2 * i2] - pSrc[2 * i6];
- r3 = pSrc[2 * i3] + pSrc[2 * i7];
- r7 = pSrc[2 * i3] - pSrc[2 * i7];
- r4 = pSrc[2 * i4] + pSrc[2 * i8];
- r8 = pSrc[2 * i4] - pSrc[2 * i8];
- t1 = r1 - r3;
- r1 = r1 + r3;
- r3 = r2 - r4;
- r2 = r2 + r4;
- pSrc[2 * i1] = r1 + r2;
- r2 = r1 - r2;
- s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
- s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
- s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
- s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
- s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
- s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
- s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
- s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
- t2 = s1 - s3;
- s1 = s1 + s3;
- s3 = s2 - s4;
- s2 = s2 + s4;
- r1 = t1 + s3;
- t1 = t1 - s3;
- pSrc[2 * i1 + 1] = s1 + s2;
- s2 = s1 - s2;
- s1 = t2 - r3;
- t2 = t2 + r3;
- p1 = co5 * r2;
- p2 = si5 * s2;
- p3 = co5 * s2;
- p4 = si5 * r2;
- pSrc[2 * i5] = p1 + p2;
- pSrc[2 * i5 + 1] = p3 - p4;
- p1 = co3 * r1;
- p2 = si3 * s1;
- p3 = co3 * s1;
- p4 = si3 * r1;
- pSrc[2 * i3] = p1 + p2;
- pSrc[2 * i3 + 1] = p3 - p4;
- p1 = co7 * t1;
- p2 = si7 * t2;
- p3 = co7 * t2;
- p4 = si7 * t1;
- pSrc[2 * i7] = p1 + p2;
- pSrc[2 * i7 + 1] = p3 - p4;
- r1 = (r6 - r8) * C81;
- r6 = (r6 + r8) * C81;
- s1 = (s6 - s8) * C81;
- s6 = (s6 + s8) * C81;
- t1 = r5 - r1;
- r5 = r5 + r1;
- r8 = r7 - r6;
- r7 = r7 + r6;
- t2 = s5 - s1;
- s5 = s5 + s1;
- s8 = s7 - s6;
- s7 = s7 + s6;
- r1 = r5 + s7;
- r5 = r5 - s7;
- r6 = t1 + s8;
- t1 = t1 - s8;
- s1 = s5 - r7;
- s5 = s5 + r7;
- s6 = t2 - r8;
- t2 = t2 + r8;
- p1 = co2 * r1;
- p2 = si2 * s1;
- p3 = co2 * s1;
- p4 = si2 * r1;
- pSrc[2 * i2] = p1 + p2;
- pSrc[2 * i2 + 1] = p3 - p4;
- p1 = co8 * r5;
- p2 = si8 * s5;
- p3 = co8 * s5;
- p4 = si8 * r5;
- pSrc[2 * i8] = p1 + p2;
- pSrc[2 * i8 + 1] = p3 - p4;
- p1 = co6 * r6;
- p2 = si6 * s6;
- p3 = co6 * s6;
- p4 = si6 * r6;
- pSrc[2 * i6] = p1 + p2;
- pSrc[2 * i6 + 1] = p3 - p4;
- p1 = co4 * t1;
- p2 = si4 * t2;
- p3 = co4 * t2;
- p4 = si4 * t1;
- pSrc[2 * i4] = p1 + p2;
- pSrc[2 * i4 + 1] = p3 - p4;
-
- i1 += n1;
- } while (i1 < fftLen);
-
- j++;
- } while (j < n2);
-
- twidCoefModifier <<= 3;
- } while (n2 > 7);
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
deleted file mode 100644
index c928ddd..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_f32.c
- * Description: Processing function of DCT4 & IDCT4 F32
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @defgroup DCT4_IDCT4 DCT Type IV Functions
- * Representation of signals by minimum number of values is important for storage and transmission.
- * The possibility of large discontinuity between the beginning and end of a period of a signal
- * in DFT can be avoided by extending the signal so that it is even-symmetric.
- * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
- * spectrum and is very widely used in signal and image coding applications.
- * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
- * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
- *
- * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
- * Reordering of the input data makes the computation of DCT just a problem of
- * computing the DFT of a real signal with a few additional operations.
- * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
- *
- * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
- * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
- * DCT2 implementation can be described in the following steps:
- * - Re-ordering input
- * - Calculating Real FFT
- * - Multiplication of weights and Real FFT output and getting real part from the product.
- *
- * This process is explained by the block diagram below:
- * \image html DCT4.gif "Discrete Cosine Transform - type-IV"
- *
- * \par Algorithm:
- * The N-point type-IV DCT is defined as a real, linear transformation by the formula:
- * \image html DCT4Equation.gif
- * where k = 0,1,2,.....N-1
- *\par
- * Its inverse is defined as follows:
- * \image html IDCT4Equation.gif
- * where n = 0,1,2,.....N-1
- *\par
- * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
- * The symmetry of the transform matrix indicates that the fast algorithms for the forward
- * and inverse transform computation are identical.
- * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
- *
- * \par Lengths supported by the transform:
- * As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().
- * The library provides separate functions for Q15, Q31, and floating-point data types.
- * \par Instance Structure
- * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
- * A separate instance structure must be defined for each transform.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
- * To place an instance structure into a const data section, the instance structure must be manually initialized.
- * Manually initialize the instance structure as follows:
- *
- *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
- *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
- *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
- *
- * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
- * \c normalize is normalizing factor used and is equal to sqrt(2/N);
- * \c pTwiddle points to the twiddle factor table;
- * \c pCosFactor points to the cosFactor table;
- * \c pRfft points to the real FFT instance;
- * \c pCfft points to the complex FFT instance;
- * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
- * and arm_rfft_f32() respectively for details regarding static initialization.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the DCT4 transform functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
-void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer)
-{
- uint32_t i; /* Loop counter */
- float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */
- float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
- float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
- float32_t in; /* Temporary variable */
-
-
- /* DCT4 computation involves DCT2 (which is calculated using RFFT)
- * along with some pre-processing and post-processing.
- * Computational procedure is explained as follows:
- * (a) Pre-processing involves multiplying input with cos factor,
- * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
- * where,
- * r(n) -- output of preprocessing
- * u(n) -- input to preprocessing(actual Source buffer)
- * (b) Calculation of DCT2 using FFT is divided into three steps:
- * Step1: Re-ordering of even and odd elements of input.
- * Step2: Calculating FFT of the re-ordered input.
- * Step3: Taking the real part of the product of FFT output and weights.
- * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * where,
- * Y4 -- DCT4 output, Y2 -- DCT2 output
- * (d) Multiplying the output with the normalizing factor sqrt(2/N).
- */
-
- /*-------- Pre-processing ------------*/
- /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
- arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
- arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-
- /* ----------------------------------------------------------------
- * Step1: Re-ordering of even and odd elements as,
- * pState[i] = pInlineBuffer[2*i] and
- * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
- ---------------------------------------------------------------------*/
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
- pS2 = pState + (S->N - 1u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
- i = (uint32_t) S->Nby2 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = (uint32_t) S->N >> 2u;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4.
- * Compute 4 outputs at a time */
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
- i = ((uint32_t) S->N - 1u) >> 2u;
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ * (float32_t) 0.5;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- i = ((uint32_t) S->N - 1u) % 0x4u;
-
- while (i > 0u)
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = (uint32_t) S->N >> 2u;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = in * S->normalize;
-
- in = *pbuff;
- *pbuff++ = in * S->normalize;
-
- in = *pbuff;
- *pbuff++ = in * S->normalize;
-
- in = *pbuff;
- *pbuff++ = in * S->normalize;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initializing the loop counter to N/2 */
- i = (uint32_t) S->Nby2;
-
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter */
- i = (uint32_t) S->N;
-
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ * (float32_t) 0.5;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- /* Initializing the loop counter */
- i = ((uint32_t) S->N - 1u);
-
- do
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter */
- i = (uint32_t) S->N;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = in * S->normalize;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
deleted file mode 100644
index 2bdbdce..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
+++ /dev/null
@@ -1,16513 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_init_f32.c
- * Description: Initialization function of DCT-4 & IDCT4 F32
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup DCT4_IDCT4
- */
-
-/**
- * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
- * @{
- */
-
-/*
-* @brief Weights Table
-*/
-
-/**
- * \par
- * Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
- * \par
- * C command to generate the table
- *
- * for(i = 0; i< N; i++)
- * {
- * weights[2*i]= cos(i*c);
- * weights[(2*i)+1]= -sin(i * c);
- * }
- * \par
- * Where N is the Number of weights to be calculated and c is pi/(2*N)
- * \par
- * In the tables below the real and imaginary values are placed alternatively, hence the
- * array length is 2*N.
- */
-
-static const float32_t Weights_128[256] = {
- 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
- -0.012271538285719925f,
- 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
- -0.036807222941358832f,
- 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
- -0.061320736302208578f,
- 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
- -0.085797312344439894f,
- 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
- -0.110222207293883060f,
- 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
- -0.134580708507126170f,
- 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
- -0.158858143333861450f,
- 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
- -0.183039887955140950f,
- 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
- -0.207111376192218560f,
- 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
- -0.231058108280671110f,
- 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
- -0.254865659604514570f,
- 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
- -0.278519689385053060f,
- 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
- -0.302005949319228080f,
- 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
- -0.325310292162262930f,
- 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
- -0.348418680249434560f,
- 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
- -0.371317193951837540f,
- 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
- -0.393992040061048100f,
- 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
- -0.416429560097637150f,
- 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
- -0.438616238538527660f,
- 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
- -0.460538710958240010f,
- 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
- -0.482183772079122720f,
- 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
- -0.503538383725717580f,
- 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
- -0.524589682678468950f,
- 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
- -0.545324988422046460f,
- 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
- -0.565731810783613120f,
- 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
- -0.585797857456438860f,
- 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
- -0.605511041404325550f,
- 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
- -0.624859488142386340f,
- 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
- -0.643831542889791390f,
- 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
- -0.662415777590171780f,
- 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
- -0.680600997795453020f,
- 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
- -0.698376249408972920f,
- 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
- -0.715730825283818590f,
- 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
- -0.732654271672412820f,
- 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
- -0.749136394523459260f,
- 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
- -0.765167265622458960f,
- 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
- -0.780737228572094380f,
- 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
- -0.795836904608883460f,
- 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
- -0.810457198252594770f,
- 0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
- -0.824589302785025290f,
- 0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
- -0.838224705554837970f,
- 0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
- -0.851355193105265200f,
- 0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
- -0.863972856121586700f,
- 0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
- -0.876070094195406600f,
- 0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
- -0.887639620402853930f,
- 0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
- -0.898674465693953820f,
- 0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
- -0.909167983090522270f,
- 0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
- -0.919113851690057770f,
- 0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
- -0.928506080473215480f,
- 0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
- -0.937339011912574960f,
- 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
- -0.945607325380521280f,
- 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
- -0.953306040354193750f,
- 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
- -0.960430519415565790f,
- 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
- -0.966976471044852070f,
- 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
- -0.972939952205560070f,
- 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
- -0.978317370719627650f,
- 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
- -0.983105487431216290f,
- 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
- -0.987301418157858430f,
- 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
- -0.990902635427780010f,
- 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
- -0.993906970002356060f,
- 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
- -0.996312612182778000f,
- 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
- -0.998118112900149180f,
- 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
- -0.999322384588349540f,
- 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
- -0.999924701839144500f
-};
-
-static const float32_t Weights_512[1024] = {
- 1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
- -0.003067956762965976f,
- 0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
- -0.009203754782059819f,
- 0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
- -0.015339206284988100f,
- 0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
- -0.021474080275469508f,
- 0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
- -0.027608145778965740f,
- 0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
- -0.033741171851377580f,
- 0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
- -0.039872927587739811f,
- 0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
- -0.046003182130914623f,
- 0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
- -0.052131704680283324f,
- 0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
- -0.058258264500435752f,
- 0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
- -0.064382630929857465f,
- 0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
- -0.070504573389613856f,
- 0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
- -0.076623861392031492f,
- 0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
- -0.082740264549375692f,
- 0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
- -0.088853552582524600f,
- 0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
- -0.094963495329638992f,
- 0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
- -0.101069862754827820f,
- 0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
- -0.107172424956808840f,
- 0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
- -0.113270952177564350f,
- 0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
- -0.119365214810991350f,
- 0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
- -0.125454983411546230f,
- 0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
- -0.131540028702883120f,
- 0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
- -0.137620121586486040f,
- 0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
- -0.143695033150294470f,
- 0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
- -0.149764534677321510f,
- 0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
- -0.155828397654265230f,
- 0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
- -0.161886393780111830f,
- 0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
- -0.167938294974731170f,
- 0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
- -0.173983873387463820f,
- 0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
- -0.180022901405699510f,
- 0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
- -0.186055151663446630f,
- 0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
- -0.192080397049892440f,
- 0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
- -0.198098410717953560f,
- 0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
- -0.204108966092816870f,
- 0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
- -0.210111836880469610f,
- 0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
- -0.216106797076219520f,
- 0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
- -0.222093620973203510f,
- 0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
- -0.228072083170885730f,
- 0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
- -0.234041958583543430f,
- 0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
- -0.240003022448741500f,
- 0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
- -0.245955050335794590f,
- 0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
- -0.251897818154216970f,
- 0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,
- -0.257831102162158990f,
- 0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,
- -0.263754678974831350f,
- 0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f,
- -0.269668325572915090f,
- 0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f,
- -0.275571819310958140f,
- 0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f,
- -0.281464937925757940f,
- 0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f,
- -0.287347459544729510f,
- 0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f,
- -0.293219162694258630f,
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- 0.008820275160807512f, -0.999961100616462820f, 0.008628534860211857f,
- -0.999962773500176930f,
- 0.008436794242369860f, -0.999964409618118280f, 0.008245053314331058f,
- -0.999966008970226920f,
- 0.008053312083144991f, -0.999967571556443780f, 0.007861570555861883f,
- -0.999969097376711580f,
- 0.007669828739531077f, -0.999970586430974140f, 0.007478086641202815f,
- -0.999972038719176730f,
- 0.007286344267926684f, -0.999973454241265940f, 0.007094601626752279f,
- -0.999974832997189810f,
- 0.006902858724729877f, -0.999976174986897610f, 0.006711115568908869f,
- -0.999977480210339940f,
- 0.006519372166339549f, -0.999978748667468830f, 0.006327628524071549f,
- -0.999979980358237650f,
- 0.006135884649154515f, -0.999981175282601110f, 0.005944140548638765f,
- -0.999982333440515350f,
- 0.005752396229573737f, -0.999983454831937730f, 0.005560651699009764f,
- -0.999984539456826970f,
- 0.005368906963996303f, -0.999985587315143200f, 0.005177162031583702f,
- -0.999986598406848000f,
- 0.004985416908821652f, -0.999987572731904080f, 0.004793671602759852f,
- -0.999988510290275690f,
- 0.004601926120448672f, -0.999989411081928400f, 0.004410180468937601f,
- -0.999990275106828920f,
- 0.004218434655277024f, -0.999991102364945590f, 0.004026688686516664f,
- -0.999991892856248010f,
- 0.003834942569706248f, -0.999992646580707190f, 0.003643196311896179f,
- -0.999993363538295150f,
- 0.003451449920135975f, -0.999994043728985820f, 0.003259703401476044f,
- -0.999994687152754080f,
- 0.003067956762966138f, -0.999995293809576190f, 0.002876210011656010f,
- -0.999995863699429940f,
- 0.002684463154596083f, -0.999996396822294350f, 0.002492716198835898f,
- -0.999996893178149880f,
- 0.002300969151425887f, -0.999997352766978210f, 0.002109222019415816f,
- -0.999997775588762350f,
- 0.001917474809855460f, -0.999998161643486980f, 0.001725727529795258f,
- -0.999998510931137790f,
- 0.001533980186284766f, -0.999998823451701880f, 0.001342232786374430f,
- -0.999999099205167830f,
- 0.001150485337113809f, -0.999999338191525530f, 0.000958737845553352f,
- -0.999999540410766110f,
- 0.000766990318742846f, -0.999999705862882230f, 0.000575242763732077f,
- -0.999999834547867670f,
- 0.000383495187571497f, -0.999999926465717890f, 0.000191747597310674f,
- -0.999999981616429330f
-};
-
-/**
-* \par
-* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
-* \par
-* C command to generate the table
-* \par
-* for(i = 0; i< N; i++)
-* {
-* cos_factors[i]= 2 * cos((2*i+1)*c/2);
-* }
-* \par
-* where N is the number of factors to generate and c is pi/(2*N)
-*/
-static const float32_t cos_factors_128[128] = {
- 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
- 0.999077727752645360f,
- 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
- 0.995767414467659820f,
- 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
- 0.990058210262297120f,
- 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
- 0.981963869109555240f,
- 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
- 0.971503890986251780f,
- 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
- 0.958703474895871600f,
- 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
- 0.943593458161960390f,
- 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
- 0.926210242138311380f,
- 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
- 0.906595704514915330f,
- 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
- 0.884797098430937790f,
- 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
- 0.860866938637767310f,
- 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
- 0.834862874986380010f,
- 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
- 0.806847553543799330f,
- 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
- 0.776888465673232440f,
- 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
- 0.745057785441466060f,
- 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
- 0.711432195745216430f,
- 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
- 0.676092703575316030f,
- 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
- 0.639124444863775730f,
- 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
- 0.600616479383868970f,
- 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
- 0.560661576197336030f,
- 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
- 0.519355990165589530f,
- 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
- 0.476799230063322250f,
- 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
- 0.433093818853152010f,
- 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
- 0.388345046698826300f,
- 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
- 0.342660717311994380f,
- 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
- 0.296150888243623960f,
- 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
- 0.248927605745720260f,
- 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
- 0.201104634842091960f,
- 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
- 0.152797185258443410f,
- 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
- 0.104121633872054730f,
- 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
- 0.055195244349690031f,
- 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
- 0.006135884649154515f
-};
-
-static const float32_t cos_factors_512[512] = {
- 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
- 0.999942349676023910f,
- 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
- 0.999735288260561680f,
- 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
- 0.999377670388002850f,
- 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
- 0.998869549914283560f,
- 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
- 0.998211003360478190f,
- 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
- 0.997402129901275300f,
- 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
- 0.996443051350042630f,
- 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
- 0.995333912140482280f,
- 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
- 0.994074879304879370f,
- 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
- 0.992666142448948020f,
- 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
- 0.991107913723276890f,
- 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
- 0.989400427791380380f,
- 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
- 0.987543941794359230f,
- 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
- 0.985538735312176060f,
- 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
- 0.983385110321551180f,
- 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
- 0.981083391150486710f,
- 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
- 0.978633924429423210f,
- 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
- 0.976037079039039020f,
- 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
- 0.973293246054698250f,
- 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
- 0.970402838687555500f,
- 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
- 0.967366292222328510f,
- 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
- 0.964184063951745830f,
- 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
- 0.960856633107679660f,
- 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
- 0.957384500788975860f,
- 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
- 0.953768189885990330f,
- 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
- 0.950008245001843000f,
- 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
- 0.946105232370403450f,
- 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
- 0.942059739771017310f,
- 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
- 0.937872376439989890f,
- 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
- 0.933543772978836170f,
- 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
- 0.929074581259315860f,
- 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
- 0.924465474325262600f,
- 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
- 0.919717146291227360f,
- 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
- 0.914830312237946200f,
- 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
- 0.909805708104652220f,
- 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
- 0.904644090578246240f,
- 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
- 0.899346236979341570f,
- 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
- 0.893912945145203250f,
- 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
- 0.888345033309596350f,
- 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
- 0.882643339979562790f,
- 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
- 0.876808723809145650f,
- 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
- 0.870842063470078980f,
- 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
- 0.864744257519462380f,
- 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
- 0.858516224264442740f,
- 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
- 0.852158901623919830f,
- 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
- 0.845673246987299070f,
- 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
- 0.839060237070312740f,
- 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
- 0.832320867767929680f,
- 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
- 0.825456154004377550f,
- 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
- 0.818467129580298660f,
- 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
- 0.811354847017063730f,
- 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
- 0.804120377398265810f,
- 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
- 0.796764810208418830f,
- 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
- 0.789289253168885650f,
- 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
- 0.781694832071059390f,
- 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
- 0.773982690606822900f,
- 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
- 0.766153990196312920f,
- 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
- 0.758209909813015280f,
- 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
- 0.750151645806215070f,
- 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
- 0.741980411720831070f,
- 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
- 0.733697438114660370f,
- 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
- 0.725303972373060770f,
- 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
- 0.716801278521099540f,
- 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
- 0.708190637033195400f,
- 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
- 0.699473344640283770f,
- 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
- 0.690650714134534720f,
- 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
- 0.681724074171649820f,
- 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
- 0.672694769070772970f,
- 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
- 0.663564158612039880f,
- 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
- 0.654333617831800550f,
- 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
- 0.645004536815544040f,
- 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
- 0.635578320488556230f,
- 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
- 0.626056388404343520f,
- 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
- 0.616440174530853650f,
- 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
- 0.606731127034524480f,
- 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
- 0.596930708062196500f,
- 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
- 0.587040393520918080f,
- 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
- 0.577061672855679550f,
- 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
- 0.566996048825108680f,
- 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
- 0.556845037275160100f,
- 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
- 0.546610166910834860f,
- 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
- 0.536292979065963180f,
- 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
- 0.525895027471084740f,
- 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
- 0.515417878019463150f,
- 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
- 0.504863108531267480f,
- 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
- 0.494232308515959730f,
- 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
- 0.483527078932918740f,
- 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
- 0.472749031950342900f,
- 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
- 0.461899790702462840f,
- 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
- 0.450980989045103810f,
- 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
- 0.439994271309633260f,
- 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
- 0.428941292055329550f,
- 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
- 0.417823715820212380f,
- 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
- 0.406643216870369140f,
- 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
- 0.395401478947816300f,
- 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
- 0.384100195016935040f,
- 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
- 0.372741067009515810f,
- 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
- 0.361325805568454340f,
- 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
- 0.349856129790135030f,
- 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
- 0.338333766965541290f,
- 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
- 0.326760452320131790f,
- 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
- 0.315137928752522440f,
- 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
- 0.303467946572011370f,
- 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
- 0.291752263234989370f,
- 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
- 0.279992643080273380f,
- 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
- 0.268190857063403180f,
- 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
- 0.256348682489942910f,
- 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
- 0.244467902747824210f,
- 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
- 0.232550307038775330f,
- 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
- 0.220597690108873650f,
- 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
- 0.208611851978263460f,
- 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
- 0.196594597670080220f,
- 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
- 0.184547736938619640f,
- 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
- 0.172473083996796030f,
- 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
- 0.160372457242928400f,
- 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
- 0.148247678986896200f,
- 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
- 0.136100575175706200f,
- 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
- 0.123932975118512200f,
- 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
- 0.111746711211126660f,
- 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
- 0.099543618660069444f,
- 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
- 0.087325535206192226f,
- 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
- 0.075094300847921291f,
- 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
- 0.062851757564161420f,
- 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
- 0.050599749036899337f,
- 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
- 0.038340120373552791f,
- 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
- 0.026074717829104040f,
- 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
- 0.013805388528060349f,
- 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
- 0.001533980186284766f
-};
-
-static const float32_t cos_factors_2048[2048] = {
- 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
- 0.999996396822294350f,
- 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
- 0.999983454831937730f,
- 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
- 0.999961100616462820f,
- 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
- 0.999929334386276070f,
- 0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
- 0.999888156440373320f,
- 0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
- 0.999837567166337090f,
- 0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
- 0.999777567040332940f,
- 0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
- 0.999708156627104880f,
- 0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
- 0.999629336579970110f,
- 0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
- 0.999541107640812940f,
- 0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
- 0.999443470640077770f,
- 0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
- 0.999336426496761240f,
- 0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
- 0.999219976218403530f,
- 0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
- 0.999094120901079070f,
- 0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
- 0.998958861729386080f,
- 0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
- 0.998814199976435390f,
- 0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
- 0.998660137003838490f,
- 0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
- 0.998496674261694640f,
- 0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
- 0.998323813288577560f,
- 0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
- 0.998141555711520520f,
- 0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
- 0.997949903246001190f,
- 0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
- 0.997748857695925690f,
- 0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
- 0.997538420953611340f,
- 0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
- 0.997318594999768600f,
- 0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
- 0.997089381903483400f,
- 0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
- 0.996850783822196610f,
- 0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
- 0.996602803001684130f,
- 0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
- 0.996345441776035900f,
- 0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
- 0.996078702567633980f,
- 0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
- 0.995802587887129160f,
- 0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
- 0.995517100333418110f,
- 0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
- 0.995222242593618360f,
- 0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
- 0.994918017443043200f,
- 0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
- 0.994604427745175660f,
- 0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
- 0.994281476451641550f,
- 0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
- 0.993949166602181130f,
- 0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
- 0.993607501324621610f,
- 0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
- 0.993256483834846440f,
- 0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
- 0.992896117436765980f,
- 0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
- 0.992526405522286100f,
- 0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
- 0.992147351571276090f,
- 0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
- 0.991758959151536110f,
- 0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
- 0.991361231918763460f,
- 0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
- 0.990954173616518500f,
- 0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
- 0.990537788076188750f,
- 0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
- 0.990112079216953770f,
- 0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
- 0.989677051045747210f,
- 0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
- 0.989232707657220050f,
- 0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
- 0.988779053233701520f,
- 0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
- 0.988316092045159690f,
- 0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
- 0.987843828449161740f,
- 0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
- 0.987362266890832400f,
- 0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
- 0.986871411902812470f,
- 0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
- 0.986371268105216030f,
- 0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
- 0.985861840205586980f,
- 0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
- 0.985343132998854790f,
- 0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
- 0.984815151367289140f,
- 0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
- 0.984277900280454370f,
- 0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
- 0.983731384795162090f,
- 0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,
- 0.983175610055424420f,
- 0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
- 0.982610581292404750f,
- 0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,
- 0.982036303824369020f,
- 0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,
- 0.981452783056635520f,
- 0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,
- 0.980860024481523870f,
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- 0.980258033678303550f,
- 0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
- 0.979646816313141210f,
- 0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
- 0.979026378139047580f,
- 0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
- 0.978396724995823090f,
- 0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f,
- 0.977757862810002760f,
- 0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f,
- 0.977109797594800880f,
- 0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f,
- 0.976452535450054060f,
- 0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f,
- 0.975786082562163930f,
- 0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
- 0.975110445204038890f,
- 0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f,
- 0.974425629735034990f,
- 0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f,
- 0.973731642600896400f,
- 0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f,
- 0.973028490333694210f,
- 0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f,
- 0.972316179551765300f,
- 0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f,
- 0.971594716959650160f,
- 0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f,
- 0.970864109348029470f,
- 0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
- 0.970124363593660280f,
- 0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f,
- 0.969375486659311280f,
- 0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f,
- 0.968617485593697540f,
- 0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f,
- 0.967850367531413620f,
- 0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f,
- 0.967074139692867040f,
- 0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f,
- 0.966288809384209690f,
- 0.966091055410438830f, 0.965892733110190860f, 0.965693842600133690f,
- 0.965494383997269500f,
- 0.965294357418934660f, 0.965093762982799590f, 0.964892600806868890f,
- 0.964690871009481030f,
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- 0.963878277983814200f,
- 0.963673711865903230f, 0.963468578843575950f, 0.963262879037507070f,
- 0.963056612568704340f,
- 0.962849779558509030f, 0.962642380128595710f, 0.962434414400972100f,
- 0.962225882497979020f,
- 0.962016784542290560f, 0.961807120656913540f, 0.961596890965187860f,
- 0.961386095590786250f,
- 0.961174734657714080f, 0.960962808290309780f, 0.960750316613243950f,
- 0.960537259751520050f,
- 0.960323637830473920f, 0.960109450975773940f, 0.959894699313420530f,
- 0.959679382969746750f,
- 0.959463502071417510f, 0.959247056745430090f, 0.959030047119113660f,
- 0.958812473320129310f,
- 0.958594335476470220f, 0.958375633716461170f, 0.958156368168758820f,
- 0.957936538962351420f,
- 0.957716146226558870f, 0.957495190091032570f, 0.957273670685755200f,
- 0.957051588141040970f,
- 0.956828942587535370f, 0.956605734156215080f, 0.956381962978387730f,
- 0.956157629185692140f,
- 0.955932732910098280f, 0.955707274283906560f, 0.955481253439748770f,
- 0.955254670510586990f,
- 0.955027525629714160f, 0.954799818930753720f, 0.954571550547659630f,
- 0.954342720614716480f,
- 0.954113329266538800f, 0.953883376638071770f, 0.953652862864590500f,
- 0.953421788081700310f,
- 0.953190152425336670f, 0.952957956031764700f, 0.952725199037579570f,
- 0.952491881579706320f,
- 0.952258003795399600f, 0.952023565822243570f, 0.951788567798152130f,
- 0.951553009861368590f,
- 0.951316892150465550f, 0.951080214804345010f, 0.950842977962238160f,
- 0.950605181763705340f,
- 0.950366826348635780f, 0.950127911857248100f, 0.949888438430089300f,
- 0.949648406208035480f,
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- 0.948682692199895090f,
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- 0.944730634696167800f,
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- 0.943720366450326200f,
- 0.943466411100659320f, 0.943211900734010620f, 0.942956835500102120f,
- 0.942701215548981900f,
- 0.942445041031024890f, 0.942188312096931770f, 0.941931028897729620f,
- 0.941673191584771360f,
- 0.941414800309736340f, 0.941155855224629190f, 0.940896356481780830f,
- 0.940636304233847590f,
- 0.940375698633811540f, 0.940114539834980280f, 0.939852827990986680f,
- 0.939590563255789270f,
- 0.939327745783671400f, 0.939064375729241950f, 0.938800453247434770f,
- 0.938535978493508560f,
- 0.938270951623047190f, 0.938005372791958840f, 0.937739242156476970f,
- 0.937472559873159250f,
- 0.937205326098887960f, 0.936937540990869900f, 0.936669204706636170f,
- 0.936400317404042060f,
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- 0.000383495187571497f
-};
-
-static const float32_t cos_factors_8192[8192] = {
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- 1.999999549602533100f,
- 1.999999255465430200f, 1.999998887794072000f, 1.999998446588471700f,
- 1.999997931848645600f,
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- 1.999995137547503600f,
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- 1.999991166700750800f,
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- 1.999986019310723500f,
- 1.999984548628669600f, 1.999983004412901000f, 1.999981386663474400f,
- 1.999979695380449400f,
- 1.999977930563888100f, 1.999976092213855400f, 1.999974180330418700f,
- 1.999972194913648900f,
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- 1.999963517914734100f,
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- 1.999953664388809800f,
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- 1.999111027190001000f,
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- 0.001725728172227238f,
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- 0.000191747598192208f
-};
-
-/**
- * @} end of DCT4_IDCT4_Table group
- */
-
-/**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
- * \par Normalizing factor:
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
- * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
- * \image html dct4NormalizingF32Table.gif
- */
-
-arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize)
-{
- /* Initialize the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initializing the pointer array with the weight table base addresses of different lengths */
- float32_t *twiddlePtr[4] =
- { (float32_t *) Weights_128, (float32_t *) Weights_512,
- (float32_t *) Weights_2048, (float32_t *) Weights_8192
- };
-
- /* Initializing the pointer array with the cos factor table base addresses of different lengths */
- float32_t *pCosFactor[4] =
- { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
- (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
- };
-
- /* Initialize the DCT4 length */
- S->N = N;
-
- /* Initialize the half of DCT4 length */
- S->Nby2 = Nby2;
-
- /* Initialize the DCT4 Normalizing factor */
- S->normalize = normalize;
-
- /* Initialize Real FFT Instance */
- S->pRfft = S_RFFT;
-
- /* Initialize Complex FFT Instance */
- S->pCfft = S_CFFT;
-
- switch (N)
- {
- /* Initialize the table modifier values */
- case 8192u:
- S->pTwiddle = twiddlePtr[3];
- S->pCosFactor = pCosFactor[3];
- break;
- case 2048u:
- S->pTwiddle = twiddlePtr[2];
- S->pCosFactor = pCosFactor[2];
- break;
- case 512u:
- S->pTwiddle = twiddlePtr[1];
- S->pCosFactor = pCosFactor[1];
- break;
- case 128u:
- S->pTwiddle = twiddlePtr[0];
- S->pCosFactor = pCosFactor[0];
- break;
- default:
- status = ARM_MATH_ARGUMENT_ERROR;
- }
-
- /* Initialize the RFFT/RIFFT */
- arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
-
- /* return the status of DCT4 Init function */
- return (status);
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c
deleted file mode 100644
index 0898da7..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c
+++ /dev/null
@@ -1,4280 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_init_q15.c
- * Description: Initialization function of DCT-4 & IDCT4 Q15
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup DCT4_IDCT4
- */
-
-/**
- * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
- * @{
- */
-
-/*
-* @brief Weights Table
-*/
-
-/**
- * \par
- * Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
- * \par
- * C command to generate the table
- *
- * for(i = 0; i< N; i++)
- * {
- * weights[2*i]= cos(i*c);
- * weights[(2*i)+1]= -sin(i * c);
- * }
- * \par
- * where N is the Number of weights to be calculated and c is pi/(2*N)
- * \par
- * Converted the output to q15 format by multiplying with 2^31 and saturated if required.
- * \par
- * In the tables below the real and imaginary values are placed alternatively, hence the
- * array length is 2*N.
- */
-
-static const q15_t ALIGN4 WeightsQ15_128[256] = {
- (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a,
- (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505,
- (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7,
- (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893,
- (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d,
- (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a,
- (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d,
- (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079,
- (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3,
- (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e,
- (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d,
- (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33,
- (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505,
- (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005,
- (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36,
- (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c,
- (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239,
- (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f,
- (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23,
- (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674,
- (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307,
- (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd,
- (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9,
- (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b,
- (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806,
- (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb,
- (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b,
- (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7,
- (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1,
- (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8,
- (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e,
- (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003
-};
-
-static const q15_t ALIGN4 WeightsQ15_512[1024] = {
- (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3,
- (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41,
- (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf,
- (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d,
- (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b,
- (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa,
- (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569,
- (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9,
- (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249,
- (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9,
- (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a,
- (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c,
- (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e,
- (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81,
- (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6,
- (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a,
- (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0,
- (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457,
- (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf,
- (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148,
- (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2,
- (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e,
- (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb,
- (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39,
- (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8,
- (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839,
- (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc,
- (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540,
- (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6,
- (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d,
- (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7,
- (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62,
- (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef,
- (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e,
- (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e,
- (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1,
- (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836,
- (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x7282, (q15_t)0xc6ce,
- (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71cc, (q15_t)0xc567,
- (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7112, (q15_t)0xc403,
- (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7053, (q15_t)0xc2a0,
- (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6f90, (q15_t)0xc141,
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- (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b,
- (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d,
- (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004,
- (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001
-};
-
-static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
- (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5,
- (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51,
- (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec,
- (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88,
- (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23,
- (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe,
- (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a,
- (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5,
- (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91,
- (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c,
- (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8,
- (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64,
- (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff,
- (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b,
- (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36,
- (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2,
- (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d,
- (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909,
- (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5,
- (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840,
- (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc,
- (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778,
- (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713,
- (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af,
- (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b,
- (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7,
- (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582,
- (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e,
- (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba,
- (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456,
- (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2,
- (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e,
- (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a,
- (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6,
- (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262,
- (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe,
- (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a,
- (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136,
- (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2,
- (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0c, (q15_t)0xf06e,
- (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f00, (q15_t)0xf00b,
- (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef3, (q15_t)0xefa7,
- (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee6, (q15_t)0xef43,
- (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7ed9, (q15_t)0xeedf,
- (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ecb, (q15_t)0xee7c,
- (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ebd, (q15_t)0xee18,
- (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eaf, (q15_t)0xedb5,
- (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea1, (q15_t)0xed51,
- (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e92, (q15_t)0xecee,
- (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e83, (q15_t)0xec8a,
- (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e73, (q15_t)0xec27,
- (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e63, (q15_t)0xebc4,
- (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e53, (q15_t)0xeb61,
- (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e43, (q15_t)0xeafd,
- (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e32, (q15_t)0xea9a,
- (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e21, (q15_t)0xea37,
- (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e10, (q15_t)0xe9d4,
- (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7dff, (q15_t)0xe971,
- (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7ded, (q15_t)0xe90e,
- (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dda, (q15_t)0xe8ab,
- (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dc8, (q15_t)0xe849,
- (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db5, (q15_t)0xe7e6,
- (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da2, (q15_t)0xe783,
- (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d8f, (q15_t)0xe720,
- (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7b, (q15_t)0xe6be,
- (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d67, (q15_t)0xe65b,
- (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d53, (q15_t)0xe5f9,
- (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d3e, (q15_t)0xe596,
- (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d29, (q15_t)0xe534,
- (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d14, (q15_t)0xe4d2,
- (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7cff, (q15_t)0xe470,
- (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ce9, (q15_t)0xe40e,
- (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd3, (q15_t)0xe3ab,
- (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cbc, (q15_t)0xe349,
- (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7ca6, (q15_t)0xe2e8,
- (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c8f, (q15_t)0xe286,
- (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c77, (q15_t)0xe224,
- (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c60, (q15_t)0xe1c2,
- (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c48, (q15_t)0xe160,
- (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c30, (q15_t)0xe0ff,
- (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c17, (q15_t)0xe09d,
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- (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011,
- (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e,
- (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b,
- (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009,
- (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007,
- (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005,
- (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003,
- (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002,
- (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001,
- (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001,
- (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001
-};
-
-static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
- (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee,
- (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5,
- (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb,
- (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2,
- (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89,
- (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70,
- (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57,
- (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e,
- (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25,
- (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b,
- (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2,
- (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9,
- (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0,
- (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7,
- (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e,
- (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75,
- (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c,
- (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42,
- (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29,
- (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10,
- (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7,
- (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde,
- (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5,
- (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac,
- (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93,
- (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79,
- (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60,
- (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47,
- (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e,
- (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15,
- (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc,
- (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3,
- (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9,
- (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0,
- (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97,
- (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e,
- (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65,
- (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c,
- (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33,
- (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a,
- (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01,
- (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7,
- (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce,
- (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5,
- (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c,
- (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83,
- (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a,
- (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51,
- (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38,
- (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e,
- (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05,
- (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec,
- (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3,
- (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba,
- (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1,
- (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88,
- (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f,
- (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56,
- (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c,
- (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23,
- (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdd, (q15_t)0xfa17, (q15_t)0x7fdc, (q15_t)0xfa11, (q15_t)0x7fdc, (q15_t)0xfa0a,
- (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fdb, (q15_t)0xf9fe, (q15_t)0x7fdb, (q15_t)0xf9f7, (q15_t)0x7fdb, (q15_t)0xf9f1,
- (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fda, (q15_t)0xf9e5, (q15_t)0x7fda, (q15_t)0xf9de, (q15_t)0x7fda, (q15_t)0xf9d8,
- (q15_t)0x7fd9, (q15_t)0xf9d2, (q15_t)0x7fd9, (q15_t)0xf9cb, (q15_t)0x7fd9, (q15_t)0xf9c5, (q15_t)0x7fd8, (q15_t)0xf9bf,
- (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd8, (q15_t)0xf9b2, (q15_t)0x7fd7, (q15_t)0xf9ac, (q15_t)0x7fd7, (q15_t)0xf9a6,
- (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf999, (q15_t)0x7fd6, (q15_t)0xf993, (q15_t)0x7fd6, (q15_t)0xf98d,
- (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd5, (q15_t)0xf980, (q15_t)0x7fd5, (q15_t)0xf97a, (q15_t)0x7fd5, (q15_t)0xf974,
- (q15_t)0x7fd4, (q15_t)0xf96d, (q15_t)0x7fd4, (q15_t)0xf967, (q15_t)0x7fd4, (q15_t)0xf961, (q15_t)0x7fd3, (q15_t)0xf95b,
- (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd3, (q15_t)0xf94e, (q15_t)0x7fd2, (q15_t)0xf948, (q15_t)0x7fd2, (q15_t)0xf941,
- (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd1, (q15_t)0xf935, (q15_t)0x7fd1, (q15_t)0xf92f, (q15_t)0x7fd1, (q15_t)0xf928,
- (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fd0, (q15_t)0xf91c, (q15_t)0x7fd0, (q15_t)0xf916, (q15_t)0x7fcf, (q15_t)0xf90f,
- (q15_t)0x7fcf, (q15_t)0xf909, (q15_t)0x7fcf, (q15_t)0xf903, (q15_t)0x7fce, (q15_t)0xf8fc, (q15_t)0x7fce, (q15_t)0xf8f6,
- (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcd, (q15_t)0xf8ea, (q15_t)0x7fcd, (q15_t)0xf8e3, (q15_t)0x7fcd, (q15_t)0xf8dd,
- (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcc, (q15_t)0xf8d0, (q15_t)0x7fcb, (q15_t)0xf8ca, (q15_t)0x7fcb, (q15_t)0xf8c4,
- (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fca, (q15_t)0xf8b7, (q15_t)0x7fca, (q15_t)0xf8b1, (q15_t)0x7fca, (q15_t)0xf8ab,
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- (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a8, (q15_t)0xc92a, (q15_t)0x73a5, (q15_t)0xc924, (q15_t)0x73a3, (q15_t)0xc91f,
- (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x739d, (q15_t)0xc913, (q15_t)0x739b, (q15_t)0xc90e, (q15_t)0x7398, (q15_t)0xc908,
- (q15_t)0x7395, (q15_t)0xc902, (q15_t)0x7392, (q15_t)0xc8fd, (q15_t)0x7390, (q15_t)0xc8f7, (q15_t)0x738d, (q15_t)0xc8f1,
- (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x7388, (q15_t)0xc8e6, (q15_t)0x7385, (q15_t)0xc8e0, (q15_t)0x7382, (q15_t)0xc8db,
- (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x737d, (q15_t)0xc8cf, (q15_t)0x737a, (q15_t)0xc8ca, (q15_t)0x7377, (q15_t)0xc8c4,
- (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x7372, (q15_t)0xc8b9, (q15_t)0x736f, (q15_t)0xc8b3, (q15_t)0x736c, (q15_t)0xc8ad,
- (q15_t)0x736a, (q15_t)0xc8a8, (q15_t)0x7367, (q15_t)0xc8a2, (q15_t)0x7364, (q15_t)0xc89c, (q15_t)0x7362, (q15_t)0xc897,
- (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x735c, (q15_t)0xc88b, (q15_t)0x7359, (q15_t)0xc886, (q15_t)0x7357, (q15_t)0xc880,
- (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7351, (q15_t)0xc875, (q15_t)0x734f, (q15_t)0xc86f, (q15_t)0x734c, (q15_t)0xc869,
- (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x7346, (q15_t)0xc85e, (q15_t)0x7344, (q15_t)0xc858, (q15_t)0x7341, (q15_t)0xc853,
- (q15_t)0x733e, (q15_t)0xc84d, (q15_t)0x733b, (q15_t)0xc847, (q15_t)0x7339, (q15_t)0xc842, (q15_t)0x7336, (q15_t)0xc83c,
- (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7330, (q15_t)0xc831, (q15_t)0x732e, (q15_t)0xc82b, (q15_t)0x732b, (q15_t)0xc825,
- (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x7326, (q15_t)0xc81a, (q15_t)0x7323, (q15_t)0xc814, (q15_t)0x7320, (q15_t)0xc80f,
- (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x731b, (q15_t)0xc803, (q15_t)0x7318, (q15_t)0xc7fe, (q15_t)0x7315, (q15_t)0xc7f8,
- (q15_t)0x7312, (q15_t)0xc7f3, (q15_t)0x7310, (q15_t)0xc7ed, (q15_t)0x730d, (q15_t)0xc7e7, (q15_t)0x730a, (q15_t)0xc7e2,
- (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7305, (q15_t)0xc7d6, (q15_t)0x7302, (q15_t)0xc7d1, (q15_t)0x72ff, (q15_t)0xc7cb,
- (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f9, (q15_t)0xc7c0, (q15_t)0x72f7, (q15_t)0xc7ba, (q15_t)0x72f4, (q15_t)0xc7b4,
- (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72ee, (q15_t)0xc7a9, (q15_t)0x72ec, (q15_t)0xc7a3, (q15_t)0x72e9, (q15_t)0xc79e,
- (q15_t)0x72e6, (q15_t)0xc798, (q15_t)0x72e3, (q15_t)0xc793, (q15_t)0x72e1, (q15_t)0xc78d, (q15_t)0x72de, (q15_t)0xc787,
- (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d8, (q15_t)0xc77c, (q15_t)0x72d5, (q15_t)0xc776, (q15_t)0x72d3, (q15_t)0xc771,
- (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72cd, (q15_t)0xc765, (q15_t)0x72ca, (q15_t)0xc760, (q15_t)0x72c8, (q15_t)0xc75a,
- (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72c2, (q15_t)0xc74f, (q15_t)0x72bf, (q15_t)0xc749, (q15_t)0x72bc, (q15_t)0xc744,
- (q15_t)0x72ba, (q15_t)0xc73e, (q15_t)0x72b7, (q15_t)0xc738, (q15_t)0x72b4, (q15_t)0xc733, (q15_t)0x72b1, (q15_t)0xc72d,
- (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72ac, (q15_t)0xc722, (q15_t)0x72a9, (q15_t)0xc71c, (q15_t)0x72a6, (q15_t)0xc717,
- (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x72a1, (q15_t)0xc70b, (q15_t)0x729e, (q15_t)0xc706, (q15_t)0x729b, (q15_t)0xc700,
- (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x7295, (q15_t)0xc6f5, (q15_t)0x7293, (q15_t)0xc6ef, (q15_t)0x7290, (q15_t)0xc6ea,
- (q15_t)0x728d, (q15_t)0xc6e4, (q15_t)0x728a, (q15_t)0xc6de, (q15_t)0x7287, (q15_t)0xc6d9, (q15_t)0x7285, (q15_t)0xc6d3,
- (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x727f, (q15_t)0xc6c8, (q15_t)0x727c, (q15_t)0xc6c2, (q15_t)0x7279, (q15_t)0xc6bd,
- (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x7274, (q15_t)0xc6b1, (q15_t)0x7271, (q15_t)0xc6ac, (q15_t)0x726e, (q15_t)0xc6a6,
- (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7268, (q15_t)0xc69b, (q15_t)0x7266, (q15_t)0xc695, (q15_t)0x7263, (q15_t)0xc690,
- (q15_t)0x7260, (q15_t)0xc68a, (q15_t)0x725d, (q15_t)0xc684, (q15_t)0x725a, (q15_t)0xc67f, (q15_t)0x7257, (q15_t)0xc679,
- (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7252, (q15_t)0xc66e, (q15_t)0x724f, (q15_t)0xc668, (q15_t)0x724c, (q15_t)0xc663,
- (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x7247, (q15_t)0xc658, (q15_t)0x7244, (q15_t)0xc652, (q15_t)0x7241, (q15_t)0xc64c,
- (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x723b, (q15_t)0xc641, (q15_t)0x7238, (q15_t)0xc63c, (q15_t)0x7236, (q15_t)0xc636,
- (q15_t)0x7233, (q15_t)0xc630, (q15_t)0x7230, (q15_t)0xc62b, (q15_t)0x722d, (q15_t)0xc625, (q15_t)0x722a, (q15_t)0xc620,
- (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x7224, (q15_t)0xc614, (q15_t)0x7222, (q15_t)0xc60f, (q15_t)0x721f, (q15_t)0xc609,
- (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7219, (q15_t)0xc5fe, (q15_t)0x7216, (q15_t)0xc5f8, (q15_t)0x7213, (q15_t)0xc5f3,
- (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x720e, (q15_t)0xc5e7, (q15_t)0x720b, (q15_t)0xc5e2, (q15_t)0x7208, (q15_t)0xc5dc,
- (q15_t)0x7205, (q15_t)0xc5d7, (q15_t)0x7202, (q15_t)0xc5d1, (q15_t)0x71ff, (q15_t)0xc5cc, (q15_t)0x71fd, (q15_t)0xc5c6,
- (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71f7, (q15_t)0xc5bb, (q15_t)0x71f4, (q15_t)0xc5b5, (q15_t)0x71f1, (q15_t)0xc5b0,
- (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71eb, (q15_t)0xc5a4, (q15_t)0x71e9, (q15_t)0xc59f, (q15_t)0x71e6, (q15_t)0xc599,
- (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71e0, (q15_t)0xc58e, (q15_t)0x71dd, (q15_t)0xc588, (q15_t)0x71da, (q15_t)0xc583,
- (q15_t)0x71d7, (q15_t)0xc57d, (q15_t)0x71d4, (q15_t)0xc578, (q15_t)0x71d2, (q15_t)0xc572, (q15_t)0x71cf, (q15_t)0xc56c,
- (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c9, (q15_t)0xc561, (q15_t)0x71c6, (q15_t)0xc55c, (q15_t)0x71c3, (q15_t)0xc556,
- (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71bd, (q15_t)0xc54b, (q15_t)0x71bb, (q15_t)0xc545, (q15_t)0x71b8, (q15_t)0xc540,
- (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71b2, (q15_t)0xc535, (q15_t)0x71af, (q15_t)0xc52f, (q15_t)0x71ac, (q15_t)0xc529,
- (q15_t)0x71a9, (q15_t)0xc524, (q15_t)0x71a6, (q15_t)0xc51e, (q15_t)0x71a3, (q15_t)0xc519, (q15_t)0x71a1, (q15_t)0xc513,
- (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x719b, (q15_t)0xc508, (q15_t)0x7198, (q15_t)0xc502, (q15_t)0x7195, (q15_t)0xc4fd,
- (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x718f, (q15_t)0xc4f2, (q15_t)0x718c, (q15_t)0xc4ec, (q15_t)0x7189, (q15_t)0xc4e7,
- (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x7184, (q15_t)0xc4db, (q15_t)0x7181, (q15_t)0xc4d6, (q15_t)0x717e, (q15_t)0xc4d0,
- (q15_t)0x717b, (q15_t)0xc4cb, (q15_t)0x7178, (q15_t)0xc4c5, (q15_t)0x7175, (q15_t)0xc4c0, (q15_t)0x7172, (q15_t)0xc4ba,
- (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x716c, (q15_t)0xc4af, (q15_t)0x7169, (q15_t)0xc4a9, (q15_t)0x7167, (q15_t)0xc4a4,
- (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7161, (q15_t)0xc499, (q15_t)0x715e, (q15_t)0xc493, (q15_t)0x715b, (q15_t)0xc48d,
- (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x7155, (q15_t)0xc482, (q15_t)0x7152, (q15_t)0xc47d, (q15_t)0x714f, (q15_t)0xc477,
- (q15_t)0x714c, (q15_t)0xc472, (q15_t)0x7149, (q15_t)0xc46c, (q15_t)0x7146, (q15_t)0xc467, (q15_t)0x7143, (q15_t)0xc461,
- (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x713e, (q15_t)0xc456, (q15_t)0x713b, (q15_t)0xc450, (q15_t)0x7138, (q15_t)0xc44b,
- (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7132, (q15_t)0xc440, (q15_t)0x712f, (q15_t)0xc43a, (q15_t)0x712c, (q15_t)0xc434,
- (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x7126, (q15_t)0xc429, (q15_t)0x7123, (q15_t)0xc424, (q15_t)0x7120, (q15_t)0xc41e,
- (q15_t)0x711d, (q15_t)0xc419, (q15_t)0x711a, (q15_t)0xc413, (q15_t)0x7117, (q15_t)0xc40e, (q15_t)0x7114, (q15_t)0xc408,
- (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x710f, (q15_t)0xc3fd, (q15_t)0x710c, (q15_t)0xc3f7, (q15_t)0x7109, (q15_t)0xc3f2,
- (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x7103, (q15_t)0xc3e7, (q15_t)0x7100, (q15_t)0xc3e1, (q15_t)0x70fd, (q15_t)0xc3dc,
- (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70f7, (q15_t)0xc3d1, (q15_t)0x70f4, (q15_t)0xc3cb, (q15_t)0x70f1, (q15_t)0xc3c5,
- (q15_t)0x70ee, (q15_t)0xc3c0, (q15_t)0x70eb, (q15_t)0xc3ba, (q15_t)0x70e8, (q15_t)0xc3b5, (q15_t)0x70e5, (q15_t)0xc3af,
- (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70df, (q15_t)0xc3a4, (q15_t)0x70dc, (q15_t)0xc39f, (q15_t)0x70d9, (q15_t)0xc399,
- (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70d3, (q15_t)0xc38e, (q15_t)0x70d1, (q15_t)0xc389, (q15_t)0x70ce, (q15_t)0xc383,
- (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70c8, (q15_t)0xc378, (q15_t)0x70c5, (q15_t)0xc372, (q15_t)0x70c2, (q15_t)0xc36d,
- (q15_t)0x70bf, (q15_t)0xc367, (q15_t)0x70bc, (q15_t)0xc362, (q15_t)0x70b9, (q15_t)0xc35c, (q15_t)0x70b6, (q15_t)0xc357,
- (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70b0, (q15_t)0xc34c, (q15_t)0x70ad, (q15_t)0xc346, (q15_t)0x70aa, (q15_t)0xc341,
- (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x70a4, (q15_t)0xc336, (q15_t)0x70a1, (q15_t)0xc330, (q15_t)0x709e, (q15_t)0xc32a,
- (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x7098, (q15_t)0xc31f, (q15_t)0x7095, (q15_t)0xc31a, (q15_t)0x7092, (q15_t)0xc314,
- (q15_t)0x708f, (q15_t)0xc30f, (q15_t)0x708c, (q15_t)0xc309, (q15_t)0x7089, (q15_t)0xc304, (q15_t)0x7086, (q15_t)0xc2fe,
- (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7080, (q15_t)0xc2f3, (q15_t)0x707d, (q15_t)0xc2ee, (q15_t)0x707a, (q15_t)0xc2e8,
- (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x7074, (q15_t)0xc2dd, (q15_t)0x7071, (q15_t)0xc2d8, (q15_t)0x706e, (q15_t)0xc2d2,
- (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x7068, (q15_t)0xc2c7, (q15_t)0x7065, (q15_t)0xc2c2, (q15_t)0x7062, (q15_t)0xc2bc,
- (q15_t)0x705f, (q15_t)0xc2b7, (q15_t)0x705c, (q15_t)0xc2b1, (q15_t)0x7059, (q15_t)0xc2ab, (q15_t)0x7056, (q15_t)0xc2a6,
- (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7050, (q15_t)0xc29b, (q15_t)0x704d, (q15_t)0xc295, (q15_t)0x704a, (q15_t)0xc290,
- (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x7044, (q15_t)0xc285, (q15_t)0x7041, (q15_t)0xc27f, (q15_t)0x703e, (q15_t)0xc27a,
- (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x7038, (q15_t)0xc26f, (q15_t)0x7035, (q15_t)0xc269, (q15_t)0x7032, (q15_t)0xc264,
- (q15_t)0x702f, (q15_t)0xc25e, (q15_t)0x702c, (q15_t)0xc259, (q15_t)0x7029, (q15_t)0xc253, (q15_t)0x7026, (q15_t)0xc24e,
- (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7020, (q15_t)0xc243, (q15_t)0x701d, (q15_t)0xc23d, (q15_t)0x7019, (q15_t)0xc238,
- (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x7013, (q15_t)0xc22d, (q15_t)0x7010, (q15_t)0xc227, (q15_t)0x700d, (q15_t)0xc222,
- (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x7007, (q15_t)0xc217, (q15_t)0x7004, (q15_t)0xc211, (q15_t)0x7001, (q15_t)0xc20c,
- (q15_t)0x6ffe, (q15_t)0xc206, (q15_t)0x6ffb, (q15_t)0xc201, (q15_t)0x6ff8, (q15_t)0xc1fb, (q15_t)0x6ff5, (q15_t)0xc1f6,
- (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fef, (q15_t)0xc1eb, (q15_t)0x6fec, (q15_t)0xc1e5, (q15_t)0x6fe9, (q15_t)0xc1e0,
- (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fe3, (q15_t)0xc1d5, (q15_t)0x6fe0, (q15_t)0xc1cf, (q15_t)0x6fdd, (q15_t)0xc1ca,
- (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fd6, (q15_t)0xc1bf, (q15_t)0x6fd3, (q15_t)0xc1b9, (q15_t)0x6fd0, (q15_t)0xc1b4,
- (q15_t)0x6fcd, (q15_t)0xc1ae, (q15_t)0x6fca, (q15_t)0xc1a9, (q15_t)0x6fc7, (q15_t)0xc1a3, (q15_t)0x6fc4, (q15_t)0xc19e,
- (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fbe, (q15_t)0xc193, (q15_t)0x6fbb, (q15_t)0xc18d, (q15_t)0x6fb8, (q15_t)0xc188,
- (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fb2, (q15_t)0xc17d, (q15_t)0x6faf, (q15_t)0xc178, (q15_t)0x6fac, (q15_t)0xc172,
- (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6fa5, (q15_t)0xc167, (q15_t)0x6fa2, (q15_t)0xc162, (q15_t)0x6f9f, (q15_t)0xc15c,
- (q15_t)0x6f9c, (q15_t)0xc157, (q15_t)0x6f99, (q15_t)0xc151, (q15_t)0x6f96, (q15_t)0xc14c, (q15_t)0x6f93, (q15_t)0xc146,
- (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f8d, (q15_t)0xc13b, (q15_t)0x6f8a, (q15_t)0xc136, (q15_t)0x6f87, (q15_t)0xc130,
- (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f81, (q15_t)0xc125, (q15_t)0x6f7d, (q15_t)0xc120, (q15_t)0x6f7a, (q15_t)0xc11a,
- (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f74, (q15_t)0xc10f, (q15_t)0x6f71, (q15_t)0xc10a, (q15_t)0x6f6e, (q15_t)0xc105,
- (q15_t)0x6f6b, (q15_t)0xc0ff, (q15_t)0x6f68, (q15_t)0xc0fa, (q15_t)0x6f65, (q15_t)0xc0f4, (q15_t)0x6f62, (q15_t)0xc0ef,
- (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f5b, (q15_t)0xc0e4, (q15_t)0x6f58, (q15_t)0xc0de, (q15_t)0x6f55, (q15_t)0xc0d9,
- (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f4f, (q15_t)0xc0ce, (q15_t)0x6f4c, (q15_t)0xc0c8, (q15_t)0x6f49, (q15_t)0xc0c3,
- (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f43, (q15_t)0xc0b8, (q15_t)0x6f3f, (q15_t)0xc0b3, (q15_t)0x6f3c, (q15_t)0xc0ad,
- (q15_t)0x6f39, (q15_t)0xc0a8, (q15_t)0x6f36, (q15_t)0xc0a2, (q15_t)0x6f33, (q15_t)0xc09d, (q15_t)0x6f30, (q15_t)0xc097,
- (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f2a, (q15_t)0xc08c, (q15_t)0x6f27, (q15_t)0xc087, (q15_t)0x6f23, (q15_t)0xc081,
- (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f1d, (q15_t)0xc077, (q15_t)0x6f1a, (q15_t)0xc071, (q15_t)0x6f17, (q15_t)0xc06c,
- (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f11, (q15_t)0xc061, (q15_t)0x6f0e, (q15_t)0xc05b, (q15_t)0x6f0b, (q15_t)0xc056,
- (q15_t)0x6f07, (q15_t)0xc050, (q15_t)0x6f04, (q15_t)0xc04b, (q15_t)0x6f01, (q15_t)0xc045, (q15_t)0x6efe, (q15_t)0xc040,
- (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ef8, (q15_t)0xc035, (q15_t)0x6ef5, (q15_t)0xc030, (q15_t)0x6ef1, (q15_t)0xc02a,
- (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6eeb, (q15_t)0xc01f, (q15_t)0x6ee8, (q15_t)0xc01a, (q15_t)0x6ee5, (q15_t)0xc014,
- (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6edf, (q15_t)0xc00a, (q15_t)0x6edc, (q15_t)0xc004, (q15_t)0x6ed8, (q15_t)0xbfff,
- (q15_t)0x6ed5, (q15_t)0xbff9, (q15_t)0x6ed2, (q15_t)0xbff4, (q15_t)0x6ecf, (q15_t)0xbfee, (q15_t)0x6ecc, (q15_t)0xbfe9,
- (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ec6, (q15_t)0xbfde, (q15_t)0x6ec2, (q15_t)0xbfd9, (q15_t)0x6ebf, (q15_t)0xbfd3,
- (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eb9, (q15_t)0xbfc8, (q15_t)0x6eb6, (q15_t)0xbfc3, (q15_t)0x6eb3, (q15_t)0xbfbd,
- (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6eac, (q15_t)0xbfb3, (q15_t)0x6ea9, (q15_t)0xbfad, (q15_t)0x6ea6, (q15_t)0xbfa8,
- (q15_t)0x6ea3, (q15_t)0xbfa2, (q15_t)0x6ea0, (q15_t)0xbf9d, (q15_t)0x6e9c, (q15_t)0xbf97, (q15_t)0x6e99, (q15_t)0xbf92,
- (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e93, (q15_t)0xbf87, (q15_t)0x6e90, (q15_t)0xbf82, (q15_t)0x6e8d, (q15_t)0xbf7c,
- (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e86, (q15_t)0xbf71, (q15_t)0x6e83, (q15_t)0xbf6c, (q15_t)0x6e80, (q15_t)0xbf67,
- (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e7a, (q15_t)0xbf5c, (q15_t)0x6e76, (q15_t)0xbf56, (q15_t)0x6e73, (q15_t)0xbf51,
- (q15_t)0x6e70, (q15_t)0xbf4b, (q15_t)0x6e6d, (q15_t)0xbf46, (q15_t)0x6e6a, (q15_t)0xbf41, (q15_t)0x6e67, (q15_t)0xbf3b,
- (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e60, (q15_t)0xbf30, (q15_t)0x6e5d, (q15_t)0xbf2b, (q15_t)0x6e5a, (q15_t)0xbf26,
- (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e53, (q15_t)0xbf1b, (q15_t)0x6e50, (q15_t)0xbf15, (q15_t)0x6e4d, (q15_t)0xbf10,
- (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e47, (q15_t)0xbf05, (q15_t)0x6e44, (q15_t)0xbf00, (q15_t)0x6e40, (q15_t)0xbefa,
- (q15_t)0x6e3d, (q15_t)0xbef5, (q15_t)0x6e3a, (q15_t)0xbeef, (q15_t)0x6e37, (q15_t)0xbeea, (q15_t)0x6e34, (q15_t)0xbee5,
- (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e2d, (q15_t)0xbeda, (q15_t)0x6e2a, (q15_t)0xbed4, (q15_t)0x6e27, (q15_t)0xbecf,
- (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e20, (q15_t)0xbec4, (q15_t)0x6e1d, (q15_t)0xbebf, (q15_t)0x6e1a, (q15_t)0xbeb9,
- (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e14, (q15_t)0xbeae, (q15_t)0x6e10, (q15_t)0xbea9, (q15_t)0x6e0d, (q15_t)0xbea4,
- (q15_t)0x6e0a, (q15_t)0xbe9e, (q15_t)0x6e07, (q15_t)0xbe99, (q15_t)0x6e04, (q15_t)0xbe93, (q15_t)0x6e00, (q15_t)0xbe8e,
- (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6dfa, (q15_t)0xbe83, (q15_t)0x6df7, (q15_t)0xbe7e, (q15_t)0x6df3, (q15_t)0xbe78,
- (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6ded, (q15_t)0xbe6e, (q15_t)0x6dea, (q15_t)0xbe68, (q15_t)0x6de7, (q15_t)0xbe63,
- (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6de0, (q15_t)0xbe58, (q15_t)0x6ddd, (q15_t)0xbe53, (q15_t)0x6dda, (q15_t)0xbe4d,
- (q15_t)0x6dd6, (q15_t)0xbe48, (q15_t)0x6dd3, (q15_t)0xbe43, (q15_t)0x6dd0, (q15_t)0xbe3d, (q15_t)0x6dcd, (q15_t)0xbe38,
- (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dc6, (q15_t)0xbe2d, (q15_t)0x6dc3, (q15_t)0xbe28, (q15_t)0x6dc0, (q15_t)0xbe22,
- (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db9, (q15_t)0xbe17, (q15_t)0x6db6, (q15_t)0xbe12, (q15_t)0x6db3, (q15_t)0xbe0d,
- (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6dac, (q15_t)0xbe02, (q15_t)0x6da9, (q15_t)0xbdfd, (q15_t)0x6da6, (q15_t)0xbdf7,
- (q15_t)0x6da3, (q15_t)0xbdf2, (q15_t)0x6d9f, (q15_t)0xbdec, (q15_t)0x6d9c, (q15_t)0xbde7, (q15_t)0x6d99, (q15_t)0xbde2,
- (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d92, (q15_t)0xbdd7, (q15_t)0x6d8f, (q15_t)0xbdd1, (q15_t)0x6d8c, (q15_t)0xbdcc,
- (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d85, (q15_t)0xbdc1, (q15_t)0x6d82, (q15_t)0xbdbc, (q15_t)0x6d7f, (q15_t)0xbdb7,
- (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d78, (q15_t)0xbdac, (q15_t)0x6d75, (q15_t)0xbda6, (q15_t)0x6d72, (q15_t)0xbda1,
- (q15_t)0x6d6f, (q15_t)0xbd9c, (q15_t)0x6d6b, (q15_t)0xbd96, (q15_t)0x6d68, (q15_t)0xbd91, (q15_t)0x6d65, (q15_t)0xbd8c,
- (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d5e, (q15_t)0xbd81, (q15_t)0x6d5b, (q15_t)0xbd7c, (q15_t)0x6d58, (q15_t)0xbd76,
- (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d51, (q15_t)0xbd6b, (q15_t)0x6d4e, (q15_t)0xbd66, (q15_t)0x6d4b, (q15_t)0xbd61,
- (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d44, (q15_t)0xbd56, (q15_t)0x6d41, (q15_t)0xbd51, (q15_t)0x6d3e, (q15_t)0xbd4b,
- (q15_t)0x6d3a, (q15_t)0xbd46, (q15_t)0x6d37, (q15_t)0xbd40, (q15_t)0x6d34, (q15_t)0xbd3b, (q15_t)0x6d31, (q15_t)0xbd36,
- (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d2a, (q15_t)0xbd2b, (q15_t)0x6d27, (q15_t)0xbd26, (q15_t)0x6d23, (q15_t)0xbd20,
- (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d1d, (q15_t)0xbd16, (q15_t)0x6d1a, (q15_t)0xbd10, (q15_t)0x6d16, (q15_t)0xbd0b,
- (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d10, (q15_t)0xbd00, (q15_t)0x6d0c, (q15_t)0xbcfb, (q15_t)0x6d09, (q15_t)0xbcf5,
- (q15_t)0x6d06, (q15_t)0xbcf0, (q15_t)0x6d03, (q15_t)0xbceb, (q15_t)0x6cff, (q15_t)0xbce5, (q15_t)0x6cfc, (q15_t)0xbce0,
- (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cf5, (q15_t)0xbcd5, (q15_t)0x6cf2, (q15_t)0xbcd0, (q15_t)0x6cef, (q15_t)0xbccb,
- (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6ce8, (q15_t)0xbcc0, (q15_t)0x6ce5, (q15_t)0xbcbb, (q15_t)0x6ce2, (q15_t)0xbcb5,
- (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cdb, (q15_t)0xbcab, (q15_t)0x6cd8, (q15_t)0xbca5, (q15_t)0x6cd4, (q15_t)0xbca0,
- (q15_t)0x6cd1, (q15_t)0xbc9b, (q15_t)0x6cce, (q15_t)0xbc95, (q15_t)0x6cca, (q15_t)0xbc90, (q15_t)0x6cc7, (q15_t)0xbc8b,
- (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cc1, (q15_t)0xbc80, (q15_t)0x6cbd, (q15_t)0xbc7b, (q15_t)0x6cba, (q15_t)0xbc75,
- (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6cb3, (q15_t)0xbc6b, (q15_t)0x6cb0, (q15_t)0xbc65, (q15_t)0x6cad, (q15_t)0xbc60,
- (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6ca6, (q15_t)0xbc55, (q15_t)0x6ca3, (q15_t)0xbc50, (q15_t)0x6c9f, (q15_t)0xbc4b,
- (q15_t)0x6c9c, (q15_t)0xbc45, (q15_t)0x6c99, (q15_t)0xbc40, (q15_t)0x6c95, (q15_t)0xbc3b, (q15_t)0x6c92, (q15_t)0xbc35,
- (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c8b, (q15_t)0xbc2b, (q15_t)0x6c88, (q15_t)0xbc25, (q15_t)0x6c85, (q15_t)0xbc20,
- (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c7e, (q15_t)0xbc15, (q15_t)0x6c7b, (q15_t)0xbc10, (q15_t)0x6c77, (q15_t)0xbc0b,
- (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c71, (q15_t)0xbc00, (q15_t)0x6c6d, (q15_t)0xbbfb, (q15_t)0x6c6a, (q15_t)0xbbf5,
- (q15_t)0x6c67, (q15_t)0xbbf0, (q15_t)0x6c63, (q15_t)0xbbeb, (q15_t)0x6c60, (q15_t)0xbbe5, (q15_t)0x6c5d, (q15_t)0xbbe0,
- (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c56, (q15_t)0xbbd5, (q15_t)0x6c53, (q15_t)0xbbd0, (q15_t)0x6c4f, (q15_t)0xbbcb,
- (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c49, (q15_t)0xbbc0, (q15_t)0x6c45, (q15_t)0xbbbb, (q15_t)0x6c42, (q15_t)0xbbb5,
- (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c3b, (q15_t)0xbbab, (q15_t)0x6c38, (q15_t)0xbba6, (q15_t)0x6c34, (q15_t)0xbba0,
- (q15_t)0x6c31, (q15_t)0xbb9b, (q15_t)0x6c2e, (q15_t)0xbb96, (q15_t)0x6c2a, (q15_t)0xbb90, (q15_t)0x6c27, (q15_t)0xbb8b,
- (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c20, (q15_t)0xbb80, (q15_t)0x6c1d, (q15_t)0xbb7b, (q15_t)0x6c1a, (q15_t)0xbb76,
- (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c13, (q15_t)0xbb6b, (q15_t)0x6c0f, (q15_t)0xbb66, (q15_t)0x6c0c, (q15_t)0xbb61,
- (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6c05, (q15_t)0xbb56, (q15_t)0x6c02, (q15_t)0xbb51, (q15_t)0x6bff, (q15_t)0xbb4b,
- (q15_t)0x6bfb, (q15_t)0xbb46, (q15_t)0x6bf8, (q15_t)0xbb41, (q15_t)0x6bf5, (q15_t)0xbb3b, (q15_t)0x6bf1, (q15_t)0xbb36,
- (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bea, (q15_t)0xbb2c, (q15_t)0x6be7, (q15_t)0xbb26, (q15_t)0x6be4, (q15_t)0xbb21,
- (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bdd, (q15_t)0xbb16, (q15_t)0x6bd9, (q15_t)0xbb11, (q15_t)0x6bd6, (q15_t)0xbb0c,
- (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bcf, (q15_t)0xbb01, (q15_t)0x6bcc, (q15_t)0xbafc, (q15_t)0x6bc9, (q15_t)0xbaf7,
- (q15_t)0x6bc5, (q15_t)0xbaf1, (q15_t)0x6bc2, (q15_t)0xbaec, (q15_t)0x6bbe, (q15_t)0xbae7, (q15_t)0x6bbb, (q15_t)0xbae1,
- (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6bb4, (q15_t)0xbad7, (q15_t)0x6bb1, (q15_t)0xbad2, (q15_t)0x6bad, (q15_t)0xbacc,
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- (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1499, (q15_t)0x81ac, (q15_t)0x1493, (q15_t)0x81ab, (q15_t)0x148d, (q15_t)0x81aa,
- (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x1480, (q15_t)0x81a8, (q15_t)0x147a, (q15_t)0x81a7, (q15_t)0x1474, (q15_t)0x81a6,
- (q15_t)0x146e, (q15_t)0x81a5, (q15_t)0x1468, (q15_t)0x81a4, (q15_t)0x1461, (q15_t)0x81a3, (q15_t)0x145b, (q15_t)0x81a2,
- (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x144f, (q15_t)0x81a0, (q15_t)0x1449, (q15_t)0x819f, (q15_t)0x1442, (q15_t)0x819e,
- (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1436, (q15_t)0x819c, (q15_t)0x1430, (q15_t)0x819b, (q15_t)0x142a, (q15_t)0x819a,
- (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x141d, (q15_t)0x8198, (q15_t)0x1417, (q15_t)0x8197, (q15_t)0x1411, (q15_t)0x8196,
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- (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13eb, (q15_t)0x8190, (q15_t)0x13e5, (q15_t)0x818f, (q15_t)0x13df, (q15_t)0x818e,
- (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13d3, (q15_t)0x818c, (q15_t)0x13cc, (q15_t)0x818b, (q15_t)0x13c6, (q15_t)0x818a,
- (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13ba, (q15_t)0x8188, (q15_t)0x13b4, (q15_t)0x8187, (q15_t)0x13ad, (q15_t)0x8186,
- (q15_t)0x13a7, (q15_t)0x8185, (q15_t)0x13a1, (q15_t)0x8184, (q15_t)0x139b, (q15_t)0x8183, (q15_t)0x1395, (q15_t)0x8182,
- (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1388, (q15_t)0x8180, (q15_t)0x1382, (q15_t)0x817f, (q15_t)0x137c, (q15_t)0x817e,
- (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x136f, (q15_t)0x817c, (q15_t)0x1369, (q15_t)0x817c, (q15_t)0x1363, (q15_t)0x817b,
- (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1356, (q15_t)0x8179, (q15_t)0x1350, (q15_t)0x8178, (q15_t)0x134a, (q15_t)0x8177,
- (q15_t)0x1344, (q15_t)0x8176, (q15_t)0x133e, (q15_t)0x8175, (q15_t)0x1337, (q15_t)0x8174, (q15_t)0x1331, (q15_t)0x8173,
- (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1325, (q15_t)0x8171, (q15_t)0x131f, (q15_t)0x8170, (q15_t)0x1318, (q15_t)0x816f,
- (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x130c, (q15_t)0x816d, (q15_t)0x1306, (q15_t)0x816c, (q15_t)0x12ff, (q15_t)0x816c,
- (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12f3, (q15_t)0x816a, (q15_t)0x12ed, (q15_t)0x8169, (q15_t)0x12e7, (q15_t)0x8168,
- (q15_t)0x12e0, (q15_t)0x8167, (q15_t)0x12da, (q15_t)0x8166, (q15_t)0x12d4, (q15_t)0x8165, (q15_t)0x12ce, (q15_t)0x8164,
- (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12c1, (q15_t)0x8162, (q15_t)0x12bb, (q15_t)0x8161, (q15_t)0x12b5, (q15_t)0x8160,
- (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x12a8, (q15_t)0x815f, (q15_t)0x12a2, (q15_t)0x815e, (q15_t)0x129c, (q15_t)0x815d,
- (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x1290, (q15_t)0x815b, (q15_t)0x1289, (q15_t)0x815a, (q15_t)0x1283, (q15_t)0x8159,
- (q15_t)0x127d, (q15_t)0x8158, (q15_t)0x1277, (q15_t)0x8157, (q15_t)0x1271, (q15_t)0x8156, (q15_t)0x126a, (q15_t)0x8155,
- (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x125e, (q15_t)0x8154, (q15_t)0x1258, (q15_t)0x8153, (q15_t)0x1251, (q15_t)0x8152,
- (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1245, (q15_t)0x8150, (q15_t)0x123f, (q15_t)0x814f, (q15_t)0x1239, (q15_t)0x814e,
- (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x122c, (q15_t)0x814c, (q15_t)0x1226, (q15_t)0x814c, (q15_t)0x1220, (q15_t)0x814b,
- (q15_t)0x1219, (q15_t)0x814a, (q15_t)0x1213, (q15_t)0x8149, (q15_t)0x120d, (q15_t)0x8148, (q15_t)0x1207, (q15_t)0x8147,
- (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11fa, (q15_t)0x8145, (q15_t)0x11f4, (q15_t)0x8145, (q15_t)0x11ee, (q15_t)0x8144,
- (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11e1, (q15_t)0x8142, (q15_t)0x11db, (q15_t)0x8141, (q15_t)0x11d5, (q15_t)0x8140,
- (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11c9, (q15_t)0x813e, (q15_t)0x11c2, (q15_t)0x813d, (q15_t)0x11bc, (q15_t)0x813d,
- (q15_t)0x11b6, (q15_t)0x813c, (q15_t)0x11b0, (q15_t)0x813b, (q15_t)0x11a9, (q15_t)0x813a, (q15_t)0x11a3, (q15_t)0x8139,
- (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1197, (q15_t)0x8137, (q15_t)0x1191, (q15_t)0x8137, (q15_t)0x118a, (q15_t)0x8136,
- (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x117e, (q15_t)0x8134, (q15_t)0x1178, (q15_t)0x8133, (q15_t)0x1171, (q15_t)0x8132,
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- (q15_t)0x1152, (q15_t)0x812e, (q15_t)0x114c, (q15_t)0x812d, (q15_t)0x1146, (q15_t)0x812c, (q15_t)0x1140, (q15_t)0x812b,
- (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1133, (q15_t)0x812a, (q15_t)0x112d, (q15_t)0x8129, (q15_t)0x1127, (q15_t)0x8128,
- (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x111a, (q15_t)0x8126, (q15_t)0x1114, (q15_t)0x8126, (q15_t)0x110e, (q15_t)0x8125,
- (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x1101, (q15_t)0x8123, (q15_t)0x10fb, (q15_t)0x8122, (q15_t)0x10f5, (q15_t)0x8121,
- (q15_t)0x10ef, (q15_t)0x8121, (q15_t)0x10e8, (q15_t)0x8120, (q15_t)0x10e2, (q15_t)0x811f, (q15_t)0x10dc, (q15_t)0x811e,
- (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10d0, (q15_t)0x811c, (q15_t)0x10c9, (q15_t)0x811c, (q15_t)0x10c3, (q15_t)0x811b,
- (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10b7, (q15_t)0x8119, (q15_t)0x10b0, (q15_t)0x8118, (q15_t)0x10aa, (q15_t)0x8117,
- (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x109e, (q15_t)0x8116, (q15_t)0x1098, (q15_t)0x8115, (q15_t)0x1091, (q15_t)0x8114,
- (q15_t)0x108b, (q15_t)0x8113, (q15_t)0x1085, (q15_t)0x8113, (q15_t)0x107f, (q15_t)0x8112, (q15_t)0x1078, (q15_t)0x8111,
- (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x106c, (q15_t)0x810f, (q15_t)0x1066, (q15_t)0x810f, (q15_t)0x105f, (q15_t)0x810e,
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- (q15_t)0x1027, (q15_t)0x8107, (q15_t)0x1021, (q15_t)0x8106, (q15_t)0x101b, (q15_t)0x8105, (q15_t)0x1015, (q15_t)0x8104,
- (q15_t)0x100e, (q15_t)0x8103, (q15_t)0x1008, (q15_t)0x8103, (q15_t)0x1002, (q15_t)0x8102, (q15_t)0xffc, (q15_t)0x8101,
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- (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xce9, (q15_t)0x80a8, (q15_t)0xce3, (q15_t)0x80a7, (q15_t)0xcdd, (q15_t)0x80a6,
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- (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xcb7, (q15_t)0x80a3, (q15_t)0xcb1, (q15_t)0x80a2, (q15_t)0xcab, (q15_t)0x80a1,
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- (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc6c, (q15_t)0x809b, (q15_t)0xc66, (q15_t)0x809b, (q15_t)0xc60, (q15_t)0x809a,
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- (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xc08, (q15_t)0x8092, (q15_t)0xc02, (q15_t)0x8091, (q15_t)0xbfb, (q15_t)0x8090,
- (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbef, (q15_t)0x808f, (q15_t)0xbe9, (q15_t)0x808f, (q15_t)0xbe2, (q15_t)0x808e,
- (q15_t)0xbdc, (q15_t)0x808e, (q15_t)0xbd6, (q15_t)0x808d, (q15_t)0xbd0, (q15_t)0x808c, (q15_t)0xbc9, (q15_t)0x808c,
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- (q15_t)0xb78, (q15_t)0x8084, (q15_t)0xb72, (q15_t)0x8084, (q15_t)0xb6c, (q15_t)0x8083, (q15_t)0xb65, (q15_t)0x8083,
- (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb59, (q15_t)0x8082, (q15_t)0xb53, (q15_t)0x8081, (q15_t)0xb4c, (q15_t)0x8080,
- (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb40, (q15_t)0x807f, (q15_t)0xb3a, (q15_t)0x807f, (q15_t)0xb33, (q15_t)0x807e,
- (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb27, (q15_t)0x807d, (q15_t)0xb20, (q15_t)0x807d, (q15_t)0xb1a, (q15_t)0x807c,
- (q15_t)0xb14, (q15_t)0x807b, (q15_t)0xb0e, (q15_t)0x807b, (q15_t)0xb07, (q15_t)0x807a, (q15_t)0xb01, (q15_t)0x807a,
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- (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xac3, (q15_t)0x8075, (q15_t)0xabc, (q15_t)0x8074, (q15_t)0xab6, (q15_t)0x8073,
- (q15_t)0xab0, (q15_t)0x8073, (q15_t)0xaaa, (q15_t)0x8072, (q15_t)0xaa3, (q15_t)0x8072, (q15_t)0xa9d, (q15_t)0x8071,
- (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa90, (q15_t)0x8070, (q15_t)0xa8a, (q15_t)0x8070, (q15_t)0xa84, (q15_t)0x806f,
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- (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa5e, (q15_t)0x806c, (q15_t)0xa58, (q15_t)0x806c, (q15_t)0xa52, (q15_t)0x806b,
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- (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa2c, (q15_t)0x8068, (q15_t)0xa26, (q15_t)0x8068, (q15_t)0xa20, (q15_t)0x8067,
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- (q15_t)0x9e7, (q15_t)0x8063, (q15_t)0x9e1, (q15_t)0x8062, (q15_t)0x9db, (q15_t)0x8062, (q15_t)0x9d5, (q15_t)0x8061,
- (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9c8, (q15_t)0x8060, (q15_t)0x9c2, (q15_t)0x8060, (q15_t)0x9bc, (q15_t)0x805f,
- (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x9af, (q15_t)0x805e, (q15_t)0x9a9, (q15_t)0x805e, (q15_t)0x9a2, (q15_t)0x805d,
- (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x996, (q15_t)0x805d, (q15_t)0x990, (q15_t)0x805c, (q15_t)0x989, (q15_t)0x805c,
- (q15_t)0x983, (q15_t)0x805b, (q15_t)0x97d, (q15_t)0x805b, (q15_t)0x977, (q15_t)0x805a, (q15_t)0x970, (q15_t)0x805a,
- (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x964, (q15_t)0x8059, (q15_t)0x95e, (q15_t)0x8058, (q15_t)0x957, (q15_t)0x8058,
- (q15_t)0x951, (q15_t)0x8057, (q15_t)0x94b, (q15_t)0x8057, (q15_t)0x944, (q15_t)0x8057, (q15_t)0x93e, (q15_t)0x8056,
- (q15_t)0x938, (q15_t)0x8056, (q15_t)0x932, (q15_t)0x8055, (q15_t)0x92b, (q15_t)0x8055, (q15_t)0x925, (q15_t)0x8054,
- (q15_t)0x91f, (q15_t)0x8054, (q15_t)0x919, (q15_t)0x8053, (q15_t)0x912, (q15_t)0x8053, (q15_t)0x90c, (q15_t)0x8052,
- (q15_t)0x906, (q15_t)0x8052, (q15_t)0x900, (q15_t)0x8052, (q15_t)0x8f9, (q15_t)0x8051, (q15_t)0x8f3, (q15_t)0x8051,
- (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8e6, (q15_t)0x8050, (q15_t)0x8e0, (q15_t)0x804f, (q15_t)0x8da, (q15_t)0x804f,
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- (q15_t)0x8bb, (q15_t)0x804d, (q15_t)0x8b4, (q15_t)0x804c, (q15_t)0x8ae, (q15_t)0x804c, (q15_t)0x8a8, (q15_t)0x804c,
- (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x89b, (q15_t)0x804b, (q15_t)0x895, (q15_t)0x804a, (q15_t)0x88f, (q15_t)0x804a,
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- (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x869, (q15_t)0x8047, (q15_t)0x863, (q15_t)0x8047, (q15_t)0x85d, (q15_t)0x8047,
- (q15_t)0x856, (q15_t)0x8046, (q15_t)0x850, (q15_t)0x8046, (q15_t)0x84a, (q15_t)0x8045, (q15_t)0x843, (q15_t)0x8045,
- (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x837, (q15_t)0x8044, (q15_t)0x831, (q15_t)0x8044, (q15_t)0x82a, (q15_t)0x8043,
- (q15_t)0x824, (q15_t)0x8043, (q15_t)0x81e, (q15_t)0x8042, (q15_t)0x818, (q15_t)0x8042, (q15_t)0x811, (q15_t)0x8042,
- (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x805, (q15_t)0x8041, (q15_t)0x7fe, (q15_t)0x8040, (q15_t)0x7f8, (q15_t)0x8040,
- (q15_t)0x7f2, (q15_t)0x8040, (q15_t)0x7ec, (q15_t)0x803f, (q15_t)0x7e5, (q15_t)0x803f, (q15_t)0x7df, (q15_t)0x803f,
- (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7d3, (q15_t)0x803e, (q15_t)0x7cc, (q15_t)0x803d, (q15_t)0x7c6, (q15_t)0x803d,
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- (q15_t)0x775, (q15_t)0x8038, (q15_t)0x76e, (q15_t)0x8038, (q15_t)0x768, (q15_t)0x8037, (q15_t)0x762, (q15_t)0x8037,
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- (q15_t)0x710, (q15_t)0x8032, (q15_t)0x70a, (q15_t)0x8032, (q15_t)0x704, (q15_t)0x8032, (q15_t)0x6fd, (q15_t)0x8031,
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- (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6d8, (q15_t)0x802f, (q15_t)0x6d1, (q15_t)0x802f, (q15_t)0x6cb, (q15_t)0x802f,
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- (q15_t)0x406, (q15_t)0x8011, (q15_t)0x3ff, (q15_t)0x8011, (q15_t)0x3f9, (q15_t)0x8010, (q15_t)0x3f3, (q15_t)0x8010,
- (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3e6, (q15_t)0x8010, (q15_t)0x3e0, (q15_t)0x8010, (q15_t)0x3da, (q15_t)0x800f,
- (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3cd, (q15_t)0x800f, (q15_t)0x3c7, (q15_t)0x800f, (q15_t)0x3c1, (q15_t)0x800f,
- (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3b4, (q15_t)0x800e, (q15_t)0x3ae, (q15_t)0x800e, (q15_t)0x3a8, (q15_t)0x800e,
- (q15_t)0x3a1, (q15_t)0x800e, (q15_t)0x39b, (q15_t)0x800e, (q15_t)0x395, (q15_t)0x800d, (q15_t)0x38e, (q15_t)0x800d,
- (q15_t)0x388, (q15_t)0x800d, (q15_t)0x382, (q15_t)0x800d, (q15_t)0x37c, (q15_t)0x800d, (q15_t)0x375, (q15_t)0x800c,
- (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x369, (q15_t)0x800c, (q15_t)0x362, (q15_t)0x800c, (q15_t)0x35c, (q15_t)0x800c,
- (q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b,
- (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b,
- (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a,
- (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009,
- (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009,
- (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008,
- (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008,
- (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007,
- (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007,
- (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006,
- (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006,
- (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005,
- (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005,
- (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004,
- (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004,
- (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004,
- (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003,
- (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003,
- (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003,
- (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002,
- (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002,
- (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002,
- (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002,
- (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002,
- (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001,
- (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001,
- (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001,
- (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001,
- (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001,
- (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001,
- (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001,
- (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001,
- (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001,
- (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001
-};
-
-
-/**
-* \par
-* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
-* \par
-* C command to generate the table
-*
-* for(i = 0; i< N; i++)
-* {
-* cos_factors[i]= 2 * cos((2*i+1)*c/2);
-* }
-* \par
-* where N is the number of factors to generate and c is pi/(2*N)
-* \par
-* Then converted to q15 format by multiplying with 2^31 and saturated if required.
-
-*/
-
-static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
- (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75,
- (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0,
- (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6,
- (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e,
- (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141,
- (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc,
- (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371,
- (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10,
- (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce,
- (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3,
- (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07,
- (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5,
- (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8,
- (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd,
- (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53,
- (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7,
- (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda,
- (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa,
- (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67,
- (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f,
- (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4,
- (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26,
- (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94,
- (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee,
- (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36,
- (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a,
- (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b,
- (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999,
- (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895,
- (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e,
- (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654,
- (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519,
- (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb,
- (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b,
- (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa,
- (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77,
- (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3,
- (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f,
- (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89,
- (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3,
- (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed,
- (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507,
- (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311,
- (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d,
- (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9,
- (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6,
- (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5,
- (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867,
- (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a,
- (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1,
- (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a,
- (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7,
- (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68,
- (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd,
- (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746,
- (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5,
- (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9,
- (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43,
- (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83,
- (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9,
- (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7,
- (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c,
- (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a,
- (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f,
- (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e,
- (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856,
- (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558,
- (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254,
- (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a,
- (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c,
- (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a,
- (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613,
- (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9,
- (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd,
- (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd,
- (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c,
- (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a,
- (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356,
- (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd,
- (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa,
- (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6,
- (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0,
- (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea,
- (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2,
- (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9,
- (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce,
- (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3,
- (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6,
- (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8,
- (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98,
- (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88,
- (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76,
- (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63,
- (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f,
- (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39,
- (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23,
- (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b,
- (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1,
- (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7,
- (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb,
- (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f,
- (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81,
- (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61,
- (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41,
- (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f,
- (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc,
- (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8,
- (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3,
- (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c,
- (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65,
- (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c,
- (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11,
- (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6,
- (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9,
- (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c,
- (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d,
- (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d,
- (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb,
- (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9,
- (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95,
- (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60,
- (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a,
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- (q15_t)0x245b, (q15_t)0x2443, (q15_t)0x242b, (q15_t)0x2413, (q15_t)0x23fa, (q15_t)0x23e2, (q15_t)0x23ca, (q15_t)0x23b2,
- (q15_t)0x239a, (q15_t)0x2382, (q15_t)0x236a, (q15_t)0x2352, (q15_t)0x2339, (q15_t)0x2321, (q15_t)0x2309, (q15_t)0x22f1,
- (q15_t)0x22d9, (q15_t)0x22c0, (q15_t)0x22a8, (q15_t)0x2290, (q15_t)0x2278, (q15_t)0x2260, (q15_t)0x2247, (q15_t)0x222f,
- (q15_t)0x2217, (q15_t)0x21ff, (q15_t)0x21e7, (q15_t)0x21ce, (q15_t)0x21b6, (q15_t)0x219e, (q15_t)0x2186, (q15_t)0x216d,
- (q15_t)0x2155, (q15_t)0x213d, (q15_t)0x2125, (q15_t)0x210c, (q15_t)0x20f4, (q15_t)0x20dc, (q15_t)0x20c3, (q15_t)0x20ab,
- (q15_t)0x2093, (q15_t)0x207a, (q15_t)0x2062, (q15_t)0x204a, (q15_t)0x2032, (q15_t)0x2019, (q15_t)0x2001, (q15_t)0x1fe9,
- (q15_t)0x1fd0, (q15_t)0x1fb8, (q15_t)0x1f9f, (q15_t)0x1f87, (q15_t)0x1f6f, (q15_t)0x1f56, (q15_t)0x1f3e, (q15_t)0x1f26,
- (q15_t)0x1f0d, (q15_t)0x1ef5, (q15_t)0x1edd, (q15_t)0x1ec4, (q15_t)0x1eac, (q15_t)0x1e93, (q15_t)0x1e7b, (q15_t)0x1e62,
- (q15_t)0x1e4a, (q15_t)0x1e32, (q15_t)0x1e19, (q15_t)0x1e01, (q15_t)0x1de8, (q15_t)0x1dd0, (q15_t)0x1db7, (q15_t)0x1d9f,
- (q15_t)0x1d87, (q15_t)0x1d6e, (q15_t)0x1d56, (q15_t)0x1d3d, (q15_t)0x1d25, (q15_t)0x1d0c, (q15_t)0x1cf4, (q15_t)0x1cdb,
- (q15_t)0x1cc3, (q15_t)0x1caa, (q15_t)0x1c92, (q15_t)0x1c79, (q15_t)0x1c61, (q15_t)0x1c48, (q15_t)0x1c30, (q15_t)0x1c17,
- (q15_t)0x1bff, (q15_t)0x1be6, (q15_t)0x1bce, (q15_t)0x1bb5, (q15_t)0x1b9d, (q15_t)0x1b84, (q15_t)0x1b6c, (q15_t)0x1b53,
- (q15_t)0x1b3a, (q15_t)0x1b22, (q15_t)0x1b09, (q15_t)0x1af1, (q15_t)0x1ad8, (q15_t)0x1ac0, (q15_t)0x1aa7, (q15_t)0x1a8e,
- (q15_t)0x1a76, (q15_t)0x1a5d, (q15_t)0x1a45, (q15_t)0x1a2c, (q15_t)0x1a13, (q15_t)0x19fb, (q15_t)0x19e2, (q15_t)0x19ca,
- (q15_t)0x19b1, (q15_t)0x1998, (q15_t)0x1980, (q15_t)0x1967, (q15_t)0x194e, (q15_t)0x1936, (q15_t)0x191d, (q15_t)0x1905,
- (q15_t)0x18ec, (q15_t)0x18d3, (q15_t)0x18bb, (q15_t)0x18a2, (q15_t)0x1889, (q15_t)0x1871, (q15_t)0x1858, (q15_t)0x183f,
- (q15_t)0x1827, (q15_t)0x180e, (q15_t)0x17f5, (q15_t)0x17dd, (q15_t)0x17c4, (q15_t)0x17ab, (q15_t)0x1792, (q15_t)0x177a,
- (q15_t)0x1761, (q15_t)0x1748, (q15_t)0x1730, (q15_t)0x1717, (q15_t)0x16fe, (q15_t)0x16e5, (q15_t)0x16cd, (q15_t)0x16b4,
- (q15_t)0x169b, (q15_t)0x1682, (q15_t)0x166a, (q15_t)0x1651, (q15_t)0x1638, (q15_t)0x161f, (q15_t)0x1607, (q15_t)0x15ee,
- (q15_t)0x15d5, (q15_t)0x15bc, (q15_t)0x15a4, (q15_t)0x158b, (q15_t)0x1572, (q15_t)0x1559, (q15_t)0x1541, (q15_t)0x1528,
- (q15_t)0x150f, (q15_t)0x14f6, (q15_t)0x14dd, (q15_t)0x14c5, (q15_t)0x14ac, (q15_t)0x1493, (q15_t)0x147a, (q15_t)0x1461,
- (q15_t)0x1449, (q15_t)0x1430, (q15_t)0x1417, (q15_t)0x13fe, (q15_t)0x13e5, (q15_t)0x13cc, (q15_t)0x13b4, (q15_t)0x139b,
- (q15_t)0x1382, (q15_t)0x1369, (q15_t)0x1350, (q15_t)0x1337, (q15_t)0x131f, (q15_t)0x1306, (q15_t)0x12ed, (q15_t)0x12d4,
- (q15_t)0x12bb, (q15_t)0x12a2, (q15_t)0x1289, (q15_t)0x1271, (q15_t)0x1258, (q15_t)0x123f, (q15_t)0x1226, (q15_t)0x120d,
- (q15_t)0x11f4, (q15_t)0x11db, (q15_t)0x11c2, (q15_t)0x11a9, (q15_t)0x1191, (q15_t)0x1178, (q15_t)0x115f, (q15_t)0x1146,
- (q15_t)0x112d, (q15_t)0x1114, (q15_t)0x10fb, (q15_t)0x10e2, (q15_t)0x10c9, (q15_t)0x10b0, (q15_t)0x1098, (q15_t)0x107f,
- (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7,
- (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0,
- (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28,
- (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60,
- (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98,
- (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0,
- (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07,
- (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f,
- (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977,
- (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae,
- (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5,
- (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d,
- (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654,
- (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b,
- (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2,
- (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9,
- (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330,
- (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267,
- (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e,
- (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5,
- (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc
-
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff,
- (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe,
- (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe,
- (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd,
- (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc,
- (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc,
- (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb,
- (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa,
- (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9,
- (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8,
- (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7,
- (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6,
- (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4,
- (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3,
- (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2,
- (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0,
- (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef,
- (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed,
- (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb,
- (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9,
- (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8,
- (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6,
- (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4,
- (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1,
- (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf,
- (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd,
- (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb,
- (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8,
- (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6,
- (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3,
- (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0,
- (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce,
- (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb,
- (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8,
- (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5,
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- (q15_t)0xf76, (q15_t)0xf6f, (q15_t)0xf69, (q15_t)0xf63, (q15_t)0xf5d, (q15_t)0xf56, (q15_t)0xf50, (q15_t)0xf4a,
- (q15_t)0xf44, (q15_t)0xf3e, (q15_t)0xf37, (q15_t)0xf31, (q15_t)0xf2b, (q15_t)0xf25, (q15_t)0xf1e, (q15_t)0xf18,
- (q15_t)0xf12, (q15_t)0xf0c, (q15_t)0xf05, (q15_t)0xeff, (q15_t)0xef9, (q15_t)0xef3, (q15_t)0xeec, (q15_t)0xee6,
- (q15_t)0xee0, (q15_t)0xeda, (q15_t)0xed3, (q15_t)0xecd, (q15_t)0xec7, (q15_t)0xec1, (q15_t)0xeba, (q15_t)0xeb4,
- (q15_t)0xeae, (q15_t)0xea8, (q15_t)0xea1, (q15_t)0xe9b, (q15_t)0xe95, (q15_t)0xe8f, (q15_t)0xe89, (q15_t)0xe82,
- (q15_t)0xe7c, (q15_t)0xe76, (q15_t)0xe70, (q15_t)0xe69, (q15_t)0xe63, (q15_t)0xe5d, (q15_t)0xe57, (q15_t)0xe50,
- (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e,
- (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec,
- (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba,
- (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88,
- (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56,
- (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24,
- (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2,
- (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0,
- (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e,
- (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c,
- (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a,
- (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8,
- (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6,
- (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94,
- (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62,
- (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30,
- (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe,
- (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc,
- (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a,
- (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68,
- (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36,
- (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04,
- (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1,
- (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f,
- (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d,
- (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b,
- (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909,
- (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7,
- (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5,
- (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872,
- (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840,
- (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e,
- (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc,
- (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa,
- (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778,
- (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745,
- (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713,
- (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1,
- (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af,
- (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d,
- (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a,
- (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618,
- (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6,
- (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4,
- (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582,
- (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f,
- (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d,
- (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb,
- (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9,
- (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487,
- (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454,
- (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422,
- (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0,
- (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be,
- (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b,
- (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359,
- (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327,
- (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5,
- (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2,
- (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290,
- (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e,
- (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c,
- (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9,
- (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7,
- (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195,
- (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162,
- (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130,
- (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe,
- (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc,
- (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99,
- (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67,
- (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35,
- (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3
-};
-
-/**
- * @} end of DCT4_IDCT4_Table group
- */
-
-/**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- * \par Normalizing factor:
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
- * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:
- * \image html dct4NormalizingQ15Table.gif
- */
-
-arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initializing the pointer array with the weight table base addresses of different lengths */
- q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
- (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
- };
-
- /* Initializing the pointer array with the cos factor table base addresses of different lengths */
- q15_t *pCosFactor[4] =
- { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
- (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
- };
-
- /* Initialize the DCT4 length */
- S->N = N;
-
- /* Initialize the half of DCT4 length */
- S->Nby2 = Nby2;
-
- /* Initialize the DCT4 Normalizing factor */
- S->normalize = normalize;
-
- /* Initialize Real FFT Instance */
- S->pRfft = S_RFFT;
-
- /* Initialize Complex FFT Instance */
- S->pCfft = S_CFFT;
-
- switch (N)
- {
- /* Initialize the table modifier values */
- case 8192u:
- S->pTwiddle = twiddlePtr[3];
- S->pCosFactor = pCosFactor[3];
- break;
- case 2048u:
- S->pTwiddle = twiddlePtr[2];
- S->pCosFactor = pCosFactor[2];
- break;
- case 512u:
- S->pTwiddle = twiddlePtr[1];
- S->pCosFactor = pCosFactor[1];
- break;
- case 128u:
- S->pTwiddle = twiddlePtr[0];
- S->pCosFactor = pCosFactor[0];
- break;
- default:
- status = ARM_MATH_ARGUMENT_ERROR;
- }
-
- /* Initialize the RFFT/RIFFT */
- arm_rfft_init_q15(S->pRfft, S->N, 0u, 1u);
-
- /* return the status of DCT4 Init function */
- return (status);
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c
deleted file mode 100644
index efda6de..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c
+++ /dev/null
@@ -1,7686 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_init_q31.c
- * Description: Initialization function of DCT-4 & IDCT4 Q31
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup DCT4_IDCT4
- */
-
-/**
- * @addtogroup DCT4_IDCT4_Table DCT Type IV Tables
- * @{
- */
-
-/*
-* @brief Weights Table
-*/
-
-/**
- * \par
- * Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
- * \par
- * C command to generate the table
- *
- * for(i = 0; i< N; i++)
- * {
- * weights[2*i]= cos(i*c);
- * weights[(2*i)+1]= -sin(i * c);
- * }
- * \par
- * where N is the Number of weights to be calculated and c is pi/(2*N)
- * \par
- * Convert the output to q31 format by multiplying with 2^31 and saturated if required.
- * \par
- * In the tables below the real and imaginary values are placed alternatively, hence the
- * array length is 2*N.
- */
-
-static const q31_t WeightsQ31_128[256] = {
- (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3,
- (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb,
- (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31,
- (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622,
- (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b,
- (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781,
- (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b,
- (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e,
- (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9,
- (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149,
- (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3,
- (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71,
- (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368,
- (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3,
- (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5,
- (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68,
- (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284,
- (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1,
- (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d,
- (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94,
- (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04,
- (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66,
- (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30,
- (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31,
- (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677,
- (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153,
- (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70,
- (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14,
- (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d,
- (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a,
- (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x7d95b9e, (q31_t)0x803daa6a,
- (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x1921d20, (q31_t)0x800277a6
-};
-
-static const q31_t WeightsQ31_512[1024] = {
- (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f,
- (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c,
- (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89,
- (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157,
- (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42,
- (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6,
- (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b,
- (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77,
- (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a,
- (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401,
- (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243,
- (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2,
- (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8,
- (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a,
- (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273,
- (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8,
- (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5,
- (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb,
- (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3,
- (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c4242f2, (q31_t)0xe14794ba,
- (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3,
- (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b77ada8, (q31_t)0xde3d4964,
- (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008,
- (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd,
- (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a24256f, (q31_t)0xd9b7c094,
- (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79a98715, (q31_t)0xd838c82d,
- (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x792a37fe, (q31_t)0xd6bb585e,
- (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78a63d11, (q31_t)0xd53f7fda,
- (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x781d9b65, (q31_t)0xd3c54d47,
- (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x7790583e, (q31_t)0xd24ccf39,
- (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x76fe790e, (q31_t)0xd0d61434,
- (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x76680376, (q31_t)0xcf612aaa,
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- (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e,
- (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac,
- (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359,
- (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28,
- (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb,
- (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286,
- (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf,
- (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad,
- (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507,
- (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97,
- (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5,
- (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b,
- (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3,
- (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7,
- (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2,
- (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e,
- (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6,
- (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4,
- (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2,
- (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xcefdb76, (q31_t)0x80a7cb49,
- (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xb5f8d9f, (q31_t)0x80819b74,
- (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0x9cecf89, (q31_t)0x806055eb,
- (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x83db0a7, (q31_t)0x8043fbf6,
- (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6ac406f, (q31_t)0x802c8ead,
- (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x51a8e5c, (q31_t)0x801a0ef8,
- (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x388a9ea, (q31_t)0x800c7d8c,
- (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x1f6a297, (q31_t)0x8003daf1,
- (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0x6487e3, (q31_t)0x8000277a
-};
-
-static const q31_t WeightsQ31_2048[4096] = {
- (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12,
- (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258,
- (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a,
- (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467,
- (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac,
- (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18,
- (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9,
- (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c,
- (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af,
- (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821,
- (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0,
- (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459,
- (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b,
- (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3,
- (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f,
- (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de,
- (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed,
- (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a,
- (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574,
- (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68,
- (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423,
- (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5,
- (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea,
- (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071,
- (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8,
- (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc,
- (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b,
- (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273,
- (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21,
- (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5,
- (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a,
- (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0,
- (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3,
- (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2,
- (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba,
- (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829,
- (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d,
- (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32,
- (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848,
- (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba,
- (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8,
- (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae,
- (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa,
- (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9,
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- (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032,
- (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754,
- (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84,
- (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd,
- (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136,
- (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca,
- (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f,
- (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90,
- (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4,
- (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63,
- (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446,
- (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984,
- (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24,
- (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e,
- (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9,
- (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c,
- (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e,
- (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806,
- (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289,
- (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f,
- (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c,
- (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998,
- (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87,
- (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f,
- (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466,
- (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560,
- (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512,
- (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381,
- (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2,
- (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9,
- (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a,
- (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8,
- (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959,
- (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e,
- (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c,
- (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86,
- (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f,
- (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa,
- (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388,
- (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe,
- (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c,
- (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5,
- (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb,
- (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00,
- (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614,
- (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a,
- (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912,
- (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd,
- (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0xfb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc,
- (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0xafeda8, (q31_t)0x800078e7, (q31_t)0x96cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf,
- (q31_t)0x6487e3, (q31_t)0x8000277a, (q31_t)0x4b65ee, (q31_t)0x80001635, (q31_t)0x3243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278
-};
-
-static const q31_t WeightsQ31_8192[16384] = {
- (q31_t)0x7fffffff, (q31_t)0x0, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d,
- (q31_t)0xffed2684,
- (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08,
- (q31_t)0x7ffff872, (q31_t)0xffd40489,
- (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e,
- (q31_t)0x7fffed57, (q31_t)0xffbae290,
- (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917,
- (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a,
- (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724,
- (q31_t)0x7fffc854, (q31_t)0xff889ea7,
- (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535,
- (q31_t)0x7fffae6c, (q31_t)0xff6f7cba,
- (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b,
- (q31_t)0x7fff8f94, (q31_t)0xff565ad1,
- (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167,
- (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef,
- (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b,
- (q31_t)0x7fff4317, (q31_t)0xff241715,
- (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7,
- (q31_t)0x7fff1572, (q31_t)0xff0af543,
- (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec,
- (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b,
- (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b,
- (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd,
- (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876,
- (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a,
- (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc,
- (q31_t)0x7ffe2d83, (q31_t)0xfea66e64,
- (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530,
- (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb,
- (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2,
- (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41,
- (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223,
- (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5,
- (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3,
- (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a,
- (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55,
- (q31_t)0x7ffc9c92, (q31_t)0xfe28c700,
- (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09,
- (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8,
- (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf,
- (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484,
- (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9,
- (q31_t)0x7ffb70cb, (q31_t)0xfddd6363,
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- (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904,
- (q31_t)0x2616f10, (q31_t)0x8005aaf2,
- (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296,
- (q31_t)0x2484e26, (q31_t)0x800535c0,
- (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117,
- (q31_t)0x22f2d25, (q31_t)0x8004c57d,
- (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488,
- (q31_t)0x2160c0f, (q31_t)0x80045a29,
- (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7,
- (q31_t)0x1fceae4, (q31_t)0x8003f3c5,
- (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36,
- (q31_t)0x1e3c9a6, (q31_t)0x8003924f,
- (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74,
- (q31_t)0x1caa855, (q31_t)0x800335c9,
- (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1,
- (q31_t)0x1b186f3, (q31_t)0x8002de32,
- (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe,
- (q31_t)0x198657f, (q31_t)0x80028b8a,
- (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9,
- (q31_t)0x17f43fc, (q31_t)0x80023dd2,
- (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4,
- (q31_t)0x166226a, (q31_t)0x8001f508,
- (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae,
- (q31_t)0x14d00ca, (q31_t)0x8001b12e,
- (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187,
- (q31_t)0x133df1e, (q31_t)0x80017243,
- (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650,
- (q31_t)0x11abd66, (q31_t)0x80013847,
- (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008,
- (q31_t)0x1019ba2, (q31_t)0x8001033b,
- (q31_t)0xfb5330, (q31_t)0x8000f6bd, (q31_t)0xf50abd, (q31_t)0x8000ea8e, (q31_t)0xeec249, (q31_t)0x8000deaf, (q31_t)0xe879d5,
- (q31_t)0x8000d31e,
- (q31_t)0xe23160, (q31_t)0x8000c7dc, (q31_t)0xdbe8eb, (q31_t)0x8000bce9, (q31_t)0xd5a075, (q31_t)0x8000b245, (q31_t)0xcf57ff,
- (q31_t)0x8000a7f0,
- (q31_t)0xc90f88, (q31_t)0x80009dea, (q31_t)0xc2c711, (q31_t)0x80009433, (q31_t)0xbc7e99, (q31_t)0x80008aca, (q31_t)0xb63621,
- (q31_t)0x800081b1,
- (q31_t)0xafeda8, (q31_t)0x800078e7, (q31_t)0xa9a52f, (q31_t)0x8000706c, (q31_t)0xa35cb5, (q31_t)0x8000683f, (q31_t)0x9d143b,
- (q31_t)0x80006062,
- (q31_t)0x96cbc1, (q31_t)0x800058d4, (q31_t)0x908346, (q31_t)0x80005194, (q31_t)0x8a3acb, (q31_t)0x80004aa4, (q31_t)0x83f250,
- (q31_t)0x80004402,
- (q31_t)0x7da9d4, (q31_t)0x80003daf, (q31_t)0x776159, (q31_t)0x800037ac, (q31_t)0x7118dc, (q31_t)0x800031f7, (q31_t)0x6ad060,
- (q31_t)0x80002c91,
- (q31_t)0x6487e3, (q31_t)0x8000277a, (q31_t)0x5e3f66, (q31_t)0x800022b3, (q31_t)0x57f6e9, (q31_t)0x80001e3a, (q31_t)0x51ae6b,
- (q31_t)0x80001a10,
- (q31_t)0x4b65ee, (q31_t)0x80001635, (q31_t)0x451d70, (q31_t)0x800012a9, (q31_t)0x3ed4f2, (q31_t)0x80000f6c, (q31_t)0x388c74,
- (q31_t)0x80000c7e,
- (q31_t)0x3243f5, (q31_t)0x800009df, (q31_t)0x2bfb77, (q31_t)0x8000078e, (q31_t)0x25b2f8, (q31_t)0x8000058d, (q31_t)0x1f6a7a,
- (q31_t)0x800003db,
- (q31_t)0x1921fb, (q31_t)0x80000278, (q31_t)0x12d97c, (q31_t)0x80000163, (q31_t)0xc90fe, (q31_t)0x8000009e, (q31_t)0x6487f,
- (q31_t)0x80000027
-
-};
-
-/**
-* \par
-* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
-* \par
-* C command to generate the table
-*
-* for(i = 0; i< N; i++)
-* {
-* cos_factors[i]= 2 * cos((2*i+1)*c/2);
-* }
-* \par
-* where N is the number of factors to generate and c is pi/(2*N)
-* \par
-* Then converted to q31 format by multiplying with 2^31 and saturated if required.
-*/
-
-
-static const q31_t cos_factorsQ31_128[128] = {
- (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3,
- (q31_t)0x7f97cebd, (q31_t)0x7f754e80,
- (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff,
- (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8,
- (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89,
- (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4,
- (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df,
- (q31_t)0x77235f2d, (q31_t)0x768e0ea6,
- (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7,
- (q31_t)0x71fa3949, (q31_t)0x71410805,
- (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c,
- (q31_t)0x6bb812d1, (q31_t)0x6adcc964,
- (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92,
- (q31_t)0x646c59bf, (q31_t)0x637114cc,
- (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237,
- (q31_t)0x5c290acc, (q31_t)0x5b1035cf,
- (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d,
- (q31_t)0x53028518, (q31_t)0x51ced46e,
- (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e,
- (q31_t)0x490f57ee, (q31_t)0x47c3c22f,
- (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98,
- (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6,
- (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250,
- (q31_t)0x3326e2c3, (q31_t)0x31b54a5e,
- (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b,
- (q31_t)0x27679df4, (q31_t)0x25e845b6,
- (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3,
- (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3,
- (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048,
- (q31_t)0xee38766, (q31_t)0xd53db92,
- (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7,
- (q31_t)0xc90f88
-};
-
-static const q31_t cos_factorsQ31_512[512] = {
- (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce,
- (q31_t)0x7ff97c18, (q31_t)0x7ff75370,
- (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616,
- (q31_t)0x7fdf9508, (q31_t)0x7fdaf519,
- (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8,
- (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c,
- (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a,
- (q31_t)0x7f70a5fe, (q31_t)0x7f671a05,
- (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af,
- (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25,
- (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270,
- (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58,
- (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b,
- (q31_t)0x7e37042a, (q31_t)0x7e26221f,
- (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534,
- (q31_t)0x7da77359, (q31_t)0x7d9423fc,
- (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf,
- (q31_t)0x7d048228, (q31_t)0x7ceec873,
- (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc,
- (q31_t)0x7c4e49b7, (q31_t)0x7c362904,
- (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6,
- (q31_t)0x7b84e61f, (q31_t)0x7b6a6227,
- (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec,
- (q31_t)0x7aa8766f, (q31_t)0x7a8b9348,
- (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f,
- (q31_t)0x79b91ca4, (q31_t)0x7999dec4,
- (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb,
- (q31_t)0x78b6fda8, (q31_t)0x789569df,
- (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01,
- (q31_t)0x77a24148, (q31_t)0x777e5cc3,
- (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2,
- (q31_t)0x767b1231, (q31_t)0x7654e279,
- (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99,
- (q31_t)0x75419de7, (q31_t)0x751928e0,
- (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150,
- (q31_t)0x73f614c0, (q31_t)0x73cb60a8,
- (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1,
- (q31_t)0x7298a9dd, (q31_t)0x726bbd48,
- (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74,
- (q31_t)0x7129931f, (q31_t)0x70fa74fc,
- (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae,
- (q31_t)0x6fa90921, (q31_t)0x6f77c0b3,
- (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66,
- (q31_t)0x6e174730, (q31_t)0x6de3dc11,
- (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b,
- (q31_t)0x6c748b3f, (q31_t)0x6c3f055d,
- (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c,
- (q31_t)0x6ac115e2, (q31_t)0x6a897d7d,
- (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce,
- (q31_t)0x68fd2a3d, (q31_t)0x68c387e9,
- (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0,
- (q31_t)0x67290e02, (q31_t)0x66ed6aa1,
- (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622,
- (q31_t)0x6545095f, (q31_t)0x65076e25,
- (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a,
- (q31_t)0x635166f9, (q31_t)0x6311dd64,
- (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7,
- (q31_t)0x614e73da, (q31_t)0x610d05b7,
- (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46,
- (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1,
- (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7,
- (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5,
- (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce,
- (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5,
- (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9,
- (q31_t)0x58afd6bd, (q31_t)0x58673e1b,
- (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750,
- (q31_t)0x566524aa, (q31_t)0x561adcb9,
- (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9,
- (q31_t)0x540d2005, (q31_t)0x53c13439,
- (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea,
- (q31_t)0x51a82555, (q31_t)0x515aa162,
- (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269,
- (q31_t)0x4f369320, (q31_t)0x4ee782fb,
- (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0,
- (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7,
- (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de,
- (q31_t)0x4a2f2be6, (q31_t)0x49dd282a,
- (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6,
- (q31_t)0x479a1d67, (q31_t)0x4746b2bc,
- (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80,
- (q31_t)0x44fa0450, (q31_t)0x44a53f93,
- (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b,
- (q31_t)0x424f4845, (q31_t)0x41f93689,
- (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca,
- (q31_t)0x3f9a5290, (q31_t)0x3f430119,
- (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39,
- (q31_t)0x3cdb8e09, (q31_t)0x3c830a50,
- (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96,
- (q31_t)0x3a136712, (q31_t)0x39b9bebc,
- (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885,
- (q31_t)0x37424b7b, (q31_t)0x36e78c5b,
- (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d,
- (q31_t)0x3468aa76, (q31_t)0x340ce28b,
- (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889,
- (q31_t)0x3186f487, (q31_t)0x312a31f8,
- (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95,
- (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b,
- (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa,
- (q31_t)0x2bad1221, (q31_t)0x2b4e8558,
- (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1,
- (q31_t)0x28b5cca5, (q31_t)0x2856708d,
- (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581,
- (q31_t)0x25b84012, (q31_t)0x2558235f,
- (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88,
- (q31_t)0x22b4e274, (q31_t)0x225413f8,
- (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d,
- (q31_t)0x1fac2abf, (q31_t)0x1f4ab968,
- (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d,
- (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c,
- (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707,
- (q31_t)0x198c8ce7, (q31_t)0x192a0304,
- (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c,
- (q31_t)0x1676987f, (q31_t)0x16139918,
- (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a,
- (q31_t)0x135d2d53, (q31_t)0x12f9c7aa,
- (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b,
- (q31_t)0x1040c5bb, (q31_t)0xfdd0926,
- (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87,
- (q31_t)0xcbdd865,
- (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8,
- (q31_t)0x99cb0a7,
- (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262,
- (q31_t)0x67a0d76,
- (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2,
- (q31_t)0x3566a96,
- (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1,
- (q31_t)0x3243f5
-};
-
-static const q31_t cos_factorsQ31_2048[2048] = {
- (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c,
- (q31_t)0x7fff97c1, (q31_t)0x7fff7536,
- (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52,
- (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37,
- (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78,
- (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a,
- (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6,
- (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7,
- (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275,
- (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688,
- (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62,
- (q31_t)0x7feb296d, (q31_t)0x7fea418b,
- (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac,
- (q31_t)0x7fe36045, (q31_t)0x7fe250ef,
- (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67,
- (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca,
- (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8,
- (q31_t)0x7fd01b63, (q31_t)0x7fcebd31,
- (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089,
- (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d,
- (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125,
- (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d,
- (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b,
- (q31_t)0x7fa9f723, (q31_t)0x7fa822bf,
- (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d,
- (q31_t)0x7f9aca37, (q31_t)0x7f98ce76,
- (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1,
- (q31_t)0x7f8a6272, (q31_t)0x7f883f58,
- (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e,
- (q31_t)0x7f78bffb, (q31_t)0x7f76758e,
- (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0,
- (q31_t)0x7f65e2ff, (q31_t)0x7f637144,
- (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5,
- (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9,
- (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d,
- (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee,
- (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d,
- (q31_t)0x7f25eec7, (q31_t)0x7f230749,
- (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d,
- (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2,
- (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7,
- (q31_t)0x7ef52b00, (q31_t)0x7ef1f524,
- (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38,
- (q31_t)0x7edaf31c, (q31_t)0x7ed7961c,
- (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f,
- (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c,
- (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2,
- (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68,
- (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5,
- (q31_t)0x7e84f67e, (q31_t)0x7e812447,
- (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093,
- (q31_t)0x7e65dc3b, (q31_t)0x7e61e303,
- (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567,
- (q31_t)0x7e458a17, (q31_t)0x7e4169e9,
- (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2,
- (q31_t)0x7e240064, (q31_t)0x7e1fb94a,
- (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894,
- (q31_t)0x7e013f74, (q31_t)0x7dfcd178,
- (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795,
- (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca,
- (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc,
- (q31_t)0x7db81936, (q31_t)0x7db35d98,
- (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224,
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- (q31_t)0xfd090e1, (q31_t)0xfb79fe4,
- (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836,
- (q31_t)0xef0027b,
- (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72,
- (q31_t)0xe284036,
- (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982,
- (q31_t)0xd605b03,
- (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752,
- (q31_t)0xc9854cf,
- (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2,
- (q31_t)0xbd02f87,
- (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee,
- (q31_t)0xb07ed19,
- (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94,
- (q31_t)0xa3f8f73,
- (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3,
- (q31_t)0x9771884,
- (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a,
- (q31_t)0x8ae8a3a,
- (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16,
- (q31_t)0x7e5e685,
- (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738,
- (q31_t)0x71d2f52,
- (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f,
- (q31_t)0x6546692,
- (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09,
- (q31_t)0x58b8e34,
- (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597,
- (q31_t)0x4c2a827,
- (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528,
- (q31_t)0x3f9b65b,
- (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac,
- (q31_t)0x330bac1,
- (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813,
- (q31_t)0x267b747,
- (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d,
- (q31_t)0x19eaddd,
- (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249,
- (q31_t)0xd5a075,
- (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8,
- (q31_t)0xc90fe
-};
-
-static const q31_t cos_factorsQ31_8192[8192] = {
- (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56,
- (q31_t)0x7ffff97c, (q31_t)0x7ffff753,
- (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5,
- (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3,
- (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7,
- (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6,
- (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc,
- (q31_t)0x7fff708b, (q31_t)0x7fff66fc,
- (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724,
- (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64,
- (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be,
- (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f,
- (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c,
- (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe,
- (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc,
- (q31_t)0x7ffda59d, (q31_t)0x7ffd922f,
- (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720,
- (q31_t)0x7ffd0189, (q31_t)0x7ffceba4,
- (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7,
- (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b,
- (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1,
- (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356,
- (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf,
- (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195,
- (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50,
- (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17,
- (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705,
- (q31_t)0x7ff8a519, (q31_t)0x7ff882dd,
- (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe,
- (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7,
- (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b,
- (q31_t)0x7ff65c5f, (q31_t)0x7ff63535,
- (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc,
- (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7,
- (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082,
- (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e,
- (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c,
- (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9,
- (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb,
- (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19,
- (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f,
- (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf,
- (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, (q31_t)0x7fee13a1, (q31_t)0x7fedde48,
- (q31_t)0x7feda8a0, (q31_t)0x7fed72aa,
- (q31_t)0x7fed3c64, (q31_t)0x7fed05cf, (q31_t)0x7fecceec, (q31_t)0x7fec97b9, (q31_t)0x7fec6038, (q31_t)0x7fec2867,
- (q31_t)0x7febf048, (q31_t)0x7febb7da,
- (q31_t)0x7feb7f1d, (q31_t)0x7feb4611, (q31_t)0x7feb0cb6, (q31_t)0x7fead30c, (q31_t)0x7fea9914, (q31_t)0x7fea5ecc,
- (q31_t)0x7fea2436, (q31_t)0x7fe9e950,
- (q31_t)0x7fe9ae1c, (q31_t)0x7fe97299, (q31_t)0x7fe936c7, (q31_t)0x7fe8faa6, (q31_t)0x7fe8be36, (q31_t)0x7fe88177,
- (q31_t)0x7fe84469, (q31_t)0x7fe8070d,
- (q31_t)0x7fe7c961, (q31_t)0x7fe78b67, (q31_t)0x7fe74d1e, (q31_t)0x7fe70e85, (q31_t)0x7fe6cf9e, (q31_t)0x7fe69068,
- (q31_t)0x7fe650e3, (q31_t)0x7fe61110,
- (q31_t)0x7fe5d0ed, (q31_t)0x7fe5907b, (q31_t)0x7fe54fbb, (q31_t)0x7fe50eac, (q31_t)0x7fe4cd4d, (q31_t)0x7fe48ba0,
- (q31_t)0x7fe449a4, (q31_t)0x7fe40759,
- (q31_t)0x7fe3c4bf, (q31_t)0x7fe381d7, (q31_t)0x7fe33e9f, (q31_t)0x7fe2fb19, (q31_t)0x7fe2b743, (q31_t)0x7fe2731f,
- (q31_t)0x7fe22eac, (q31_t)0x7fe1e9ea,
- (q31_t)0x7fe1a4d9, (q31_t)0x7fe15f79, (q31_t)0x7fe119cb, (q31_t)0x7fe0d3cd, (q31_t)0x7fe08d81, (q31_t)0x7fe046e5,
- (q31_t)0x7fdffffb, (q31_t)0x7fdfb8c2,
- (q31_t)0x7fdf713a, (q31_t)0x7fdf2963, (q31_t)0x7fdee13e, (q31_t)0x7fde98c9, (q31_t)0x7fde5006, (q31_t)0x7fde06f3,
- (q31_t)0x7fddbd92, (q31_t)0x7fdd73e2,
- (q31_t)0x7fdd29e3, (q31_t)0x7fdcdf95, (q31_t)0x7fdc94f9, (q31_t)0x7fdc4a0d, (q31_t)0x7fdbfed3, (q31_t)0x7fdbb349,
- (q31_t)0x7fdb6771, (q31_t)0x7fdb1b4a,
- (q31_t)0x7fdaced4, (q31_t)0x7fda820f, (q31_t)0x7fda34fc, (q31_t)0x7fd9e799, (q31_t)0x7fd999e8, (q31_t)0x7fd94be8,
- (q31_t)0x7fd8fd98, (q31_t)0x7fd8aefa,
- (q31_t)0x7fd8600e, (q31_t)0x7fd810d2, (q31_t)0x7fd7c147, (q31_t)0x7fd7716e, (q31_t)0x7fd72146, (q31_t)0x7fd6d0cf,
- (q31_t)0x7fd68009, (q31_t)0x7fd62ef4,
- (q31_t)0x7fd5dd90, (q31_t)0x7fd58bdd, (q31_t)0x7fd539dc, (q31_t)0x7fd4e78c, (q31_t)0x7fd494ed, (q31_t)0x7fd441ff,
- (q31_t)0x7fd3eec2, (q31_t)0x7fd39b36,
- (q31_t)0x7fd3475c, (q31_t)0x7fd2f332, (q31_t)0x7fd29eba, (q31_t)0x7fd249f3, (q31_t)0x7fd1f4dd, (q31_t)0x7fd19f78,
- (q31_t)0x7fd149c5, (q31_t)0x7fd0f3c2,
- (q31_t)0x7fd09d71, (q31_t)0x7fd046d1, (q31_t)0x7fcfefe2, (q31_t)0x7fcf98a4, (q31_t)0x7fcf4117, (q31_t)0x7fcee93c,
- (q31_t)0x7fce9112, (q31_t)0x7fce3898,
- (q31_t)0x7fcddfd0, (q31_t)0x7fcd86b9, (q31_t)0x7fcd2d54, (q31_t)0x7fccd39f, (q31_t)0x7fcc799c, (q31_t)0x7fcc1f4a,
- (q31_t)0x7fcbc4a9, (q31_t)0x7fcb69b9,
- (q31_t)0x7fcb0e7a, (q31_t)0x7fcab2ed, (q31_t)0x7fca5710, (q31_t)0x7fc9fae5, (q31_t)0x7fc99e6b, (q31_t)0x7fc941a2,
- (q31_t)0x7fc8e48b, (q31_t)0x7fc88724,
- (q31_t)0x7fc8296f, (q31_t)0x7fc7cb6b, (q31_t)0x7fc76d18, (q31_t)0x7fc70e76, (q31_t)0x7fc6af86, (q31_t)0x7fc65046,
- (q31_t)0x7fc5f0b8, (q31_t)0x7fc590db,
- (q31_t)0x7fc530af, (q31_t)0x7fc4d035, (q31_t)0x7fc46f6b, (q31_t)0x7fc40e53, (q31_t)0x7fc3acec, (q31_t)0x7fc34b36,
- (q31_t)0x7fc2e931, (q31_t)0x7fc286de,
- (q31_t)0x7fc2243b, (q31_t)0x7fc1c14a, (q31_t)0x7fc15e0a, (q31_t)0x7fc0fa7b, (q31_t)0x7fc0969e, (q31_t)0x7fc03271,
- (q31_t)0x7fbfcdf6, (q31_t)0x7fbf692c,
- (q31_t)0x7fbf0414, (q31_t)0x7fbe9eac, (q31_t)0x7fbe38f6, (q31_t)0x7fbdd2f0, (q31_t)0x7fbd6c9c, (q31_t)0x7fbd05fa,
- (q31_t)0x7fbc9f08, (q31_t)0x7fbc37c8,
- (q31_t)0x7fbbd039, (q31_t)0x7fbb685b, (q31_t)0x7fbb002e, (q31_t)0x7fba97b2, (q31_t)0x7fba2ee8, (q31_t)0x7fb9c5cf,
- (q31_t)0x7fb95c67, (q31_t)0x7fb8f2b0,
- (q31_t)0x7fb888ab, (q31_t)0x7fb81e57, (q31_t)0x7fb7b3b4, (q31_t)0x7fb748c2, (q31_t)0x7fb6dd81, (q31_t)0x7fb671f2,
- (q31_t)0x7fb60614, (q31_t)0x7fb599e7,
- (q31_t)0x7fb52d6b, (q31_t)0x7fb4c0a1, (q31_t)0x7fb45387, (q31_t)0x7fb3e61f, (q31_t)0x7fb37869, (q31_t)0x7fb30a63,
- (q31_t)0x7fb29c0f, (q31_t)0x7fb22d6c,
- (q31_t)0x7fb1be7a, (q31_t)0x7fb14f39, (q31_t)0x7fb0dfaa, (q31_t)0x7fb06fcb, (q31_t)0x7fafff9e, (q31_t)0x7faf8f23,
- (q31_t)0x7faf1e58, (q31_t)0x7faead3f,
- (q31_t)0x7fae3bd7, (q31_t)0x7fadca20, (q31_t)0x7fad581b, (q31_t)0x7face5c6, (q31_t)0x7fac7323, (q31_t)0x7fac0031,
- (q31_t)0x7fab8cf1, (q31_t)0x7fab1962,
- (q31_t)0x7faaa584, (q31_t)0x7faa3157, (q31_t)0x7fa9bcdb, (q31_t)0x7fa94811, (q31_t)0x7fa8d2f8, (q31_t)0x7fa85d90,
- (q31_t)0x7fa7e7d9, (q31_t)0x7fa771d4,
- (q31_t)0x7fa6fb80, (q31_t)0x7fa684dd, (q31_t)0x7fa60dec, (q31_t)0x7fa596ac, (q31_t)0x7fa51f1d, (q31_t)0x7fa4a73f,
- (q31_t)0x7fa42f12, (q31_t)0x7fa3b697,
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- (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba,
- (q31_t)0x38bcdda,
- (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680,
- (q31_t)0x3598e8f,
- (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1,
- (q31_t)0x3274ec0,
- (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684,
- (q31_t)0x2f50e74,
- (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2,
- (q31_t)0x2c2cdb4,
- (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2,
- (q31_t)0x2908c87,
- (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b,
- (q31_t)0x25e4af4,
- (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147,
- (q31_t)0x22c0904,
- (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b,
- (q31_t)0x1f9c6be,
- (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80,
- (q31_t)0x1c7842a,
- (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae,
- (q31_t)0x1954150,
- (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d,
- (q31_t)0x162fe37,
- (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354,
- (q31_t)0x130bae7,
- (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb,
- (q31_t)0xfe7769,
- (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a,
- (q31_t)0xcc33c3,
- (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878,
- (q31_t)0x99effe,
- (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e,
- (q31_t)0x67ac21,
- (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3,
- (q31_t)0x356835,
- (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f
-};
-
-/**
- * @} end of DCT4_IDCT4_Table group
- */
-
-/**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- * \par Normalizing factor:
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
- * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:
- * \image html dct4NormalizingQ31Table.gif
- */
-
-arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initializing the pointer array with the weight table base addresses of different lengths */
- q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
- (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
- };
-
- /* Initializing the pointer array with the cos factor table base addresses of different lengths */
- q31_t *pCosFactor[4] =
- { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
- (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
- };
-
- /* Initialize the DCT4 length */
- S->N = N;
-
- /* Initialize the half of DCT4 length */
- S->Nby2 = Nby2;
-
- /* Initialize the DCT4 Normalizing factor */
- S->normalize = normalize;
-
- /* Initialize Real FFT Instance */
- S->pRfft = S_RFFT;
-
- /* Initialize Complex FFT Instance */
- S->pCfft = S_CFFT;
-
- switch (N)
- {
- /* Initialize the table modifier values */
- case 8192u:
- S->pTwiddle = twiddlePtr[3];
- S->pCosFactor = pCosFactor[3];
- break;
- case 2048u:
- S->pTwiddle = twiddlePtr[2];
- S->pCosFactor = pCosFactor[2];
- break;
- case 512u:
- S->pTwiddle = twiddlePtr[1];
- S->pCosFactor = pCosFactor[1];
- break;
- case 128u:
- S->pTwiddle = twiddlePtr[0];
- S->pCosFactor = pCosFactor[0];
- break;
- default:
- status = ARM_MATH_ARGUMENT_ERROR;
- }
-
- /* Initialize the RFFT/RIFFT Function */
- arm_rfft_init_q31(S->pRfft, S->N, 0, 1);
-
- /* return the status of DCT4 Init function */
- return (status);
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c
deleted file mode 100644
index 87257a8..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_q15.c
- * Description: Processing function of DCT4 & IDCT4 Q15
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q15 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- *
- * \par Input an output formats:
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.
- * Number of bits downscaled, depends on the size of the transform.
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
- *
- * \image html dct4FormatsQ15Table.gif
- */
-
-void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer)
-{
- uint32_t i; /* Loop counter */
- q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */
- q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
- q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
- q15_t in; /* Temporary variable */
-
-
- /* DCT4 computation involves DCT2 (which is calculated using RFFT)
- * along with some pre-processing and post-processing.
- * Computational procedure is explained as follows:
- * (a) Pre-processing involves multiplying input with cos factor,
- * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
- * where,
- * r(n) -- output of preprocessing
- * u(n) -- input to preprocessing(actual Source buffer)
- * (b) Calculation of DCT2 using FFT is divided into three steps:
- * Step1: Re-ordering of even and odd elements of input.
- * Step2: Calculating FFT of the re-ordered input.
- * Step3: Taking the real part of the product of FFT output and weights.
- * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * where,
- * Y4 -- DCT4 output, Y2 -- DCT2 output
- * (d) Multiplying the output with the normalizing factor sqrt(2/N).
- */
-
- /*-------- Pre-processing ------------*/
- /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
- arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
- arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
-
- /* ----------------------------------------------------------------
- * Step1: Re-ordering of even and odd elements as
- * pState[i] = pInlineBuffer[2*i] and
- * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
- ---------------------------------------------------------------------*/
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
- pS2 = pState + (S->N - 1u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
- i = (uint32_t) S->Nby2 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = (uint32_t) S->N >> 2u;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4.
- * Compute 4 outputs at a time */
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
- /* The output of complex multiplication is in 3.13 format.
- * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
- arm_shift_q15(pState, 2, pState, S->N * 2);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
- i = ((uint32_t) S->N - 1u) >> 2u;
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ >> 1u;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- i = ((uint32_t) S->N - 1u) % 0x4u;
-
- while (i > 0u)
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = (uint32_t) S->N >> 2u;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
- in = *pbuff;
- *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
- in = *pbuff;
- *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
- in = *pbuff;
- *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initializing the loop counter to N/2 */
- i = (uint32_t) S->Nby2;
-
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter */
- i = (uint32_t) S->N;
-
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
- /* The output of complex multiplication is in 3.13 format.
- * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
- arm_shift_q15(pState, 2, pState, S->N * 2);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* Initializing the loop counter */
- i = ((uint32_t) S->N - 1u);
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ >> 1u;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- do
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter */
- i = (uint32_t) S->N;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c
deleted file mode 100644
index b5ac9c4..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_dct4_q31.c
- * Description: Processing function of DCT4 & IDCT4 Q31
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @addtogroup DCT4_IDCT4
- * @{
- */
-
-/**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q31 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- * \par Input an output formats:
- * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,
- * as the conversion from DCT2 to DCT4 involves one subtraction.
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.
- * Number of bits downscaled, depends on the size of the transform.
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
- *
- * \image html dct4FormatsQ31Table.gif
- */
-
-void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer)
-{
- uint16_t i; /* Loop counter */
- q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */
- q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
- q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
- q31_t in; /* Temporary variable */
-
-
- /* DCT4 computation involves DCT2 (which is calculated using RFFT)
- * along with some pre-processing and post-processing.
- * Computational procedure is explained as follows:
- * (a) Pre-processing involves multiplying input with cos factor,
- * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
- * where,
- * r(n) -- output of preprocessing
- * u(n) -- input to preprocessing(actual Source buffer)
- * (b) Calculation of DCT2 using FFT is divided into three steps:
- * Step1: Re-ordering of even and odd elements of input.
- * Step2: Calculating FFT of the re-ordered input.
- * Step3: Taking the real part of the product of FFT output and weights.
- * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * where,
- * Y4 -- DCT4 output, Y2 -- DCT2 output
- * (d) Multiplying the output with the normalizing factor sqrt(2/N).
- */
-
- /*-------- Pre-processing ------------*/
- /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
- arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
- arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
-
- /* ----------------------------------------------------------------
- * Step1: Re-ordering of even and odd elements as
- * pState[i] = pInlineBuffer[2*i] and
- * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
- ---------------------------------------------------------------------*/
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
- pS2 = pState + (S->N - 1u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
-
- /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
- i = S->Nby2 >> 2u;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- *pS1++ = *pbuff++;
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = S->N >> 2u;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4.
- * Compute 4 outputs at a time */
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
- /* The output of complex multiplication is in 3.29 format.
- * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
- arm_shift_q31(pState, 2, pState, S->N * 2);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
- i = (S->N - 1u) >> 2u;
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ >> 1u;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
- ** a second loop below computes the remaining 1 to 3 samples. */
- do
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- in = *pS1++ - in;
- *pbuff++ = in;
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
- ** No loop unrolling is used. */
- i = (S->N - 1u) % 0x4u;
-
- while (i > 0u)
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter to N/4 instead of N for loop unrolling */
- i = S->N >> 2u;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
- in = *pbuff;
- *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
- in = *pbuff;
- *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
- in = *pbuff;
- *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
-#else
-
- /* Run the below code for Cortex-M0 */
-
- /* Initializing the loop counter to N/2 */
- i = S->Nby2;
-
- do
- {
- /* Re-ordering of even and odd elements */
- /* pState[i] = pInlineBuffer[2*i] */
- *pS1++ = *pbuff++;
- /* pState[N-i-1] = pInlineBuffer[2*i+1] */
- *pS2-- = *pbuff++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
- /* pbuff initialized to input buffer */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Initializing the loop counter */
- i = S->N;
-
- do
- {
- /* Writing the re-ordered output back to inplace input buffer */
- *pbuff++ = *pS1++;
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-
- /* ---------------------------------------------------------
- * Step2: Calculate RFFT for N-point input
- * ---------------------------------------------------------- */
- /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
- arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------
- * Step3: Multiply the FFT output with the weights.
- *----------------------------------------------------------------------*/
- arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
- /* The output of complex multiplication is in 3.29 format.
- * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
- arm_shift_q31(pState, 2, pState, S->N * 2);
-
- /* ----------- Post-processing ---------- */
- /* DCT-IV can be obtained from DCT-II by the equation,
- * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
- * Hence, Y4(0) = Y2(0)/2 */
- /* Getting only real part from the output and Converting to DCT-IV */
-
- /* pbuff initialized to input buffer. */
- pbuff = pInlineBuffer;
-
- /* pS1 initialized to pState */
- pS1 = pState;
-
- /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
- in = *pS1++ >> 1u;
- /* input buffer acts as inplace, so output values are stored in the input itself. */
- *pbuff++ = in;
-
- /* pState pointer is incremented twice as the real values are located alternatively in the array */
- pS1++;
-
- /* Initializing the loop counter */
- i = (S->N - 1u);
-
- while (i > 0u)
- {
- /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
- /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
- in = *pS1++ - in;
- *pbuff++ = in;
- /* points to the next real value */
- pS1++;
-
- /* Decrement the loop counter */
- i--;
- }
-
-
- /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
- /* Initializing the loop counter */
- i = S->N;
-
- /* pbuff initialized to the pInlineBuffer(now contains the output values) */
- pbuff = pInlineBuffer;
-
- do
- {
- /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
- in = *pbuff;
- *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
- /* Decrement the loop counter */
- i--;
- } while (i > 0u);
-
-#endif /* #if defined (ARM_MATH_DSP) */
-
-}
-
-/**
- * @} end of DCT4_IDCT4 group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
deleted file mode 100644
index 0362bce..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_f32.c
- * Description: RFFT & RIFFT Floating point process function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/* ----------------------------------------------------------------------
- * Internal functions prototypes
- * -------------------------------------------------------------------- */
-
-extern void arm_radix4_butterfly_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier);
-
-extern void arm_radix4_butterfly_inverse_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier,
- float32_t onebyfftLen);
-
-extern void arm_bitreversal_f32(
- float32_t * pSrc,
- uint16_t fftSize,
- uint16_t bitRevFactor,
- uint16_t * pBitRevTab);
-
-void arm_split_rfft_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pATable,
- float32_t * pBTable,
- float32_t * pDst,
- uint32_t modifier);
-
-void arm_split_rifft_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pATable,
- float32_t * pBTable,
- float32_t * pDst,
- uint32_t modifier);
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
- * @addtogroup RealFFT
- * @{
- */
-
-/**
- * @brief Processing function for the floating-point RFFT/RIFFT.
- * @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed
- * in the future.
- * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
- * @param[in] *pSrc points to the input buffer.
- * @param[out] *pDst points to the output buffer.
- * @return none.
- */
-
-void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst)
-{
- const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
-
-
- /* Calculation of Real IFFT of input */
- if (S->ifftFlagR == 1u)
- {
- /* Real IFFT core process */
- arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
-
- /* Complex radix-4 IFFT process */
- arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
- S_CFFT->pTwiddle,
- S_CFFT->twidCoefModifier,
- S_CFFT->onebyfftLen);
-
- /* Bit reversal process */
- if (S->bitReverseFlagR == 1u)
- {
- arm_bitreversal_f32(pDst, S_CFFT->fftLen,
- S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
- }
- }
- else
- {
-
- /* Calculation of RFFT of input */
-
- /* Complex radix-4 FFT process */
- arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
- S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
-
- /* Bit reversal process */
- if (S->bitReverseFlagR == 1u)
- {
- arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
- S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
- }
-
-
- /* Real FFT core process */
- arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
- }
-
-}
-
-/**
- * @} end of RealFFT group
- */
-
-/**
- * @brief Core Real FFT process
- * @param[in] *pSrc points to the input buffer.
- * @param[in] fftLen length of FFT.
- * @param[in] *pATable points to the twiddle Coef A buffer.
- * @param[in] *pBTable points to the twiddle Coef B buffer.
- * @param[out] *pDst points to the output buffer.
- * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-void arm_split_rfft_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pATable,
- float32_t * pBTable,
- float32_t * pDst,
- uint32_t modifier)
-{
- uint32_t i; /* Loop Counter */
- float32_t outR, outI; /* Temporary variables for output */
- float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
- float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u]; /* temp pointers for output buffer */
- float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u]; /* temp pointers for input buffer */
-
- /* Init coefficient pointers */
- pCoefA = &pATable[modifier * 2u];
- pCoefB = &pBTable[modifier * 2u];
-
- i = fftLen - 1u;
-
- while (i > 0u)
- {
- /*
- outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
- + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
- pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
- */
-
- /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
- /* read pATable[2 * i] */
- CoefA1 = *pCoefA++;
- /* pATable[2 * i + 1] */
- CoefA2 = *pCoefA;
-
- /* pSrc[2 * i] * pATable[2 * i] */
- outR = *pSrc1 * CoefA1;
- /* pSrc[2 * i] * CoefA2 */
- outI = *pSrc1++ * CoefA2;
-
- /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
- outR -= (*pSrc1 + *pSrc2) * CoefA2;
- /* pSrc[2 * i + 1] * CoefA1 */
- outI += *pSrc1++ * CoefA1;
-
- CoefB1 = *pCoefB;
-
- /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
- outI -= *pSrc2-- * CoefB1;
- /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
- outI -= *pSrc2 * CoefA2;
-
- /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
- outR += *pSrc2-- * CoefB1;
-
- /* write output */
- *pDst1++ = outR;
- *pDst1++ = outI;
-
- /* write complex conjugate output */
- *pDst2-- = -outI;
- *pDst2-- = outR;
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (modifier * 2u);
- pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
- i--;
-
- }
-
- pDst[2u * fftLen] = pSrc[0] - pSrc[1];
- pDst[(2u * fftLen) + 1u] = 0.0f;
-
- pDst[0] = pSrc[0] + pSrc[1];
- pDst[1] = 0.0f;
-
-}
-
-
-/**
- * @brief Core Real IFFT process
- * @param[in] *pSrc points to the input buffer.
- * @param[in] fftLen length of FFT.
- * @param[in] *pATable points to the twiddle Coef A buffer.
- * @param[in] *pBTable points to the twiddle Coef B buffer.
- * @param[out] *pDst points to the output buffer.
- * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
- * @return none.
- */
-
-void arm_split_rifft_f32(
- float32_t * pSrc,
- uint32_t fftLen,
- float32_t * pATable,
- float32_t * pBTable,
- float32_t * pDst,
- uint32_t modifier)
-{
- float32_t outR, outI; /* Temporary variables for output */
- float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
- float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
-
- pCoefA = &pATable[0];
- pCoefB = &pBTable[0];
-
- while (fftLen > 0u)
- {
- /*
- outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
-
- outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
-
- */
-
- CoefA1 = *pCoefA++;
- CoefA2 = *pCoefA;
-
- /* outR = (pSrc[2 * i] * CoefA1 */
- outR = *pSrc1 * CoefA1;
-
- /* - pSrc[2 * i] * CoefA2 */
- outI = -(*pSrc1++) * CoefA2;
-
- /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
- outR += (*pSrc1 + *pSrc2) * CoefA2;
-
- /* pSrc[2 * i + 1] * CoefA1 */
- outI += (*pSrc1++) * CoefA1;
-
- CoefB1 = *pCoefB;
-
- /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
- outI -= *pSrc2-- * CoefB1;
-
- /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
- outR += *pSrc2 * CoefB1;
-
- /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
- outI += *pSrc2-- * CoefA2;
-
- /* write output */
- *pDst++ = outR;
- *pDst++ = outI;
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (modifier * 2u);
- pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
- /* Decrement loop count */
- fftLen--;
- }
-
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
deleted file mode 100644
index fe46896..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_f32.c
- * Description: RFFT & RIFFT Floating point process function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-void stage_rfft_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut)
-{
- uint32_t k; /* Loop Counter */
- float32_t twR, twI; /* RFFT Twiddle coefficients */
- float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
- float32_t *pA = p; /* increasing pointer */
- float32_t *pB = p; /* decreasing pointer */
- float32_t xAR, xAI, xBR, xBI; /* temporary variables */
- float32_t t1a, t1b; /* temporary variables */
- float32_t p0, p1, p2, p3; /* temporary variables */
-
-
- k = (S->Sint).fftLen - 1;
-
- /* Pack first and last sample of the frequency domain together */
-
- xBR = pB[0];
- xBI = pB[1];
- xAR = pA[0];
- xAI = pA[1];
-
- twR = *pCoeff++ ;
- twI = *pCoeff++ ;
-
- // U1 = XA(1) + XB(1); % It is real
- t1a = xBR + xAR ;
-
- // U2 = XB(1) - XA(1); % It is imaginary
- t1b = xBI + xAI ;
-
- // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
- // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
- *pOut++ = 0.5f * ( t1a + t1b );
- *pOut++ = 0.5f * ( t1a - t1b );
-
- // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) ));
- pB = p + 2*k;
- pA += 2;
-
- do
- {
- /*
- function X = my_split_rfft(X, ifftFlag)
- % X is a series of real numbers
- L = length(X);
- XC = X(1:2:end) +i*X(2:2:end);
- XA = fft(XC);
- XB = conj(XA([1 end:-1:2]));
- TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
- for l = 2:L/2
- XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
- end
- XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
- X = XA;
- */
-
- xBI = pB[1];
- xBR = pB[0];
- xAR = pA[0];
- xAI = pA[1];
-
- twR = *pCoeff++;
- twI = *pCoeff++;
-
- t1a = xBR - xAR ;
- t1b = xBI + xAI ;
-
- // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
- // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
- p0 = twR * t1a;
- p1 = twI * t1a;
- p2 = twR * t1b;
- p3 = twI * t1b;
-
- *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
- *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
-
- pA += 2;
- pB -= 2;
- k--;
- } while (k > 0u);
-}
-
-/* Prepares data for inverse cfft */
-void merge_rfft_f32(
-arm_rfft_fast_instance_f32 * S,
-float32_t * p, float32_t * pOut)
-{
- uint32_t k; /* Loop Counter */
- float32_t twR, twI; /* RFFT Twiddle coefficients */
- float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
- float32_t *pA = p; /* increasing pointer */
- float32_t *pB = p; /* decreasing pointer */
- float32_t xAR, xAI, xBR, xBI; /* temporary variables */
- float32_t t1a, t1b, r, s, t, u; /* temporary variables */
-
- k = (S->Sint).fftLen - 1;
-
- xAR = pA[0];
- xAI = pA[1];
-
- pCoeff += 2 ;
-
- *pOut++ = 0.5f * ( xAR + xAI );
- *pOut++ = 0.5f * ( xAR - xAI );
-
- pB = p + 2*k ;
- pA += 2 ;
-
- while (k > 0u)
- {
- /* G is half of the frequency complex spectrum */
- //for k = 2:N
- // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
- xBI = pB[1] ;
- xBR = pB[0] ;
- xAR = pA[0];
- xAI = pA[1];
-
- twR = *pCoeff++;
- twI = *pCoeff++;
-
- t1a = xAR - xBR ;
- t1b = xAI + xBI ;
-
- r = twR * t1a;
- s = twI * t1b;
- t = twI * t1a;
- u = twR * t1b;
-
- // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
- // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
- *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
- *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
-
- pA += 2;
- pB -= 2;
- k--;
- }
-
-}
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
- * @defgroup RealFFT Real FFT Functions
- *
- * \par
- * The CMSIS DSP library includes specialized algorithms for computing the
- * FFT of real data sequences. The FFT is defined over complex data but
- * in many applications the input is real. Real FFT algorithms take advantage
- * of the symmetry properties of the FFT and have a speed advantage over complex
- * algorithms of the same length.
- * \par
- * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
- * \par
- * The real length N forward FFT of a sequence is computed using the steps shown below.
- * \par
- * \image html RFFT.gif "Real Fast Fourier Transform"
- * \par
- * The real sequence is initially treated as if it were complex to perform a CFFT.
- * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
- * in complex format. Except the first complex number that contains the two real numbers
- * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
- * contains two real values packed.
- * \par
- * The input for the inverse RFFT should keep the same format as the output of the
- * forward RFFT. A first processing stage pre-process the data to later perform an
- * inverse CFFT.
- * \par
- * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
- * \par
- * The algorithms for floating-point, Q15, and Q31 data are slightly different
- * and we describe each algorithm in turn.
- * \par Floating-point
- * The main functions are arm_rfft_fast_f32() and arm_rfft_fast_init_f32().
- * The older functions arm_rfft_f32() and arm_rfft_init_f32() have been
- * deprecated but are still documented.
- * \par
- * The FFT of a real N-point sequence has even symmetry in the frequency
- * domain. The second half of the data equals the conjugate of the first
- * half flipped in frequency. Looking at the data, we see that we can
- * uniquely represent the FFT using only N/2 complex numbers. These are
- * packed into the output array in alternating real and imaginary
- * components:
- * \par
- * X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ...
- * real[(N/2)-1], imag[(N/2)-1 }
- * \par
- * It happens that the first complex number (real[0], imag[0]) is actually
- * all real. real[0] represents the DC offset, and imag[0] should be 0.
- * (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is
- * the first harmonic and so on.
- * \par
- * The real FFT functions pack the frequency domain data in this fashion.
- * The forward transform outputs the data in this form and the inverse
- * transform expects input data in this form. The function always performs
- * the needed bitreversal so that the input and output data is always in
- * normal order. The functions support lengths of [32, 64, 128, ..., 4096]
- * samples.
- * \par Q15 and Q31
- * The real algorithms are defined in a similar manner and utilize N/2 complex
- * transforms behind the scenes.
- * \par
- * The complex transforms used internally include scaling to prevent fixed-point
- * overflows. The overall scaling equals 1/(fftLen/2).
- * \par
- * A separate instance structure must be defined for each transform used but
- * twiddle factor and bit reversal tables can be reused.
- * \par
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.
- * - Initializes twiddle factor table and bit reversal table pointers.
- * - Initializes the internal complex FFT data structure.
- * \par
- * Use of the initialization function is optional.
- * However, if the initialization function is used, then the instance structure
- * cannot be placed into a const data section. To place an instance structure
- * into a const data section, the instance structure should be manually
- * initialized as follows:
- *
- *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
- *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
- *
- * where fftLenReal is the length of the real transform;
- * fftLenBy2 length of the internal complex transform.
- * ifftFlagR Selects forward (=0) or inverse (=1) transform.
- * bitReverseFlagR Selects bit reversed output (=0) or normal order
- * output (=1).
- * twidCoefRModifier stride modifier for the twiddle factor table.
- * The value is based on the FFT length;
- * pTwiddleARealpoints to the A array of twiddle coefficients;
- * pTwiddleBRealpoints to the B array of twiddle coefficients;
- * pCfft points to the CFFT Instance structure. The CFFT structure
- * must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding
- * static initialization of the complex FFT instance structure.
- */
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Processing function for the floating-point real FFT.
-* @param[in] *S points to an arm_rfft_fast_instance_f32 structure.
-* @param[in] *p points to the input buffer.
-* @param[in] *pOut points to the output buffer.
-* @param[in] ifftFlag RFFT if flag is 0, RIFFT if flag is 1
-* @return none.
-*/
-
-void arm_rfft_fast_f32(
-arm_rfft_fast_instance_f32 * S,
-float32_t * p, float32_t * pOut,
-uint8_t ifftFlag)
-{
- arm_cfft_instance_f32 * Sint = &(S->Sint);
- Sint->fftLen = S->fftLenRFFT / 2;
-
- /* Calculation of Real FFT */
- if (ifftFlag)
- {
- /* Real FFT compression */
- merge_rfft_f32(S, p, pOut);
-
- /* Complex radix-4 IFFT process */
- arm_cfft_f32( Sint, pOut, ifftFlag, 1);
- }
- else
- {
- /* Calculation of RFFT of input */
- arm_cfft_f32( Sint, p, ifftFlag, 1);
-
- /* Real FFT extraction */
- stage_rfft_f32(S, p, pOut);
- }
-}
-
-/**
-* @} end of RealFFT group
-*/
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
deleted file mode 100644
index 0abc57f..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_cfft_init_f32.c
- * Description: Split Radix Decimation in Frequency CFFT Floating point processing function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**
- * @ingroup groupTransforms
- */
-
-/**
- * @addtogroup RealFFT
- * @{
- */
-
-/**
-* @brief Initialization function for the floating-point real FFT.
-* @param[in,out] *S points to an arm_rfft_fast_instance_f32 structure.
-* @param[in] fftLen length of the Real Sequence.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter fftLen Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096.
-* \par
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
-*/
-arm_status arm_rfft_fast_init_f32(
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen)
-{
- arm_cfft_instance_f32 * Sint;
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
- /* Initialise the FFT length */
- Sint = &(S->Sint);
- Sint->fftLen = fftLen/2;
- S->fftLenRFFT = fftLen;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (Sint->fftLen)
- {
- case 2048u:
- /* Initializations of structure parameters for 2048 point FFT */
- /* Initialise the bit reversal table length */
- Sint->bitRevLength = ARMBITREVINDEXTABLE_2048_TABLE_LENGTH;
- /* Initialise the bit reversal table pointer */
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
- /* Initialise the Twiddle coefficient pointers */
- Sint->pTwiddle = (float32_t *) twiddleCoef_2048;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096;
- break;
- case 1024u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_1024_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
- Sint->pTwiddle = (float32_t *) twiddleCoef_1024;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048;
- break;
- case 512u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
- Sint->pTwiddle = (float32_t *) twiddleCoef_512;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024;
- break;
- case 256u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
- Sint->pTwiddle = (float32_t *) twiddleCoef_256;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512;
- break;
- case 128u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
- Sint->pTwiddle = (float32_t *) twiddleCoef_128;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256;
- break;
- case 64u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_64_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
- Sint->pTwiddle = (float32_t *) twiddleCoef_64;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128;
- break;
- case 32u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_32_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
- Sint->pTwiddle = (float32_t *) twiddleCoef_32;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64;
- break;
- case 16u:
- Sint->bitRevLength = ARMBITREVINDEXTABLE_16_TABLE_LENGTH;
- Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
- Sint->pTwiddle = (float32_t *) twiddleCoef_16;
- S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32;
- break;
- default:
- /* Reporting argument error if fftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- return (status);
-}
-
-/**
- * @} end of RealFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
deleted file mode 100644
index eebef0e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
+++ /dev/null
@@ -1,4273 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_init_f32.c
- * Description: RFFT & RIFFT Floating point initialisation function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/**
- * @ingroup RealFFT
- */
-
-/**
- * @addtogroup RealFFT_Table Real FFT Tables
- * @{
- */
-
-/**
-* \par
-* Generation of realCoefA array:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
-* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-*/
-static const float32_t realCoefA[8192] = {
- 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f,
- 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f,
- 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f,
- 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f,
- 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f,
- 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f,
- 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f,
- 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f,
- 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f,
- 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f,
- 0.492330402135849f, -0.499941170215607f, 0.491946935653687f, -0.499935150146484f,
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- 0.438033521175385f, 0.496145308017731f, 0.438414067029953f, 0.496192663908005f,
- 0.438794672489166f, 0.496239781379700f, 0.439175277948380f, 0.496286571025848f,
- 0.439555943012238f, 0.496333062648773f, 0.439936667680740f, 0.496379286050797f,
- 0.440317392349243f, 0.496425211429596f, 0.440698176622391f, 0.496470838785172f,
- 0.441078960895538f, 0.496516168117523f, 0.441459804773331f, 0.496561229228973f,
- 0.441840678453445f, 0.496605962514877f, 0.442221581935883f, 0.496650427579880f,
- 0.442602545022964f, 0.496694594621658f, 0.442983508110046f, 0.496738493442535f,
- 0.443364530801773f, 0.496782064437866f, 0.443745553493500f, 0.496825367212296f,
- 0.444126635789871f, 0.496868371963501f, 0.444507747888565f, 0.496911078691483f,
- 0.444888889789581f, 0.496953487396240f, 0.445270061492920f, 0.496995598077774f,
- 0.445651292800903f, 0.497037440538406f, 0.446032524108887f, 0.497078984975815f,
- 0.446413785219193f, 0.497120231389999f, 0.446795076131821f, 0.497161179780960f,
- 0.447176426649094f, 0.497201830148697f, 0.447557777166367f, 0.497242212295532f,
- 0.447939187288284f, 0.497282296419144f, 0.448320597410202f, 0.497322082519531f,
- 0.448702067136765f, 0.497361570596695f, 0.449083566665649f, 0.497400760650635f,
- 0.449465066194534f, 0.497439652681351f, 0.449846625328064f, 0.497478276491165f,
- 0.450228184461594f, 0.497516602277756f, 0.450609803199768f, 0.497554630041122f,
- 0.450991421937943f, 0.497592359781265f, 0.451373100280762f, 0.497629791498184f,
- 0.451754778623581f, 0.497666954994202f, 0.452136516571045f, 0.497703820466995f,
- 0.452518254518509f, 0.497740387916565f, 0.452900022268295f, 0.497776657342911f,
- 0.453281819820404f, 0.497812628746033f, 0.453663676977158f, 0.497848302125931f,
- 0.454045534133911f, 0.497883707284927f, 0.454427421092987f, 0.497918814420700f,
- 0.454809308052063f, 0.497953623533249f, 0.455191254615784f, 0.497988134622574f,
- 0.455573230981827f, 0.498022347688675f, 0.455955207347870f, 0.498056292533875f,
- 0.456337243318558f, 0.498089909553528f, 0.456719279289246f, 0.498123258352280f,
- 0.457101345062256f, 0.498156309127808f, 0.457483440637589f, 0.498189061880112f,
- 0.457865566015244f, 0.498221516609192f, 0.458247691392899f, 0.498253703117371f,
- 0.458629876375198f, 0.498285561800003f, 0.459012061357498f, 0.498317152261734f,
- 0.459394276142120f, 0.498348444700241f, 0.459776520729065f, 0.498379439115524f,
- 0.460158795118332f, 0.498410135507584f, 0.460541069507599f, 0.498440563678741f,
- 0.460923373699188f, 0.498470664024353f, 0.461305707693100f, 0.498500496149063f,
- 0.461688071489334f, 0.498530030250549f, 0.462070435285568f, 0.498559266328812f,
- 0.462452858686447f, 0.498588204383850f, 0.462835282087326f, 0.498616874217987f,
- 0.463217705488205f, 0.498645216226578f, 0.463600188493729f, 0.498673290014267f,
- 0.463982671499252f, 0.498701065778732f, 0.464365184307098f, 0.498728543519974f,
- 0.464747726917267f, 0.498755723237991f, 0.465130269527435f, 0.498782604932785f,
- 0.465512841939926f, 0.498809218406677f, 0.465895414352417f, 0.498835533857346f,
- 0.466278046369553f, 0.498861521482468f, 0.466660678386688f, 0.498887240886688f,
- 0.467043310403824f, 0.498912662267685f, 0.467426002025604f, 0.498937815427780f,
- 0.467808693647385f, 0.498962640762329f, 0.468191385269165f, 0.498987197875977f,
- 0.468574106693268f, 0.499011427164078f, 0.468956857919693f, 0.499035388231277f,
- 0.469339638948441f, 0.499059051275253f, 0.469722419977188f, 0.499082416296005f,
- 0.470105201005936f, 0.499105513095856f, 0.470488041639328f, 0.499128282070160f,
- 0.470870882272720f, 0.499150782823563f, 0.471253722906113f, 0.499172955751419f,
- 0.471636593341827f, 0.499194860458374f, 0.472019463777542f, 0.499216467142105f,
- 0.472402364015579f, 0.499237775802612f, 0.472785294055939f, 0.499258816242218f,
- 0.473168224096298f, 0.499279528856277f, 0.473551183938980f, 0.499299973249435f,
- 0.473934143781662f, 0.499320119619370f, 0.474317133426666f, 0.499339967966080f,
- 0.474700123071671f, 0.499359518289566f, 0.475083142518997f, 0.499378770589828f,
- 0.475466161966324f, 0.499397724866867f, 0.475849211215973f, 0.499416410923004f,
- 0.476232260465622f, 0.499434769153595f, 0.476615339517593f, 0.499452859163284f,
- 0.476998418569565f, 0.499470651149750f, 0.477381497621536f, 0.499488145112991f,
- 0.477764606475830f, 0.499505341053009f, 0.478147745132446f, 0.499522238969803f,
- 0.478530883789063f, 0.499538868665695f, 0.478914022445679f, 0.499555170536041f,
- 0.479297190904617f, 0.499571204185486f, 0.479680359363556f, 0.499586939811707f,
- 0.480063527822495f, 0.499602377414703f, 0.480446726083755f, 0.499617516994476f,
- 0.480829954147339f, 0.499632388353348f, 0.481213152408600f, 0.499646931886673f,
- 0.481596380472183f, 0.499661177396774f, 0.481979638338089f, 0.499675154685974f,
- 0.482362866401672f, 0.499688833951950f, 0.482746154069901f, 0.499702215194702f,
- 0.483129411935806f, 0.499715298414230f, 0.483512699604034f, 0.499728083610535f,
- 0.483895987272263f, 0.499740600585938f, 0.484279274940491f, 0.499752789735794f,
- 0.484662592411041f, 0.499764710664749f, 0.485045909881592f, 0.499776333570480f,
- 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f,
- 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f,
- 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f,
- 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f,
- 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f,
- 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f,
- 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f,
- 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f,
- 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f,
- 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f,
- 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f,
- 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f,
- 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f,
- 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f,
- 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f,
- 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f,
- 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f,
- 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f,
- 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f,
-};
-
-
-/**
-* \par
-* Generation of realCoefB array:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
-* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-*
-*/
-static const float32_t realCoefB[8192] = {
- 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f,
- 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f,
- 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f,
- 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f,
- 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f,
- 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f,
- 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f,
- 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f,
- 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f,
- 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f,
- 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f,
- 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f,
- 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f,
- 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f,
- 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f,
- 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f,
- 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f,
- 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f,
- 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f,
- 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f,
- 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f,
- 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f,
- 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f,
- 0.517637133598328f, 0.499688833951950f, 0.518020391464233f, 0.499675154685974f,
- 0.518403589725494f, 0.499661177396774f, 0.518786847591400f, 0.499646931886673f,
- 0.519170045852661f, 0.499632388353348f, 0.519553244113922f, 0.499617516994476f,
- 0.519936442375183f, 0.499602377414703f, 0.520319640636444f, 0.499586939811707f,
- 0.520702838897705f, 0.499571204185486f, 0.521085977554321f, 0.499555170536041f,
- 0.521469116210938f, 0.499538868665695f, 0.521852254867554f, 0.499522238969803f,
- 0.522235393524170f, 0.499505341053009f, 0.522618472576141f, 0.499488145112991f,
- 0.523001611232758f, 0.499470651149750f, 0.523384690284729f, 0.499452859163284f,
- 0.523767769336700f, 0.499434769153595f, 0.524150788784027f, 0.499416410923004f,
- 0.524533808231354f, 0.499397724866867f, 0.524916887283325f, 0.499378770589828f,
- 0.525299847126007f, 0.499359518289566f, 0.525682866573334f, 0.499339967966080f,
- 0.526065826416016f, 0.499320119619370f, 0.526448845863342f, 0.499299973249435f,
- 0.526831746101379f, 0.499279528856277f, 0.527214705944061f, 0.499258816242218f,
- 0.527597606182098f, 0.499237775802612f, 0.527980506420136f, 0.499216467142105f,
- 0.528363406658173f, 0.499194860458374f, 0.528746306896210f, 0.499172955751419f,
- 0.529129147529602f, 0.499150782823563f, 0.529511988162994f, 0.499128282070160f,
- 0.529894769191742f, 0.499105513095856f, 0.530277609825134f, 0.499082416296005f,
- 0.530660390853882f, 0.499059051275253f, 0.531043112277985f, 0.499035388231277f,
- 0.531425893306732f, 0.499011427164078f, 0.531808614730835f, 0.498987197875977f,
- 0.532191336154938f, 0.498962640762329f, 0.532573997974396f, 0.498937815427780f,
- 0.532956659793854f, 0.498912662267685f, 0.533339321613312f, 0.498887240886688f,
- 0.533721983432770f, 0.498861521482468f, 0.534104585647583f, 0.498835533857346f,
- 0.534487187862396f, 0.498809218406677f, 0.534869730472565f, 0.498782604932785f,
- 0.535252273082733f, 0.498755723237991f, 0.535634815692902f, 0.498728543519974f,
- 0.536017298698425f, 0.498701065778732f, 0.536399841308594f, 0.498673290014267f,
- 0.536782264709473f, 0.498645216226578f, 0.537164747714996f, 0.498616874217987f,
- 0.537547171115875f, 0.498588204383850f, 0.537929534912109f, 0.498559266328812f,
- 0.538311958312988f, 0.498530030250549f, 0.538694262504578f, 0.498500496149063f,
- 0.539076626300812f, 0.498470664024353f, 0.539458930492401f, 0.498440563678741f,
- 0.539841234683990f, 0.498410135507584f, 0.540223479270935f, 0.498379439115524f,
- 0.540605723857880f, 0.498348444700241f, 0.540987968444824f, 0.498317152261734f,
- 0.541370153427124f, 0.498285561800003f, 0.541752278804779f, 0.498253703117371f,
- 0.542134463787079f, 0.498221516609192f, 0.542516589164734f, 0.498189061880112f,
- 0.542898654937744f, 0.498156309127808f, 0.543280720710754f, 0.498123258352280f,
- 0.543662786483765f, 0.498089909553528f, 0.544044792652130f, 0.498056292533875f,
- 0.544426798820496f, 0.498022347688675f, 0.544808745384216f, 0.497988134622574f,
- 0.545190691947937f, 0.497953623533249f, 0.545572578907013f, 0.497918814420700f,
- 0.545954465866089f, 0.497883707284927f, 0.546336352825165f, 0.497848302125931f,
- 0.546718180179596f, 0.497812628746033f, 0.547099947929382f, 0.497776657342911f,
- 0.547481775283813f, 0.497740387916565f, 0.547863483428955f, 0.497703820466995f,
- 0.548245191574097f, 0.497666954994202f, 0.548626899719238f, 0.497629791498184f,
- 0.549008548259735f, 0.497592359781265f, 0.549390196800232f, 0.497554630041122f,
- 0.549771785736084f, 0.497516602277756f, 0.550153374671936f, 0.497478276491165f,
- 0.550534904003143f, 0.497439652681351f, 0.550916433334351f, 0.497400760650635f,
- 0.551297962665558f, 0.497361570596695f, 0.551679372787476f, 0.497322082519531f,
- 0.552060842514038f, 0.497282296419144f, 0.552442193031311f, 0.497242212295532f,
- 0.552823603153229f, 0.497201830148697f, 0.553204894065857f, 0.497161179780960f,
- 0.553586184978485f, 0.497120231389999f, 0.553967475891113f, 0.497078984975815f,
- 0.554348707199097f, 0.497037440538406f, 0.554729938507080f, 0.496995598077774f,
- 0.555111110210419f, 0.496953487396240f, 0.555492222309113f, 0.496911078691483f,
- 0.555873334407806f, 0.496868371963501f, 0.556254446506500f, 0.496825367212296f,
- 0.556635499000549f, 0.496782064437866f, 0.557016491889954f, 0.496738493442535f,
- 0.557397484779358f, 0.496694594621658f, 0.557778418064117f, 0.496650427579880f,
- 0.558159291744232f, 0.496605962514877f, 0.558540165424347f, 0.496561229228973f,
- 0.558921039104462f, 0.496516168117523f, 0.559301853179932f, 0.496470838785172f,
- 0.559682607650757f, 0.496425211429596f, 0.560063362121582f, 0.496379286050797f,
- 0.560444056987762f, 0.496333062648773f, 0.560824692249298f, 0.496286571025848f,
- 0.561205327510834f, 0.496239781379700f, 0.561585903167725f, 0.496192663908005f,
- 0.561966478824615f, 0.496145308017731f, 0.562346994876862f, 0.496097624301910f,
- 0.562727510929108f, 0.496049642562866f, 0.563107967376709f, 0.496001392602921f,
- 0.563488364219666f, 0.495952844619751f, 0.563868701457977f, 0.495903998613358f,
- 0.564249038696289f, 0.495854884386063f, 0.564629375934601f, 0.495805442333221f,
- 0.565009593963623f, 0.495755732059479f, 0.565389811992645f, 0.495705723762512f,
- 0.565770030021667f, 0.495655417442322f, 0.566150128841400f, 0.495604842901230f,
- 0.566530287265778f, 0.495553970336914f, 0.566910326480865f, 0.495502769947052f,
- 0.567290365695953f, 0.495451331138611f, 0.567670345306396f, 0.495399564504623f,
- 0.568050265312195f, 0.495347499847412f, 0.568430185317993f, 0.495295166969299f,
- 0.568810045719147f, 0.495242536067963f, 0.569189906120300f, 0.495189607143402f,
- 0.569569647312164f, 0.495136409997940f, 0.569949388504028f, 0.495082914829254f,
- 0.570329129695892f, 0.495029091835022f, 0.570708811283112f, 0.494975030422211f,
- 0.571088373661041f, 0.494920641183853f, 0.571467995643616f, 0.494865983724594f,
- 0.571847498416901f, 0.494810998439789f, 0.572227001190186f, 0.494755744934082f,
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- 0.508436501026154f, -0.499928832054138f, 0.508053064346313f, -0.499935150146484f,
- 0.507669627666473f, -0.499941170215607f, 0.507286131381989f, -0.499946922063828f,
- 0.506902694702148f, -0.499952346086502f, 0.506519258022308f, -0.499957501888275f,
- 0.506135761737823f, -0.499962359666824f, 0.505752325057983f, -0.499966919422150f,
- 0.505368828773499f, -0.499971181154251f, 0.504985332489014f, -0.499975144863129f,
- 0.504601895809174f, -0.499978810548782f, 0.504218399524689f, -0.499982208013535f,
- 0.503834903240204f, -0.499985307455063f, 0.503451406955719f, -0.499988079071045f,
- 0.503067970275879f, -0.499990582466125f, 0.502684473991394f, -0.499992787837982f,
- 0.502300977706909f, -0.499994695186615f, 0.501917481422424f, -0.499996334314346f,
- 0.501533985137939f, -0.499997645616531f, 0.501150488853455f, -0.499998688697815f,
- 0.500766992568970f, -0.499999403953552f, 0.500383496284485f, -0.499999850988388f,
-};
-
-
-
-/**
-* @brief Initialization function for the floating-point RFFT/RIFFT.
-* @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
-* in the future.
-* @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
-* @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
-* @param[in] fftLenReal length of the FFT.
-* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
-* \par
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* This function also initializes Twiddle factor table.
-*/
-
-/**
-* @} end of RealFFT_Table group
-*/
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag)
-{
-
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialize the Real FFT length */
- S->fftLenReal = (uint16_t) fftLenReal;
-
- /* Initialize the Complex FFT length */
- S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
-
- /* Initialize the Twiddle coefficientA pointer */
- S->pTwiddleAReal = (float32_t *) realCoefA;
-
- /* Initialize the Twiddle coefficientB pointer */
- S->pTwiddleBReal = (float32_t *) realCoefB;
-
- /* Initialize the Flag for selection of RFFT or RIFFT */
- S->ifftFlagR = (uint8_t) ifftFlagR;
-
- /* Initialize the Flag for calculation Bit reversal or not */
- S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
- /* Initializations of structure parameters depending on the FFT length */
- switch (S->fftLenReal)
- {
- /* Init table modifier value */
- case 8192u:
- S->twidCoefRModifier = 1u;
- break;
- case 2048u:
- S->twidCoefRModifier = 4u;
- break;
- case 512u:
- S->twidCoefRModifier = 16u;
- break;
- case 128u:
- S->twidCoefRModifier = 64u;
- break;
- default:
- /* Reporting argument error if rfftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- /* Init Complex FFT Instance */
- S->pCfft = S_CFFT;
-
- if (S->ifftFlagR)
- {
- /* Initializes the CIFFT Module for fftLenreal/2 length */
- arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
- }
- else
- {
- /* Initializes the CFFT Module for fftLenreal/2 length */
- arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
- }
-
- /* return the status of RFFT Init function */
- return (status);
-
-}
-
- /**
- * @} end of RealFFT group
- */
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c
deleted file mode 100644
index 83c45fe..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c
+++ /dev/null
@@ -1,2229 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_init_q15.c
- * Description: RFFT & RIFFT Q15 initialisation function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include "arm_const_structs.h"
-
-/**
-* @ingroup RealFFT
-*/
-
-/**
- * @addtogroup RealFFT_Table Real FFT Tables
-* @{
-*/
-
-/**
-* \par
-* Generation fixed-point realCoefAQ15 array in Q15 format:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
-* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-* \par
-* Convert to fixed point Q15 format
-* round(pATable[i] * pow(2, 15))
-*/
-const q15_t ALIGN4 realCoefAQ15[8192] = {
- (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000,
- (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000,
- (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001,
- (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001,
- (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002,
- (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003,
- (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004,
- (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005,
- (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006,
- (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007,
- (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009,
- (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b,
- (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d,
- (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f,
- (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011,
- (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013,
- (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016,
- (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018,
- (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b,
- (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e,
- (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021,
- (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024,
- (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028,
- (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b,
- (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f,
- (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033,
- (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037,
- (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b,
- (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040,
- (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044,
- (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049,
- (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e,
- (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053,
- (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058,
- (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d,
- (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062,
- (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068,
- (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e,
- (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074,
- (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a,
- (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080,
- (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086,
- (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d,
- (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093,
- (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a,
- (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1,
- (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8,
- (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, (q15_t)0x36a8, (q15_t)0xc0af,
- (q15_t)0x369c, (q15_t)0xc0b1, (q15_t)0x3690, (q15_t)0xc0b3, (q15_t)0x3683, (q15_t)0xc0b5, (q15_t)0x3677, (q15_t)0xc0b7,
- (q15_t)0x366a, (q15_t)0xc0b9, (q15_t)0x365e, (q15_t)0xc0bb, (q15_t)0x3651, (q15_t)0xc0bd, (q15_t)0x3645, (q15_t)0xc0be,
- (q15_t)0x3639, (q15_t)0xc0c0, (q15_t)0x362c, (q15_t)0xc0c2, (q15_t)0x3620, (q15_t)0xc0c4, (q15_t)0x3613, (q15_t)0xc0c6,
- (q15_t)0x3607, (q15_t)0xc0c8, (q15_t)0x35fa, (q15_t)0xc0ca, (q15_t)0x35ee, (q15_t)0xc0cc, (q15_t)0x35e2, (q15_t)0xc0ce,
- (q15_t)0x35d5, (q15_t)0xc0d0, (q15_t)0x35c9, (q15_t)0xc0d2, (q15_t)0x35bc, (q15_t)0xc0d4, (q15_t)0x35b0, (q15_t)0xc0d6,
- (q15_t)0x35a4, (q15_t)0xc0d8, (q15_t)0x3597, (q15_t)0xc0da, (q15_t)0x358b, (q15_t)0xc0dc, (q15_t)0x357e, (q15_t)0xc0de,
- (q15_t)0x3572, (q15_t)0xc0e0, (q15_t)0x3566, (q15_t)0xc0e2, (q15_t)0x3559, (q15_t)0xc0e4, (q15_t)0x354d, (q15_t)0xc0e7,
- (q15_t)0x3540, (q15_t)0xc0e9, (q15_t)0x3534, (q15_t)0xc0eb, (q15_t)0x3528, (q15_t)0xc0ed, (q15_t)0x351b, (q15_t)0xc0ef,
- (q15_t)0x350f, (q15_t)0xc0f1, (q15_t)0x3503, (q15_t)0xc0f3, (q15_t)0x34f6, (q15_t)0xc0f6, (q15_t)0x34ea, (q15_t)0xc0f8,
- (q15_t)0x34dd, (q15_t)0xc0fa, (q15_t)0x34d1, (q15_t)0xc0fc, (q15_t)0x34c5, (q15_t)0xc0fe, (q15_t)0x34b8, (q15_t)0xc100,
- (q15_t)0x34ac, (q15_t)0xc103, (q15_t)0x34a0, (q15_t)0xc105, (q15_t)0x3493, (q15_t)0xc107, (q15_t)0x3487, (q15_t)0xc109,
- (q15_t)0x347b, (q15_t)0xc10c, (q15_t)0x346e, (q15_t)0xc10e, (q15_t)0x3462, (q15_t)0xc110, (q15_t)0x3455, (q15_t)0xc113,
- (q15_t)0x3449, (q15_t)0xc115, (q15_t)0x343d, (q15_t)0xc117, (q15_t)0x3430, (q15_t)0xc119, (q15_t)0x3424, (q15_t)0xc11c,
- (q15_t)0x3418, (q15_t)0xc11e, (q15_t)0x340b, (q15_t)0xc120, (q15_t)0x33ff, (q15_t)0xc123, (q15_t)0x33f3, (q15_t)0xc125,
- (q15_t)0x33e6, (q15_t)0xc128, (q15_t)0x33da, (q15_t)0xc12a, (q15_t)0x33ce, (q15_t)0xc12c, (q15_t)0x33c1, (q15_t)0xc12f,
- (q15_t)0x33b5, (q15_t)0xc131, (q15_t)0x33a9, (q15_t)0xc134, (q15_t)0x339c, (q15_t)0xc136, (q15_t)0x3390, (q15_t)0xc138,
- (q15_t)0x3384, (q15_t)0xc13b, (q15_t)0x3377, (q15_t)0xc13d, (q15_t)0x336b, (q15_t)0xc140, (q15_t)0x335f, (q15_t)0xc142,
- (q15_t)0x3352, (q15_t)0xc145, (q15_t)0x3346, (q15_t)0xc147, (q15_t)0x333a, (q15_t)0xc14a, (q15_t)0x332d, (q15_t)0xc14c,
- (q15_t)0x3321, (q15_t)0xc14f, (q15_t)0x3315, (q15_t)0xc151, (q15_t)0x3308, (q15_t)0xc154, (q15_t)0x32fc, (q15_t)0xc156,
- (q15_t)0x32f0, (q15_t)0xc159, (q15_t)0x32e4, (q15_t)0xc15b, (q15_t)0x32d7, (q15_t)0xc15e, (q15_t)0x32cb, (q15_t)0xc161,
- (q15_t)0x32bf, (q15_t)0xc163, (q15_t)0x32b2, (q15_t)0xc166, (q15_t)0x32a6, (q15_t)0xc168, (q15_t)0x329a, (q15_t)0xc16b,
- (q15_t)0x328e, (q15_t)0xc16e, (q15_t)0x3281, (q15_t)0xc170, (q15_t)0x3275, (q15_t)0xc173, (q15_t)0x3269, (q15_t)0xc176,
- (q15_t)0x325c, (q15_t)0xc178, (q15_t)0x3250, (q15_t)0xc17b, (q15_t)0x3244, (q15_t)0xc17e, (q15_t)0x3238, (q15_t)0xc180,
- (q15_t)0x322b, (q15_t)0xc183, (q15_t)0x321f, (q15_t)0xc186, (q15_t)0x3213, (q15_t)0xc189, (q15_t)0x3207, (q15_t)0xc18b,
- (q15_t)0x31fa, (q15_t)0xc18e, (q15_t)0x31ee, (q15_t)0xc191, (q15_t)0x31e2, (q15_t)0xc194, (q15_t)0x31d5, (q15_t)0xc196,
- (q15_t)0x31c9, (q15_t)0xc199, (q15_t)0x31bd, (q15_t)0xc19c, (q15_t)0x31b1, (q15_t)0xc19f, (q15_t)0x31a4, (q15_t)0xc1a2,
- (q15_t)0x3198, (q15_t)0xc1a4, (q15_t)0x318c, (q15_t)0xc1a7, (q15_t)0x3180, (q15_t)0xc1aa, (q15_t)0x3174, (q15_t)0xc1ad,
- (q15_t)0x3167, (q15_t)0xc1b0, (q15_t)0x315b, (q15_t)0xc1b3, (q15_t)0x314f, (q15_t)0xc1b6, (q15_t)0x3143, (q15_t)0xc1b8,
- (q15_t)0x3136, (q15_t)0xc1bb, (q15_t)0x312a, (q15_t)0xc1be, (q15_t)0x311e, (q15_t)0xc1c1, (q15_t)0x3112, (q15_t)0xc1c4,
- (q15_t)0x3105, (q15_t)0xc1c7, (q15_t)0x30f9, (q15_t)0xc1ca, (q15_t)0x30ed, (q15_t)0xc1cd, (q15_t)0x30e1, (q15_t)0xc1d0,
- (q15_t)0x30d5, (q15_t)0xc1d3, (q15_t)0x30c8, (q15_t)0xc1d6, (q15_t)0x30bc, (q15_t)0xc1d9, (q15_t)0x30b0, (q15_t)0xc1dc,
- (q15_t)0x30a4, (q15_t)0xc1df, (q15_t)0x3098, (q15_t)0xc1e2, (q15_t)0x308b, (q15_t)0xc1e5, (q15_t)0x307f, (q15_t)0xc1e8,
- (q15_t)0x3073, (q15_t)0xc1eb, (q15_t)0x3067, (q15_t)0xc1ee, (q15_t)0x305b, (q15_t)0xc1f1, (q15_t)0x304e, (q15_t)0xc1f4,
- (q15_t)0x3042, (q15_t)0xc1f7, (q15_t)0x3036, (q15_t)0xc1fa, (q15_t)0x302a, (q15_t)0xc1fd, (q15_t)0x301e, (q15_t)0xc201,
- (q15_t)0x3012, (q15_t)0xc204, (q15_t)0x3005, (q15_t)0xc207, (q15_t)0x2ff9, (q15_t)0xc20a, (q15_t)0x2fed, (q15_t)0xc20d,
- (q15_t)0x2fe1, (q15_t)0xc210, (q15_t)0x2fd5, (q15_t)0xc213, (q15_t)0x2fc9, (q15_t)0xc217, (q15_t)0x2fbc, (q15_t)0xc21a,
- (q15_t)0x2fb0, (q15_t)0xc21d, (q15_t)0x2fa4, (q15_t)0xc220, (q15_t)0x2f98, (q15_t)0xc223, (q15_t)0x2f8c, (q15_t)0xc227,
- (q15_t)0x2f80, (q15_t)0xc22a, (q15_t)0x2f74, (q15_t)0xc22d, (q15_t)0x2f67, (q15_t)0xc230, (q15_t)0x2f5b, (q15_t)0xc234,
- (q15_t)0x2f4f, (q15_t)0xc237, (q15_t)0x2f43, (q15_t)0xc23a, (q15_t)0x2f37, (q15_t)0xc23e, (q15_t)0x2f2b, (q15_t)0xc241,
- (q15_t)0x2f1f, (q15_t)0xc244, (q15_t)0x2f13, (q15_t)0xc247, (q15_t)0x2f06, (q15_t)0xc24b, (q15_t)0x2efa, (q15_t)0xc24e,
- (q15_t)0x2eee, (q15_t)0xc251, (q15_t)0x2ee2, (q15_t)0xc255, (q15_t)0x2ed6, (q15_t)0xc258, (q15_t)0x2eca, (q15_t)0xc25c,
- (q15_t)0x2ebe, (q15_t)0xc25f, (q15_t)0x2eb2, (q15_t)0xc262, (q15_t)0x2ea6, (q15_t)0xc266, (q15_t)0x2e99, (q15_t)0xc269,
- (q15_t)0x2e8d, (q15_t)0xc26d, (q15_t)0x2e81, (q15_t)0xc270, (q15_t)0x2e75, (q15_t)0xc273, (q15_t)0x2e69, (q15_t)0xc277,
- (q15_t)0x2e5d, (q15_t)0xc27a, (q15_t)0x2e51, (q15_t)0xc27e, (q15_t)0x2e45, (q15_t)0xc281, (q15_t)0x2e39, (q15_t)0xc285,
- (q15_t)0x2e2d, (q15_t)0xc288, (q15_t)0x2e21, (q15_t)0xc28c, (q15_t)0x2e15, (q15_t)0xc28f, (q15_t)0x2e09, (q15_t)0xc293,
- (q15_t)0x2dfc, (q15_t)0xc296, (q15_t)0x2df0, (q15_t)0xc29a, (q15_t)0x2de4, (q15_t)0xc29d, (q15_t)0x2dd8, (q15_t)0xc2a1,
- (q15_t)0x2dcc, (q15_t)0xc2a5, (q15_t)0x2dc0, (q15_t)0xc2a8, (q15_t)0x2db4, (q15_t)0xc2ac, (q15_t)0x2da8, (q15_t)0xc2af,
- (q15_t)0x2d9c, (q15_t)0xc2b3, (q15_t)0x2d90, (q15_t)0xc2b7, (q15_t)0x2d84, (q15_t)0xc2ba, (q15_t)0x2d78, (q15_t)0xc2be,
- (q15_t)0x2d6c, (q15_t)0xc2c1, (q15_t)0x2d60, (q15_t)0xc2c5, (q15_t)0x2d54, (q15_t)0xc2c9, (q15_t)0x2d48, (q15_t)0xc2cc,
- (q15_t)0x2d3c, (q15_t)0xc2d0, (q15_t)0x2d30, (q15_t)0xc2d4, (q15_t)0x2d24, (q15_t)0xc2d8, (q15_t)0x2d18, (q15_t)0xc2db,
- (q15_t)0x2d0c, (q15_t)0xc2df, (q15_t)0x2d00, (q15_t)0xc2e3, (q15_t)0x2cf4, (q15_t)0xc2e6, (q15_t)0x2ce8, (q15_t)0xc2ea,
- (q15_t)0x2cdc, (q15_t)0xc2ee, (q15_t)0x2cd0, (q15_t)0xc2f2, (q15_t)0x2cc4, (q15_t)0xc2f5, (q15_t)0x2cb8, (q15_t)0xc2f9,
- (q15_t)0x2cac, (q15_t)0xc2fd, (q15_t)0x2ca0, (q15_t)0xc301, (q15_t)0x2c94, (q15_t)0xc305, (q15_t)0x2c88, (q15_t)0xc308,
- (q15_t)0x2c7c, (q15_t)0xc30c, (q15_t)0x2c70, (q15_t)0xc310, (q15_t)0x2c64, (q15_t)0xc314, (q15_t)0x2c58, (q15_t)0xc318,
- (q15_t)0x2c4c, (q15_t)0xc31c, (q15_t)0x2c40, (q15_t)0xc320, (q15_t)0x2c34, (q15_t)0xc323, (q15_t)0x2c28, (q15_t)0xc327,
- (q15_t)0x2c1c, (q15_t)0xc32b, (q15_t)0x2c10, (q15_t)0xc32f, (q15_t)0x2c05, (q15_t)0xc333, (q15_t)0x2bf9, (q15_t)0xc337,
- (q15_t)0x2bed, (q15_t)0xc33b, (q15_t)0x2be1, (q15_t)0xc33f, (q15_t)0x2bd5, (q15_t)0xc343, (q15_t)0x2bc9, (q15_t)0xc347,
- (q15_t)0x2bbd, (q15_t)0xc34b, (q15_t)0x2bb1, (q15_t)0xc34f, (q15_t)0x2ba5, (q15_t)0xc353, (q15_t)0x2b99, (q15_t)0xc357,
- (q15_t)0x2b8d, (q15_t)0xc35b, (q15_t)0x2b81, (q15_t)0xc35f, (q15_t)0x2b75, (q15_t)0xc363, (q15_t)0x2b6a, (q15_t)0xc367,
- (q15_t)0x2b5e, (q15_t)0xc36b, (q15_t)0x2b52, (q15_t)0xc36f, (q15_t)0x2b46, (q15_t)0xc373, (q15_t)0x2b3a, (q15_t)0xc377,
- (q15_t)0x2b2e, (q15_t)0xc37b, (q15_t)0x2b22, (q15_t)0xc37f, (q15_t)0x2b16, (q15_t)0xc383, (q15_t)0x2b0a, (q15_t)0xc387,
- (q15_t)0x2aff, (q15_t)0xc38c, (q15_t)0x2af3, (q15_t)0xc390, (q15_t)0x2ae7, (q15_t)0xc394, (q15_t)0x2adb, (q15_t)0xc398,
- (q15_t)0x2acf, (q15_t)0xc39c, (q15_t)0x2ac3, (q15_t)0xc3a0, (q15_t)0x2ab7, (q15_t)0xc3a5, (q15_t)0x2aac, (q15_t)0xc3a9,
- (q15_t)0x2aa0, (q15_t)0xc3ad, (q15_t)0x2a94, (q15_t)0xc3b1, (q15_t)0x2a88, (q15_t)0xc3b5, (q15_t)0x2a7c, (q15_t)0xc3ba,
- (q15_t)0x2a70, (q15_t)0xc3be, (q15_t)0x2a65, (q15_t)0xc3c2, (q15_t)0x2a59, (q15_t)0xc3c6, (q15_t)0x2a4d, (q15_t)0xc3ca,
- (q15_t)0x2a41, (q15_t)0xc3cf, (q15_t)0x2a35, (q15_t)0xc3d3, (q15_t)0x2a29, (q15_t)0xc3d7, (q15_t)0x2a1e, (q15_t)0xc3dc,
- (q15_t)0x2a12, (q15_t)0xc3e0, (q15_t)0x2a06, (q15_t)0xc3e4, (q15_t)0x29fa, (q15_t)0xc3e9, (q15_t)0x29ee, (q15_t)0xc3ed,
- (q15_t)0x29e3, (q15_t)0xc3f1, (q15_t)0x29d7, (q15_t)0xc3f6, (q15_t)0x29cb, (q15_t)0xc3fa, (q15_t)0x29bf, (q15_t)0xc3fe,
- (q15_t)0x29b4, (q15_t)0xc403, (q15_t)0x29a8, (q15_t)0xc407, (q15_t)0x299c, (q15_t)0xc40b, (q15_t)0x2990, (q15_t)0xc410,
- (q15_t)0x2984, (q15_t)0xc414, (q15_t)0x2979, (q15_t)0xc419, (q15_t)0x296d, (q15_t)0xc41d, (q15_t)0x2961, (q15_t)0xc422,
- (q15_t)0x2955, (q15_t)0xc426, (q15_t)0x294a, (q15_t)0xc42a, (q15_t)0x293e, (q15_t)0xc42f, (q15_t)0x2932, (q15_t)0xc433,
- (q15_t)0x2926, (q15_t)0xc438, (q15_t)0x291b, (q15_t)0xc43c, (q15_t)0x290f, (q15_t)0xc441, (q15_t)0x2903, (q15_t)0xc445,
- (q15_t)0x28f7, (q15_t)0xc44a, (q15_t)0x28ec, (q15_t)0xc44e, (q15_t)0x28e0, (q15_t)0xc453, (q15_t)0x28d4, (q15_t)0xc457,
- (q15_t)0x28c9, (q15_t)0xc45c, (q15_t)0x28bd, (q15_t)0xc461, (q15_t)0x28b1, (q15_t)0xc465, (q15_t)0x28a5, (q15_t)0xc46a,
- (q15_t)0x289a, (q15_t)0xc46e, (q15_t)0x288e, (q15_t)0xc473, (q15_t)0x2882, (q15_t)0xc478, (q15_t)0x2877, (q15_t)0xc47c,
- (q15_t)0x286b, (q15_t)0xc481, (q15_t)0x285f, (q15_t)0xc485, (q15_t)0x2854, (q15_t)0xc48a, (q15_t)0x2848, (q15_t)0xc48f,
- (q15_t)0x283c, (q15_t)0xc493, (q15_t)0x2831, (q15_t)0xc498, (q15_t)0x2825, (q15_t)0xc49d, (q15_t)0x2819, (q15_t)0xc4a1,
- (q15_t)0x280e, (q15_t)0xc4a6, (q15_t)0x2802, (q15_t)0xc4ab, (q15_t)0x27f6, (q15_t)0xc4b0, (q15_t)0x27eb, (q15_t)0xc4b4,
- (q15_t)0x27df, (q15_t)0xc4b9, (q15_t)0x27d3, (q15_t)0xc4be, (q15_t)0x27c8, (q15_t)0xc4c2, (q15_t)0x27bc, (q15_t)0xc4c7,
- (q15_t)0x27b1, (q15_t)0xc4cc, (q15_t)0x27a5, (q15_t)0xc4d1, (q15_t)0x2799, (q15_t)0xc4d6, (q15_t)0x278e, (q15_t)0xc4da,
- (q15_t)0x2782, (q15_t)0xc4df, (q15_t)0x2777, (q15_t)0xc4e4, (q15_t)0x276b, (q15_t)0xc4e9, (q15_t)0x275f, (q15_t)0xc4ee,
- (q15_t)0x2754, (q15_t)0xc4f2, (q15_t)0x2748, (q15_t)0xc4f7, (q15_t)0x273d, (q15_t)0xc4fc, (q15_t)0x2731, (q15_t)0xc501,
- (q15_t)0x2725, (q15_t)0xc506, (q15_t)0x271a, (q15_t)0xc50b, (q15_t)0x270e, (q15_t)0xc510, (q15_t)0x2703, (q15_t)0xc515,
- (q15_t)0x26f7, (q15_t)0xc51a, (q15_t)0x26ec, (q15_t)0xc51e, (q15_t)0x26e0, (q15_t)0xc523, (q15_t)0x26d4, (q15_t)0xc528,
- (q15_t)0x26c9, (q15_t)0xc52d, (q15_t)0x26bd, (q15_t)0xc532, (q15_t)0x26b2, (q15_t)0xc537, (q15_t)0x26a6, (q15_t)0xc53c,
- (q15_t)0x269b, (q15_t)0xc541, (q15_t)0x268f, (q15_t)0xc546, (q15_t)0x2684, (q15_t)0xc54b, (q15_t)0x2678, (q15_t)0xc550,
- (q15_t)0x266d, (q15_t)0xc555, (q15_t)0x2661, (q15_t)0xc55a, (q15_t)0x2656, (q15_t)0xc55f, (q15_t)0x264a, (q15_t)0xc564,
- (q15_t)0x263f, (q15_t)0xc569, (q15_t)0x2633, (q15_t)0xc56e, (q15_t)0x2628, (q15_t)0xc573, (q15_t)0x261c, (q15_t)0xc578,
- (q15_t)0x2611, (q15_t)0xc57e, (q15_t)0x2605, (q15_t)0xc583, (q15_t)0x25fa, (q15_t)0xc588, (q15_t)0x25ee, (q15_t)0xc58d,
- (q15_t)0x25e3, (q15_t)0xc592, (q15_t)0x25d7, (q15_t)0xc597, (q15_t)0x25cc, (q15_t)0xc59c, (q15_t)0x25c0, (q15_t)0xc5a1,
- (q15_t)0x25b5, (q15_t)0xc5a7, (q15_t)0x25a9, (q15_t)0xc5ac, (q15_t)0x259e, (q15_t)0xc5b1, (q15_t)0x2592, (q15_t)0xc5b6,
- (q15_t)0x2587, (q15_t)0xc5bb, (q15_t)0x257c, (q15_t)0xc5c1, (q15_t)0x2570, (q15_t)0xc5c6, (q15_t)0x2565, (q15_t)0xc5cb,
- (q15_t)0x2559, (q15_t)0xc5d0, (q15_t)0x254e, (q15_t)0xc5d5, (q15_t)0x2542, (q15_t)0xc5db, (q15_t)0x2537, (q15_t)0xc5e0,
- (q15_t)0x252c, (q15_t)0xc5e5, (q15_t)0x2520, (q15_t)0xc5ea, (q15_t)0x2515, (q15_t)0xc5f0, (q15_t)0x2509, (q15_t)0xc5f5,
- (q15_t)0x24fe, (q15_t)0xc5fa, (q15_t)0x24f3, (q15_t)0xc600, (q15_t)0x24e7, (q15_t)0xc605, (q15_t)0x24dc, (q15_t)0xc60a,
- (q15_t)0x24d0, (q15_t)0xc610, (q15_t)0x24c5, (q15_t)0xc615, (q15_t)0x24ba, (q15_t)0xc61a, (q15_t)0x24ae, (q15_t)0xc620,
- (q15_t)0x24a3, (q15_t)0xc625, (q15_t)0x2498, (q15_t)0xc62a, (q15_t)0x248c, (q15_t)0xc630, (q15_t)0x2481, (q15_t)0xc635,
- (q15_t)0x2476, (q15_t)0xc63b, (q15_t)0x246a, (q15_t)0xc640, (q15_t)0x245f, (q15_t)0xc645, (q15_t)0x2454, (q15_t)0xc64b,
- (q15_t)0x2448, (q15_t)0xc650, (q15_t)0x243d, (q15_t)0xc656, (q15_t)0x2432, (q15_t)0xc65b, (q15_t)0x2426, (q15_t)0xc661,
- (q15_t)0x241b, (q15_t)0xc666, (q15_t)0x2410, (q15_t)0xc66c, (q15_t)0x2404, (q15_t)0xc671, (q15_t)0x23f9, (q15_t)0xc677,
- (q15_t)0x23ee, (q15_t)0xc67c, (q15_t)0x23e2, (q15_t)0xc682, (q15_t)0x23d7, (q15_t)0xc687, (q15_t)0x23cc, (q15_t)0xc68d,
- (q15_t)0x23c1, (q15_t)0xc692, (q15_t)0x23b5, (q15_t)0xc698, (q15_t)0x23aa, (q15_t)0xc69d, (q15_t)0x239f, (q15_t)0xc6a3,
- (q15_t)0x2394, (q15_t)0xc6a8, (q15_t)0x2388, (q15_t)0xc6ae, (q15_t)0x237d, (q15_t)0xc6b4, (q15_t)0x2372, (q15_t)0xc6b9,
- (q15_t)0x2367, (q15_t)0xc6bf, (q15_t)0x235b, (q15_t)0xc6c5, (q15_t)0x2350, (q15_t)0xc6ca, (q15_t)0x2345, (q15_t)0xc6d0,
- (q15_t)0x233a, (q15_t)0xc6d5, (q15_t)0x232e, (q15_t)0xc6db, (q15_t)0x2323, (q15_t)0xc6e1, (q15_t)0x2318, (q15_t)0xc6e6,
- (q15_t)0x230d, (q15_t)0xc6ec, (q15_t)0x2301, (q15_t)0xc6f2, (q15_t)0x22f6, (q15_t)0xc6f7, (q15_t)0x22eb, (q15_t)0xc6fd,
- (q15_t)0x22e0, (q15_t)0xc703, (q15_t)0x22d5, (q15_t)0xc709, (q15_t)0x22ca, (q15_t)0xc70e, (q15_t)0x22be, (q15_t)0xc714,
- (q15_t)0x22b3, (q15_t)0xc71a, (q15_t)0x22a8, (q15_t)0xc720, (q15_t)0x229d, (q15_t)0xc725, (q15_t)0x2292, (q15_t)0xc72b,
- (q15_t)0x2287, (q15_t)0xc731, (q15_t)0x227b, (q15_t)0xc737, (q15_t)0x2270, (q15_t)0xc73d, (q15_t)0x2265, (q15_t)0xc742,
- (q15_t)0x225a, (q15_t)0xc748, (q15_t)0x224f, (q15_t)0xc74e, (q15_t)0x2244, (q15_t)0xc754, (q15_t)0x2239, (q15_t)0xc75a,
- (q15_t)0x222d, (q15_t)0xc75f, (q15_t)0x2222, (q15_t)0xc765, (q15_t)0x2217, (q15_t)0xc76b, (q15_t)0x220c, (q15_t)0xc771,
- (q15_t)0x2201, (q15_t)0xc777, (q15_t)0x21f6, (q15_t)0xc77d, (q15_t)0x21eb, (q15_t)0xc783, (q15_t)0x21e0, (q15_t)0xc789,
- (q15_t)0x21d5, (q15_t)0xc78f, (q15_t)0x21ca, (q15_t)0xc795, (q15_t)0x21be, (q15_t)0xc79a, (q15_t)0x21b3, (q15_t)0xc7a0,
- (q15_t)0x21a8, (q15_t)0xc7a6, (q15_t)0x219d, (q15_t)0xc7ac, (q15_t)0x2192, (q15_t)0xc7b2, (q15_t)0x2187, (q15_t)0xc7b8,
- (q15_t)0x217c, (q15_t)0xc7be, (q15_t)0x2171, (q15_t)0xc7c4, (q15_t)0x2166, (q15_t)0xc7ca, (q15_t)0x215b, (q15_t)0xc7d0,
- (q15_t)0x2150, (q15_t)0xc7d6, (q15_t)0x2145, (q15_t)0xc7dc, (q15_t)0x213a, (q15_t)0xc7e2, (q15_t)0x212f, (q15_t)0xc7e8,
- (q15_t)0x2124, (q15_t)0xc7ee, (q15_t)0x2119, (q15_t)0xc7f5, (q15_t)0x210e, (q15_t)0xc7fb, (q15_t)0x2103, (q15_t)0xc801,
- (q15_t)0x20f8, (q15_t)0xc807, (q15_t)0x20ed, (q15_t)0xc80d, (q15_t)0x20e2, (q15_t)0xc813, (q15_t)0x20d7, (q15_t)0xc819,
- (q15_t)0x20cc, (q15_t)0xc81f, (q15_t)0x20c1, (q15_t)0xc825, (q15_t)0x20b6, (q15_t)0xc82b, (q15_t)0x20ab, (q15_t)0xc832,
- (q15_t)0x20a0, (q15_t)0xc838, (q15_t)0x2095, (q15_t)0xc83e, (q15_t)0x208a, (q15_t)0xc844, (q15_t)0x207f, (q15_t)0xc84a,
- (q15_t)0x2074, (q15_t)0xc850, (q15_t)0x2069, (q15_t)0xc857, (q15_t)0x205e, (q15_t)0xc85d, (q15_t)0x2054, (q15_t)0xc863,
- (q15_t)0x2049, (q15_t)0xc869, (q15_t)0x203e, (q15_t)0xc870, (q15_t)0x2033, (q15_t)0xc876, (q15_t)0x2028, (q15_t)0xc87c,
- (q15_t)0x201d, (q15_t)0xc882, (q15_t)0x2012, (q15_t)0xc889, (q15_t)0x2007, (q15_t)0xc88f, (q15_t)0x1ffc, (q15_t)0xc895,
- (q15_t)0x1ff1, (q15_t)0xc89b, (q15_t)0x1fe7, (q15_t)0xc8a2, (q15_t)0x1fdc, (q15_t)0xc8a8, (q15_t)0x1fd1, (q15_t)0xc8ae,
- (q15_t)0x1fc6, (q15_t)0xc8b5, (q15_t)0x1fbb, (q15_t)0xc8bb, (q15_t)0x1fb0, (q15_t)0xc8c1, (q15_t)0x1fa5, (q15_t)0xc8c8,
- (q15_t)0x1f9b, (q15_t)0xc8ce, (q15_t)0x1f90, (q15_t)0xc8d4, (q15_t)0x1f85, (q15_t)0xc8db, (q15_t)0x1f7a, (q15_t)0xc8e1,
- (q15_t)0x1f6f, (q15_t)0xc8e8, (q15_t)0x1f65, (q15_t)0xc8ee, (q15_t)0x1f5a, (q15_t)0xc8f4, (q15_t)0x1f4f, (q15_t)0xc8fb,
- (q15_t)0x1f44, (q15_t)0xc901, (q15_t)0x1f39, (q15_t)0xc908, (q15_t)0x1f2f, (q15_t)0xc90e, (q15_t)0x1f24, (q15_t)0xc915,
- (q15_t)0x1f19, (q15_t)0xc91b, (q15_t)0x1f0e, (q15_t)0xc921, (q15_t)0x1f03, (q15_t)0xc928, (q15_t)0x1ef9, (q15_t)0xc92e,
- (q15_t)0x1eee, (q15_t)0xc935, (q15_t)0x1ee3, (q15_t)0xc93b, (q15_t)0x1ed8, (q15_t)0xc942, (q15_t)0x1ece, (q15_t)0xc948,
- (q15_t)0x1ec3, (q15_t)0xc94f, (q15_t)0x1eb8, (q15_t)0xc955, (q15_t)0x1ead, (q15_t)0xc95c, (q15_t)0x1ea3, (q15_t)0xc963,
- (q15_t)0x1e98, (q15_t)0xc969, (q15_t)0x1e8d, (q15_t)0xc970, (q15_t)0x1e83, (q15_t)0xc976, (q15_t)0x1e78, (q15_t)0xc97d,
- (q15_t)0x1e6d, (q15_t)0xc983, (q15_t)0x1e62, (q15_t)0xc98a, (q15_t)0x1e58, (q15_t)0xc991, (q15_t)0x1e4d, (q15_t)0xc997,
- (q15_t)0x1e42, (q15_t)0xc99e, (q15_t)0x1e38, (q15_t)0xc9a4, (q15_t)0x1e2d, (q15_t)0xc9ab, (q15_t)0x1e22, (q15_t)0xc9b2,
- (q15_t)0x1e18, (q15_t)0xc9b8, (q15_t)0x1e0d, (q15_t)0xc9bf, (q15_t)0x1e02, (q15_t)0xc9c6, (q15_t)0x1df8, (q15_t)0xc9cc,
- (q15_t)0x1ded, (q15_t)0xc9d3, (q15_t)0x1de2, (q15_t)0xc9da, (q15_t)0x1dd8, (q15_t)0xc9e0, (q15_t)0x1dcd, (q15_t)0xc9e7,
- (q15_t)0x1dc3, (q15_t)0xc9ee, (q15_t)0x1db8, (q15_t)0xc9f5, (q15_t)0x1dad, (q15_t)0xc9fb, (q15_t)0x1da3, (q15_t)0xca02,
- (q15_t)0x1d98, (q15_t)0xca09, (q15_t)0x1d8e, (q15_t)0xca10, (q15_t)0x1d83, (q15_t)0xca16, (q15_t)0x1d78, (q15_t)0xca1d,
- (q15_t)0x1d6e, (q15_t)0xca24, (q15_t)0x1d63, (q15_t)0xca2b, (q15_t)0x1d59, (q15_t)0xca32, (q15_t)0x1d4e, (q15_t)0xca38,
- (q15_t)0x1d44, (q15_t)0xca3f, (q15_t)0x1d39, (q15_t)0xca46, (q15_t)0x1d2e, (q15_t)0xca4d, (q15_t)0x1d24, (q15_t)0xca54,
- (q15_t)0x1d19, (q15_t)0xca5b, (q15_t)0x1d0f, (q15_t)0xca61, (q15_t)0x1d04, (q15_t)0xca68, (q15_t)0x1cfa, (q15_t)0xca6f,
- (q15_t)0x1cef, (q15_t)0xca76, (q15_t)0x1ce5, (q15_t)0xca7d, (q15_t)0x1cda, (q15_t)0xca84, (q15_t)0x1cd0, (q15_t)0xca8b,
- (q15_t)0x1cc5, (q15_t)0xca92, (q15_t)0x1cbb, (q15_t)0xca99, (q15_t)0x1cb0, (q15_t)0xca9f, (q15_t)0x1ca6, (q15_t)0xcaa6,
- (q15_t)0x1c9b, (q15_t)0xcaad, (q15_t)0x1c91, (q15_t)0xcab4, (q15_t)0x1c86, (q15_t)0xcabb, (q15_t)0x1c7c, (q15_t)0xcac2,
- (q15_t)0x1c72, (q15_t)0xcac9, (q15_t)0x1c67, (q15_t)0xcad0, (q15_t)0x1c5d, (q15_t)0xcad7, (q15_t)0x1c52, (q15_t)0xcade,
- (q15_t)0x1c48, (q15_t)0xcae5, (q15_t)0x1c3d, (q15_t)0xcaec, (q15_t)0x1c33, (q15_t)0xcaf3, (q15_t)0x1c29, (q15_t)0xcafa,
- (q15_t)0x1c1e, (q15_t)0xcb01, (q15_t)0x1c14, (q15_t)0xcb08, (q15_t)0x1c09, (q15_t)0xcb0f, (q15_t)0x1bff, (q15_t)0xcb16,
- (q15_t)0x1bf5, (q15_t)0xcb1e, (q15_t)0x1bea, (q15_t)0xcb25, (q15_t)0x1be0, (q15_t)0xcb2c, (q15_t)0x1bd5, (q15_t)0xcb33,
- (q15_t)0x1bcb, (q15_t)0xcb3a, (q15_t)0x1bc1, (q15_t)0xcb41, (q15_t)0x1bb6, (q15_t)0xcb48, (q15_t)0x1bac, (q15_t)0xcb4f,
- (q15_t)0x1ba2, (q15_t)0xcb56, (q15_t)0x1b97, (q15_t)0xcb5e, (q15_t)0x1b8d, (q15_t)0xcb65, (q15_t)0x1b83, (q15_t)0xcb6c,
- (q15_t)0x1b78, (q15_t)0xcb73, (q15_t)0x1b6e, (q15_t)0xcb7a, (q15_t)0x1b64, (q15_t)0xcb81, (q15_t)0x1b59, (q15_t)0xcb89,
- (q15_t)0x1b4f, (q15_t)0xcb90, (q15_t)0x1b45, (q15_t)0xcb97, (q15_t)0x1b3b, (q15_t)0xcb9e, (q15_t)0x1b30, (q15_t)0xcba5,
- (q15_t)0x1b26, (q15_t)0xcbad, (q15_t)0x1b1c, (q15_t)0xcbb4, (q15_t)0x1b11, (q15_t)0xcbbb, (q15_t)0x1b07, (q15_t)0xcbc2,
- (q15_t)0x1afd, (q15_t)0xcbca, (q15_t)0x1af3, (q15_t)0xcbd1, (q15_t)0x1ae8, (q15_t)0xcbd8, (q15_t)0x1ade, (q15_t)0xcbe0,
- (q15_t)0x1ad4, (q15_t)0xcbe7, (q15_t)0x1aca, (q15_t)0xcbee, (q15_t)0x1abf, (q15_t)0xcbf5, (q15_t)0x1ab5, (q15_t)0xcbfd,
- (q15_t)0x1aab, (q15_t)0xcc04, (q15_t)0x1aa1, (q15_t)0xcc0b, (q15_t)0x1a97, (q15_t)0xcc13, (q15_t)0x1a8c, (q15_t)0xcc1a,
- (q15_t)0x1a82, (q15_t)0xcc21, (q15_t)0x1a78, (q15_t)0xcc29, (q15_t)0x1a6e, (q15_t)0xcc30, (q15_t)0x1a64, (q15_t)0xcc38,
- (q15_t)0x1a5a, (q15_t)0xcc3f, (q15_t)0x1a4f, (q15_t)0xcc46, (q15_t)0x1a45, (q15_t)0xcc4e, (q15_t)0x1a3b, (q15_t)0xcc55,
- (q15_t)0x1a31, (q15_t)0xcc5d, (q15_t)0x1a27, (q15_t)0xcc64, (q15_t)0x1a1d, (q15_t)0xcc6b, (q15_t)0x1a13, (q15_t)0xcc73,
- (q15_t)0x1a08, (q15_t)0xcc7a, (q15_t)0x19fe, (q15_t)0xcc82, (q15_t)0x19f4, (q15_t)0xcc89, (q15_t)0x19ea, (q15_t)0xcc91,
- (q15_t)0x19e0, (q15_t)0xcc98, (q15_t)0x19d6, (q15_t)0xcca0, (q15_t)0x19cc, (q15_t)0xcca7, (q15_t)0x19c2, (q15_t)0xccaf,
- (q15_t)0x19b8, (q15_t)0xccb6, (q15_t)0x19ae, (q15_t)0xccbe, (q15_t)0x19a4, (q15_t)0xccc5, (q15_t)0x199a, (q15_t)0xcccd,
- (q15_t)0x198f, (q15_t)0xccd4, (q15_t)0x1985, (q15_t)0xccdc, (q15_t)0x197b, (q15_t)0xcce3, (q15_t)0x1971, (q15_t)0xcceb,
- (q15_t)0x1967, (q15_t)0xccf3, (q15_t)0x195d, (q15_t)0xccfa, (q15_t)0x1953, (q15_t)0xcd02, (q15_t)0x1949, (q15_t)0xcd09,
- (q15_t)0x193f, (q15_t)0xcd11, (q15_t)0x1935, (q15_t)0xcd19, (q15_t)0x192b, (q15_t)0xcd20, (q15_t)0x1921, (q15_t)0xcd28,
- (q15_t)0x1917, (q15_t)0xcd30, (q15_t)0x190d, (q15_t)0xcd37, (q15_t)0x1903, (q15_t)0xcd3f, (q15_t)0x18f9, (q15_t)0xcd46,
- (q15_t)0x18ef, (q15_t)0xcd4e, (q15_t)0x18e6, (q15_t)0xcd56, (q15_t)0x18dc, (q15_t)0xcd5d, (q15_t)0x18d2, (q15_t)0xcd65,
- (q15_t)0x18c8, (q15_t)0xcd6d, (q15_t)0x18be, (q15_t)0xcd75, (q15_t)0x18b4, (q15_t)0xcd7c, (q15_t)0x18aa, (q15_t)0xcd84,
- (q15_t)0x18a0, (q15_t)0xcd8c, (q15_t)0x1896, (q15_t)0xcd93, (q15_t)0x188c, (q15_t)0xcd9b, (q15_t)0x1882, (q15_t)0xcda3,
- (q15_t)0x1878, (q15_t)0xcdab, (q15_t)0x186f, (q15_t)0xcdb2, (q15_t)0x1865, (q15_t)0xcdba, (q15_t)0x185b, (q15_t)0xcdc2,
- (q15_t)0x1851, (q15_t)0xcdca, (q15_t)0x1847, (q15_t)0xcdd2, (q15_t)0x183d, (q15_t)0xcdd9, (q15_t)0x1833, (q15_t)0xcde1,
- (q15_t)0x182a, (q15_t)0xcde9, (q15_t)0x1820, (q15_t)0xcdf1, (q15_t)0x1816, (q15_t)0xcdf9, (q15_t)0x180c, (q15_t)0xce01,
- (q15_t)0x1802, (q15_t)0xce08, (q15_t)0x17f8, (q15_t)0xce10, (q15_t)0x17ef, (q15_t)0xce18, (q15_t)0x17e5, (q15_t)0xce20,
- (q15_t)0x17db, (q15_t)0xce28, (q15_t)0x17d1, (q15_t)0xce30, (q15_t)0x17c8, (q15_t)0xce38, (q15_t)0x17be, (q15_t)0xce40,
- (q15_t)0x17b4, (q15_t)0xce47, (q15_t)0x17aa, (q15_t)0xce4f, (q15_t)0x17a0, (q15_t)0xce57, (q15_t)0x1797, (q15_t)0xce5f,
- (q15_t)0x178d, (q15_t)0xce67, (q15_t)0x1783, (q15_t)0xce6f, (q15_t)0x177a, (q15_t)0xce77, (q15_t)0x1770, (q15_t)0xce7f,
- (q15_t)0x1766, (q15_t)0xce87, (q15_t)0x175c, (q15_t)0xce8f, (q15_t)0x1753, (q15_t)0xce97, (q15_t)0x1749, (q15_t)0xce9f,
- (q15_t)0x173f, (q15_t)0xcea7, (q15_t)0x1736, (q15_t)0xceaf, (q15_t)0x172c, (q15_t)0xceb7, (q15_t)0x1722, (q15_t)0xcebf,
- (q15_t)0x1719, (q15_t)0xcec7, (q15_t)0x170f, (q15_t)0xcecf, (q15_t)0x1705, (q15_t)0xced7, (q15_t)0x16fc, (q15_t)0xcedf,
- (q15_t)0x16f2, (q15_t)0xcee7, (q15_t)0x16e8, (q15_t)0xceef, (q15_t)0x16df, (q15_t)0xcef7, (q15_t)0x16d5, (q15_t)0xceff,
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- (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6,
- (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9,
- (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec,
- (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee,
- (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0,
- (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2,
- (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4,
- (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6,
- (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8,
- (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9,
- (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb,
- (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc,
- (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd,
- (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe,
- (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff,
- (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff,
- (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000,
- (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000,
- (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000,
-};
-
-/**
-* \par
-* Generation of real_CoefB array:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
-* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-* \par
-* Convert to fixed point Q15 format
-* round(pBTable[i] * pow(2, 15))
-*
-*/
-const q15_t ALIGN4 realCoefBQ15[8192] = {
- (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000,
- (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000,
- (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff,
- (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff,
- (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe,
- (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd,
- (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc,
- (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb,
- (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa,
- (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9,
- (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7,
- (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5,
- (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3,
- (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1,
- (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef,
- (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed,
- (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea,
- (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8,
- (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5,
- (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2,
- (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf,
- (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc,
- (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8,
- (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5,
- (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1,
- (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd,
- (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9,
- (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5,
- (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0,
- (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc,
- (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7,
- (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2,
- (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad,
- (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8,
- (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3,
- (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e,
- (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98,
- (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92,
- (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c,
- (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86,
- (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80,
- (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a,
- (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73,
- (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d,
- (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66,
- (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f,
- (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58,
- (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51,
- (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49,
- (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42,
- (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a,
- (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32,
- (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a,
- (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22,
- (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19,
- (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, (q15_t)0x3f11,
- (q15_t)0x4af1, (q15_t)0x3f0f, (q15_t)0x4afd, (q15_t)0x3f0d, (q15_t)0x4b0a, (q15_t)0x3f0a, (q15_t)0x4b16, (q15_t)0x3f08,
- (q15_t)0x4b23, (q15_t)0x3f06, (q15_t)0x4b2f, (q15_t)0x3f04, (q15_t)0x4b3b, (q15_t)0x3f02, (q15_t)0x4b48, (q15_t)0x3f00,
- (q15_t)0x4b54, (q15_t)0x3efd, (q15_t)0x4b60, (q15_t)0x3efb, (q15_t)0x4b6d, (q15_t)0x3ef9, (q15_t)0x4b79, (q15_t)0x3ef7,
- (q15_t)0x4b85, (q15_t)0x3ef4, (q15_t)0x4b92, (q15_t)0x3ef2, (q15_t)0x4b9e, (q15_t)0x3ef0, (q15_t)0x4bab, (q15_t)0x3eed,
- (q15_t)0x4bb7, (q15_t)0x3eeb, (q15_t)0x4bc3, (q15_t)0x3ee9, (q15_t)0x4bd0, (q15_t)0x3ee7, (q15_t)0x4bdc, (q15_t)0x3ee4,
- (q15_t)0x4be8, (q15_t)0x3ee2, (q15_t)0x4bf5, (q15_t)0x3ee0, (q15_t)0x4c01, (q15_t)0x3edd, (q15_t)0x4c0d, (q15_t)0x3edb,
- (q15_t)0x4c1a, (q15_t)0x3ed8, (q15_t)0x4c26, (q15_t)0x3ed6, (q15_t)0x4c32, (q15_t)0x3ed4, (q15_t)0x4c3f, (q15_t)0x3ed1,
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- (q15_t)0x6671, (q15_t)0xccd4, (q15_t)0x6666, (q15_t)0xcccd, (q15_t)0x665c, (q15_t)0xccc5, (q15_t)0x6652, (q15_t)0xccbe,
- (q15_t)0x6648, (q15_t)0xccb6, (q15_t)0x663e, (q15_t)0xccaf, (q15_t)0x6634, (q15_t)0xcca7, (q15_t)0x662a, (q15_t)0xcca0,
- (q15_t)0x6620, (q15_t)0xcc98, (q15_t)0x6616, (q15_t)0xcc91, (q15_t)0x660c, (q15_t)0xcc89, (q15_t)0x6602, (q15_t)0xcc82,
- (q15_t)0x65f8, (q15_t)0xcc7a, (q15_t)0x65ed, (q15_t)0xcc73, (q15_t)0x65e3, (q15_t)0xcc6b, (q15_t)0x65d9, (q15_t)0xcc64,
- (q15_t)0x65cf, (q15_t)0xcc5d, (q15_t)0x65c5, (q15_t)0xcc55, (q15_t)0x65bb, (q15_t)0xcc4e, (q15_t)0x65b1, (q15_t)0xcc46,
- (q15_t)0x65a6, (q15_t)0xcc3f, (q15_t)0x659c, (q15_t)0xcc38, (q15_t)0x6592, (q15_t)0xcc30, (q15_t)0x6588, (q15_t)0xcc29,
- (q15_t)0x657e, (q15_t)0xcc21, (q15_t)0x6574, (q15_t)0xcc1a, (q15_t)0x6569, (q15_t)0xcc13, (q15_t)0x655f, (q15_t)0xcc0b,
- (q15_t)0x6555, (q15_t)0xcc04, (q15_t)0x654b, (q15_t)0xcbfd, (q15_t)0x6541, (q15_t)0xcbf5, (q15_t)0x6536, (q15_t)0xcbee,
- (q15_t)0x652c, (q15_t)0xcbe7, (q15_t)0x6522, (q15_t)0xcbe0, (q15_t)0x6518, (q15_t)0xcbd8, (q15_t)0x650d, (q15_t)0xcbd1,
- (q15_t)0x6503, (q15_t)0xcbca, (q15_t)0x64f9, (q15_t)0xcbc2, (q15_t)0x64ef, (q15_t)0xcbbb, (q15_t)0x64e4, (q15_t)0xcbb4,
- (q15_t)0x64da, (q15_t)0xcbad, (q15_t)0x64d0, (q15_t)0xcba5, (q15_t)0x64c5, (q15_t)0xcb9e, (q15_t)0x64bb, (q15_t)0xcb97,
- (q15_t)0x64b1, (q15_t)0xcb90, (q15_t)0x64a7, (q15_t)0xcb89, (q15_t)0x649c, (q15_t)0xcb81, (q15_t)0x6492, (q15_t)0xcb7a,
- (q15_t)0x6488, (q15_t)0xcb73, (q15_t)0x647d, (q15_t)0xcb6c, (q15_t)0x6473, (q15_t)0xcb65, (q15_t)0x6469, (q15_t)0xcb5e,
- (q15_t)0x645e, (q15_t)0xcb56, (q15_t)0x6454, (q15_t)0xcb4f, (q15_t)0x644a, (q15_t)0xcb48, (q15_t)0x643f, (q15_t)0xcb41,
- (q15_t)0x6435, (q15_t)0xcb3a, (q15_t)0x642b, (q15_t)0xcb33, (q15_t)0x6420, (q15_t)0xcb2c, (q15_t)0x6416, (q15_t)0xcb25,
- (q15_t)0x640b, (q15_t)0xcb1e, (q15_t)0x6401, (q15_t)0xcb16, (q15_t)0x63f7, (q15_t)0xcb0f, (q15_t)0x63ec, (q15_t)0xcb08,
- (q15_t)0x63e2, (q15_t)0xcb01, (q15_t)0x63d7, (q15_t)0xcafa, (q15_t)0x63cd, (q15_t)0xcaf3, (q15_t)0x63c3, (q15_t)0xcaec,
- (q15_t)0x63b8, (q15_t)0xcae5, (q15_t)0x63ae, (q15_t)0xcade, (q15_t)0x63a3, (q15_t)0xcad7, (q15_t)0x6399, (q15_t)0xcad0,
- (q15_t)0x638e, (q15_t)0xcac9, (q15_t)0x6384, (q15_t)0xcac2, (q15_t)0x637a, (q15_t)0xcabb, (q15_t)0x636f, (q15_t)0xcab4,
- (q15_t)0x6365, (q15_t)0xcaad, (q15_t)0x635a, (q15_t)0xcaa6, (q15_t)0x6350, (q15_t)0xca9f, (q15_t)0x6345, (q15_t)0xca99,
- (q15_t)0x633b, (q15_t)0xca92, (q15_t)0x6330, (q15_t)0xca8b, (q15_t)0x6326, (q15_t)0xca84, (q15_t)0x631b, (q15_t)0xca7d,
- (q15_t)0x6311, (q15_t)0xca76, (q15_t)0x6306, (q15_t)0xca6f, (q15_t)0x62fc, (q15_t)0xca68, (q15_t)0x62f1, (q15_t)0xca61,
- (q15_t)0x62e7, (q15_t)0xca5b, (q15_t)0x62dc, (q15_t)0xca54, (q15_t)0x62d2, (q15_t)0xca4d, (q15_t)0x62c7, (q15_t)0xca46,
- (q15_t)0x62bc, (q15_t)0xca3f, (q15_t)0x62b2, (q15_t)0xca38, (q15_t)0x62a7, (q15_t)0xca32, (q15_t)0x629d, (q15_t)0xca2b,
- (q15_t)0x6292, (q15_t)0xca24, (q15_t)0x6288, (q15_t)0xca1d, (q15_t)0x627d, (q15_t)0xca16, (q15_t)0x6272, (q15_t)0xca10,
- (q15_t)0x6268, (q15_t)0xca09, (q15_t)0x625d, (q15_t)0xca02, (q15_t)0x6253, (q15_t)0xc9fb, (q15_t)0x6248, (q15_t)0xc9f5,
- (q15_t)0x623d, (q15_t)0xc9ee, (q15_t)0x6233, (q15_t)0xc9e7, (q15_t)0x6228, (q15_t)0xc9e0, (q15_t)0x621e, (q15_t)0xc9da,
- (q15_t)0x6213, (q15_t)0xc9d3, (q15_t)0x6208, (q15_t)0xc9cc, (q15_t)0x61fe, (q15_t)0xc9c6, (q15_t)0x61f3, (q15_t)0xc9bf,
- (q15_t)0x61e8, (q15_t)0xc9b8, (q15_t)0x61de, (q15_t)0xc9b2, (q15_t)0x61d3, (q15_t)0xc9ab, (q15_t)0x61c8, (q15_t)0xc9a4,
- (q15_t)0x61be, (q15_t)0xc99e, (q15_t)0x61b3, (q15_t)0xc997, (q15_t)0x61a8, (q15_t)0xc991, (q15_t)0x619e, (q15_t)0xc98a,
- (q15_t)0x6193, (q15_t)0xc983, (q15_t)0x6188, (q15_t)0xc97d, (q15_t)0x617d, (q15_t)0xc976, (q15_t)0x6173, (q15_t)0xc970,
- (q15_t)0x6168, (q15_t)0xc969, (q15_t)0x615d, (q15_t)0xc963, (q15_t)0x6153, (q15_t)0xc95c, (q15_t)0x6148, (q15_t)0xc955,
- (q15_t)0x613d, (q15_t)0xc94f, (q15_t)0x6132, (q15_t)0xc948, (q15_t)0x6128, (q15_t)0xc942, (q15_t)0x611d, (q15_t)0xc93b,
- (q15_t)0x6112, (q15_t)0xc935, (q15_t)0x6107, (q15_t)0xc92e, (q15_t)0x60fd, (q15_t)0xc928, (q15_t)0x60f2, (q15_t)0xc921,
- (q15_t)0x60e7, (q15_t)0xc91b, (q15_t)0x60dc, (q15_t)0xc915, (q15_t)0x60d1, (q15_t)0xc90e, (q15_t)0x60c7, (q15_t)0xc908,
- (q15_t)0x60bc, (q15_t)0xc901, (q15_t)0x60b1, (q15_t)0xc8fb, (q15_t)0x60a6, (q15_t)0xc8f4, (q15_t)0x609b, (q15_t)0xc8ee,
- (q15_t)0x6091, (q15_t)0xc8e8, (q15_t)0x6086, (q15_t)0xc8e1, (q15_t)0x607b, (q15_t)0xc8db, (q15_t)0x6070, (q15_t)0xc8d4,
- (q15_t)0x6065, (q15_t)0xc8ce, (q15_t)0x605b, (q15_t)0xc8c8, (q15_t)0x6050, (q15_t)0xc8c1, (q15_t)0x6045, (q15_t)0xc8bb,
- (q15_t)0x603a, (q15_t)0xc8b5, (q15_t)0x602f, (q15_t)0xc8ae, (q15_t)0x6024, (q15_t)0xc8a8, (q15_t)0x6019, (q15_t)0xc8a2,
- (q15_t)0x600f, (q15_t)0xc89b, (q15_t)0x6004, (q15_t)0xc895, (q15_t)0x5ff9, (q15_t)0xc88f, (q15_t)0x5fee, (q15_t)0xc889,
- (q15_t)0x5fe3, (q15_t)0xc882, (q15_t)0x5fd8, (q15_t)0xc87c, (q15_t)0x5fcd, (q15_t)0xc876, (q15_t)0x5fc2, (q15_t)0xc870,
- (q15_t)0x5fb7, (q15_t)0xc869, (q15_t)0x5fac, (q15_t)0xc863, (q15_t)0x5fa2, (q15_t)0xc85d, (q15_t)0x5f97, (q15_t)0xc857,
- (q15_t)0x5f8c, (q15_t)0xc850, (q15_t)0x5f81, (q15_t)0xc84a, (q15_t)0x5f76, (q15_t)0xc844, (q15_t)0x5f6b, (q15_t)0xc83e,
- (q15_t)0x5f60, (q15_t)0xc838, (q15_t)0x5f55, (q15_t)0xc832, (q15_t)0x5f4a, (q15_t)0xc82b, (q15_t)0x5f3f, (q15_t)0xc825,
- (q15_t)0x5f34, (q15_t)0xc81f, (q15_t)0x5f29, (q15_t)0xc819, (q15_t)0x5f1e, (q15_t)0xc813, (q15_t)0x5f13, (q15_t)0xc80d,
- (q15_t)0x5f08, (q15_t)0xc807, (q15_t)0x5efd, (q15_t)0xc801, (q15_t)0x5ef2, (q15_t)0xc7fb, (q15_t)0x5ee7, (q15_t)0xc7f5,
- (q15_t)0x5edc, (q15_t)0xc7ee, (q15_t)0x5ed1, (q15_t)0xc7e8, (q15_t)0x5ec6, (q15_t)0xc7e2, (q15_t)0x5ebb, (q15_t)0xc7dc,
- (q15_t)0x5eb0, (q15_t)0xc7d6, (q15_t)0x5ea5, (q15_t)0xc7d0, (q15_t)0x5e9a, (q15_t)0xc7ca, (q15_t)0x5e8f, (q15_t)0xc7c4,
- (q15_t)0x5e84, (q15_t)0xc7be, (q15_t)0x5e79, (q15_t)0xc7b8, (q15_t)0x5e6e, (q15_t)0xc7b2, (q15_t)0x5e63, (q15_t)0xc7ac,
- (q15_t)0x5e58, (q15_t)0xc7a6, (q15_t)0x5e4d, (q15_t)0xc7a0, (q15_t)0x5e42, (q15_t)0xc79a, (q15_t)0x5e36, (q15_t)0xc795,
- (q15_t)0x5e2b, (q15_t)0xc78f, (q15_t)0x5e20, (q15_t)0xc789, (q15_t)0x5e15, (q15_t)0xc783, (q15_t)0x5e0a, (q15_t)0xc77d,
- (q15_t)0x5dff, (q15_t)0xc777, (q15_t)0x5df4, (q15_t)0xc771, (q15_t)0x5de9, (q15_t)0xc76b, (q15_t)0x5dde, (q15_t)0xc765,
- (q15_t)0x5dd3, (q15_t)0xc75f, (q15_t)0x5dc7, (q15_t)0xc75a, (q15_t)0x5dbc, (q15_t)0xc754, (q15_t)0x5db1, (q15_t)0xc74e,
- (q15_t)0x5da6, (q15_t)0xc748, (q15_t)0x5d9b, (q15_t)0xc742, (q15_t)0x5d90, (q15_t)0xc73d, (q15_t)0x5d85, (q15_t)0xc737,
- (q15_t)0x5d79, (q15_t)0xc731, (q15_t)0x5d6e, (q15_t)0xc72b, (q15_t)0x5d63, (q15_t)0xc725, (q15_t)0x5d58, (q15_t)0xc720,
- (q15_t)0x5d4d, (q15_t)0xc71a, (q15_t)0x5d42, (q15_t)0xc714, (q15_t)0x5d36, (q15_t)0xc70e, (q15_t)0x5d2b, (q15_t)0xc709,
- (q15_t)0x5d20, (q15_t)0xc703, (q15_t)0x5d15, (q15_t)0xc6fd, (q15_t)0x5d0a, (q15_t)0xc6f7, (q15_t)0x5cff, (q15_t)0xc6f2,
- (q15_t)0x5cf3, (q15_t)0xc6ec, (q15_t)0x5ce8, (q15_t)0xc6e6, (q15_t)0x5cdd, (q15_t)0xc6e1, (q15_t)0x5cd2, (q15_t)0xc6db,
- (q15_t)0x5cc6, (q15_t)0xc6d5, (q15_t)0x5cbb, (q15_t)0xc6d0, (q15_t)0x5cb0, (q15_t)0xc6ca, (q15_t)0x5ca5, (q15_t)0xc6c5,
- (q15_t)0x5c99, (q15_t)0xc6bf, (q15_t)0x5c8e, (q15_t)0xc6b9, (q15_t)0x5c83, (q15_t)0xc6b4, (q15_t)0x5c78, (q15_t)0xc6ae,
- (q15_t)0x5c6c, (q15_t)0xc6a8, (q15_t)0x5c61, (q15_t)0xc6a3, (q15_t)0x5c56, (q15_t)0xc69d, (q15_t)0x5c4b, (q15_t)0xc698,
- (q15_t)0x5c3f, (q15_t)0xc692, (q15_t)0x5c34, (q15_t)0xc68d, (q15_t)0x5c29, (q15_t)0xc687, (q15_t)0x5c1e, (q15_t)0xc682,
- (q15_t)0x5c12, (q15_t)0xc67c, (q15_t)0x5c07, (q15_t)0xc677, (q15_t)0x5bfc, (q15_t)0xc671, (q15_t)0x5bf0, (q15_t)0xc66c,
- (q15_t)0x5be5, (q15_t)0xc666, (q15_t)0x5bda, (q15_t)0xc661, (q15_t)0x5bce, (q15_t)0xc65b, (q15_t)0x5bc3, (q15_t)0xc656,
- (q15_t)0x5bb8, (q15_t)0xc650, (q15_t)0x5bac, (q15_t)0xc64b, (q15_t)0x5ba1, (q15_t)0xc645, (q15_t)0x5b96, (q15_t)0xc640,
- (q15_t)0x5b8a, (q15_t)0xc63b, (q15_t)0x5b7f, (q15_t)0xc635, (q15_t)0x5b74, (q15_t)0xc630, (q15_t)0x5b68, (q15_t)0xc62a,
- (q15_t)0x5b5d, (q15_t)0xc625, (q15_t)0x5b52, (q15_t)0xc620, (q15_t)0x5b46, (q15_t)0xc61a, (q15_t)0x5b3b, (q15_t)0xc615,
- (q15_t)0x5b30, (q15_t)0xc610, (q15_t)0x5b24, (q15_t)0xc60a, (q15_t)0x5b19, (q15_t)0xc605, (q15_t)0x5b0d, (q15_t)0xc600,
- (q15_t)0x5b02, (q15_t)0xc5fa, (q15_t)0x5af7, (q15_t)0xc5f5, (q15_t)0x5aeb, (q15_t)0xc5f0, (q15_t)0x5ae0, (q15_t)0xc5ea,
- (q15_t)0x5ad4, (q15_t)0xc5e5, (q15_t)0x5ac9, (q15_t)0xc5e0, (q15_t)0x5abe, (q15_t)0xc5db, (q15_t)0x5ab2, (q15_t)0xc5d5,
- (q15_t)0x5aa7, (q15_t)0xc5d0, (q15_t)0x5a9b, (q15_t)0xc5cb, (q15_t)0x5a90, (q15_t)0xc5c6, (q15_t)0x5a84, (q15_t)0xc5c1,
- (q15_t)0x5a79, (q15_t)0xc5bb, (q15_t)0x5a6e, (q15_t)0xc5b6, (q15_t)0x5a62, (q15_t)0xc5b1, (q15_t)0x5a57, (q15_t)0xc5ac,
- (q15_t)0x5a4b, (q15_t)0xc5a7, (q15_t)0x5a40, (q15_t)0xc5a1, (q15_t)0x5a34, (q15_t)0xc59c, (q15_t)0x5a29, (q15_t)0xc597,
- (q15_t)0x5a1d, (q15_t)0xc592, (q15_t)0x5a12, (q15_t)0xc58d, (q15_t)0x5a06, (q15_t)0xc588, (q15_t)0x59fb, (q15_t)0xc583,
- (q15_t)0x59ef, (q15_t)0xc57e, (q15_t)0x59e4, (q15_t)0xc578, (q15_t)0x59d8, (q15_t)0xc573, (q15_t)0x59cd, (q15_t)0xc56e,
- (q15_t)0x59c1, (q15_t)0xc569, (q15_t)0x59b6, (q15_t)0xc564, (q15_t)0x59aa, (q15_t)0xc55f, (q15_t)0x599f, (q15_t)0xc55a,
- (q15_t)0x5993, (q15_t)0xc555, (q15_t)0x5988, (q15_t)0xc550, (q15_t)0x597c, (q15_t)0xc54b, (q15_t)0x5971, (q15_t)0xc546,
- (q15_t)0x5965, (q15_t)0xc541, (q15_t)0x595a, (q15_t)0xc53c, (q15_t)0x594e, (q15_t)0xc537, (q15_t)0x5943, (q15_t)0xc532,
- (q15_t)0x5937, (q15_t)0xc52d, (q15_t)0x592c, (q15_t)0xc528, (q15_t)0x5920, (q15_t)0xc523, (q15_t)0x5914, (q15_t)0xc51e,
- (q15_t)0x5909, (q15_t)0xc51a, (q15_t)0x58fd, (q15_t)0xc515, (q15_t)0x58f2, (q15_t)0xc510, (q15_t)0x58e6, (q15_t)0xc50b,
- (q15_t)0x58db, (q15_t)0xc506, (q15_t)0x58cf, (q15_t)0xc501, (q15_t)0x58c3, (q15_t)0xc4fc, (q15_t)0x58b8, (q15_t)0xc4f7,
- (q15_t)0x58ac, (q15_t)0xc4f2, (q15_t)0x58a1, (q15_t)0xc4ee, (q15_t)0x5895, (q15_t)0xc4e9, (q15_t)0x5889, (q15_t)0xc4e4,
- (q15_t)0x587e, (q15_t)0xc4df, (q15_t)0x5872, (q15_t)0xc4da, (q15_t)0x5867, (q15_t)0xc4d6, (q15_t)0x585b, (q15_t)0xc4d1,
- (q15_t)0x584f, (q15_t)0xc4cc, (q15_t)0x5844, (q15_t)0xc4c7, (q15_t)0x5838, (q15_t)0xc4c2, (q15_t)0x582d, (q15_t)0xc4be,
- (q15_t)0x5821, (q15_t)0xc4b9, (q15_t)0x5815, (q15_t)0xc4b4, (q15_t)0x580a, (q15_t)0xc4b0, (q15_t)0x57fe, (q15_t)0xc4ab,
- (q15_t)0x57f2, (q15_t)0xc4a6, (q15_t)0x57e7, (q15_t)0xc4a1, (q15_t)0x57db, (q15_t)0xc49d, (q15_t)0x57cf, (q15_t)0xc498,
- (q15_t)0x57c4, (q15_t)0xc493, (q15_t)0x57b8, (q15_t)0xc48f, (q15_t)0x57ac, (q15_t)0xc48a, (q15_t)0x57a1, (q15_t)0xc485,
- (q15_t)0x5795, (q15_t)0xc481, (q15_t)0x5789, (q15_t)0xc47c, (q15_t)0x577e, (q15_t)0xc478, (q15_t)0x5772, (q15_t)0xc473,
- (q15_t)0x5766, (q15_t)0xc46e, (q15_t)0x575b, (q15_t)0xc46a, (q15_t)0x574f, (q15_t)0xc465, (q15_t)0x5743, (q15_t)0xc461,
- (q15_t)0x5737, (q15_t)0xc45c, (q15_t)0x572c, (q15_t)0xc457, (q15_t)0x5720, (q15_t)0xc453, (q15_t)0x5714, (q15_t)0xc44e,
- (q15_t)0x5709, (q15_t)0xc44a, (q15_t)0x56fd, (q15_t)0xc445, (q15_t)0x56f1, (q15_t)0xc441, (q15_t)0x56e5, (q15_t)0xc43c,
- (q15_t)0x56da, (q15_t)0xc438, (q15_t)0x56ce, (q15_t)0xc433, (q15_t)0x56c2, (q15_t)0xc42f, (q15_t)0x56b6, (q15_t)0xc42a,
- (q15_t)0x56ab, (q15_t)0xc426, (q15_t)0x569f, (q15_t)0xc422, (q15_t)0x5693, (q15_t)0xc41d, (q15_t)0x5687, (q15_t)0xc419,
- (q15_t)0x567c, (q15_t)0xc414, (q15_t)0x5670, (q15_t)0xc410, (q15_t)0x5664, (q15_t)0xc40b, (q15_t)0x5658, (q15_t)0xc407,
- (q15_t)0x564c, (q15_t)0xc403, (q15_t)0x5641, (q15_t)0xc3fe, (q15_t)0x5635, (q15_t)0xc3fa, (q15_t)0x5629, (q15_t)0xc3f6,
- (q15_t)0x561d, (q15_t)0xc3f1, (q15_t)0x5612, (q15_t)0xc3ed, (q15_t)0x5606, (q15_t)0xc3e9, (q15_t)0x55fa, (q15_t)0xc3e4,
- (q15_t)0x55ee, (q15_t)0xc3e0, (q15_t)0x55e2, (q15_t)0xc3dc, (q15_t)0x55d7, (q15_t)0xc3d7, (q15_t)0x55cb, (q15_t)0xc3d3,
- (q15_t)0x55bf, (q15_t)0xc3cf, (q15_t)0x55b3, (q15_t)0xc3ca, (q15_t)0x55a7, (q15_t)0xc3c6, (q15_t)0x559b, (q15_t)0xc3c2,
- (q15_t)0x5590, (q15_t)0xc3be, (q15_t)0x5584, (q15_t)0xc3ba, (q15_t)0x5578, (q15_t)0xc3b5, (q15_t)0x556c, (q15_t)0xc3b1,
- (q15_t)0x5560, (q15_t)0xc3ad, (q15_t)0x5554, (q15_t)0xc3a9, (q15_t)0x5549, (q15_t)0xc3a5, (q15_t)0x553d, (q15_t)0xc3a0,
- (q15_t)0x5531, (q15_t)0xc39c, (q15_t)0x5525, (q15_t)0xc398, (q15_t)0x5519, (q15_t)0xc394, (q15_t)0x550d, (q15_t)0xc390,
- (q15_t)0x5501, (q15_t)0xc38c, (q15_t)0x54f6, (q15_t)0xc387, (q15_t)0x54ea, (q15_t)0xc383, (q15_t)0x54de, (q15_t)0xc37f,
- (q15_t)0x54d2, (q15_t)0xc37b, (q15_t)0x54c6, (q15_t)0xc377, (q15_t)0x54ba, (q15_t)0xc373, (q15_t)0x54ae, (q15_t)0xc36f,
- (q15_t)0x54a2, (q15_t)0xc36b, (q15_t)0x5496, (q15_t)0xc367, (q15_t)0x548b, (q15_t)0xc363, (q15_t)0x547f, (q15_t)0xc35f,
- (q15_t)0x5473, (q15_t)0xc35b, (q15_t)0x5467, (q15_t)0xc357, (q15_t)0x545b, (q15_t)0xc353, (q15_t)0x544f, (q15_t)0xc34f,
- (q15_t)0x5443, (q15_t)0xc34b, (q15_t)0x5437, (q15_t)0xc347, (q15_t)0x542b, (q15_t)0xc343, (q15_t)0x541f, (q15_t)0xc33f,
- (q15_t)0x5413, (q15_t)0xc33b, (q15_t)0x5407, (q15_t)0xc337, (q15_t)0x53fb, (q15_t)0xc333, (q15_t)0x53f0, (q15_t)0xc32f,
- (q15_t)0x53e4, (q15_t)0xc32b, (q15_t)0x53d8, (q15_t)0xc327, (q15_t)0x53cc, (q15_t)0xc323, (q15_t)0x53c0, (q15_t)0xc320,
- (q15_t)0x53b4, (q15_t)0xc31c, (q15_t)0x53a8, (q15_t)0xc318, (q15_t)0x539c, (q15_t)0xc314, (q15_t)0x5390, (q15_t)0xc310,
- (q15_t)0x5384, (q15_t)0xc30c, (q15_t)0x5378, (q15_t)0xc308, (q15_t)0x536c, (q15_t)0xc305, (q15_t)0x5360, (q15_t)0xc301,
- (q15_t)0x5354, (q15_t)0xc2fd, (q15_t)0x5348, (q15_t)0xc2f9, (q15_t)0x533c, (q15_t)0xc2f5, (q15_t)0x5330, (q15_t)0xc2f2,
- (q15_t)0x5324, (q15_t)0xc2ee, (q15_t)0x5318, (q15_t)0xc2ea, (q15_t)0x530c, (q15_t)0xc2e6, (q15_t)0x5300, (q15_t)0xc2e3,
- (q15_t)0x52f4, (q15_t)0xc2df, (q15_t)0x52e8, (q15_t)0xc2db, (q15_t)0x52dc, (q15_t)0xc2d8, (q15_t)0x52d0, (q15_t)0xc2d4,
- (q15_t)0x52c4, (q15_t)0xc2d0, (q15_t)0x52b8, (q15_t)0xc2cc, (q15_t)0x52ac, (q15_t)0xc2c9, (q15_t)0x52a0, (q15_t)0xc2c5,
- (q15_t)0x5294, (q15_t)0xc2c1, (q15_t)0x5288, (q15_t)0xc2be, (q15_t)0x527c, (q15_t)0xc2ba, (q15_t)0x5270, (q15_t)0xc2b7,
- (q15_t)0x5264, (q15_t)0xc2b3, (q15_t)0x5258, (q15_t)0xc2af, (q15_t)0x524c, (q15_t)0xc2ac, (q15_t)0x5240, (q15_t)0xc2a8,
- (q15_t)0x5234, (q15_t)0xc2a5, (q15_t)0x5228, (q15_t)0xc2a1, (q15_t)0x521c, (q15_t)0xc29d, (q15_t)0x5210, (q15_t)0xc29a,
- (q15_t)0x5204, (q15_t)0xc296, (q15_t)0x51f7, (q15_t)0xc293, (q15_t)0x51eb, (q15_t)0xc28f, (q15_t)0x51df, (q15_t)0xc28c,
- (q15_t)0x51d3, (q15_t)0xc288, (q15_t)0x51c7, (q15_t)0xc285, (q15_t)0x51bb, (q15_t)0xc281, (q15_t)0x51af, (q15_t)0xc27e,
- (q15_t)0x51a3, (q15_t)0xc27a, (q15_t)0x5197, (q15_t)0xc277, (q15_t)0x518b, (q15_t)0xc273, (q15_t)0x517f, (q15_t)0xc270,
- (q15_t)0x5173, (q15_t)0xc26d, (q15_t)0x5167, (q15_t)0xc269, (q15_t)0x515a, (q15_t)0xc266, (q15_t)0x514e, (q15_t)0xc262,
- (q15_t)0x5142, (q15_t)0xc25f, (q15_t)0x5136, (q15_t)0xc25c, (q15_t)0x512a, (q15_t)0xc258, (q15_t)0x511e, (q15_t)0xc255,
- (q15_t)0x5112, (q15_t)0xc251, (q15_t)0x5106, (q15_t)0xc24e, (q15_t)0x50fa, (q15_t)0xc24b, (q15_t)0x50ed, (q15_t)0xc247,
- (q15_t)0x50e1, (q15_t)0xc244, (q15_t)0x50d5, (q15_t)0xc241, (q15_t)0x50c9, (q15_t)0xc23e, (q15_t)0x50bd, (q15_t)0xc23a,
- (q15_t)0x50b1, (q15_t)0xc237, (q15_t)0x50a5, (q15_t)0xc234, (q15_t)0x5099, (q15_t)0xc230, (q15_t)0x508c, (q15_t)0xc22d,
- (q15_t)0x5080, (q15_t)0xc22a, (q15_t)0x5074, (q15_t)0xc227, (q15_t)0x5068, (q15_t)0xc223, (q15_t)0x505c, (q15_t)0xc220,
- (q15_t)0x5050, (q15_t)0xc21d, (q15_t)0x5044, (q15_t)0xc21a, (q15_t)0x5037, (q15_t)0xc217, (q15_t)0x502b, (q15_t)0xc213,
- (q15_t)0x501f, (q15_t)0xc210, (q15_t)0x5013, (q15_t)0xc20d, (q15_t)0x5007, (q15_t)0xc20a, (q15_t)0x4ffb, (q15_t)0xc207,
- (q15_t)0x4fee, (q15_t)0xc204, (q15_t)0x4fe2, (q15_t)0xc201, (q15_t)0x4fd6, (q15_t)0xc1fd, (q15_t)0x4fca, (q15_t)0xc1fa,
- (q15_t)0x4fbe, (q15_t)0xc1f7, (q15_t)0x4fb2, (q15_t)0xc1f4, (q15_t)0x4fa5, (q15_t)0xc1f1, (q15_t)0x4f99, (q15_t)0xc1ee,
- (q15_t)0x4f8d, (q15_t)0xc1eb, (q15_t)0x4f81, (q15_t)0xc1e8, (q15_t)0x4f75, (q15_t)0xc1e5, (q15_t)0x4f68, (q15_t)0xc1e2,
- (q15_t)0x4f5c, (q15_t)0xc1df, (q15_t)0x4f50, (q15_t)0xc1dc, (q15_t)0x4f44, (q15_t)0xc1d9, (q15_t)0x4f38, (q15_t)0xc1d6,
- (q15_t)0x4f2b, (q15_t)0xc1d3, (q15_t)0x4f1f, (q15_t)0xc1d0, (q15_t)0x4f13, (q15_t)0xc1cd, (q15_t)0x4f07, (q15_t)0xc1ca,
- (q15_t)0x4efb, (q15_t)0xc1c7, (q15_t)0x4eee, (q15_t)0xc1c4, (q15_t)0x4ee2, (q15_t)0xc1c1, (q15_t)0x4ed6, (q15_t)0xc1be,
- (q15_t)0x4eca, (q15_t)0xc1bb, (q15_t)0x4ebd, (q15_t)0xc1b8, (q15_t)0x4eb1, (q15_t)0xc1b6, (q15_t)0x4ea5, (q15_t)0xc1b3,
- (q15_t)0x4e99, (q15_t)0xc1b0, (q15_t)0x4e8c, (q15_t)0xc1ad, (q15_t)0x4e80, (q15_t)0xc1aa, (q15_t)0x4e74, (q15_t)0xc1a7,
- (q15_t)0x4e68, (q15_t)0xc1a4, (q15_t)0x4e5c, (q15_t)0xc1a2, (q15_t)0x4e4f, (q15_t)0xc19f, (q15_t)0x4e43, (q15_t)0xc19c,
- (q15_t)0x4e37, (q15_t)0xc199, (q15_t)0x4e2b, (q15_t)0xc196, (q15_t)0x4e1e, (q15_t)0xc194, (q15_t)0x4e12, (q15_t)0xc191,
- (q15_t)0x4e06, (q15_t)0xc18e, (q15_t)0x4df9, (q15_t)0xc18b, (q15_t)0x4ded, (q15_t)0xc189, (q15_t)0x4de1, (q15_t)0xc186,
- (q15_t)0x4dd5, (q15_t)0xc183, (q15_t)0x4dc8, (q15_t)0xc180, (q15_t)0x4dbc, (q15_t)0xc17e, (q15_t)0x4db0, (q15_t)0xc17b,
- (q15_t)0x4da4, (q15_t)0xc178, (q15_t)0x4d97, (q15_t)0xc176, (q15_t)0x4d8b, (q15_t)0xc173, (q15_t)0x4d7f, (q15_t)0xc170,
- (q15_t)0x4d72, (q15_t)0xc16e, (q15_t)0x4d66, (q15_t)0xc16b, (q15_t)0x4d5a, (q15_t)0xc168, (q15_t)0x4d4e, (q15_t)0xc166,
- (q15_t)0x4d41, (q15_t)0xc163, (q15_t)0x4d35, (q15_t)0xc161, (q15_t)0x4d29, (q15_t)0xc15e, (q15_t)0x4d1c, (q15_t)0xc15b,
- (q15_t)0x4d10, (q15_t)0xc159, (q15_t)0x4d04, (q15_t)0xc156, (q15_t)0x4cf8, (q15_t)0xc154, (q15_t)0x4ceb, (q15_t)0xc151,
- (q15_t)0x4cdf, (q15_t)0xc14f, (q15_t)0x4cd3, (q15_t)0xc14c, (q15_t)0x4cc6, (q15_t)0xc14a, (q15_t)0x4cba, (q15_t)0xc147,
- (q15_t)0x4cae, (q15_t)0xc145, (q15_t)0x4ca1, (q15_t)0xc142, (q15_t)0x4c95, (q15_t)0xc140, (q15_t)0x4c89, (q15_t)0xc13d,
- (q15_t)0x4c7c, (q15_t)0xc13b, (q15_t)0x4c70, (q15_t)0xc138, (q15_t)0x4c64, (q15_t)0xc136, (q15_t)0x4c57, (q15_t)0xc134,
- (q15_t)0x4c4b, (q15_t)0xc131, (q15_t)0x4c3f, (q15_t)0xc12f, (q15_t)0x4c32, (q15_t)0xc12c, (q15_t)0x4c26, (q15_t)0xc12a,
- (q15_t)0x4c1a, (q15_t)0xc128, (q15_t)0x4c0d, (q15_t)0xc125, (q15_t)0x4c01, (q15_t)0xc123, (q15_t)0x4bf5, (q15_t)0xc120,
- (q15_t)0x4be8, (q15_t)0xc11e, (q15_t)0x4bdc, (q15_t)0xc11c, (q15_t)0x4bd0, (q15_t)0xc119, (q15_t)0x4bc3, (q15_t)0xc117,
- (q15_t)0x4bb7, (q15_t)0xc115, (q15_t)0x4bab, (q15_t)0xc113, (q15_t)0x4b9e, (q15_t)0xc110, (q15_t)0x4b92, (q15_t)0xc10e,
- (q15_t)0x4b85, (q15_t)0xc10c, (q15_t)0x4b79, (q15_t)0xc109, (q15_t)0x4b6d, (q15_t)0xc107, (q15_t)0x4b60, (q15_t)0xc105,
- (q15_t)0x4b54, (q15_t)0xc103, (q15_t)0x4b48, (q15_t)0xc100, (q15_t)0x4b3b, (q15_t)0xc0fe, (q15_t)0x4b2f, (q15_t)0xc0fc,
- (q15_t)0x4b23, (q15_t)0xc0fa, (q15_t)0x4b16, (q15_t)0xc0f8, (q15_t)0x4b0a, (q15_t)0xc0f6, (q15_t)0x4afd, (q15_t)0xc0f3,
- (q15_t)0x4af1, (q15_t)0xc0f1, (q15_t)0x4ae5, (q15_t)0xc0ef, (q15_t)0x4ad8, (q15_t)0xc0ed, (q15_t)0x4acc, (q15_t)0xc0eb,
- (q15_t)0x4ac0, (q15_t)0xc0e9, (q15_t)0x4ab3, (q15_t)0xc0e7, (q15_t)0x4aa7, (q15_t)0xc0e4, (q15_t)0x4a9a, (q15_t)0xc0e2,
- (q15_t)0x4a8e, (q15_t)0xc0e0, (q15_t)0x4a82, (q15_t)0xc0de, (q15_t)0x4a75, (q15_t)0xc0dc, (q15_t)0x4a69, (q15_t)0xc0da,
- (q15_t)0x4a5c, (q15_t)0xc0d8, (q15_t)0x4a50, (q15_t)0xc0d6, (q15_t)0x4a44, (q15_t)0xc0d4, (q15_t)0x4a37, (q15_t)0xc0d2,
- (q15_t)0x4a2b, (q15_t)0xc0d0, (q15_t)0x4a1e, (q15_t)0xc0ce, (q15_t)0x4a12, (q15_t)0xc0cc, (q15_t)0x4a06, (q15_t)0xc0ca,
- (q15_t)0x49f9, (q15_t)0xc0c8, (q15_t)0x49ed, (q15_t)0xc0c6, (q15_t)0x49e0, (q15_t)0xc0c4, (q15_t)0x49d4, (q15_t)0xc0c2,
- (q15_t)0x49c7, (q15_t)0xc0c0, (q15_t)0x49bb, (q15_t)0xc0be, (q15_t)0x49af, (q15_t)0xc0bd, (q15_t)0x49a2, (q15_t)0xc0bb,
- (q15_t)0x4996, (q15_t)0xc0b9, (q15_t)0x4989, (q15_t)0xc0b7, (q15_t)0x497d, (q15_t)0xc0b5, (q15_t)0x4970, (q15_t)0xc0b3,
- (q15_t)0x4964, (q15_t)0xc0b1, (q15_t)0x4958, (q15_t)0xc0af, (q15_t)0x494b, (q15_t)0xc0ae, (q15_t)0x493f, (q15_t)0xc0ac,
- (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5,
- (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e,
- (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097,
- (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090,
- (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089,
- (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083,
- (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d,
- (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077,
- (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071,
- (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b,
- (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065,
- (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060,
- (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a,
- (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055,
- (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050,
- (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b,
- (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047,
- (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042,
- (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d,
- (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039,
- (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035,
- (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031,
- (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d,
- (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a,
- (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026,
- (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023,
- (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020,
- (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d,
- (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a,
- (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017,
- (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014,
- (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012,
- (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010,
- (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e,
- (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c,
- (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a,
- (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008,
- (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007,
- (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005,
- (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004,
- (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003,
- (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002,
- (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001,
- (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001,
- (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000,
- (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000,
- (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000,
-};
-
-/**
-* @} end of RealFFT_Table group
-*/
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Initialization function for the Q15 RFFT/RIFFT.
-* @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
-* @param[in] fftLenReal length of the FFT.
-* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
-* \par
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par
-* This function also initializes Twiddle factor table.
-*/
-arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialize the Real FFT length */
- S->fftLenReal = (uint16_t) fftLenReal;
-
- /* Initialize the Twiddle coefficientA pointer */
- S->pTwiddleAReal = (q15_t *) realCoefAQ15;
-
- /* Initialize the Twiddle coefficientB pointer */
- S->pTwiddleBReal = (q15_t *) realCoefBQ15;
-
- /* Initialize the Flag for selection of RFFT or RIFFT */
- S->ifftFlagR = (uint8_t) ifftFlagR;
-
- /* Initialize the Flag for calculation Bit reversal or not */
- S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
- /* Initialization of coef modifier depending on the FFT length */
- switch (S->fftLenReal)
- {
- case 8192u:
- S->twidCoefRModifier = 1u;
- S->pCfft = &arm_cfft_sR_q15_len4096;
- break;
- case 4096u:
- S->twidCoefRModifier = 2u;
- S->pCfft = &arm_cfft_sR_q15_len2048;
- break;
- case 2048u:
- S->twidCoefRModifier = 4u;
- S->pCfft = &arm_cfft_sR_q15_len1024;
- break;
- case 1024u:
- S->twidCoefRModifier = 8u;
- S->pCfft = &arm_cfft_sR_q15_len512;
- break;
- case 512u:
- S->twidCoefRModifier = 16u;
- S->pCfft = &arm_cfft_sR_q15_len256;
- break;
- case 256u:
- S->twidCoefRModifier = 32u;
- S->pCfft = &arm_cfft_sR_q15_len128;
- break;
- case 128u:
- S->twidCoefRModifier = 64u;
- S->pCfft = &arm_cfft_sR_q15_len64;
- break;
- case 64u:
- S->twidCoefRModifier = 128u;
- S->pCfft = &arm_cfft_sR_q15_len32;
- break;
- case 32u:
- S->twidCoefRModifier = 256u;
- S->pCfft = &arm_cfft_sR_q15_len16;
- break;
- default:
- /* Reporting argument error if rfftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- /* return the status of RFFT Init function */
- return (status);
-}
-
-/**
-* @} end of RealFFT group
-*/
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c
deleted file mode 100644
index 8cfae7e..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c
+++ /dev/null
@@ -1,4280 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_init_q31.c
- * Description: RFFT & RIFFT Q31 initialisation function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include "arm_const_structs.h"
-
-/**
-* @ingroup RealFFT
-*/
-
-/**
- * @addtogroup RealFFT_Table Real FFT Tables
-* @{
-*/
-
-/**
-* \par
-* Generation fixed-point realCoefAQ31 array in Q31 format:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
-* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-* \par
-* Convert to fixed point Q31 format
-* round(pATable[i] * pow(2, 31))
-*/
-const q31_t realCoefAQ31[8192] = {
- (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c,
- (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a,
- (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8,
- (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74,
- (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee,
- (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547,
- (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e,
- (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594,
- (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489,
- (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c,
- (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d,
- (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c,
- (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a,
- (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356,
- (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80,
- (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188,
- (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e,
- (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731,
- (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3,
- (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452,
- (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae,
- (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8,
- (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff,
- (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3,
- (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4,
- (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872,
- (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd,
- (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364,
- (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8,
- (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7,
- (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3,
- (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b,
- (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e,
- (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd,
- (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047,
- (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c,
- (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac,
- (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7,
- (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c,
- (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b,
- (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5,
- (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018,
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- (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce,
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- (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674,
- (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9,
- (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23,
- (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2,
- (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065,
- (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d,
- (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39,
- (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858,
- (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c,
- (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703,
- (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e,
- (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c,
- (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d,
- (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01,
- (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718,
- (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652,
- (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae,
- (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d,
- (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf,
- (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092,
- (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78,
- (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280,
- (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa,
- (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6,
- (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364,
- (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3,
- (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4,
- (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77,
- (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c,
- (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82,
- (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9,
- (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12,
- (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c,
- (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128,
- (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6,
- (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4,
-};
-
-
-/**
-* \par
-* Generation of realCoefBQ31 array:
-* \par
-* n = 4096
-* for (i = 0; i < n; i++)
-* {
-* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
-* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
-* }
-* \par
-* Convert to fixed point Q31 format
-* round(pBTable[i] * pow(2, 31))
-*
-*/
-
-const q31_t realCoefBQ31[8192] = {
- (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4,
- (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6,
- (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128,
- (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c,
- (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12,
- (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9,
- (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82,
- (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c,
- (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77,
- (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4,
- (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3,
- (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364,
- (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6,
- (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa,
- (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280,
- (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78,
- (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092,
- (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf,
- (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d,
- (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae,
- (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652,
- (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718,
- (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01,
- (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d,
- (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c,
- (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e,
- (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703,
- (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c,
- (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858,
- (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39,
- (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d,
- (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065,
- (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2,
- (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23,
- (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9,
- (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674,
- (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354,
- (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659,
- (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84,
- (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5,
- (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b,
- (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8,
- (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac,
- (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996,
- (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7,
- (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf,
- (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f,
- (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7,
- (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77,
- (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f,
- (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50,
- (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a,
- (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd,
- (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a,
- (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0,
- (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1,
- (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc,
- (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3,
- (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334,
- (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1,
- (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a,
- (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f,
- (q31_t)0x4613e1c5, (q31_t)0x3fb5f4ea, (q31_t)0x4620641a, (q31_t)0x3fb4c231,
- (q31_t)0x462ce634, (q31_t)0x3fb38d02, (q31_t)0x46396810, (q31_t)0x3fb2555f,
- (q31_t)0x4645e9af, (q31_t)0x3fb11b48, (q31_t)0x46526b10, (q31_t)0x3fafdebb,
- (q31_t)0x465eec33, (q31_t)0x3fae9fbb, (q31_t)0x466b6d16, (q31_t)0x3fad5e45,
- (q31_t)0x4677edbb, (q31_t)0x3fac1a5b, (q31_t)0x46846e1f, (q31_t)0x3faad3fd,
- (q31_t)0x4690ee44, (q31_t)0x3fa98b2a, (q31_t)0x469d6e27, (q31_t)0x3fa83fe3,
- (q31_t)0x46a9edc9, (q31_t)0x3fa6f228, (q31_t)0x46b66d29, (q31_t)0x3fa5a1f9,
- (q31_t)0x46c2ec48, (q31_t)0x3fa44f55, (q31_t)0x46cf6b23, (q31_t)0x3fa2fa3d,
- (q31_t)0x46dbe9bb, (q31_t)0x3fa1a2b2, (q31_t)0x46e86810, (q31_t)0x3fa048b2,
- (q31_t)0x46f4e620, (q31_t)0x3f9eec3e, (q31_t)0x470163eb, (q31_t)0x3f9d8d56,
- (q31_t)0x470de172, (q31_t)0x3f9c2bfb, (q31_t)0x471a5eb3, (q31_t)0x3f9ac82c,
- (q31_t)0x4726dbae, (q31_t)0x3f9961e8, (q31_t)0x47335862, (q31_t)0x3f97f932,
- (q31_t)0x473fd4cf, (q31_t)0x3f968e07, (q31_t)0x474c50f4, (q31_t)0x3f952069,
- (q31_t)0x4758ccd2, (q31_t)0x3f93b058, (q31_t)0x47654867, (q31_t)0x3f923dd2,
- (q31_t)0x4771c3b3, (q31_t)0x3f90c8da, (q31_t)0x477e3eb5, (q31_t)0x3f8f516e,
- (q31_t)0x478ab96e, (q31_t)0x3f8dd78f, (q31_t)0x479733dc, (q31_t)0x3f8c5b3d,
- (q31_t)0x47a3adff, (q31_t)0x3f8adc77, (q31_t)0x47b027d7, (q31_t)0x3f895b3e,
- (q31_t)0x47bca163, (q31_t)0x3f87d792, (q31_t)0x47c91aa3, (q31_t)0x3f865174,
- (q31_t)0x47d59396, (q31_t)0x3f84c8e2, (q31_t)0x47e20c3b, (q31_t)0x3f833ddd,
- (q31_t)0x47ee8493, (q31_t)0x3f81b065, (q31_t)0x47fafc9c, (q31_t)0x3f80207b,
- (q31_t)0x48077457, (q31_t)0x3f7e8e1e, (q31_t)0x4813ebc2, (q31_t)0x3f7cf94e,
- (q31_t)0x482062de, (q31_t)0x3f7b620c, (q31_t)0x482cd9a9, (q31_t)0x3f79c857,
- (q31_t)0x48395024, (q31_t)0x3f782c30, (q31_t)0x4845c64d, (q31_t)0x3f768d96,
- (q31_t)0x48523c25, (q31_t)0x3f74ec8a, (q31_t)0x485eb1ab, (q31_t)0x3f73490b,
- (q31_t)0x486b26de, (q31_t)0x3f71a31b, (q31_t)0x48779bbe, (q31_t)0x3f6ffab8,
- (q31_t)0x4884104b, (q31_t)0x3f6e4fe3, (q31_t)0x48908483, (q31_t)0x3f6ca29c,
- (q31_t)0x489cf867, (q31_t)0x3f6af2e3, (q31_t)0x48a96bf6, (q31_t)0x3f6940b8,
- (q31_t)0x48b5df30, (q31_t)0x3f678c1c, (q31_t)0x48c25213, (q31_t)0x3f65d50d,
- (q31_t)0x48cec4a0, (q31_t)0x3f641b8d, (q31_t)0x48db36d6, (q31_t)0x3f625f9b,
- (q31_t)0x48e7a8b5, (q31_t)0x3f60a138, (q31_t)0x48f41a3c, (q31_t)0x3f5ee063,
- (q31_t)0x49008b6a, (q31_t)0x3f5d1d1d, (q31_t)0x490cfc40, (q31_t)0x3f5b5765,
- (q31_t)0x49196cbc, (q31_t)0x3f598f3c, (q31_t)0x4925dcdf, (q31_t)0x3f57c4a2,
- (q31_t)0x49324ca7, (q31_t)0x3f55f796, (q31_t)0x493ebc14, (q31_t)0x3f54281a,
- (q31_t)0x494b2b27, (q31_t)0x3f52562c, (q31_t)0x495799dd, (q31_t)0x3f5081cd,
- (q31_t)0x49640837, (q31_t)0x3f4eaafe, (q31_t)0x49707635, (q31_t)0x3f4cd1be,
- (q31_t)0x497ce3d5, (q31_t)0x3f4af60d, (q31_t)0x49895118, (q31_t)0x3f4917eb,
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- (q31_t)0x5caff965, (q31_t)0xc6ca215c, (q31_t)0x5ca4bd21, (q31_t)0xc6c4807a,
- (q31_t)0x5c997fc4, (q31_t)0xc6bee1cd, (q31_t)0x5c8e414b, (q31_t)0xc6b94554,
- (q31_t)0x5c8301b9, (q31_t)0xc6b3ab12, (q31_t)0x5c77c10e, (q31_t)0xc6ae1304,
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- (q31_t)0x5c3f6d47, (q31_t)0xc6923bec, (q31_t)0x5c34260c, (q31_t)0xc68cb124,
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- (q31_t)0x5bfbb1a0, (q31_t)0xc6711c7b, (q31_t)0x5bf063e6, (q31_t)0xc66b9f01,
- (q31_t)0x5be51518, (q31_t)0xc66623be, (q31_t)0x5bd9c537, (q31_t)0xc660aab5,
- (q31_t)0x5bce7442, (q31_t)0xc65b33e4, (q31_t)0x5bc3223c, (q31_t)0xc655bf4c,
- (q31_t)0x5bb7cf23, (q31_t)0xc6504ced, (q31_t)0x5bac7af9, (q31_t)0xc64adcc7,
- (q31_t)0x5ba125bd, (q31_t)0xc6456edb, (q31_t)0x5b95cf71, (q31_t)0xc6400329,
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- (q31_t)0x5aeb4253, (q31_t)0xc5efbf58, (q31_t)0x5adfdb37, (q31_t)0xc5ea775e,
- (q31_t)0x5ad47312, (q31_t)0xc5e531a1, (q31_t)0x5ac909e5, (q31_t)0xc5dfee22,
- (q31_t)0x5abd9faf, (q31_t)0xc5daace1, (q31_t)0x5ab23471, (q31_t)0xc5d56ddd,
- (q31_t)0x5aa6c82b, (q31_t)0xc5d03118, (q31_t)0x5a9b5adf, (q31_t)0xc5caf690,
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- (q31_t)0x5a622907, (q31_t)0xc5b0f399, (q31_t)0x5a56b599, (q31_t)0xc5abc68c,
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- (q31_t)0x5a1d6544, (q31_t)0xc5920708, (q31_t)0x5a11ebc5, (q31_t)0xc58ce77c,
- (q31_t)0x5a067145, (q31_t)0xc587ca31, (q31_t)0x59faf5c5, (q31_t)0xc582af26,
- (q31_t)0x59ef7944, (q31_t)0xc57d965d, (q31_t)0x59e3fbc3, (q31_t)0xc5787fd6,
- (q31_t)0x59d87d42, (q31_t)0xc5736b90, (q31_t)0x59ccfdc2, (q31_t)0xc56e598c,
- (q31_t)0x59c17d44, (q31_t)0xc56949ca, (q31_t)0x59b5fbc8, (q31_t)0xc5643c4a,
- (q31_t)0x59aa794d, (q31_t)0xc55f310d, (q31_t)0x599ef5d6, (q31_t)0xc55a2812,
- (q31_t)0x59937161, (q31_t)0xc555215a, (q31_t)0x5987ebf0, (q31_t)0xc5501ce5,
- (q31_t)0x597c6584, (q31_t)0xc54b1ab4, (q31_t)0x5970de1b, (q31_t)0xc5461ac6,
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- (q31_t)0x594e4201, (q31_t)0xc5372891, (q31_t)0x5942b6af, (q31_t)0xc53231b3,
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- (q31_t)0x59200ee3, (q31_t)0xc5235ab2, (q31_t)0x59147fae, (q31_t)0xc51e6ce6,
- (q31_t)0x5908ef82, (q31_t)0xc519815f, (q31_t)0x58fd5e5f, (q31_t)0xc514981d,
- (q31_t)0x58f1cc45, (q31_t)0xc50fb121, (q31_t)0x58e63935, (q31_t)0xc50acc6b,
- (q31_t)0x58daa52f, (q31_t)0xc505e9fb, (q31_t)0x58cf1034, (q31_t)0xc50109d0,
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- (q31_t)0x512a09fc, (q31_t)0xc25836f9, (q31_t)0x511dee84, (q31_t)0xc254d965,
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- (q31_t)0x50b0d9d0, (q31_t)0xc236fa3b, (q31_t)0x50a4b7d3, (q31_t)0xc233b473,
- (q31_t)0x50989532, (q31_t)0xc230710d, (q31_t)0x508c71ee, (q31_t)0xc22d3009,
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- (q31_t)0x504fb80e, (q31_t)0xc21d0eb8, (q31_t)0x504390fd, (q31_t)0xc219dc03,
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- (q31_t)0x501f1807, (q31_t)0xc2105236, (q31_t)0x5012ee76, (q31_t)0xc20d290d,
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- (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3,
- (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff,
- (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8,
- (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae,
- (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452,
- (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3,
- (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731,
- (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e,
- (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188,
- (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80,
- (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356,
- (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a,
- (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c,
- (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d,
- (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c,
- (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489,
- (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594,
- (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e,
- (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547,
- (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee,
- (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74,
- (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8,
- (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a,
- (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c,
-};
-
-/**
-* @} end of RealFFT_Table group
-*/
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Initialization function for the Q31 RFFT/RIFFT.
-* @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
-* @param[in] fftLenReal length of the FFT.
-* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
-*
-* \par Description:
-* \par
-* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
-* \par
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
-* \par
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
-* \par 7
-* This function also initializes Twiddle factor table.
-*/
-
-arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag)
-{
- /* Initialise the default arm status */
- arm_status status = ARM_MATH_SUCCESS;
-
- /* Initialize the Real FFT length */
- S->fftLenReal = (uint16_t) fftLenReal;
-
- /* Initialize the Twiddle coefficientA pointer */
- S->pTwiddleAReal = (q31_t *) realCoefAQ31;
-
- /* Initialize the Twiddle coefficientB pointer */
- S->pTwiddleBReal = (q31_t *) realCoefBQ31;
-
- /* Initialize the Flag for selection of RFFT or RIFFT */
- S->ifftFlagR = (uint8_t) ifftFlagR;
-
- /* Initialize the Flag for calculation Bit reversal or not */
- S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
- /* Initialization of coef modifier depending on the FFT length */
- switch (S->fftLenReal)
- {
- case 8192u:
- S->twidCoefRModifier = 1u;
- S->pCfft = &arm_cfft_sR_q31_len4096;
- break;
- case 4096u:
- S->twidCoefRModifier = 2u;
- S->pCfft = &arm_cfft_sR_q31_len2048;
- break;
- case 2048u:
- S->twidCoefRModifier = 4u;
- S->pCfft = &arm_cfft_sR_q31_len1024;
- break;
- case 1024u:
- S->twidCoefRModifier = 8u;
- S->pCfft = &arm_cfft_sR_q31_len512;
- break;
- case 512u:
- S->twidCoefRModifier = 16u;
- S->pCfft = &arm_cfft_sR_q31_len256;
- break;
- case 256u:
- S->twidCoefRModifier = 32u;
- S->pCfft = &arm_cfft_sR_q31_len128;
- break;
- case 128u:
- S->twidCoefRModifier = 64u;
- S->pCfft = &arm_cfft_sR_q31_len64;
- break;
- case 64u:
- S->twidCoefRModifier = 128u;
- S->pCfft = &arm_cfft_sR_q31_len32;
- break;
- case 32u:
- S->twidCoefRModifier = 256u;
- S->pCfft = &arm_cfft_sR_q31_len16;
- break;
- default:
- /* Reporting argument error if rfftSize is not valid value */
- status = ARM_MATH_ARGUMENT_ERROR;
- break;
- }
-
- /* return the status of RFFT Init function */
- return (status);
-}
-
-/**
-* @} end of RealFFT group
-*/
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c
deleted file mode 100644
index 53ab9e6..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_q15.c
- * Description: RFFT & RIFFT Q15 process function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/* ----------------------------------------------------------------------
- * Internal functions prototypes
- * -------------------------------------------------------------------- */
-
-void arm_split_rfft_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pATable,
- q15_t * pBTable,
- q15_t * pDst,
- uint32_t modifier);
-
-void arm_split_rifft_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pATable,
- q15_t * pBTable,
- q15_t * pDst,
- uint32_t modifier);
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Processing function for the Q15 RFFT/RIFFT.
-* @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
-* @param[in] *pSrc points to the input buffer.
-* @param[out] *pDst points to the output buffer.
-* @return none.
-*
-* \par Input an output formats:
-* \par
-* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
-* Hence the output format is different for different RFFT sizes.
-* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
-* \par
-* \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
-* \par
-* \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
-*/
-
-void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst)
-{
- const arm_cfft_instance_q15 *S_CFFT = S->pCfft;
- uint32_t i;
- uint32_t L2 = S->fftLenReal >> 1;
-
- /* Calculation of RIFFT of input */
- if (S->ifftFlagR == 1u)
- {
- /* Real IFFT core process */
- arm_split_rifft_q15(pSrc, L2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
- /* Complex IFFT process */
- arm_cfft_q15(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
-
- for(i=0;ifftLenReal;i++)
- {
- pDst[i] = pDst[i] << 1;
- }
- }
- else
- {
- /* Calculation of RFFT of input */
-
- /* Complex FFT process */
- arm_cfft_q15(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
-
- /* Real FFT core process */
- arm_split_rfft_q15(pSrc, L2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
- }
-}
-
-/**
-* @} end of RealFFT group
-*/
-
-/**
-* @brief Core Real FFT process
-* @param *pSrc points to the input buffer.
-* @param fftLen length of FFT.
-* @param *pATable points to the A twiddle Coef buffer.
-* @param *pBTable points to the B twiddle Coef buffer.
-* @param *pDst points to the output buffer.
-* @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-* The function implements a Real FFT
-*/
-
-void arm_split_rfft_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pATable,
- q15_t * pBTable,
- q15_t * pDst,
- uint32_t modifier)
-{
- uint32_t i; /* Loop Counter */
- q31_t outR, outI; /* Temporary variables for output */
- q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- q15_t *pSrc1, *pSrc2;
-#if defined (ARM_MATH_DSP)
- q15_t *pD1, *pD2;
-#endif
-
- // pSrc[2u * fftLen] = pSrc[0];
- // pSrc[(2u * fftLen) + 1u] = pSrc[1];
-
- pCoefA = &pATable[modifier * 2u];
- pCoefB = &pBTable[modifier * 2u];
-
- pSrc1 = &pSrc[2];
- pSrc2 = &pSrc[(2u * fftLen) - 2u];
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- i = 1u;
- pD1 = pDst + 2;
- pD2 = pDst + (4u * fftLen) - 2;
-
- for(i = fftLen - 1; i > 0; i--)
- {
- /*
- outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
- + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
- pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
- */
-
- /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
- outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
-
-#else
-
- /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
- outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
- pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
- outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 16u;
-
- /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
-#else
-
- outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
- outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
-
- /* write output */
- *pD1++ = (q15_t) outR;
- *pD1++ = outI >> 16u;
-
- /* write complex conjugate output */
- pD2[0] = (q15_t) outR;
- pD2[1] = -(outI >> 16u);
- pD2 -= 2;
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (2u * modifier);
- pCoefA = pCoefA + (2u * modifier);
- }
-
- pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
- pDst[(2u * fftLen) + 1u] = 0;
-
- pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
- pDst[1] = 0;
-
-#else
-
- /* Run the below code for Cortex-M0 */
- i = 1u;
-
- while (i < fftLen)
- {
- /*
- outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
- + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
- pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
- */
-
- outR = *pSrc1 * *pCoefA;
- outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
- outR = outR + (*pSrc2 * *pCoefB);
- outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16;
-
-
- /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
- */
-
- outI = *pSrc2 * *(pCoefB + 1);
- outI = outI - (*(pSrc2 + 1) * *pCoefB);
- outI = outI + (*(pSrc1 + 1) * *pCoefA);
- outI = outI + (*pSrc1 * *(pCoefA + 1));
-
- /* update input pointers */
- pSrc1 += 2u;
- pSrc2 -= 2u;
-
- /* write output */
- pDst[2u * i] = (q15_t) outR;
- pDst[(2u * i) + 1u] = outI >> 16u;
-
- /* write complex conjugate output */
- pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
- pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 16u);
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (2u * modifier);
- pCoefA = pCoefA + (2u * modifier);
-
- i++;
- }
-
- pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
- pDst[(2u * fftLen) + 1u] = 0;
-
- pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
- pDst[1] = 0;
-
-#endif /* #if defined (ARM_MATH_DSP) */
-}
-
-
-/**
-* @brief Core Real IFFT process
-* @param[in] *pSrc points to the input buffer.
-* @param[in] fftLen length of FFT.
-* @param[in] *pATable points to the twiddle Coef A buffer.
-* @param[in] *pBTable points to the twiddle Coef B buffer.
-* @param[out] *pDst points to the output buffer.
-* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-* The function implements a Real IFFT
-*/
-void arm_split_rifft_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- q15_t * pATable,
- q15_t * pBTable,
- q15_t * pDst,
- uint32_t modifier)
-{
- uint32_t i; /* Loop Counter */
- q31_t outR, outI; /* Temporary variables for output */
- q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- q15_t *pSrc1, *pSrc2;
- q15_t *pDst1 = &pDst[0];
-
- pCoefA = &pATable[0];
- pCoefB = &pBTable[0];
-
- pSrc1 = &pSrc[0];
- pSrc2 = &pSrc[2u * fftLen];
-
-#if defined (ARM_MATH_DSP)
-
- /* Run the below code for Cortex-M4 and Cortex-M3 */
- i = fftLen;
-
- while (i > 0u)
- {
- /*
- outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
-
- outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
- */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
- outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
-
-#else
-
- /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
- outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i] */
- outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 16u;
-
- /*
- -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
- outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
- /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
-
-#else
-
- outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
- /* write output */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
- *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 16u), 16);
-
-#else
-
- *__SIMD32(pDst1)++ = __PKHBT((outI >> 16u), outR, 16);
-
-#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (2u * modifier);
- pCoefA = pCoefA + (2u * modifier);
-
- i--;
- }
-#else
- /* Run the below code for Cortex-M0 */
- i = fftLen;
-
- while (i > 0u)
- {
- /*
- outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
- */
-
- outR = *pSrc2 * *pCoefB;
- outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
- outR = outR + (*pSrc1 * *pCoefA);
- outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16;
-
- /*
- outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
- */
-
- outI = *(pSrc1 + 1) * *pCoefA;
- outI = outI - (*pSrc1 * *(pCoefA + 1));
- outI = outI - (*pSrc2 * *(pCoefB + 1));
- outI = outI - (*(pSrc2 + 1) * *(pCoefB));
-
- /* update input pointers */
- pSrc1 += 2u;
- pSrc2 -= 2u;
-
- /* write output */
- *pDst1++ = (q15_t) outR;
- *pDst1++ = (q15_t) (outI >> 16);
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (2u * modifier);
- pCoefA = pCoefA + (2u * modifier);
-
- i--;
- }
-#endif /* #if defined (ARM_MATH_DSP) */
-}
diff --git a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c
deleted file mode 100644
index 460d77d..0000000
--- a/KugleFirmware/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_rfft_q31.c
- * Description: FFT & RIFFT Q31 process function
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "arm_math.h"
-
-/* ----------------------------------------------------------------------
- * Internal functions prototypes
- * -------------------------------------------------------------------- */
-
-void arm_split_rfft_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pATable,
- q31_t * pBTable,
- q31_t * pDst,
- uint32_t modifier);
-
-void arm_split_rifft_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pATable,
- q31_t * pBTable,
- q31_t * pDst,
- uint32_t modifier);
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Processing function for the Q31 RFFT/RIFFT.
-* @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
-* @param[in] *pSrc points to the input buffer.
-* @param[out] *pDst points to the output buffer.
-* @return none.
-*
-* \par Input an output formats:
-* \par
-* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
-* Hence the output format is different for different RFFT sizes.
-* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
-* \par
-* \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"
-*
-* \par
-* \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"
-*/
-void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst)
-{
- const arm_cfft_instance_q31 *S_CFFT = S->pCfft;
- uint32_t i;
- uint32_t L2 = S->fftLenReal >> 1;
-
- /* Calculation of RIFFT of input */
- if (S->ifftFlagR == 1u)
- {
- /* Real IFFT core process */
- arm_split_rifft_q31(pSrc, L2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
- /* Complex IFFT process */
- arm_cfft_q31(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
-
- for(i=0;ifftLenReal;i++)
- {
- pDst[i] = pDst[i] << 1;
- }
- }
- else
- {
- /* Calculation of RFFT of input */
-
- /* Complex FFT process */
- arm_cfft_q31(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
-
- /* Real FFT core process */
- arm_split_rfft_q31(pSrc, L2, S->pTwiddleAReal,
- S->pTwiddleBReal, pDst, S->twidCoefRModifier);
- }
-}
-
-/**
-* @} end of RealFFT group
-*/
-
-/**
-* @brief Core Real FFT process
-* @param[in] *pSrc points to the input buffer.
-* @param[in] fftLen length of FFT.
-* @param[in] *pATable points to the twiddle Coef A buffer.
-* @param[in] *pBTable points to the twiddle Coef B buffer.
-* @param[out] *pDst points to the output buffer.
-* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-*/
-void arm_split_rfft_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pATable,
- q31_t * pBTable,
- q31_t * pDst,
- uint32_t modifier)
-{
- uint32_t i; /* Loop Counter */
- q31_t outR, outI; /* Temporary variables for output */
- q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
- q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
- q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
-
- /* Init coefficient pointers */
- pCoefA = &pATable[modifier * 2u];
- pCoefB = &pBTable[modifier * 2u];
-
- i = fftLen - 1u;
-
- while (i > 0u)
- {
- /*
- outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
- + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
- pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
- */
-
- /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
- CoefA1 = *pCoefA++;
- CoefA2 = *pCoefA;
-
- /* outR = (pSrc[2 * i] * pATable[2 * i] */
- mult_32x32_keep32_R(outR, *pIn1, CoefA1);
-
- /* outI = pIn[2 * i] * pATable[2 * i + 1] */
- mult_32x32_keep32_R(outI, *pIn1++, CoefA2);
-
- /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
- multSub_32x32_keep32_R(outR, *pIn1, CoefA2);
-
- /* (pIn[2 * i + 1] * pATable[2 * i] */
- multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
-
- /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */
- multSub_32x32_keep32_R(outR, *pIn2, CoefA2);
- CoefB1 = *pCoefB;
-
- /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
- multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
-
- /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
- multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
-
- /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
- multSub_32x32_keep32_R(outI, *pIn2--, CoefA2);
-
- /* write output */
- *pOut1++ = outR;
- *pOut1++ = outI;
-
- /* write complex conjugate output */
- *pOut2-- = -outI;
- *pOut2-- = outR;
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (modifier * 2u);
- pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
- i--;
- }
- pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
- pDst[(2u * fftLen) + 1u] = 0;
-
- pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
- pDst[1] = 0;
-}
-
-/**
-* @brief Core Real IFFT process
-* @param[in] *pSrc points to the input buffer.
-* @param[in] fftLen length of FFT.
-* @param[in] *pATable points to the twiddle Coef A buffer.
-* @param[in] *pBTable points to the twiddle Coef B buffer.
-* @param[out] *pDst points to the output buffer.
-* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-* @return none.
-*/
-void arm_split_rifft_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pATable,
- q31_t * pBTable,
- q31_t * pDst,
- uint32_t modifier)
-{
- q31_t outR, outI; /* Temporary variables for output */
- q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
- q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
- q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
-
- pCoefA = &pATable[0];
- pCoefB = &pBTable[0];
-
- while (fftLen > 0u)
- {
- /*
- outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
- pIn[2 * n - 2 * i] * pBTable[2 * i] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
-
- outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
- pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
- pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
- */
- CoefA1 = *pCoefA++;
- CoefA2 = *pCoefA;
-
- /* outR = (pIn[2 * i] * pATable[2 * i] */
- mult_32x32_keep32_R(outR, *pIn1, CoefA1);
-
- /* - pIn[2 * i] * pATable[2 * i + 1] */
- mult_32x32_keep32_R(outI, *pIn1++, -CoefA2);
-
- /* pIn[2 * i + 1] * pATable[2 * i + 1] */
- multAcc_32x32_keep32_R(outR, *pIn1, CoefA2);
-
- /* pIn[2 * i + 1] * pATable[2 * i] */
- multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
-
- /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
- multAcc_32x32_keep32_R(outR, *pIn2, CoefA2);
- CoefB1 = *pCoefB;
-
- /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
- multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
-
- /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
- multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
-
- /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
- multAcc_32x32_keep32_R(outI, *pIn2--, CoefA2);
-
- /* write output */
- *pDst++ = outR;
- *pDst++ = outI;
-
- /* update coefficient pointer */
- pCoefB = pCoefB + (modifier * 2u);
- pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
- /* Decrement loop count */
- fftLen--;
- }
-}
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
deleted file mode 100644
index 2d8fee4..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
+++ /dev/null
@@ -1,25547 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h743xx.h
- * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral's registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS_Device
- * @{
- */
-
-/** @addtogroup stm32h743xx
- * @{
- */
-
-#ifndef STM32H743xx_H
-#define STM32H743xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32H7XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
- FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
- FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
- FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
- FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- RNG_IRQn = 80, /*!< RNG global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
- LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
- CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
- I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
- I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
- SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
- OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
- OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
- OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
- OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
- DMAMUX1_OVR_IRQn = 102, /*!
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
- __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
- __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
- uint32_t RESERVED1; /*!< Reserved, 0x028 */
- uint32_t RESERVED2; /*!< Reserved, 0x02C */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
- __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- uint32_t RESERVED3; /*!< Reserved, 0x044 */
- uint32_t RESERVED4; /*!< Reserved, 0x048 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
- uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
- __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
- __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
- __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
- __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
- uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
- uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
- __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
- __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
- uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
- uint32_t RESERVED9; /*!< Reserved, 0x0AC */
- __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
- __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
- __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
- __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
- __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
- __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
- __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
-} ADC_TypeDef;
-
-
-typedef struct
-{
-__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
-uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
-__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
-__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
-__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
-} ADC_Common_TypeDef;
-
-/**
- * @brief VREFBUF
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
- __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
- __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
- __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
- __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
- __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
- __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
- __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
- __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
- __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
- __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
- __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
- __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
- __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
- __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
- __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
- __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
- __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
- __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
- __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
- __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
- __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
- __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
- __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
- __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
- __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
- __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
- __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
- __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
- __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
- __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
- __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
- __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
- __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
- __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
- __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
- __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
- __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
- __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
- __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
- __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
- __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
- __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
- __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
- __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
- __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
- __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
- __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
- __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
- __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
- __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
- __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
- __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
-} FDCAN_GlobalTypeDef;
-
-/**
- * @brief TTFD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
- __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
- __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
- __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
- __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
- __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
- __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
- __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
- __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
- __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
- __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
- __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
- __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
- __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
- __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
- __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
- __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
- __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
- __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
-} TTCAN_TypeDef;
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
- __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
- __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
- __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
- __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
- __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
-} FDCAN_ClockCalibrationUnit_TypeDef;
-
-
-/**
- * @brief Consumer Electronics Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
- __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
- __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
- __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
- __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
- __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
- __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
- __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
- __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
- __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
- uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
- __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
-}DBGMCU_TypeDef;
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} BDMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} BDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< DMA Channel Status Register */
- __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
- __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
- * @brief MDMA Controller
- */
-typedef struct
-{
- __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
-}MDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
- __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
- __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
- __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
- __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
- __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
- __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
- __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
- __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
- __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
- __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
- __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
- __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
-}MDMA_Channel_TypeDef;
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACECR;
- __IO uint32_t MACPFR;
- __IO uint32_t MACWTR;
- __IO uint32_t MACHT0R;
- __IO uint32_t MACHT1R;
- uint32_t RESERVED1[14];
- __IO uint32_t MACVTR;
- uint32_t RESERVED2;
- __IO uint32_t MACVHTR;
- uint32_t RESERVED3;
- __IO uint32_t MACVIR;
- __IO uint32_t MACIVIR;
- uint32_t RESERVED4[2];
- __IO uint32_t MACTFCR;
- uint32_t RESERVED5[7];
- __IO uint32_t MACRFCR;
- uint32_t RESERVED6[7];
- __IO uint32_t MACISR;
- __IO uint32_t MACIER;
- __IO uint32_t MACRXTXSR;
- uint32_t RESERVED7;
- __IO uint32_t MACPCSR;
- __IO uint32_t MACRWKPFR;
- uint32_t RESERVED8[2];
- __IO uint32_t MACLCSR;
- __IO uint32_t MACLTCR;
- __IO uint32_t MACLETR;
- __IO uint32_t MAC1USTCR;
- uint32_t RESERVED9[12];
- __IO uint32_t MACVR;
- __IO uint32_t MACDR;
- uint32_t RESERVED10;
- __IO uint32_t MACHWF0R;
- __IO uint32_t MACHWF1R;
- __IO uint32_t MACHWF2R;
- uint32_t RESERVED11[54];
- __IO uint32_t MACMDIOAR;
- __IO uint32_t MACMDIODR;
- uint32_t RESERVED12[2];
- __IO uint32_t MACARPAR;
- uint32_t RESERVED13[59];
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR;
- uint32_t RESERVED14[248];
- __IO uint32_t MMCCR;
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR;
- uint32_t RESERVED15[14];
- __IO uint32_t MMCTSCGPR;
- __IO uint32_t MMCTMCGPR;
- int32_t RESERVED16[5];
- __IO uint32_t MMCTPCGR;
- uint32_t RESERVED17[10];
- __IO uint32_t MMCRCRCEPR;
- __IO uint32_t MMCRAEPR;
- uint32_t RESERVED18[10];
- __IO uint32_t MMCRUPGR;
- uint32_t RESERVED19[9];
- __IO uint32_t MMCTLPIMSTR;
- __IO uint32_t MMCTLPITCR;
- __IO uint32_t MMCRLPIMSTR;
- __IO uint32_t MMCRLPITCR;
- uint32_t RESERVED20[65];
- __IO uint32_t MACL3L4C0R;
- __IO uint32_t MACL4A0R;
- uint32_t RESERVED21[2];
- __IO uint32_t MACL3A0R0R;
- __IO uint32_t MACL3A1R0R;
- __IO uint32_t MACL3A2R0R;
- __IO uint32_t MACL3A3R0R;
- uint32_t RESERVED22[4];
- __IO uint32_t MACL3L4C1R;
- __IO uint32_t MACL4A1R;
- uint32_t RESERVED23[2];
- __IO uint32_t MACL3A0R1R;
- __IO uint32_t MACL3A1R1R;
- __IO uint32_t MACL3A2R1R;
- __IO uint32_t MACL3A3R1R;
- uint32_t RESERVED24[108];
- __IO uint32_t MACTSCR;
- __IO uint32_t MACSSIR;
- __IO uint32_t MACSTSR;
- __IO uint32_t MACSTNR;
- __IO uint32_t MACSTSUR;
- __IO uint32_t MACSTNUR;
- __IO uint32_t MACTSAR;
- uint32_t RESERVED25;
- __IO uint32_t MACTSSR;
- uint32_t RESERVED26[3];
- __IO uint32_t MACTTSSNR;
- __IO uint32_t MACTTSSSR;
- uint32_t RESERVED27[2];
- __IO uint32_t MACACR;
- uint32_t RESERVED28;
- __IO uint32_t MACATSNR;
- __IO uint32_t MACATSSR;
- __IO uint32_t MACTSIACR;
- __IO uint32_t MACTSEACR;
- __IO uint32_t MACTSICNR;
- __IO uint32_t MACTSECNR;
- uint32_t RESERVED29[4];
- __IO uint32_t MACPPSCR;
- uint32_t RESERVED30[3];
- __IO uint32_t MACPPSTTSR;
- __IO uint32_t MACPPSTTNR;
- __IO uint32_t MACPPSIR;
- __IO uint32_t MACPPSWR;
- uint32_t RESERVED31[12];
- __IO uint32_t MACPOCR;
- __IO uint32_t MACSPI0R;
- __IO uint32_t MACSPI1R;
- __IO uint32_t MACSPI2R;
- __IO uint32_t MACLMIR;
- uint32_t RESERVED32[11];
- __IO uint32_t MTLOMR;
- uint32_t RESERVED33[7];
- __IO uint32_t MTLISR;
- uint32_t RESERVED34[55];
- __IO uint32_t MTLTQOMR;
- __IO uint32_t MTLTQUR;
- __IO uint32_t MTLTQDR;
- uint32_t RESERVED35[8];
- __IO uint32_t MTLQICSR;
- __IO uint32_t MTLRQOMR;
- __IO uint32_t MTLRQMPOCR;
- __IO uint32_t MTLRQDR;
- uint32_t RESERVED36[177];
- __IO uint32_t DMAMR;
- __IO uint32_t DMASBMR;
- __IO uint32_t DMAISR;
- __IO uint32_t DMADSR;
- uint32_t RESERVED37[60];
- __IO uint32_t DMACCR;
- __IO uint32_t DMACTCR;
- __IO uint32_t DMACRCR;
- uint32_t RESERVED38[2];
- __IO uint32_t DMACTDLAR;
- uint32_t RESERVED39;
- __IO uint32_t DMACRDLAR;
- __IO uint32_t DMACTDTPR;
- uint32_t RESERVED40;
- __IO uint32_t DMACRDTPR;
- __IO uint32_t DMACTDRLR;
- __IO uint32_t DMACRDRLR;
- __IO uint32_t DMACIER;
- __IO uint32_t DMACRIWTR;
-__IO uint32_t DMACSFCSR;
- uint32_t RESERVED41;
- __IO uint32_t DMACCATDR;
- uint32_t RESERVED42;
- __IO uint32_t DMACCARDR;
- uint32_t RESERVED43;
- __IO uint32_t DMACCATBR;
- uint32_t RESERVED44;
- __IO uint32_t DMACCARBR;
- __IO uint32_t DMACSR;
-uint32_t RESERVED45[2];
-__IO uint32_t DMACMFCR;
-}ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
-__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
-__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
-__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
-__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, Address offset: 0x0C */
-__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x10 */
-__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x14 */
-uint32_t RESERVED1; /*!< Reserved, 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
-__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
-__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
-__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, Address offset: 0x2C */
-__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x30 */
-__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x34 */
-uint32_t RESERVED3; /*!< Reserved, 0x38 */
-uint32_t RESERVED4; /*!< Reserved, 0x3C */
-__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
-__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
-__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
-__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, Address offset: 0x4C */
-__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x50 */
-__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x54 */
-}EXTI_TypeDef;
-
-typedef struct
-{
-__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
-__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
-__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
-uint32_t RESERVED1; /*!< Reserved, 0x0C */
-__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
-__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
-__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
-__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
-__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
-}EXTI_Core_TypeDef;
-
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
- __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
- __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
- __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
- __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
- __IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */
- __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
- __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
- __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
- __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
- __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */
- __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
- __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
- __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
- __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
- __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
- __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
- __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
- __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
- __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
- uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
- __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
- uint32_t RESERVED2; /*!< Reserved, 0x108 */
- __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
- __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
- __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
- uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
- __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
- __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
- __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
- __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
- __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
- __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
- uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
- __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
- __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
- __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
- __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
- __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5 and 6
- */
-
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief Operational Amplifier (OPAMP)
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
- __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
- __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
- __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
- __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
- __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
- __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
- uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
- __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
- uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
- __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
- __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
- __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
- __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
- __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
- __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
- __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
- __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
- __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
- __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
- __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
- __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
- __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
- __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
- __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
- __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
- __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
- __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
-
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
- * @brief JPEG Codec
- */
-typedef struct
-{
- __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
- __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
- __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
- __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
- __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
- __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
- __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
- __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
- uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
- __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
- __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
- __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
- uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
- __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
- __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
- uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
- __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
- __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
- __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
- __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
- __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
- __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
- __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
- __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
- uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
- __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
- __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
- __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
- __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
- __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
- __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
- __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
- __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
- __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
- __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
- __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
- __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
- __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
- __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
- __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
- __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
- __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
- __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
- __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
- __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
- __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
- __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
- __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
- __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
- __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
- __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
- __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
- __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
- __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
- __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
- __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA4 */
- __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
- uint32_t RESERVED8[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
- __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
- __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
- __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
- __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
- __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
- __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
- uint32_t RESERVED9; /*!< Reserved, Address offset: 0xF8 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
- __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
- __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
- __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
- __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
- __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
- uint32_t RESERVED10[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
-
-} RCC_TypeDef;
-
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- uint32_t reserved; /*!< Reserved */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAMPCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
- __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
- __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
- __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
- __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
- __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
- __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
- __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
- __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
- __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
- __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
- __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
- __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
- __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
- uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
- __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
- __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SPDIF-RX Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-
-
-/**
- * @brief Secure digital input/output Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
- __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
- uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
- __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
- __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
- __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
- __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
- uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
- uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
- __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
-} SDMMC_TypeDef;
-
-
-/**
- * @brief Delay Block DLYB
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
-} DLYB_TypeDef;
-
-/**
- * @brief HW Semaphore HSEM
- */
-
-typedef struct
-{
- __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
- __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
- __IO uint32_t IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
- __IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
- __IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
- __IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
- uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
- __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
- __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
-
-} HSEM_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- __IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
- __IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
- __IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
- __IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
- __IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
- uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
- __IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
- uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
- __IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
- __IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
- __IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
- __IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
- __IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
-
-} SPI_TypeDef;
-
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- uint16_t RESERVED14; /*!< Reserved, 0x50 */
- __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
- __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
- __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
- __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
- __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
- __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
-} TIM_TypeDef;
-
-/**
- * @brief LPTIMIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- uint16_t RESERVED1; /*!< Reserved, 0x20 */
- __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
-} LPTIM_TypeDef;
-
-/**
- * @brief Comparator
- */
-typedef struct
-{
- __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
- __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
- __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
-} COMPOPT_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- uint16_t RESERVED2; /*!< Reserved, 0x12 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
- uint16_t RESERVED3; /*!< Reserved, 0x1A */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- uint16_t RESERVED4; /*!< Reserved, 0x26 */
- __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- uint16_t RESERVED5; /*!< Reserved, 0x2A */
- __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
-} USART_TypeDef;
-
-/**
- * @brief Single Wire Protocol Master Interface SPWMI
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
- __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
- uint32_t RESERVED1; /*!< Reserved, 0x08 */
- __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
- __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
- __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
- __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
- __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
- __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
-} SWPMI_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief High resolution Timer (HRTIM)
- */
-/* HRTIM master registers definition */
-typedef struct
-{
- __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
- __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
- __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
- __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
- __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
- __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
- __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
- uint32_t RESERVED0; /*!< Reserved, 0x20 */
- __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
- __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
- __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
- uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
-}HRTIM_Master_TypeDef;
-
-/* HRTIM Timer A to E registers definition */
-typedef struct
-{
- __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
- __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
- __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
- __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
- __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
- __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
- __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
- __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
- __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
- __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
- __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
- __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
- __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
- __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
- __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
- __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
- __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
- __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
- __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
- __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
- __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
- __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
- __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
- __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
- __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
- __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
- uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
-}HRTIM_Timerx_TypeDef;
-
-/* HRTIM common register definition */
-typedef struct
-{
- __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
- __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
- __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
- __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
- __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
- __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
- __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
- __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
- __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
- __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
- __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
- __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
- __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
- __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
- __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
- __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
- __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
- __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
- __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
- __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
- __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
- __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
- __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
- __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
- __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
- __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
- __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
-}HRTIM_Common_TypeDef;
-
-/* HRTIM register definition */
-typedef struct {
- HRTIM_Master_TypeDef sMasterRegs;
- HRTIM_Timerx_TypeDef sTimerxRegs[5];
- uint32_t RESERVED0[32];
- HRTIM_Common_TypeDef sCommonRegs;
-}HRTIM_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @brief MDIOS
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t WRFR;
- __IO uint32_t CWRFR;
- __IO uint32_t RDFR;
- __IO uint32_t CRDFR;
- __IO uint32_t SR;
- __IO uint32_t CLRFR;
- uint32_t RESERVED[57];
- __IO uint32_t DINR0;
- __IO uint32_t DINR1;
- __IO uint32_t DINR2;
- __IO uint32_t DINR3;
- __IO uint32_t DINR4;
- __IO uint32_t DINR5;
- __IO uint32_t DINR6;
- __IO uint32_t DINR7;
- __IO uint32_t DINR8;
- __IO uint32_t DINR9;
- __IO uint32_t DINR10;
- __IO uint32_t DINR11;
- __IO uint32_t DINR12;
- __IO uint32_t DINR13;
- __IO uint32_t DINR14;
- __IO uint32_t DINR15;
- __IO uint32_t DINR16;
- __IO uint32_t DINR17;
- __IO uint32_t DINR18;
- __IO uint32_t DINR19;
- __IO uint32_t DINR20;
- __IO uint32_t DINR21;
- __IO uint32_t DINR22;
- __IO uint32_t DINR23;
- __IO uint32_t DINR24;
- __IO uint32_t DINR25;
- __IO uint32_t DINR26;
- __IO uint32_t DINR27;
- __IO uint32_t DINR28;
- __IO uint32_t DINR29;
- __IO uint32_t DINR30;
- __IO uint32_t DINR31;
- __IO uint32_t DOUTR0;
- __IO uint32_t DOUTR1;
- __IO uint32_t DOUTR2;
- __IO uint32_t DOUTR3;
- __IO uint32_t DOUTR4;
- __IO uint32_t DOUTR5;
- __IO uint32_t DOUTR6;
- __IO uint32_t DOUTR7;
- __IO uint32_t DOUTR8;
- __IO uint32_t DOUTR9;
- __IO uint32_t DOUTR10;
- __IO uint32_t DOUTR11;
- __IO uint32_t DOUTR12;
- __IO uint32_t DOUTR13;
- __IO uint32_t DOUTR14;
- __IO uint32_t DOUTR15;
- __IO uint32_t DOUTR16;
- __IO uint32_t DOUTR17;
- __IO uint32_t DOUTR18;
- __IO uint32_t DOUTR19;
- __IO uint32_t DOUTR20;
- __IO uint32_t DOUTR21;
- __IO uint32_t DOUTR22;
- __IO uint32_t DOUTR23;
- __IO uint32_t DOUTR24;
- __IO uint32_t DOUTR25;
- __IO uint32_t DOUTR26;
- __IO uint32_t DOUTR27;
- __IO uint32_t DOUTR28;
- __IO uint32_t DOUTR29;
- __IO uint32_t DOUTR30;
- __IO uint32_t DOUTR31;
-} MDIOS_TypeDef;
-
-
-/**
- * @brief USB_OTG_Core_Registers
- */
-typedef struct
-{
- __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
- __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
- __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
- __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
- __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
- __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
- __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
- __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
- __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
- __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
- __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
- uint32_t Reserved30[2]; /*!< Reserved 030h */
- __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
- __IO uint32_t CID; /*!< User ID Register 03Ch */
- __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
- __IO uint32_t GHWCFG1; /* User HW config1 044h*/
- __IO uint32_t GHWCFG2; /* User HW config2 048h*/
- __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
- uint32_t Reserved6; /*!< Reserved 050h */
- __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
- __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
- __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
- * @brief USB_OTG_device_Registers
- */
-typedef struct
-{
- __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
- __IO uint32_t DCTL; /*!< dev Control Register 804h */
- __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
- uint32_t Reserved0C; /*!< Reserved 80Ch */
- __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
- __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
- __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
- __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
- uint32_t Reserved20; /*!< Reserved 820h */
- uint32_t Reserved9; /*!< Reserved 824h */
- __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
- __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
- __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
- __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
- __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
- __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
- uint32_t Reserved40; /*!< dedicated EP mask 840h */
- __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
- uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
- __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
- * @brief USB_OTG_IN_Endpoint-Specific_Register
- */
-typedef struct
-{
- __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_OUT_Endpoint-Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
- __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
- __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
- uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_Host_Mode_Register_Structures
- */
-typedef struct
-{
- __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
- __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
- __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
- uint32_t Reserved40C; /*!< Reserved 40Ch */
- __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
- __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
- __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
-} USB_OTG_HostTypeDef;
-
-/**
- * @brief USB_OTG_Host_Channel_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
- __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
- __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
- __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
- __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
- __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
- uint32_t Reserved[2]; /*!< Reserved */
-} USB_OTG_HostChannelTypeDef;
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define D1_ITCMRAM_BASE ((uint32_t)0x00000000) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define D1_ITCMICP_BASE ((uint32_t)0x00100000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
-#define D1_DTCMRAM_BASE ((uint32_t)0x20000000) /*!< Base address of : 128KB system data RAM accessible over DTCM */
-#define D1_AXIFLASH_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
-#define D1_AXIICP_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
-#define D1_AXISRAM_BASE ((uint32_t)0x24000000) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
-
-#define D2_AXISRAM_BASE ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
-#define D2_AHBSRAM_BASE ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
-
-#define D3_BKPSRAM_BASE ((uint32_t)0x38800000) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
-#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
-
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
-#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
-
-#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
-#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
-#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
-
-#define FLASH_OTP_BANK1_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-#define FLASH_OTP_BANK1_END ((uint32_t)0x1FF1FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-#define FLASH_OTP_BANK2_BASE ((uint32_t)0x1FF40000) /*!< Base address of : (up to 128KB) embedded FLASH Bank2 OTP Area */
-#define FLASH_OTP_BANK2_END ((uint32_t)0x1FF5FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank2 OTP Area */
-
-/* Legacy define */
-#define FLASH_BASE FLASH_BANK1_BASE
-
-
-/*!< Peripheral memory map */
-#define D2_APB1PERIPH_BASE PERIPH_BASE
-#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000)
-
-#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000)
-
-#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000)
-#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000)
-
-/*!< Legacy Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-/*!< D1_AHB1PERIPH peripherals */
-
-#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000)
-#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000)
-#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000)
-#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000)
-#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000)
-#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000)
-#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000)
-#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000)
-#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000)
-
-/*!< D2_AHB1PERIPH peripherals */
-
-#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000)
-#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400)
-#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800)
-#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000)
-#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100)
-#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300)
-#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400)
-#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-
-/*!< USB registers base address */
-#define USB1_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
-#define USB2_OTG_FS_PERIPH_BASE ((uint32_t )0x40080000)
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
-
-/*!< D2_AHB2PERIPH peripherals */
-
-#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000)
-#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800)
-#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400)
-#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800)
-
-
-/*!< D3_AHB1PERIPH peripherals */
-#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800)
-#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400)
-#define RCC_C1_BASE (RCC_BASE + 0x130)
-#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800)
-#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00)
-#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400)
-#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800)
-#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000)
-#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300)
-#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400)
-
-/*!< D1_APB1PERIPH peripherals */
-#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000)
-
-/*!< D2_APB1PERIPH peripherals */
-#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000)
-#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400)
-
-
-#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00)
-#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00)
-#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00)
-#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00)
-#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400)
-#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800)
-#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010)
-#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400)
-#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000)
-#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400)
-#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800)
-#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00)
-
-/*!< D2_APB2PERIPH peripherals */
-
-#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400)
-#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400)
-#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000)
-#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000)
-#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
-#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
-#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
-#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
-#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
-#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
-#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
-#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
-#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
-#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400)
-#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
-#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
-#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
-#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
-#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
-#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
-
-
-/*!< D3_APB1PERIPH peripherals */
-#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000)
-#define EXTI_D1_BASE (EXTI_BASE + 0x0080)
-#define EXTI_D2_BASE (EXTI_BASE + 0x00C0)
-#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400)
-#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00)
-#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400)
-#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00)
-#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400)
-#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800)
-#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00)
-#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000)
-#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800)
-#define COMP1_BASE (COMP12_BASE + 0x0C)
-#define COMP2_BASE (COMP12_BASE + 0x10)
-#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00)
-#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000)
-#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800)
-
-
-#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400)
-#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
-#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
-
-
-#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008)
-#define BDMA_Channel1_BASE (BDMA_BASE + 0x001C)
-#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030)
-#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044)
-#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058)
-#define BDMA_Channel5_BASE (BDMA_BASE + 0x006C)
-#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080)
-#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094)
-
-#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
-#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004)
-#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008)
-#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000C)
-#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010)
-#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014)
-#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018)
-#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001C)
-
-#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100)
-#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104)
-#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108)
-#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010C)
-#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110)
-#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114)
-#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118)
-#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011C)
-
-#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080)
-#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140)
-
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-
-#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
-#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
-#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
-#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
-#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
-#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
-#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
-#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
-#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
-#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
-#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
-#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
-#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
-#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
-#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
-
-#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
-#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
-#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
-#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
-#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110)
-#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114)
-#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118)
-#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011C)
-
-#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
-#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
-
-
-
-/*!< FMC Banks registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0x5C001000)
-
-#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
-#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
-#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
-#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
-#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
-#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
-#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
-#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
-#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
-#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
-#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
-#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
-#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
-#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
-#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
-#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
-
-
-#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
-#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
-#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
-#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
-#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
-#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
-#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
-#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
-
-
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
-#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
-#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
-#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
-#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
-#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
-#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
-#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
-#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
-#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
-#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
-#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
-#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
-#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
-
-
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
-#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
-
-#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
-#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
-#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
-#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
-#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
-#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
-#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
-#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
-#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
-
-#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
-#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
-#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
-#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
-#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
-#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
-#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
-#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
-
-
-#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
-#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
-#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
-#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
-#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
-#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
-#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
-#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
-
-#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
-#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
-
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
-
-#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
-#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
-
-#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
-#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
-#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
-#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
-
-#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
-
-#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
-#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
-
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-
-#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
-
-#define ETH ((ETH_TypeDef *)ETH_BASE)
-#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
-#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
-#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
-#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
-#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
-#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
-#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
-#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
-#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
-#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
-#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
-#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
-#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
-#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
-#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
-#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
-#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
-
-
-#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
-#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
-
-
-/* Legacy defines */
-#define USB_OTG_HS USB1_OTG_HS
-#define USB_OTG_FS USB2_OTG_FS
-#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
-#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_ISR register ********************/
-#define ADC_ISR_ADRD_Pos (0U)
-#define ADC_ISR_ADRD_Msk (0x1U << ADC_ISR_ADRD_Pos) /*!< 0x00000001 */
-#define ADC_ISR_ADRD ADC_ISR_ADRD_Msk /*!< ADC Ready (ADRDY) flag */
-#define ADC_ISR_EOSMP_Pos (1U)
-#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
-#define ADC_ISR_EOC_Pos (2U)
-#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
-#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
-#define ADC_ISR_EOS_Pos (3U)
-#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
-#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_ISR_OVR_Pos (4U)
-#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
-#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
-#define ADC_ISR_JEOC_Pos (5U)
-#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
-#define ADC_ISR_JEOS_Pos (6U)
-#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_ISR_AWD1_Pos (7U)
-#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos (8U)
-#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos (9U)
-#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
-#define ADC_ISR_JQOVF_Pos (10U)
-#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
-
-/******************** Bit definition for ADC_IER register ********************/
-#define ADC_IER_RDY_Pos (0U)
-#define ADC_IER_RDY_Msk (0x1U << ADC_IER_RDY_Pos) /*!< 0x00000001 */
-#define ADC_IER_RDY ADC_IER_RDY_Msk /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IER_EOSMP_Pos (1U)
-#define ADC_IER_EOSMP_Msk (0x1U << ADC_IER_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_IER_EOSMP ADC_IER_EOSMP_Msk /*!< ADC End of Sampling interrupt source */
-#define ADC_IER_EOC_Pos (2U)
-#define ADC_IER_EOC_Msk (0x1U << ADC_IER_EOC_Pos) /*!< 0x00000004 */
-#define ADC_IER_EOC ADC_IER_EOC_Msk /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IER_EOS_Pos (3U)
-#define ADC_IER_EOS_Msk (0x1U << ADC_IER_EOS_Pos) /*!< 0x00000008 */
-#define ADC_IER_EOS ADC_IER_EOS_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IER_OVR_Pos (4U)
-#define ADC_IER_OVR_Msk (0x1U << ADC_IER_OVR_Pos) /*!< 0x00000010 */
-#define ADC_IER_OVR ADC_IER_OVR_Msk /*!< ADC overrun interrupt source */
-#define ADC_IER_JEOC_Pos (5U)
-#define ADC_IER_JEOC_Msk (0x1U << ADC_IER_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_IER_JEOC ADC_IER_JEOC_Msk /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IER_JEOS_Pos (6U)
-#define ADC_IER_JEOS_Msk (0x1U << ADC_IER_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_IER_JEOS ADC_IER_JEOS_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IER_AWD1_Pos (7U)
-#define ADC_IER_AWD1_Msk (0x1U << ADC_IER_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_IER_AWD1 ADC_IER_AWD1_Msk /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IER_AWD2_Pos (8U)
-#define ADC_IER_AWD2_Msk (0x1U << ADC_IER_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_IER_AWD2 ADC_IER_AWD2_Msk /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IER_AWD3_Pos (9U)
-#define ADC_IER_AWD3_Msk (0x1U << ADC_IER_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_IER_AWD3 ADC_IER_AWD3_Msk /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IER_JQOVF_Pos (10U)
-#define ADC_IER_JQOVF_Msk (0x1U << ADC_IER_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_IER_JQOVF ADC_IER_JQOVF_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
-
-/******************** Bit definition for ADC_CR register ********************/
-#define ADC_CR_ADEN_Pos (0U)
-#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
-#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
-#define ADC_CR_ADDIS_Pos (1U)
-#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
-#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
-#define ADC_CR_ADSTART_Pos (2U)
-#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
-#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
-#define ADC_CR_JADSTART_Pos (3U)
-#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
-#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
-#define ADC_CR_ADSTP_Pos (4U)
-#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
-#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
-#define ADC_CR_JADSTP_Pos (5U)
-#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
-#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Boost Mode */
-#define ADC_CR_BOOST_Pos (8U)
-#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
-#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Stop of injected conversion */
-#define ADC_CR_ADCALLIN_Pos (16U)
-#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
-#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
-#define ADC_CR_LINCALRDYW1_Pos (22U)
-#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
-#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
-#define ADC_CR_LINCALRDYW2_Pos (23U)
-#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
-#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
-#define ADC_CR_LINCALRDYW3_Pos (24U)
-#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
-#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
-#define ADC_CR_LINCALRDYW4_Pos (25U)
-#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
-#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
-#define ADC_CR_LINCALRDYW5_Pos (26U)
-#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
-#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
-#define ADC_CR_LINCALRDYW6_Pos (27U)
-#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
-#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
-#define ADC_CR_ADVREGEN_Pos (28U)
-#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
-#define ADC_CR_DEEPPWD_Pos (29U)
-#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
-#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
-#define ADC_CR_ADCALDIF_Pos (30U)
-#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
-#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
-#define ADC_CR_ADCAL_Pos (31U)
-#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
-#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
-
-/******************** Bit definition for ADC_CFGR register ********************/
-#define ADC_CFGR_DMNGT_Pos (0U)
-#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
-#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
-#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
-#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
-
-#define ADC_CFGR_RES_Pos (2U)
-#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
-#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
-#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
-#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
-#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
-
-#define ADC_CFGR_EXTSEL_Pos (5U)
-#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
-#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
-#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
-#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
-#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
-
-#define ADC_CFGR_EXTEN_Pos (10U)
-#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
-#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
-#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
-#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
-
-#define ADC_CFGR_OVRMOD_Pos (12U)
-#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
-#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
-#define ADC_CFGR_CONT_Pos (13U)
-#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
-#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
-#define ADC_CFGR_AUTDLY_Pos (14U)
-#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
-#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
-
-#define ADC_CFGR_DISCEN_Pos (16U)
-#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
-#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
-
-#define ADC_CFGR_DISCNUM_Pos (17U)
-#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
-#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
-#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
-#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
-
-#define ADC_CFGR_JDISCEN_Pos (20U)
-#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
-#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
-#define ADC_CFGR_JQM_Pos (21U)
-#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
-#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
-#define ADC_CFGR_AWD1SGL_Pos (22U)
-#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
-#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
-#define ADC_CFGR_AWD1EN_Pos (23U)
-#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
-#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
-#define ADC_CFGR_JAWD1EN_Pos (24U)
-#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
-#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
-#define ADC_CFGR_JAUTO_Pos (25U)
-#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
-#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
-
-#define ADC_CFGR_AWD1CH_Pos (26U)
-#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
-#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
-#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
-#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
-#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
-#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
-#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
-
-#define ADC_CFGR_JQDIS_Pos (31U)
-#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
-#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
-
-/******************** Bit definition for ADC_CFGR2 register ********************/
-#define ADC_CFGR2_ROVSE_Pos (0U)
-#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
-#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
-#define ADC_CFGR2_JOVSE_Pos (1U)
-#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
-#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
-
-#define ADC_CFGR2_OVSS_Pos (5U)
-#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
-#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
-
-#define ADC_CFGR2_TROVS_Pos (9U)
-#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
-#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
-#define ADC_CFGR2_ROVSM_Pos (10U)
-#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
-#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
-
-#define ADC_CFGR2_RSHIFT1_Pos (11U)
-#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
-#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
-#define ADC_CFGR2_RSHIFT2_Pos (12U)
-#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
-#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
-#define ADC_CFGR2_RSHIFT3_Pos (13U)
-#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
-#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
-#define ADC_CFGR2_RSHIFT4_Pos (14U)
-#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
-#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
-
-#define ADC_CFGR2_OSR_Pos (16U)
-#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
-#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
-#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
-#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
-#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
-#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
-#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
-#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
-#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
-#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
-#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
-#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
-
-#define ADC_CFGR2_LSHIFT_Pos (28U)
-#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
-#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
-#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
-#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
-#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
-#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_SMPR1 register ********************/
-#define ADC_SMPR1_SMP0_Pos (0U)
-#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
-#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP1_Pos (3U)
-#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
-#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP2_Pos (6U)
-#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
-#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP3_Pos (9U)
-#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
-#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP4_Pos (12U)
-#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
-#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP5_Pos (15U)
-#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
-#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP6_Pos (18U)
-#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
-#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP7_Pos (21U)
-#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
-#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP8_Pos (24U)
-#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
-#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP9_Pos (27U)
-#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
-#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_SMPR2 register ********************/
-#define ADC_SMPR2_SMP10_Pos (0U)
-#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
-#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos (3U)
-#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
-#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos (6U)
-#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
-#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos (9U)
-#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
-#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos (12U)
-#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
-#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos (15U)
-#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
-#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos (18U)
-#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
-#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos (21U)
-#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
-#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos (24U)
-#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
-#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos (27U)
-#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
-#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_PCSEL register ********************/
-#define ADC_PCSEL_PCSEL_Pos (0U)
-#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
-#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
-#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
-#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
-#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
-#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
-#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
-#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
-#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
-#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
-#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
-#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
-#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
-#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
-#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
-#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
-#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
-#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
-#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
-#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
-#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_LTR1 register ********************/
-#define ADC_LTR1_LT1_Pos (0U)
-#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
-#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
-#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
-#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
-#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
-#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
-#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
-#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
-#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
-#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
-#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
-#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
-#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
-#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
-#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
-#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
-#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
-#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
-#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
-#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
-#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
-#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
-#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
-#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
-#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
-#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
-#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR1 register ********************/
-#define ADC_HTR1_HT1_Pos (0U)
-#define ADC_HTR1_HT1_Msk (0x3FFFFFFU << ADC_HTR1_HT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR1_HT1 ADC_HTR1_HT1_Msk /*!< ADC Analog watchdog 1 higher threshold */
-#define ADC_HTR1_HT1_0 (0x0000001U << ADC_HTR1_HT1_Pos) /*!< 0x00000001 */
-#define ADC_HTR1_HT1_1 (0x0000002U << ADC_HTR1_HT1_Pos) /*!< 0x00000002 */
-#define ADC_HTR1_HT1_2 (0x0000004U << ADC_HTR1_HT1_Pos) /*!< 0x00000004 */
-#define ADC_HTR1_HT1_3 (0x0000008U << ADC_HTR1_HT1_Pos) /*!< 0x00000008 */
-#define ADC_HTR1_HT1_4 (0x0000010U << ADC_HTR1_HT1_Pos) /*!< 0x00000010 */
-#define ADC_HTR1_HT1_5 (0x0000020U << ADC_HTR1_HT1_Pos) /*!< 0x00000020 */
-#define ADC_HTR1_HT1_6 (0x0000040U << ADC_HTR1_HT1_Pos) /*!< 0x00000040 */
-#define ADC_HTR1_HT1_7 (0x0000080U << ADC_HTR1_HT1_Pos) /*!< 0x00000080 */
-#define ADC_HTR1_HT1_8 (0x0000100U << ADC_HTR1_HT1_Pos) /*!< 0x00000100 */
-#define ADC_HTR1_HT1_9 (0x0000200U << ADC_HTR1_HT1_Pos) /*!< 0x00000200 */
-#define ADC_HTR1_HT1_10 (0x0000400U << ADC_HTR1_HT1_Pos) /*!< 0x00000400 */
-#define ADC_HTR1_HT1_11 (0x0000800U << ADC_HTR1_HT1_Pos) /*!< 0x00000800 */
-#define ADC_HTR1_HT1_12 (0x0001000U << ADC_HTR1_HT1_Pos) /*!< 0x00001000 */
-#define ADC_HTR1_HT1_13 (0x0002000U << ADC_HTR1_HT1_Pos) /*!< 0x00002000 */
-#define ADC_HTR1_HT1_14 (0x0004000U << ADC_HTR1_HT1_Pos) /*!< 0x00004000 */
-#define ADC_HTR1_HT1_15 (0x0008000U << ADC_HTR1_HT1_Pos) /*!< 0x00008000 */
-#define ADC_HTR1_HT1_16 (0x0010000U << ADC_HTR1_HT1_Pos) /*!< 0x00010000 */
-#define ADC_HTR1_HT1_17 (0x0020000U << ADC_HTR1_HT1_Pos) /*!< 0x00020000 */
-#define ADC_HTR1_HT1_18 (0x0040000U << ADC_HTR1_HT1_Pos) /*!< 0x00040000 */
-#define ADC_HTR1_HT1_19 (0x0080000U << ADC_HTR1_HT1_Pos) /*!< 0x00080000 */
-#define ADC_HTR1_HT1_20 (0x0100000U << ADC_HTR1_HT1_Pos) /*!< 0x00100000 */
-#define ADC_HTR1_HT1_21 (0x0200000U << ADC_HTR1_HT1_Pos) /*!< 0x00200000 */
-#define ADC_HTR1_HT1_22 (0x0400000U << ADC_HTR1_HT1_Pos) /*!< 0x00400000 */
-#define ADC_HTR1_HT1_23 (0x0800000U << ADC_HTR1_HT1_Pos) /*!< 0x00800000 */
-#define ADC_HTR1_HT1_24 (0x1000000U << ADC_HTR1_HT1_Pos) /*!< 0x01000000 */
-#define ADC_HTR1_HT1_25 (0x2000000U << ADC_HTR1_HT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR2 register ********************/
-#define ADC_LTR2_LT2_Pos (0U)
-#define ADC_LTR2_LT2_Msk (0x3FFFFFFU << ADC_LTR2_LT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR2_LT2 ADC_LTR2_LT2_Msk /*!< ADC Analog watchdog 2 lower threshold */
-#define ADC_LTR2_LT2_0 (0x0000001U << ADC_LTR2_LT2_Pos) /*!< 0x00000001 */
-#define ADC_LTR2_LT2_1 (0x0000002U << ADC_LTR2_LT2_Pos) /*!< 0x00000002 */
-#define ADC_LTR2_LT2_2 (0x0000004U << ADC_LTR2_LT2_Pos) /*!< 0x00000004 */
-#define ADC_LTR2_LT2_3 (0x0000008U << ADC_LTR2_LT2_Pos) /*!< 0x00000008 */
-#define ADC_LTR2_LT2_4 (0x0000010U << ADC_LTR2_LT2_Pos) /*!< 0x00000010 */
-#define ADC_LTR2_LT2_5 (0x0000020U << ADC_LTR2_LT2_Pos) /*!< 0x00000020 */
-#define ADC_LTR2_LT2_6 (0x0000040U << ADC_LTR2_LT2_Pos) /*!< 0x00000040 */
-#define ADC_LTR2_LT2_7 (0x0000080U << ADC_LTR2_LT2_Pos) /*!< 0x00000080 */
-#define ADC_LTR2_LT2_8 (0x0000100U << ADC_LTR2_LT2_Pos) /*!< 0x00000100 */
-#define ADC_LTR2_LT2_9 (0x0000200U << ADC_LTR2_LT2_Pos) /*!< 0x00000200 */
-#define ADC_LTR2_LT2_10 (0x0000400U << ADC_LTR2_LT2_Pos) /*!< 0x00000400 */
-#define ADC_LTR2_LT2_11 (0x0000800U << ADC_LTR2_LT2_Pos) /*!< 0x00000800 */
-#define ADC_LTR2_LT2_12 (0x0001000U << ADC_LTR2_LT2_Pos) /*!< 0x00001000 */
-#define ADC_LTR2_LT2_13 (0x0002000U << ADC_LTR2_LT2_Pos) /*!< 0x00002000 */
-#define ADC_LTR2_LT2_14 (0x0004000U << ADC_LTR2_LT2_Pos) /*!< 0x00004000 */
-#define ADC_LTR2_LT2_15 (0x0008000U << ADC_LTR2_LT2_Pos) /*!< 0x00008000 */
-#define ADC_LTR2_LT2_16 (0x0010000U << ADC_LTR2_LT2_Pos) /*!< 0x00010000 */
-#define ADC_LTR2_LT2_17 (0x0020000U << ADC_LTR2_LT2_Pos) /*!< 0x00020000 */
-#define ADC_LTR2_LT2_18 (0x0040000U << ADC_LTR2_LT2_Pos) /*!< 0x00040000 */
-#define ADC_LTR2_LT2_19 (0x0080000U << ADC_LTR2_LT2_Pos) /*!< 0x00080000 */
-#define ADC_LTR2_LT2_20 (0x0100000U << ADC_LTR2_LT2_Pos) /*!< 0x00100000 */
-#define ADC_LTR2_LT2_21 (0x0200000U << ADC_LTR2_LT2_Pos) /*!< 0x00200000 */
-#define ADC_LTR2_LT2_22 (0x0400000U << ADC_LTR2_LT2_Pos) /*!< 0x00400000 */
-#define ADC_LTR2_LT2_23 (0x0800000U << ADC_LTR2_LT2_Pos) /*!< 0x00800000 */
-#define ADC_LTR2_LT2_24 (0x1000000U << ADC_LTR2_LT2_Pos) /*!< 0x01000000 */
-#define ADC_LTR2_LT2_25 (0x2000000U << ADC_LTR2_LT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR2 register ********************/
-#define ADC_HTR2_HT2_Pos (0U)
-#define ADC_HTR2_HT2_Msk (0x3FFFFFFU << ADC_HTR2_HT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR2_HT2 ADC_HTR2_HT2_Msk /*!< ADC Analog watchdog 2 higher threshold */
-#define ADC_HTR2_HT2_0 (0x0000001U << ADC_HTR2_HT2_Pos) /*!< 0x00000001 */
-#define ADC_HTR2_HT2_1 (0x0000002U << ADC_HTR2_HT2_Pos) /*!< 0x00000002 */
-#define ADC_HTR2_HT2_2 (0x0000004U << ADC_HTR2_HT2_Pos) /*!< 0x00000004 */
-#define ADC_HTR2_HT2_3 (0x0000008U << ADC_HTR2_HT2_Pos) /*!< 0x00000008 */
-#define ADC_HTR2_HT2_4 (0x0000010U << ADC_HTR2_HT2_Pos) /*!< 0x00000010 */
-#define ADC_HTR2_HT2_5 (0x0000020U << ADC_HTR2_HT2_Pos) /*!< 0x00000020 */
-#define ADC_HTR2_HT2_6 (0x0000040U << ADC_HTR2_HT2_Pos) /*!< 0x00000040 */
-#define ADC_HTR2_HT2_7 (0x0000080U << ADC_HTR2_HT2_Pos) /*!< 0x00000080 */
-#define ADC_HTR2_HT2_8 (0x0000100U << ADC_HTR2_HT2_Pos) /*!< 0x00000100 */
-#define ADC_HTR2_HT2_9 (0x0000200U << ADC_HTR2_HT2_Pos) /*!< 0x00000200 */
-#define ADC_HTR2_HT2_10 (0x0000400U << ADC_HTR2_HT2_Pos) /*!< 0x00000400 */
-#define ADC_HTR2_HT2_11 (0x0000800U << ADC_HTR2_HT2_Pos) /*!< 0x00000800 */
-#define ADC_HTR2_HT2_12 (0x0001000U << ADC_HTR2_HT2_Pos) /*!< 0x00001000 */
-#define ADC_HTR2_HT2_13 (0x0002000U << ADC_HTR2_HT2_Pos) /*!< 0x00002000 */
-#define ADC_HTR2_HT2_14 (0x0004000U << ADC_HTR2_HT2_Pos) /*!< 0x00004000 */
-#define ADC_HTR2_HT2_15 (0x0008000U << ADC_HTR2_HT2_Pos) /*!< 0x00008000 */
-#define ADC_HTR2_HT2_16 (0x0010000U << ADC_HTR2_HT2_Pos) /*!< 0x00010000 */
-#define ADC_HTR2_HT2_17 (0x0020000U << ADC_HTR2_HT2_Pos) /*!< 0x00020000 */
-#define ADC_HTR2_HT2_18 (0x0040000U << ADC_HTR2_HT2_Pos) /*!< 0x00040000 */
-#define ADC_HTR2_HT2_19 (0x0080000U << ADC_HTR2_HT2_Pos) /*!< 0x00080000 */
-#define ADC_HTR2_HT2_20 (0x0100000U << ADC_HTR2_HT2_Pos) /*!< 0x00100000 */
-#define ADC_HTR2_HT2_21 (0x0200000U << ADC_HTR2_HT2_Pos) /*!< 0x00200000 */
-#define ADC_HTR2_HT2_22 (0x0400000U << ADC_HTR2_HT2_Pos) /*!< 0x00400000 */
-#define ADC_HTR2_HT2_23 (0x0800000U << ADC_HTR2_HT2_Pos) /*!< 0x00800000 */
-#define ADC_HTR2_HT2_24 (0x1000000U << ADC_HTR2_HT2_Pos) /*!< 0x01000000 */
-#define ADC_HTR2_HT2_25 (0x2000000U << ADC_HTR2_HT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR3 register ********************/
-#define ADC_LTR3_LT3_Pos (0U)
-#define ADC_LTR3_LT3_Msk (0x3FFFFFFU << ADC_LTR3_LT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR3_LT3 ADC_LTR3_LT3_Msk /*!< ADC Analog watchdog 3 lower threshold */
-#define ADC_LTR3_LT3_0 (0x0000001U << ADC_LTR3_LT3_Pos) /*!< 0x00000001 */
-#define ADC_LTR3_LT3_1 (0x0000002U << ADC_LTR3_LT3_Pos) /*!< 0x00000002 */
-#define ADC_LTR3_LT3_2 (0x0000004U << ADC_LTR3_LT3_Pos) /*!< 0x00000004 */
-#define ADC_LTR3_LT3_3 (0x0000008U << ADC_LTR3_LT3_Pos) /*!< 0x00000008 */
-#define ADC_LTR3_LT3_4 (0x0000010U << ADC_LTR3_LT3_Pos) /*!< 0x00000010 */
-#define ADC_LTR3_LT3_5 (0x0000020U << ADC_LTR3_LT3_Pos) /*!< 0x00000020 */
-#define ADC_LTR3_LT3_6 (0x0000040U << ADC_LTR3_LT3_Pos) /*!< 0x00000040 */
-#define ADC_LTR3_LT3_7 (0x0000080U << ADC_LTR3_LT3_Pos) /*!< 0x00000080 */
-#define ADC_LTR3_LT3_8 (0x0000100U << ADC_LTR3_LT3_Pos) /*!< 0x00000100 */
-#define ADC_LTR3_LT3_9 (0x0000200U << ADC_LTR3_LT3_Pos) /*!< 0x00000200 */
-#define ADC_LTR3_LT3_10 (0x0000400U << ADC_LTR3_LT3_Pos) /*!< 0x00000400 */
-#define ADC_LTR3_LT3_11 (0x0000800U << ADC_LTR3_LT3_Pos) /*!< 0x00000800 */
-#define ADC_LTR3_LT3_12 (0x0001000U << ADC_LTR3_LT3_Pos) /*!< 0x00001000 */
-#define ADC_LTR3_LT3_13 (0x0002000U << ADC_LTR3_LT3_Pos) /*!< 0x00002000 */
-#define ADC_LTR3_LT3_14 (0x0004000U << ADC_LTR3_LT3_Pos) /*!< 0x00004000 */
-#define ADC_LTR3_LT3_15 (0x0008000U << ADC_LTR3_LT3_Pos) /*!< 0x00008000 */
-#define ADC_LTR3_LT3_16 (0x0010000U << ADC_LTR3_LT3_Pos) /*!< 0x00010000 */
-#define ADC_LTR3_LT3_17 (0x0020000U << ADC_LTR3_LT3_Pos) /*!< 0x00020000 */
-#define ADC_LTR3_LT3_18 (0x0040000U << ADC_LTR3_LT3_Pos) /*!< 0x00040000 */
-#define ADC_LTR3_LT3_19 (0x0080000U << ADC_LTR3_LT3_Pos) /*!< 0x00080000 */
-#define ADC_LTR3_LT3_20 (0x0100000U << ADC_LTR3_LT3_Pos) /*!< 0x00100000 */
-#define ADC_LTR3_LT3_21 (0x0200000U << ADC_LTR3_LT3_Pos) /*!< 0x00200000 */
-#define ADC_LTR3_LT3_22 (0x0400000U << ADC_LTR3_LT3_Pos) /*!< 0x00400000 */
-#define ADC_LTR3_LT3_23 (0x0800000U << ADC_LTR3_LT3_Pos) /*!< 0x00800000 */
-#define ADC_LTR3_LT3_24 (0x1000000U << ADC_LTR3_LT3_Pos) /*!< 0x01000000 */
-#define ADC_LTR3_LT3_25 (0x2000000U << ADC_LTR3_LT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR3 register ********************/
-#define ADC_HTR3_HT3_Pos (0U)
-#define ADC_HTR3_HT3_Msk (0x3FFFFFFU << ADC_HTR3_HT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR3_HT3 ADC_HTR3_HT3_Msk /*!< ADC Analog watchdog 3 higher threshold */
-#define ADC_HTR3_HT3_0 (0x0000001U << ADC_HTR3_HT3_Pos) /*!< 0x00000001 */
-#define ADC_HTR3_HT3_1 (0x0000002U << ADC_HTR3_HT3_Pos) /*!< 0x00000002 */
-#define ADC_HTR3_HT3_2 (0x0000004U << ADC_HTR3_HT3_Pos) /*!< 0x00000004 */
-#define ADC_HTR3_HT3_3 (0x0000008U << ADC_HTR3_HT3_Pos) /*!< 0x00000008 */
-#define ADC_HTR3_HT3_4 (0x0000010U << ADC_HTR3_HT3_Pos) /*!< 0x00000010 */
-#define ADC_HTR3_HT3_5 (0x0000020U << ADC_HTR3_HT3_Pos) /*!< 0x00000020 */
-#define ADC_HTR3_HT3_6 (0x0000040U << ADC_HTR3_HT3_Pos) /*!< 0x00000040 */
-#define ADC_HTR3_HT3_7 (0x0000080U << ADC_HTR3_HT3_Pos) /*!< 0x00000080 */
-#define ADC_HTR3_HT3_8 (0x0000100U << ADC_HTR3_HT3_Pos) /*!< 0x00000100 */
-#define ADC_HTR3_HT3_9 (0x0000200U << ADC_HTR3_HT3_Pos) /*!< 0x00000200 */
-#define ADC_HTR3_HT3_10 (0x0000400U << ADC_HTR3_HT3_Pos) /*!< 0x00000400 */
-#define ADC_HTR3_HT3_11 (0x0000800U << ADC_HTR3_HT3_Pos) /*!< 0x00000800 */
-#define ADC_HTR3_HT3_12 (0x0001000U << ADC_HTR3_HT3_Pos) /*!< 0x00001000 */
-#define ADC_HTR3_HT3_13 (0x0002000U << ADC_HTR3_HT3_Pos) /*!< 0x00002000 */
-#define ADC_HTR3_HT3_14 (0x0004000U << ADC_HTR3_HT3_Pos) /*!< 0x00004000 */
-#define ADC_HTR3_HT3_15 (0x0008000U << ADC_HTR3_HT3_Pos) /*!< 0x00008000 */
-#define ADC_HTR3_HT3_16 (0x0010000U << ADC_HTR3_HT3_Pos) /*!< 0x00010000 */
-#define ADC_HTR3_HT3_17 (0x0020000U << ADC_HTR3_HT3_Pos) /*!< 0x00020000 */
-#define ADC_HTR3_HT3_18 (0x0040000U << ADC_HTR3_HT3_Pos) /*!< 0x00040000 */
-#define ADC_HTR3_HT3_19 (0x0080000U << ADC_HTR3_HT3_Pos) /*!< 0x00080000 */
-#define ADC_HTR3_HT3_20 (0x0100000U << ADC_HTR3_HT3_Pos) /*!< 0x00100000 */
-#define ADC_HTR3_HT3_21 (0x0200000U << ADC_HTR3_HT3_Pos) /*!< 0x00200000 */
-#define ADC_HTR3_HT3_22 (0x0400000U << ADC_HTR3_HT3_Pos) /*!< 0x00400000 */
-#define ADC_HTR3_HT3_23 (0x0800000U << ADC_HTR3_HT3_Pos) /*!< 0x00800000 */
-#define ADC_HTR3_HT3_24 (0x1000000U << ADC_HTR3_HT3_Pos) /*!< 0x01000000 */
-#define ADC_HTR3_HT3_25 (0x2000000U << ADC_HTR3_HT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_SQR1 register ********************/
-#define ADC_SQR1_L_Pos (0U)
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
-
-#define ADC_SQR1_SQ1_Pos (6U)
-#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
-#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
-#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
-#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR1_SQ2_Pos (12U)
-#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
-#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
-#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
-#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR1_SQ3_Pos (18U)
-#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
-#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
-#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
-#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR1_SQ4_Pos (24U)
-#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
-#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
-#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
-#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
-#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
-#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
-#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR2 register ********************/
-#define ADC_SQR2_SQ5_Pos (0U)
-#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
-#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ6_Pos (6U)
-#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
-#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
-#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
-#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR2_SQ7_Pos (12U)
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR2_SQ8_Pos (18U)
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR2_SQ9_Pos (24U)
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR3 register ********************/
-#define ADC_SQR3_SQ10_Pos (0U)
-#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
-#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ11_Pos (6U)
-#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
-#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
-#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
-#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR3_SQ12_Pos (12U)
-#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
-#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
-#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
-#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR3_SQ13_Pos (18U)
-#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
-#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
-#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
-#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR3_SQ14_Pos (24U)
-#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
-#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
-#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
-#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR4 register ********************/
-#define ADC_SQR4_SQ15_Pos (0U)
-#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
-#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
-#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
-#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
-#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
-#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
-#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ16_Pos (6U)
-#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
-#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
-#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
-#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
-#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
-#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
-#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
-#define ADC_DR_RDATA_0 (0x00000001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
-#define ADC_DR_RDATA_1 (0x00000002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
-#define ADC_DR_RDATA_2 (0x00000004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
-#define ADC_DR_RDATA_3 (0x00000008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
-#define ADC_DR_RDATA_4 (0x00000010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
-#define ADC_DR_RDATA_5 (0x00000020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
-#define ADC_DR_RDATA_6 (0x00000040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
-#define ADC_DR_RDATA_7 (0x00000080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
-#define ADC_DR_RDATA_8 (0x00000100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
-#define ADC_DR_RDATA_9 (0x00000200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
-#define ADC_DR_RDATA_10 (0x00000400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
-#define ADC_DR_RDATA_11 (0x00000800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
-#define ADC_DR_RDATA_12 (0x00001000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
-#define ADC_DR_RDATA_13 (0x00002000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
-#define ADC_DR_RDATA_14 (0x00004000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
-#define ADC_DR_RDATA_15 (0x00008000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
-#define ADC_DR_RDATA_16 (0x00010000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
-#define ADC_DR_RDATA_17 (0x00020000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
-#define ADC_DR_RDATA_18 (0x00040000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
-#define ADC_DR_RDATA_19 (0x00080000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
-#define ADC_DR_RDATA_20 (0x00100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
-#define ADC_DR_RDATA_21 (0x00200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
-#define ADC_DR_RDATA_22 (0x00400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
-#define ADC_DR_RDATA_23 (0x00800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
-#define ADC_DR_RDATA_24 (0x01000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
-#define ADC_DR_RDATA_25 (0x02000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
-#define ADC_DR_RDATA_26 (0x04000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
-#define ADC_DR_RDATA_27 (0x08000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
-#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
-#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
-#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
-#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JSQR register ********************/
-#define ADC_JSQR_JL_Pos (0U)
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
-
-#define ADC_JSQR_JEXTSEL_Pos (2U)
-#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
-#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
-#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
-#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
-
-#define ADC_JSQR_JEXTEN_Pos (7U)
-#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
-#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
-#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
-
-#define ADC_JSQR_JSQ1_Pos (9U)
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
-
-#define ADC_JSQR_JSQ2_Pos (15U)
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JSQ3_Pos (21U)
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
-
-#define ADC_JSQR_JSQ4_Pos (27U)
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_OFR1 register ********************/
-#define ADC_OFR1_OFFSET1_Pos (0U)
-#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
-#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
-#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
-#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
-#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
-#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
-#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
-#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
-#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
-#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
-#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
-#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
-#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
-#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
-#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
-#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
-#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
-#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
-#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
-#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
-#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
-#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
-#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
-#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
-#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
-#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
-#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR1_OFFSET1_CH_Pos (26U)
-#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
-#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR1_SSATE_Pos (31U)
-#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR2 register ********************/
-#define ADC_OFR2_OFFSET2_Pos (0U)
-#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
-#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
-#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
-#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
-#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
-#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
-#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
-#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
-#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
-#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
-#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
-#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
-#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
-#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
-#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
-#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
-#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
-#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
-#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
-#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
-#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
-#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
-#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
-#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
-#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
-#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
-#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR2_OFFSET2_CH_Pos (26U)
-#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
-#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR2_SSATE_Pos (31U)
-#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR3 register ********************/
-#define ADC_OFR3_OFFSET3_Pos (0U)
-#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
-#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
-#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
-#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
-#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
-#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
-#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
-#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
-#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
-#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
-#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
-#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
-#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
-#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
-#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
-#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
-#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
-#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
-#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
-#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
-#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
-#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
-#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
-#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
-#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
-#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
-#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR3_OFFSET3_CH_Pos (26U)
-#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
-#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR3_SSATE_Pos (31U)
-#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR4 register ********************/
-#define ADC_OFR4_OFFSET4_Pos (0U)
-#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
-#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
-#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
-#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
-#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
-#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
-#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
-#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
-#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
-#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
-#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
-#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
-#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
-#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
-#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
-#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
-#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
-#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
-#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
-#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
-#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
-#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
-#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
-#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
-#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
-#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
-#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR4_OFFSET4_CH_Pos (26U)
-#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
-#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR4_SSATE_Pos (31U)
-#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_JDR1 register ********************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR1_JDATA_0 (0x00000001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR1_JDATA_1 (0x00000002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR1_JDATA_2 (0x00000004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR1_JDATA_3 (0x00000008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR1_JDATA_4 (0x00000010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR1_JDATA_5 (0x00000020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR1_JDATA_6 (0x00000040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR1_JDATA_7 (0x00000080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR1_JDATA_8 (0x00000100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR1_JDATA_9 (0x00000200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR1_JDATA_10 (0x00000400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR1_JDATA_11 (0x00000800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR1_JDATA_12 (0x00001000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR1_JDATA_13 (0x00002000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR1_JDATA_14 (0x00004000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR1_JDATA_15 (0x00008000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR1_JDATA_16 (0x00010000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR1_JDATA_17 (0x00020000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR1_JDATA_18 (0x00040000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR1_JDATA_19 (0x00080000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR1_JDATA_20 (0x00100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR1_JDATA_21 (0x00200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR1_JDATA_22 (0x00400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR1_JDATA_23 (0x00800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR1_JDATA_24 (0x01000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR1_JDATA_25 (0x02000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR1_JDATA_26 (0x04000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR1_JDATA_27 (0x08000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR2 register ********************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR2_JDATA_0 (0x00000001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR2_JDATA_1 (0x00000002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR2_JDATA_2 (0x00000004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR2_JDATA_3 (0x00000008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR2_JDATA_4 (0x00000010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR2_JDATA_5 (0x00000020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR2_JDATA_6 (0x00000040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR2_JDATA_7 (0x00000080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR2_JDATA_8 (0x00000100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR2_JDATA_9 (0x00000200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR2_JDATA_10 (0x00000400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR2_JDATA_11 (0x00000800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR2_JDATA_12 (0x00001000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR2_JDATA_13 (0x00002000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR2_JDATA_14 (0x00004000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR2_JDATA_15 (0x00008000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR2_JDATA_16 (0x00010000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR2_JDATA_17 (0x00020000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR2_JDATA_18 (0x00040000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR2_JDATA_19 (0x00080000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR2_JDATA_20 (0x00100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR2_JDATA_21 (0x00200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR2_JDATA_22 (0x00400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR2_JDATA_23 (0x00800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR2_JDATA_24 (0x01000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR2_JDATA_25 (0x02000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR2_JDATA_26 (0x04000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR2_JDATA_27 (0x08000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR3 register ********************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR3_JDATA_0 (0x00000001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR3_JDATA_1 (0x00000002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR3_JDATA_2 (0x00000004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR3_JDATA_3 (0x00000008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR3_JDATA_4 (0x00000010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR3_JDATA_5 (0x00000020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR3_JDATA_6 (0x00000040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR3_JDATA_7 (0x00000080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR3_JDATA_8 (0x00000100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR3_JDATA_9 (0x00000200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR3_JDATA_10 (0x00000400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR3_JDATA_11 (0x00000800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR3_JDATA_12 (0x00001000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR3_JDATA_13 (0x00002000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR3_JDATA_14 (0x00004000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR3_JDATA_15 (0x00008000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR3_JDATA_16 (0x00010000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR3_JDATA_17 (0x00020000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR3_JDATA_18 (0x00040000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR3_JDATA_19 (0x00080000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR3_JDATA_20 (0x00100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR3_JDATA_21 (0x00200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR3_JDATA_22 (0x00400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR3_JDATA_23 (0x00800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR3_JDATA_24 (0x01000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR3_JDATA_25 (0x02000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR3_JDATA_26 (0x04000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR3_JDATA_27 (0x08000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR4 register ********************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR4_JDATA_0 (0x00000001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR4_JDATA_1 (0x00000002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR4_JDATA_2 (0x00000004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR4_JDATA_3 (0x00000008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR4_JDATA_4 (0x00000010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR4_JDATA_5 (0x00000020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR4_JDATA_6 (0x00000040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR4_JDATA_7 (0x00000080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR4_JDATA_8 (0x00000100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR4_JDATA_9 (0x00000200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR4_JDATA_10 (0x00000400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR4_JDATA_11 (0x00000800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR4_JDATA_12 (0x00001000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR4_JDATA_13 (0x00002000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR4_JDATA_14 (0x00004000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR4_JDATA_15 (0x00008000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR4_JDATA_16 (0x00010000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR4_JDATA_17 (0x00020000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR4_JDATA_18 (0x00040000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR4_JDATA_19 (0x00080000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR4_JDATA_20 (0x00100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR4_JDATA_21 (0x00200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR4_JDATA_22 (0x00400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR4_JDATA_23 (0x00800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR4_JDATA_24 (0x01000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR4_JDATA_25 (0x02000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR4_JDATA_26 (0x04000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR4_JDATA_27 (0x08000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_AWD2CR register ********************/
-#define ADC_AWD2CR_AWD2CH_Pos (0U)
-#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_AWD3CR register ********************/
-#define ADC_AWD3CR_AWD3CH_Pos (0U)
-#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_DIFSEL register ********************/
-#define ADC_DIFSEL_DIFSEL_Pos (0U)
-#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
-#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
-#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
-#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
-#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
-#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
-#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
-#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
-#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
-#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
-#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
-#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
-#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
-#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
-#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
-#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
-#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
-#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
-#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
-#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
-#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT_S_Pos (0U)
-#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
-#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT_CALFACT_D_Pos (16U)
-#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
-#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
-
-/******************** Bit definition for ADC_CALFACT2 register ********************/
-#define ADC_CALFACT2_LINCALFACT_Pos (0U)
-#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
-#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
-#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
-#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
-#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
-#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
-#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
-#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
-#define ADC_CALFACT2_LINCALFACT_27 (0x08000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
-#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
-#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
-
-/************************* ADC Common registers *****************************/
-/******************** Bit definition for ADC_CSR register ********************/
-#define ADC123_CSR_ADRDY_MST_Pos (0U)
-#define ADC123_CSR_ADRDY_MST_Msk (0x1U << ADC123_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CSR_ADRDY_MST ADC123_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
-#define ADC123_CSR_EOSMP_MST_Pos (1U)
-#define ADC123_CSR_EOSMP_MST_Msk (0x1U << ADC123_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CSR_EOSMP_MST ADC123_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
-#define ADC123_CSR_EOC_MST_Pos (2U)
-#define ADC123_CSR_EOC_MST_Msk (0x1U << ADC123_CSR_EOC_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CSR_EOC_MST ADC123_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
-#define ADC123_CSR_EOS_MST_Pos (3U)
-#define ADC123_CSR_EOS_MST_Msk (0x1U << ADC123_CSR_EOS_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CSR_EOS_MST ADC123_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
-#define ADC123_CSR_OVR_MST_Pos (4U)
-#define ADC123_CSR_OVR_MST_Msk (0x1U << ADC123_CSR_OVR_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CSR_OVR_MST ADC123_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
-#define ADC123_CSR_JEOC_MST_Pos (5U)
-#define ADC123_CSR_JEOC_MST_Msk (0x1U << ADC123_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CSR_JEOC_MST ADC123_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
-#define ADC123_CSR_JEOS_MST_Pos (6U)
-#define ADC123_CSR_JEOS_MST_Msk (0x1U << ADC123_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CSR_JEOS_MST ADC123_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
-#define ADC123_CSR_AWD1_MST_Pos (7U)
-#define ADC123_CSR_AWD1_MST_Msk (0x1U << ADC123_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CSR_AWD1_MST ADC123_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC123_CSR_AWD2_MST_Pos (8U)
-#define ADC123_CSR_AWD2_MST_Msk (0x1U << ADC123_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CSR_AWD2_MST ADC123_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC123_CSR_AWD3_MST_Pos (9U)
-#define ADC123_CSR_AWD3_MST_Msk (0x1U << ADC123_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CSR_AWD3_MST ADC123_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC123_CSR_JQOVF_MST_Pos (10U)
-#define ADC123_CSR_JQOVF_MST_Msk (0x1U << ADC123_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CSR_JQOVF_MST ADC123_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
-#define ADC123_CSR_ADRDY_SLV_Pos (16U)
-#define ADC123_CSR_ADRDY_SLV_Msk (0x1U << ADC123_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CSR_ADRDY_SLV ADC123_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
-#define ADC123_CSR_EOSMP_SLV_Pos (17U)
-#define ADC123_CSR_EOSMP_SLV_Msk (0x1U << ADC123_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CSR_EOSMP_SLV ADC123_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
-#define ADC123_CSR_EOC_SLV_Pos (18U)
-#define ADC123_CSR_EOC_SLV_Msk (0x1U << ADC123_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CSR_EOC_SLV ADC123_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
-#define ADC123_CSR_EOS_SLV_Pos (19U)
-#define ADC123_CSR_EOS_SLV_Msk (0x1U << ADC123_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CSR_EOS_SLV ADC123_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
-#define ADC123_CSR_OVR_SLV_Pos (20U)
-#define ADC123_CSR_OVR_SLV_Msk (0x1U << ADC123_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CSR_OVR_SLV ADC123_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
-#define ADC123_CSR_JEOC_SLV_Pos (21U)
-#define ADC123_CSR_JEOC_SLV_Msk (0x1U << ADC123_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CSR_JEOC_SLV ADC123_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
-#define ADC123_CSR_JEOS_SLV_Pos (22U)
-#define ADC123_CSR_JEOS_SLV_Msk (0x1U << ADC123_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CSR_JEOS_SLV ADC123_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
-#define ADC123_CSR_AWD1_SLV_Pos (23U)
-#define ADC123_CSR_AWD1_SLV_Msk (0x1U << ADC123_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CSR_AWD1_SLV ADC123_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC123_CSR_AWD2_SLV_Pos (24U)
-#define ADC123_CSR_AWD2_SLV_Msk (0x1U << ADC123_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CSR_AWD2_SLV ADC123_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC123_CSR_AWD3_SLV_Pos (25U)
-#define ADC123_CSR_AWD3_SLV_Msk (0x1U << ADC123_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CSR_AWD3_SLV ADC123_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC123_CSR_JQOVF_SLV_Pos (26U)
-#define ADC123_CSR_JQOVF_SLV_Msk (0x1U << ADC123_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CSR_JQOVF_SLV ADC123_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
-
-/******************** Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_DUAL_Pos (0U)
-#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
-#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
-#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
-#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
-#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
-#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
-#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
-
-#define ADC_CCR_DELAY_Pos (8U)
-#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
-#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
-#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
-#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
-#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
-#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
-
-
-#define ADC_CCR_DAMDF_Pos (14U)
-#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
-#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
-#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
-#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
-
-#define ADC_CCR_CKMODE_Pos (16U)
-#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
-#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
-#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
-#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
-
-#define ADC_CCR_PRESC_Pos (18U)
-#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
-#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
-#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos (22U)
-#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
-#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
-#define ADC_CCR_TSEN_Pos (23U)
-#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
-#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos (24U)
-#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
-#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
-
-/******************** Bit definition for ADC_CDR register ********************/
-#define ADC123_CDR_RDATA_MST_Pos (0U)
-#define ADC123_CDR_RDATA_MST_Msk (0xFFFFU << ADC123_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
-#define ADC123_CDR_RDATA_MST ADC123_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_MST_0 (0x0001U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CDR_RDATA_MST_1 (0x0002U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CDR_RDATA_MST_2 (0x0004U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CDR_RDATA_MST_3 (0x0008U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CDR_RDATA_MST_4 (0x0010U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CDR_RDATA_MST_5 (0x0020U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CDR_RDATA_MST_6 (0x0040U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CDR_RDATA_MST_7 (0x0080U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CDR_RDATA_MST_8 (0x0100U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CDR_RDATA_MST_9 (0x0200U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CDR_RDATA_MST_10 (0x0400U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CDR_RDATA_MST_11 (0x0800U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
-#define ADC123_CDR_RDATA_MST_12 (0x1000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
-#define ADC123_CDR_RDATA_MST_13 (0x2000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
-#define ADC123_CDR_RDATA_MST_14 (0x4000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
-#define ADC123_CDR_RDATA_MST_15 (0x8000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
-
-#define ADC123_CDR_RDATA_SLV_Pos (16U)
-#define ADC123_CDR_RDATA_SLV_Msk (0xFFFFU << ADC123_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
-#define ADC123_CDR_RDATA_SLV ADC123_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_SLV_0 (0x0001U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CDR_RDATA_SLV_1 (0x0002U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CDR_RDATA_SLV_2 (0x0004U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CDR_RDATA_SLV_3 (0x0008U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CDR_RDATA_SLV_4 (0x0010U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CDR_RDATA_SLV_5 (0x0020U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CDR_RDATA_SLV_6 (0x0040U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CDR_RDATA_SLV_7 (0x0080U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CDR_RDATA_SLV_8 (0x0100U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CDR_RDATA_SLV_9 (0x0200U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CDR_RDATA_SLV_10 (0x0400U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CDR_RDATA_SLV_11 (0x0800U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
-#define ADC123_CDR_RDATA_SLV_12 (0x1000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
-#define ADC123_CDR_RDATA_SLV_13 (0x2000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
-#define ADC123_CDR_RDATA_SLV_14 (0x4000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
-#define ADC123_CDR_RDATA_SLV_15 (0x8000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_CDR2 register ********************/
-#define ADC123_CDR2_RDATA_ALT_Pos (0U)
-#define ADC123_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
-#define ADC123_CDR2_RDATA_ALT ADC123_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
-#define ADC123_CDR2_RDATA_ALT_0 (0x00000001U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
-#define ADC123_CDR2_RDATA_ALT_1 (0x00000002U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
-#define ADC123_CDR2_RDATA_ALT_2 (0x00000004U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
-#define ADC123_CDR2_RDATA_ALT_3 (0x00000008U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
-#define ADC123_CDR2_RDATA_ALT_4 (0x00000010U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
-#define ADC123_CDR2_RDATA_ALT_5 (0x00000020U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
-#define ADC123_CDR2_RDATA_ALT_6 (0x00000040U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
-#define ADC123_CDR2_RDATA_ALT_7 (0x00000080U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
-#define ADC123_CDR2_RDATA_ALT_8 (0x00000100U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
-#define ADC123_CDR2_RDATA_ALT_9 (0x00000200U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
-#define ADC123_CDR2_RDATA_ALT_10 (0x00000400U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
-#define ADC123_CDR2_RDATA_ALT_11 (0x00000800U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
-#define ADC123_CDR2_RDATA_ALT_12 (0x00001000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
-#define ADC123_CDR2_RDATA_ALT_13 (0x00002000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
-#define ADC123_CDR2_RDATA_ALT_14 (0x00004000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
-#define ADC123_CDR2_RDATA_ALT_15 (0x00008000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
-#define ADC123_CDR2_RDATA_ALT_16 (0x00010000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
-#define ADC123_CDR2_RDATA_ALT_17 (0x00020000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
-#define ADC123_CDR2_RDATA_ALT_18 (0x00040000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
-#define ADC123_CDR2_RDATA_ALT_19 (0x00080000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
-#define ADC123_CDR2_RDATA_ALT_20 (0x00100000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
-#define ADC123_CDR2_RDATA_ALT_21 (0x00200000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
-#define ADC123_CDR2_RDATA_ALT_22 (0x00400000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
-#define ADC123_CDR2_RDATA_ALT_23 (0x00800000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
-#define ADC123_CDR2_RDATA_ALT_24 (0x01000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
-#define ADC123_CDR2_RDATA_ALT_25 (0x02000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
-#define ADC123_CDR2_RDATA_ALT_26 (0x04000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
-#define ADC123_CDR2_RDATA_ALT_27 (0x08000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
-#define ADC123_CDR2_RDATA_ALT_28 (0x10000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
-#define ADC123_CDR2_RDATA_ALT_29 (0x20000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
-#define ADC123_CDR2_RDATA_ALT_30 (0x40000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
-#define ADC123_CDR2_RDATA_ALT_31 (0x80000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
-
-/******************************************************************************/
-/* */
-/* VREFBUF */
-/* */
-/******************************************************************************/
-/******************* Bit definition for VREFBUF_CSR register ****************/
-#define VREFBUF_CSR_ENVR_Pos (0U)
-#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/
-#define DAC_CR_CEN1_Pos (14U)
-#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
-#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
-
-#define DAC_CR_EN2_Pos (16U)
-#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
-#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
-#define DAC_CR_CEN2_Pos (30U)
-#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
-#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1MB */
-
-#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32H743xx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
deleted file mode 100644
index 2f9e15f..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
+++ /dev/null
@@ -1,25810 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h750xx.h
- * @author MCD Application Team
- * @brief CMSIS STM32H750xx Device Peripheral Access Layer Header File.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS_Device
- * @{
- */
-
-/** @addtogroup stm32h750xx
- * @{
- */
-
-#ifndef __STM32H750xx_H
-#define __STM32H750xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32H7XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
- FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
- FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
- FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
- FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
- LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
- CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
- I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
- I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
- SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
- OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
- OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
- OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
- OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
- DMAMUX1_OVR_IRQn = 102, /*!
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
- __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
- __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
- uint32_t RESERVED1; /*!< Reserved, 0x028 */
- uint32_t RESERVED2; /*!< Reserved, 0x02C */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
- __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- uint32_t RESERVED3; /*!< Reserved, 0x044 */
- uint32_t RESERVED4; /*!< Reserved, 0x048 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
- uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
- __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
- __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
- __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
- __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
- uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
- uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
- __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
- __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
- uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
- uint32_t RESERVED9; /*!< Reserved, 0x0AC */
- __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
- __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
- __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
- __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
- __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
- __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
- __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
-} ADC_TypeDef;
-
-
-typedef struct
-{
-__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
-uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
-__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
-__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
-__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
-} ADC_Common_TypeDef;
-
-/**
- * @brief VREFBUF
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
- __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
- __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
- __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
- __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
- __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
- __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
- __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
- __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
- __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
- __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
- __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
- __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
- __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
- __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
- __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
- __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
- __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
- __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
- __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
- __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
- __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
- __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
- __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
- __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
- __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
- __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
- __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
- __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
- __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
- __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
- __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
- __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
- __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
- __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
- __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
- __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
- __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
- __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
- __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
- __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
- __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
- __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
- __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
- __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
- __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
- __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
- __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
- __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
- __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
- __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
- __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
- __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
-} FDCAN_GlobalTypeDef;
-
-/**
- * @brief TTFD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
- __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
- __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
- __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
- __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
- __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
- __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
- __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
- __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
- __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
- __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
- __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
- __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
- __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
- __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
- __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
- __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
- __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
- __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
-} TTCAN_TypeDef;
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
- __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
- __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
- __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
- __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
- __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
-} FDCAN_ClockCalibrationUnit_TypeDef;
-
-
-/**
- * @brief Consumer Electronics Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
- __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
- __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
- __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
- __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
- __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
- __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
- __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
- __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
- __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
- uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
- __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} BDMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} BDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< DMA Channel Status Register */
- __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
- __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
- * @brief MDMA Controller
- */
-typedef struct
-{
- __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
-}MDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
- __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
- __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
- __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
- __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
- __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
- __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
- __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
- __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
- __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
- __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
- __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
- __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
-}MDMA_Channel_TypeDef;
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACECR;
- __IO uint32_t MACPFR;
- __IO uint32_t MACWTR;
- __IO uint32_t MACHT0R;
- __IO uint32_t MACHT1R;
- uint32_t RESERVED1[14];
- __IO uint32_t MACVTR;
- uint32_t RESERVED2;
- __IO uint32_t MACVHTR;
- uint32_t RESERVED3;
- __IO uint32_t MACVIR;
- __IO uint32_t MACIVIR;
- uint32_t RESERVED4[2];
- __IO uint32_t MACTFCR;
- uint32_t RESERVED5[7];
- __IO uint32_t MACRFCR;
- uint32_t RESERVED6[7];
- __IO uint32_t MACISR;
- __IO uint32_t MACIER;
- __IO uint32_t MACRXTXSR;
- uint32_t RESERVED7;
- __IO uint32_t MACPCSR;
- __IO uint32_t MACRWKPFR;
- uint32_t RESERVED8[2];
- __IO uint32_t MACLCSR;
- __IO uint32_t MACLTCR;
- __IO uint32_t MACLETR;
- __IO uint32_t MAC1USTCR;
- uint32_t RESERVED9[12];
- __IO uint32_t MACVR;
- __IO uint32_t MACDR;
- uint32_t RESERVED10;
- __IO uint32_t MACHWF0R;
- __IO uint32_t MACHWF1R;
- __IO uint32_t MACHWF2R;
- uint32_t RESERVED11[54];
- __IO uint32_t MACMDIOAR;
- __IO uint32_t MACMDIODR;
- uint32_t RESERVED12[2];
- __IO uint32_t MACARPAR;
- uint32_t RESERVED13[59];
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR;
- uint32_t RESERVED14[248];
- __IO uint32_t MMCCR;
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR;
- uint32_t RESERVED15[14];
- __IO uint32_t MMCTSCGPR;
- __IO uint32_t MMCTMCGPR;
- int32_t RESERVED16[5];
- __IO uint32_t MMCTPCGR;
- uint32_t RESERVED17[10];
- __IO uint32_t MMCRCRCEPR;
- __IO uint32_t MMCRAEPR;
- uint32_t RESERVED18[10];
- __IO uint32_t MMCRUPGR;
- uint32_t RESERVED19[9];
- __IO uint32_t MMCTLPIMSTR;
- __IO uint32_t MMCTLPITCR;
- __IO uint32_t MMCRLPIMSTR;
- __IO uint32_t MMCRLPITCR;
- uint32_t RESERVED20[65];
- __IO uint32_t MACL3L4C0R;
- __IO uint32_t MACL4A0R;
- uint32_t RESERVED21[2];
- __IO uint32_t MACL3A0R0R;
- __IO uint32_t MACL3A1R0R;
- __IO uint32_t MACL3A2R0R;
- __IO uint32_t MACL3A3R0R;
- uint32_t RESERVED22[4];
- __IO uint32_t MACL3L4C1R;
- __IO uint32_t MACL4A1R;
- uint32_t RESERVED23[2];
- __IO uint32_t MACL3A0R1R;
- __IO uint32_t MACL3A1R1R;
- __IO uint32_t MACL3A2R1R;
- __IO uint32_t MACL3A3R1R;
- uint32_t RESERVED24[108];
- __IO uint32_t MACTSCR;
- __IO uint32_t MACSSIR;
- __IO uint32_t MACSTSR;
- __IO uint32_t MACSTNR;
- __IO uint32_t MACSTSUR;
- __IO uint32_t MACSTNUR;
- __IO uint32_t MACTSAR;
- uint32_t RESERVED25;
- __IO uint32_t MACTSSR;
- uint32_t RESERVED26[3];
- __IO uint32_t MACTTSSNR;
- __IO uint32_t MACTTSSSR;
- uint32_t RESERVED27[2];
- __IO uint32_t MACACR;
- uint32_t RESERVED28;
- __IO uint32_t MACATSNR;
- __IO uint32_t MACATSSR;
- __IO uint32_t MACTSIACR;
- __IO uint32_t MACTSEACR;
- __IO uint32_t MACTSICNR;
- __IO uint32_t MACTSECNR;
- uint32_t RESERVED29[4];
- __IO uint32_t MACPPSCR;
- uint32_t RESERVED30[3];
- __IO uint32_t MACPPSTTSR;
- __IO uint32_t MACPPSTTNR;
- __IO uint32_t MACPPSIR;
- __IO uint32_t MACPPSWR;
- uint32_t RESERVED31[12];
- __IO uint32_t MACPOCR;
- __IO uint32_t MACSPI0R;
- __IO uint32_t MACSPI1R;
- __IO uint32_t MACSPI2R;
- __IO uint32_t MACLMIR;
- uint32_t RESERVED32[11];
- __IO uint32_t MTLOMR;
- uint32_t RESERVED33[7];
- __IO uint32_t MTLISR;
- uint32_t RESERVED34[55];
- __IO uint32_t MTLTQOMR;
- __IO uint32_t MTLTQUR;
- __IO uint32_t MTLTQDR;
- uint32_t RESERVED35[8];
- __IO uint32_t MTLQICSR;
- __IO uint32_t MTLRQOMR;
- __IO uint32_t MTLRQMPOCR;
- __IO uint32_t MTLRQDR;
- uint32_t RESERVED36[177];
- __IO uint32_t DMAMR;
- __IO uint32_t DMASBMR;
- __IO uint32_t DMAISR;
- __IO uint32_t DMADSR;
- uint32_t RESERVED37[60];
- __IO uint32_t DMACCR;
- __IO uint32_t DMACTCR;
- __IO uint32_t DMACRCR;
- uint32_t RESERVED38[2];
- __IO uint32_t DMACTDLAR;
- uint32_t RESERVED39;
- __IO uint32_t DMACRDLAR;
- __IO uint32_t DMACTDTPR;
- uint32_t RESERVED40;
- __IO uint32_t DMACRDTPR;
- __IO uint32_t DMACTDRLR;
- __IO uint32_t DMACRDRLR;
- __IO uint32_t DMACIER;
- __IO uint32_t DMACRIWTR;
-__IO uint32_t DMACSFCSR;
- uint32_t RESERVED41;
- __IO uint32_t DMACCATDR;
- uint32_t RESERVED42;
- __IO uint32_t DMACCARDR;
- uint32_t RESERVED43;
- __IO uint32_t DMACCATBR;
- uint32_t RESERVED44;
- __IO uint32_t DMACCARBR;
- __IO uint32_t DMACSR;
-uint32_t RESERVED45[2];
-__IO uint32_t DMACMFCR;
-}ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
-__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
-__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
-__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
-__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, Address offset: 0x0C */
-__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x10 */
-__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x14 */
-uint32_t RESERVED1; /*!< Reserved, 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
-__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
-__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
-__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, Address offset: 0x2C */
-__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x30 */
-__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x34 */
-uint32_t RESERVED3; /*!< Reserved, 0x38 */
-uint32_t RESERVED4; /*!< Reserved, 0x3C */
-__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
-__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
-__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
-__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, Address offset: 0x4C */
-__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x50 */
-__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x54 */
-}EXTI_TypeDef;
-
-typedef struct
-{
-__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
-__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
-__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
-uint32_t RESERVED1; /*!< Reserved, 0x0C */
-__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
-__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
-__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
-__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
-__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
-}EXTI_Core_TypeDef;
-
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
- __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
- __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
- __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
- __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
- __IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */
- __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
- __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
- __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
- __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
- __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */
- __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
- __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
- __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
- __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
- __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
- __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
- __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
- __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
- __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
- uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
- __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
- uint32_t RESERVED2; /*!< Reserved, 0x108 */
- __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
- __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
- __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
- uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
- __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
- __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
- __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
- __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
- __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
- __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
- uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
- __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
- __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
- __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
- __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
- __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5 and 6
- */
-
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief Operational Amplifier (OPAMP)
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
- __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
- __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
- __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
- __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
- __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
- __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
- uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
- __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
- uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
- __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
- __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
- __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
- __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
- __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
- __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
- __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
- __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
- __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
- __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
- __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
- __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
- __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
- __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
- __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
- __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
- __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
- __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
-
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
- * @brief JPEG Codec
- */
-typedef struct
-{
- __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
- __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
- __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
- __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
- __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
- __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
- __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
- __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
- uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
- __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
- __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
- __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
- uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
- __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
- __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
- uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
- __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
- __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
- __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
- __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
- __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
- __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
- __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
- __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
- uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
- __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
- __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
- __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
- __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
- __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
- __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
- __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
- __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
- __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
- __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
- __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
- __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
- __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
- __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
- __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
- __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
- __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
- __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
- __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
- __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
- __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
- __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
- __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
- __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
- __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
- __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
- __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
- __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
- __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
- __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
- __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA4 */
- __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
- uint32_t RESERVED8[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
- __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
- __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
- __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
- __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
- __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
- __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
- uint32_t RESERVED9; /*!< Reserved, Address offset: 0xF8 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
- __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
- __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
- __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
- __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
- __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
- uint32_t RESERVED10[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
-
-} RCC_TypeDef;
-
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- uint32_t reserved; /*!< Reserved */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAMPCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
- __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
- __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
- __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
- __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
- __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
- __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
- __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
- __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
- __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
- __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
- __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
- __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
- __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
- uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
- __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
- __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SPDIF-RX Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-
-
-/**
- * @brief Secure digital input/output Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
- __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
- uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
- __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
- __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
- __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
- __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
- uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
- uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
- __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
-} SDMMC_TypeDef;
-
-
-/**
- * @brief Delay Block DLYB
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
-} DLYB_TypeDef;
-
-/**
- * @brief HW Semaphore HSEM
- */
-
-typedef struct
-{
- __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
- __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
- __IO uint32_t IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
- __IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
- __IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
- __IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
- uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch*/
- __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
- __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
-
-} HSEM_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- __IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
- __IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
- __IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
- __IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
- __IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
- uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
- __IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
- uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
- __IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
- __IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
- __IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
- __IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
- __IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
-
-} SPI_TypeDef;
-
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- uint16_t RESERVED14; /*!< Reserved, 0x50 */
- __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
- __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
- __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
- __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
- __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
- __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
-} TIM_TypeDef;
-
-/**
- * @brief LPTIMIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- uint16_t RESERVED1; /*!< Reserved, 0x20 */
- __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
-} LPTIM_TypeDef;
-
-/**
- * @brief Comparator
- */
-typedef struct
-{
- __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
- __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
- __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
-} COMPOPT_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- uint16_t RESERVED2; /*!< Reserved, 0x12 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
- uint16_t RESERVED3; /*!< Reserved, 0x1A */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- uint16_t RESERVED4; /*!< Reserved, 0x26 */
- __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- uint16_t RESERVED5; /*!< Reserved, 0x2A */
- __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
-} USART_TypeDef;
-
-/**
- * @brief Single Wire Protocol Master Interface SPWMI
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
- __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
- uint32_t RESERVED1; /*!< Reserved, 0x08 */
- __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
- __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
- __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
- __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
- __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
- __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
-} SWPMI_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
- * @brief HASH_DIGEST
- */
-
-typedef struct
-{
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
- * @brief High resolution Timer (HRTIM)
- */
-/* HRTIM master registers definition */
-typedef struct
-{
- __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
- __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
- __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
- __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
- __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
- __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
- __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
- uint32_t RESERVED0; /*!< Reserved, 0x20 */
- __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
- __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
- __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
- uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
-}HRTIM_Master_TypeDef;
-
-/* HRTIM Timer A to E registers definition */
-typedef struct
-{
- __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
- __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
- __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
- __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
- __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
- __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
- __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
- __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
- __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
- __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
- __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
- __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
- __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
- __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
- __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
- __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
- __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
- __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
- __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
- __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
- __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
- __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
- __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
- __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
- __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
- __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
- uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
-}HRTIM_Timerx_TypeDef;
-
-/* HRTIM common register definition */
-typedef struct
-{
- __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
- __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
- __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
- __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
- __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
- __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
- __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
- __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
- __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
- __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
- __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
- __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
- __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
- __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
- __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
- __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
- __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
- __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
- __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
- __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
- __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
- __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
- __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
- __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
- __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
- __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
- __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
-}HRTIM_Common_TypeDef;
-
-/* HRTIM register definition */
-typedef struct {
- HRTIM_Master_TypeDef sMasterRegs;
- HRTIM_Timerx_TypeDef sTimerxRegs[5];
- uint32_t RESERVED0[32];
- HRTIM_Common_TypeDef sCommonRegs;
-}HRTIM_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @brief MDIOS
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t WRFR;
- __IO uint32_t CWRFR;
- __IO uint32_t RDFR;
- __IO uint32_t CRDFR;
- __IO uint32_t SR;
- __IO uint32_t CLRFR;
- uint32_t RESERVED[57];
- __IO uint32_t DINR0;
- __IO uint32_t DINR1;
- __IO uint32_t DINR2;
- __IO uint32_t DINR3;
- __IO uint32_t DINR4;
- __IO uint32_t DINR5;
- __IO uint32_t DINR6;
- __IO uint32_t DINR7;
- __IO uint32_t DINR8;
- __IO uint32_t DINR9;
- __IO uint32_t DINR10;
- __IO uint32_t DINR11;
- __IO uint32_t DINR12;
- __IO uint32_t DINR13;
- __IO uint32_t DINR14;
- __IO uint32_t DINR15;
- __IO uint32_t DINR16;
- __IO uint32_t DINR17;
- __IO uint32_t DINR18;
- __IO uint32_t DINR19;
- __IO uint32_t DINR20;
- __IO uint32_t DINR21;
- __IO uint32_t DINR22;
- __IO uint32_t DINR23;
- __IO uint32_t DINR24;
- __IO uint32_t DINR25;
- __IO uint32_t DINR26;
- __IO uint32_t DINR27;
- __IO uint32_t DINR28;
- __IO uint32_t DINR29;
- __IO uint32_t DINR30;
- __IO uint32_t DINR31;
- __IO uint32_t DOUTR0;
- __IO uint32_t DOUTR1;
- __IO uint32_t DOUTR2;
- __IO uint32_t DOUTR3;
- __IO uint32_t DOUTR4;
- __IO uint32_t DOUTR5;
- __IO uint32_t DOUTR6;
- __IO uint32_t DOUTR7;
- __IO uint32_t DOUTR8;
- __IO uint32_t DOUTR9;
- __IO uint32_t DOUTR10;
- __IO uint32_t DOUTR11;
- __IO uint32_t DOUTR12;
- __IO uint32_t DOUTR13;
- __IO uint32_t DOUTR14;
- __IO uint32_t DOUTR15;
- __IO uint32_t DOUTR16;
- __IO uint32_t DOUTR17;
- __IO uint32_t DOUTR18;
- __IO uint32_t DOUTR19;
- __IO uint32_t DOUTR20;
- __IO uint32_t DOUTR21;
- __IO uint32_t DOUTR22;
- __IO uint32_t DOUTR23;
- __IO uint32_t DOUTR24;
- __IO uint32_t DOUTR25;
- __IO uint32_t DOUTR26;
- __IO uint32_t DOUTR27;
- __IO uint32_t DOUTR28;
- __IO uint32_t DOUTR29;
- __IO uint32_t DOUTR30;
- __IO uint32_t DOUTR31;
-} MDIOS_TypeDef;
-
-
-/**
- * @brief USB_OTG_Core_Registers
- */
-typedef struct
-{
- __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
- __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
- __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
- __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
- __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
- __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
- __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
- __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
- __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
- __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
- __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
- uint32_t Reserved30[2]; /*!< Reserved 030h */
- __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
- __IO uint32_t CID; /*!< User ID Register 03Ch */
- __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
- __IO uint32_t GHWCFG1; /* User HW config1 044h*/
- __IO uint32_t GHWCFG2; /* User HW config2 048h*/
- __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
- uint32_t Reserved6; /*!< Reserved 050h */
- __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
- __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
- __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
- * @brief USB_OTG_device_Registers
- */
-typedef struct
-{
- __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
- __IO uint32_t DCTL; /*!< dev Control Register 804h */
- __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
- uint32_t Reserved0C; /*!< Reserved 80Ch */
- __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
- __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
- __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
- __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
- uint32_t Reserved20; /*!< Reserved 820h */
- uint32_t Reserved9; /*!< Reserved 824h */
- __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
- __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
- __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
- __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
- __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
- __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
- uint32_t Reserved40; /*!< dedicated EP mask 840h */
- __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
- uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
- __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
- * @brief USB_OTG_IN_Endpoint-Specific_Register
- */
-typedef struct
-{
- __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_OUT_Endpoint-Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
- __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
- __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
- uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_Host_Mode_Register_Structures
- */
-typedef struct
-{
- __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
- __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
- __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
- uint32_t Reserved40C; /*!< Reserved 40Ch */
- __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
- __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
- __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
-} USB_OTG_HostTypeDef;
-
-/**
- * @brief USB_OTG_Host_Channel_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
- __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
- __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
- __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
- __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
- __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
- uint32_t Reserved[2]; /*!< Reserved */
-} USB_OTG_HostChannelTypeDef;
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define D1_ITCMRAM_BASE ((uint32_t)0x00000000) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define D1_ITCMICP_BASE ((uint32_t)0x00100000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
-#define D1_DTCMRAM_BASE ((uint32_t)0x20000000) /*!< Base address of : 128KB system data RAM accessible over DTCM */
-#define D1_AXIFLASH_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 128 KB) embedded FLASH memory accessible over AXI */
-#define D1_AXIICP_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
-#define D1_AXISRAM_BASE ((uint32_t)0x24000000) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
-
-#define D2_AXISRAM_BASE ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
-#define D2_AHBSRAM_BASE ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
-
-#define D3_BKPSRAM_BASE ((uint32_t)0x38800000) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
-#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
-
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
-#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
-
-#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI */
-#define FLASH_END ((uint32_t)0x0801FFFF) /*!< FLASH end address */
-
-#define FLASH_OTP_BANK1_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-#define FLASH_OTP_BANK1_END ((uint32_t)0x1FF1FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-
-/* Legacy define */
-#define FLASH_BASE FLASH_BANK1_BASE
-
-#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< For legacy only , Flash bank 2 not available on STM32H750xx value line */
-#define FLASH_OTP_BANK2_BASE ((uint32_t)0x1FF40000) /*!< For legacy only , Flash bank 2 not available on STM32H750xx value line */
-#define FLASH_OTP_BANK2_END ((uint32_t)0x1FF5FFFF) /*!< For legacy only , Flash bank 2 not available on STM32H750xx value line */
-
-/*!< Peripheral memory map */
-#define D2_APB1PERIPH_BASE PERIPH_BASE
-#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000)
-
-#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000)
-
-#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000)
-#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000)
-
-/*!< Legacy Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-/*!< D1_AHB1PERIPH peripherals */
-
-#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000)
-#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000)
-#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000)
-#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000)
-#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000)
-#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000)
-#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000)
-#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000)
-#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000)
-
-/*!< D2_AHB1PERIPH peripherals */
-
-#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000)
-#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400)
-#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800)
-#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000)
-#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100)
-#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300)
-#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400)
-#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-
-/*!< USB registers base address */
-#define USB1_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
-#define USB2_OTG_FS_PERIPH_BASE ((uint32_t )0x40080000)
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
-
-/*!< D2_AHB2PERIPH peripherals */
-
-#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000)
-#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000)
-#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400)
-#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710)
-#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800)
-#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400)
-#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800)
-
-
-/*!< D3_AHB1PERIPH peripherals */
-#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800)
-#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400)
-#define RCC_C1_BASE (RCC_BASE + 0x130)
-#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800)
-#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00)
-#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400)
-#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800)
-#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000)
-#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300)
-#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400)
-
-/*!< D1_APB1PERIPH peripherals */
-#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000)
-
-/*!< D2_APB1PERIPH peripherals */
-#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000)
-#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400)
-
-
-#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00)
-#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00)
-#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00)
-#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00)
-#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400)
-#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800)
-#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010)
-#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400)
-#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000)
-#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400)
-#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800)
-#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00)
-
-/*!< D2_APB2PERIPH peripherals */
-
-#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400)
-#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400)
-#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000)
-#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000)
-#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
-#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
-#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
-#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
-#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
-#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
-#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
-#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
-#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
-#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400)
-#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
-#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
-#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
-#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
-#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
-#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
-
-
-/*!< D3_APB1PERIPH peripherals */
-#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000)
-#define EXTI_D1_BASE (EXTI_BASE + 0x0080)
-#define EXTI_D2_BASE (EXTI_BASE + 0x00C0)
-#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400)
-#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00)
-#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400)
-#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00)
-#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400)
-#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800)
-#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00)
-#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000)
-#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800)
-#define COMP1_BASE (COMP12_BASE + 0x0C)
-#define COMP2_BASE (COMP12_BASE + 0x10)
-#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00)
-#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000)
-#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800)
-
-
-#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400)
-#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
-#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
-
-
-#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008)
-#define BDMA_Channel1_BASE (BDMA_BASE + 0x001C)
-#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030)
-#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044)
-#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058)
-#define BDMA_Channel5_BASE (BDMA_BASE + 0x006C)
-#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080)
-#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094)
-
-#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
-#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004)
-#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008)
-#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000C)
-#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010)
-#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014)
-#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018)
-#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001C)
-
-#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100)
-#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104)
-#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108)
-#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010C)
-#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110)
-#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114)
-#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118)
-#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011C)
-
-#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080)
-#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140)
-
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-
-#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
-#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
-#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
-#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
-#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
-#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
-#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
-#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
-#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
-#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
-#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
-#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
-#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
-#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
-#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
-
-#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
-#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
-#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
-#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
-#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110)
-#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114)
-#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118)
-#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011C)
-
-#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
-#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
-
-
-
-/*!< FMC Banks registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0x5C001000)
-
-#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
-#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
-#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
-#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
-#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
-#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
-#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
-#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
-#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
-#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
-#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
-#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
-#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
-#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
-#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
-#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
-#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
-#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
-#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
-#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
-#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
-#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
-#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
-#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
-
-
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
-#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
-#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
-#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
-#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
-#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
-#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
-#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
-#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
-#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
-#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
-#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
-#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
-#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
-
-
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
-#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
-
-#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
-#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
-#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
-#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
-#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
-#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
-#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
-#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
-#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
-
-#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
-#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
-#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
-#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
-#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
-#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
-#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
-#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
-
-
-#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
-#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
-#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
-#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
-#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
-#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
-#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
-#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
-
-#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
-#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
-
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
-
-#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
-#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
-
-#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
-#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
-#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
-#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
-
-#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
-
-#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
-#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
-
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
-
-#define ETH ((ETH_TypeDef *)ETH_BASE)
-#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
-#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
-#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
-#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
-#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
-#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
-#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
-#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
-#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
-#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
-#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
-#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
-#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
-#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
-#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
-#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
-#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
-
-
-#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
-#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
-
-
-/* Legacy defines */
-#define USB_OTG_HS USB1_OTG_HS
-#define USB_OTG_FS USB2_OTG_FS
-#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
-#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
-
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_ISR register ********************/
-#define ADC_ISR_ADRD_Pos (0U)
-#define ADC_ISR_ADRD_Msk (0x1U << ADC_ISR_ADRD_Pos) /*!< 0x00000001 */
-#define ADC_ISR_ADRD ADC_ISR_ADRD_Msk /*!< ADC Ready (ADRDY) flag */
-#define ADC_ISR_EOSMP_Pos (1U)
-#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
-#define ADC_ISR_EOC_Pos (2U)
-#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
-#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
-#define ADC_ISR_EOS_Pos (3U)
-#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
-#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_ISR_OVR_Pos (4U)
-#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
-#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
-#define ADC_ISR_JEOC_Pos (5U)
-#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
-#define ADC_ISR_JEOS_Pos (6U)
-#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_ISR_AWD1_Pos (7U)
-#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos (8U)
-#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos (9U)
-#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
-#define ADC_ISR_JQOVF_Pos (10U)
-#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
-
-/******************** Bit definition for ADC_IER register ********************/
-#define ADC_IER_RDY_Pos (0U)
-#define ADC_IER_RDY_Msk (0x1U << ADC_IER_RDY_Pos) /*!< 0x00000001 */
-#define ADC_IER_RDY ADC_IER_RDY_Msk /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IER_EOSMP_Pos (1U)
-#define ADC_IER_EOSMP_Msk (0x1U << ADC_IER_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_IER_EOSMP ADC_IER_EOSMP_Msk /*!< ADC End of Sampling interrupt source */
-#define ADC_IER_EOC_Pos (2U)
-#define ADC_IER_EOC_Msk (0x1U << ADC_IER_EOC_Pos) /*!< 0x00000004 */
-#define ADC_IER_EOC ADC_IER_EOC_Msk /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IER_EOS_Pos (3U)
-#define ADC_IER_EOS_Msk (0x1U << ADC_IER_EOS_Pos) /*!< 0x00000008 */
-#define ADC_IER_EOS ADC_IER_EOS_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IER_OVR_Pos (4U)
-#define ADC_IER_OVR_Msk (0x1U << ADC_IER_OVR_Pos) /*!< 0x00000010 */
-#define ADC_IER_OVR ADC_IER_OVR_Msk /*!< ADC overrun interrupt source */
-#define ADC_IER_JEOC_Pos (5U)
-#define ADC_IER_JEOC_Msk (0x1U << ADC_IER_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_IER_JEOC ADC_IER_JEOC_Msk /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IER_JEOS_Pos (6U)
-#define ADC_IER_JEOS_Msk (0x1U << ADC_IER_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_IER_JEOS ADC_IER_JEOS_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IER_AWD1_Pos (7U)
-#define ADC_IER_AWD1_Msk (0x1U << ADC_IER_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_IER_AWD1 ADC_IER_AWD1_Msk /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IER_AWD2_Pos (8U)
-#define ADC_IER_AWD2_Msk (0x1U << ADC_IER_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_IER_AWD2 ADC_IER_AWD2_Msk /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IER_AWD3_Pos (9U)
-#define ADC_IER_AWD3_Msk (0x1U << ADC_IER_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_IER_AWD3 ADC_IER_AWD3_Msk /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IER_JQOVF_Pos (10U)
-#define ADC_IER_JQOVF_Msk (0x1U << ADC_IER_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_IER_JQOVF ADC_IER_JQOVF_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
-
-/******************** Bit definition for ADC_CR register ********************/
-#define ADC_CR_ADEN_Pos (0U)
-#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
-#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
-#define ADC_CR_ADDIS_Pos (1U)
-#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
-#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
-#define ADC_CR_ADSTART_Pos (2U)
-#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
-#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
-#define ADC_CR_JADSTART_Pos (3U)
-#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
-#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
-#define ADC_CR_ADSTP_Pos (4U)
-#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
-#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
-#define ADC_CR_JADSTP_Pos (5U)
-#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
-#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Boost Mode */
-#define ADC_CR_BOOST_Pos (8U)
-#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
-#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Stop of injected conversion */
-#define ADC_CR_ADCALLIN_Pos (16U)
-#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
-#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
-#define ADC_CR_LINCALRDYW1_Pos (22U)
-#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
-#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
-#define ADC_CR_LINCALRDYW2_Pos (23U)
-#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
-#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
-#define ADC_CR_LINCALRDYW3_Pos (24U)
-#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
-#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
-#define ADC_CR_LINCALRDYW4_Pos (25U)
-#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
-#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
-#define ADC_CR_LINCALRDYW5_Pos (26U)
-#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
-#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
-#define ADC_CR_LINCALRDYW6_Pos (27U)
-#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
-#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
-#define ADC_CR_ADVREGEN_Pos (28U)
-#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
-#define ADC_CR_DEEPPWD_Pos (29U)
-#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
-#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
-#define ADC_CR_ADCALDIF_Pos (30U)
-#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
-#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
-#define ADC_CR_ADCAL_Pos (31U)
-#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
-#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
-
-/******************** Bit definition for ADC_CFGR register ********************/
-#define ADC_CFGR_DMNGT_Pos (0U)
-#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
-#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
-#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
-#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
-
-#define ADC_CFGR_RES_Pos (2U)
-#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
-#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
-#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
-#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
-#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
-
-#define ADC_CFGR_EXTSEL_Pos (5U)
-#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
-#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
-#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
-#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
-#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
-
-#define ADC_CFGR_EXTEN_Pos (10U)
-#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
-#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
-#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
-#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
-
-#define ADC_CFGR_OVRMOD_Pos (12U)
-#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
-#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
-#define ADC_CFGR_CONT_Pos (13U)
-#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
-#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
-#define ADC_CFGR_AUTDLY_Pos (14U)
-#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
-#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
-
-#define ADC_CFGR_DISCEN_Pos (16U)
-#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
-#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
-
-#define ADC_CFGR_DISCNUM_Pos (17U)
-#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
-#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
-#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
-#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
-
-#define ADC_CFGR_JDISCEN_Pos (20U)
-#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
-#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
-#define ADC_CFGR_JQM_Pos (21U)
-#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
-#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
-#define ADC_CFGR_AWD1SGL_Pos (22U)
-#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
-#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
-#define ADC_CFGR_AWD1EN_Pos (23U)
-#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
-#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
-#define ADC_CFGR_JAWD1EN_Pos (24U)
-#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
-#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
-#define ADC_CFGR_JAUTO_Pos (25U)
-#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
-#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
-
-#define ADC_CFGR_AWD1CH_Pos (26U)
-#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
-#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
-#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
-#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
-#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
-#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
-#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
-
-#define ADC_CFGR_JQDIS_Pos (31U)
-#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
-#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
-
-/******************** Bit definition for ADC_CFGR2 register ********************/
-#define ADC_CFGR2_ROVSE_Pos (0U)
-#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
-#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
-#define ADC_CFGR2_JOVSE_Pos (1U)
-#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
-#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
-
-#define ADC_CFGR2_OVSS_Pos (5U)
-#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
-#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
-
-#define ADC_CFGR2_TROVS_Pos (9U)
-#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
-#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
-#define ADC_CFGR2_ROVSM_Pos (10U)
-#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
-#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
-
-#define ADC_CFGR2_RSHIFT1_Pos (11U)
-#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
-#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
-#define ADC_CFGR2_RSHIFT2_Pos (12U)
-#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
-#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
-#define ADC_CFGR2_RSHIFT3_Pos (13U)
-#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
-#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
-#define ADC_CFGR2_RSHIFT4_Pos (14U)
-#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
-#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
-
-#define ADC_CFGR2_OSR_Pos (16U)
-#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
-#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
-#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
-#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
-#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
-#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
-#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
-#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
-#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
-#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
-#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
-#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
-
-#define ADC_CFGR2_LSHIFT_Pos (28U)
-#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
-#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
-#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
-#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
-#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
-#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_SMPR1 register ********************/
-#define ADC_SMPR1_SMP0_Pos (0U)
-#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
-#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP1_Pos (3U)
-#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
-#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP2_Pos (6U)
-#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
-#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP3_Pos (9U)
-#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
-#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP4_Pos (12U)
-#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
-#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP5_Pos (15U)
-#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
-#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP6_Pos (18U)
-#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
-#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP7_Pos (21U)
-#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
-#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP8_Pos (24U)
-#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
-#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP9_Pos (27U)
-#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
-#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_SMPR2 register ********************/
-#define ADC_SMPR2_SMP10_Pos (0U)
-#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
-#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos (3U)
-#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
-#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos (6U)
-#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
-#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos (9U)
-#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
-#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos (12U)
-#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
-#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos (15U)
-#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
-#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos (18U)
-#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
-#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos (21U)
-#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
-#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos (24U)
-#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
-#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos (27U)
-#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
-#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_PCSEL register ********************/
-#define ADC_PCSEL_PCSEL_Pos (0U)
-#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
-#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
-#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
-#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
-#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
-#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
-#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
-#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
-#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
-#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
-#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
-#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
-#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
-#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
-#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
-#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
-#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
-#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
-#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
-#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
-#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_LTR1 register ********************/
-#define ADC_LTR1_LT1_Pos (0U)
-#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
-#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
-#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
-#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
-#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
-#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
-#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
-#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
-#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
-#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
-#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
-#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
-#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
-#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
-#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
-#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
-#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
-#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
-#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
-#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
-#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
-#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
-#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
-#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
-#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
-#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
-#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR1 register ********************/
-#define ADC_HTR1_HT1_Pos (0U)
-#define ADC_HTR1_HT1_Msk (0x3FFFFFFU << ADC_HTR1_HT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR1_HT1 ADC_HTR1_HT1_Msk /*!< ADC Analog watchdog 1 higher threshold */
-#define ADC_HTR1_HT1_0 (0x0000001U << ADC_HTR1_HT1_Pos) /*!< 0x00000001 */
-#define ADC_HTR1_HT1_1 (0x0000002U << ADC_HTR1_HT1_Pos) /*!< 0x00000002 */
-#define ADC_HTR1_HT1_2 (0x0000004U << ADC_HTR1_HT1_Pos) /*!< 0x00000004 */
-#define ADC_HTR1_HT1_3 (0x0000008U << ADC_HTR1_HT1_Pos) /*!< 0x00000008 */
-#define ADC_HTR1_HT1_4 (0x0000010U << ADC_HTR1_HT1_Pos) /*!< 0x00000010 */
-#define ADC_HTR1_HT1_5 (0x0000020U << ADC_HTR1_HT1_Pos) /*!< 0x00000020 */
-#define ADC_HTR1_HT1_6 (0x0000040U << ADC_HTR1_HT1_Pos) /*!< 0x00000040 */
-#define ADC_HTR1_HT1_7 (0x0000080U << ADC_HTR1_HT1_Pos) /*!< 0x00000080 */
-#define ADC_HTR1_HT1_8 (0x0000100U << ADC_HTR1_HT1_Pos) /*!< 0x00000100 */
-#define ADC_HTR1_HT1_9 (0x0000200U << ADC_HTR1_HT1_Pos) /*!< 0x00000200 */
-#define ADC_HTR1_HT1_10 (0x0000400U << ADC_HTR1_HT1_Pos) /*!< 0x00000400 */
-#define ADC_HTR1_HT1_11 (0x0000800U << ADC_HTR1_HT1_Pos) /*!< 0x00000800 */
-#define ADC_HTR1_HT1_12 (0x0001000U << ADC_HTR1_HT1_Pos) /*!< 0x00001000 */
-#define ADC_HTR1_HT1_13 (0x0002000U << ADC_HTR1_HT1_Pos) /*!< 0x00002000 */
-#define ADC_HTR1_HT1_14 (0x0004000U << ADC_HTR1_HT1_Pos) /*!< 0x00004000 */
-#define ADC_HTR1_HT1_15 (0x0008000U << ADC_HTR1_HT1_Pos) /*!< 0x00008000 */
-#define ADC_HTR1_HT1_16 (0x0010000U << ADC_HTR1_HT1_Pos) /*!< 0x00010000 */
-#define ADC_HTR1_HT1_17 (0x0020000U << ADC_HTR1_HT1_Pos) /*!< 0x00020000 */
-#define ADC_HTR1_HT1_18 (0x0040000U << ADC_HTR1_HT1_Pos) /*!< 0x00040000 */
-#define ADC_HTR1_HT1_19 (0x0080000U << ADC_HTR1_HT1_Pos) /*!< 0x00080000 */
-#define ADC_HTR1_HT1_20 (0x0100000U << ADC_HTR1_HT1_Pos) /*!< 0x00100000 */
-#define ADC_HTR1_HT1_21 (0x0200000U << ADC_HTR1_HT1_Pos) /*!< 0x00200000 */
-#define ADC_HTR1_HT1_22 (0x0400000U << ADC_HTR1_HT1_Pos) /*!< 0x00400000 */
-#define ADC_HTR1_HT1_23 (0x0800000U << ADC_HTR1_HT1_Pos) /*!< 0x00800000 */
-#define ADC_HTR1_HT1_24 (0x1000000U << ADC_HTR1_HT1_Pos) /*!< 0x01000000 */
-#define ADC_HTR1_HT1_25 (0x2000000U << ADC_HTR1_HT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR2 register ********************/
-#define ADC_LTR2_LT2_Pos (0U)
-#define ADC_LTR2_LT2_Msk (0x3FFFFFFU << ADC_LTR2_LT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR2_LT2 ADC_LTR2_LT2_Msk /*!< ADC Analog watchdog 2 lower threshold */
-#define ADC_LTR2_LT2_0 (0x0000001U << ADC_LTR2_LT2_Pos) /*!< 0x00000001 */
-#define ADC_LTR2_LT2_1 (0x0000002U << ADC_LTR2_LT2_Pos) /*!< 0x00000002 */
-#define ADC_LTR2_LT2_2 (0x0000004U << ADC_LTR2_LT2_Pos) /*!< 0x00000004 */
-#define ADC_LTR2_LT2_3 (0x0000008U << ADC_LTR2_LT2_Pos) /*!< 0x00000008 */
-#define ADC_LTR2_LT2_4 (0x0000010U << ADC_LTR2_LT2_Pos) /*!< 0x00000010 */
-#define ADC_LTR2_LT2_5 (0x0000020U << ADC_LTR2_LT2_Pos) /*!< 0x00000020 */
-#define ADC_LTR2_LT2_6 (0x0000040U << ADC_LTR2_LT2_Pos) /*!< 0x00000040 */
-#define ADC_LTR2_LT2_7 (0x0000080U << ADC_LTR2_LT2_Pos) /*!< 0x00000080 */
-#define ADC_LTR2_LT2_8 (0x0000100U << ADC_LTR2_LT2_Pos) /*!< 0x00000100 */
-#define ADC_LTR2_LT2_9 (0x0000200U << ADC_LTR2_LT2_Pos) /*!< 0x00000200 */
-#define ADC_LTR2_LT2_10 (0x0000400U << ADC_LTR2_LT2_Pos) /*!< 0x00000400 */
-#define ADC_LTR2_LT2_11 (0x0000800U << ADC_LTR2_LT2_Pos) /*!< 0x00000800 */
-#define ADC_LTR2_LT2_12 (0x0001000U << ADC_LTR2_LT2_Pos) /*!< 0x00001000 */
-#define ADC_LTR2_LT2_13 (0x0002000U << ADC_LTR2_LT2_Pos) /*!< 0x00002000 */
-#define ADC_LTR2_LT2_14 (0x0004000U << ADC_LTR2_LT2_Pos) /*!< 0x00004000 */
-#define ADC_LTR2_LT2_15 (0x0008000U << ADC_LTR2_LT2_Pos) /*!< 0x00008000 */
-#define ADC_LTR2_LT2_16 (0x0010000U << ADC_LTR2_LT2_Pos) /*!< 0x00010000 */
-#define ADC_LTR2_LT2_17 (0x0020000U << ADC_LTR2_LT2_Pos) /*!< 0x00020000 */
-#define ADC_LTR2_LT2_18 (0x0040000U << ADC_LTR2_LT2_Pos) /*!< 0x00040000 */
-#define ADC_LTR2_LT2_19 (0x0080000U << ADC_LTR2_LT2_Pos) /*!< 0x00080000 */
-#define ADC_LTR2_LT2_20 (0x0100000U << ADC_LTR2_LT2_Pos) /*!< 0x00100000 */
-#define ADC_LTR2_LT2_21 (0x0200000U << ADC_LTR2_LT2_Pos) /*!< 0x00200000 */
-#define ADC_LTR2_LT2_22 (0x0400000U << ADC_LTR2_LT2_Pos) /*!< 0x00400000 */
-#define ADC_LTR2_LT2_23 (0x0800000U << ADC_LTR2_LT2_Pos) /*!< 0x00800000 */
-#define ADC_LTR2_LT2_24 (0x1000000U << ADC_LTR2_LT2_Pos) /*!< 0x01000000 */
-#define ADC_LTR2_LT2_25 (0x2000000U << ADC_LTR2_LT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR2 register ********************/
-#define ADC_HTR2_HT2_Pos (0U)
-#define ADC_HTR2_HT2_Msk (0x3FFFFFFU << ADC_HTR2_HT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR2_HT2 ADC_HTR2_HT2_Msk /*!< ADC Analog watchdog 2 higher threshold */
-#define ADC_HTR2_HT2_0 (0x0000001U << ADC_HTR2_HT2_Pos) /*!< 0x00000001 */
-#define ADC_HTR2_HT2_1 (0x0000002U << ADC_HTR2_HT2_Pos) /*!< 0x00000002 */
-#define ADC_HTR2_HT2_2 (0x0000004U << ADC_HTR2_HT2_Pos) /*!< 0x00000004 */
-#define ADC_HTR2_HT2_3 (0x0000008U << ADC_HTR2_HT2_Pos) /*!< 0x00000008 */
-#define ADC_HTR2_HT2_4 (0x0000010U << ADC_HTR2_HT2_Pos) /*!< 0x00000010 */
-#define ADC_HTR2_HT2_5 (0x0000020U << ADC_HTR2_HT2_Pos) /*!< 0x00000020 */
-#define ADC_HTR2_HT2_6 (0x0000040U << ADC_HTR2_HT2_Pos) /*!< 0x00000040 */
-#define ADC_HTR2_HT2_7 (0x0000080U << ADC_HTR2_HT2_Pos) /*!< 0x00000080 */
-#define ADC_HTR2_HT2_8 (0x0000100U << ADC_HTR2_HT2_Pos) /*!< 0x00000100 */
-#define ADC_HTR2_HT2_9 (0x0000200U << ADC_HTR2_HT2_Pos) /*!< 0x00000200 */
-#define ADC_HTR2_HT2_10 (0x0000400U << ADC_HTR2_HT2_Pos) /*!< 0x00000400 */
-#define ADC_HTR2_HT2_11 (0x0000800U << ADC_HTR2_HT2_Pos) /*!< 0x00000800 */
-#define ADC_HTR2_HT2_12 (0x0001000U << ADC_HTR2_HT2_Pos) /*!< 0x00001000 */
-#define ADC_HTR2_HT2_13 (0x0002000U << ADC_HTR2_HT2_Pos) /*!< 0x00002000 */
-#define ADC_HTR2_HT2_14 (0x0004000U << ADC_HTR2_HT2_Pos) /*!< 0x00004000 */
-#define ADC_HTR2_HT2_15 (0x0008000U << ADC_HTR2_HT2_Pos) /*!< 0x00008000 */
-#define ADC_HTR2_HT2_16 (0x0010000U << ADC_HTR2_HT2_Pos) /*!< 0x00010000 */
-#define ADC_HTR2_HT2_17 (0x0020000U << ADC_HTR2_HT2_Pos) /*!< 0x00020000 */
-#define ADC_HTR2_HT2_18 (0x0040000U << ADC_HTR2_HT2_Pos) /*!< 0x00040000 */
-#define ADC_HTR2_HT2_19 (0x0080000U << ADC_HTR2_HT2_Pos) /*!< 0x00080000 */
-#define ADC_HTR2_HT2_20 (0x0100000U << ADC_HTR2_HT2_Pos) /*!< 0x00100000 */
-#define ADC_HTR2_HT2_21 (0x0200000U << ADC_HTR2_HT2_Pos) /*!< 0x00200000 */
-#define ADC_HTR2_HT2_22 (0x0400000U << ADC_HTR2_HT2_Pos) /*!< 0x00400000 */
-#define ADC_HTR2_HT2_23 (0x0800000U << ADC_HTR2_HT2_Pos) /*!< 0x00800000 */
-#define ADC_HTR2_HT2_24 (0x1000000U << ADC_HTR2_HT2_Pos) /*!< 0x01000000 */
-#define ADC_HTR2_HT2_25 (0x2000000U << ADC_HTR2_HT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR3 register ********************/
-#define ADC_LTR3_LT3_Pos (0U)
-#define ADC_LTR3_LT3_Msk (0x3FFFFFFU << ADC_LTR3_LT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR3_LT3 ADC_LTR3_LT3_Msk /*!< ADC Analog watchdog 3 lower threshold */
-#define ADC_LTR3_LT3_0 (0x0000001U << ADC_LTR3_LT3_Pos) /*!< 0x00000001 */
-#define ADC_LTR3_LT3_1 (0x0000002U << ADC_LTR3_LT3_Pos) /*!< 0x00000002 */
-#define ADC_LTR3_LT3_2 (0x0000004U << ADC_LTR3_LT3_Pos) /*!< 0x00000004 */
-#define ADC_LTR3_LT3_3 (0x0000008U << ADC_LTR3_LT3_Pos) /*!< 0x00000008 */
-#define ADC_LTR3_LT3_4 (0x0000010U << ADC_LTR3_LT3_Pos) /*!< 0x00000010 */
-#define ADC_LTR3_LT3_5 (0x0000020U << ADC_LTR3_LT3_Pos) /*!< 0x00000020 */
-#define ADC_LTR3_LT3_6 (0x0000040U << ADC_LTR3_LT3_Pos) /*!< 0x00000040 */
-#define ADC_LTR3_LT3_7 (0x0000080U << ADC_LTR3_LT3_Pos) /*!< 0x00000080 */
-#define ADC_LTR3_LT3_8 (0x0000100U << ADC_LTR3_LT3_Pos) /*!< 0x00000100 */
-#define ADC_LTR3_LT3_9 (0x0000200U << ADC_LTR3_LT3_Pos) /*!< 0x00000200 */
-#define ADC_LTR3_LT3_10 (0x0000400U << ADC_LTR3_LT3_Pos) /*!< 0x00000400 */
-#define ADC_LTR3_LT3_11 (0x0000800U << ADC_LTR3_LT3_Pos) /*!< 0x00000800 */
-#define ADC_LTR3_LT3_12 (0x0001000U << ADC_LTR3_LT3_Pos) /*!< 0x00001000 */
-#define ADC_LTR3_LT3_13 (0x0002000U << ADC_LTR3_LT3_Pos) /*!< 0x00002000 */
-#define ADC_LTR3_LT3_14 (0x0004000U << ADC_LTR3_LT3_Pos) /*!< 0x00004000 */
-#define ADC_LTR3_LT3_15 (0x0008000U << ADC_LTR3_LT3_Pos) /*!< 0x00008000 */
-#define ADC_LTR3_LT3_16 (0x0010000U << ADC_LTR3_LT3_Pos) /*!< 0x00010000 */
-#define ADC_LTR3_LT3_17 (0x0020000U << ADC_LTR3_LT3_Pos) /*!< 0x00020000 */
-#define ADC_LTR3_LT3_18 (0x0040000U << ADC_LTR3_LT3_Pos) /*!< 0x00040000 */
-#define ADC_LTR3_LT3_19 (0x0080000U << ADC_LTR3_LT3_Pos) /*!< 0x00080000 */
-#define ADC_LTR3_LT3_20 (0x0100000U << ADC_LTR3_LT3_Pos) /*!< 0x00100000 */
-#define ADC_LTR3_LT3_21 (0x0200000U << ADC_LTR3_LT3_Pos) /*!< 0x00200000 */
-#define ADC_LTR3_LT3_22 (0x0400000U << ADC_LTR3_LT3_Pos) /*!< 0x00400000 */
-#define ADC_LTR3_LT3_23 (0x0800000U << ADC_LTR3_LT3_Pos) /*!< 0x00800000 */
-#define ADC_LTR3_LT3_24 (0x1000000U << ADC_LTR3_LT3_Pos) /*!< 0x01000000 */
-#define ADC_LTR3_LT3_25 (0x2000000U << ADC_LTR3_LT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR3 register ********************/
-#define ADC_HTR3_HT3_Pos (0U)
-#define ADC_HTR3_HT3_Msk (0x3FFFFFFU << ADC_HTR3_HT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR3_HT3 ADC_HTR3_HT3_Msk /*!< ADC Analog watchdog 3 higher threshold */
-#define ADC_HTR3_HT3_0 (0x0000001U << ADC_HTR3_HT3_Pos) /*!< 0x00000001 */
-#define ADC_HTR3_HT3_1 (0x0000002U << ADC_HTR3_HT3_Pos) /*!< 0x00000002 */
-#define ADC_HTR3_HT3_2 (0x0000004U << ADC_HTR3_HT3_Pos) /*!< 0x00000004 */
-#define ADC_HTR3_HT3_3 (0x0000008U << ADC_HTR3_HT3_Pos) /*!< 0x00000008 */
-#define ADC_HTR3_HT3_4 (0x0000010U << ADC_HTR3_HT3_Pos) /*!< 0x00000010 */
-#define ADC_HTR3_HT3_5 (0x0000020U << ADC_HTR3_HT3_Pos) /*!< 0x00000020 */
-#define ADC_HTR3_HT3_6 (0x0000040U << ADC_HTR3_HT3_Pos) /*!< 0x00000040 */
-#define ADC_HTR3_HT3_7 (0x0000080U << ADC_HTR3_HT3_Pos) /*!< 0x00000080 */
-#define ADC_HTR3_HT3_8 (0x0000100U << ADC_HTR3_HT3_Pos) /*!< 0x00000100 */
-#define ADC_HTR3_HT3_9 (0x0000200U << ADC_HTR3_HT3_Pos) /*!< 0x00000200 */
-#define ADC_HTR3_HT3_10 (0x0000400U << ADC_HTR3_HT3_Pos) /*!< 0x00000400 */
-#define ADC_HTR3_HT3_11 (0x0000800U << ADC_HTR3_HT3_Pos) /*!< 0x00000800 */
-#define ADC_HTR3_HT3_12 (0x0001000U << ADC_HTR3_HT3_Pos) /*!< 0x00001000 */
-#define ADC_HTR3_HT3_13 (0x0002000U << ADC_HTR3_HT3_Pos) /*!< 0x00002000 */
-#define ADC_HTR3_HT3_14 (0x0004000U << ADC_HTR3_HT3_Pos) /*!< 0x00004000 */
-#define ADC_HTR3_HT3_15 (0x0008000U << ADC_HTR3_HT3_Pos) /*!< 0x00008000 */
-#define ADC_HTR3_HT3_16 (0x0010000U << ADC_HTR3_HT3_Pos) /*!< 0x00010000 */
-#define ADC_HTR3_HT3_17 (0x0020000U << ADC_HTR3_HT3_Pos) /*!< 0x00020000 */
-#define ADC_HTR3_HT3_18 (0x0040000U << ADC_HTR3_HT3_Pos) /*!< 0x00040000 */
-#define ADC_HTR3_HT3_19 (0x0080000U << ADC_HTR3_HT3_Pos) /*!< 0x00080000 */
-#define ADC_HTR3_HT3_20 (0x0100000U << ADC_HTR3_HT3_Pos) /*!< 0x00100000 */
-#define ADC_HTR3_HT3_21 (0x0200000U << ADC_HTR3_HT3_Pos) /*!< 0x00200000 */
-#define ADC_HTR3_HT3_22 (0x0400000U << ADC_HTR3_HT3_Pos) /*!< 0x00400000 */
-#define ADC_HTR3_HT3_23 (0x0800000U << ADC_HTR3_HT3_Pos) /*!< 0x00800000 */
-#define ADC_HTR3_HT3_24 (0x1000000U << ADC_HTR3_HT3_Pos) /*!< 0x01000000 */
-#define ADC_HTR3_HT3_25 (0x2000000U << ADC_HTR3_HT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_SQR1 register ********************/
-#define ADC_SQR1_L_Pos (0U)
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
-
-#define ADC_SQR1_SQ1_Pos (6U)
-#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
-#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
-#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
-#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR1_SQ2_Pos (12U)
-#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
-#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
-#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
-#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR1_SQ3_Pos (18U)
-#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
-#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
-#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
-#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR1_SQ4_Pos (24U)
-#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
-#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
-#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
-#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
-#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
-#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
-#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR2 register ********************/
-#define ADC_SQR2_SQ5_Pos (0U)
-#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
-#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ6_Pos (6U)
-#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
-#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
-#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
-#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR2_SQ7_Pos (12U)
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR2_SQ8_Pos (18U)
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR2_SQ9_Pos (24U)
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR3 register ********************/
-#define ADC_SQR3_SQ10_Pos (0U)
-#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
-#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ11_Pos (6U)
-#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
-#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
-#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
-#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR3_SQ12_Pos (12U)
-#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
-#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
-#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
-#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR3_SQ13_Pos (18U)
-#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
-#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
-#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
-#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR3_SQ14_Pos (24U)
-#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
-#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
-#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
-#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR4 register ********************/
-#define ADC_SQR4_SQ15_Pos (0U)
-#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
-#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
-#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
-#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
-#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
-#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
-#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ16_Pos (6U)
-#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
-#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
-#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
-#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
-#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
-#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
-#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
-#define ADC_DR_RDATA_0 (0x00000001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
-#define ADC_DR_RDATA_1 (0x00000002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
-#define ADC_DR_RDATA_2 (0x00000004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
-#define ADC_DR_RDATA_3 (0x00000008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
-#define ADC_DR_RDATA_4 (0x00000010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
-#define ADC_DR_RDATA_5 (0x00000020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
-#define ADC_DR_RDATA_6 (0x00000040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
-#define ADC_DR_RDATA_7 (0x00000080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
-#define ADC_DR_RDATA_8 (0x00000100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
-#define ADC_DR_RDATA_9 (0x00000200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
-#define ADC_DR_RDATA_10 (0x00000400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
-#define ADC_DR_RDATA_11 (0x00000800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
-#define ADC_DR_RDATA_12 (0x00001000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
-#define ADC_DR_RDATA_13 (0x00002000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
-#define ADC_DR_RDATA_14 (0x00004000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
-#define ADC_DR_RDATA_15 (0x00008000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
-#define ADC_DR_RDATA_16 (0x00010000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
-#define ADC_DR_RDATA_17 (0x00020000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
-#define ADC_DR_RDATA_18 (0x00040000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
-#define ADC_DR_RDATA_19 (0x00080000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
-#define ADC_DR_RDATA_20 (0x00100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
-#define ADC_DR_RDATA_21 (0x00200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
-#define ADC_DR_RDATA_22 (0x00400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
-#define ADC_DR_RDATA_23 (0x00800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
-#define ADC_DR_RDATA_24 (0x01000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
-#define ADC_DR_RDATA_25 (0x02000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
-#define ADC_DR_RDATA_26 (0x04000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
-#define ADC_DR_RDATA_27 (0x08000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
-#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
-#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
-#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
-#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JSQR register ********************/
-#define ADC_JSQR_JL_Pos (0U)
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
-
-#define ADC_JSQR_JEXTSEL_Pos (2U)
-#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
-#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
-#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
-#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
-
-#define ADC_JSQR_JEXTEN_Pos (7U)
-#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
-#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
-#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
-
-#define ADC_JSQR_JSQ1_Pos (9U)
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
-
-#define ADC_JSQR_JSQ2_Pos (15U)
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JSQ3_Pos (21U)
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
-
-#define ADC_JSQR_JSQ4_Pos (27U)
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_OFR1 register ********************/
-#define ADC_OFR1_OFFSET1_Pos (0U)
-#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
-#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
-#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
-#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
-#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
-#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
-#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
-#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
-#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
-#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
-#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
-#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
-#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
-#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
-#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
-#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
-#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
-#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
-#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
-#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
-#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
-#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
-#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
-#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
-#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
-#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
-#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR1_OFFSET1_CH_Pos (26U)
-#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
-#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR1_SSATE_Pos (31U)
-#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR2 register ********************/
-#define ADC_OFR2_OFFSET2_Pos (0U)
-#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
-#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
-#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
-#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
-#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
-#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
-#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
-#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
-#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
-#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
-#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
-#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
-#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
-#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
-#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
-#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
-#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
-#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
-#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
-#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
-#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
-#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
-#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
-#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
-#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
-#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
-#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR2_OFFSET2_CH_Pos (26U)
-#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
-#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR2_SSATE_Pos (31U)
-#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR3 register ********************/
-#define ADC_OFR3_OFFSET3_Pos (0U)
-#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
-#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
-#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
-#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
-#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
-#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
-#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
-#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
-#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
-#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
-#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
-#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
-#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
-#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
-#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
-#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
-#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
-#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
-#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
-#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
-#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
-#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
-#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
-#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
-#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
-#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
-#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR3_OFFSET3_CH_Pos (26U)
-#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
-#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR3_SSATE_Pos (31U)
-#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR4 register ********************/
-#define ADC_OFR4_OFFSET4_Pos (0U)
-#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
-#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
-#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
-#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
-#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
-#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
-#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
-#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
-#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
-#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
-#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
-#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
-#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
-#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
-#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
-#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
-#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
-#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
-#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
-#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
-#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
-#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
-#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
-#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
-#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
-#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
-#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR4_OFFSET4_CH_Pos (26U)
-#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
-#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR4_SSATE_Pos (31U)
-#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_JDR1 register ********************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR1_JDATA_0 (0x00000001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR1_JDATA_1 (0x00000002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR1_JDATA_2 (0x00000004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR1_JDATA_3 (0x00000008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR1_JDATA_4 (0x00000010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR1_JDATA_5 (0x00000020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR1_JDATA_6 (0x00000040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR1_JDATA_7 (0x00000080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR1_JDATA_8 (0x00000100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR1_JDATA_9 (0x00000200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR1_JDATA_10 (0x00000400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR1_JDATA_11 (0x00000800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR1_JDATA_12 (0x00001000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR1_JDATA_13 (0x00002000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR1_JDATA_14 (0x00004000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR1_JDATA_15 (0x00008000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR1_JDATA_16 (0x00010000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR1_JDATA_17 (0x00020000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR1_JDATA_18 (0x00040000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR1_JDATA_19 (0x00080000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR1_JDATA_20 (0x00100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR1_JDATA_21 (0x00200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR1_JDATA_22 (0x00400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR1_JDATA_23 (0x00800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR1_JDATA_24 (0x01000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR1_JDATA_25 (0x02000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR1_JDATA_26 (0x04000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR1_JDATA_27 (0x08000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR2 register ********************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR2_JDATA_0 (0x00000001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR2_JDATA_1 (0x00000002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR2_JDATA_2 (0x00000004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR2_JDATA_3 (0x00000008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR2_JDATA_4 (0x00000010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR2_JDATA_5 (0x00000020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR2_JDATA_6 (0x00000040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR2_JDATA_7 (0x00000080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR2_JDATA_8 (0x00000100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR2_JDATA_9 (0x00000200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR2_JDATA_10 (0x00000400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR2_JDATA_11 (0x00000800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR2_JDATA_12 (0x00001000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR2_JDATA_13 (0x00002000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR2_JDATA_14 (0x00004000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR2_JDATA_15 (0x00008000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR2_JDATA_16 (0x00010000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR2_JDATA_17 (0x00020000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR2_JDATA_18 (0x00040000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR2_JDATA_19 (0x00080000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR2_JDATA_20 (0x00100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR2_JDATA_21 (0x00200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR2_JDATA_22 (0x00400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR2_JDATA_23 (0x00800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR2_JDATA_24 (0x01000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR2_JDATA_25 (0x02000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR2_JDATA_26 (0x04000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR2_JDATA_27 (0x08000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR3 register ********************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR3_JDATA_0 (0x00000001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR3_JDATA_1 (0x00000002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR3_JDATA_2 (0x00000004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR3_JDATA_3 (0x00000008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR3_JDATA_4 (0x00000010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR3_JDATA_5 (0x00000020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR3_JDATA_6 (0x00000040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR3_JDATA_7 (0x00000080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR3_JDATA_8 (0x00000100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR3_JDATA_9 (0x00000200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR3_JDATA_10 (0x00000400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR3_JDATA_11 (0x00000800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR3_JDATA_12 (0x00001000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR3_JDATA_13 (0x00002000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR3_JDATA_14 (0x00004000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR3_JDATA_15 (0x00008000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR3_JDATA_16 (0x00010000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR3_JDATA_17 (0x00020000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR3_JDATA_18 (0x00040000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR3_JDATA_19 (0x00080000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR3_JDATA_20 (0x00100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR3_JDATA_21 (0x00200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR3_JDATA_22 (0x00400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR3_JDATA_23 (0x00800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR3_JDATA_24 (0x01000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR3_JDATA_25 (0x02000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR3_JDATA_26 (0x04000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR3_JDATA_27 (0x08000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR4 register ********************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR4_JDATA_0 (0x00000001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR4_JDATA_1 (0x00000002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR4_JDATA_2 (0x00000004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR4_JDATA_3 (0x00000008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR4_JDATA_4 (0x00000010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR4_JDATA_5 (0x00000020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR4_JDATA_6 (0x00000040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR4_JDATA_7 (0x00000080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR4_JDATA_8 (0x00000100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR4_JDATA_9 (0x00000200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR4_JDATA_10 (0x00000400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR4_JDATA_11 (0x00000800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR4_JDATA_12 (0x00001000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR4_JDATA_13 (0x00002000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR4_JDATA_14 (0x00004000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR4_JDATA_15 (0x00008000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR4_JDATA_16 (0x00010000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR4_JDATA_17 (0x00020000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR4_JDATA_18 (0x00040000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR4_JDATA_19 (0x00080000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR4_JDATA_20 (0x00100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR4_JDATA_21 (0x00200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR4_JDATA_22 (0x00400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR4_JDATA_23 (0x00800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR4_JDATA_24 (0x01000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR4_JDATA_25 (0x02000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR4_JDATA_26 (0x04000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR4_JDATA_27 (0x08000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_AWD2CR register ********************/
-#define ADC_AWD2CR_AWD2CH_Pos (0U)
-#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_AWD3CR register ********************/
-#define ADC_AWD3CR_AWD3CH_Pos (0U)
-#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_DIFSEL register ********************/
-#define ADC_DIFSEL_DIFSEL_Pos (0U)
-#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
-#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
-#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
-#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
-#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
-#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
-#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
-#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
-#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
-#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
-#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
-#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
-#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
-#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
-#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
-#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
-#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
-#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
-#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
-#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
-#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT_S_Pos (0U)
-#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
-#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT_CALFACT_D_Pos (16U)
-#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
-#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
-
-/******************** Bit definition for ADC_CALFACT2 register ********************/
-#define ADC_CALFACT2_LINCALFACT_Pos (0U)
-#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
-#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
-#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
-#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
-#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
-#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
-#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
-#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
-#define ADC_CALFACT2_LINCALFACT_27 (0x08000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
-#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
-#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
-
-/************************* ADC Common registers *****************************/
-/******************** Bit definition for ADC_CSR register ********************/
-#define ADC123_CSR_ADRDY_MST_Pos (0U)
-#define ADC123_CSR_ADRDY_MST_Msk (0x1U << ADC123_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CSR_ADRDY_MST ADC123_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
-#define ADC123_CSR_EOSMP_MST_Pos (1U)
-#define ADC123_CSR_EOSMP_MST_Msk (0x1U << ADC123_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CSR_EOSMP_MST ADC123_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
-#define ADC123_CSR_EOC_MST_Pos (2U)
-#define ADC123_CSR_EOC_MST_Msk (0x1U << ADC123_CSR_EOC_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CSR_EOC_MST ADC123_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
-#define ADC123_CSR_EOS_MST_Pos (3U)
-#define ADC123_CSR_EOS_MST_Msk (0x1U << ADC123_CSR_EOS_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CSR_EOS_MST ADC123_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
-#define ADC123_CSR_OVR_MST_Pos (4U)
-#define ADC123_CSR_OVR_MST_Msk (0x1U << ADC123_CSR_OVR_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CSR_OVR_MST ADC123_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
-#define ADC123_CSR_JEOC_MST_Pos (5U)
-#define ADC123_CSR_JEOC_MST_Msk (0x1U << ADC123_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CSR_JEOC_MST ADC123_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
-#define ADC123_CSR_JEOS_MST_Pos (6U)
-#define ADC123_CSR_JEOS_MST_Msk (0x1U << ADC123_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CSR_JEOS_MST ADC123_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
-#define ADC123_CSR_AWD1_MST_Pos (7U)
-#define ADC123_CSR_AWD1_MST_Msk (0x1U << ADC123_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CSR_AWD1_MST ADC123_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC123_CSR_AWD2_MST_Pos (8U)
-#define ADC123_CSR_AWD2_MST_Msk (0x1U << ADC123_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CSR_AWD2_MST ADC123_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC123_CSR_AWD3_MST_Pos (9U)
-#define ADC123_CSR_AWD3_MST_Msk (0x1U << ADC123_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CSR_AWD3_MST ADC123_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC123_CSR_JQOVF_MST_Pos (10U)
-#define ADC123_CSR_JQOVF_MST_Msk (0x1U << ADC123_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CSR_JQOVF_MST ADC123_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
-#define ADC123_CSR_ADRDY_SLV_Pos (16U)
-#define ADC123_CSR_ADRDY_SLV_Msk (0x1U << ADC123_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CSR_ADRDY_SLV ADC123_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
-#define ADC123_CSR_EOSMP_SLV_Pos (17U)
-#define ADC123_CSR_EOSMP_SLV_Msk (0x1U << ADC123_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CSR_EOSMP_SLV ADC123_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
-#define ADC123_CSR_EOC_SLV_Pos (18U)
-#define ADC123_CSR_EOC_SLV_Msk (0x1U << ADC123_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CSR_EOC_SLV ADC123_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
-#define ADC123_CSR_EOS_SLV_Pos (19U)
-#define ADC123_CSR_EOS_SLV_Msk (0x1U << ADC123_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CSR_EOS_SLV ADC123_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
-#define ADC123_CSR_OVR_SLV_Pos (20U)
-#define ADC123_CSR_OVR_SLV_Msk (0x1U << ADC123_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CSR_OVR_SLV ADC123_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
-#define ADC123_CSR_JEOC_SLV_Pos (21U)
-#define ADC123_CSR_JEOC_SLV_Msk (0x1U << ADC123_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CSR_JEOC_SLV ADC123_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
-#define ADC123_CSR_JEOS_SLV_Pos (22U)
-#define ADC123_CSR_JEOS_SLV_Msk (0x1U << ADC123_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CSR_JEOS_SLV ADC123_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
-#define ADC123_CSR_AWD1_SLV_Pos (23U)
-#define ADC123_CSR_AWD1_SLV_Msk (0x1U << ADC123_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CSR_AWD1_SLV ADC123_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC123_CSR_AWD2_SLV_Pos (24U)
-#define ADC123_CSR_AWD2_SLV_Msk (0x1U << ADC123_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CSR_AWD2_SLV ADC123_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC123_CSR_AWD3_SLV_Pos (25U)
-#define ADC123_CSR_AWD3_SLV_Msk (0x1U << ADC123_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CSR_AWD3_SLV ADC123_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC123_CSR_JQOVF_SLV_Pos (26U)
-#define ADC123_CSR_JQOVF_SLV_Msk (0x1U << ADC123_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CSR_JQOVF_SLV ADC123_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
-
-/******************** Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_DUAL_Pos (0U)
-#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
-#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
-#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
-#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
-#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
-#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
-#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
-
-#define ADC_CCR_DELAY_Pos (8U)
-#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
-#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
-#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
-#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
-#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
-#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
-
-
-#define ADC_CCR_DAMDF_Pos (14U)
-#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
-#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
-#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
-#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
-
-#define ADC_CCR_CKMODE_Pos (16U)
-#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
-#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
-#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
-#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
-
-#define ADC_CCR_PRESC_Pos (18U)
-#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
-#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
-#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos (22U)
-#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
-#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
-#define ADC_CCR_TSEN_Pos (23U)
-#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
-#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos (24U)
-#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
-#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
-
-/******************** Bit definition for ADC_CDR register ********************/
-#define ADC123_CDR_RDATA_MST_Pos (0U)
-#define ADC123_CDR_RDATA_MST_Msk (0xFFFFU << ADC123_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
-#define ADC123_CDR_RDATA_MST ADC123_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_MST_0 (0x0001U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CDR_RDATA_MST_1 (0x0002U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CDR_RDATA_MST_2 (0x0004U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CDR_RDATA_MST_3 (0x0008U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CDR_RDATA_MST_4 (0x0010U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CDR_RDATA_MST_5 (0x0020U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CDR_RDATA_MST_6 (0x0040U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CDR_RDATA_MST_7 (0x0080U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CDR_RDATA_MST_8 (0x0100U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CDR_RDATA_MST_9 (0x0200U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CDR_RDATA_MST_10 (0x0400U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CDR_RDATA_MST_11 (0x0800U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
-#define ADC123_CDR_RDATA_MST_12 (0x1000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
-#define ADC123_CDR_RDATA_MST_13 (0x2000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
-#define ADC123_CDR_RDATA_MST_14 (0x4000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
-#define ADC123_CDR_RDATA_MST_15 (0x8000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
-
-#define ADC123_CDR_RDATA_SLV_Pos (16U)
-#define ADC123_CDR_RDATA_SLV_Msk (0xFFFFU << ADC123_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
-#define ADC123_CDR_RDATA_SLV ADC123_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_SLV_0 (0x0001U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CDR_RDATA_SLV_1 (0x0002U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CDR_RDATA_SLV_2 (0x0004U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CDR_RDATA_SLV_3 (0x0008U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CDR_RDATA_SLV_4 (0x0010U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CDR_RDATA_SLV_5 (0x0020U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CDR_RDATA_SLV_6 (0x0040U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CDR_RDATA_SLV_7 (0x0080U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CDR_RDATA_SLV_8 (0x0100U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CDR_RDATA_SLV_9 (0x0200U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CDR_RDATA_SLV_10 (0x0400U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CDR_RDATA_SLV_11 (0x0800U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
-#define ADC123_CDR_RDATA_SLV_12 (0x1000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
-#define ADC123_CDR_RDATA_SLV_13 (0x2000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
-#define ADC123_CDR_RDATA_SLV_14 (0x4000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
-#define ADC123_CDR_RDATA_SLV_15 (0x8000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_CDR2 register ********************/
-#define ADC123_CDR2_RDATA_ALT_Pos (0U)
-#define ADC123_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
-#define ADC123_CDR2_RDATA_ALT ADC123_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
-#define ADC123_CDR2_RDATA_ALT_0 (0x00000001U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
-#define ADC123_CDR2_RDATA_ALT_1 (0x00000002U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
-#define ADC123_CDR2_RDATA_ALT_2 (0x00000004U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
-#define ADC123_CDR2_RDATA_ALT_3 (0x00000008U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
-#define ADC123_CDR2_RDATA_ALT_4 (0x00000010U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
-#define ADC123_CDR2_RDATA_ALT_5 (0x00000020U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
-#define ADC123_CDR2_RDATA_ALT_6 (0x00000040U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
-#define ADC123_CDR2_RDATA_ALT_7 (0x00000080U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
-#define ADC123_CDR2_RDATA_ALT_8 (0x00000100U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
-#define ADC123_CDR2_RDATA_ALT_9 (0x00000200U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
-#define ADC123_CDR2_RDATA_ALT_10 (0x00000400U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
-#define ADC123_CDR2_RDATA_ALT_11 (0x00000800U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
-#define ADC123_CDR2_RDATA_ALT_12 (0x00001000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
-#define ADC123_CDR2_RDATA_ALT_13 (0x00002000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
-#define ADC123_CDR2_RDATA_ALT_14 (0x00004000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
-#define ADC123_CDR2_RDATA_ALT_15 (0x00008000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
-#define ADC123_CDR2_RDATA_ALT_16 (0x00010000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
-#define ADC123_CDR2_RDATA_ALT_17 (0x00020000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
-#define ADC123_CDR2_RDATA_ALT_18 (0x00040000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
-#define ADC123_CDR2_RDATA_ALT_19 (0x00080000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
-#define ADC123_CDR2_RDATA_ALT_20 (0x00100000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
-#define ADC123_CDR2_RDATA_ALT_21 (0x00200000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
-#define ADC123_CDR2_RDATA_ALT_22 (0x00400000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
-#define ADC123_CDR2_RDATA_ALT_23 (0x00800000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
-#define ADC123_CDR2_RDATA_ALT_24 (0x01000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
-#define ADC123_CDR2_RDATA_ALT_25 (0x02000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
-#define ADC123_CDR2_RDATA_ALT_26 (0x04000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
-#define ADC123_CDR2_RDATA_ALT_27 (0x08000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
-#define ADC123_CDR2_RDATA_ALT_28 (0x10000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
-#define ADC123_CDR2_RDATA_ALT_29 (0x20000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
-#define ADC123_CDR2_RDATA_ALT_30 (0x40000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
-#define ADC123_CDR2_RDATA_ALT_31 (0x80000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
-
-/******************************************************************************/
-/* */
-/* VREFBUF */
-/* */
-/******************************************************************************/
-/******************* Bit definition for VREFBUF_CSR register ****************/
-#define VREFBUF_CSR_ENVR_Pos (0U)
-#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/
-#define DAC_CR_CEN1_Pos (14U)
-#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
-#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
-
-#define DAC_CR_EN2_Pos (16U)
-#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
-#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
-#define DAC_CR_CEN2_Pos (30U)
-#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
-#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!© COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS_Device
- * @{
- */
-
-/** @addtogroup stm32h753xx
- * @{
- */
-
-#ifndef __STM32H753xx_H
-#define __STM32H753xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32H7XX Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
- ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
- FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
- FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
- FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
- FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
- USART6_IRQn = 71, /*!< USART6 global interrupt */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
- DCMI_IRQn = 78, /*!< DCMI global interrupt */
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
- FPU_IRQn = 81, /*!< FPU global interrupt */
- UART7_IRQn = 82, /*!< UART7 global interrupt */
- UART8_IRQn = 83, /*!< UART8 global interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
- DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
- SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
- QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
- LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
- CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
- I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
- I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
- SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
- OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
- OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
- OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
- OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
- DMAMUX1_OVR_IRQn = 102, /*!
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
- __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
- __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
- uint32_t RESERVED1; /*!< Reserved, 0x028 */
- uint32_t RESERVED2; /*!< Reserved, 0x02C */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
- __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- uint32_t RESERVED3; /*!< Reserved, 0x044 */
- uint32_t RESERVED4; /*!< Reserved, 0x048 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
- uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
- __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
- __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
- __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
- __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
- uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
- uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
- __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
- __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
- uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
- uint32_t RESERVED9; /*!< Reserved, 0x0AC */
- __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
- __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
- __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
- __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
- __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
- __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
- __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
-} ADC_TypeDef;
-
-
-typedef struct
-{
-__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
-uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
-__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
-__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
-__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
-
-} ADC_Common_TypeDef;
-
-/**
- * @brief VREFBUF
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
- __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
- __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
- __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
- __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
- __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
- __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
- __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
- __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
- __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
- __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
- __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
- __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
- __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
- __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
- __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
- __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
- __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
- __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
- __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
- __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
- __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
- __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
- __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
- __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
- __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
- __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
- __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
- __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
- __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
- __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
- __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
- __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
- __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
- __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
- __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
- __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
- __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
- __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
- __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
- __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
- __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
- __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
- __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
- __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
- __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
- __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
- __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
- __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
- __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
- __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
- __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
- __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
- __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
-} FDCAN_GlobalTypeDef;
-
-/**
- * @brief TTFD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
- __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
- __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
- __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
- __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
- __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
- __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
- __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
- __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
- __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
- __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
- __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
- __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
- __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
- __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
- __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
- __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
- __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
- __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
-} TTCAN_TypeDef;
-
-/**
- * @brief FD Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
- __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
- __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
- __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
- __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
- __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
-} FDCAN_ClockCalibrationUnit_TypeDef;
-
-
-/**
- * @brief Consumer Electronics Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
- __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
- __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
- __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
- __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
- __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
- __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
- * @brief DFSDM module registers
- */
-typedef struct
-{
- __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
- __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
- __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
- __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
- __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
- __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
- __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
- __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
- __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
- __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
- __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
- __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
- __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
- __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
- __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
-} DFSDM_Filter_TypeDef;
-
-/**
- * @brief DFSDM channel configuration registers
- */
-typedef struct
-{
- __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
- __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
- __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
- short circuit detector register, Address offset: 0x08 */
- __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
- __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
-} DFSDM_Channel_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
- __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
- __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
- __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
- uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
- __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DCMI
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA stream x configuration register */
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} BDMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} BDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< DMA Channel Status Register */
- __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
- __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
- __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
- * @brief MDMA Controller
- */
-typedef struct
-{
- __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
-}MDMA_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
- __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
- __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
- __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
- __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
- __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
- __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
- __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
- __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
- __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
- __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
- __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
- __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
-}MDMA_Channel_TypeDef;
-/**
- * @brief DMA2D Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
-} DMA2D_TypeDef;
-
-/**
- * @brief Ethernet MAC
- */
-typedef struct
-{
- __IO uint32_t MACCR;
- __IO uint32_t MACECR;
- __IO uint32_t MACPFR;
- __IO uint32_t MACWTR;
- __IO uint32_t MACHT0R;
- __IO uint32_t MACHT1R;
- uint32_t RESERVED1[14];
- __IO uint32_t MACVTR;
- uint32_t RESERVED2;
- __IO uint32_t MACVHTR;
- uint32_t RESERVED3;
- __IO uint32_t MACVIR;
- __IO uint32_t MACIVIR;
- uint32_t RESERVED4[2];
- __IO uint32_t MACTFCR;
- uint32_t RESERVED5[7];
- __IO uint32_t MACRFCR;
- uint32_t RESERVED6[7];
- __IO uint32_t MACISR;
- __IO uint32_t MACIER;
- __IO uint32_t MACRXTXSR;
- uint32_t RESERVED7;
- __IO uint32_t MACPCSR;
- __IO uint32_t MACRWKPFR;
- uint32_t RESERVED8[2];
- __IO uint32_t MACLCSR;
- __IO uint32_t MACLTCR;
- __IO uint32_t MACLETR;
- __IO uint32_t MAC1USTCR;
- uint32_t RESERVED9[12];
- __IO uint32_t MACVR;
- __IO uint32_t MACDR;
- uint32_t RESERVED10;
- __IO uint32_t MACHWF0R;
- __IO uint32_t MACHWF1R;
- __IO uint32_t MACHWF2R;
- uint32_t RESERVED11[54];
- __IO uint32_t MACMDIOAR;
- __IO uint32_t MACMDIODR;
- uint32_t RESERVED12[2];
- __IO uint32_t MACARPAR;
- uint32_t RESERVED13[59];
- __IO uint32_t MACA0HR;
- __IO uint32_t MACA0LR;
- __IO uint32_t MACA1HR;
- __IO uint32_t MACA1LR;
- __IO uint32_t MACA2HR;
- __IO uint32_t MACA2LR;
- __IO uint32_t MACA3HR;
- __IO uint32_t MACA3LR;
- uint32_t RESERVED14[248];
- __IO uint32_t MMCCR;
- __IO uint32_t MMCRIR;
- __IO uint32_t MMCTIR;
- __IO uint32_t MMCRIMR;
- __IO uint32_t MMCTIMR;
- uint32_t RESERVED15[14];
- __IO uint32_t MMCTSCGPR;
- __IO uint32_t MMCTMCGPR;
- int32_t RESERVED16[5];
- __IO uint32_t MMCTPCGR;
- uint32_t RESERVED17[10];
- __IO uint32_t MMCRCRCEPR;
- __IO uint32_t MMCRAEPR;
- uint32_t RESERVED18[10];
- __IO uint32_t MMCRUPGR;
- uint32_t RESERVED19[9];
- __IO uint32_t MMCTLPIMSTR;
- __IO uint32_t MMCTLPITCR;
- __IO uint32_t MMCRLPIMSTR;
- __IO uint32_t MMCRLPITCR;
- uint32_t RESERVED20[65];
- __IO uint32_t MACL3L4C0R;
- __IO uint32_t MACL4A0R;
- uint32_t RESERVED21[2];
- __IO uint32_t MACL3A0R0R;
- __IO uint32_t MACL3A1R0R;
- __IO uint32_t MACL3A2R0R;
- __IO uint32_t MACL3A3R0R;
- uint32_t RESERVED22[4];
- __IO uint32_t MACL3L4C1R;
- __IO uint32_t MACL4A1R;
- uint32_t RESERVED23[2];
- __IO uint32_t MACL3A0R1R;
- __IO uint32_t MACL3A1R1R;
- __IO uint32_t MACL3A2R1R;
- __IO uint32_t MACL3A3R1R;
- uint32_t RESERVED24[108];
- __IO uint32_t MACTSCR;
- __IO uint32_t MACSSIR;
- __IO uint32_t MACSTSR;
- __IO uint32_t MACSTNR;
- __IO uint32_t MACSTSUR;
- __IO uint32_t MACSTNUR;
- __IO uint32_t MACTSAR;
- uint32_t RESERVED25;
- __IO uint32_t MACTSSR;
- uint32_t RESERVED26[3];
- __IO uint32_t MACTTSSNR;
- __IO uint32_t MACTTSSSR;
- uint32_t RESERVED27[2];
- __IO uint32_t MACACR;
- uint32_t RESERVED28;
- __IO uint32_t MACATSNR;
- __IO uint32_t MACATSSR;
- __IO uint32_t MACTSIACR;
- __IO uint32_t MACTSEACR;
- __IO uint32_t MACTSICNR;
- __IO uint32_t MACTSECNR;
- uint32_t RESERVED29[4];
- __IO uint32_t MACPPSCR;
- uint32_t RESERVED30[3];
- __IO uint32_t MACPPSTTSR;
- __IO uint32_t MACPPSTTNR;
- __IO uint32_t MACPPSIR;
- __IO uint32_t MACPPSWR;
- uint32_t RESERVED31[12];
- __IO uint32_t MACPOCR;
- __IO uint32_t MACSPI0R;
- __IO uint32_t MACSPI1R;
- __IO uint32_t MACSPI2R;
- __IO uint32_t MACLMIR;
- uint32_t RESERVED32[11];
- __IO uint32_t MTLOMR;
- uint32_t RESERVED33[7];
- __IO uint32_t MTLISR;
- uint32_t RESERVED34[55];
- __IO uint32_t MTLTQOMR;
- __IO uint32_t MTLTQUR;
- __IO uint32_t MTLTQDR;
- uint32_t RESERVED35[8];
- __IO uint32_t MTLQICSR;
- __IO uint32_t MTLRQOMR;
- __IO uint32_t MTLRQMPOCR;
- __IO uint32_t MTLRQDR;
- uint32_t RESERVED36[177];
- __IO uint32_t DMAMR;
- __IO uint32_t DMASBMR;
- __IO uint32_t DMAISR;
- __IO uint32_t DMADSR;
- uint32_t RESERVED37[60];
- __IO uint32_t DMACCR;
- __IO uint32_t DMACTCR;
- __IO uint32_t DMACRCR;
- uint32_t RESERVED38[2];
- __IO uint32_t DMACTDLAR;
- uint32_t RESERVED39;
- __IO uint32_t DMACRDLAR;
- __IO uint32_t DMACTDTPR;
- uint32_t RESERVED40;
- __IO uint32_t DMACRDTPR;
- __IO uint32_t DMACTDRLR;
- __IO uint32_t DMACRDRLR;
- __IO uint32_t DMACIER;
- __IO uint32_t DMACRIWTR;
-__IO uint32_t DMACSFCSR;
- uint32_t RESERVED41;
- __IO uint32_t DMACCATDR;
- uint32_t RESERVED42;
- __IO uint32_t DMACCARDR;
- uint32_t RESERVED43;
- __IO uint32_t DMACCATBR;
- uint32_t RESERVED44;
- __IO uint32_t DMACCARBR;
- __IO uint32_t DMACSR;
-uint32_t RESERVED45[2];
-__IO uint32_t DMACMFCR;
-}ETH_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
-__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
-__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
-__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
-__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, Address offset: 0x0C */
-__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x10 */
-__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x14 */
-uint32_t RESERVED1; /*!< Reserved, 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
-__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
-__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
-__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, Address offset: 0x2C */
-__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x30 */
-__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x34 */
-uint32_t RESERVED3; /*!< Reserved, 0x38 */
-uint32_t RESERVED4; /*!< Reserved, 0x3C */
-__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
-__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
-__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
-__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, Address offset: 0x4C */
-__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, Address offset: 0x50 */
-__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High,Address offset: 0x54 */
-}EXTI_TypeDef;
-
-typedef struct
-{
-__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
-__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
-__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
-uint32_t RESERVED1; /*!< Reserved, 0x0C */
-__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
-__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
-__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
-uint32_t RESERVED2; /*!< Reserved, 0x1C */
-__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
-__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
-__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
-}EXTI_Core_TypeDef;
-
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
- __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
- __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
- __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
- __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
- __IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */
- __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
- __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
- __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
- __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
- __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */
- __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
- __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
- __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
- __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
- __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
- __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
- __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
- __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
- __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
- uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
- __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
- uint32_t RESERVED2; /*!< Reserved, 0x108 */
- __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
- __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
- __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
- uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
- __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
- __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
- __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
- __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
- __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
- __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
- uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
- __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
- __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
- __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
- __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
- __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
-} FLASH_TypeDef;
-
-/**
- * @brief Flexible Memory Controller
- */
-
-typedef struct
-{
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FMC_Bank1_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank1E
- */
-
-typedef struct
-{
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FMC_Bank1E_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank2
- */
-
-typedef struct
-{
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
- uint32_t RESERVED0; /*!< Reserved, 0x70 */
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
-} FMC_Bank2_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank3
- */
-
-typedef struct
-{
- __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
- __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
- __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
- __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
- uint32_t RESERVED; /*!< Reserved, 0x90 */
- __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
-} FMC_Bank3_TypeDef;
-
-/**
- * @brief Flexible Memory Controller Bank5 and 6
- */
-
-
-typedef struct
-{
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
-} FMC_Bank5_6_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/**
- * @brief Operational Amplifier (OPAMP)
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
- __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
- __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/**
- * @brief System configuration controller
- */
-
-typedef struct
-{
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
- __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
- uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
- __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
- __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
- __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
- uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
- __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
- uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
- __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
- __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
- __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
- __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
- __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
- __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
- __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
- __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
- __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
- __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
- __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
- __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
- __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
- __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
- __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
- __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
- __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
- __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
-
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-
-/**
- * @brief JPEG Codec
- */
-typedef struct
-{
- __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
- __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
- __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
- __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
- __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
- __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
- __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
- __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
- uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
- __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
- __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
- __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
- uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
- __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
- __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
- uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
- __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
- __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
- __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
- __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
- __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
- __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
- __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
- __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
- uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
- __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
- __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
- __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
- __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
-
-} JPEG_TypeDef;
-
-
-/**
- * @brief LCD-TFT Display Controller
- */
-
-typedef struct
-{
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
-} LTDC_TypeDef;
-
-/**
- * @brief LCD-TFT Display layer x Controller
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
- uint32_t RESERVED0[2]; /*!< Reserved */
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
- uint32_t RESERVED1[3]; /*!< Reserved */
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
-
-} LTDC_Layer_TypeDef;
-
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
- __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
- __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
- __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
- __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
- __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
- __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
- uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
- __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
- __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
- __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
- __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
- __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
- __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
- __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
- __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
- __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
- __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
- __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
- __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
- __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
- __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
- __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
- uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
- __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
- uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
- __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
- __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
- __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
- __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
- __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
- uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA4 */
- __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
- uint32_t RESERVED8[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
- __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
- __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
- __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
- __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
- __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
- __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
- uint32_t RESERVED9; /*!< Reserved, Address offset: 0xF8 */
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
- __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
- __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
- __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
- __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
- __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
- uint32_t RESERVED10[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
-
-} RCC_TypeDef;
-
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
- uint32_t reserved; /*!< Reserved */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAMPCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
- __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
- __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
- __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
- __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
- __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
- __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
- __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
- __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
- __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
- __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
- __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
- __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
- __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
-} RTC_TypeDef;
-
-
-/**
- * @brief Serial Audio Interface
- */
-
-typedef struct
-{
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
- uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
- __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
- __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
-} SAI_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
-} SAI_Block_TypeDef;
-
-/**
- * @brief SPDIF-RX Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
- __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
- __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
- __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
- __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1A */
-} SPDIFRX_TypeDef;
-
-
-/**
- * @brief Secure digital input/output Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
- __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
- __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
- __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
- __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
- __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
- __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
- __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
- __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
- __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
- __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
- __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
- __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
- __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
- __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
- __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
- __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
- uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
- __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
- __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
- __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
- __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
- uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
- __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
- uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
- __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
-} SDMMC_TypeDef;
-
-
-/**
- * @brief Delay Block DLYB
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
-} DLYB_TypeDef;
-
-/**
- * @brief HW Semaphore HSEM
- */
-
-typedef struct
-{
- __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
- __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
- __IO uint32_t IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
- __IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
- __IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
- __IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
- uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch*/
- __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
- __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
-
-} HSEM_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- __IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
- __IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
- __IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
- __IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
- uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
- __IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
- uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
- __IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
- uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
- __IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
- __IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
- __IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
- __IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
- __IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
-
-} SPI_TypeDef;
-
-/**
- * @brief QUAD Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
- __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
- __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
- __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
- __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
- __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
- __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
- __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
- __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
- __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
- __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
- __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
-} QUADSPI_TypeDef;
-
-
-/**
- * @brief TIM
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
- uint16_t RESERVED9; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED10; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED12; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
- uint16_t RESERVED13; /*!< Reserved, 0x4E */
- uint16_t RESERVED14; /*!< Reserved, 0x50 */
- __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
- __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
- __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
- __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
- __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
- __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
-} TIM_TypeDef;
-
-/**
- * @brief LPTIMIMER
- */
-typedef struct
-{
- __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
- __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
- __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
- __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
- __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
- __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
- uint16_t RESERVED1; /*!< Reserved, 0x20 */
- __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
-} LPTIM_TypeDef;
-
-/**
- * @brief Comparator
- */
-typedef struct
-{
- __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
- __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
- __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
-} COMPOPT_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- uint16_t RESERVED2; /*!< Reserved, 0x12 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
- uint16_t RESERVED3; /*!< Reserved, 0x1A */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- uint16_t RESERVED4; /*!< Reserved, 0x26 */
- __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- uint16_t RESERVED5; /*!< Reserved, 0x2A */
- __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
-} USART_TypeDef;
-
-/**
- * @brief Single Wire Protocol Master Interface SPWMI
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
- __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
- uint32_t RESERVED1; /*!< Reserved, 0x08 */
- __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
- __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
- __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
- __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
- __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
- __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
-} SWPMI_TypeDef;
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @brief Crypto Processor
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
- __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
-} CRYP_TypeDef;
-
-/**
- * @brief HASH
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
-} HASH_TypeDef;
-
-/**
- * @brief HASH_DIGEST
- */
-
-typedef struct
-{
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
-} HASH_DIGEST_TypeDef;
-
-/**
- * @brief High resolution Timer (HRTIM)
- */
-/* HRTIM master registers definition */
-typedef struct
-{
- __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
- __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
- __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
- __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
- __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
- __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
- __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
- uint32_t RESERVED0; /*!< Reserved, 0x20 */
- __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
- __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
- __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
- uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
-}HRTIM_Master_TypeDef;
-
-/* HRTIM Timer A to E registers definition */
-typedef struct
-{
- __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
- __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
- __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
- __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
- __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
- __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
- __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
- __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
- __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
- __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
- __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
- __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
- __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
- __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
- __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
- __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
- __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
- __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
- __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
- __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
- __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
- __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
- __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
- __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
- __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
- __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
- uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
-}HRTIM_Timerx_TypeDef;
-
-/* HRTIM common register definition */
-typedef struct
-{
- __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
- __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
- __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
- __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
- __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
- __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
- __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
- __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
- __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
- __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
- __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
- __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
- __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
- __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
- __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
- __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
- __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
- __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
- __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
- __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
- __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
- __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
- __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
- __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
- __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
- __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
- __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
- __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
-}HRTIM_Common_TypeDef;
-
-/* HRTIM register definition */
-typedef struct {
- HRTIM_Master_TypeDef sMasterRegs;
- HRTIM_Timerx_TypeDef sTimerxRegs[5];
- uint32_t RESERVED0[32];
- HRTIM_Common_TypeDef sCommonRegs;
-}HRTIM_TypeDef;
-
-/**
- * @brief RNG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
-} RNG_TypeDef;
-
-/**
- * @brief MDIOS
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t WRFR;
- __IO uint32_t CWRFR;
- __IO uint32_t RDFR;
- __IO uint32_t CRDFR;
- __IO uint32_t SR;
- __IO uint32_t CLRFR;
- uint32_t RESERVED[57];
- __IO uint32_t DINR0;
- __IO uint32_t DINR1;
- __IO uint32_t DINR2;
- __IO uint32_t DINR3;
- __IO uint32_t DINR4;
- __IO uint32_t DINR5;
- __IO uint32_t DINR6;
- __IO uint32_t DINR7;
- __IO uint32_t DINR8;
- __IO uint32_t DINR9;
- __IO uint32_t DINR10;
- __IO uint32_t DINR11;
- __IO uint32_t DINR12;
- __IO uint32_t DINR13;
- __IO uint32_t DINR14;
- __IO uint32_t DINR15;
- __IO uint32_t DINR16;
- __IO uint32_t DINR17;
- __IO uint32_t DINR18;
- __IO uint32_t DINR19;
- __IO uint32_t DINR20;
- __IO uint32_t DINR21;
- __IO uint32_t DINR22;
- __IO uint32_t DINR23;
- __IO uint32_t DINR24;
- __IO uint32_t DINR25;
- __IO uint32_t DINR26;
- __IO uint32_t DINR27;
- __IO uint32_t DINR28;
- __IO uint32_t DINR29;
- __IO uint32_t DINR30;
- __IO uint32_t DINR31;
- __IO uint32_t DOUTR0;
- __IO uint32_t DOUTR1;
- __IO uint32_t DOUTR2;
- __IO uint32_t DOUTR3;
- __IO uint32_t DOUTR4;
- __IO uint32_t DOUTR5;
- __IO uint32_t DOUTR6;
- __IO uint32_t DOUTR7;
- __IO uint32_t DOUTR8;
- __IO uint32_t DOUTR9;
- __IO uint32_t DOUTR10;
- __IO uint32_t DOUTR11;
- __IO uint32_t DOUTR12;
- __IO uint32_t DOUTR13;
- __IO uint32_t DOUTR14;
- __IO uint32_t DOUTR15;
- __IO uint32_t DOUTR16;
- __IO uint32_t DOUTR17;
- __IO uint32_t DOUTR18;
- __IO uint32_t DOUTR19;
- __IO uint32_t DOUTR20;
- __IO uint32_t DOUTR21;
- __IO uint32_t DOUTR22;
- __IO uint32_t DOUTR23;
- __IO uint32_t DOUTR24;
- __IO uint32_t DOUTR25;
- __IO uint32_t DOUTR26;
- __IO uint32_t DOUTR27;
- __IO uint32_t DOUTR28;
- __IO uint32_t DOUTR29;
- __IO uint32_t DOUTR30;
- __IO uint32_t DOUTR31;
-} MDIOS_TypeDef;
-
-
-/**
- * @brief USB_OTG_Core_Registers
- */
-typedef struct
-{
- __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
- __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
- __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
- __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
- __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
- __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
- __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
- __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
- __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
- __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
- __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
- uint32_t Reserved30[2]; /*!< Reserved 030h */
- __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
- __IO uint32_t CID; /*!< User ID Register 03Ch */
- __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
- __IO uint32_t GHWCFG1; /* User HW config1 044h*/
- __IO uint32_t GHWCFG2; /* User HW config2 048h*/
- __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
- uint32_t Reserved6; /*!< Reserved 050h */
- __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
- __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
- __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
-
-
-/**
- * @brief USB_OTG_device_Registers
- */
-typedef struct
-{
- __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
- __IO uint32_t DCTL; /*!< dev Control Register 804h */
- __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
- uint32_t Reserved0C; /*!< Reserved 80Ch */
- __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
- __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
- __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
- __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
- uint32_t Reserved20; /*!< Reserved 820h */
- uint32_t Reserved9; /*!< Reserved 824h */
- __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
- __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
- __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
- __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
- __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
- __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
- uint32_t Reserved40; /*!< dedicated EP mask 840h */
- __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
- uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
- __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
-} USB_OTG_DeviceTypeDef;
-
-
-/**
- * @brief USB_OTG_IN_Endpoint-Specific_Register
- */
-typedef struct
-{
- __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_OUT_Endpoint-Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
- uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
- __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
- __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
- uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-
-/**
- * @brief USB_OTG_Host_Mode_Register_Structures
- */
-typedef struct
-{
- __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
- __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
- __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
- uint32_t Reserved40C; /*!< Reserved 40Ch */
- __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
- __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
- __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
-} USB_OTG_HostTypeDef;
-
-/**
- * @brief USB_OTG_Host_Channel_Specific_Registers
- */
-typedef struct
-{
- __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
- __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
- __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
- __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
- __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
- __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
- uint32_t Reserved[2]; /*!< Reserved */
-} USB_OTG_HostChannelTypeDef;
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-#define D1_ITCMRAM_BASE ((uint32_t)0x00000000) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define D1_ITCMICP_BASE ((uint32_t)0x00100000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
-#define D1_DTCMRAM_BASE ((uint32_t)0x20000000) /*!< Base address of : 128KB system data RAM accessible over DTCM */
-#define D1_AXIFLASH_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
-#define D1_AXIICP_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
-#define D1_AXISRAM_BASE ((uint32_t)0x24000000) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
-
-#define D2_AXISRAM_BASE ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
-#define D2_AHBSRAM_BASE ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
-
-#define D3_BKPSRAM_BASE ((uint32_t)0x38800000) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
-#define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
-
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
-#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
-
-#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
-#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
-#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
-
-#define FLASH_OTP_BANK1_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-#define FLASH_OTP_BANK1_END ((uint32_t)0x1FF1FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank1 OTP Area */
-#define FLASH_OTP_BANK2_BASE ((uint32_t)0x1FF40000) /*!< Base address of : (up to 128KB) embedded FLASH Bank2 OTP Area */
-#define FLASH_OTP_BANK2_END ((uint32_t)0x1FF5FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank2 OTP Area */
-
-/* Legacy define */
-#define FLASH_BASE FLASH_BANK1_BASE
-
-
-/*!< Peripheral memory map */
-#define D2_APB1PERIPH_BASE PERIPH_BASE
-#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000)
-
-#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000)
-
-#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000)
-#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000)
-
-/*!< Legacy Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-/*!< D1_AHB1PERIPH peripherals */
-
-#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000)
-#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000)
-#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000)
-#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000)
-#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000)
-#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000)
-#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000)
-#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000)
-#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000)
-
-/*!< D2_AHB1PERIPH peripherals */
-
-#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000)
-#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400)
-#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800)
-#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000)
-#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100)
-#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300)
-#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400)
-#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000)
-#define ETH_MAC_BASE (ETH_BASE)
-
-/*!< USB registers base address */
-#define USB1_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
-#define USB2_OTG_FS_PERIPH_BASE ((uint32_t )0x40080000)
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
-
-/*!< D2_AHB2PERIPH peripherals */
-
-#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000)
-#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000)
-#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400)
-#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710)
-#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800)
-#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400)
-#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800)
-
-
-/*!< D3_AHB1PERIPH peripherals */
-#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000)
-#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400)
-#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800)
-#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400)
-#define RCC_C1_BASE (RCC_BASE + 0x130)
-#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800)
-#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00)
-#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400)
-#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800)
-#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000)
-#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300)
-#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400)
-
-/*!< D1_APB1PERIPH peripherals */
-#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000)
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
-#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000)
-
-/*!< D2_APB1PERIPH peripherals */
-#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000)
-#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400)
-
-
-#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00)
-#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00)
-#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00)
-#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400)
-#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800)
-#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00)
-#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400)
-#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800)
-#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000)
-#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010)
-#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400)
-#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000)
-#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400)
-#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800)
-#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00)
-
-/*!< D2_APB2PERIPH peripherals */
-
-#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400)
-#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000)
-#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400)
-#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000)
-#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
-#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
-#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000)
-#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
-#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
-#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000)
-#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
-#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
-#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
-#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
-#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
-#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
-#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
-#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
-#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
-#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
-#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
-#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
-#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400)
-#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
-#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
-#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
-#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
-#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
-#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
-
-
-/*!< D3_APB1PERIPH peripherals */
-#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000)
-#define EXTI_D1_BASE (EXTI_BASE + 0x0080)
-#define EXTI_D2_BASE (EXTI_BASE + 0x00C0)
-#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400)
-#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00)
-#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400)
-#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00)
-#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400)
-#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800)
-#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00)
-#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000)
-#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800)
-#define COMP1_BASE (COMP12_BASE + 0x0C)
-#define COMP2_BASE (COMP12_BASE + 0x10)
-#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00)
-#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000)
-#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800)
-
-
-#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400)
-#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
-#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
-
-
-#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008)
-#define BDMA_Channel1_BASE (BDMA_BASE + 0x001C)
-#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030)
-#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044)
-#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058)
-#define BDMA_Channel5_BASE (BDMA_BASE + 0x006C)
-#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080)
-#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094)
-
-#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
-#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004)
-#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008)
-#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000C)
-#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010)
-#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014)
-#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018)
-#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001C)
-
-#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100)
-#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104)
-#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108)
-#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010C)
-#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110)
-#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114)
-#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118)
-#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011C)
-
-#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080)
-#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140)
-
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
-
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
-
-#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
-#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
-#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
-#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
-#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
-#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
-#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
-#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
-#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
-#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
-#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
-#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
-#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
-#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
-#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
-
-#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
-#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
-#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
-#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
-#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110)
-#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114)
-#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118)
-#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011C)
-
-#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
-#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
-
-
-
-/*!< FMC Banks registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-
-/* Debug MCU registers base address */
-#define DBGMCU_BASE ((uint32_t )0x5C001000)
-
-#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
-#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
-#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
-#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
-#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
-#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
-#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
-#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
-#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
-#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
-#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
-#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
-#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
-#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
-#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
-#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
-#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART6 ((USART_TypeDef *) USART6_BASE)
-#define UART7 ((USART_TypeDef *) UART7_BASE)
-#define UART8 ((USART_TypeDef *) UART8_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
-#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
-#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
-#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
-#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
-#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
-#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
-#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
-#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
-
-
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
-#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
-#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
-#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
-#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
-#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
-#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
-#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
-#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
-#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
-#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
-#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
-#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
-#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
-#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
-#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
-#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
-#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
-
-
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
-#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
-#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
-#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
-#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
-#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
-#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
-#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
-#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
-#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
-#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
-#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
-#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
-#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
-#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
-#define HASH ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
-#define RNG ((RNG_TypeDef *) RNG_BASE)
-#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
-#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
-
-#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
-#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
-#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
-#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
-#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
-#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
-#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
-#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
-#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
-
-#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
-#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
-#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
-#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
-#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
-#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
-#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
-#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
-
-
-#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
-#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
-#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
-#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
-#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
-#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
-#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
-#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
-
-#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
-#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
-
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-
-
-#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
-#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
-
-#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
-#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
-#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
-#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
-
-#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-
-#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
-#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
-
-#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
-#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
-
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
-#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
-
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
-#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
-
-#define ETH ((ETH_TypeDef *)ETH_BASE)
-#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
-#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
-#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
-#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
-#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
-#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
-#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
-#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
-#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
-#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
-#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
-#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
-#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
-#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
-#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
-#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
-#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
-
-
-#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
-#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
-
-
-/* Legacy defines */
-#define USB_OTG_HS USB1_OTG_HS
-#define USB_OTG_FS USB2_OTG_FS
-#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
-#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
-
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter */
-/* */
-/******************************************************************************/
-/******************** Bit definition for ADC_ISR register ********************/
-#define ADC_ISR_ADRD_Pos (0U)
-#define ADC_ISR_ADRD_Msk (0x1U << ADC_ISR_ADRD_Pos) /*!< 0x00000001 */
-#define ADC_ISR_ADRD ADC_ISR_ADRD_Msk /*!< ADC Ready (ADRDY) flag */
-#define ADC_ISR_EOSMP_Pos (1U)
-#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
-#define ADC_ISR_EOC_Pos (2U)
-#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
-#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
-#define ADC_ISR_EOS_Pos (3U)
-#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
-#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_ISR_OVR_Pos (4U)
-#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
-#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
-#define ADC_ISR_JEOC_Pos (5U)
-#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
-#define ADC_ISR_JEOS_Pos (6U)
-#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_ISR_AWD1_Pos (7U)
-#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos (8U)
-#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos (9U)
-#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
-#define ADC_ISR_JQOVF_Pos (10U)
-#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
-
-/******************** Bit definition for ADC_IER register ********************/
-#define ADC_IER_RDY_Pos (0U)
-#define ADC_IER_RDY_Msk (0x1U << ADC_IER_RDY_Pos) /*!< 0x00000001 */
-#define ADC_IER_RDY ADC_IER_RDY_Msk /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IER_EOSMP_Pos (1U)
-#define ADC_IER_EOSMP_Msk (0x1U << ADC_IER_EOSMP_Pos) /*!< 0x00000002 */
-#define ADC_IER_EOSMP ADC_IER_EOSMP_Msk /*!< ADC End of Sampling interrupt source */
-#define ADC_IER_EOC_Pos (2U)
-#define ADC_IER_EOC_Msk (0x1U << ADC_IER_EOC_Pos) /*!< 0x00000004 */
-#define ADC_IER_EOC ADC_IER_EOC_Msk /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IER_EOS_Pos (3U)
-#define ADC_IER_EOS_Msk (0x1U << ADC_IER_EOS_Pos) /*!< 0x00000008 */
-#define ADC_IER_EOS ADC_IER_EOS_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IER_OVR_Pos (4U)
-#define ADC_IER_OVR_Msk (0x1U << ADC_IER_OVR_Pos) /*!< 0x00000010 */
-#define ADC_IER_OVR ADC_IER_OVR_Msk /*!< ADC overrun interrupt source */
-#define ADC_IER_JEOC_Pos (5U)
-#define ADC_IER_JEOC_Msk (0x1U << ADC_IER_JEOC_Pos) /*!< 0x00000020 */
-#define ADC_IER_JEOC ADC_IER_JEOC_Msk /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IER_JEOS_Pos (6U)
-#define ADC_IER_JEOS_Msk (0x1U << ADC_IER_JEOS_Pos) /*!< 0x00000040 */
-#define ADC_IER_JEOS ADC_IER_JEOS_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IER_AWD1_Pos (7U)
-#define ADC_IER_AWD1_Msk (0x1U << ADC_IER_AWD1_Pos) /*!< 0x00000080 */
-#define ADC_IER_AWD1 ADC_IER_AWD1_Msk /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IER_AWD2_Pos (8U)
-#define ADC_IER_AWD2_Msk (0x1U << ADC_IER_AWD2_Pos) /*!< 0x00000100 */
-#define ADC_IER_AWD2 ADC_IER_AWD2_Msk /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IER_AWD3_Pos (9U)
-#define ADC_IER_AWD3_Msk (0x1U << ADC_IER_AWD3_Pos) /*!< 0x00000200 */
-#define ADC_IER_AWD3 ADC_IER_AWD3_Msk /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IER_JQOVF_Pos (10U)
-#define ADC_IER_JQOVF_Msk (0x1U << ADC_IER_JQOVF_Pos) /*!< 0x00000400 */
-#define ADC_IER_JQOVF ADC_IER_JQOVF_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
-
-/******************** Bit definition for ADC_CR register ********************/
-#define ADC_CR_ADEN_Pos (0U)
-#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
-#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
-#define ADC_CR_ADDIS_Pos (1U)
-#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
-#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
-#define ADC_CR_ADSTART_Pos (2U)
-#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
-#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
-#define ADC_CR_JADSTART_Pos (3U)
-#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
-#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
-#define ADC_CR_ADSTP_Pos (4U)
-#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
-#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
-#define ADC_CR_JADSTP_Pos (5U)
-#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
-#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Boost Mode */
-#define ADC_CR_BOOST_Pos (8U)
-#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
-#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Stop of injected conversion */
-#define ADC_CR_ADCALLIN_Pos (16U)
-#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
-#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
-#define ADC_CR_LINCALRDYW1_Pos (22U)
-#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
-#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
-#define ADC_CR_LINCALRDYW2_Pos (23U)
-#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
-#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
-#define ADC_CR_LINCALRDYW3_Pos (24U)
-#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
-#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
-#define ADC_CR_LINCALRDYW4_Pos (25U)
-#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
-#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
-#define ADC_CR_LINCALRDYW5_Pos (26U)
-#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
-#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
-#define ADC_CR_LINCALRDYW6_Pos (27U)
-#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
-#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
-#define ADC_CR_ADVREGEN_Pos (28U)
-#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
-#define ADC_CR_DEEPPWD_Pos (29U)
-#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
-#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
-#define ADC_CR_ADCALDIF_Pos (30U)
-#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
-#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
-#define ADC_CR_ADCAL_Pos (31U)
-#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
-#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
-
-/******************** Bit definition for ADC_CFGR register ********************/
-#define ADC_CFGR_DMNGT_Pos (0U)
-#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
-#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
-#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
-#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
-
-#define ADC_CFGR_RES_Pos (2U)
-#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
-#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
-#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
-#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
-#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
-
-#define ADC_CFGR_EXTSEL_Pos (5U)
-#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
-#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
-#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
-#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
-#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
-#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
-
-#define ADC_CFGR_EXTEN_Pos (10U)
-#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
-#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
-#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
-#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
-
-#define ADC_CFGR_OVRMOD_Pos (12U)
-#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
-#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
-#define ADC_CFGR_CONT_Pos (13U)
-#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
-#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
-#define ADC_CFGR_AUTDLY_Pos (14U)
-#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
-#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
-
-#define ADC_CFGR_DISCEN_Pos (16U)
-#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
-#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
-
-#define ADC_CFGR_DISCNUM_Pos (17U)
-#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
-#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
-#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
-#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
-#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
-
-#define ADC_CFGR_JDISCEN_Pos (20U)
-#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
-#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
-#define ADC_CFGR_JQM_Pos (21U)
-#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
-#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
-#define ADC_CFGR_AWD1SGL_Pos (22U)
-#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
-#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
-#define ADC_CFGR_AWD1EN_Pos (23U)
-#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
-#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
-#define ADC_CFGR_JAWD1EN_Pos (24U)
-#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
-#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
-#define ADC_CFGR_JAUTO_Pos (25U)
-#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
-#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
-
-#define ADC_CFGR_AWD1CH_Pos (26U)
-#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
-#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
-#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
-#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
-#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
-#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
-#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
-
-#define ADC_CFGR_JQDIS_Pos (31U)
-#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
-#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
-
-/******************** Bit definition for ADC_CFGR2 register ********************/
-#define ADC_CFGR2_ROVSE_Pos (0U)
-#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
-#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
-#define ADC_CFGR2_JOVSE_Pos (1U)
-#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
-#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
-
-#define ADC_CFGR2_OVSS_Pos (5U)
-#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
-#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
-
-#define ADC_CFGR2_TROVS_Pos (9U)
-#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
-#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
-#define ADC_CFGR2_ROVSM_Pos (10U)
-#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
-#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
-
-#define ADC_CFGR2_RSHIFT1_Pos (11U)
-#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
-#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
-#define ADC_CFGR2_RSHIFT2_Pos (12U)
-#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
-#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
-#define ADC_CFGR2_RSHIFT3_Pos (13U)
-#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
-#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
-#define ADC_CFGR2_RSHIFT4_Pos (14U)
-#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
-#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
-
-#define ADC_CFGR2_OSR_Pos (16U)
-#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
-#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
-#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
-#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
-#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
-#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
-#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
-#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
-#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
-#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
-#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
-#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
-
-#define ADC_CFGR2_LSHIFT_Pos (28U)
-#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
-#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
-#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
-#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
-#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
-#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_SMPR1 register ********************/
-#define ADC_SMPR1_SMP0_Pos (0U)
-#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
-#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP1_Pos (3U)
-#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
-#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP2_Pos (6U)
-#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
-#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP3_Pos (9U)
-#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
-#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP4_Pos (12U)
-#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
-#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP5_Pos (15U)
-#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
-#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP6_Pos (18U)
-#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
-#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP7_Pos (21U)
-#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
-#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP8_Pos (24U)
-#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
-#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP9_Pos (27U)
-#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
-#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_SMPR2 register ********************/
-#define ADC_SMPR2_SMP10_Pos (0U)
-#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
-#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos (3U)
-#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
-#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos (6U)
-#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
-#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos (9U)
-#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
-#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos (12U)
-#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
-#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos (15U)
-#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
-#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos (18U)
-#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
-#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos (21U)
-#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
-#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos (24U)
-#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
-#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos (27U)
-#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
-#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
-
-/******************** Bit definition for ADC_PCSEL register ********************/
-#define ADC_PCSEL_PCSEL_Pos (0U)
-#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
-#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
-#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
-#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
-#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
-#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
-#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
-#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
-#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
-#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
-#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
-#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
-#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
-#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
-#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
-#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
-#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
-#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
-#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
-#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
-#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_LTR1 register ********************/
-#define ADC_LTR1_LT1_Pos (0U)
-#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
-#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
-#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
-#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
-#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
-#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
-#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
-#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
-#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
-#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
-#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
-#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
-#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
-#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
-#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
-#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
-#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
-#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
-#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
-#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
-#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
-#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
-#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
-#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
-#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
-#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
-#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR1 register ********************/
-#define ADC_HTR1_HT1_Pos (0U)
-#define ADC_HTR1_HT1_Msk (0x3FFFFFFU << ADC_HTR1_HT1_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR1_HT1 ADC_HTR1_HT1_Msk /*!< ADC Analog watchdog 1 higher threshold */
-#define ADC_HTR1_HT1_0 (0x0000001U << ADC_HTR1_HT1_Pos) /*!< 0x00000001 */
-#define ADC_HTR1_HT1_1 (0x0000002U << ADC_HTR1_HT1_Pos) /*!< 0x00000002 */
-#define ADC_HTR1_HT1_2 (0x0000004U << ADC_HTR1_HT1_Pos) /*!< 0x00000004 */
-#define ADC_HTR1_HT1_3 (0x0000008U << ADC_HTR1_HT1_Pos) /*!< 0x00000008 */
-#define ADC_HTR1_HT1_4 (0x0000010U << ADC_HTR1_HT1_Pos) /*!< 0x00000010 */
-#define ADC_HTR1_HT1_5 (0x0000020U << ADC_HTR1_HT1_Pos) /*!< 0x00000020 */
-#define ADC_HTR1_HT1_6 (0x0000040U << ADC_HTR1_HT1_Pos) /*!< 0x00000040 */
-#define ADC_HTR1_HT1_7 (0x0000080U << ADC_HTR1_HT1_Pos) /*!< 0x00000080 */
-#define ADC_HTR1_HT1_8 (0x0000100U << ADC_HTR1_HT1_Pos) /*!< 0x00000100 */
-#define ADC_HTR1_HT1_9 (0x0000200U << ADC_HTR1_HT1_Pos) /*!< 0x00000200 */
-#define ADC_HTR1_HT1_10 (0x0000400U << ADC_HTR1_HT1_Pos) /*!< 0x00000400 */
-#define ADC_HTR1_HT1_11 (0x0000800U << ADC_HTR1_HT1_Pos) /*!< 0x00000800 */
-#define ADC_HTR1_HT1_12 (0x0001000U << ADC_HTR1_HT1_Pos) /*!< 0x00001000 */
-#define ADC_HTR1_HT1_13 (0x0002000U << ADC_HTR1_HT1_Pos) /*!< 0x00002000 */
-#define ADC_HTR1_HT1_14 (0x0004000U << ADC_HTR1_HT1_Pos) /*!< 0x00004000 */
-#define ADC_HTR1_HT1_15 (0x0008000U << ADC_HTR1_HT1_Pos) /*!< 0x00008000 */
-#define ADC_HTR1_HT1_16 (0x0010000U << ADC_HTR1_HT1_Pos) /*!< 0x00010000 */
-#define ADC_HTR1_HT1_17 (0x0020000U << ADC_HTR1_HT1_Pos) /*!< 0x00020000 */
-#define ADC_HTR1_HT1_18 (0x0040000U << ADC_HTR1_HT1_Pos) /*!< 0x00040000 */
-#define ADC_HTR1_HT1_19 (0x0080000U << ADC_HTR1_HT1_Pos) /*!< 0x00080000 */
-#define ADC_HTR1_HT1_20 (0x0100000U << ADC_HTR1_HT1_Pos) /*!< 0x00100000 */
-#define ADC_HTR1_HT1_21 (0x0200000U << ADC_HTR1_HT1_Pos) /*!< 0x00200000 */
-#define ADC_HTR1_HT1_22 (0x0400000U << ADC_HTR1_HT1_Pos) /*!< 0x00400000 */
-#define ADC_HTR1_HT1_23 (0x0800000U << ADC_HTR1_HT1_Pos) /*!< 0x00800000 */
-#define ADC_HTR1_HT1_24 (0x1000000U << ADC_HTR1_HT1_Pos) /*!< 0x01000000 */
-#define ADC_HTR1_HT1_25 (0x2000000U << ADC_HTR1_HT1_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR2 register ********************/
-#define ADC_LTR2_LT2_Pos (0U)
-#define ADC_LTR2_LT2_Msk (0x3FFFFFFU << ADC_LTR2_LT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR2_LT2 ADC_LTR2_LT2_Msk /*!< ADC Analog watchdog 2 lower threshold */
-#define ADC_LTR2_LT2_0 (0x0000001U << ADC_LTR2_LT2_Pos) /*!< 0x00000001 */
-#define ADC_LTR2_LT2_1 (0x0000002U << ADC_LTR2_LT2_Pos) /*!< 0x00000002 */
-#define ADC_LTR2_LT2_2 (0x0000004U << ADC_LTR2_LT2_Pos) /*!< 0x00000004 */
-#define ADC_LTR2_LT2_3 (0x0000008U << ADC_LTR2_LT2_Pos) /*!< 0x00000008 */
-#define ADC_LTR2_LT2_4 (0x0000010U << ADC_LTR2_LT2_Pos) /*!< 0x00000010 */
-#define ADC_LTR2_LT2_5 (0x0000020U << ADC_LTR2_LT2_Pos) /*!< 0x00000020 */
-#define ADC_LTR2_LT2_6 (0x0000040U << ADC_LTR2_LT2_Pos) /*!< 0x00000040 */
-#define ADC_LTR2_LT2_7 (0x0000080U << ADC_LTR2_LT2_Pos) /*!< 0x00000080 */
-#define ADC_LTR2_LT2_8 (0x0000100U << ADC_LTR2_LT2_Pos) /*!< 0x00000100 */
-#define ADC_LTR2_LT2_9 (0x0000200U << ADC_LTR2_LT2_Pos) /*!< 0x00000200 */
-#define ADC_LTR2_LT2_10 (0x0000400U << ADC_LTR2_LT2_Pos) /*!< 0x00000400 */
-#define ADC_LTR2_LT2_11 (0x0000800U << ADC_LTR2_LT2_Pos) /*!< 0x00000800 */
-#define ADC_LTR2_LT2_12 (0x0001000U << ADC_LTR2_LT2_Pos) /*!< 0x00001000 */
-#define ADC_LTR2_LT2_13 (0x0002000U << ADC_LTR2_LT2_Pos) /*!< 0x00002000 */
-#define ADC_LTR2_LT2_14 (0x0004000U << ADC_LTR2_LT2_Pos) /*!< 0x00004000 */
-#define ADC_LTR2_LT2_15 (0x0008000U << ADC_LTR2_LT2_Pos) /*!< 0x00008000 */
-#define ADC_LTR2_LT2_16 (0x0010000U << ADC_LTR2_LT2_Pos) /*!< 0x00010000 */
-#define ADC_LTR2_LT2_17 (0x0020000U << ADC_LTR2_LT2_Pos) /*!< 0x00020000 */
-#define ADC_LTR2_LT2_18 (0x0040000U << ADC_LTR2_LT2_Pos) /*!< 0x00040000 */
-#define ADC_LTR2_LT2_19 (0x0080000U << ADC_LTR2_LT2_Pos) /*!< 0x00080000 */
-#define ADC_LTR2_LT2_20 (0x0100000U << ADC_LTR2_LT2_Pos) /*!< 0x00100000 */
-#define ADC_LTR2_LT2_21 (0x0200000U << ADC_LTR2_LT2_Pos) /*!< 0x00200000 */
-#define ADC_LTR2_LT2_22 (0x0400000U << ADC_LTR2_LT2_Pos) /*!< 0x00400000 */
-#define ADC_LTR2_LT2_23 (0x0800000U << ADC_LTR2_LT2_Pos) /*!< 0x00800000 */
-#define ADC_LTR2_LT2_24 (0x1000000U << ADC_LTR2_LT2_Pos) /*!< 0x01000000 */
-#define ADC_LTR2_LT2_25 (0x2000000U << ADC_LTR2_LT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR2 register ********************/
-#define ADC_HTR2_HT2_Pos (0U)
-#define ADC_HTR2_HT2_Msk (0x3FFFFFFU << ADC_HTR2_HT2_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR2_HT2 ADC_HTR2_HT2_Msk /*!< ADC Analog watchdog 2 higher threshold */
-#define ADC_HTR2_HT2_0 (0x0000001U << ADC_HTR2_HT2_Pos) /*!< 0x00000001 */
-#define ADC_HTR2_HT2_1 (0x0000002U << ADC_HTR2_HT2_Pos) /*!< 0x00000002 */
-#define ADC_HTR2_HT2_2 (0x0000004U << ADC_HTR2_HT2_Pos) /*!< 0x00000004 */
-#define ADC_HTR2_HT2_3 (0x0000008U << ADC_HTR2_HT2_Pos) /*!< 0x00000008 */
-#define ADC_HTR2_HT2_4 (0x0000010U << ADC_HTR2_HT2_Pos) /*!< 0x00000010 */
-#define ADC_HTR2_HT2_5 (0x0000020U << ADC_HTR2_HT2_Pos) /*!< 0x00000020 */
-#define ADC_HTR2_HT2_6 (0x0000040U << ADC_HTR2_HT2_Pos) /*!< 0x00000040 */
-#define ADC_HTR2_HT2_7 (0x0000080U << ADC_HTR2_HT2_Pos) /*!< 0x00000080 */
-#define ADC_HTR2_HT2_8 (0x0000100U << ADC_HTR2_HT2_Pos) /*!< 0x00000100 */
-#define ADC_HTR2_HT2_9 (0x0000200U << ADC_HTR2_HT2_Pos) /*!< 0x00000200 */
-#define ADC_HTR2_HT2_10 (0x0000400U << ADC_HTR2_HT2_Pos) /*!< 0x00000400 */
-#define ADC_HTR2_HT2_11 (0x0000800U << ADC_HTR2_HT2_Pos) /*!< 0x00000800 */
-#define ADC_HTR2_HT2_12 (0x0001000U << ADC_HTR2_HT2_Pos) /*!< 0x00001000 */
-#define ADC_HTR2_HT2_13 (0x0002000U << ADC_HTR2_HT2_Pos) /*!< 0x00002000 */
-#define ADC_HTR2_HT2_14 (0x0004000U << ADC_HTR2_HT2_Pos) /*!< 0x00004000 */
-#define ADC_HTR2_HT2_15 (0x0008000U << ADC_HTR2_HT2_Pos) /*!< 0x00008000 */
-#define ADC_HTR2_HT2_16 (0x0010000U << ADC_HTR2_HT2_Pos) /*!< 0x00010000 */
-#define ADC_HTR2_HT2_17 (0x0020000U << ADC_HTR2_HT2_Pos) /*!< 0x00020000 */
-#define ADC_HTR2_HT2_18 (0x0040000U << ADC_HTR2_HT2_Pos) /*!< 0x00040000 */
-#define ADC_HTR2_HT2_19 (0x0080000U << ADC_HTR2_HT2_Pos) /*!< 0x00080000 */
-#define ADC_HTR2_HT2_20 (0x0100000U << ADC_HTR2_HT2_Pos) /*!< 0x00100000 */
-#define ADC_HTR2_HT2_21 (0x0200000U << ADC_HTR2_HT2_Pos) /*!< 0x00200000 */
-#define ADC_HTR2_HT2_22 (0x0400000U << ADC_HTR2_HT2_Pos) /*!< 0x00400000 */
-#define ADC_HTR2_HT2_23 (0x0800000U << ADC_HTR2_HT2_Pos) /*!< 0x00800000 */
-#define ADC_HTR2_HT2_24 (0x1000000U << ADC_HTR2_HT2_Pos) /*!< 0x01000000 */
-#define ADC_HTR2_HT2_25 (0x2000000U << ADC_HTR2_HT2_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_LTR3 register ********************/
-#define ADC_LTR3_LT3_Pos (0U)
-#define ADC_LTR3_LT3_Msk (0x3FFFFFFU << ADC_LTR3_LT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_LTR3_LT3 ADC_LTR3_LT3_Msk /*!< ADC Analog watchdog 3 lower threshold */
-#define ADC_LTR3_LT3_0 (0x0000001U << ADC_LTR3_LT3_Pos) /*!< 0x00000001 */
-#define ADC_LTR3_LT3_1 (0x0000002U << ADC_LTR3_LT3_Pos) /*!< 0x00000002 */
-#define ADC_LTR3_LT3_2 (0x0000004U << ADC_LTR3_LT3_Pos) /*!< 0x00000004 */
-#define ADC_LTR3_LT3_3 (0x0000008U << ADC_LTR3_LT3_Pos) /*!< 0x00000008 */
-#define ADC_LTR3_LT3_4 (0x0000010U << ADC_LTR3_LT3_Pos) /*!< 0x00000010 */
-#define ADC_LTR3_LT3_5 (0x0000020U << ADC_LTR3_LT3_Pos) /*!< 0x00000020 */
-#define ADC_LTR3_LT3_6 (0x0000040U << ADC_LTR3_LT3_Pos) /*!< 0x00000040 */
-#define ADC_LTR3_LT3_7 (0x0000080U << ADC_LTR3_LT3_Pos) /*!< 0x00000080 */
-#define ADC_LTR3_LT3_8 (0x0000100U << ADC_LTR3_LT3_Pos) /*!< 0x00000100 */
-#define ADC_LTR3_LT3_9 (0x0000200U << ADC_LTR3_LT3_Pos) /*!< 0x00000200 */
-#define ADC_LTR3_LT3_10 (0x0000400U << ADC_LTR3_LT3_Pos) /*!< 0x00000400 */
-#define ADC_LTR3_LT3_11 (0x0000800U << ADC_LTR3_LT3_Pos) /*!< 0x00000800 */
-#define ADC_LTR3_LT3_12 (0x0001000U << ADC_LTR3_LT3_Pos) /*!< 0x00001000 */
-#define ADC_LTR3_LT3_13 (0x0002000U << ADC_LTR3_LT3_Pos) /*!< 0x00002000 */
-#define ADC_LTR3_LT3_14 (0x0004000U << ADC_LTR3_LT3_Pos) /*!< 0x00004000 */
-#define ADC_LTR3_LT3_15 (0x0008000U << ADC_LTR3_LT3_Pos) /*!< 0x00008000 */
-#define ADC_LTR3_LT3_16 (0x0010000U << ADC_LTR3_LT3_Pos) /*!< 0x00010000 */
-#define ADC_LTR3_LT3_17 (0x0020000U << ADC_LTR3_LT3_Pos) /*!< 0x00020000 */
-#define ADC_LTR3_LT3_18 (0x0040000U << ADC_LTR3_LT3_Pos) /*!< 0x00040000 */
-#define ADC_LTR3_LT3_19 (0x0080000U << ADC_LTR3_LT3_Pos) /*!< 0x00080000 */
-#define ADC_LTR3_LT3_20 (0x0100000U << ADC_LTR3_LT3_Pos) /*!< 0x00100000 */
-#define ADC_LTR3_LT3_21 (0x0200000U << ADC_LTR3_LT3_Pos) /*!< 0x00200000 */
-#define ADC_LTR3_LT3_22 (0x0400000U << ADC_LTR3_LT3_Pos) /*!< 0x00400000 */
-#define ADC_LTR3_LT3_23 (0x0800000U << ADC_LTR3_LT3_Pos) /*!< 0x00800000 */
-#define ADC_LTR3_LT3_24 (0x1000000U << ADC_LTR3_LT3_Pos) /*!< 0x01000000 */
-#define ADC_LTR3_LT3_25 (0x2000000U << ADC_LTR3_LT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_HTR3 register ********************/
-#define ADC_HTR3_HT3_Pos (0U)
-#define ADC_HTR3_HT3_Msk (0x3FFFFFFU << ADC_HTR3_HT3_Pos) /*!< 0x03FFFFFF */
-#define ADC_HTR3_HT3 ADC_HTR3_HT3_Msk /*!< ADC Analog watchdog 3 higher threshold */
-#define ADC_HTR3_HT3_0 (0x0000001U << ADC_HTR3_HT3_Pos) /*!< 0x00000001 */
-#define ADC_HTR3_HT3_1 (0x0000002U << ADC_HTR3_HT3_Pos) /*!< 0x00000002 */
-#define ADC_HTR3_HT3_2 (0x0000004U << ADC_HTR3_HT3_Pos) /*!< 0x00000004 */
-#define ADC_HTR3_HT3_3 (0x0000008U << ADC_HTR3_HT3_Pos) /*!< 0x00000008 */
-#define ADC_HTR3_HT3_4 (0x0000010U << ADC_HTR3_HT3_Pos) /*!< 0x00000010 */
-#define ADC_HTR3_HT3_5 (0x0000020U << ADC_HTR3_HT3_Pos) /*!< 0x00000020 */
-#define ADC_HTR3_HT3_6 (0x0000040U << ADC_HTR3_HT3_Pos) /*!< 0x00000040 */
-#define ADC_HTR3_HT3_7 (0x0000080U << ADC_HTR3_HT3_Pos) /*!< 0x00000080 */
-#define ADC_HTR3_HT3_8 (0x0000100U << ADC_HTR3_HT3_Pos) /*!< 0x00000100 */
-#define ADC_HTR3_HT3_9 (0x0000200U << ADC_HTR3_HT3_Pos) /*!< 0x00000200 */
-#define ADC_HTR3_HT3_10 (0x0000400U << ADC_HTR3_HT3_Pos) /*!< 0x00000400 */
-#define ADC_HTR3_HT3_11 (0x0000800U << ADC_HTR3_HT3_Pos) /*!< 0x00000800 */
-#define ADC_HTR3_HT3_12 (0x0001000U << ADC_HTR3_HT3_Pos) /*!< 0x00001000 */
-#define ADC_HTR3_HT3_13 (0x0002000U << ADC_HTR3_HT3_Pos) /*!< 0x00002000 */
-#define ADC_HTR3_HT3_14 (0x0004000U << ADC_HTR3_HT3_Pos) /*!< 0x00004000 */
-#define ADC_HTR3_HT3_15 (0x0008000U << ADC_HTR3_HT3_Pos) /*!< 0x00008000 */
-#define ADC_HTR3_HT3_16 (0x0010000U << ADC_HTR3_HT3_Pos) /*!< 0x00010000 */
-#define ADC_HTR3_HT3_17 (0x0020000U << ADC_HTR3_HT3_Pos) /*!< 0x00020000 */
-#define ADC_HTR3_HT3_18 (0x0040000U << ADC_HTR3_HT3_Pos) /*!< 0x00040000 */
-#define ADC_HTR3_HT3_19 (0x0080000U << ADC_HTR3_HT3_Pos) /*!< 0x00080000 */
-#define ADC_HTR3_HT3_20 (0x0100000U << ADC_HTR3_HT3_Pos) /*!< 0x00100000 */
-#define ADC_HTR3_HT3_21 (0x0200000U << ADC_HTR3_HT3_Pos) /*!< 0x00200000 */
-#define ADC_HTR3_HT3_22 (0x0400000U << ADC_HTR3_HT3_Pos) /*!< 0x00400000 */
-#define ADC_HTR3_HT3_23 (0x0800000U << ADC_HTR3_HT3_Pos) /*!< 0x00800000 */
-#define ADC_HTR3_HT3_24 (0x1000000U << ADC_HTR3_HT3_Pos) /*!< 0x01000000 */
-#define ADC_HTR3_HT3_25 (0x2000000U << ADC_HTR3_HT3_Pos) /*!< 0x02000000 */
-
-/******************** Bit definition for ADC_SQR1 register ********************/
-#define ADC_SQR1_L_Pos (0U)
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
-
-#define ADC_SQR1_SQ1_Pos (6U)
-#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
-#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
-#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
-#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR1_SQ2_Pos (12U)
-#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
-#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
-#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
-#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR1_SQ3_Pos (18U)
-#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
-#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
-#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
-#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR1_SQ4_Pos (24U)
-#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
-#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
-#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
-#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
-#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
-#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
-#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR2 register ********************/
-#define ADC_SQR2_SQ5_Pos (0U)
-#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
-#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ6_Pos (6U)
-#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
-#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
-#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
-#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR2_SQ7_Pos (12U)
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR2_SQ8_Pos (18U)
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR2_SQ9_Pos (24U)
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR3 register ********************/
-#define ADC_SQR3_SQ10_Pos (0U)
-#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
-#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ11_Pos (6U)
-#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
-#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
-#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
-#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
-
-#define ADC_SQR3_SQ12_Pos (12U)
-#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
-#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
-#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
-#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
-
-#define ADC_SQR3_SQ13_Pos (18U)
-#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
-#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
-#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
-#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
-
-#define ADC_SQR3_SQ14_Pos (24U)
-#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
-#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
-#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
-#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
-
-/******************** Bit definition for ADC_SQR4 register ********************/
-#define ADC_SQR4_SQ15_Pos (0U)
-#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
-#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
-#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
-#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
-#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
-#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
-#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ16_Pos (6U)
-#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
-#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
-#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
-#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
-#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
-#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
-#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_RDATA_Pos (0U)
-#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
-#define ADC_DR_RDATA_0 (0x00000001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
-#define ADC_DR_RDATA_1 (0x00000002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
-#define ADC_DR_RDATA_2 (0x00000004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
-#define ADC_DR_RDATA_3 (0x00000008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
-#define ADC_DR_RDATA_4 (0x00000010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
-#define ADC_DR_RDATA_5 (0x00000020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
-#define ADC_DR_RDATA_6 (0x00000040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
-#define ADC_DR_RDATA_7 (0x00000080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
-#define ADC_DR_RDATA_8 (0x00000100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
-#define ADC_DR_RDATA_9 (0x00000200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
-#define ADC_DR_RDATA_10 (0x00000400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
-#define ADC_DR_RDATA_11 (0x00000800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
-#define ADC_DR_RDATA_12 (0x00001000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
-#define ADC_DR_RDATA_13 (0x00002000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
-#define ADC_DR_RDATA_14 (0x00004000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
-#define ADC_DR_RDATA_15 (0x00008000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
-#define ADC_DR_RDATA_16 (0x00010000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
-#define ADC_DR_RDATA_17 (0x00020000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
-#define ADC_DR_RDATA_18 (0x00040000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
-#define ADC_DR_RDATA_19 (0x00080000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
-#define ADC_DR_RDATA_20 (0x00100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
-#define ADC_DR_RDATA_21 (0x00200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
-#define ADC_DR_RDATA_22 (0x00400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
-#define ADC_DR_RDATA_23 (0x00800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
-#define ADC_DR_RDATA_24 (0x01000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
-#define ADC_DR_RDATA_25 (0x02000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
-#define ADC_DR_RDATA_26 (0x04000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
-#define ADC_DR_RDATA_27 (0x08000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
-#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
-#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
-#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
-#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JSQR register ********************/
-#define ADC_JSQR_JL_Pos (0U)
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
-
-#define ADC_JSQR_JEXTSEL_Pos (2U)
-#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
-#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
-#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
-#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
-
-#define ADC_JSQR_JEXTEN_Pos (7U)
-#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
-#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
-#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
-
-#define ADC_JSQR_JSQ1_Pos (9U)
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
-
-#define ADC_JSQR_JSQ2_Pos (15U)
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JSQ3_Pos (21U)
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
-
-#define ADC_JSQR_JSQ4_Pos (27U)
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_OFR1 register ********************/
-#define ADC_OFR1_OFFSET1_Pos (0U)
-#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
-#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
-#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
-#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
-#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
-#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
-#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
-#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
-#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
-#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
-#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
-#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
-#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
-#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
-#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
-#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
-#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
-#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
-#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
-#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
-#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
-#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
-#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
-#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
-#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
-#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
-#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR1_OFFSET1_CH_Pos (26U)
-#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
-#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR1_SSATE_Pos (31U)
-#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR2 register ********************/
-#define ADC_OFR2_OFFSET2_Pos (0U)
-#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
-#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
-#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
-#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
-#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
-#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
-#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
-#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
-#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
-#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
-#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
-#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
-#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
-#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
-#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
-#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
-#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
-#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
-#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
-#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
-#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
-#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
-#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
-#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
-#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
-#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
-#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR2_OFFSET2_CH_Pos (26U)
-#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
-#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR2_SSATE_Pos (31U)
-#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR3 register ********************/
-#define ADC_OFR3_OFFSET3_Pos (0U)
-#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
-#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
-#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
-#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
-#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
-#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
-#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
-#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
-#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
-#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
-#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
-#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
-#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
-#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
-#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
-#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
-#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
-#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
-#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
-#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
-#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
-#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
-#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
-#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
-#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
-#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
-#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR3_OFFSET3_CH_Pos (26U)
-#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
-#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR3_SSATE_Pos (31U)
-#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_OFR4 register ********************/
-#define ADC_OFR4_OFFSET4_Pos (0U)
-#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
-#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
-#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
-#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
-#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
-#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
-#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
-#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
-#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
-#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
-#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
-#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
-#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
-#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
-#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
-#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
-#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
-#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
-#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
-#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
-#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
-#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
-#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
-#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
-#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
-#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
-#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
-#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
-
-#define ADC_OFR4_OFFSET4_CH_Pos (26U)
-#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
-#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
-#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
-#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
-#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
-#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
-#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
-
-#define ADC_OFR4_SSATE_Pos (31U)
-#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
-#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
-
-/******************** Bit definition for ADC_JDR1 register ********************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR1_JDATA_0 (0x00000001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR1_JDATA_1 (0x00000002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR1_JDATA_2 (0x00000004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR1_JDATA_3 (0x00000008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR1_JDATA_4 (0x00000010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR1_JDATA_5 (0x00000020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR1_JDATA_6 (0x00000040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR1_JDATA_7 (0x00000080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR1_JDATA_8 (0x00000100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR1_JDATA_9 (0x00000200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR1_JDATA_10 (0x00000400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR1_JDATA_11 (0x00000800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR1_JDATA_12 (0x00001000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR1_JDATA_13 (0x00002000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR1_JDATA_14 (0x00004000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR1_JDATA_15 (0x00008000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR1_JDATA_16 (0x00010000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR1_JDATA_17 (0x00020000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR1_JDATA_18 (0x00040000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR1_JDATA_19 (0x00080000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR1_JDATA_20 (0x00100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR1_JDATA_21 (0x00200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR1_JDATA_22 (0x00400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR1_JDATA_23 (0x00800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR1_JDATA_24 (0x01000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR1_JDATA_25 (0x02000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR1_JDATA_26 (0x04000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR1_JDATA_27 (0x08000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR2 register ********************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR2_JDATA_0 (0x00000001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR2_JDATA_1 (0x00000002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR2_JDATA_2 (0x00000004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR2_JDATA_3 (0x00000008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR2_JDATA_4 (0x00000010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR2_JDATA_5 (0x00000020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR2_JDATA_6 (0x00000040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR2_JDATA_7 (0x00000080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR2_JDATA_8 (0x00000100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR2_JDATA_9 (0x00000200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR2_JDATA_10 (0x00000400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR2_JDATA_11 (0x00000800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR2_JDATA_12 (0x00001000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR2_JDATA_13 (0x00002000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR2_JDATA_14 (0x00004000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR2_JDATA_15 (0x00008000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR2_JDATA_16 (0x00010000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR2_JDATA_17 (0x00020000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR2_JDATA_18 (0x00040000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR2_JDATA_19 (0x00080000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR2_JDATA_20 (0x00100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR2_JDATA_21 (0x00200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR2_JDATA_22 (0x00400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR2_JDATA_23 (0x00800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR2_JDATA_24 (0x01000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR2_JDATA_25 (0x02000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR2_JDATA_26 (0x04000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR2_JDATA_27 (0x08000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR3 register ********************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR3_JDATA_0 (0x00000001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR3_JDATA_1 (0x00000002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR3_JDATA_2 (0x00000004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR3_JDATA_3 (0x00000008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR3_JDATA_4 (0x00000010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR3_JDATA_5 (0x00000020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR3_JDATA_6 (0x00000040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR3_JDATA_7 (0x00000080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR3_JDATA_8 (0x00000100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR3_JDATA_9 (0x00000200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR3_JDATA_10 (0x00000400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR3_JDATA_11 (0x00000800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR3_JDATA_12 (0x00001000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR3_JDATA_13 (0x00002000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR3_JDATA_14 (0x00004000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR3_JDATA_15 (0x00008000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR3_JDATA_16 (0x00010000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR3_JDATA_17 (0x00020000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR3_JDATA_18 (0x00040000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR3_JDATA_19 (0x00080000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR3_JDATA_20 (0x00100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR3_JDATA_21 (0x00200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR3_JDATA_22 (0x00400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR3_JDATA_23 (0x00800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR3_JDATA_24 (0x01000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR3_JDATA_25 (0x02000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR3_JDATA_26 (0x04000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR3_JDATA_27 (0x08000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_JDR4 register ********************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
-#define ADC_JDR4_JDATA_0 (0x00000001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
-#define ADC_JDR4_JDATA_1 (0x00000002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
-#define ADC_JDR4_JDATA_2 (0x00000004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
-#define ADC_JDR4_JDATA_3 (0x00000008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
-#define ADC_JDR4_JDATA_4 (0x00000010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
-#define ADC_JDR4_JDATA_5 (0x00000020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
-#define ADC_JDR4_JDATA_6 (0x00000040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
-#define ADC_JDR4_JDATA_7 (0x00000080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
-#define ADC_JDR4_JDATA_8 (0x00000100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
-#define ADC_JDR4_JDATA_9 (0x00000200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
-#define ADC_JDR4_JDATA_10 (0x00000400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
-#define ADC_JDR4_JDATA_11 (0x00000800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
-#define ADC_JDR4_JDATA_12 (0x00001000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
-#define ADC_JDR4_JDATA_13 (0x00002000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
-#define ADC_JDR4_JDATA_14 (0x00004000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
-#define ADC_JDR4_JDATA_15 (0x00008000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
-#define ADC_JDR4_JDATA_16 (0x00010000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
-#define ADC_JDR4_JDATA_17 (0x00020000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
-#define ADC_JDR4_JDATA_18 (0x00040000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
-#define ADC_JDR4_JDATA_19 (0x00080000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
-#define ADC_JDR4_JDATA_20 (0x00100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
-#define ADC_JDR4_JDATA_21 (0x00200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
-#define ADC_JDR4_JDATA_22 (0x00400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
-#define ADC_JDR4_JDATA_23 (0x00800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
-#define ADC_JDR4_JDATA_24 (0x01000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
-#define ADC_JDR4_JDATA_25 (0x02000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
-#define ADC_JDR4_JDATA_26 (0x04000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
-#define ADC_JDR4_JDATA_27 (0x08000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
-#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
-#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
-#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
-#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_AWD2CR register ********************/
-#define ADC_AWD2CR_AWD2CH_Pos (0U)
-#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_AWD3CR register ********************/
-#define ADC_AWD3CR_AWD3CH_Pos (0U)
-#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
-#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
-#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
-#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
-#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_DIFSEL register ********************/
-#define ADC_DIFSEL_DIFSEL_Pos (0U)
-#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
-#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
-#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
-#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
-#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
-#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
-#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
-#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
-#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
-#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
-#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
-#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
-#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
-#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
-#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
-#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
-#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
-#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
-#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
-#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
-#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
-#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
-
-/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT_S_Pos (0U)
-#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
-#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
-#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT_CALFACT_D_Pos (16U)
-#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
-#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
-#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
-
-/******************** Bit definition for ADC_CALFACT2 register ********************/
-#define ADC_CALFACT2_LINCALFACT_Pos (0U)
-#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
-#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
-#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
-#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
-#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
-#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
-#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
-#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
-#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
-#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
-#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
-#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
-#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
-#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
-#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
-#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
-#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
-#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
-#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
-#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
-#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
-#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
-#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
-#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
-#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
-#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
-#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
-#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
-#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
-#define ADC_CALFACT2_LINCALFACT_27 (0x08000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
-#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
-#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
-
-/************************* ADC Common registers *****************************/
-/******************** Bit definition for ADC_CSR register ********************/
-#define ADC123_CSR_ADRDY_MST_Pos (0U)
-#define ADC123_CSR_ADRDY_MST_Msk (0x1U << ADC123_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CSR_ADRDY_MST ADC123_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
-#define ADC123_CSR_EOSMP_MST_Pos (1U)
-#define ADC123_CSR_EOSMP_MST_Msk (0x1U << ADC123_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CSR_EOSMP_MST ADC123_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
-#define ADC123_CSR_EOC_MST_Pos (2U)
-#define ADC123_CSR_EOC_MST_Msk (0x1U << ADC123_CSR_EOC_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CSR_EOC_MST ADC123_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
-#define ADC123_CSR_EOS_MST_Pos (3U)
-#define ADC123_CSR_EOS_MST_Msk (0x1U << ADC123_CSR_EOS_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CSR_EOS_MST ADC123_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
-#define ADC123_CSR_OVR_MST_Pos (4U)
-#define ADC123_CSR_OVR_MST_Msk (0x1U << ADC123_CSR_OVR_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CSR_OVR_MST ADC123_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
-#define ADC123_CSR_JEOC_MST_Pos (5U)
-#define ADC123_CSR_JEOC_MST_Msk (0x1U << ADC123_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CSR_JEOC_MST ADC123_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
-#define ADC123_CSR_JEOS_MST_Pos (6U)
-#define ADC123_CSR_JEOS_MST_Msk (0x1U << ADC123_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CSR_JEOS_MST ADC123_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
-#define ADC123_CSR_AWD1_MST_Pos (7U)
-#define ADC123_CSR_AWD1_MST_Msk (0x1U << ADC123_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CSR_AWD1_MST ADC123_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
-#define ADC123_CSR_AWD2_MST_Pos (8U)
-#define ADC123_CSR_AWD2_MST_Msk (0x1U << ADC123_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CSR_AWD2_MST ADC123_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
-#define ADC123_CSR_AWD3_MST_Pos (9U)
-#define ADC123_CSR_AWD3_MST_Msk (0x1U << ADC123_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CSR_AWD3_MST ADC123_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
-#define ADC123_CSR_JQOVF_MST_Pos (10U)
-#define ADC123_CSR_JQOVF_MST_Msk (0x1U << ADC123_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CSR_JQOVF_MST ADC123_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
-#define ADC123_CSR_ADRDY_SLV_Pos (16U)
-#define ADC123_CSR_ADRDY_SLV_Msk (0x1U << ADC123_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CSR_ADRDY_SLV ADC123_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
-#define ADC123_CSR_EOSMP_SLV_Pos (17U)
-#define ADC123_CSR_EOSMP_SLV_Msk (0x1U << ADC123_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CSR_EOSMP_SLV ADC123_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
-#define ADC123_CSR_EOC_SLV_Pos (18U)
-#define ADC123_CSR_EOC_SLV_Msk (0x1U << ADC123_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CSR_EOC_SLV ADC123_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
-#define ADC123_CSR_EOS_SLV_Pos (19U)
-#define ADC123_CSR_EOS_SLV_Msk (0x1U << ADC123_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CSR_EOS_SLV ADC123_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
-#define ADC123_CSR_OVR_SLV_Pos (20U)
-#define ADC123_CSR_OVR_SLV_Msk (0x1U << ADC123_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CSR_OVR_SLV ADC123_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
-#define ADC123_CSR_JEOC_SLV_Pos (21U)
-#define ADC123_CSR_JEOC_SLV_Msk (0x1U << ADC123_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CSR_JEOC_SLV ADC123_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
-#define ADC123_CSR_JEOS_SLV_Pos (22U)
-#define ADC123_CSR_JEOS_SLV_Msk (0x1U << ADC123_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CSR_JEOS_SLV ADC123_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
-#define ADC123_CSR_AWD1_SLV_Pos (23U)
-#define ADC123_CSR_AWD1_SLV_Msk (0x1U << ADC123_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CSR_AWD1_SLV ADC123_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
-#define ADC123_CSR_AWD2_SLV_Pos (24U)
-#define ADC123_CSR_AWD2_SLV_Msk (0x1U << ADC123_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CSR_AWD2_SLV ADC123_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
-#define ADC123_CSR_AWD3_SLV_Pos (25U)
-#define ADC123_CSR_AWD3_SLV_Msk (0x1U << ADC123_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CSR_AWD3_SLV ADC123_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
-#define ADC123_CSR_JQOVF_SLV_Pos (26U)
-#define ADC123_CSR_JQOVF_SLV_Msk (0x1U << ADC123_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CSR_JQOVF_SLV ADC123_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
-
-/******************** Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_DUAL_Pos (0U)
-#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
-#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
-#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
-#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
-#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
-#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
-#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
-
-#define ADC_CCR_DELAY_Pos (8U)
-#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
-#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
-#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
-#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
-#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
-#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
-
-
-#define ADC_CCR_DAMDF_Pos (14U)
-#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
-#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
-#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
-#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
-
-#define ADC_CCR_CKMODE_Pos (16U)
-#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
-#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
-#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
-#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
-
-#define ADC_CCR_PRESC_Pos (18U)
-#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
-#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
-#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos (22U)
-#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
-#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
-#define ADC_CCR_TSEN_Pos (23U)
-#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
-#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos (24U)
-#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
-#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
-
-/******************** Bit definition for ADC_CDR register ********************/
-#define ADC123_CDR_RDATA_MST_Pos (0U)
-#define ADC123_CDR_RDATA_MST_Msk (0xFFFFU << ADC123_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
-#define ADC123_CDR_RDATA_MST ADC123_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_MST_0 (0x0001U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
-#define ADC123_CDR_RDATA_MST_1 (0x0002U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
-#define ADC123_CDR_RDATA_MST_2 (0x0004U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
-#define ADC123_CDR_RDATA_MST_3 (0x0008U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
-#define ADC123_CDR_RDATA_MST_4 (0x0010U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
-#define ADC123_CDR_RDATA_MST_5 (0x0020U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
-#define ADC123_CDR_RDATA_MST_6 (0x0040U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
-#define ADC123_CDR_RDATA_MST_7 (0x0080U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
-#define ADC123_CDR_RDATA_MST_8 (0x0100U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
-#define ADC123_CDR_RDATA_MST_9 (0x0200U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
-#define ADC123_CDR_RDATA_MST_10 (0x0400U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
-#define ADC123_CDR_RDATA_MST_11 (0x0800U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
-#define ADC123_CDR_RDATA_MST_12 (0x1000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
-#define ADC123_CDR_RDATA_MST_13 (0x2000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
-#define ADC123_CDR_RDATA_MST_14 (0x4000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
-#define ADC123_CDR_RDATA_MST_15 (0x8000U << ADC123_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
-
-#define ADC123_CDR_RDATA_SLV_Pos (16U)
-#define ADC123_CDR_RDATA_SLV_Msk (0xFFFFU << ADC123_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
-#define ADC123_CDR_RDATA_SLV ADC123_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
-#define ADC123_CDR_RDATA_SLV_0 (0x0001U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
-#define ADC123_CDR_RDATA_SLV_1 (0x0002U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
-#define ADC123_CDR_RDATA_SLV_2 (0x0004U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
-#define ADC123_CDR_RDATA_SLV_3 (0x0008U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
-#define ADC123_CDR_RDATA_SLV_4 (0x0010U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
-#define ADC123_CDR_RDATA_SLV_5 (0x0020U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
-#define ADC123_CDR_RDATA_SLV_6 (0x0040U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
-#define ADC123_CDR_RDATA_SLV_7 (0x0080U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
-#define ADC123_CDR_RDATA_SLV_8 (0x0100U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
-#define ADC123_CDR_RDATA_SLV_9 (0x0200U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
-#define ADC123_CDR_RDATA_SLV_10 (0x0400U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
-#define ADC123_CDR_RDATA_SLV_11 (0x0800U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
-#define ADC123_CDR_RDATA_SLV_12 (0x1000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
-#define ADC123_CDR_RDATA_SLV_13 (0x2000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
-#define ADC123_CDR_RDATA_SLV_14 (0x4000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
-#define ADC123_CDR_RDATA_SLV_15 (0x8000U << ADC123_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
-
-/******************** Bit definition for ADC_CDR2 register ********************/
-#define ADC123_CDR2_RDATA_ALT_Pos (0U)
-#define ADC123_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
-#define ADC123_CDR2_RDATA_ALT ADC123_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
-#define ADC123_CDR2_RDATA_ALT_0 (0x00000001U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
-#define ADC123_CDR2_RDATA_ALT_1 (0x00000002U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
-#define ADC123_CDR2_RDATA_ALT_2 (0x00000004U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
-#define ADC123_CDR2_RDATA_ALT_3 (0x00000008U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
-#define ADC123_CDR2_RDATA_ALT_4 (0x00000010U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
-#define ADC123_CDR2_RDATA_ALT_5 (0x00000020U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
-#define ADC123_CDR2_RDATA_ALT_6 (0x00000040U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
-#define ADC123_CDR2_RDATA_ALT_7 (0x00000080U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
-#define ADC123_CDR2_RDATA_ALT_8 (0x00000100U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
-#define ADC123_CDR2_RDATA_ALT_9 (0x00000200U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
-#define ADC123_CDR2_RDATA_ALT_10 (0x00000400U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
-#define ADC123_CDR2_RDATA_ALT_11 (0x00000800U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
-#define ADC123_CDR2_RDATA_ALT_12 (0x00001000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
-#define ADC123_CDR2_RDATA_ALT_13 (0x00002000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
-#define ADC123_CDR2_RDATA_ALT_14 (0x00004000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
-#define ADC123_CDR2_RDATA_ALT_15 (0x00008000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
-#define ADC123_CDR2_RDATA_ALT_16 (0x00010000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
-#define ADC123_CDR2_RDATA_ALT_17 (0x00020000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
-#define ADC123_CDR2_RDATA_ALT_18 (0x00040000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
-#define ADC123_CDR2_RDATA_ALT_19 (0x00080000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
-#define ADC123_CDR2_RDATA_ALT_20 (0x00100000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
-#define ADC123_CDR2_RDATA_ALT_21 (0x00200000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
-#define ADC123_CDR2_RDATA_ALT_22 (0x00400000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
-#define ADC123_CDR2_RDATA_ALT_23 (0x00800000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
-#define ADC123_CDR2_RDATA_ALT_24 (0x01000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
-#define ADC123_CDR2_RDATA_ALT_25 (0x02000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
-#define ADC123_CDR2_RDATA_ALT_26 (0x04000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
-#define ADC123_CDR2_RDATA_ALT_27 (0x08000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
-#define ADC123_CDR2_RDATA_ALT_28 (0x10000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
-#define ADC123_CDR2_RDATA_ALT_29 (0x20000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
-#define ADC123_CDR2_RDATA_ALT_30 (0x40000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
-#define ADC123_CDR2_RDATA_ALT_31 (0x80000000U << ADC123_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
-
-/******************************************************************************/
-/* */
-/* VREFBUF */
-/* */
-/******************************************************************************/
-/******************* Bit definition for VREFBUF_CSR register ****************/
-#define VREFBUF_CSR_ENVR_Pos (0U)
-#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/
-#define DAC_CR_CEN1_Pos (14U)
-#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
-#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
-
-#define DAC_CR_EN2_Pos (16U)
-#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
-#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
-#define DAC_CR_CEN2_Pos (30U)
-#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
-#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1MB */
-
-#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB */
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32H753xx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
deleted file mode 100644
index 1a454b5..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx.h
- * @author MCD Application Team
- * @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The STM32H7xx device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_HAL_DRIVER"
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx
- * @{
- */
-
-#ifndef STM32H7xx_H
-#define STM32H7xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined (STM32H7)
-#define STM32H7
-#endif /* STM32H7 */
-
-
-/* Uncomment the line below according to the target STM32H7 device used in your
- application
- */
-
-#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx)
- /* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI Devices */
- /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753II, STM32H753BI, STM32H753XI Devices */
- /* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-#if !defined (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V1.3.0
- */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
- |(__CMSIS_DEVICE_HAL_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32H743xx)
- #include "stm32h743xx.h"
-#elif defined(STM32H753xx)
- #include "stm32h753xx.h"
-#elif defined(STM32H750xx)
- #include "stm32h750xx.h"
-#else
- #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum
-{
- RESET = 0,
- SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
- DISABLE = 0,
- ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
- ERROR = 0,
- SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
- * @}
- */
-
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-
-/**
- * @}
- */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32h7xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* STM32H7xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
deleted file mode 100644
index c22d942..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.h
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef SYSTEM_STM32H7XX_H
-#define SYSTEM_STM32H7XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32H7xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32H7xx_System_Exported_types
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
-extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
-extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_STM32H7XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s
deleted file mode 100644
index f28305a..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s
+++ /dev/null
@@ -1,612 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32h743xx.s
-;* @author MCD Application Team
-;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_AVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT FDCAN1_IT0_IRQHandler [WEAK]
- EXPORT FDCAN2_IT0_IRQHandler [WEAK]
- EXPORT FDCAN1_IT1_IRQHandler [WEAK]
- EXPORT FDCAN2_IT1_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDMMC1_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT FDCAN_CAL_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
- EXPORT SAI2_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT I2C4_EV_IRQHandler [WEAK]
- EXPORT I2C4_ER_IRQHandler [WEAK]
- EXPORT SPDIF_RX_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT HRTIM1_Master_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
- EXPORT HRTIM1_TIME_IRQHandler [WEAK]
- EXPORT HRTIM1_FLT_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
- EXPORT SAI3_IRQHandler [WEAK]
- EXPORT SWPMI1_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT MDIOS_WKUP_IRQHandler [WEAK]
- EXPORT MDIOS_IRQHandler [WEAK]
- EXPORT JPEG_IRQHandler [WEAK]
- EXPORT MDMA_IRQHandler [WEAK]
- EXPORT SDMMC2_IRQHandler [WEAK]
- EXPORT HSEM1_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
- EXPORT BDMA_Channel0_IRQHandler [WEAK]
- EXPORT BDMA_Channel1_IRQHandler [WEAK]
- EXPORT BDMA_Channel2_IRQHandler [WEAK]
- EXPORT BDMA_Channel3_IRQHandler [WEAK]
- EXPORT BDMA_Channel4_IRQHandler [WEAK]
- EXPORT BDMA_Channel5_IRQHandler [WEAK]
- EXPORT BDMA_Channel6_IRQHandler [WEAK]
- EXPORT BDMA_Channel7_IRQHandler [WEAK]
- EXPORT COMP1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT LPTIM3_IRQHandler [WEAK]
- EXPORT LPTIM4_IRQHandler [WEAK]
- EXPORT LPTIM5_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT CRS_IRQHandler [WEAK]
- EXPORT SAI4_IRQHandler [WEAK]
- EXPORT WAKEUP_PIN_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_AVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-FDCAN1_IT0_IRQHandler
-FDCAN2_IT0_IRQHandler
-FDCAN1_IT1_IRQHandler
-FDCAN2_IT1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDMMC1_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-FDCAN_CAL_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
-SAI2_IRQHandler
-QUADSPI_IRQHandler
-LPTIM1_IRQHandler
-CEC_IRQHandler
-I2C4_EV_IRQHandler
-I2C4_ER_IRQHandler
-SPDIF_RX_IRQHandler
-OTG_FS_EP1_OUT_IRQHandler
-OTG_FS_EP1_IN_IRQHandler
-OTG_FS_WKUP_IRQHandler
-OTG_FS_IRQHandler
-DMAMUX1_OVR_IRQHandler
-HRTIM1_Master_IRQHandler
-HRTIM1_TIMA_IRQHandler
-HRTIM1_TIMB_IRQHandler
-HRTIM1_TIMC_IRQHandler
-HRTIM1_TIMD_IRQHandler
-HRTIM1_TIME_IRQHandler
-HRTIM1_FLT_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-DFSDM1_FLT2_IRQHandler
-DFSDM1_FLT3_IRQHandler
-SAI3_IRQHandler
-SWPMI1_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-MDIOS_WKUP_IRQHandler
-MDIOS_IRQHandler
-JPEG_IRQHandler
-MDMA_IRQHandler
-SDMMC2_IRQHandler
-HSEM1_IRQHandler
-ADC3_IRQHandler
-DMAMUX2_OVR_IRQHandler
-BDMA_Channel0_IRQHandler
-BDMA_Channel1_IRQHandler
-BDMA_Channel2_IRQHandler
-BDMA_Channel3_IRQHandler
-BDMA_Channel4_IRQHandler
-BDMA_Channel5_IRQHandler
-BDMA_Channel6_IRQHandler
-BDMA_Channel7_IRQHandler
-COMP1_IRQHandler
-LPTIM2_IRQHandler
-LPTIM3_IRQHandler
-LPTIM4_IRQHandler
-LPTIM5_IRQHandler
-LPUART1_IRQHandler
-CRS_IRQHandler
-SAI4_IRQHandler
-WAKEUP_PIN_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s
deleted file mode 100644
index 1116b4e..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s
+++ /dev/null
@@ -1,614 +0,0 @@
-;******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
-;* File Name : startup_stm32h750xx.s
-;* @author MCD Application Team
-;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_AVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT FDCAN1_IT0_IRQHandler [WEAK]
- EXPORT FDCAN2_IT0_IRQHandler [WEAK]
- EXPORT FDCAN1_IT1_IRQHandler [WEAK]
- EXPORT FDCAN2_IT1_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDMMC1_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT FDCAN_CAL_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
- EXPORT SAI2_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT I2C4_EV_IRQHandler [WEAK]
- EXPORT I2C4_ER_IRQHandler [WEAK]
- EXPORT SPDIF_RX_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT HRTIM1_Master_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
- EXPORT HRTIM1_TIME_IRQHandler [WEAK]
- EXPORT HRTIM1_FLT_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
- EXPORT SAI3_IRQHandler [WEAK]
- EXPORT SWPMI1_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT MDIOS_WKUP_IRQHandler [WEAK]
- EXPORT MDIOS_IRQHandler [WEAK]
- EXPORT JPEG_IRQHandler [WEAK]
- EXPORT MDMA_IRQHandler [WEAK]
- EXPORT SDMMC2_IRQHandler [WEAK]
- EXPORT HSEM1_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
- EXPORT BDMA_Channel0_IRQHandler [WEAK]
- EXPORT BDMA_Channel1_IRQHandler [WEAK]
- EXPORT BDMA_Channel2_IRQHandler [WEAK]
- EXPORT BDMA_Channel3_IRQHandler [WEAK]
- EXPORT BDMA_Channel4_IRQHandler [WEAK]
- EXPORT BDMA_Channel5_IRQHandler [WEAK]
- EXPORT BDMA_Channel6_IRQHandler [WEAK]
- EXPORT BDMA_Channel7_IRQHandler [WEAK]
- EXPORT COMP1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT LPTIM3_IRQHandler [WEAK]
- EXPORT LPTIM4_IRQHandler [WEAK]
- EXPORT LPTIM5_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT CRS_IRQHandler [WEAK]
- EXPORT SAI4_IRQHandler [WEAK]
- EXPORT WAKEUP_PIN_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_AVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-FDCAN1_IT0_IRQHandler
-FDCAN2_IT0_IRQHandler
-FDCAN1_IT1_IRQHandler
-FDCAN2_IT1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDMMC1_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-FDCAN_CAL_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
-SAI2_IRQHandler
-QUADSPI_IRQHandler
-LPTIM1_IRQHandler
-CEC_IRQHandler
-I2C4_EV_IRQHandler
-I2C4_ER_IRQHandler
-SPDIF_RX_IRQHandler
-OTG_FS_EP1_OUT_IRQHandler
-OTG_FS_EP1_IN_IRQHandler
-OTG_FS_WKUP_IRQHandler
-OTG_FS_IRQHandler
-DMAMUX1_OVR_IRQHandler
-HRTIM1_Master_IRQHandler
-HRTIM1_TIMA_IRQHandler
-HRTIM1_TIMB_IRQHandler
-HRTIM1_TIMC_IRQHandler
-HRTIM1_TIMD_IRQHandler
-HRTIM1_TIME_IRQHandler
-HRTIM1_FLT_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-DFSDM1_FLT2_IRQHandler
-DFSDM1_FLT3_IRQHandler
-SAI3_IRQHandler
-SWPMI1_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-MDIOS_WKUP_IRQHandler
-MDIOS_IRQHandler
-JPEG_IRQHandler
-MDMA_IRQHandler
-SDMMC2_IRQHandler
-HSEM1_IRQHandler
-ADC3_IRQHandler
-DMAMUX2_OVR_IRQHandler
-BDMA_Channel0_IRQHandler
-BDMA_Channel1_IRQHandler
-BDMA_Channel2_IRQHandler
-BDMA_Channel3_IRQHandler
-BDMA_Channel4_IRQHandler
-BDMA_Channel5_IRQHandler
-BDMA_Channel6_IRQHandler
-BDMA_Channel7_IRQHandler
-COMP1_IRQHandler
-LPTIM2_IRQHandler
-LPTIM3_IRQHandler
-LPTIM4_IRQHandler
-LPTIM5_IRQHandler
-LPUART1_IRQHandler
-CRS_IRQHandler
-SAI4_IRQHandler
-WAKEUP_PIN_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s
deleted file mode 100644
index efd1a7a..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s
+++ /dev/null
@@ -1,614 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32h753xx.s
-;* @author MCD Application Team
-;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_AVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Stream0_IRQHandler [WEAK]
- EXPORT DMA1_Stream1_IRQHandler [WEAK]
- EXPORT DMA1_Stream2_IRQHandler [WEAK]
- EXPORT DMA1_Stream3_IRQHandler [WEAK]
- EXPORT DMA1_Stream4_IRQHandler [WEAK]
- EXPORT DMA1_Stream5_IRQHandler [WEAK]
- EXPORT DMA1_Stream6_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT FDCAN1_IT0_IRQHandler [WEAK]
- EXPORT FDCAN2_IT0_IRQHandler [WEAK]
- EXPORT FDCAN1_IT1_IRQHandler [WEAK]
- EXPORT FDCAN2_IT1_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_IRQHandler [WEAK]
- EXPORT TIM1_UP_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
- EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT DMA1_Stream7_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SDMMC1_IRQHandler [WEAK]
- EXPORT TIM5_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Stream0_IRQHandler [WEAK]
- EXPORT DMA2_Stream1_IRQHandler [WEAK]
- EXPORT DMA2_Stream2_IRQHandler [WEAK]
- EXPORT DMA2_Stream3_IRQHandler [WEAK]
- EXPORT DMA2_Stream4_IRQHandler [WEAK]
- EXPORT ETH_IRQHandler [WEAK]
- EXPORT ETH_WKUP_IRQHandler [WEAK]
- EXPORT FDCAN_CAL_IRQHandler [WEAK]
- EXPORT DMA2_Stream5_IRQHandler [WEAK]
- EXPORT DMA2_Stream6_IRQHandler [WEAK]
- EXPORT DMA2_Stream7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_HS_IRQHandler [WEAK]
- EXPORT DCMI_IRQHandler [WEAK]
- EXPORT CRYP_IRQHandler [WEAK]
- EXPORT HASH_RNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT SPI6_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT LTDC_IRQHandler [WEAK]
- EXPORT LTDC_ER_IRQHandler [WEAK]
- EXPORT DMA2D_IRQHandler [WEAK]
- EXPORT SAI2_IRQHandler [WEAK]
- EXPORT QUADSPI_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT I2C4_EV_IRQHandler [WEAK]
- EXPORT I2C4_ER_IRQHandler [WEAK]
- EXPORT SPDIF_RX_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
- EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
- EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
- EXPORT OTG_FS_IRQHandler [WEAK]
- EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT HRTIM1_Master_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
- EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
- EXPORT HRTIM1_TIME_IRQHandler [WEAK]
- EXPORT HRTIM1_FLT_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
- EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
- EXPORT SAI3_IRQHandler [WEAK]
- EXPORT SWPMI1_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT MDIOS_WKUP_IRQHandler [WEAK]
- EXPORT MDIOS_IRQHandler [WEAK]
- EXPORT JPEG_IRQHandler [WEAK]
- EXPORT MDMA_IRQHandler [WEAK]
- EXPORT SDMMC2_IRQHandler [WEAK]
- EXPORT HSEM1_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
- EXPORT BDMA_Channel0_IRQHandler [WEAK]
- EXPORT BDMA_Channel1_IRQHandler [WEAK]
- EXPORT BDMA_Channel2_IRQHandler [WEAK]
- EXPORT BDMA_Channel3_IRQHandler [WEAK]
- EXPORT BDMA_Channel4_IRQHandler [WEAK]
- EXPORT BDMA_Channel5_IRQHandler [WEAK]
- EXPORT BDMA_Channel6_IRQHandler [WEAK]
- EXPORT BDMA_Channel7_IRQHandler [WEAK]
- EXPORT COMP1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT LPTIM3_IRQHandler [WEAK]
- EXPORT LPTIM4_IRQHandler [WEAK]
- EXPORT LPTIM5_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT CRS_IRQHandler [WEAK]
- EXPORT SAI4_IRQHandler [WEAK]
- EXPORT WAKEUP_PIN_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_AVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Stream0_IRQHandler
-DMA1_Stream1_IRQHandler
-DMA1_Stream2_IRQHandler
-DMA1_Stream3_IRQHandler
-DMA1_Stream4_IRQHandler
-DMA1_Stream5_IRQHandler
-DMA1_Stream6_IRQHandler
-ADC_IRQHandler
-FDCAN1_IT0_IRQHandler
-FDCAN2_IT0_IRQHandler
-FDCAN1_IT1_IRQHandler
-FDCAN2_IT1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-DMA1_Stream7_IRQHandler
-FMC_IRQHandler
-SDMMC1_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Stream0_IRQHandler
-DMA2_Stream1_IRQHandler
-DMA2_Stream2_IRQHandler
-DMA2_Stream3_IRQHandler
-DMA2_Stream4_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-FDCAN_CAL_IRQHandler
-DMA2_Stream5_IRQHandler
-DMA2_Stream6_IRQHandler
-DMA2_Stream7_IRQHandler
-USART6_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-OTG_HS_EP1_OUT_IRQHandler
-OTG_HS_EP1_IN_IRQHandler
-OTG_HS_WKUP_IRQHandler
-OTG_HS_IRQHandler
-DCMI_IRQHandler
-CRYP_IRQHandler
-HASH_RNG_IRQHandler
-FPU_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-SPI6_IRQHandler
-SAI1_IRQHandler
-LTDC_IRQHandler
-LTDC_ER_IRQHandler
-DMA2D_IRQHandler
-SAI2_IRQHandler
-QUADSPI_IRQHandler
-LPTIM1_IRQHandler
-CEC_IRQHandler
-I2C4_EV_IRQHandler
-I2C4_ER_IRQHandler
-SPDIF_RX_IRQHandler
-OTG_FS_EP1_OUT_IRQHandler
-OTG_FS_EP1_IN_IRQHandler
-OTG_FS_WKUP_IRQHandler
-OTG_FS_IRQHandler
-DMAMUX1_OVR_IRQHandler
-HRTIM1_Master_IRQHandler
-HRTIM1_TIMA_IRQHandler
-HRTIM1_TIMB_IRQHandler
-HRTIM1_TIMC_IRQHandler
-HRTIM1_TIMD_IRQHandler
-HRTIM1_TIME_IRQHandler
-HRTIM1_FLT_IRQHandler
-DFSDM1_FLT0_IRQHandler
-DFSDM1_FLT1_IRQHandler
-DFSDM1_FLT2_IRQHandler
-DFSDM1_FLT3_IRQHandler
-SAI3_IRQHandler
-SWPMI1_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-MDIOS_WKUP_IRQHandler
-MDIOS_IRQHandler
-JPEG_IRQHandler
-MDMA_IRQHandler
-SDMMC2_IRQHandler
-HSEM1_IRQHandler
-ADC3_IRQHandler
-DMAMUX2_OVR_IRQHandler
-BDMA_Channel0_IRQHandler
-BDMA_Channel1_IRQHandler
-BDMA_Channel2_IRQHandler
-BDMA_Channel3_IRQHandler
-BDMA_Channel4_IRQHandler
-BDMA_Channel5_IRQHandler
-BDMA_Channel6_IRQHandler
-BDMA_Channel7_IRQHandler
-COMP1_IRQHandler
-LPTIM2_IRQHandler
-LPTIM3_IRQHandler
-LPTIM4_IRQHandler
-LPTIM5_IRQHandler
-LPUART1_IRQHandler
-CRS_IRQHandler
-SAI4_IRQHandler
-WAKEUP_PIN_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s
deleted file mode 100644
index cfb7ee1..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32h743xx.s
- * @author MCD Application Team
- * @brief STM32H743xx Devices vector table for GCC based toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m7
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
- .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word 0 /* Reserved */
- .word RNG_IRQHandler /* Rng */
- .word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
- .word UART8_IRQHandler /* UART8 */
- .word SPI4_IRQHandler /* SPI4 */
- .word SPI5_IRQHandler /* SPI5 */
- .word SPI6_IRQHandler /* SPI6 */
- .word SAI1_IRQHandler /* SAI1 */
- .word LTDC_IRQHandler /* LTDC */
- .word LTDC_ER_IRQHandler /* LTDC error */
- .word DMA2D_IRQHandler /* DMA2D */
- .word SAI2_IRQHandler /* SAI2 */
- .word QUADSPI_IRQHandler /* QUADSPI */
- .word LPTIM1_IRQHandler /* LPTIM1 */
- .word CEC_IRQHandler /* HDMI_CEC */
- .word I2C4_EV_IRQHandler /* I2C4 Event */
- .word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
- .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
- .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
- .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
- .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
- .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
- .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
- .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
- .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
- .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word SAI3_IRQHandler /* SAI3 global Interrupt */
- .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word JPEG_IRQHandler /* JPEG global Interrupt */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
- .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word 0 /* Reserved */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
- .thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
- .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
- .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
- .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
- .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
- .thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak RNG_IRQHandler
- .thumb_set RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
- .thumb_set LTDC_IRQHandler,Default_Handler
-
- .weak LTDC_ER_IRQHandler
- .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
- .weak DMA2D_IRQHandler
- .thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak SAI2_IRQHandler
- .thumb_set SAI2_IRQHandler,Default_Handler
-
- .weak QUADSPI_IRQHandler
- .thumb_set QUADSPI_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
- .thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
- .thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_OUT_IRQHandler
- .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_IN_IRQHandler
- .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak HRTIM1_Master_IRQHandler
- .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMA_IRQHandler
- .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMB_IRQHandler
- .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMC_IRQHandler
- .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMD_IRQHandler
- .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIME_IRQHandler
- .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
-
- .weak HRTIM1_FLT_IRQHandler
- .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT3_IRQHandler
- .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SAI3_IRQHandler
- .thumb_set SAI3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
- .thumb_set SWPMI1_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
-
- .weak MDIOS_IRQHandler
- .thumb_set MDIOS_IRQHandler,Default_Handler
-
- .weak JPEG_IRQHandler
- .thumb_set JPEG_IRQHandler,Default_Handler
-
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
-
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
- .thumb_set HSEM1_IRQHandler,Default_Handler
-
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
-
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
-
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
-
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
-
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
-
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
-
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
-
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
-
- .weak BDMA_Channel6_IRQHandler
- .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
-
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
-
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
-
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
-
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
-
- .weak SAI4_IRQHandler
- .thumb_set SAI4_IRQHandler,Default_Handler
-
- .weak WAKEUP_PIN_IRQHandler
- .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s
deleted file mode 100644
index 9ce1160..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s
+++ /dev/null
@@ -1,764 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32h750xx.s
- * @author MCD Application Team
- * @brief STM32H750xx Devices vector table for GCC based toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m7
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
- .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word CRYP_IRQHandler /* Crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
- .word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
- .word UART8_IRQHandler /* UART8 */
- .word SPI4_IRQHandler /* SPI4 */
- .word SPI5_IRQHandler /* SPI5 */
- .word SPI6_IRQHandler /* SPI6 */
- .word SAI1_IRQHandler /* SAI1 */
- .word LTDC_IRQHandler /* LTDC */
- .word LTDC_ER_IRQHandler /* LTDC error */
- .word DMA2D_IRQHandler /* DMA2D */
- .word SAI2_IRQHandler /* SAI2 */
- .word QUADSPI_IRQHandler /* QUADSPI */
- .word LPTIM1_IRQHandler /* LPTIM1 */
- .word CEC_IRQHandler /* HDMI_CEC */
- .word I2C4_EV_IRQHandler /* I2C4 Event */
- .word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
- .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
- .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
- .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
- .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
- .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
- .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
- .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
- .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
- .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word SAI3_IRQHandler /* SAI3 global Interrupt */
- .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word JPEG_IRQHandler /* JPEG global Interrupt */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
- .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word 0 /* Reserved */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
- .thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
- .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
- .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
- .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
- .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
- .thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
- .thumb_set LTDC_IRQHandler,Default_Handler
-
- .weak LTDC_ER_IRQHandler
- .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
- .weak DMA2D_IRQHandler
- .thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak SAI2_IRQHandler
- .thumb_set SAI2_IRQHandler,Default_Handler
-
- .weak QUADSPI_IRQHandler
- .thumb_set QUADSPI_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
- .thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
- .thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_OUT_IRQHandler
- .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_IN_IRQHandler
- .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak HRTIM1_Master_IRQHandler
- .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMA_IRQHandler
- .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMB_IRQHandler
- .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMC_IRQHandler
- .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMD_IRQHandler
- .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIME_IRQHandler
- .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
-
- .weak HRTIM1_FLT_IRQHandler
- .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT3_IRQHandler
- .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SAI3_IRQHandler
- .thumb_set SAI3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
- .thumb_set SWPMI1_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
-
- .weak MDIOS_IRQHandler
- .thumb_set MDIOS_IRQHandler,Default_Handler
-
- .weak JPEG_IRQHandler
- .thumb_set JPEG_IRQHandler,Default_Handler
-
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
-
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
- .thumb_set HSEM1_IRQHandler,Default_Handler
-
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
-
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
-
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
-
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
-
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
-
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
-
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
-
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
-
- .weak BDMA_Channel6_IRQHandler
- .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
-
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
-
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
-
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
-
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
-
- .weak SAI4_IRQHandler
- .thumb_set SAI4_IRQHandler,Default_Handler
-
- .weak WAKEUP_PIN_IRQHandler
- .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s
deleted file mode 100644
index fda2b83..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s
+++ /dev/null
@@ -1,764 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32h753xx.s
- * @author MCD Application Team
- * @brief STM32H753xx Devices vector table for GCC based toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m7
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
- .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word CRYP_IRQHandler /* Crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
- .word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
- .word UART8_IRQHandler /* UART8 */
- .word SPI4_IRQHandler /* SPI4 */
- .word SPI5_IRQHandler /* SPI5 */
- .word SPI6_IRQHandler /* SPI6 */
- .word SAI1_IRQHandler /* SAI1 */
- .word LTDC_IRQHandler /* LTDC */
- .word LTDC_ER_IRQHandler /* LTDC error */
- .word DMA2D_IRQHandler /* DMA2D */
- .word SAI2_IRQHandler /* SAI2 */
- .word QUADSPI_IRQHandler /* QUADSPI */
- .word LPTIM1_IRQHandler /* LPTIM1 */
- .word CEC_IRQHandler /* HDMI_CEC */
- .word I2C4_EV_IRQHandler /* I2C4 Event */
- .word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
- .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
- .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
- .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
- .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
- .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
- .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
- .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
- .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
- .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word SAI3_IRQHandler /* SAI3 global Interrupt */
- .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word JPEG_IRQHandler /* JPEG global Interrupt */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
- .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word 0 /* Reserved */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
- .thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
- .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
- .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
- .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
- .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
- .thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
- .thumb_set LTDC_IRQHandler,Default_Handler
-
- .weak LTDC_ER_IRQHandler
- .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
- .weak DMA2D_IRQHandler
- .thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak SAI2_IRQHandler
- .thumb_set SAI2_IRQHandler,Default_Handler
-
- .weak QUADSPI_IRQHandler
- .thumb_set QUADSPI_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
- .thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
- .thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_OUT_IRQHandler
- .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_FS_EP1_IN_IRQHandler
- .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak HRTIM1_Master_IRQHandler
- .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMA_IRQHandler
- .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMB_IRQHandler
- .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMC_IRQHandler
- .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIMD_IRQHandler
- .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
-
- .weak HRTIM1_TIME_IRQHandler
- .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
-
- .weak HRTIM1_FLT_IRQHandler
- .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
-
- .weak DFSDM1_FLT3_IRQHandler
- .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SAI3_IRQHandler
- .thumb_set SAI3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
- .thumb_set SWPMI1_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
-
- .weak MDIOS_IRQHandler
- .thumb_set MDIOS_IRQHandler,Default_Handler
-
- .weak JPEG_IRQHandler
- .thumb_set JPEG_IRQHandler,Default_Handler
-
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
-
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
- .thumb_set HSEM1_IRQHandler,Default_Handler
-
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
-
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
-
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
-
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
-
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
-
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
-
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
-
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
-
- .weak BDMA_Channel6_IRQHandler
- .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
-
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
-
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
-
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
-
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
-
- .weak SAI4_IRQHandler
- .thumb_set SAI4_IRQHandler,Default_Handler
-
- .weak WAKEUP_PIN_IRQHandler
- .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf
deleted file mode 100644
index f011c3f..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf
deleted file mode 100644
index d174484..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf
deleted file mode 100644
index 89dc6fd..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf
deleted file mode 100644
index 1cc4edd..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf
deleted file mode 100644
index be46274..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x24000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf
deleted file mode 100644
index f011c3f..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf
deleted file mode 100644
index 0822bd0..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf
deleted file mode 100644
index 356f0ce..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf
deleted file mode 100644
index a0c63a8..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf
deleted file mode 100644
index be46274..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x24000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf
deleted file mode 100644
index f011c3f..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf
deleted file mode 100644
index d174484..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf
deleted file mode 100644
index 89dc6fd..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf
deleted file mode 100644
index 1cc4edd..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf
deleted file mode 100644
index be46274..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x24000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
-define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s
deleted file mode 100644
index a0cdcd5..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s
+++ /dev/null
@@ -1,987 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32h743xx.s
-;* Author : MCD Application Team
-;* Description : STM32H743xx devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD 0 ; Reserved
- DCD RNG_IRQHandler ; Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_AVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_AVD_IRQHandler
- B PVD_AVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK FDCAN1_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT0_IRQHandler
- B FDCAN1_IT0_IRQHandler
-
- PUBWEAK FDCAN2_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT0_IRQHandler
- B FDCAN2_IT0_IRQHandler
-
- PUBWEAK FDCAN1_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT1_IRQHandler
- B FDCAN1_IT1_IRQHandler
-
- PUBWEAK FDCAN2_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT1_IRQHandler
- B FDCAN2_IT1_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
- B TIM1_BRK_IRQHandler
-
- PUBWEAK TIM1_UP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
- B TIM1_UP_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
- B TIM1_TRG_COM_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FMC_IRQHandler
- B FMC_IRQHandler
-
- PUBWEAK SDMMC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC1_IRQHandler
- B SDMMC1_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK ETH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_IRQHandler
- B ETH_IRQHandler
-
- PUBWEAK ETH_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_WKUP_IRQHandler
- B ETH_WKUP_IRQHandler
-
- PUBWEAK FDCAN_CAL_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN_CAL_IRQHandler
- B FDCAN_CAL_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK DCMI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DCMI_IRQHandler
- B DCMI_IRQHandler
-
- PUBWEAK RNG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
- B RNG_IRQHandler
-
- PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FPU_IRQHandler
- B FPU_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK SPI5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI5_IRQHandler
- B SPI5_IRQHandler
-
- PUBWEAK SPI6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI6_IRQHandler
- B SPI6_IRQHandler
-
- PUBWEAK SAI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI1_IRQHandler
- B SAI1_IRQHandler
-
- PUBWEAK LTDC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_IRQHandler
- B LTDC_IRQHandler
-
- PUBWEAK LTDC_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_ER_IRQHandler
- B LTDC_ER_IRQHandler
-
- PUBWEAK DMA2D_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2D_IRQHandler
- B DMA2D_IRQHandler
-
- PUBWEAK SAI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI2_IRQHandler
- B SAI2_IRQHandler
-
- PUBWEAK QUADSPI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-QUADSPI_IRQHandler
- B QUADSPI_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK CEC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
- B CEC_IRQHandler
-
- PUBWEAK I2C4_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_EV_IRQHandler
- B I2C4_EV_IRQHandler
-
- PUBWEAK I2C4_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_ER_IRQHandler
- B I2C4_ER_IRQHandler
-
- PUBWEAK SPDIF_RX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPDIF_RX_IRQHandler
- B SPDIF_RX_IRQHandler
-
- PUBWEAK OTG_FS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_OUT_IRQHandler
- B OTG_FS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_FS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_IN_IRQHandler
- B OTG_FS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
- B DMAMUX1_OVR_IRQHandler
-
- PUBWEAK HRTIM1_Master_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_Master_IRQHandler
- B HRTIM1_Master_IRQHandler
-
- PUBWEAK HRTIM1_TIMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMA_IRQHandler
- B HRTIM1_TIMA_IRQHandler
-
- PUBWEAK HRTIM1_TIMB_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMB_IRQHandler
- B HRTIM1_TIMB_IRQHandler
-
- PUBWEAK HRTIM1_TIMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMC_IRQHandler
- B HRTIM1_TIMC_IRQHandler
-
- PUBWEAK HRTIM1_TIMD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMD_IRQHandler
- B HRTIM1_TIMD_IRQHandler
-
- PUBWEAK HRTIM1_TIME_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIME_IRQHandler
- B HRTIM1_TIME_IRQHandler
-
- PUBWEAK HRTIM1_FLT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_FLT_IRQHandler
- B HRTIM1_FLT_IRQHandler
-
- PUBWEAK DFSDM1_FLT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT0_IRQHandler
- B DFSDM1_FLT0_IRQHandler
-
- PUBWEAK DFSDM1_FLT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT1_IRQHandler
- B DFSDM1_FLT1_IRQHandler
-
- PUBWEAK DFSDM1_FLT2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT2_IRQHandler
- B DFSDM1_FLT2_IRQHandler
-
- PUBWEAK DFSDM1_FLT3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT3_IRQHandler
- B DFSDM1_FLT3_IRQHandler
-
- PUBWEAK SAI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI3_IRQHandler
- B SAI3_IRQHandler
-
- PUBWEAK SWPMI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SWPMI1_IRQHandler
- B SWPMI1_IRQHandler
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK MDIOS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_WKUP_IRQHandler
- B MDIOS_WKUP_IRQHandler
-
- PUBWEAK MDIOS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_IRQHandler
- B MDIOS_IRQHandler
-
- PUBWEAK JPEG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-JPEG_IRQHandler
- B JPEG_IRQHandler
-
- PUBWEAK MDMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDMA_IRQHandler
- B MDMA_IRQHandler
-
- PUBWEAK SDMMC2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC2_IRQHandler
- B SDMMC2_IRQHandler
-
- PUBWEAK HSEM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM1_IRQHandler
- B HSEM1_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK DMAMUX2_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX2_OVR_IRQHandler
- B DMAMUX2_OVR_IRQHandler
-
- PUBWEAK BDMA_Channel0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel0_IRQHandler
- B BDMA_Channel0_IRQHandler
-
- PUBWEAK BDMA_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel1_IRQHandler
- B BDMA_Channel1_IRQHandler
-
- PUBWEAK BDMA_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel2_IRQHandler
- B BDMA_Channel2_IRQHandler
-
- PUBWEAK BDMA_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel3_IRQHandler
- B BDMA_Channel3_IRQHandler
-
- PUBWEAK BDMA_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel4_IRQHandler
- B BDMA_Channel4_IRQHandler
-
- PUBWEAK BDMA_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel5_IRQHandler
- B BDMA_Channel5_IRQHandler
-
- PUBWEAK BDMA_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel6_IRQHandler
- B BDMA_Channel6_IRQHandler
-
- PUBWEAK BDMA_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel7_IRQHandler
- B BDMA_Channel7_IRQHandler
-
- PUBWEAK COMP1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP1_IRQHandler
- B COMP1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK LPTIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
- B LPTIM3_IRQHandler
-
- PUBWEAK LPTIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM4_IRQHandler
- B LPTIM4_IRQHandler
-
- PUBWEAK LPTIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM5_IRQHandler
- B LPTIM5_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CRS_IRQHandler
- B CRS_IRQHandler
-
- PUBWEAK SAI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI4_IRQHandler
- B SAI4_IRQHandler
-
- PUBWEAK WAKEUP_PIN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WAKEUP_PIN_IRQHandler
- B WAKEUP_PIN_IRQHandler
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s
deleted file mode 100644
index 6b41911..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s
+++ /dev/null
@@ -1,992 +0,0 @@
-;/******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
-;* File Name : startup_stm32h750xx.s
-;* Author : MCD Application Team
-;* Description : STM32H750xx devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_AVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_AVD_IRQHandler
- B PVD_AVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK FDCAN1_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT0_IRQHandler
- B FDCAN1_IT0_IRQHandler
-
- PUBWEAK FDCAN2_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT0_IRQHandler
- B FDCAN2_IT0_IRQHandler
-
- PUBWEAK FDCAN1_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT1_IRQHandler
- B FDCAN1_IT1_IRQHandler
-
- PUBWEAK FDCAN2_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT1_IRQHandler
- B FDCAN2_IT1_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
- B TIM1_BRK_IRQHandler
-
- PUBWEAK TIM1_UP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
- B TIM1_UP_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
- B TIM1_TRG_COM_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FMC_IRQHandler
- B FMC_IRQHandler
-
- PUBWEAK SDMMC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC1_IRQHandler
- B SDMMC1_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK ETH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_IRQHandler
- B ETH_IRQHandler
-
- PUBWEAK ETH_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_WKUP_IRQHandler
- B ETH_WKUP_IRQHandler
-
- PUBWEAK FDCAN_CAL_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN_CAL_IRQHandler
- B FDCAN_CAL_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK DCMI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DCMI_IRQHandler
- B DCMI_IRQHandler
-
- PUBWEAK CRYP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CRYP_IRQHandler
- B CRYP_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
- PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FPU_IRQHandler
- B FPU_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK SPI5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI5_IRQHandler
- B SPI5_IRQHandler
-
- PUBWEAK SPI6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI6_IRQHandler
- B SPI6_IRQHandler
-
- PUBWEAK SAI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI1_IRQHandler
- B SAI1_IRQHandler
-
- PUBWEAK LTDC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_IRQHandler
- B LTDC_IRQHandler
-
- PUBWEAK LTDC_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_ER_IRQHandler
- B LTDC_ER_IRQHandler
-
- PUBWEAK DMA2D_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2D_IRQHandler
- B DMA2D_IRQHandler
-
- PUBWEAK SAI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI2_IRQHandler
- B SAI2_IRQHandler
-
- PUBWEAK QUADSPI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-QUADSPI_IRQHandler
- B QUADSPI_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK CEC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
- B CEC_IRQHandler
-
- PUBWEAK I2C4_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_EV_IRQHandler
- B I2C4_EV_IRQHandler
-
- PUBWEAK I2C4_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_ER_IRQHandler
- B I2C4_ER_IRQHandler
-
- PUBWEAK SPDIF_RX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPDIF_RX_IRQHandler
- B SPDIF_RX_IRQHandler
-
- PUBWEAK OTG_FS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_OUT_IRQHandler
- B OTG_FS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_FS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_IN_IRQHandler
- B OTG_FS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
- B DMAMUX1_OVR_IRQHandler
-
- PUBWEAK HRTIM1_Master_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_Master_IRQHandler
- B HRTIM1_Master_IRQHandler
-
- PUBWEAK HRTIM1_TIMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMA_IRQHandler
- B HRTIM1_TIMA_IRQHandler
-
- PUBWEAK HRTIM1_TIMB_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMB_IRQHandler
- B HRTIM1_TIMB_IRQHandler
-
- PUBWEAK HRTIM1_TIMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMC_IRQHandler
- B HRTIM1_TIMC_IRQHandler
-
- PUBWEAK HRTIM1_TIMD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMD_IRQHandler
- B HRTIM1_TIMD_IRQHandler
-
- PUBWEAK HRTIM1_TIME_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIME_IRQHandler
- B HRTIM1_TIME_IRQHandler
-
- PUBWEAK HRTIM1_FLT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_FLT_IRQHandler
- B HRTIM1_FLT_IRQHandler
-
- PUBWEAK DFSDM1_FLT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT0_IRQHandler
- B DFSDM1_FLT0_IRQHandler
-
- PUBWEAK DFSDM1_FLT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT1_IRQHandler
- B DFSDM1_FLT1_IRQHandler
-
- PUBWEAK DFSDM1_FLT2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT2_IRQHandler
- B DFSDM1_FLT2_IRQHandler
-
- PUBWEAK DFSDM1_FLT3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT3_IRQHandler
- B DFSDM1_FLT3_IRQHandler
-
- PUBWEAK SAI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI3_IRQHandler
- B SAI3_IRQHandler
-
- PUBWEAK SWPMI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SWPMI1_IRQHandler
- B SWPMI1_IRQHandler
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK MDIOS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_WKUP_IRQHandler
- B MDIOS_WKUP_IRQHandler
-
- PUBWEAK MDIOS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_IRQHandler
- B MDIOS_IRQHandler
-
- PUBWEAK JPEG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-JPEG_IRQHandler
- B JPEG_IRQHandler
-
- PUBWEAK MDMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDMA_IRQHandler
- B MDMA_IRQHandler
-
- PUBWEAK SDMMC2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC2_IRQHandler
- B SDMMC2_IRQHandler
-
- PUBWEAK HSEM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM1_IRQHandler
- B HSEM1_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK DMAMUX2_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX2_OVR_IRQHandler
- B DMAMUX2_OVR_IRQHandler
-
- PUBWEAK BDMA_Channel0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel0_IRQHandler
- B BDMA_Channel0_IRQHandler
-
- PUBWEAK BDMA_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel1_IRQHandler
- B BDMA_Channel1_IRQHandler
-
- PUBWEAK BDMA_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel2_IRQHandler
- B BDMA_Channel2_IRQHandler
-
- PUBWEAK BDMA_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel3_IRQHandler
- B BDMA_Channel3_IRQHandler
-
- PUBWEAK BDMA_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel4_IRQHandler
- B BDMA_Channel4_IRQHandler
-
- PUBWEAK BDMA_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel5_IRQHandler
- B BDMA_Channel5_IRQHandler
-
- PUBWEAK BDMA_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel6_IRQHandler
- B BDMA_Channel6_IRQHandler
-
- PUBWEAK BDMA_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel7_IRQHandler
- B BDMA_Channel7_IRQHandler
-
- PUBWEAK COMP1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP1_IRQHandler
- B COMP1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK LPTIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
- B LPTIM3_IRQHandler
-
- PUBWEAK LPTIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM4_IRQHandler
- B LPTIM4_IRQHandler
-
- PUBWEAK LPTIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM5_IRQHandler
- B LPTIM5_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CRS_IRQHandler
- B CRS_IRQHandler
-
- PUBWEAK SAI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI4_IRQHandler
- B SAI4_IRQHandler
-
- PUBWEAK WAKEUP_PIN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WAKEUP_PIN_IRQHandler
- B WAKEUP_PIN_IRQHandler
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s
deleted file mode 100644
index 5efeabe..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s
+++ /dev/null
@@ -1,992 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32h753xx.s
-;* Author : MCD Application Team
-;* Description : STM32H753xx devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
- DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2
- DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
- DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
- DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
- DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
- DCD TIM1_UP_IRQHandler ; TIM1 Update
- DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD 0 ; Reserved
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FMC_IRQHandler ; FMC
- DCD SDMMC1_IRQHandler ; SDMMC1
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and Rng
- DCD FPU_IRQHandler ; FPU
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
- DCD SPI4_IRQHandler ; SPI4
- DCD SPI5_IRQHandler ; SPI5
- DCD SPI6_IRQHandler ; SPI6
- DCD SAI1_IRQHandler ; SAI1
- DCD LTDC_IRQHandler ; LTDC
- DCD LTDC_ER_IRQHandler ; LTDC error
- DCD DMA2D_IRQHandler ; DMA2D
- DCD SAI2_IRQHandler ; SAI2
- DCD QUADSPI_IRQHandler ; QUADSPI
- DCD LPTIM1_IRQHandler ; LPTIM1
- DCD CEC_IRQHandler ; HDMI_CEC
- DCD I2C4_EV_IRQHandler ; I2C4 Event
- DCD I2C4_ER_IRQHandler ; I2C4 Error
- DCD SPDIF_RX_IRQHandler ; SPDIF_RX
- DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
- DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
- DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
- DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
- DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
- DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
- DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
- DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
- DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
- DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
- DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
- DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
- DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
- DCD SAI3_IRQHandler ; SAI3 global Interrupt
- DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
- DCD TIM15_IRQHandler ; TIM15 global Interrupt
- DCD TIM16_IRQHandler ; TIM16 global Interrupt
- DCD TIM17_IRQHandler ; TIM17 global Interrupt
- DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
- DCD MDIOS_IRQHandler ; MDIOS global Interrupt
- DCD JPEG_IRQHandler ; JPEG global Interrupt
- DCD MDMA_IRQHandler ; MDMA global Interrupt
- DCD 0 ; Reserved
- DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
- DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
- DCD 0 ; Reserved
- DCD ADC3_IRQHandler ; ADC3 global Interrupt
- DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
- DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
- DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
- DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
- DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
- DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
- DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
- DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
- DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
- DCD COMP1_IRQHandler ; COMP1 global Interrupt
- DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
- DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
- DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
- DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
- DCD LPUART1_IRQHandler ; LP UART1 interrupt
- DCD 0 ; Reserved
- DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
- DCD 0 ; Reserved
- DCD SAI4_IRQHandler ; SAI4 global interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_AVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_AVD_IRQHandler
- B PVD_AVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK FDCAN1_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT0_IRQHandler
- B FDCAN1_IT0_IRQHandler
-
- PUBWEAK FDCAN2_IT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT0_IRQHandler
- B FDCAN2_IT0_IRQHandler
-
- PUBWEAK FDCAN1_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN1_IT1_IRQHandler
- B FDCAN1_IT1_IRQHandler
-
- PUBWEAK FDCAN2_IT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN2_IT1_IRQHandler
- B FDCAN2_IT1_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
- B TIM1_BRK_IRQHandler
-
- PUBWEAK TIM1_UP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
- B TIM1_UP_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
- B TIM1_TRG_COM_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FMC_IRQHandler
- B FMC_IRQHandler
-
- PUBWEAK SDMMC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC1_IRQHandler
- B SDMMC1_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK ETH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_IRQHandler
- B ETH_IRQHandler
-
- PUBWEAK ETH_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ETH_WKUP_IRQHandler
- B ETH_WKUP_IRQHandler
-
- PUBWEAK FDCAN_CAL_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FDCAN_CAL_IRQHandler
- B FDCAN_CAL_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK DCMI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DCMI_IRQHandler
- B DCMI_IRQHandler
-
- PUBWEAK CRYP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CRYP_IRQHandler
- B CRYP_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
- PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FPU_IRQHandler
- B FPU_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK SPI5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI5_IRQHandler
- B SPI5_IRQHandler
-
- PUBWEAK SPI6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI6_IRQHandler
- B SPI6_IRQHandler
-
- PUBWEAK SAI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI1_IRQHandler
- B SAI1_IRQHandler
-
- PUBWEAK LTDC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_IRQHandler
- B LTDC_IRQHandler
-
- PUBWEAK LTDC_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LTDC_ER_IRQHandler
- B LTDC_ER_IRQHandler
-
- PUBWEAK DMA2D_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2D_IRQHandler
- B DMA2D_IRQHandler
-
- PUBWEAK SAI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI2_IRQHandler
- B SAI2_IRQHandler
-
- PUBWEAK QUADSPI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-QUADSPI_IRQHandler
- B QUADSPI_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK CEC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
- B CEC_IRQHandler
-
- PUBWEAK I2C4_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_EV_IRQHandler
- B I2C4_EV_IRQHandler
-
- PUBWEAK I2C4_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C4_ER_IRQHandler
- B I2C4_ER_IRQHandler
-
- PUBWEAK SPDIF_RX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPDIF_RX_IRQHandler
- B SPDIF_RX_IRQHandler
-
- PUBWEAK OTG_FS_EP1_OUT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_OUT_IRQHandler
- B OTG_FS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_FS_EP1_IN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_EP1_IN_IRQHandler
- B OTG_FS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
- B DMAMUX1_OVR_IRQHandler
-
- PUBWEAK HRTIM1_Master_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_Master_IRQHandler
- B HRTIM1_Master_IRQHandler
-
- PUBWEAK HRTIM1_TIMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMA_IRQHandler
- B HRTIM1_TIMA_IRQHandler
-
- PUBWEAK HRTIM1_TIMB_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMB_IRQHandler
- B HRTIM1_TIMB_IRQHandler
-
- PUBWEAK HRTIM1_TIMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMC_IRQHandler
- B HRTIM1_TIMC_IRQHandler
-
- PUBWEAK HRTIM1_TIMD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIMD_IRQHandler
- B HRTIM1_TIMD_IRQHandler
-
- PUBWEAK HRTIM1_TIME_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_TIME_IRQHandler
- B HRTIM1_TIME_IRQHandler
-
- PUBWEAK HRTIM1_FLT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HRTIM1_FLT_IRQHandler
- B HRTIM1_FLT_IRQHandler
-
- PUBWEAK DFSDM1_FLT0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT0_IRQHandler
- B DFSDM1_FLT0_IRQHandler
-
- PUBWEAK DFSDM1_FLT1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT1_IRQHandler
- B DFSDM1_FLT1_IRQHandler
-
- PUBWEAK DFSDM1_FLT2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT2_IRQHandler
- B DFSDM1_FLT2_IRQHandler
-
- PUBWEAK DFSDM1_FLT3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DFSDM1_FLT3_IRQHandler
- B DFSDM1_FLT3_IRQHandler
-
- PUBWEAK SAI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI3_IRQHandler
- B SAI3_IRQHandler
-
- PUBWEAK SWPMI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SWPMI1_IRQHandler
- B SWPMI1_IRQHandler
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK MDIOS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_WKUP_IRQHandler
- B MDIOS_WKUP_IRQHandler
-
- PUBWEAK MDIOS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDIOS_IRQHandler
- B MDIOS_IRQHandler
-
- PUBWEAK JPEG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-JPEG_IRQHandler
- B JPEG_IRQHandler
-
- PUBWEAK MDMA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MDMA_IRQHandler
- B MDMA_IRQHandler
-
- PUBWEAK SDMMC2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDMMC2_IRQHandler
- B SDMMC2_IRQHandler
-
- PUBWEAK HSEM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM1_IRQHandler
- B HSEM1_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK DMAMUX2_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX2_OVR_IRQHandler
- B DMAMUX2_OVR_IRQHandler
-
- PUBWEAK BDMA_Channel0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel0_IRQHandler
- B BDMA_Channel0_IRQHandler
-
- PUBWEAK BDMA_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel1_IRQHandler
- B BDMA_Channel1_IRQHandler
-
- PUBWEAK BDMA_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel2_IRQHandler
- B BDMA_Channel2_IRQHandler
-
- PUBWEAK BDMA_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel3_IRQHandler
- B BDMA_Channel3_IRQHandler
-
- PUBWEAK BDMA_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel4_IRQHandler
- B BDMA_Channel4_IRQHandler
-
- PUBWEAK BDMA_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel5_IRQHandler
- B BDMA_Channel5_IRQHandler
-
- PUBWEAK BDMA_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel6_IRQHandler
- B BDMA_Channel6_IRQHandler
-
- PUBWEAK BDMA_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BDMA_Channel7_IRQHandler
- B BDMA_Channel7_IRQHandler
-
- PUBWEAK COMP1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP1_IRQHandler
- B COMP1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK LPTIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
- B LPTIM3_IRQHandler
-
- PUBWEAK LPTIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM4_IRQHandler
- B LPTIM4_IRQHandler
-
- PUBWEAK LPTIM5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM5_IRQHandler
- B LPTIM5_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CRS_IRQHandler
- B CRS_IRQHandler
-
- PUBWEAK SAI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI4_IRQHandler
- B SAI4_IRQHandler
-
- PUBWEAK WAKEUP_PIN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WAKEUP_PIN_IRQHandler
- B WAKEUP_PIN_IRQHandler
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c
deleted file mode 100644
index 4018f50..0000000
--- a/KugleFirmware/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32h7xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/** @addtogroup STM32H7xx_System_Private_Includes
- * @{
- */
-
-#include "stm32h7xx.h"
-
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
- on EVAL board as data memory */
-/*#define DATA_IN_ExtSRAM */
-/*#define DATA_IN_ExtSDRAM*/
-
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
- uint32_t SystemCoreClock = 64000000;
- uint32_t SystemD2Clock = 64000000;
- const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
- * @{
- */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and External memory
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= RCC_CR_HSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEAF6ED7F;
-
- /* Reset D1CFGR register */
- RCC->D1CFGR = 0x00000000;
-
- /* Reset D2CFGR register */
- RCC->D2CFGR = 0x00000000;
-
- /* Reset D3CFGR register */
- RCC->D3CFGR = 0x00000000;
-
- /* Reset PLLCKSELR register */
- RCC->PLLCKSELR = 0x00000000;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00000000;
- /* Reset PLL1DIVR register */
- RCC->PLL1DIVR = 0x00000000;
- /* Reset PLL1FRACR register */
- RCC->PLL1FRACR = 0x00000000;
-
- /* Reset PLL2DIVR register */
- RCC->PLL2DIVR = 0x00000000;
-
- /* Reset PLL2FRACR register */
-
- RCC->PLL2FRACR = 0x00000000;
- /* Reset PLL3DIVR register */
- RCC->PLL3DIVR = 0x00000000;
-
- /* Reset PLL3FRACR register */
- RCC->PLL3FRACR = 0x00000000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000;
-
- /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
- *((__IO uint32_t*)0x51008108) = 0x00000001;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal ITCMSRAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock , it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
- * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- *
- * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 4 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 64 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
-uint32_t pllp = 2, pllsource = 0, pllm = 2 ,tmp, pllfracen =0 , hsivalue = 0;
-float fracn1, pllvco = 0 ;
-
- /* Get SYSCLK source -------------------------------------------------------*/
-
- switch (RCC->CFGR & RCC_CFGR_SWS)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
- break;
-
- case 0x08: /* CSI used as system clock source */
- SystemCoreClock = CSI_VALUE;
- break;
-
- case 0x10: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
-
- case 0x18: /* PLL1 used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
- pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
- fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
- switch (pllsource)
- {
-
- case 0x00: /* HSI used as PLL clock source */
- hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
- pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- case 0x01: /* CSI used as PLL clock source */
- pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- case 0x02: /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- default:
- pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
- }
- pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
- SystemCoreClock = (uint32_t) (pllvco/pllp);
- break;
-
- default:
- SystemCoreClock = CSI_VALUE;
- break;
- }
-
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32h7xx.s before jump to main.
- * This function configures the external memories (SRAM/SDRAM)
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
-#if defined (DATA_IN_ExtSDRAM)
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register __IO uint32_t index;
-
- /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
- clock */
- RCC->AHB4ENR |= 0x000001F8;
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAFEAFFFA;
- /* Configure PDx pins speed to 50 MHz */
- GPIOD->OSPEEDR = 0xA02A000A;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x55555505;
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAABFFA;
- /* Configure PEx pins speed to 50 MHz */
- GPIOE->OSPEEDR = 0xAAAA800A;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x55554005;
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCCC000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAABFFAAA;
- /* Configure PFx pins speed to 50 MHz */
- GPIOF->OSPEEDR = 0xAA800AAA;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x55400555;
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0xC000000C;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xBFFEFAAA;
- /* Configure PGx pins speed to 50 MHz */
- GPIOG->OSPEEDR = 0x80020AAA;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x40010515;
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0xCCC00000;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAAABFF;
- /* Configure PHx pins speed to 50 MHz */
- GPIOH->OSPEEDR = 0xAAAAA800;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x55555400;
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0xFFEBAAAA;
- /* Configure PIx pins speed to 50 MHz */
- GPIOI->OSPEEDR = 0x0028AAAA;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00145555;
-/*-- FMC Configuration ------------------------------------------------------*/
- /* Enable the FMC interface clock */
- (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
- /*SDRAM Timing and access interface configuration*/
- /*LoadToActiveDelay = 2
- ExitSelfRefreshDelay = 6
- SelfRefreshTime = 4
- RowCycleDelay = 6
- WriteRecoveryTime = 2
- RPDelay = 2
- RCDDelay = 2
- SDBank = FMC_SDRAM_BANK2
- ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
- RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
- MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
- InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
- CASLatency = FMC_SDRAM_CAS_LATENCY_2
- WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
- SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
- ReadBurst = FMC_SDRAM_RBURST_ENABLE
- ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
-
- FMC_Bank5_6->SDCR[0] = 0x00001800;
- FMC_Bank5_6->SDCR[1] = 0x00000165;
- FMC_Bank5_6->SDTR[0] = 0x00105000;
- FMC_Bank5_6->SDTR[1] = 0x01010351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000009;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x0000000A;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6->SDCMR = 0x000000EB;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6->SDCMR = 0x0004400C;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[1];
- FMC_Bank5_6->SDCR[1] = (tmpreg & 0xFFFFFDFF);
-
- /*FMC controller Enable*/
- FMC_Bank1->BTCR[0] |= 0x80000000;
-
-
-#endif /* DATA_IN_ExtSDRAM */
-
-#if defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB4ENR |= 0x00000078;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CCC0CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAA0A8A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0FCF;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x55550545;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA828A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x55554145;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCC0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA000AAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFF000FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x55000555;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0x000000C0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00200AAA;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x00300FFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00100555;
-
-/*-- FMC/FSMC Configuration --------------------------------------------------*/
- /* Enable the FMC/FSMC interface clock */
- (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
-
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1->BTCR[4] = 0x00001091;
- FMC_Bank1->BTCR[5] = 0x00110212;
- FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
- /*FMC controller Enable*/
- FMC_Bank1->BTCR[0] |= 0x80000000;
-
-
-#endif /* DATA_IN_ExtSRAM */
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/CMSIS/Include/cmsis_armcc.h b/KugleFirmware/Drivers/CMSIS/Include/cmsis_armcc.h
deleted file mode 100644
index 3ddc308..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/cmsis_armcc.h
+++ /dev/null
@@ -1,797 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armcc.h
- * @brief CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version V5.0.1
- * @date 03. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
- (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
- #define __ARM_ARCH_6M__ 1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
- #define __ARM_ARCH_7M__ 1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
- #define __ARM_ARCH_7EM__ 1
-#endif
-
- /* __ARM_ARCH_8M_BASE__ not applicable */
- /* __ARM_ARCH_8M_MAIN__ not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __declspec(noreturn)
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
- #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT __packed struct
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); */
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#else
- (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() do {\
- __schedule_barrier();\
- __isb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
- __schedule_barrier();\
- __dsb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
- #define __RBIT __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
- int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
- return(result);
-}
-#endif
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-#else
- #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-#else
- #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-#else
- #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXB(value, ptr) __strex(value, ptr)
-#else
- #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXH(value, ptr) __strex(value, ptr)
-#else
- #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXW(value, ptr) __strex(value, ptr)
-#else
- #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __clrex
-
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32U) ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/cmsis_armclang.h b/KugleFirmware/Drivers/CMSIS/Include/cmsis_armclang.h
deleted file mode 100644
index be7d1f3..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/cmsis_armclang.h
+++ /dev/null
@@ -1,1734 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armclang.h
- * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version V5.0.1
- * @date 02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#ifndef __ARM_COMPAT_H
-#include /* Compatibility header for ARM Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); see arm_compat.h */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); see arm_compat.h */
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-/* #define __get_FPSCR __builtin_arm_get_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-/* #define __set_FPSCR __builtin_arm_set_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
-#else
- (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __builtin_arm_nop
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __builtin_arm_wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __builtin_arm_wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __builtin_arm_sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() __builtin_arm_isb(0xF);
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __builtin_arm_dsb(0xF);
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __builtin_arm_dmb(0xF);
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __builtin_bswap32
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
- /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
- int32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
- /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return(result);
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB (uint8_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH (uint16_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW (uint32_t)__builtin_arm_ldrex
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __builtin_arm_ssat
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __builtin_arm_usat
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDAEXB (uint8_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDAEXH (uint16_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDAEX (uint32_t)__builtin_arm_ldaex
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXB (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXH (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEX (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/cmsis_compiler.h b/KugleFirmware/Drivers/CMSIS/Include/cmsis_compiler.h
deleted file mode 100644
index 8b989f8..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/cmsis_compiler.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_compiler.h
- * @brief CMSIS compiler generic header file
- * @version V5.0.1
- * @date 30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include
-
-/*
- * ARM Compiler 4/5
- */
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-
-/*
- * ARM Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
-
- #include
-
- #ifndef __NO_RETURN
- #define __NO_RETURN __noreturn
- #endif
- #ifndef __USED
- #define __USED __root
- #endif
- #ifndef __WEAK
- #define __WEAK __weak
- #endif
- #ifndef __UNALIGNED_UINT32
- __packed struct T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
- #ifndef __PACKED
- #define __PACKED __packed
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT __packed struct
- #endif
-
-
-/*
- * TI ARM Compiler
- */
-#elif defined ( __TI_ARM__ )
- #include
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __UNALIGNED_UINT32
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
- #endif
- #ifndef __PACKED
- #define __PACKED __attribute__((packed))
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed))
- #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __UNALIGNED_UINT32
- struct __packed__ T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __align(x)
- #endif
- #ifndef __PACKED
- #define __PACKED __packed__
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __packed__
- #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
- #include
-
- #ifndef __ASM
- #define __ASM _asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __NO_RETURN
- // NO RETURN is automatically detected hence no warning here
- #define __NO_RETURN
- #endif
- #ifndef __USED
- #warning No compiler specific solution for __USED. __USED is ignored.
- #define __USED
- #endif
- #ifndef __WEAK
- #define __WEAK __weak
- #endif
- #ifndef __UNALIGNED_UINT32
- @packed struct T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __ALIGNED
- #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
- #ifndef __PACKED
- #define __PACKED @packed
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT @packed struct
- #endif
-
-
-#else
- #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/KugleFirmware/Drivers/CMSIS/Include/cmsis_gcc.h b/KugleFirmware/Drivers/CMSIS/Include/cmsis_gcc.h
deleted file mode 100644
index 074cd7a..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/cmsis_gcc.h
+++ /dev/null
@@ -1,1899 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_gcc.h
- * @brief CMSIS compiler GCC header file
- * @version V5.0.1
- * @date 02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __UNALIGNED_UINT32
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpacked"
-#pragma GCC diagnostic ignored "-Wattributes"
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-#pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
- return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
- (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
- (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-// __ASM volatile ("nop");
-//}
-#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-// __ASM volatile ("wfi");
-//}
-#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-// __ASM volatile ("wfe");
-//}
-#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-// __ASM volatile ("sev");
-//}
-#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- int32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return(result);
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_armv8mbl.h b/KugleFirmware/Drivers/CMSIS/Include/core_armv8mbl.h
deleted file mode 100644
index 5ce9a52..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_armv8mbl.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-/**************************************************************************//**
- * @file core_armv8mbl.h
- * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_ARMv8MBL
- @{
- */
-
-/* CMSIS cmGrebe definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
- __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __ARMv8MBL_REV
- #define __ARMv8MBL_REV 0x0000U
- #warning "__ARMv8MBL_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-
- #ifndef __ETM_PRESENT
- #define __ETM_PRESENT 0U
- #warning "__ETM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MTB_PRESENT
- #define __MTB_PRESENT 0U
- #warning "__MTB_PRESENT not defined in device header file; using default!"
- #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- uint32_t RESERVED0[6U];
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- uint32_t RESERVED0[7U];
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_armv8mml.h b/KugleFirmware/Drivers/CMSIS/Include/core_armv8mml.h
deleted file mode 100644
index c821f56..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_armv8mml.h
+++ /dev/null
@@ -1,2885 +0,0 @@
-/**************************************************************************//**
- * @file core_armv8mml.h
- * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version V5.0.2
- * @date 07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_ARMv8MML
- @{
- */
-
-/* CMSIS ARMv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
- __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (81U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __ARMv8MML_REV
- #define __ARMv8MML_REV 0x0000U
- #warning "__ARMv8MML_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DSP_PRESENT
- #define __DSP_PRESENT 0U
- #warning "__DSP_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm0.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm0.h
deleted file mode 100644
index 2fb5821..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm0.h
+++ /dev/null
@@ -1,875 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000U
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- Address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm0plus.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm0plus.h
deleted file mode 100644
index 751384b..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm0plus.h
+++ /dev/null
@@ -1,1001 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0plus.h
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex-M0+
- @{
- */
-
-/* CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
- __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0PLUS_REV
- #define __CM0PLUS_REV 0x0000U
- #warning "__CM0PLUS_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0+ header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm23.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm23.h
deleted file mode 100644
index 83055ba..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm23.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-/**************************************************************************//**
- * @file core_cm23.h
- * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M23
- @{
- */
-
-/* CMSIS cmGrebe definitions */
-#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
- __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (23U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM23_REV
- #define __CM23_REV 0x0000U
- #warning "__CM23_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-
- #ifndef __ETM_PRESENT
- #define __ETM_PRESENT 0U
- #warning "__ETM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MTB_PRESENT
- #define __MTB_PRESENT 0U
- #warning "__MTB_PRESENT not defined in device header file; using default!"
- #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- uint32_t RESERVED0[6U];
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- uint32_t RESERVED0[7U];
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm3.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm3.h
deleted file mode 100644
index 499199c..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm3.h
+++ /dev/null
@@ -1,1919 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M3
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (3U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200U
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm33.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm33.h
deleted file mode 100644
index 65da8ef..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm33.h
+++ /dev/null
@@ -1,2885 +0,0 @@
-/**************************************************************************//**
- * @file core_cm33.h
- * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version V5.0.2
- * @date 07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M33
- @{
- */
-
-/* CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
- __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (33U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM33_REV
- #define __CM33_REV 0x0000U
- #warning "__CM33_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DSP_PRESENT
- #define __DSP_PRESENT 0U
- #warning "__DSP_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm4.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm4.h
deleted file mode 100644
index 2da78d3..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm4.h
+++ /dev/null
@@ -1,2103 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (4U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000U
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_cm7.h b/KugleFirmware/Drivers/CMSIS/Include/core_cm7.h
deleted file mode 100644
index 8bfbe94..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_cm7.h
+++ /dev/null
@@ -1,2635 +0,0 @@
-/**************************************************************************//**
- * @file core_cm7.h
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M7
- @{
- */
-
-/* CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
- __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (7U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM7_REV
- #define __CM7_REV 0x0000U
- #warning "__CM7_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __ICACHE_PRESENT
- #define __ICACHE_PRESENT 0U
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DCACHE_PRESENT
- #define __DCACHE_PRESENT 0U
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DTCM_PRESENT
- #define __DTCM_PRESENT 0U
- #warning "__DTCM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[1U];
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED3[93U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED3[981U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = SCB->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## Cache functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_CacheFunctions Cache Functions
- \brief Functions that configure Instruction and Data cache.
- @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
-
-
-/**
- \brief Enable I-Cache
- \details Turns on I-Cache
- */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- __DSB();
- __ISB();
- SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable I-Cache
- \details Turns off I-Cache
- */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate I-Cache
- \details Invalidates I-Cache
- */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL;
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Enable D-Cache
- \details Turns on D-Cache
- */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
- __DSB();
-
- SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable D-Cache
- \details Turns off D-Cache
- */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- register uint32_t ccsidr;
- register uint32_t sets;
- register uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate D-Cache
- \details Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean D-Cache
- \details Cleans D-Cache
- */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
- ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean & Invalidate D-Cache
- \details Cleans and Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Invalidate by address
- \details Invalidates D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t)addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCIMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean by address
- \details Cleans D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean and Invalidate by address
- \details Cleans and invalidates D_Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCIMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_sc000.h b/KugleFirmware/Drivers/CMSIS/Include/core_sc000.h
deleted file mode 100644
index 8305271..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_sc000.h
+++ /dev/null
@@ -1,1003 +0,0 @@
-/**************************************************************************//**
- * @file core_sc000.h
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC000
- @{
- */
-
-/* CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
- __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (000U) /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC000_REV
- #define __SC000_REV 0x0000U
- #warning "__SC000_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- uint32_t RESERVED1[154U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the SC000 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/core_sc300.h b/KugleFirmware/Drivers/CMSIS/Include/core_sc300.h
deleted file mode 100644
index 1b5041a..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/core_sc300.h
+++ /dev/null
@@ -1,1890 +0,0 @@
-/**************************************************************************//**
- * @file core_sc300.h
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V5.0.1
- * @date 25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC3000
- @{
- */
-
-/* CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
- __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (300U) /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC300_REV
- #define __SC300_REV 0x0000U
- #warning "__SC300_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED1[129U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/KugleFirmware/Drivers/CMSIS/Include/tz_context.h b/KugleFirmware/Drivers/CMSIS/Include/tz_context.h
deleted file mode 100644
index 0784d26..0000000
--- a/KugleFirmware/Drivers/CMSIS/Include/tz_context.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date: 21. September 2016
- * $Revision: V1.0
- *
- * Project: TrustZone for ARMv8-M
- * Title: Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- * Initial Release
- *---------------------------------------------------------------------------*/
-
-#ifndef TZ_CONTEXT_H
-#define TZ_CONTEXT_H
-
-#include
-
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
-
-/// \details TZ Memory ID identifies an allocated memory slot.
-typedef uint32_t TZ_MemoryId_t;
-
-/// Initialize secure context memory system
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
-
-/// Allocate context memory for calling secure software modules in TrustZone
-/// \param[in] module identifies software modules called from non-secure mode
-/// \return value != 0 id TrustZone memory slot identifier
-/// \return value 0 no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
-
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
-/// \param[in] id TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
-
-/// Load secure context (called on RTOS thread context switch)
-/// \param[in] id TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
-
-/// Store secure context (called on RTOS thread context switch)
-/// \param[in] id TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
-
-#endif // TZ_CONTEXT_H
diff --git a/KugleFirmware/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/KugleFirmware/Drivers/CMSIS/RTOS/Template/cmsis_os.h
deleted file mode 100644
index 5fcfad2..0000000
--- a/KugleFirmware/Drivers/CMSIS/RTOS/Template/cmsis_os.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/* ----------------------------------------------------------------------
- * $Date: 5. February 2013
- * $Revision: V1.02
- *
- * Project: CMSIS-RTOS API
- * Title: cmsis_os.h template header file
- *
- * Version 0.02
- * Initial Proposal Phase
- * Version 0.03
- * osKernelStart added, optional feature: main started as thread
- * osSemaphores have standard behavior
- * osTimerCreate does not start the timer, added osTimerStart
- * osThreadPass is renamed to osThreadYield
- * Version 1.01
- * Support for C++ interface
- * - const attribute removed from the osXxxxDef_t typedef's
- * - const attribute added to the osXxxxDef macros
- * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
- * Added: osKernelInitialize
- * Version 1.02
- * Control functions for short timeouts in microsecond resolution:
- * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- * Removed: osSignalGet
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2013 ARM LIMITED
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
-
-
-#ifndef _CMSIS_OS_H
-#define _CMSIS_OS_H
-
-/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
-#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
-
-/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
-#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
-
-/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
-#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
-
-/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
-#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
-#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
-#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
-#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
-#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
-#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function
-#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
-#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
-
-#include
-#include
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-// ==== Enumeration, structures, defines ====
-
-/// Priority used for thread control.
-/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
-typedef enum {
- osPriorityIdle = -3, ///< priority: idle (lowest)
- osPriorityLow = -2, ///< priority: low
- osPriorityBelowNormal = -1, ///< priority: below normal
- osPriorityNormal = 0, ///< priority: normal (default)
- osPriorityAboveNormal = +1, ///< priority: above normal
- osPriorityHigh = +2, ///< priority: high
- osPriorityRealtime = +3, ///< priority: realtime (highest)
- osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
-} osPriority;
-
-/// Timeout value.
-/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
-#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
-
-/// Status code values returned by CMSIS-RTOS functions.
-/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
-typedef enum {
- osOK = 0, ///< function completed; no error or event occurred.
- osEventSignal = 0x08, ///< function completed; signal event occurred.
- osEventMessage = 0x10, ///< function completed; message event occurred.
- osEventMail = 0x20, ///< function completed; mail event occurred.
- osEventTimeout = 0x40, ///< function completed; timeout occurred.
- osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
- osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
- osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
- osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
- osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
- osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
- osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
- osErrorValue = 0x86, ///< value of a parameter is out of range.
- osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
- os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
-} osStatus;
-
-
-/// Timer type value for the timer definition.
-/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
-typedef enum {
- osTimerOnce = 0, ///< one-shot timer
- osTimerPeriodic = 1 ///< repeating timer
-} os_timer_type;
-
-/// Entry point of a thread.
-/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
-typedef void (*os_pthread) (void const *argument);
-
-/// Entry point of a timer call back function.
-/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
-typedef void (*os_ptimer) (void const *argument);
-
-// >>> the following data type definitions may shall adapted towards a specific RTOS
-
-/// Thread ID identifies the thread (pointer to a thread control block).
-/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_thread_cb *osThreadId;
-
-/// Timer ID identifies the timer (pointer to a timer control block).
-/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_timer_cb *osTimerId;
-
-/// Mutex ID identifies the mutex (pointer to a mutex control block).
-/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_mutex_cb *osMutexId;
-
-/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
-/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_semaphore_cb *osSemaphoreId;
-
-/// Pool ID identifies the memory pool (pointer to a memory pool control block).
-/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_pool_cb *osPoolId;
-
-/// Message ID identifies the message queue (pointer to a message queue control block).
-/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_messageQ_cb *osMessageQId;
-
-/// Mail ID identifies the mail queue (pointer to a mail queue control block).
-/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_mailQ_cb *osMailQId;
-
-
-/// Thread Definition structure contains startup information of a thread.
-/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_thread_def {
- os_pthread pthread; ///< start address of thread function
- osPriority tpriority; ///< initial thread priority
- uint32_t instances; ///< maximum number of instances of that thread function
- uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
-} osThreadDef_t;
-
-/// Timer Definition structure contains timer parameters.
-/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_timer_def {
- os_ptimer ptimer; ///< start address of a timer function
-} osTimerDef_t;
-
-/// Mutex Definition structure contains setup information for a mutex.
-/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_mutex_def {
- uint32_t dummy; ///< dummy value.
-} osMutexDef_t;
-
-/// Semaphore Definition structure contains setup information for a semaphore.
-/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_semaphore_def {
- uint32_t dummy; ///< dummy value.
-} osSemaphoreDef_t;
-
-/// Definition structure for memory block allocation.
-/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_pool_def {
- uint32_t pool_sz; ///< number of items (elements) in the pool
- uint32_t item_sz; ///< size of an item
- void *pool; ///< pointer to memory for pool
-} osPoolDef_t;
-
-/// Definition structure for message queue.
-/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_messageQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- uint32_t item_sz; ///< size of an item
- void *pool; ///< memory array for messages
-} osMessageQDef_t;
-
-/// Definition structure for mail queue.
-/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_mailQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- uint32_t item_sz; ///< size of an item
- void *pool; ///< memory array for mail
-} osMailQDef_t;
-
-/// Event structure contains detailed information about an event.
-/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
-/// However the struct may be extended at the end.
-typedef struct {
- osStatus status; ///< status code: event or error information
- union {
- uint32_t v; ///< message as 32-bit value
- void *p; ///< message or mail as void pointer
- int32_t signals; ///< signal flags
- } value; ///< event value
- union {
- osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
- osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
- } def; ///< event definition
-} osEvent;
-
-
-// ==== Kernel Control Functions ====
-
-/// Initialize the RTOS Kernel for creating objects.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
-osStatus osKernelInitialize (void);
-
-/// Start the RTOS Kernel.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
-osStatus osKernelStart (void);
-
-/// Check if the RTOS kernel is already started.
-/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
-/// \return 0 RTOS is not started, 1 RTOS is started.
-int32_t osKernelRunning(void);
-
-#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
-
-/// Get the RTOS kernel system timer counter
-/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
-/// \return RTOS kernel system timer as 32-bit value
-uint32_t osKernelSysTick (void);
-
-/// The RTOS kernel system timer frequency in Hz
-/// \note Reflects the system timer setting and is typically defined in a configuration file.
-#define osKernelSysTickFrequency 100000000
-
-/// Convert a microseconds value to a RTOS kernel system timer value.
-/// \param microsec time value in microseconds.
-/// \return time value normalized to the \ref osKernelSysTickFrequency
-#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
-
-#endif // System Timer available
-
-// ==== Thread Management ====
-
-/// Create a Thread Definition with function, priority, and stack requirements.
-/// \param name name of the thread function.
-/// \param priority initial priority of the thread function.
-/// \param instances number of possible thread instances.
-/// \param stacksz stack size (in bytes) requirements for the thread function.
-/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osThreadDef(name, priority, instances, stacksz) \
-extern const osThreadDef_t os_thread_def_##name
-#else // define the object
-#define osThreadDef(name, priority, instances, stacksz) \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), (priority), (instances), (stacksz) }
-#endif
-
-/// Access a Thread definition.
-/// \param name name of the thread definition object.
-/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osThread(name) \
-&os_thread_def_##name
-
-/// Create a thread and add it to Active Threads and set it to state READY.
-/// \param[in] thread_def thread definition referenced with \ref osThread.
-/// \param[in] argument pointer that is passed to the thread function as start argument.
-/// \return thread ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
-
-/// Return the thread ID of the current running thread.
-/// \return thread ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
-osThreadId osThreadGetId (void);
-
-/// Terminate execution of a thread and remove it from Active Threads.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
-osStatus osThreadTerminate (osThreadId thread_id);
-
-/// Pass control to next thread that is in state \b READY.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
-osStatus osThreadYield (void);
-
-/// Change priority of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] priority new priority value for the thread function.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
-osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
-
-/// Get current priority of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return current priority value of the thread function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
-osPriority osThreadGetPriority (osThreadId thread_id);
-
-
-// ==== Generic Wait Functions ====
-
-/// Wait for Timeout (Time Delay).
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
-/// \return status code that indicates the execution status of the function.
-osStatus osDelay (uint32_t millisec);
-
-#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
-
-/// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return event that contains signal, message, or mail information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
-osEvent osWait (uint32_t millisec);
-
-#endif // Generic Wait available
-
-
-// ==== Timer Management Functions ====
-/// Define a Timer object.
-/// \param name name of the timer object.
-/// \param function name of the timer call back function.
-/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osTimerDef(name, function) \
-extern const osTimerDef_t os_timer_def_##name
-#else // define the object
-#define osTimerDef(name, function) \
-const osTimerDef_t os_timer_def_##name = \
-{ (function) }
-#endif
-
-/// Access a Timer definition.
-/// \param name name of the timer object.
-/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osTimer(name) \
-&os_timer_def_##name
-
-/// Create a timer.
-/// \param[in] timer_def timer object referenced with \ref osTimer.
-/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
-/// \param[in] argument argument to the timer call back function.
-/// \return timer ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
-
-/// Start or restart a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
-osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
-
-/// Stop the timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
-osStatus osTimerStop (osTimerId timer_id);
-
-/// Delete a timer that was created by \ref osTimerCreate.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
-osStatus osTimerDelete (osTimerId timer_id);
-
-
-// ==== Signal Management ====
-
-/// Set the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that should be set.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
-/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
-int32_t osSignalSet (osThreadId thread_id, int32_t signals);
-
-/// Clear the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
-/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
-int32_t osSignalClear (osThreadId thread_id, int32_t signals);
-
-/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
-/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event flag information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
-osEvent osSignalWait (int32_t signals, uint32_t millisec);
-
-
-// ==== Mutex Management ====
-
-/// Define a Mutex.
-/// \param name name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMutexDef(name) \
-extern const osMutexDef_t os_mutex_def_##name
-#else // define the object
-#define osMutexDef(name) \
-const osMutexDef_t os_mutex_def_##name = { 0 }
-#endif
-
-/// Access a Mutex definition.
-/// \param name name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMutex(name) \
-&os_mutex_def_##name
-
-/// Create and Initialize a Mutex object.
-/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
-/// \return mutex ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
-
-/// Wait until a Mutex becomes available.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
-osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
-
-/// Release a Mutex that was obtained by \ref osMutexWait.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
-osStatus osMutexRelease (osMutexId mutex_id);
-
-/// Delete a Mutex that was created by \ref osMutexCreate.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
-osStatus osMutexDelete (osMutexId mutex_id);
-
-
-// ==== Semaphore Management Functions ====
-
-#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
-
-/// Define a Semaphore object.
-/// \param name name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osSemaphoreDef(name) \
-extern const osSemaphoreDef_t os_semaphore_def_##name
-#else // define the object
-#define osSemaphoreDef(name) \
-const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
-#endif
-
-/// Access a Semaphore definition.
-/// \param name name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osSemaphore(name) \
-&os_semaphore_def_##name
-
-/// Create and Initialize a Semaphore object used for managing resources.
-/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
-/// \param[in] count number of available resources.
-/// \return semaphore ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
-
-/// Wait until a Semaphore token becomes available.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return number of available tokens, or -1 in case of incorrect parameters.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
-
-/// Release a Semaphore token.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
-osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
-
-/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
-osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
-
-#endif // Semaphore available
-
-
-// ==== Memory Pool Management Functions ====
-
-#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
-
-/// \brief Define a Memory Pool.
-/// \param name name of the memory pool.
-/// \param no maximum number of blocks (objects) in the memory pool.
-/// \param type data type of a single block (object).
-/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osPoolDef(name, no, type) \
-extern const osPoolDef_t os_pool_def_##name
-#else // define the object
-#define osPoolDef(name, no, type) \
-const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), NULL }
-#endif
-
-/// \brief Access a Memory Pool definition.
-/// \param name name of the memory pool
-/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osPool(name) \
-&os_pool_def_##name
-
-/// Create and Initialize a memory pool.
-/// \param[in] pool_def memory pool definition referenced with \ref osPool.
-/// \return memory pool ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
-osPoolId osPoolCreate (const osPoolDef_t *pool_def);
-
-/// Allocate a memory block from a memory pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
-void *osPoolAlloc (osPoolId pool_id);
-
-/// Allocate a memory block from a memory pool and set memory block to zero.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
-void *osPoolCAlloc (osPoolId pool_id);
-
-/// Return an allocated memory block back to a specific memory pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \param[in] block address of the allocated memory block that is returned to the memory pool.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
-osStatus osPoolFree (osPoolId pool_id, void *block);
-
-#endif // Memory Pool Management available
-
-
-// ==== Message Queue Management Functions ====
-
-#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
-
-/// \brief Create a Message Queue Definition.
-/// \param name name of the queue.
-/// \param queue_sz maximum number of messages in the queue.
-/// \param type data type of a single message element (for debugger).
-/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMessageQDef(name, queue_sz, type) \
-extern const osMessageQDef_t os_messageQ_def_##name
-#else // define the object
-#define osMessageQDef(name, queue_sz, type) \
-const osMessageQDef_t os_messageQ_def_##name = \
-{ (queue_sz), sizeof (type) }
-#endif
-
-/// \brief Access a Message Queue Definition.
-/// \param name name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMessageQ(name) \
-&os_messageQ_def_##name
-
-/// Create and Initialize a Message Queue.
-/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return message queue ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
-
-/// Put a Message to a Queue.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] info message information.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
-
-/// Get a Message or Wait for a Message from a Queue.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event information that includes status code.
-/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
-osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
-
-#endif // Message Queues available
-
-
-// ==== Mail Queue Management Functions ====
-
-#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
-
-/// \brief Create a Mail Queue Definition.
-/// \param name name of the queue
-/// \param queue_sz maximum number of messages in queue
-/// \param type data type of a single message element
-/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMailQDef(name, queue_sz, type) \
-extern const osMailQDef_t os_mailQ_def_##name
-#else // define the object
-#define osMailQDef(name, queue_sz, type) \
-const osMailQDef_t os_mailQ_def_##name = \
-{ (queue_sz), sizeof (type) }
-#endif
-
-/// \brief Access a Mail Queue Definition.
-/// \param name name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMailQ(name) \
-&os_mailQ_def_##name
-
-/// Create and Initialize mail queue.
-/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return mail queue ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
-
-/// Allocate a memory block from a mail.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Allocate a memory block from a mail and set memory block to zero.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Put a mail to a queue.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
-osStatus osMailPut (osMailQId queue_id, void *mail);
-
-/// Get a mail from a queue.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return event that contains mail information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
-osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
-
-/// Free a memory block from a mail.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
-osStatus osMailFree (osMailQId queue_id, void *mail);
-
-#endif // Mail Queues available
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _CMSIS_OS_H
diff --git a/KugleFirmware/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/KugleFirmware/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h
deleted file mode 100644
index d25edfa..0000000
--- a/KugleFirmware/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h
+++ /dev/null
@@ -1,745 +0,0 @@
-/*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 10. January 2017
- * $Revision: V2.1.0
- *
- * Project: CMSIS-RTOS2 API
- * Title: cmsis_os2.h header file
- *
- * Version 2.1.0
- * Support for critical and uncritical sections (nesting safe):
- * - updated: osKernelLock, osKernelUnlock
- * - added: osKernelRestoreLock
- * Updated Thread and Event Flags:
- * - changed flags parameter and return type from int32_t to uint32_t
- * Version 2.0.0
- * Initial Release
- *---------------------------------------------------------------------------*/
-
-#ifndef CMSIS_OS2_H_
-#define CMSIS_OS2_H_
-
-#ifndef __NO_RETURN
-#if defined(__CC_ARM)
-#define __NO_RETURN __declspec(noreturn)
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#define __NO_RETURN __attribute__((noreturn))
-#elif defined(__GNUC__)
-#define __NO_RETURN __attribute__((noreturn))
-#elif defined(__ICCARM__)
-#define __NO_RETURN __noreturn
-#else
-#define __NO_RETURN
-#endif
-#endif
-
-#include
-#include
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-// ==== Enumerations, structures, defines ====
-
-/// Version information.
-typedef struct {
- uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
- uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
-} osVersion_t;
-
-/// Kernel state.
-typedef enum {
- osKernelInactive = 0, ///< Inactive.
- osKernelReady = 1, ///< Ready.
- osKernelRunning = 2, ///< Running.
- osKernelLocked = 3, ///< Locked.
- osKernelSuspended = 4, ///< Suspended.
- osKernelError = -1, ///< Error.
- osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
-} osKernelState_t;
-
-/// Thread state.
-typedef enum {
- osThreadInactive = 0, ///< Inactive.
- osThreadReady = 1, ///< Ready.
- osThreadRunning = 2, ///< Running.
- osThreadBlocked = 3, ///< Blocked.
- osThreadTerminated = 4, ///< Terminated.
- osThreadError = -1, ///< Error.
- osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
-} osThreadState_t;
-
-/// Priority values.
-typedef enum {
- osPriorityNone = 0, ///< No priority (not initialized).
- osPriorityIdle = 1, ///< Reserved for Idle thread.
- osPriorityLow = 8, ///< Priority: low
- osPriorityLow1 = 8+1, ///< Priority: low + 1
- osPriorityLow2 = 8+2, ///< Priority: low + 2
- osPriorityLow3 = 8+3, ///< Priority: low + 3
- osPriorityLow4 = 8+4, ///< Priority: low + 4
- osPriorityLow5 = 8+5, ///< Priority: low + 5
- osPriorityLow6 = 8+6, ///< Priority: low + 6
- osPriorityLow7 = 8+7, ///< Priority: low + 7
- osPriorityBelowNormal = 16, ///< Priority: below normal
- osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
- osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
- osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
- osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
- osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
- osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
- osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
- osPriorityNormal = 24, ///< Priority: normal
- osPriorityNormal1 = 24+1, ///< Priority: normal + 1
- osPriorityNormal2 = 24+2, ///< Priority: normal + 2
- osPriorityNormal3 = 24+3, ///< Priority: normal + 3
- osPriorityNormal4 = 24+4, ///< Priority: normal + 4
- osPriorityNormal5 = 24+5, ///< Priority: normal + 5
- osPriorityNormal6 = 24+6, ///< Priority: normal + 6
- osPriorityNormal7 = 24+7, ///< Priority: normal + 7
- osPriorityAboveNormal = 32, ///< Priority: above normal
- osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
- osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
- osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
- osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
- osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
- osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
- osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
- osPriorityHigh = 40, ///< Priority: high
- osPriorityHigh1 = 40+1, ///< Priority: high + 1
- osPriorityHigh2 = 40+2, ///< Priority: high + 2
- osPriorityHigh3 = 40+3, ///< Priority: high + 3
- osPriorityHigh4 = 40+4, ///< Priority: high + 4
- osPriorityHigh5 = 40+5, ///< Priority: high + 5
- osPriorityHigh6 = 40+6, ///< Priority: high + 6
- osPriorityHigh7 = 40+7, ///< Priority: high + 7
- osPriorityRealtime = 48, ///< Priority: realtime
- osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
- osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
- osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
- osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
- osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
- osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
- osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
- osPriorityISR = 56, ///< Reserved for ISR deferred thread.
- osPriorityError = -1, ///< System cannot determine priority or illegal priority.
- osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
-} osPriority_t;
-
-/// Entry point of a thread.
-typedef void (*osThreadFunc_t) (void *argument);
-
-/// Entry point of a timer call back function.
-typedef void (*osTimerFunc_t) (void *argument);
-
-/// Timer type.
-typedef enum {
- osTimerOnce = 0, ///< One-shot timer.
- osTimerPeriodic = 1 ///< Repeating timer.
-} osTimerType_t;
-
-/// Timeout value.
-#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
-
-/// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
-#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
-#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
-#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
-
-/// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
-#define osFlagsError 0x80000000U ///< Error indicator.
-#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
-#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
-#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
-#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
-#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
-
-/// Thread attributes (attr_bits in \ref osThreadAttr_t).
-#define osThreadDetached 0x00000000U ///< Thread created in detached state (default)
-#define osThreadJoinable 0x00000001U ///< Thread created in joinable state
-
-/// Mutex attributes (attr_bits in \ref osMutexAttr_t).
-#define osMutexRecursive 0x00000001U ///< Recursive mutex.
-#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
-#define osMutexRobust 0x00000008U ///< Robust mutex.
-
-/// Status code values returned by CMSIS-RTOS functions.
-typedef enum {
- osOK = 0, ///< Operation completed successfully.
- osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
- osErrorTimeout = -2, ///< Operation not completed within the timeout period.
- osErrorResource = -3, ///< Resource not available.
- osErrorParameter = -4, ///< Parameter error.
- osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
- osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
- osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
-} osStatus_t;
-
-
-/// \details Thread ID identifies the thread.
-typedef void *osThreadId_t;
-
-/// \details Timer ID identifies the timer.
-typedef void *osTimerId_t;
-
-/// \details Event Flags ID identifies the event flags.
-typedef void *osEventFlagsId_t;
-
-/// \details Mutex ID identifies the mutex.
-typedef void *osMutexId_t;
-
-/// \details Semaphore ID identifies the semaphore.
-typedef void *osSemaphoreId_t;
-
-/// \details Memory Pool ID identifies the memory pool.
-typedef void *osMemoryPoolId_t;
-
-/// \details Message Queue ID identifies the message queue.
-typedef void *osMessageQueueId_t;
-
-
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
-
-
-/// Attributes structure for thread.
-typedef struct {
- const char *name; ///< name of the thread
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
- void *stack_mem; ///< memory for stack
- uint32_t stack_size; ///< size of stack
- osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
- TZ_ModuleId_t tz_module; ///< TrustZone module identifier
- uint32_t reserved; ///< reserved (must be 0)
-} osThreadAttr_t;
-
-/// Attributes structure for timer.
-typedef struct {
- const char *name; ///< name of the timer
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
-} osTimerAttr_t;
-
-/// Attributes structure for event flags.
-typedef struct {
- const char *name; ///< name of the event flags
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
-} osEventFlagsAttr_t;
-
-/// Attributes structure for mutex.
-typedef struct {
- const char *name; ///< name of the mutex
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
-} osMutexAttr_t;
-
-/// Attributes structure for semaphore.
-typedef struct {
- const char *name; ///< name of the semaphore
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
-} osSemaphoreAttr_t;
-
-/// Attributes structure for memory pool.
-typedef struct {
- const char *name; ///< name of the memory pool
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
- void *mp_mem; ///< memory for data storage
- uint32_t mp_size; ///< size of provided memory for data storage
-} osMemoryPoolAttr_t;
-
-/// Attributes structure for message queue.
-typedef struct {
- const char *name; ///< name of the message queue
- uint32_t attr_bits; ///< attribute bits
- void *cb_mem; ///< memory for control block
- uint32_t cb_size; ///< size of provided memory for control block
- void *mq_mem; ///< memory for data storage
- uint32_t mq_size; ///< size of provided memory for data storage
-} osMessageQueueAttr_t;
-
-
-// ==== Kernel Management Functions ====
-
-/// Initialize the RTOS Kernel.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osKernelInitialize (void);
-
-/// Get RTOS Kernel Information.
-/// \param[out] version pointer to buffer for retrieving version information.
-/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
-/// \param[in] id_size size of buffer for kernel identification string.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
-
-/// Get the current RTOS Kernel state.
-/// \return current RTOS Kernel state.
-osKernelState_t osKernelGetState (void);
-
-/// Start the RTOS Kernel scheduler.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osKernelStart (void);
-
-/// Lock the RTOS Kernel scheduler.
-/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
-int32_t osKernelLock (void);
-
-/// Unlock the RTOS Kernel scheduler.
-/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
-int32_t osKernelUnlock (void);
-
-/// Restore the RTOS Kernel scheduler lock state.
-/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
-/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
-int32_t osKernelRestoreLock (int32_t lock);
-
-/// Suspend the RTOS Kernel scheduler.
-/// \return time in ticks, for how long the system can sleep or power-down.
-uint32_t osKernelSuspend (void);
-
-/// Resume the RTOS Kernel scheduler.
-/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
-void osKernelResume (uint32_t sleep_ticks);
-
-/// Get the RTOS kernel tick count.
-/// \return RTOS kernel current tick count.
-uint64_t osKernelGetTickCount (void);
-
-/// Get the RTOS kernel tick frequency.
-/// \return frequency of the kernel tick.
-uint32_t osKernelGetTickFreq (void);
-
-/// Get the RTOS kernel system timer count.
-/// \return RTOS kernel current system timer count as 32-bit value.
-uint32_t osKernelGetSysTimerCount (void);
-
-/// Get the RTOS kernel system timer frequency.
-/// \return frequency of the system timer.
-uint32_t osKernelGetSysTimerFreq (void);
-
-
-// ==== Thread Management Functions ====
-
-/// Create a thread and add it to Active Threads.
-/// \param[in] func thread function.
-/// \param[in] argument pointer that is passed to the thread function as start argument.
-/// \param[in] attr thread attributes; NULL: default values.
-/// \return thread ID for reference by other functions or NULL in case of error.
-osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
-
-/// Get name of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return name as NULL terminated string.
-const char *osThreadGetName (osThreadId_t thread_id);
-
-/// Return the thread ID of the current running thread.
-/// \return thread ID for reference by other functions or NULL in case of error.
-osThreadId_t osThreadGetId (void);
-
-/// Get current thread state of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return current thread state of the specified thread.
-osThreadState_t osThreadGetState (osThreadId_t thread_id);
-
-/// Get stack size of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return stack size in bytes.
-uint32_t osThreadGetStackSize (osThreadId_t thread_id);
-
-/// Get available stack space of a thread based on stack watermark recording during execution.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return remaining stack space in bytes.
-uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
-
-/// Change priority of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \param[in] priority new priority value for the thread function.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
-
-/// Get current priority of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return current priority value of the specified thread.
-osPriority_t osThreadGetPriority (osThreadId_t thread_id);
-
-/// Pass control to next thread that is in state \b READY.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadYield (void);
-
-/// Suspend execution of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadSuspend (osThreadId_t thread_id);
-
-/// Resume execution of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadResume (osThreadId_t thread_id);
-
-/// Detach a thread (thread storage can be reclaimed when thread terminates).
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadDetach (osThreadId_t thread_id);
-
-/// Wait for specified thread to terminate.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadJoin (osThreadId_t thread_id);
-
-/// Terminate execution of current running thread.
-__NO_RETURN void osThreadExit (void);
-
-/// Terminate execution of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osThreadTerminate (osThreadId_t thread_id);
-
-/// Get number of active threads.
-/// \return number of active threads.
-uint32_t osThreadGetCount (void);
-
-/// Enumerate active threads.
-/// \param[out] thread_array pointer to array for retrieving thread IDs.
-/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
-/// \return number of enumerated threads.
-uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
-
-
-// ==== Thread Flags Functions ====
-
-/// Set the specified Thread Flags of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
-/// \param[in] flags specifies the flags of the thread that shall be set.
-/// \return thread flags after setting or error code if highest bit set.
-uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
-
-/// Clear the specified Thread Flags of current running thread.
-/// \param[in] flags specifies the flags of the thread that shall be cleared.
-/// \return thread flags before clearing or error code if highest bit set.
-uint32_t osThreadFlagsClear (uint32_t flags);
-
-/// Get the current Thread Flags of current running thread.
-/// \return current thread flags.
-uint32_t osThreadFlagsGet (void);
-
-/// Wait for one or more Thread Flags of the current running thread to become signaled.
-/// \param[in] flags specifies the flags to wait for.
-/// \param[in] options specifies flags options (osFlagsXxxx).
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return thread flags before clearing or error code if highest bit set.
-uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
-
-
-// ==== Generic Wait Functions ====
-
-/// Wait for Timeout (Time Delay).
-/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
-/// \return status code that indicates the execution status of the function.
-osStatus_t osDelay (uint32_t ticks);
-
-/// Wait until specified time.
-/// \param[in] ticks absolute time in ticks
-/// \return status code that indicates the execution status of the function.
-osStatus_t osDelayUntil (uint64_t ticks);
-
-
-// ==== Timer Management Functions ====
-
-/// Create and Initialize a timer.
-/// \param[in] func start address of a timer call back function.
-/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
-/// \param[in] argument argument to the timer call back function.
-/// \param[in] attr timer attributes; NULL: default values.
-/// \return timer ID for reference by other functions or NULL in case of error.
-osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
-
-/// Get name of a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
-/// \return name as NULL terminated string.
-const char *osTimerGetName (osTimerId_t timer_id);
-
-/// Start or restart a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
-/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
-
-/// Stop a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osTimerStop (osTimerId_t timer_id);
-
-/// Check if a timer is running.
-/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
-/// \return 0 not running, 1 running.
-uint32_t osTimerIsRunning (osTimerId_t timer_id);
-
-/// Delete a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osTimerDelete (osTimerId_t timer_id);
-
-
-// ==== Event Flags Management Functions ====
-
-/// Create and Initialize an Event Flags object.
-/// \param[in] attr event flags attributes; NULL: default values.
-/// \return event flags ID for reference by other functions or NULL in case of error.
-osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
-
-/// Get name of an Event Flags object.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \return name as NULL terminated string.
-const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
-
-/// Set the specified Event Flags.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \param[in] flags specifies the flags that shall be set.
-/// \return event flags after setting or error code if highest bit set.
-uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
-
-/// Clear the specified Event Flags.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \param[in] flags specifies the flags that shall be cleared.
-/// \return event flags before clearing or error code if highest bit set.
-uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
-
-/// Get the current Event Flags.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \return current event flags.
-uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
-
-/// Wait for one or more Event Flags to become signaled.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \param[in] flags specifies the flags to wait for.
-/// \param[in] options specifies flags options (osFlagsXxxx).
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event flags before clearing or error code if highest bit set.
-uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
-
-/// Delete an Event Flags object.
-/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
-
-
-// ==== Mutex Management Functions ====
-
-/// Create and Initialize a Mutex object.
-/// \param[in] attr mutex attributes; NULL: default values.
-/// \return mutex ID for reference by other functions or NULL in case of error.
-osMutexId_t osMutexNew (const osMutexAttr_t *attr);
-
-/// Get name of a Mutex object.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
-/// \return name as NULL terminated string.
-const char *osMutexGetName (osMutexId_t mutex_id);
-
-/// Acquire a Mutex or timeout if it is locked.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
-
-/// Release a Mutex that was acquired by \ref osMutexAcquire.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMutexRelease (osMutexId_t mutex_id);
-
-/// Get Thread which owns a Mutex object.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
-/// \return thread ID of owner thread or NULL when mutex was not acquired.
-osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
-
-/// Delete a Mutex object.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMutexDelete (osMutexId_t mutex_id);
-
-
-// ==== Semaphore Management Functions ====
-
-/// Create and Initialize a Semaphore object.
-/// \param[in] max_count maximum number of available tokens.
-/// \param[in] initial_count initial number of available tokens.
-/// \param[in] attr semaphore attributes; NULL: default values.
-/// \return semaphore ID for reference by other functions or NULL in case of error.
-osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
-
-/// Get name of a Semaphore object.
-/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
-/// \return name as NULL terminated string.
-const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
-
-/// Acquire a Semaphore token or timeout if no tokens are available.
-/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
-
-/// Release a Semaphore token that was acquired by \ref osSemaphoreAcquire.
-/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
-
-/// Get current Semaphore token count.
-/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
-/// \return number of tokens available.
-uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
-
-/// Delete a Semaphore object.
-/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
-
-
-// ==== Memory Pool Management Functions ====
-
-/// Create and Initialize a Memory Pool object.
-/// \param[in] block_count maximum number of memory blocks in memory pool.
-/// \param[in] block_size memory block size in bytes.
-/// \param[in] attr memory pool attributes; NULL: default values.
-/// \return memory pool ID for reference by other functions or NULL in case of error.
-osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
-
-/// Get name of a Memory Pool object.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return name as NULL terminated string.
-const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
-
-/// Allocate a memory block from a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return address of the allocated memory block or NULL in case of no memory is available.
-void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
-
-/// Return an allocated memory block back to a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \param[in] block address of the allocated memory block to be returned to the memory pool.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
-
-/// Get maximum number of memory blocks in a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return maximum number of memory blocks.
-uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
-
-/// Get memory block size in a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return memory block size in bytes.
-uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
-
-/// Get number of memory blocks used in a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return number of memory blocks used.
-uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
-
-/// Get number of memory blocks available in a Memory Pool.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return number of memory blocks available.
-uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
-
-/// Delete a Memory Pool object.
-/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
-
-
-// ==== Message Queue Management Functions ====
-
-/// Create and Initialize a Message Queue object.
-/// \param[in] msg_count maximum number of messages in queue.
-/// \param[in] msg_size maximum message size in bytes.
-/// \param[in] attr message queue attributes; NULL: default values.
-/// \return message queue ID for reference by other functions or NULL in case of error.
-osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
-
-/// Get name of a Message Queue object.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return name as NULL terminated string.
-const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
-
-/// Put a Message into a Queue or timeout if Queue is full.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
-/// \param[in] msg_prio message priority.
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
-
-/// Get a Message from a Queue or timeout if Queue is empty.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
-/// \param[out] msg_prio pointer to buffer for message priority or NULL.
-/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
-
-/// Get maximum number of messages in a Message Queue.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return maximum number of messages.
-uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
-
-/// Get maximum message size in a Memory Pool.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return maximum message size in bytes.
-uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
-
-/// Get number of queued messages in a Message Queue.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return number of queued messages.
-uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
-
-/// Get number of available slots for messages in a Message Queue.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return number of available slots for messages.
-uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
-
-/// Reset a Message Queue to initial empty state.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
-
-/// Delete a Message Queue object.
-/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
-/// \return status code that indicates the execution status of the function.
-osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // CMSIS_OS2_H_
diff --git a/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os.h
deleted file mode 100644
index 5920d14..0000000
--- a/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os.h
+++ /dev/null
@@ -1,911 +0,0 @@
-/*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 10. January 2017
- * $Revision: V2.1.0
- *
- * Project: CMSIS-RTOS API
- * Title: cmsis_os.h template header file
- *
- * Version 0.02
- * Initial Proposal Phase
- * Version 0.03
- * osKernelStart added, optional feature: main started as thread
- * osSemaphores have standard behavior
- * osTimerCreate does not start the timer, added osTimerStart
- * osThreadPass is renamed to osThreadYield
- * Version 1.01
- * Support for C++ interface
- * - const attribute removed from the osXxxxDef_t typedefs
- * - const attribute added to the osXxxxDef macros
- * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
- * Added: osKernelInitialize
- * Version 1.02
- * Control functions for short timeouts in microsecond resolution:
- * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- * Removed: osSignalGet
- * Version 2.0.0
- * OS objects creation without macros (dynamic creation and resource allocation):
- * - added: osXxxxNew functions which replace osXxxxCreate
- * - added: osXxxxAttr_t structures
- * - deprecated: osXxxxCreate functions, osXxxxDef_t structures
- * - deprecated: osXxxxDef and osXxxx macros
- * osStatus codes simplified and renamed to osStatus_t
- * osEvent return structure deprecated
- * Kernel:
- * - added: osKernelInfo_t and osKernelGetInfo
- * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
- * - added: osKernelLock, osKernelUnlock
- * - added: osKernelSuspend, osKernelResume
- * - added: osKernelGetTickCount, osKernelGetTickFreq
- * - renamed osKernelSysTick to osKernelGetSysTimerCount
- * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
- * - deprecated osKernelSysTickMicroSec
- * Thread:
- * - extended number of thread priorities
- * - renamed osPrioriry to osPrioriry_t
- * - replaced osThreadCreate with osThreadNew
- * - added: osThreadGetName
- * - added: osThreadState_t and osThreadGetState
- * - added: osThreadGetStackSize, osThreadGetStackSpace
- * - added: osThreadSuspend, osThreadResume
- * - added: osThreadJoin, osThreadDetach, osThreadExit
- * - added: osThreadGetCount, osThreadEnumerate
- * - added: Thread Flags (moved from Signals)
- * Signals:
- * - renamed osSignals to osThreadFlags (moved to Thread Flags)
- * - changed return value of Set/Clear/Wait functions
- * - Clear function limited to current running thread
- * - extended Wait function (options)
- * - added: osThreadFlagsGet
- * Event Flags:
- * - added new independent object for handling Event Flags
- * Delay and Wait functions:
- * - added: osDelayUntil
- * - deprecated: osWait
- * Timer:
- * - replaced osTimerCreate with osTimerNew
- * - added: osTimerGetName, osTimerIsRunning
- * Mutex:
- * - extended: attributes (Recursive, Priority Inherit, Robust)
- * - replaced osMutexCreate with osMutexNew
- * - renamed osMutexWait to osMutexAcquire
- * - added: osMutexGetName, osMutexGetOwner
- * Semaphore:
- * - extended: maximum and initial token count
- * - replaced osSemaphoreCreate with osSemaphoreNew
- * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
- * - added: osSemaphoreGetName, osSemaphoreGetCount
- * Memory Pool:
- * - using osMemoryPool prefix instead of osPool
- * - replaced osPoolCreate with osMemoryPoolNew
- * - extended osMemoryPoolAlloc (timeout)
- * - added: osMemoryPoolGetName
- * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
- * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
- * - added: osMemoryPoolDelete
- * - deprecated: osPoolCAlloc
- * Message Queue:
- * - extended: fixed size message instead of a single 32-bit value
- * - using osMessageQueue prefix instead of osMessage
- * - replaced osMessageCreate with osMessageQueueNew
- * - updated: osMessageQueuePut, osMessageQueueGet
- * - added: osMessageQueueGetName
- * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
- * - added: osMessageQueueGetCount, osMessageQueueGetSpace
- * - added: osMessageQueueReset, osMessageQueueDelete
- * Mail Queue:
- * - deprecated (superseded by extended Message Queue functionality)
- * Version 2.1.0
- * Support for critical and uncritical sections (nesting safe):
- * - updated: osKernelLock, osKernelUnlock
- * - added: osKernelRestoreLock
- * Updated Thread and Event Flags:
- * - changed flags parameter and return type from int32_t to uint32_t
- *---------------------------------------------------------------------------*/
-
-#ifndef CMSIS_OS_H_
-#define CMSIS_OS_H_
-
-/// \b osCMSIS identifies the CMSIS-RTOS API version.
-#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
-
-/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
-#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0])
-
-/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel.
-#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string
-
-/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features.
-#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
-#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread
-#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
-#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
-#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
-#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
-#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
-#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
-
-#if (osCMSIS >= 0x20000U)
-#include "cmsis_os2.h"
-#else
-#include
-#include
-#endif
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-// ==== Enumerations, structures, defines ====
-
-/// Priority values.
-#if (osCMSIS < 0x20000U)
-typedef enum {
- osPriorityIdle = -3, ///< Priority: idle (lowest)
- osPriorityLow = -2, ///< Priority: low
- osPriorityBelowNormal = -1, ///< Priority: below normal
- osPriorityNormal = 0, ///< Priority: normal (default)
- osPriorityAboveNormal = +1, ///< Priority: above normal
- osPriorityHigh = +2, ///< Priority: high
- osPriorityRealtime = +3, ///< Priority: realtime (highest)
- osPriorityError = 0x84, ///< System cannot determine priority or illegal priority.
- osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
-} osPriority;
-#else
-#define osPriority osPriority_t
-#endif
-
-/// Entry point of a thread.
-typedef void (*os_pthread) (void const *argument);
-
-/// Entry point of a timer call back function.
-typedef void (*os_ptimer) (void const *argument);
-
-/// Timer type.
-#if (osCMSIS < 0x20000U)
-typedef enum {
- osTimerOnce = 0, ///< One-shot timer.
- osTimerPeriodic = 1 ///< Repeating timer.
-} os_timer_type;
-#else
-#define os_timer_type osTimerType_t
-#endif
-
-/// Timeout value.
-#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
-
-/// Status code values returned by CMSIS-RTOS functions.
-#if (osCMSIS < 0x20000U)
-typedef enum {
- osOK = 0, ///< Function completed; no error or event occurred.
- osEventSignal = 0x08, ///< Function completed; signal event occurred.
- osEventMessage = 0x10, ///< Function completed; message event occurred.
- osEventMail = 0x20, ///< Function completed; mail event occurred.
- osEventTimeout = 0x40, ///< Function completed; timeout occurred.
- osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
- osErrorResource = 0x81, ///< Resource not available: a specified resource was not available.
- osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period.
- osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
- osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object.
- osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority.
- osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
- osErrorValue = 0x86, ///< Value of a parameter is out of range.
- osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits.
- osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
-} osStatus;
-#else
-typedef int32_t osStatus;
-#define osEventSignal (0x08)
-#define osEventMessage (0x10)
-#define osEventMail (0x20)
-#define osEventTimeout (0x40)
-#define osErrorOS osError
-#define osErrorTimeoutResource osErrorTimeout
-#define osErrorISRRecursive (-126)
-#define osErrorValue (-127)
-#define osErrorPriority (-128)
-#endif
-
-
-// >>> the following data type definitions may be adapted towards a specific RTOS
-
-/// Thread ID identifies the thread.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef void *osThreadId;
-#else
-#define osThreadId osThreadId_t
-#endif
-
-/// Timer ID identifies the timer.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef void *osTimerId;
-#else
-#define osTimerId osTimerId_t
-#endif
-
-/// Mutex ID identifies the mutex.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef void *osMutexId;
-#else
-#define osMutexId osMutexId_t
-#endif
-
-/// Semaphore ID identifies the semaphore.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef void *osSemaphoreId;
-#else
-#define osSemaphoreId osSemaphoreId_t
-#endif
-
-/// Pool ID identifies the memory pool.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-typedef void *osPoolId;
-
-/// Message ID identifies the message queue.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-typedef void *osMessageQId;
-
-/// Mail ID identifies the mail queue.
-/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
-typedef void *osMailQId;
-
-
-/// Thread Definition structure contains startup information of a thread.
-/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_thread_def {
- os_pthread pthread; ///< start address of thread function
- osPriority tpriority; ///< initial thread priority
- uint32_t instances; ///< maximum number of instances of that thread function
- uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
-} osThreadDef_t;
-#else
-typedef struct os_thread_def {
- os_pthread pthread; ///< start address of thread function
- osThreadAttr_t attr; ///< thread attributes
-} osThreadDef_t;
-#endif
-
-/// Timer Definition structure contains timer parameters.
-/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_timer_def {
- os_ptimer ptimer; ///< start address of a timer function
-} osTimerDef_t;
-#else
-typedef struct os_timer_def {
- os_ptimer ptimer; ///< start address of a timer function
- osTimerAttr_t attr; ///< timer attributes
-} osTimerDef_t;
-#endif
-
-/// Mutex Definition structure contains setup information for a mutex.
-/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_mutex_def {
- uint32_t dummy; ///< dummy value
-} osMutexDef_t;
-#else
-#define osMutexDef_t osMutexAttr_t
-#endif
-
-/// Semaphore Definition structure contains setup information for a semaphore.
-/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_semaphore_def {
- uint32_t dummy; ///< dummy value
-} osSemaphoreDef_t;
-#else
-#define osSemaphoreDef_t osSemaphoreAttr_t
-#endif
-
-/// Definition structure for memory block allocation.
-/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_pool_def {
- uint32_t pool_sz; ///< number of items (elements) in the pool
- uint32_t item_sz; ///< size of an item
- void *pool; ///< pointer to memory for pool
-} osPoolDef_t;
-#else
-typedef struct os_pool_def {
- uint32_t pool_sz; ///< number of items (elements) in the pool
- uint32_t item_sz; ///< size of an item
- osMemoryPoolAttr_t attr; ///< memory pool attributes
-} osPoolDef_t;
-#endif
-
-/// Definition structure for message queue.
-/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_messageQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- void *pool; ///< memory array for messages
-} osMessageQDef_t;
-#else
-typedef struct os_messageQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- osMessageQueueAttr_t attr; ///< message queue attributes
-} osMessageQDef_t;
-#endif
-
-/// Definition structure for mail queue.
-/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
-#if (osCMSIS < 0x20000U)
-typedef struct os_mailQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- uint32_t item_sz; ///< size of an item
- void *pool; ///< memory array for mail
-} osMailQDef_t;
-#else
-typedef struct os_mailQ_def {
- uint32_t queue_sz; ///< number of elements in the queue
- uint32_t item_sz; ///< size of an item
- void *mail; ///< pointer to mail
- osMemoryPoolAttr_t mp_attr; ///< memory pool attributes
- osMessageQueueAttr_t mq_attr; ///< message queue attributes
-} osMailQDef_t;
-#endif
-
-
-/// Event structure contains detailed information about an event.
-typedef struct {
- osStatus status; ///< status code: event or error information
- union {
- uint32_t v; ///< message as 32-bit value
- void *p; ///< message or mail as void pointer
- int32_t signals; ///< signal flags
- } value; ///< event value
- union {
- osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
- osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
- } def; ///< event definition
-} osEvent;
-
-
-// ==== Kernel Management Functions ====
-
-/// Initialize the RTOS Kernel for creating objects.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osKernelInitialize (void);
-#endif
-
-/// Start the RTOS Kernel scheduler.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osKernelStart (void);
-#endif
-
-/// Check if the RTOS kernel is already started.
-/// \return 0 RTOS is not started, 1 RTOS is started.
-#if (osCMSIS < 0x20000U)
-int32_t osKernelRunning(void);
-#endif
-
-#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
-
-/// Get the RTOS kernel system timer counter.
-/// \return RTOS kernel system timer as 32-bit value
-#if (osCMSIS < 0x20000U)
-uint32_t osKernelSysTick (void);
-#else
-#define osKernelSysTick osKernelGetSysTimerCount
-#endif
-
-/// The RTOS kernel system timer frequency in Hz.
-/// \note Reflects the system timer setting and is typically defined in a configuration file.
-#if (osCMSIS < 0x20000U)
-#define osKernelSysTickFrequency 100000000
-#endif
-
-/// Convert a microseconds value to a RTOS kernel system timer value.
-/// \param microsec time value in microseconds.
-/// \return time value normalized to the \ref osKernelSysTickFrequency
-#if (osCMSIS < 0x20000U)
-#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
-#else
-#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
-#endif
-
-#endif // System Timer available
-
-
-// ==== Thread Management Functions ====
-
-/// Create a Thread Definition with function, priority, and stack requirements.
-/// \param name name of the thread function.
-/// \param priority initial priority of the thread function.
-/// \param instances number of possible thread instances.
-/// \param stacksz stack size (in bytes) requirements for the thread function.
-/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osThreadDef(name, priority, instances, stacksz) \
-extern const osThreadDef_t os_thread_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osThreadDef(name, priority, instances, stacksz) \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), (priority), (instances), (stacksz) }
-#else
-#define osThreadDef(name, priority, instances, stacksz) \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), \
- { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } }
-#endif
-#endif
-
-/// Access a Thread definition.
-/// \param name name of the thread definition object.
-/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osThread(name) \
-&os_thread_def_##name
-
-/// Create a thread and add it to Active Threads and set it to state READY.
-/// \param[in] thread_def thread definition referenced with \ref osThread.
-/// \param[in] argument pointer that is passed to the thread function as start argument.
-/// \return thread ID for reference by other functions or NULL in case of error.
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
-
-/// Return the thread ID of the current running thread.
-/// \return thread ID for reference by other functions or NULL in case of error.
-#if (osCMSIS < 0x20000U)
-osThreadId osThreadGetId (void);
-#endif
-
-/// Change priority of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] priority new priority value for the thread function.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
-#endif
-
-/// Get current priority of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return current priority value of the specified thread.
-#if (osCMSIS < 0x20000U)
-osPriority osThreadGetPriority (osThreadId thread_id);
-#endif
-
-/// Pass control to next thread that is in state \b READY.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osThreadYield (void);
-#endif
-
-/// Terminate execution of a thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osThreadTerminate (osThreadId thread_id);
-#endif
-
-
-// ==== Signal Management ====
-
-/// Set the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that should be set.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
-int32_t osSignalSet (osThreadId thread_id, int32_t signals);
-
-/// Clear the specified Signal Flags of an active thread.
-/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
-int32_t osSignalClear (osThreadId thread_id, int32_t signals);
-
-/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
-/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event flag information or error code.
-osEvent osSignalWait (int32_t signals, uint32_t millisec);
-
-
-// ==== Generic Wait Functions ====
-
-/// Wait for Timeout (Time Delay).
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osDelay (uint32_t millisec);
-#endif
-
-#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
-
-/// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return event that contains signal, message, or mail information or error code.
-osEvent osWait (uint32_t millisec);
-
-#endif // Generic Wait available
-
-
-// ==== Timer Management Functions ====
-
-/// Define a Timer object.
-/// \param name name of the timer object.
-/// \param function name of the timer call back function.
-/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osTimerDef(name, function) \
-extern const osTimerDef_t os_timer_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osTimerDef(name, function) \
-const osTimerDef_t os_timer_def_##name = { (function) }
-#else
-#define osTimerDef(name, function) \
-const osTimerDef_t os_timer_def_##name = \
-{ (function), { NULL, 0U, NULL, 0U } }
-#endif
-#endif
-
-/// Access a Timer definition.
-/// \param name name of the timer object.
-/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osTimer(name) \
-&os_timer_def_##name
-
-/// Create and Initialize a timer.
-/// \param[in] timer_def timer object referenced with \ref osTimer.
-/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
-/// \param[in] argument argument to the timer call back function.
-/// \return timer ID for reference by other functions or NULL in case of error.
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
-
-/// Start or restart a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
-#endif
-
-/// Stop a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osTimerStop (osTimerId timer_id);
-#endif
-
-/// Delete a timer.
-/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osTimerDelete (osTimerId timer_id);
-#endif
-
-
-// ==== Mutex Management Functions ====
-
-/// Define a Mutex.
-/// \param name name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMutexDef(name) \
-extern const osMutexDef_t os_mutex_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osMutexDef(name) \
-const osMutexDef_t os_mutex_def_##name = { 0 }
-#else
-#define osMutexDef(name) \
-const osMutexDef_t os_mutex_def_##name = \
-{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U }
-#endif
-#endif
-
-/// Access a Mutex definition.
-/// \param name name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMutex(name) \
-&os_mutex_def_##name
-
-/// Create and Initialize a Mutex object.
-/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
-/// \return mutex ID for reference by other functions or NULL in case of error.
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
-
-/// Wait until a Mutex becomes available.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
-#else
-#define osMutexWait osMutexAcquire
-#endif
-
-/// Release a Mutex that was obtained by \ref osMutexWait.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osMutexRelease (osMutexId mutex_id);
-#endif
-
-/// Delete a Mutex object.
-/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osMutexDelete (osMutexId mutex_id);
-#endif
-
-
-// ==== Semaphore Management Functions ====
-
-#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
-
-/// Define a Semaphore object.
-/// \param name name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osSemaphoreDef(name) \
-extern const osSemaphoreDef_t os_semaphore_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osSemaphoreDef(name) \
-const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
-#else
-#define osSemaphoreDef(name) \
-const osSemaphoreDef_t os_semaphore_def_##name = \
-{ NULL, 0U, NULL, 0U }
-#endif
-#endif
-
-/// Access a Semaphore definition.
-/// \param name name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osSemaphore(name) \
-&os_semaphore_def_##name
-
-/// Create and Initialize a Semaphore object.
-/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
-/// \param[in] count maximum and initial number of available tokens.
-/// \return semaphore ID for reference by other functions or NULL in case of error.
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
-
-/// Wait until a Semaphore token becomes available.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return number of available tokens, or -1 in case of incorrect parameters.
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
-
-/// Release a Semaphore token.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
-#endif
-
-/// Delete a Semaphore object.
-/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-#if (osCMSIS < 0x20000U)
-osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
-#endif
-
-#endif // Semaphore available
-
-
-// ==== Memory Pool Management Functions ====
-
-#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
-
-/// \brief Define a Memory Pool.
-/// \param name name of the memory pool.
-/// \param no maximum number of blocks (objects) in the memory pool.
-/// \param type data type of a single block (object).
-/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osPoolDef(name, no, type) \
-extern const osPoolDef_t os_pool_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osPoolDef(name, no, type) \
-const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), NULL }
-#else
-#define osPoolDef(name, no, type) \
-const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } }
-#endif
-#endif
-
-/// \brief Access a Memory Pool definition.
-/// \param name name of the memory pool
-/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osPool(name) \
-&os_pool_def_##name
-
-/// Create and Initialize a Memory Pool object.
-/// \param[in] pool_def memory pool definition referenced with \ref osPool.
-/// \return memory pool ID for reference by other functions or NULL in case of error.
-osPoolId osPoolCreate (const osPoolDef_t *pool_def);
-
-/// Allocate a memory block from a Memory Pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-void *osPoolAlloc (osPoolId pool_id);
-
-/// Allocate a memory block from a Memory Pool and set memory block to zero.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-void *osPoolCAlloc (osPoolId pool_id);
-
-/// Return an allocated memory block back to a Memory Pool.
-/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
-/// \param[in] block address of the allocated memory block to be returned to the memory pool.
-/// \return status code that indicates the execution status of the function.
-osStatus osPoolFree (osPoolId pool_id, void *block);
-
-#endif // Memory Pool available
-
-
-// ==== Message Queue Management Functions ====
-
-#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
-
-/// \brief Create a Message Queue Definition.
-/// \param name name of the queue.
-/// \param queue_sz maximum number of messages in the queue.
-/// \param type data type of a single message element (for debugger).
-/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMessageQDef(name, queue_sz, type) \
-extern const osMessageQDef_t os_messageQ_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osMessageQDef(name, queue_sz, type) \
-const osMessageQDef_t os_messageQ_def_##name = \
-{ (queue_sz), NULL }
-#else
-#define osMessageQDef(name, queue_sz, type) \
-const osMessageQDef_t os_messageQ_def_##name = \
-{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } }
-#endif
-#endif
-
-/// \brief Access a Message Queue Definition.
-/// \param name name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMessageQ(name) \
-&os_messageQ_def_##name
-
-/// Create and Initialize a Message Queue object.
-/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return message queue ID for reference by other functions or NULL in case of error.
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
-
-/// Put a Message to a Queue.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] info message information.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
-
-/// Get a Message from a Queue or timeout if Queue is empty.
-/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event information that includes status code.
-osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
-
-#endif // Message Queue available
-
-
-// ==== Mail Queue Management Functions ====
-
-#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
-
-/// \brief Create a Mail Queue Definition.
-/// \param name name of the queue.
-/// \param queue_sz maximum number of mails in the queue.
-/// \param type data type of a single mail element.
-/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal) // object is external
-#define osMailQDef(name, queue_sz, type) \
-extern const osMailQDef_t os_mailQ_def_##name
-#else // define the object
-#if (osCMSIS < 0x20000U)
-#define osMailQDef(name, queue_sz, type) \
-const osMailQDef_t os_mailQ_def_##name = \
-{ (queue_sz), sizeof(type), NULL }
-#else
-#define osMailQDef(name, queue_sz, type) \
-static void *os_mail_p_##name[2]; \
-const osMailQDef_t os_mailQ_def_##name = \
-{ (queue_sz), sizeof(type), (&os_mail_p_##name), \
- { NULL, 0U, NULL, 0U, NULL, 0U }, \
- { NULL, 0U, NULL, 0U, NULL, 0U } }
-#endif
-#endif
-
-/// \brief Access a Mail Queue Definition.
-/// \param name name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
-/// macro body is implementation specific in every CMSIS-RTOS.
-#define osMailQ(name) \
-&os_mailQ_def_##name
-
-/// Create and Initialize a Mail Queue object.
-/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
-/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return mail queue ID for reference by other functions or NULL in case of error.
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
-
-/// Allocate a memory block for mail from a mail memory pool.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
-
-/// Put a Mail into a Queue.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail pointer to memory with mail to put into a queue.
-/// \return status code that indicates the execution status of the function.
-osStatus osMailPut (osMailQId queue_id, const void *mail);
-
-/// Get a Mail from a Queue or timeout if Queue is empty.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
-/// \return event information that includes status code.
-osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
-
-/// Free a memory block by returning it to a mail memory pool.
-/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
-/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
-/// \return status code that indicates the execution status of the function.
-osStatus osMailFree (osMailQId queue_id, void *mail);
-
-#endif // Mail Queue available
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // CMSIS_OS_H_
diff --git a/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c
deleted file mode 100644
index de1650c..0000000
--- a/KugleFirmware/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date: 10. January 2017
- * $Revision: V1.2
- *
- * Project: CMSIS-RTOS API V1
- * Title: cmsis_os_v1.c V1 module file
- *---------------------------------------------------------------------------*/
-
-#include
-#include "cmsis_os.h"
-
-#if (osCMSIS >= 0x20000U)
-
-
-// Thread
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
-
- if (thread_def == NULL) {
- return (osThreadId)NULL;
- }
- return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
-}
-
-
-// Signals
-
-#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) {
- event.status = osEventSignal;
- event.value.signals = (int32_t)flags;
- } else {
- switch ((int32_t)flags) {
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- case osErrorParameter:
- event.status = osErrorValue;
- break;
- default:
- event.status = (osStatus)flags;
- break;
- }
- }
- return event;
-}
-
-
-// Timer
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
-
- if (timer_def == NULL) {
- return (osTimerId)NULL;
- }
- return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
-}
-
-
-// Mutex
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
-
- if (mutex_def == NULL) {
- return (osMutexId)NULL;
- }
- return osMutexNew(mutex_def);
-}
-
-
-// Semaphore
-
-#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))
-
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
-
- if (semaphore_def == NULL) {
- return (osSemaphoreId)NULL;
- }
- return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
-}
-
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
- osStatus_t status;
- uint32_t count;
-
- status = osSemaphoreAcquire(semaphore_id, millisec);
- switch (status) {
- case osOK:
- count = osSemaphoreGetCount(semaphore_id);
- return ((int32_t)count + 1);
- case osErrorResource:
- case osErrorTimeout:
- return 0;
- default:
- break;
- }
- return -1;
-}
-
-#endif // Semaphore
-
-
-// Memory Pool
-
-#if (defined(osFeature_Pool) && (osFeature_Pool != 0))
-
-osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
-
- if (pool_def == NULL) {
- return (osPoolId)NULL;
- }
- return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr)));
-}
-
-void *osPoolAlloc (osPoolId pool_id) {
- return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
-}
-
-void *osPoolCAlloc (osPoolId pool_id) {
- void *block;
- uint32_t block_size;
-
- block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
- if (block_size == 0U) {
- return NULL;
- }
- block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
- if (block != NULL) {
- memset(block, 0, block_size);
- }
- return block;
-}
-
-osStatus osPoolFree (osPoolId pool_id, void *block) {
- return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block);
-}
-
-#endif // Memory Pool
-
-
-// Message Queue
-
-#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))
-
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
- (void)thread_id;
-
- if (queue_def == NULL) {
- return (osMessageQId)NULL;
- }
- return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr)));
-}
-
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
- return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec);
-}
-
-osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
- osStatus_t status;
- osEvent event;
- uint32_t message;
-
- status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec);
- switch (status) {
- case osOK:
- event.status = osEventMessage;
- event.value.v = message;
- break;
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- default:
- event.status = status;
- break;
- }
- return event;
-}
-
-#endif // Message Queue
-
-
-// Mail Queue
-
-#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))
-
-typedef struct os_mail_queue_s {
- osMemoryPoolId_t mp_id;
- osMessageQueueId_t mq_id;
-} os_mail_queue_t;
-
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
- os_mail_queue_t *ptr;
- (void)thread_id;
-
- if (queue_def == NULL) {
- return (osMailQId)NULL;
- }
-
- ptr = queue_def->mail;
- if (ptr == NULL) {
- return (osMailQId)NULL;
- }
-
- ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
- ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
- if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) {
- if (ptr->mp_id != (osMemoryPoolId_t)NULL) {
- osMemoryPoolDelete(ptr->mp_id);
- }
- if (ptr->mq_id != (osMessageQueueId_t)NULL) {
- osMessageQueueDelete(ptr->mq_id);
- }
- return (osMailQId)NULL;
- }
-
- return (osMailQId)ptr;
-}
-
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return NULL;
- }
- return osMemoryPoolAlloc(ptr->mp_id, millisec);
-}
-
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
- void *block;
- uint32_t block_size;
-
- if (ptr == NULL) {
- return NULL;
- }
- block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
- if (block_size == 0U) {
- return NULL;
- }
- block = osMemoryPoolAlloc(ptr->mp_id, millisec);
- if (block != NULL) {
- memset(block, 0, block_size);
- }
-
- return block;
-
-}
-
-osStatus osMailPut (osMailQId queue_id, const void *mail) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return osErrorParameter;
- }
- if (mail == NULL) {
- return osErrorValue;
- }
- return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
-}
-
-osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
- osStatus_t status;
- osEvent event;
- void *mail;
-
- if (ptr == NULL) {
- event.status = osErrorParameter;
- return event;
- }
-
- status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
- switch (status) {
- case osOK:
- event.status = osEventMail;
- event.value.p = mail;
- break;
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- default:
- event.status = status;
- break;
- }
- return event;
-}
-
-osStatus osMailFree (osMailQId queue_id, void *mail) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return osErrorParameter;
- }
- if (mail == NULL) {
- return osErrorValue;
- }
- return osMemoryPoolFree(ptr->mp_id, mail);
-}
-
-#endif // Mail Queue
-
-
-#endif // osCMSIS
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index 37bd999..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3292 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @version V1.1.0
- * @date 31-August-2017
- * @brief This file contains aliases definition for the STM32Cube HAL constants
- * macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-/**
- * @}
- */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
-#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
- #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
- #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
- #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
- #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
- #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
- #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-
- #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
- #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
- #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
- #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
- #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
- #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
- #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
- #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
- #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#endif /* STM32H7 */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
- /**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
- /**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4) || defined(STM32F2)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
deleted file mode 100644
index 430830d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
+++ /dev/null
@@ -1,595 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_H
-#define __STM32H7xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_conf.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HAL_TICK_FREQ Tick Frequency
- * @{
- */
-typedef enum
-{
- HAL_TICK_FREQ_10HZ = 100U,
- HAL_TICK_FREQ_100HZ = 10U,
- HAL_TICK_FREQ_1KHZ = 1U,
- HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
- * @{
- */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
-
-
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
-
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
- * @{
- */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
-
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
- ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
-
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Ethernet_Config Ethernet Config
- * @{
- */
-#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */
-#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */
-
-#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \
- ((CONFIG) == SYSCFG_ETH_RMII))
-
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config
- * @{
- */
-#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */
-#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */
-#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */
-#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */
-
-
-#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
- (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
- (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
- (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
-
-
-#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */
-#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
-#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */
-#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
-#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */
-#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */
-#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */
-#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */
-
-#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
- (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
- (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
- (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \
- (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \
- (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \
- (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \
- (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Boot_Config Boot Config
- * @{
- */
-#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */
-#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */
-
-#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
- ((REGISTER) == SYSCFG_BOOT_ADDR1))
-
-#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
-
-/**
- * @}
- */
-
-
-/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config
- * @{
- */
-#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
-#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */
-
-#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
- ((SELECT) == SYSCFG_REGISTER_CODE))
-
-#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
-
-/**
- * @}
- */
-
-
-
-
-/** @defgroup EXTI_Event_Input_Config Event Input Config
- * @{
- */
-
-#define EXTI_MODE_IT ((uint32_t)0x00010000)
-#define EXTI_MODE_EVT ((uint32_t)0x00020000)
-#define EXTI_RISING_EDGE ((uint32_t)0x00100000)
-#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)
-
-#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
-#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
-
-#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */
-#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */
-#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */
-#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */
-#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */
-#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */
-#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */
-#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */
-#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */
-#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */
-#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */
-#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */
-#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */
-#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */
-#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */
-#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */
-#define EXTI_LINE16 ((uint32_t)0x10)
-#define EXTI_LINE17 ((uint32_t)0x11)
-#define EXTI_LINE18 ((uint32_t)0x12)
-#define EXTI_LINE19 ((uint32_t)0x13)
-#define EXTI_LINE20 ((uint32_t)0x14)
-#define EXTI_LINE21 ((uint32_t)0x15)
-#define EXTI_LINE22 ((uint32_t)0x16)
-#define EXTI_LINE23 ((uint32_t)0x17)
-#define EXTI_LINE24 ((uint32_t)0x18)
-#define EXTI_LINE25 ((uint32_t)0x19)
-#define EXTI_LINE26 ((uint32_t)0x1A)
-#define EXTI_LINE27 ((uint32_t)0x1B)
-#define EXTI_LINE28 ((uint32_t)0x1C)
-#define EXTI_LINE29 ((uint32_t)0x1D)
-#define EXTI_LINE30 ((uint32_t)0x1E)
-#define EXTI_LINE31 ((uint32_t)0x1F)
-#define EXTI_LINE32 ((uint32_t)0x20)
-#define EXTI_LINE33 ((uint32_t)0x21)
-#define EXTI_LINE34 ((uint32_t)0x22)
-#define EXTI_LINE35 ((uint32_t)0x23)
-#define EXTI_LINE36 ((uint32_t)0x24)
-#define EXTI_LINE37 ((uint32_t)0x25)
-#define EXTI_LINE38 ((uint32_t)0x26)
-#define EXTI_LINE39 ((uint32_t)0x27)
-
-#define EXTI_LINE40 ((uint32_t)0x28)
-#define EXTI_LINE41 ((uint32_t)0x29)
-#define EXTI_LINE42 ((uint32_t)0x2A)
-#define EXTI_LINE43 ((uint32_t)0x2B)
-#define EXTI_LINE44 ((uint32_t)0x2C)
-/* EXTI_LINE45 Reserved */
-/* EXTI_LINE46 Reserved */
-#define EXTI_LINE47 ((uint32_t)0x2F)
-#define EXTI_LINE48 ((uint32_t)0x30)
-#define EXTI_LINE49 ((uint32_t)0x31)
-
-#define EXTI_LINE50 ((uint32_t)0x32)
-#define EXTI_LINE51 ((uint32_t)0x33)
-#define EXTI_LINE52 ((uint32_t)0x34)
-#define EXTI_LINE53 ((uint32_t)0x35)
-#define EXTI_LINE54 ((uint32_t)0x36)
-#define EXTI_LINE55 ((uint32_t)0x37)
-#define EXTI_LINE56 ((uint32_t)0x38)
-#define EXTI_LINE57 ((uint32_t)0x39)
-#define EXTI_LINE58 ((uint32_t)0x3A)
-#define EXTI_LINE59 ((uint32_t)0x3B)
-
-#define EXTI_LINE60 ((uint32_t)0x3C)
-#define EXTI_LINE61 ((uint32_t)0x3D)
-#define EXTI_LINE62 ((uint32_t)0x3E)
-#define EXTI_LINE63 ((uint32_t)0x3F)
-#define EXTI_LINE64 ((uint32_t)0x40)
-#define EXTI_LINE65 ((uint32_t)0x41)
-#define EXTI_LINE66 ((uint32_t)0x42)
-#define EXTI_LINE67 ((uint32_t)0x43)
-#define EXTI_LINE68 ((uint32_t)0x44)
-#define EXTI_LINE69 ((uint32_t)0x45)
-
-#define EXTI_LINE70 ((uint32_t)0x46)
-#define EXTI_LINE71 ((uint32_t)0x47)
-#define EXTI_LINE72 ((uint32_t)0x48)
-#define EXTI_LINE73 ((uint32_t)0x49)
-#define EXTI_LINE74 ((uint32_t)0x4A)
-#define EXTI_LINE75 ((uint32_t)0x4B)
-#define EXTI_LINE76 ((uint32_t)0x4C)
-
-/* EXTI_LINE77 Reserved */
-/* EXTI_LINE78 Reserved */
-/* EXTI_LINE79 Reserved */
-/* EXTI_LINE80 Reserved */
-/* EXTI_LINE81 Reserved */
-/* EXTI_LINE82 Reserved */
-/* EXTI_LINE83 Reserved */
-/* EXTI_LINE84 Reserved */
-
-#define EXTI_LINE85 ((uint32_t)0x55)
-#define EXTI_LINE86 ((uint32_t)0x56)
-#define EXTI_LINE87 ((uint32_t)0x57)
-
-/* EXTI_LINE88 Reserved */
-
-
-#define IS_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
- ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
- ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
- ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
- ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
- ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
- ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
- ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
- ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
- ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
- ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
- ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
- ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
-
-#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
- ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
- ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
- ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
- ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
- ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
- ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
- ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
- ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
- ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
- ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
- ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
- ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
- ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
- ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
- ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
- ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
- ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
- ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
- ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
- ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
- ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
- ((LINE) == EXTI_LINE44) || \
- ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
- ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
- ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
- ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
- ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
- ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
- ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
- ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
- ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
- ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
- ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
- ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
- ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
- ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
- ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
- ((LINE) == EXTI_LINE85) || \
- ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
-
-#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
- ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
- ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
- ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
- ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
- ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
- ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
- ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
- ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
- ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
- ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
- ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
- ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
- ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
- ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
- ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
- ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
- ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
- ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
- ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
- ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
- ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
- ((LINE) == EXTI_LINE44) || \
- ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
- ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
- ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
- ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
- ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
- ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
- ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
- ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
- ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
- ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
- ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
- ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
- ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
- ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
- ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
- ((LINE) == EXTI_LINE85) || \
- ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
-
-
-#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
- ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
- ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
- ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
- ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
- ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
- ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
- ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
- ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
- ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
- ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
- ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
- ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
- ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
- ((LINE) == EXTI_LINE53))
-
-
-#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
-#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/
-#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/
-#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/
-
-#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
- ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config
- * @{
- */
-#define FMC_SWAPBMAP_DISABLE (0x00000000U)
-#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
-#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
-
-#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \
- ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
- ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Freeze/Unfreeze Peripherals in Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
-
-#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
-#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
-#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
-#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
-#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
-#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
-#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
-#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
-#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
-#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
-#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
-#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
-#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
-#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
-
-
-#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
-#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
-#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
-#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
-#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
-#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
-
-#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
-#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
-#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
-#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
-#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
-#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
-#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
-
-
-#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
-
-#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
-#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
-#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
-#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
-#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
-#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
-#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
-#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
-#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
-#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
-#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
-#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
-#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
-#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
-
-
-#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
-#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
-#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
-#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
-#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
-#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
-
-#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
-#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
-#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
-#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
-#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
-#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
-#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
-
-
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
- ((FREQ) == HAL_TICK_FREQ_100HZ) || \
- ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
-void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
-void HAL_SYSCFG_EnableBOOST(void);
-void HAL_SYSCFG_DisableBOOST(void);
-void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
-void HAL_EnableCompensationCell(void);
-void HAL_DisableCompensationCell(void);
-void HAL_SYSCFG_EnableIOSpeedOptimize(void);
-void HAL_SYSCFG_DisableIOSpeedOptimize(void);
-void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
-void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
-void HAL_EnableDomain3DBGStopMode(void);
-void HAL_DisableDomain3DBGStopMode(void);
-void HAL_EnableDomain3DBGStandbyMode(void);
-void HAL_DisableDomain3DBGStandbyMode(void);
-void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
-void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
-void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
-void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
-void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
-uint32_t HAL_GetFMCMemorySwappingConfig(void);
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
-void HAL_SYSCFG_DisableVREFBUF(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h
deleted file mode 100644
index e6b7cbd..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_ADC_H
-#define __STM32H7xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
- * @{
- */
-
-/**
- * @brief ADC Regular Conversion Oversampling structure definition
- */
-typedef struct
-{
- uint32_t Ratio; /*!< Configures the oversampling ratio. */
-
-
- uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
- This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
-
- uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
- This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
-
- uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
- The oversampling is either temporary stopped or reset upon an injected
- sequence interruption.
- If oversampling is enabled on both regular and injected groups, this parameter
- is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
- (the oversampling buffer is zeroed during injection sequence).
- This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */
-}ADC_OversamplingTypeDef;
-
-/**
- * @brief Structure definition of ADC instance and ADC group regular.
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
- * ScanConvMode, EOCSelection, LowPowerAutoWait.
- * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
- * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
- * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled
- * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
- * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
- * (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLL2/PLL3 clocks) and clock prescaler.
-
- This parameter can be a value of @ref ADC_ClockPrescaler.
- Note: The clock is common for all the ADCs.
- Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 16, 14, 12 or 10 bits,
- AHB clock frequency /3 for resolution 8 bits.
- Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
- if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
- must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
- Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level.
- Note: This parameter can be modified only if all ADCs are disabled. */
-
- uint32_t Resolution; /*!< Configure the ADC resolution.
- This parameter can be a value of @ref ADC_Resolution */
-
- uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
- Scan direction is upward: from rank 1 to rank 'n'.
- This parameter can be a value of @ref ADC_Scan_mode */
-
- uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
- This parameter can be a value of @ref ADC_EOCSelection. */
-
- FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
- conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
- using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
- This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
- for low frequency applications.
- This parameter can be set to ENABLE or DISABLE.
- Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
- to free the IRQ vector sequencer.
- Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
- use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
- (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
-
- FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
- after the first ADC conversion start trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
- To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
- continuous mode or external trigger that could launch a conversion). */
-
- FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
- (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-
- uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
- If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
- This parameter can be a value of @ref ADC_regular_external_trigger_source.
- Caution: external trigger source is common to all ADC instances. */
-
- uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
- If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
- This parameter can be a value of @ref ADC_regular_external_trigger_edge */
-
- uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
- This parameter can be a value of @ref ADC_ConversionDataManagement.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups
- (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
-
- uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
- This parameter applies to ADC group regular only.
- This parameter can be a value of @ref ADC_Overrun.
- Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
- end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
- HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
- Note: Error reporting with respect to the conversion mode:
- - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
- overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
-
- uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
- This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
-
- FunctionalState BoostMode; /*!< Configures the Boost mode control.
- When selecting an analog ADC clock frequency bigger than 20MHz,
- it is mandatory to first enable the BOOST Mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
- This parameter can be set to ENABLE or DISABLE.
- Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
-
- ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
- Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
-}ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of ADC analog watchdog
- * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
- * ADC state can be either:
- * ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
- */
-typedef struct
-{
- uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
- For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
- For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
- This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
-
- uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
- For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected.
- For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
- channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
- This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
-
- uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
- For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
- For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
- This parameter can be a value of @ref ADC_channels. */
-
- FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number
- between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
-
- uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
- Depending of ADC resolution selected (16, 14, 12, or 8 bits), this parameter must be a number
- between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
-
-}ADC_AnalogWDGConfTypeDef;
-
-/** @defgroup ADC_States ADC States
- * @{
- */
-/**
- * @brief HAL ADC state machine: ADC states definition (bitfields)
- * @note ADC state machine is managed by bitfields, state must be compared
- * with bit by bit.
- * For example:
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
- */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_Error_Code ADC Error Code
- * @{
- */
-#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error (problem of clocking,
- enable/disable, erroneous state, ...) */
-#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
-#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
-/**
- * @}
- */
-
-/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
- * @{
- */
-#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
-
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */
-
-#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */
-#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */
-#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */
-#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */
-#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */
-#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */
-#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */
-#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */
-#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */
-#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */
-#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */
-#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
-/**
- * @}
- */
-
-/** @defgroup ADC_Resolution ADC Resolution
- * @{
- */
-#define ADC_RESOLUTION_16B ((uint32_t)0x00000000) /*!< ADC 16-bit resolution */
-#define ADC_RESOLUTION_14B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 14-bit resolution */
-#define ADC_RESOLUTION_12B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 12-bit resolution */
-#define ADC_RESOLUTION_10B ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) /*!< ADC 10-bit resolution */
-#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_2) /*!< ADC 8-bit resolution */
-/**
- * @}
- */
-
-/** @defgroup ADC_Scan_mode ADC sequencer scan mode
- * @{
- */
-#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
-#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
- * @{
- */
-/* External triggers of regular group for ADC1, ADC2, ADC3 */
-#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
-#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
-#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_HR1_ADCTRG1 ((uint32_t) ADC_CFGR_EXTSEL_4)
-#define ADC_EXTERNALTRIG_HR1_ADCTRG3 ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_LPTIM1_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))
-#define ADC_EXTERNALTRIG_LPTIM2_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))
-#define ADC_EXTERNALTRIG_LPTIM3_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))
-
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
- * @{
- */
-#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */
-#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */
-/**
- * @}
- */
-
-/** @defgroup ADC_Overrun ADC overrun
- * @{
- */
-#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */
-#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_rank ADC group regular sequencer rank
- * @{
- */
-#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
-#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
-#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
-#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
-#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
-#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
-#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
-#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
-#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
-#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
-#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
-#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
-#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
-#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
-#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
-#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_channels ADC Channels
- * @{
- */
-#define ADC_CHANNEL_0 ((uint32_t)(0x00000000))
-#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
-#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
-#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
-#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
-#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))
-
-/* Note: Vbat/4, TempSensor and VREFINT internal channels are available on ADC3 only */
-#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_17
-#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
-#define ADC_CHANNEL_VREFINT ADC_CHANNEL_19
-
-/* Note: DAC1CH1 and DAC1CH2 internal channels is available on ADC2 only */
-#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
-#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
-/**
- * @}
- */
-
-
-/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
- * @{
- */
-#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
-#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
-#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
-#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macro ADC Private Macros
- * @{
- */
-
-/**
- * @brief Verify the ADC data conversion setting.
- * @param DATA : programmed DATA conversion mode.
- * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
- */
-#define IS_ADC_CONVERSIONDATAMGT(DATA) \
- ((((DATA) == ADC_CONVERSIONDATA_DR)) || \
- (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
- (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
- (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
-
-/**
- * @brief Test if conversion trigger of regular group is software start
- * or external trigger.
- * @param __HANDLE__: ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
-
-/**
- * @brief Returns resolution bits in CFGR register: RES[1:0].
- * Returned value is among parameters in @ref ADC_Resolution.
- * @param __HANDLE__: ADC handle
- * @retval Parameter of @ref ADC_Resolution set.
- */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
-
-/**
- * @brief Clear ADC error code (set it to error code: "no error")
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
- * @brief Verification of ADC state: enabled or disabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_IS_ENABLE(__HANDLE__) \
- (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
- ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
- ) ? SET : RESET)
-
-/**
- * @brief Check if no conversion on going on regular group
- * @param __HANDLE__: ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Simultaneously clears and sets specific bits of the handle State
- * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
- * the first parameter is the ADC handle State, the second parameter is the
- * bit field to clear, the third and last parameter is the bit field to set
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Verify that a given value is aligned with the ADC resolution range.
- * @param RESOLUTION: ADC resolution (16, 14, 12, 10 or 8 bits).
- * @param ADC_VALUE: value checked against the resolution.
- * @retval SET (ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_16B) && ((ADC_VALUE) <= ((uint32_t)0xFFFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_14B) && ((ADC_VALUE) <= ((uint32_t)0x3FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))))
-
-/**
- * @brief Verify the length of the scheduled regular conversions group.
- * @param LENGTH: number of programmed conversions.
- * @retval SET (LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
-
-/**
- * @brief Verify the number of scheduled regular conversions in discontinuous mode.
- * @param NUMBER: number of scheduled regular conversions in discontinuous mode.
- * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
- */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
-
-/**
- * @brief Verify the ADC clock setting.
- * @param ADC_CLOCK : programmed ADC clock.
- * @retval SET (ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)
- */
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128) || \
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256) )
-
-/**
- * @brief Verify the ADC resolution setting.
- * @param RESOLUTION: programmed ADC resolution.
- * @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
- */
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_16B) || \
- ((RESOLUTION) == ADC_RESOLUTION_14B) || \
- ((RESOLUTION) == ADC_RESOLUTION_12B) || \
- ((RESOLUTION) == ADC_RESOLUTION_10B) || \
- ((RESOLUTION) == ADC_RESOLUTION_8B) )
-
-/**
- * @brief Verify the ADC resolution setting when limited to 8 bits.
- * @param RESOLUTION: programmed ADC resolution when limited to 8 bits.
- * @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
- */
-#define IS_ADC_RESOLUTION_8_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B))
-
-/**
- * @brief Verify the ADC scan mode.
- * @param SCAN_MODE: programmed ADC scan mode.
- * @retval SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)
- */
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
- ((SCAN_MODE) == ADC_SCAN_ENABLE) )
-
-/**
- * @brief Verify the ADC edge trigger setting for regular group.
- * @param EDGE: programmed ADC edge trigger setting.
- * @retval SET (EDGE is a valid value) or RESET (EDGE is invalid)
- */
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
-
-/**
- * @brief Verify the ADC regular conversions external trigger.
- * @param REGTRIG: programmed ADC regular conversions external trigger.
- * @retval SET (REGTRIG is a valid value) or RESET (REGTRIG is invalid)
- */
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
- ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-
-/**
- * @brief Verify the ADC regular conversions check for converted data availability.
- * @param EOC_SELECTION: converted data availability check.
- * @retval SET (EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)
- */
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
-
-/**
- * @brief Verify the ADC regular conversions overrun handling.
- * @param OVR: ADC regular conversions overrun handling.
- * @retval SET (OVR is a valid value) or RESET (OVR is invalid)
- */
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
- ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
-
-/**
- * @brief Verify the ADC conversions sampling time.
- * @param TIME: ADC conversions sampling time.
- * @retval SET (TIME is a valid value) or RESET (TIME is invalid)
- */
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
- ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_8CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_16CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_32CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_64CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_387CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_810CYCLES_5) )
-
-/**
- * @brief Verify the ADC regular channel setting.
- * @param __CHANNEL__: programmed ADC regular channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
- ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Fixed timeout values for ADC conversion (including sampling time) */
-/* Maximum sampling time is 810.5 ADC clock cycle */
-/* Maximum conversion time is 16.5 + Maximum sampling time */
-/* or 16.5 + 810.5 = 827 ADC clock cycles */
-/* Minimum ADC Clock frequency is 0.35 MHz */
-/* Maximum conversion time is */
-/* 827 / 0.35 MHz = 2.36 ms */
-#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
-
-
-
-/* Delay for temperature sensor stabilization time. */
-/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
-/* Unit: us */
-#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
-
-
-/* Delay for ADC voltage regulator startup time */
-/* Maximum delay is 10 microseconds */
-/* (refer device RM, parameter Tadcvreg_stup). */
-#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macro ADC Exported Macros
- * @{
- */
-
-/**
- * @brief Reset ADC handle state
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
- * @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC interrupt source to check
- * This parameter can be one of the following values:
- * @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR ADC overrun interrupt source
- * @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
- * @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
- * @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \
- )? SET : RESET \
- )
-
-/**
- * @brief Enable an ADC interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt to enable
- * This parameter can be one of the following values:
- * @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR ADC overrun interrupt source
- * @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
- * @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
- * @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable an ADC interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt to disable
- * @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR ADC overrun interrupt source
- * @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
- * @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
- * @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
- * @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag to check
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_RDY ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP ADC End of Sampling flag
- * @arg ADC_FLAG_EOC ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR ADC overrun flag
- * @arg ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
- * @arg ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
- * @arg ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
- * @arg ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear a specified ADC flag
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag to clear
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_RDY ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP ADC End of Sampling flag
- * @arg ADC_FLAG_EOC ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR ADC overrun flag
- * @arg ADC_FLAG_JEOC ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
- * @arg ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
- * @arg ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
- * @arg ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
- * @note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR)
- * @retval None
- */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/* Include ADC HAL Extended module */
-#include "stm32h7xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @addtogroup ADC_Exported_Functions_Group1 Initialization and deinitialization functions
- * @brief ADC Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
- * @brief ADC IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-
-/**
- * @}
- */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
- * @{
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-
-/**
- * @}
- */
-
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAError(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*__STM32H7xx_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h
deleted file mode 100644
index 4197a51..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h
+++ /dev/null
@@ -1,1457 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_adc_ex.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_ADC_EX_H
-#define __STM32H7xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
- * @{
- */
-
-/**
- * @brief ADC group injected contexts queue configuration
- */
-typedef struct
-{
- uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
- HAL_ADCEx_InjectedConfigChannel() call to finally initialize
- JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
-
- uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
-}ADC_InjectionConfigTypeDef;
-
-/**
- * @brief ADC handle Structure definition
- */
-typedef struct
-{
- ADC_TypeDef *Instance; /*!< Register base address */
-
- ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
-
- HAL_LockTypeDef Lock; /*!< ADC locking object */
-
- __IO uint32_t State; /*!< ADC communication state (bit-map of ADC states) */
-
- __IO uint32_t ErrorCode; /*!< ADC Error code */
-
- ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
-}ADC_HandleTypeDef;
-
-/**
- * @brief ADC Injected Conversion Oversampling structure definition
- */
-typedef struct
-{
- uint32_t Ratio; /*!< Configures the oversampling ratio.
- This parameter can be a value between 0 to 1023 */
-
- uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
- This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
-}ADC_InjOversamplingTypeDef;
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
- * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
- * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
- * (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device DataSheet for channels availability. */
-
- uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
- This parameter can be a value of @ref ADC_regular_rank
- Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
- the new channel setting (or parameter number of conversions adjusted) */
-
- uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter applies to a channel that can be used into regular and/or injected group.
- It overwrites the last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device DataSheet for timings values. */
-
- uint32_t SingleDiff; /*!< Select single-ended or differential input.
- In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
- Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
- This parameter must be a value of @ref ADCEx_SingleDifferential
- Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
- It overwrites the last setting.
- Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
- Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
- of another parameter update on the fly) */
-
- uint32_t OffsetNumber; /*!< Select the offset number
- This parameter can be a value of @ref ADCEx_OffsetNumber
- Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
-
- uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
- Offset value must be a positive number.
- Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
- 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
- without continuous mode or external trigger that could launch a conversion). */
-
- FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
- This parameter is applied only for 16-bit or 8-bit resolution.
- This parameter can be set to ENABLE or DISABLE.*/
-
- FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
- This parameter is applied only for 16-bit or 8-bit resolution.
- This parameter can be set to ENABLE or DISABLE. */
-}ADC_ChannelConfTypeDef;
-
-/**
- * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
- * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
- * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
- * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
- * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
- * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
- * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
- * on ADC groups regular and injected.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
-
- uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
- This parameter must be a value of @ref ADCEx_injected_rank.
- Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
- the new channel setting (or parameter number of conversions adjusted) */
-
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles.
- Conversion time is the addition of sampling time and processing time
- This parameter can be a value of @ref ADC_sampling_times.
- Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
- It overwrites the last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values. */
-
- uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
- In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
- Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
- This parameter must be a value of @ref ADCEx_SingleDifferential.
- Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
- It overwrites the last setting.
- Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
- Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
- of another parameter update on the fly) */
-
- uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
- This parameter can be a value of @ref ADCEx_OffsetNumber.
- Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
-
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
- Offset value must be a positive number.
- Depending of ADC resolution selected (16, 14, 12, 10 or 8bits), this parameter must be a number
- between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
- without continuous mode or external trigger that could launch a conversion). */
- uint32_t InjectedOffsetRightShift; /*!< Defines the Right-shift data after Offset correction.
- This parameter is applied only for 16-bit or 8-bit resolution.
- This parameter must be a value of @ref ADCEx_Right_Bit_Shift.*/
- FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
- This parameter is applied only for 16-bit or 8-bit resolution.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
- This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-
- FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
- (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled.
- This parameter can be set to ENABLE or DISABLE.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-
- FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-
- FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
- This parameter can be set to ENABLE or DISABLE.
- If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
- new injected context is set when queue is full, error is triggered by interruption and through function
- 'HAL_ADCEx_InjectedQueueOverflowCallback'.
- Caution: This feature request that the sequence is fully configured before injected conversion start.
- Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
-
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
- This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-
- uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
- This parameter can be a value of @ref ADC_injected_external_trigger_edge.
- If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-
- FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
- This parameter can be set to ENABLE or DISABLE.
- Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared) */
-
- ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
- Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
- Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
-}ADC_InjectionConfTypeDef;
-
-
-
-/**
- * @brief Structure definition of ADC MultiMode
- * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
- * Both Master and Slave ADCs must be disabled.
- */
-typedef struct
-{
- uint32_t Mode; /*!< Configures the ADC to operate in independent or MultiMode.
- This parameter can be a value of @ref ADCEx_Common_mode */
- uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:
- This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
- uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
- Delay range depends on selected resolution:
- from 1 to 9 clock cycles for 16 bits,
- from 1 to 9 clock cycles for 14 bits
- from 1 to 8 clock cycles for 12 bits
- from 1 to 6 clock cycles for 10 bits
- from 1 to 6 clock cycles for 8 bits */
-}ADC_MultiModeTypeDef;
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
- * @{
- */
-
-/** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
- * @{
- */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 15 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 ((uint32_t)ADC_JSQR_JEXTSEL_4) /*!< Event 16 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0)) /*!< Event 17 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1)) /*!< Event 18 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 19 triggers injected group conversion start */
-#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2)) /*!< Event 20 triggers injected group conversion start */
-
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
- * @{
- */
-#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */
-#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
- * @{
- */
-#define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */
-#define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */
-#define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */
-#define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */
-#define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
- * @{
- */
-#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */
-#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */
-#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */
-#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */
-#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */
-#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */
-#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */
-#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */
-#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
- * @{
- */
-#define ADC_DUALMODEDATAFORMAT_DISABLED ((uint32_t)0x00000000) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
-#define ADC_DUALMODEDATAFORMAT_32_10_BITS ((uint32_t)ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */
-#define ADC_DUALMODEDATAFORMAT_8_BITS ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases
- * @{
- */
-#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */
-#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */
-#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */
-#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay (lower for less then 10-bit resolution) */
-#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay (lower for less then 12-bit resolution) */
-#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay (lower for less then 14-bit resolution) */
-#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for less then 16-bit resolution) */
-#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for less then 16-bit resolution) */
-#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for less then 16-bit resolution) */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
- * @{
- */
-#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */
-#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */
-#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
- * @{
- */
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
- * @{
- */
-#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */
-#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */
-#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Event_type ADC Extended Event Type
- * @{
- */
-#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
-#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
-#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
-#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
-/**
- * @}
- */
-#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
-
-/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
- * @{
- */
-#define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */
-#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
-#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
-#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
-#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
-#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
-
-#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: Naming for compatibility with other STM32 devices having only one analog watchdog */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
- * @{
- */
-#define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */
-#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
-#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
-#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
-#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
-#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
-#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
-
-#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
-
-#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
- ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
- ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
- ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
- ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift
- * @{
- */
-#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
-#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */
-#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0)) /*!< ADC 9 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1)) /*!< ADC 10 bits shift for oversampling */
-#define ADC_RIGHTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 11 bits shift for oversampling */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
- * @{
- */
-#define ADC_LEFTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift */
-#define ADC_LEFTBITSHIFT_1 ((uint32_t)ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift */
-#define ADC_LEFTBITSHIFT_2 ((uint32_t)ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift */
-#define ADC_LEFTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 3 bits shift */
-#define ADC_LEFTBITSHIFT_4 ((uint32_t)ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift */
-#define ADC_LEFTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 5 bits shift */
-#define ADC_LEFTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)) /*!< ADC 6 bits shift */
-#define ADC_LEFTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 7 bits shift */
-#define ADC_LEFTBITSHIFT_8 ((uint32_t)ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift */
-#define ADC_LEFTBITSHIFT_9 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 9 bits shift */
-#define ADC_LEFTBITSHIFT_10 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)) /*!< ADC 10 bits shift */
-#define ADC_LEFTBITSHIFT_11 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 11 bits shift */
-#define ADC_LEFTBITSHIFT_12 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)) /*!< ADC 12 bits shift */
-#define ADC_LEFTBITSHIFT_13 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 13 bits shift */
-#define ADC_LEFTBITSHIFT_14 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)) /*!< ADC 14 bits shift */
-#define ADC_LEFTBITSHIFT_15 ((uint32_t)(ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)) /*!< ADC 15 bits shift */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling
- * @{
- */
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode
- * @{
- */
-#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */
-#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times ADC Sampling Times
- * @{
- */
-#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
-#define ADC_SAMPLETIME_8CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 8.5 ADC clock cycles */
-#define ADC_SAMPLETIME_16CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 16.5 ADC clock cycles */
-#define ADC_SAMPLETIME_32CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 32.5 ADC clock cycles */
-#define ADC_SAMPLETIME_64CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 64.5 ADC clock cycles */
-#define ADC_SAMPLETIME_387CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 387.5 ADC clock cycles */
-#define ADC_SAMPLETIME_810CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 810.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
- * @{
- */
-#define ADC_CALIB_OFFSET ((uint32_t)0x00000000)
-#define ADC_CALIB_OFFSET_LINEARITY (ADC_CR_ADCALLIN)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
- * @{
- */
-
-/**
- * @brief Verify the length of scheduled injected conversions group.
- * @param LENGTH : number of programmed conversions.
- * @retval SET (LENGTH is within the maximum number of possible programmable injected conversions) or RESET (LENGTH is null or too large)
- */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-
-/**
- * @brief Calibration factor length verification (7 bits maximum)
- * @param _Calibration_Factor_: Calibration factor value
- * @retval None
- */
-#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
-
-/**
- * @brief Verify the ADC channel setting.
- * @param __CHANNEL__: programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
- ((__CHANNEL__) == ADC_CHANNEL_1) || \
- ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || \
- ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || \
- ((__CHANNEL__) == ADC_CHANNEL_15) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_18) || \
- ((__CHANNEL__) == ADC_CHANNEL_19) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT_DIV4) || \
- ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
- ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
-
-/**
- * @brief Verify the ADC channel setting in differential mode for ADC1.
- * @param __CHANNEL__: programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
- ((__CHANNEL__) == ADC_CHANNEL_2) ||\
- ((__CHANNEL__) == ADC_CHANNEL_3) ||\
- ((__CHANNEL__) == ADC_CHANNEL_4) ||\
- ((__CHANNEL__) == ADC_CHANNEL_5) ||\
- ((__CHANNEL__) == ADC_CHANNEL_10) ||\
- ((__CHANNEL__) == ADC_CHANNEL_11) ||\
- ((__CHANNEL__) == ADC_CHANNEL_12) ||\
- ((__CHANNEL__) == ADC_CHANNEL_16) ||\
- ((__CHANNEL__) == ADC_CHANNEL_18) )
-
-/**
- * @brief Verify the ADC channel setting in differential mode for ADC2.
- * @param __CHANNEL__: programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
- ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_18) )
-
-/**
- * @brief Verify the ADC channel setting in differential mode for ADC3.
- * @param __CHANNEL__: programmed ADC channel.
- * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
- ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || \
- ((__CHANNEL__) == ADC_CHANNEL_15) )
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__: ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
-
-/**
- * @brief Check if no conversion on going on regular or injected groups
- * @param __HANDLE__: ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Check if no conversion on going on injected group
- * @param __HANDLE__: ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Check whether or not ADC is independent
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC is independent) or RESET (ADC is not)
- */
-#define ADC_IS_INDEPENDENT(__HANDLE__) \
- ( ( ( ((__HANDLE__)->Instance) == ADC3) \
- )? \
- SET \
- : \
- RESET \
- )
-
-/**
- * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
- * @param __SAMPLETIME__: Sample time parameter.
- * @param __CHANNELNB__: Channel number.
- * @retval None
- */
-#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
-
-/**
- * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
- * @param __SAMPLETIME__: Sample time parameter.
- * @param __CHANNELNB__: Channel number.
- * @retval None
- */
-#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 1 and 4.
- * @param __CHANNELNB__: Channel number.
- * @param __RANKNB__: Rank number.
- * @retval None
- */
-#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 5 and 9.
- * @param __CHANNELNB__: Channel number.
- * @param __RANKNB__: Rank number.
- * @retval None
- */
-#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 10 and 14.
- * @param __CHANNELNB__: Channel number.
- * @param __RANKNB__: Rank number.
- * @retval None
- */
-#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 15 and 16.
- * @param __CHANNELNB__: Channel number.
- * @param __RANKNB__: Rank number.
- * @retval None
- */
-#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
-
-/**
- * @brief Set the selected injected Channel rank.
- * @param __CHANNELNB__: Channel number.
- * @param __RANKNB__: Rank number.
- * @retval None
- */
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-3) * (__RANKNB__) +3))
-
-/**
- * @brief Set the Analog Watchdog 1 channel.
- * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
- * @retval None
- */
-#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
-
-/**
- * @brief Configure the channel number into Analog Watchdog 2 or 3.
- * @param __CHANNEL__: ADC Channel
- * @retval None
- */
-#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
-
-/**
- * @brief Enable ADC injected context queue
- * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((uint32_t)(__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
-
-/**
- * @brief Enable ADC discontinuous conversion mode for injected group
- * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
-
-/**
- * @brief Enable ADC discontinuous conversion mode for regular group
- * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
-
-/**
- * @brief Configures the number of discontinuous conversions for regular group.
- * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
-
-/**
- * @brief Enable the ADC auto delay mode.
- * @param __AUTOWAIT__: Auto delay bit enable or disable.
- * @retval None
- */
-#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param __CONTINUOUS_MODE__: Continuous mode.
- * @retval None
- */
-#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
-
-/**
- * @brief Enable the ADC DMA continuous request.
- * @param __DMACONTREQ_MODE__: DMA continuous request mode.
- * @retval None
- */
-#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
-
-/**
- * @brief Configure the channel number into offset OFRx register
- * @param __CHANNEL__: ADC Channel
- * @retval None
- */
-#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
-
-/**
- * @brief Configure the channel number into differential mode selection register
- * @param __CHANNEL__: ADC Channel
- * @retval None
- */
-#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
-
-/**
- * @brief Calibration factor in differential mode to be set into calibration register
- * @param __CALIBRATION_FACTOR__: Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
-
-/**
- * @brief Calibration factor in differential mode to be retrieved from calibration register
- * @param __CALIBRATION_FACTOR__: Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
-
-/**
- * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
- * @param __THRESHOLD__: Threshold value
- * @retval None
- */
-#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
-
-/**
- * @brief Enable the ADC DMA continuous request for ADC multimode.
- * @param __DMACONTREQ_MODE__: DMA continuous request mode.
- * @retval None
- */
-#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
-
-/**
- * @brief Enable the ADC peripheral
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
-
-/**
- * @brief Verification of hardware constraints before ADC can be enabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
- */
-#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
- (( ( ((__HANDLE__)->Instance->CR) & \
- (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \
- ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
- ) == RESET \
- ) ? SET : RESET)
-
-/**
- * @brief Disable the ADC peripheral
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define ADC_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
- __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
- } while(0)
-
-/**
- * @brief Verification of hardware constraints before ADC can be disabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
- */
-#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
- (( ( ((__HANDLE__)->Instance->CR) & \
- (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
- ) ? SET : RESET)
-
-/**
- * @brief Shift the offset in function of the selected ADC resolution.
- * Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0
- * If resolution 16 bits, no shift.
- * If resolution 14 bits, shift of 2 ranks on the left.
- * If resolution 12 bits, shift of 4 ranks on the left.
- * If resolution 10 bits, shift of 6 ranks on the left.
- * If resolution 8 bits, shift of 8 ranks on the left.
- * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
- * @param __HANDLE__: ADC handle
- * @param __OFFSET__: Value to be shifted
- * @retval None
- */
-#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
- ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
-
-/**
- * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
- * Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
- * If resolution 16 bits, no shift.
- * If resolution 14 bits, shift of 2 ranks on the left.
- * If resolution 12 bits, shift of 4 ranks on the left.
- * If resolution 10 bits, shift of 6 ranks on the left.
- * If resolution 8 bits, shift of 8 ranks on the left.
- * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
- * @param __HANDLE__: ADC handle
- * @param __THRESHOLD__: Value to be shifted
- * @retval None
- */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
- ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
-
-/**
- * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
- * Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
- * If resolution 16 bits, no shift.
- * If resolution 14 bits, shift of 2 ranks on the left.
- * If resolution 12 bits, shift of 4 ranks on the left.
- * If resolution 10 bits, shift of 6 ranks on the left.
- * If resolution 8 bits, shift of 8 ranks on the left.
- * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
- * @param __HANDLE__: ADC handle
- * @param __THRESHOLD__: Value to be shifted
- * @retval None
- */
-#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
- ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 2)*2))
-
-/**
- * @brief Report common register to ADC1 and ADC2
- * @param __HANDLE__: ADC handle
- * @retval Common control register
- */
-#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
-
-/**
- * @brief Report common register to ADC1 and ADC2
- * @param __HANDLE__: ADC handle
- * @retval Common control register
- */
-#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
-
-/**
- * @brief Report Master Instance
- * @param __HANDLE__: ADC handle
- * @note return same instance if ADC of input handle is independent ADC
- * @retval Master Instance
- */
-#define ADC_MASTER_REGISTER(__HANDLE__) \
- ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
- )? \
- ((__HANDLE__)->Instance) \
- : \
- (ADC1) \
- )
-
-/**
- * @brief Check whether or not dual regular conversions are enabled
- * @param __HANDLE__: ADC handle
- * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
- */
-#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
- ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
- )? \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
- : \
- RESET \
- )
-
-/**
- * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
- * @param __HANDLE__: ADC handle
- * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
- */
-#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
- )? \
- SET \
- : \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
- )
-
-/**
- * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
- * @param __HANDLE__: ADC handle
- * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
- */
-#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC3) \
- )? \
- SET \
- : \
- ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
- )
-
-/**
- * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
- * @param __HANDLE__: ADC handle
- * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
- */
-#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
- )? \
- SET \
- : \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
-
-/**
- * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
- * @param __HANDLE__: ADC handle
- * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
- */
-#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
- )? \
- SET \
- : \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
-
-/**
- * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter
- * @param __INSTANCE__: ADC instance
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
- (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
- ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
- ) ? SET : RESET)
-
-/**
- * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle
- * @param __HANDLE__: ADC handle
- * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
- */
-#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC1) \
- )? \
- (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
- : \
- ( ( ((__HANDLE__)->Instance == ADC2) \
- )? \
- (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
- : \
- ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
- ) \
-
-/**
- * @brief Set handle instance of the ADC slave associated to the ADC master
- * @param __HANDLE_MASTER__: ADC master handle
- * @param __HANDLE_SLAVE__: ADC slave handle
- * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL
- * @retval None
- */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
-
-/**
- * @brief Verify the ADC single-ended input or differential mode setting.
- * @param SING_DIFF: programmed channel setting.
- * @retval SET (SING_DIFF is valid) or RESET (SING_DIFF is invalid)
- */
-#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \
- ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
-
-/**
- * @brief Verify the ADC offset management setting.
- * @param OFFSET_NUMBER: ADC offset management.
- * @retval SET (OFFSET_NUMBER is valid) or RESET (OFFSET_NUMBER is invalid)
- */
-#define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_1) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_2) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_3) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_4) )
-
-/**
- * @brief Verify the ADC injected channel setting.
- * @param CHANNEL: programmed ADC injected channel.
- * @retval SET (CHANNEL is valid) or RESET (__CHANNEL__ is invalid)
- */
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
- ((CHANNEL) == ADC_INJECTED_RANK_2) || \
- ((CHANNEL) == ADC_INJECTED_RANK_3) || \
- ((CHANNEL) == ADC_INJECTED_RANK_4) )
-
-/**
- * @brief Verify the ADC injected conversions external trigger.
- * @param INJTRIG: programmed ADC injected conversions external trigger.
- * @retval SET (INJTRIG is a valid value) or RESET (INJTRIG is invalid)
- */
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
- \
- ((INJTRIG) == ADC_SOFTWARE_START) )
-
-/**
- * @brief Verify the ADC edge trigger setting for injected group.
- * @param EDGE: programmed ADC edge trigger setting.
- * @retval SET (EDGE is a valid value) or RESET (EDGE is invalid)
- */
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
-
-/**
- * @brief Verify the ADC multimode setting.
- * @param MODE: programmed ADC multimode setting.
- * @retval SET (MODE is valid) or RESET (MODE is invalid)
- */
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERL) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) )
-
-/**
- * @brief Verify the ADC dual data mode setting.
- * @param MODE: programmed ADC dual mode setting.
- * @retval SET (MODE is valid) or RESET (MODE is invalid)
- */
-#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
- ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
- ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )
-
-/**
- * @brief Verify the ADC multimode delay setting.
- * @param DELAY: programmed ADC multimode delay setting.
- * @retval SET (DELAY is a valid value) or RESET (DELAY is invalid)
- */
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES))
-
-/**
- * @brief Verify the ADC analog watchdog setting.
- * @param WATCHDOG: programmed ADC analog watchdog setting.
- * @retval SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)
- */
-#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
-
-/**
- * @brief Verify the ADC analog watchdog mode setting.
- * @param WATCHDOG: programmed ADC analog watchdog mode setting.
- * @retval SET (WATCHDOG is valid) or RESET (WATCHDOG is invalid)
- */
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
-
-/**
- * @brief Verify the ADC conversion (regular or injected or both).
- * @param CONVERSION: ADC conversion group.
- * @retval SET (CONVERSION is valid) or RESET (CONVERSION is invalid)
- */#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
- ((CONVERSION) == ADC_INJECTED_GROUP) || \
- ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
-
-/**
- * @brief Verify the ADC event type.
- * @param EVENT: ADC event.
- * @retval SET (EVENT is valid) or RESET (EVENT is invalid)
- */
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
- ((EVENT) == ADC_AWD_EVENT) || \
- ((EVENT) == ADC_AWD2_EVENT) || \
- ((EVENT) == ADC_AWD3_EVENT) || \
- ((EVENT) == ADC_OVR_EVENT) || \
- ((EVENT) == ADC_JQOVF_EVENT) )
-
-/**
- * @brief Verify the ADC scan mode.
- * @param SCAN_MODE: ADC scan mode.
- * @retval SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)
- */
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
- ((SCAN_MODE) == ADC_SCAN_ENABLE) )
-
-/**
- * @brief Verify the ADC oversampling ratio.
- * @param RATIO: programmed ADC oversampling ratio.
- * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
- */
-#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024)
-
-/**
- * @brief Verify the ADC oversampling right shift.
- * @param SHIFT: programmed ADC oversampling right shift.
- * @retval SET (SHIFT is a valid value) or RESET (SHIFT is invalid)
- */
-#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
-
-/**
- * @brief Verify the ADC oversampling left shift.
- * @param SHIFT: programmed ADC oversampling left shift.
- * @retval SET (SHIFT is a valid value) or RESET (SHIFT is invalid)
- */
-#define IS_ADC_LEFT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_LEFTBITSHIFT_NONE) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_1 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_2 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_3 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_4 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_5 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_6 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_7 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_8 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_9 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_10 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_11 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_12 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_13 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_14 ) || \
- ((SHIFT) == ADC_LEFTBITSHIFT_15 ))
-
-/**
- * @brief Verify the ADC oversampling triggered mode.
- * @param MODE: programmed ADC oversampling triggered mode.
- * @retval SET (MODE is valid) or RESET (MODE is invalid)
- */
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
- ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
-
-/**
- * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
- * @param MODE: programmed ADC oversampling regular conversion resumed or continued mode.
- * @retval SET (MODE is valid) or RESET (MODE is invalid)
- */
-#define IS_ADC_REGOVERSAMPLING_MODE(MODE) (((MODE) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
- ((MODE) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions *********************************/
-
-/** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
- * @brief Extended IO operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-
-/* ADC calibration */
-
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer);
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-
-
-/* ADC multimode */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
-
-
-/* ADC Regular conversions stop */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-
-/**
- * @}
- */
-
-/** @addtogroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
- * @brief ADC Extended Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32H7xx_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h
deleted file mode 100644
index f7489bf..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h
+++ /dev/null
@@ -1,744 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cec.h
- * @author MCD Application Team
- * @brief Header file of CEC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CEC_H
-#define __STM32H7xx_HAL_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CEC_Exported_Types CEC Exported Types
- * @{
- */
-
-/**
- * @brief CEC Init Structure definition
- */
-typedef struct
-{
- uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
- It can be one of @ref CEC_Signal_Free_Time
- and belongs to the set {0,...,7} where
- 0x0 is the default configuration
- else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
-
- uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
- or CEC_EXTENDED_TOLERANCE */
-
- uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
- - CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
- - CEC_RX_STOP_ON_BRE: reception is stopped. */
-
- uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
- CEC line upon Bit Rising Error detection.
- - CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
- - CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
-
- uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
- CEC line upon Long Bit Period Error detection.
- - CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
- - CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
-
- uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
- upon an error detected on a broadcast message.
-
- It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
-
- - CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- - a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
- and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
- - b) LBPE detection: error-bit generation on the CEC line
- if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
-
- - CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
- no error-bit generation in case neither a) nor b) are satisfied. Additionally,
- there is no error-bit generation in case of Short Bit Period Error detection in
- a broadcast message while LSTN bit is set. */
-
- uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
- - CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- - CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
-
- uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
-
- - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
- own address (OAR). Messages addressed to different destination are ignored.
- Broadcast messages are always received.
-
- - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
- address (OAR) with positive acknowledge. Messages addressed to different destination
- are received, but without interfering with the CEC bus: no acknowledge sent. */
-
- uint16_t OwnAddress; /*!< Own addresses configuration
- This parameter can be a value of @ref CEC_OWN_ADDRESS */
-
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
-
-}CEC_InitTypeDef;
-
-/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
- * - gState contains CEC state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6 Error information
- * 0 : No Error
- * 1 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL CEC Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
-
-/**
- * @brief CEC handle Structure definition
- */
-typedef struct
-{
- CEC_TypeDef *Instance; /*!< CEC registers base address */
-
- CEC_InitTypeDef Init; /*!< CEC communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
-
- uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
-
- uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
-}CEC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CEC_Exported_Constants CEC Exported Constants
- * @{
- */
-
-/** @defgroup CEC_Error_Code CEC Error Code
- * @{
- */
-#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
-#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
-#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
-#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
-#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
-#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
-#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
-#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
-#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
-#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
-/**
- * @}
- */
-
-/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
- * @{
- */
-#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
-#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
-#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
-#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
-#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
-#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
-#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
-#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
-/**
- * @}
- */
-
-/** @defgroup CEC_Tolerance CEC Receiver Tolerance
- * @{
- */
-#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
-#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
-/**
- * @}
- */
-
-/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
- * @{
- */
-#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
-#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
-/**
- * @}
- */
-
-/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
- * @{
- */
-#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
-#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
- * @{
- */
-#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
-#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
- * @{
- */
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
-#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
- * @{
- */
-#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
-#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
-/**
- * @}
- */
-
-/** @defgroup CEC_Listening_Mode CEC Listening mode option
- * @{
- */
-#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
-#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
-/**
- * @}
- */
-
-/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
- * @{
- */
-#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
-/**
- * @}
- */
-
-/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
- * @{
- */
-#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
-/**
- * @}
- */
-
-/** @defgroup CEC_OWN_ADDRESS CEC Own Address
- * @{
- */
-#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
-#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
-#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
-#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
-#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
-#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
-#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE
-#define CEC_IT_TXERR CEC_IER_TXERRIE
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE
-#define CEC_IT_TXEND CEC_IER_TXENDIE
-#define CEC_IT_TXBR CEC_IER_TXBRIE
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE
-#define CEC_IT_LBPE CEC_IER_LBPEIE
-#define CEC_IT_SBPE CEC_IER_SBPEIE
-#define CEC_IT_BRE CEC_IER_BREIE
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE
-#define CEC_IT_RXEND CEC_IER_RXENDIE
-#define CEC_IT_RXBR CEC_IER_RXBRIE
-/**
- * @}
- */
-
-/** @defgroup CEC_Flags_Definitions CEC Flags definition
- * @{
- */
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND CEC_ISR_TXEND
-#define CEC_FLAG_TXBR CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE CEC_ISR_LBPE
-#define CEC_FLAG_SBPE CEC_ISR_SBPE
-#define CEC_FLAG_BRE CEC_ISR_BRE
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND CEC_ISR_RXEND
-#define CEC_FLAG_RXBR CEC_ISR_RXBR
-/**
- * @}
- */
-
-/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
- * @{
- */
-#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
-/**
- * @}
- */
-
-/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
- * @{
- */
-#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
-/**
- * @}
- */
-
-/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
- * @{
- */
-#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CEC_Exported_Macros CEC Exported Macros
- * @{
- */
-
-/** @brief Reset CEC handle gstate & RxState
- * @param __HANDLE__: CEC handle.
- * @retval None
- */
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
- } while(0)
-
-/** @brief Checks whether or not the specified CEC interrupt flag is set.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to check.
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval ITStatus
- */
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-
-/** @brief Clears the interrupt or status flag when raised (write at 1)
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the interrupt/status flag to clear.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval none
- */
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
-
-/** @brief Enables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to enable.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval none
- */
-#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/** @brief Disables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to disable.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval none
- */
-#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-
-/** @brief Checks whether or not the specified CEC interrupt is enabled.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
-
-/** @brief Enables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
-
-/** @brief Disables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
-
-/** @brief Set Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
-
-/** @brief Set Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
- */
-#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
-
-/** @brief Get Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
-
-/** @brief Get Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
-
-/** @brief Clear OAR register
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
-
-/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
- * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
- * @retval none
- */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions
- * @{
- */
-
-/** @addtogroup CEC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
-void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @addtogroup CEC_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
-void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
-void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @addtogroup CEC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CEC_Private_Types CEC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Variables CEC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Macros CEC Private Macros
- * @{
- */
-
-#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
-
-#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
- ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
-
-#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
- ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
-
-#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
-
-#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
-
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
-
-#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
- ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
-
-#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
- ((__MODE__) == CEC_FULL_LISTENING_MODE))
-
-/** @brief Check CEC message size.
- * The message size is the payload size: without counting the header,
- * it varies from 0 byte (ping operation, one header only, no payload) to
- * 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__: CEC message size.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
-
-/** @brief Check CEC device Own Address Register (OAR) setting.
- * OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__: CEC own address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
-
-/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h
deleted file mode 100644
index 0098e74..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h
+++ /dev/null
@@ -1,805 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_comp.h
- * @author MCD Application Team
- * @brief Header file of COMP HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_COMP_H
-#define __STM32H7xx_HAL_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup COMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup COMP_Exported_Types COMP Exported Types
- * @{
- */
-
-/**
- * @brief COMP Init structure definition
- */
-typedef struct
-{
-
- uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
- (2 consecutive instances odd and even COMP and COMP).
- Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
- This parameter can be a value of @ref COMP_WindowMode */
-
- uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
- Note: For the characteritics of comparator power modes
- (propagation delay and power consumption), refer to device datasheet.
- This parameter can be a value of @ref COMP_PowerMode */
-
- uint32_t NonInvertingInput; /*!< Set comparator input plus (non-inverting input).
- This parameter can be a value of @ref COMP_InputPlus */
-
- uint32_t InvertingInput; /*!< Set comparator input minus (inverting input).
- This parameter can be a value of @ref COMP_InputMinus */
-
- uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
- This parameter can be a value of @ref COMP_Hysteresis */
-
- uint32_t OutputPol; /*!< Set comparator output polarity.
- This parameter can be a value of @ref COMP_OutputPolarity */
-
- uint32_t BlankingSrce; /*!< Set comparator blanking source.
- This parameter can be a value of @ref COMP_BlankingSrce */
-
- uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
- This parameter can be a value of @ref COMP_EXTI_TriggerMode */
-
-}COMP_InitTypeDef;
-
-/**
- * @brief HAL COMP state machine: HAL COMP states definition
- */
-#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
-typedef enum
-{
- HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized */
- HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
- HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
- HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
- HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
- HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
-}HAL_COMP_StateTypeDef;
-
-/**
- * @brief COMP Handle Structure definition
- */
-typedef struct
-{
- COMP_TypeDef *Instance; /*!< Register base address */
- COMP_InitTypeDef Init; /*!< COMP required parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
-
-} COMP_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
- * @{
- */
-/** @defgroup COMP_WindowMode COMP Window Mode
- * @{
- */
-#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
-#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
-
-/**
- * @}
- */
-
-/** @defgroup COMP_PowerMode COMP power mode
- * @{
- */
-/* Note: For the characteritics of comparator power modes */
-/* (propagation delay and power consumption), */
-/* refer to device datasheet. */
-#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */
-#define COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0) /*!< Medium Speed */
-#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE) /*!< Ultra-low power mode */
-/**
- * @}
- */
-
-/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
- * @{
- */
-#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
-#define COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
-/**
- * @}
- */
-
-/** @defgroup COMP_InputMinus COMP input minus (inverting input)
- * @{
- */
-#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
-#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
-#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
-#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN ) /*!< Comparator input minus connected to VrefInt */
-#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
-#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
-#define COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
-#define COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
-/**
- * @}
- */
-
-/** @defgroup COMP_Hysteresis COMP hysteresis
- * @{
- */
-#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
-#define COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0) /*!< Hysteresis level low */
-#define COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1) /*!< Hysteresis level medium */
-#define COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST) /*!< Hysteresis level high */
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputPolarity COMP Output Polarity
- * @{
- */
-#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
-#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
-/**
- * @}
- */
-
-
-/** @defgroup COMP_BlankingSrce COMP Blanking Source
- * @{
- */
-/* Any blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */
-#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0) /*!< TIM1 OC5 selected as blanking source for comparator */
-#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1) /*!< TIM2 OC3 selected as blanking source for comparator */
-#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1) /*!< TIM3 OC3 selected as blanking source for compartor */
-#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2) /*!< TIM3 OC4 selected as blanking source for comparator */
-#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0) /*!< TIM8 OC5 selected as blanking source for comparator */
-#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1) /*!< TIM15 OC1 selected as blanking source for comparator */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup COMP_OutputLevel COMP Output Level
- * @{
- */
-
-/* Note: Comparator output level values are fixed to "0" and "1", */
-/* corresponding COMP register bit is managed by HAL function to match */
-/* with these values (independently of bit position in register). */
-
-/* When output polarity is not inverted, comparator output is low when
- the input plus is at a lower voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
-/* When output polarity is not inverted, comparator output is high when
- the input plus is at a higher voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)
-
-/**
- * @}
- */
-
-/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
- * @{
- */
-#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< Comparator output triggering no External Interrupt Line */
-#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
-#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
-#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
-#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
-#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Flag COMP Flag
- * @{
- */
-#define COMP_FLAG_C1I COMP_SR_C1IF /*!< Comparator 1 Interrupt Flag */
-#define COMP_FLAG_C2I COMP_SR_C2IF /*!< Comparator 2 Interrupt Flag */
-#define COMP_FLAG_LOCK COMP_CFGRx_LOCK /*!< Lock flag */
-/**
- * @}
- */
-/** @defgroup COMP_IT_CLEAR_Flags COMP Interruption Clear Flags
- * @{
- */
-#define COMP_CLEAR_C1IF COMP_ICFR_C1IF /*!< Clear Comparator 1 Interrupt Flag */
-#define COMP_CLEAR_C2IF COMP_ICFR_C2IF /*!< Clear Comparator 2 Interrupt Flag */
-/**
- * @}
- */
-/** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
- * @{
- */
-#define COMP_IT_EN COMP_CFGRx_ITEN
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup COMP_Exported_Macros COMP Exported Macros
- * @{
- */
-/** @defgroup COMP_Handle_Management COMP Handle Management
- * @{
- */
-
-/** @brief Reset COMP handle state.
- * @param __HANDLE__ COMP handle
- * @retval None
- */
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-
-/**
- * @brief Enable the specified comparator.
- * @param __HANDLE__ COMP handle
- * @retval None
- */
-#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
-
-/**
- * @brief Disable the specified comparator.
- * @param __HANDLE__ COMP handle
- * @retval None
- */
-#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
-
-/**
- * @brief Lock the specified comparator configuration.
- * @note Using this macro induce HAL COMP handle state machine being no
- * more in line with COMP instance state.
- * To keep HAL COMP handle state machine updated, it is recommended
- * to use function "HAL_COMP_Lock')".
- * @param __HANDLE__ COMP handle
- * @retval None
- */
-#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
-
-/**
- * @brief Check whether the specified comparator is locked.
- * @param __HANDLE__ COMP handle
- * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
- */
-#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exti_Management COMP external interrupt line management
- * @{
- */
-
-/**
- * @brief Enable the COMP1 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
-
-
-/**
- * @brief Disable the COMP1 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
-
-
-/**
- * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-
-/**
- * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-
-
-/**
- * @brief Enable the COMP1 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Check whether the COMP1 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
-/**
- * @brief Clear the COMP1 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Generate a software interrupt on the COMP1 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 D3 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 D3 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
-
-
-/**
- * @brief Enable the COMP2 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-
-/**
- * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Enable the COMP2 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Check whether the COMP2 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Clear the the COMP2 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 D3 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 D3 EXTI Line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Generate a software interrupt on the COMP2 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
-
-/** @brief Checks if the specified COMP interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the COMP Handle.
- * This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
- * @param __INTERRUPT__: specifies the COMP interrupt source to check.
- * This parameter can be one of the following values:
- * @arg COMP_IT_EN: Comparator interrupt enable
- *
- * @retval The new state of __IT__ (TRUE or FALSE)
- */
-#define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified COMP flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg COMP_FLAG_C1I: Comparator 1 Interrupt Flag
- * @arg COMP_FLAG_C2I: Comparator 2 Interrupt Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE)
- */
-#define __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the specified COMP pending flag.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg COMP_CLEAR_C1IF : Clear Comparator 1 Interrupt Flag
- * @arg COMP_CLEAR_C2IF : Clear Comparator 2 Interrupt Flag
- * @retval None
- */
-#define __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
-
-/** @brief Clear the COMP C1I flag.
- * @retval None
- */
-#define __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
-
-/** @brief Clear the COMP C2I flag.
- * @retval None
- */
-#define __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
-
-/** @brief Enable the specified COMP interrupt.
- * @param __HANDLE__: specifies the COMP Handle.
- * @param __INTERRUPT__: specifies the COMP interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg COMP_CFGRx_ITEN : Comparator interrupt
- * @retval None
- */
-#define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
-
-/** @brief Disable the specified COMP interrupt.
- * @param __HANDLE__: specifies the COMP Handle.
- * @param __INTERRUPT__: specifies the COMP interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg COMP_CFGRx_ITEN : Comparator interrupt
- * @retval None
- */
-#define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
-
-/**
- * @}
- */
-/** @brief Enable the specified bit in the Option register.
- * @param __AF__: specifies the Alternate Function source selection .
- * This parameter can be one of the following values:
- * @arg COMP_OR_AFOPA6 : Alternate Function PA6 source selection
- * @arg COMP_OR_AFOPA8 : Alternate Function PA8 source selection
- * @arg COMP_OR_AFOPB12 : Alternate Function PB12 source selection
- * @arg COMP_OR_AFOPE6 : Alternate Function PE6 source selection
- * @arg COMP_OR_AFOPE15 : Alternate Function PE15 source selection
- * @arg COMP_OR_AFOPG2 : Alternate Function PG2 source selection
- * @arg COMP_OR_AFOPG3 : Alternate Function PG3 source selection
- * @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
- * @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
- * @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
- * @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
- * @retval None
- */
-#define __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
-
-/** @brief Disable the specified bit in the Option register.
- * @param __AF__: specifies the Alternate Function source selection .
- * This parameter can be one of the following values:
- * @arg COMP_OR_AFOPA6 : Alternate Function PA6 source selection
- * @arg COMP_OR_AFOPA8 : Alternate Function PA8 source selection
- * @arg COMP_OR_AFOPB12 : Alternate Function PB12 source selection
- * @arg COMP_OR_AFOPE6 : Alternate Function PE6 source selection
- * @arg COMP_OR_AFOPE15 : Alternate Function PE15 source selection
- * @arg COMP_OR_AFOPG2 : Alternate Function PG2 source selection
- * @arg COMP_OR_AFOPG3 : Alternate Function PG3 source selection
- * @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
- * @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
- * @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
- * @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
- * @retval None
- */
-#define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_Private_Constants COMP Private Constants
- * @{
- */
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
- * @{
- */
-#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP1 output */
-#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21) /*!< EXTI line 21 connected to COMP2 output */
-/**
- * @}
- */
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
- * @{
- */
-#define COMP_EXTI_IT ((uint32_t) 0x01) /*!< EXTI line event with interruption */
-#define COMP_EXTI_EVENT ((uint32_t) 0x02) /*!< EXTI line event only (without interruption) */
-#define COMP_EXTI_RISING ((uint32_t) 0x10) /*!< EXTI line event on rising edge */
-#define COMP_EXTI_FALLING ((uint32_t) 0x20) /*!< EXTI line event on falling edge */
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMP_Private_Macros COMP Private Macros
- * @{
- */
-/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
- * @{
- */
-/**
- * @brief Get the specified EXTI line for a comparator instance.
- * @param __INSTANCE__: specifies the COMP instance.
- * @retval value of @ref COMP_ExtiLine
- */
-#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
- COMP_EXTI_LINE_COMP2)
-/**
- * @}
- */
-/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
- * @{
- */
-#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
- ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
-
-#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
- ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
- ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
-
-
-#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
- ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
-
-
-
-#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
-
-
-#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
- ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
- ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
- ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
-
-#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
- ((__POL__) == COMP_OUTPUTPOL_INVERTED))
-
-#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \
- ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
-
-
-#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
-
-#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
- ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
- * @{
- */
-
-/** @addtogroup COMP_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-/* Callback in Interrupt mode */
-void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/* Peripheral State functions **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
- * @{
- */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h
deleted file mode 100644
index b0bb450..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_conf_template.h
- * @author MCD Application Team
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32h7xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CONF_H
-#define __STM32H7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CEC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DCMI_MODULE_ENABLED
-#define HAL_DFSDM_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_DMA2D_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_FDCAN_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_HASH_MODULE_ENABLED
-#define HAL_HCD_MODULE_ENABLED
-#define HAL_HRTIM_MODULE_ENABLED
-#define HAL_HSEM_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_JPEG_MODULE_ENABLED
-#define HAL_LPTIM_MODULE_ENABLED
-#define HAL_LTDC_MODULE_ENABLED
-#define HAL_MDIOS_MODULE_ENABLED
-#define HAL_MDMA_MODULE_ENABLED
-#define HAL_MMC_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_QSPI_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SAI_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SDRAM_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SMBUS_MODULE_ENABLED
-#define HAL_SPDIFRX_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_SWPMI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal oscillator (CSI) default value.
- * This value is the default CSI value after Reset.
- */
-#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief External Low Speed oscillator (LSE) value.
- * This value is used by the UART, RTC HAL module to compute the system frequency
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define USE_RTOS 0
-#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
-
-/* ########################### Ethernet Configuration ######################### */
-#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
-#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
-
-#define ETH_MAC_ADDR0 ((uint8_t)0x02)
-#define ETH_MAC_ADDR1 ((uint8_t)0x00)
-#define ETH_MAC_ADDR2 ((uint8_t)0x00)
-#define ETH_MAC_ADDR3 ((uint8_t)0x00)
-#define ETH_MAC_ADDR4 ((uint8_t)0x00)
-#define ETH_MAC_ADDR5 ((uint8_t)0x00)
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1 */
-
-/* ################## SPI peripheral configuration ########################## */
-/**
- * @brief Used to activate CRC feature inside HAL SPI Driver
- * Activated (1U): CRC code is compiled within HAL SPI driver
- * Deactivated (0U): CRC code excluded from HAL SPI driver
- */
-
-#define USE_SPI_CRC 1U
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32h7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32h7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32h7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32h7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32h7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
- #include "stm32h7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32h7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
- #include "stm32h7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32h7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32h7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
- #include "stm32h7xx_hal_fdcan.h"
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32h7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32h7xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32h7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32h7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32h7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32h7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
- #include "stm32h7xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
- #include "stm32h7xx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32h7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32h7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32h7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32h7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32h7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32h7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
- #include "stm32h7xx_hal_mdma.h"
-#endif /* HAL_MDMA_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32h7xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32h7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-#include "stm32h7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32h7xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32h7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32h7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32h7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32h7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32h7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32h7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32h7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32h7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32h7xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32h7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32h7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32h7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32h7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32h7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32h7xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32h7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32h7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
deleted file mode 100644
index f6d269a..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CORTEX_H
-#define __STM32H7xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
-#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
-#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
-#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-#define MPU_REGION_NUMBER8 ((uint8_t)0x08)
-#define MPU_REGION_NUMBER9 ((uint8_t)0x09)
-#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)
-#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)
-#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)
-#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)
-#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)
-#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)
-
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-
-/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
- * @{
- */
-#define CM7_CPUID (uint32_t)0x00000003
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-uint32_t HAL_GetCurrentCPUID(void);
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7) || \
- ((NUMBER) == MPU_REGION_NUMBER8) || \
- ((NUMBER) == MPU_REGION_NUMBER9) || \
- ((NUMBER) == MPU_REGION_NUMBER10) || \
- ((NUMBER) == MPU_REGION_NUMBER11) || \
- ((NUMBER) == MPU_REGION_NUMBER12) || \
- ((NUMBER) == MPU_REGION_NUMBER13) || \
- ((NUMBER) == MPU_REGION_NUMBER14) || \
- ((NUMBER) == MPU_REGION_NUMBER15))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h
deleted file mode 100644
index 87299a9..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CRC_H
-#define __STM32H7xx_HAL_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRC CRC
- * @brief CRC HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
- * @{
- */
-
-/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
- * @{
- */
-typedef enum
-{
- HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
- HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
-}HAL_CRC_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
- * @{
- */
-typedef struct
-{
- uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
- If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
- In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
-
- uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
- If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
- 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
-
- uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
- e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
-
- uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
- Value can be either one of
- CRC_POLYLENGTH_32B (32-bit CRC)
- CRC_POLYLENGTH_16B (16-bit CRC)
- CRC_POLYLENGTH_8B (8-bit CRC)
- CRC_POLYLENGTH_7B (7-bit CRC) */
-
- uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
- is set to DEFAULT_INIT_VALUE_ENABLE */
-
- uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
- Can be either one of the following values
- CRC_INPUTDATA_INVERSION_NONE no input data inversion
- CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
-
- uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
- Can be either
- CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
- CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
-}CRC_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
- * @{
- */
-typedef struct
-{
- CRC_TypeDef *Instance; /*!< Register base address */
-
- CRC_InitTypeDef Init; /*!< CRC configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< CRC Locking object */
-
- __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-
- uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
- Can be either
- CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
- CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
- CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
- Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
- must occur if InputBufferFormat is not one of the three values listed above */
-}CRC_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC exported constants
- * @{
- */
-
-/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
- * @{
- */
-#define DEFAULT_CRC32_POLY 0x04C11DB7U
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
- * @{
- */
-#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
- * @{
- */
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
-
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
- * @{
- */
-#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
- * @{
- */
-#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
-#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
-#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
-#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
-/**
- * @}
- */
-
-/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
- * @{
- */
-#define HAL_CRC_LENGTH_32B 32U
-#define HAL_CRC_LENGTH_16B 16U
-#define HAL_CRC_LENGTH_8B 8U
-#define HAL_CRC_LENGTH_7B 7U
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Input_Buffer_Format CRC input buffer format
- * @{
- */
-/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
- * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
- * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
- * the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
-#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
-#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
-#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Macros CRC exported macros
- * @{
- */
-
-/** @brief Reset CRC handle state
- * @param __HANDLE__: CRC handle.
- * @retval None
- */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
- * @brief Reset CRC Data Register.
- * @param __HANDLE__: CRC handle
- * @retval None.
- */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
- * @brief Set CRC INIT non-default value
- * @param __HANDLE__ : CRC handle
- * @param __INIT__ : 32-bit initial value
- * @retval None.
- */
-#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
-
-/**
- * @brief Stores a 32-bit data in the Independent Data(ID) register.
- * @param __HANDLE__: CRC handle
- * @param __VALUE__: 32-bit value to be stored in the ID register
- * @retval None
- */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
- * @brief Returns the 32-bit data stored in the Independent Data(ID) register.
- * @param __HANDLE__: CRC handle
- * @retval 32-bit value of the ID register
- */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
- * @}
- */
-
-
-/* Include CRC HAL Extension module */
-#include "stm32h7xx_hal_crc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/* Aliases for inter STM32 series compatibility */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRC_Private_Types CRC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRC_Private_Defines CRC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Variables CRC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Constants CRC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRC_Private_Macros CRC Private Macros
- * @{
- */
-#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
- ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
-#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
- ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
-#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_8B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_7B))
-#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
-
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h
deleted file mode 100644
index 824952b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_crc_ex.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CRC_EX_H
-#define __STM32H7xx_HAL_CRC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRCEx CRCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
- * @{
- */
-
-/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
- * @{
- */
-#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
-#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
-#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
-#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
-
-#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
-/**
- * @}
- */
-
-/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
- * @{
- */
-#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
-#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
- ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
- * @{
- */
-
-/**
- * @brief Set CRC output reversal
- * @param __HANDLE__ : CRC handle
- * @retval None.
- */
-#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
-
-/**
- * @brief Unset CRC output reversal
- * @param __HANDLE__ : CRC handle
- * @retval None.
- */
-#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
-
-/**
- * @brief Set CRC non-default polynomial
- * @param __HANDLE__ : CRC handle
- * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
- * @retval None.
- */
-#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
-
-/**
- * @}
- */
-
-
-/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
- * @{
- */
-
-/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
- * @{
- */
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h
deleted file mode 100644
index fa34fe4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cryp.h
- * @author MCD Application Team
- * @brief Header file of CRYP HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CRYP_H
-#define __STM32H7xx_HAL_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#if defined (CRYP)
-/** @addtogroup CRYP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
- * @{
- */
-
-/**
- * @brief CRYP Init Structure definition
- */
-
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
- This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
- counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
- AES Algorithm ECB/CBC/CTR/GCM or CCM
- This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
- GCM : also known as Additional Authentication Data
- CCM : named B1 composed of the associated data length and Associated Data. */
- uint32_t HeaderSize; /*!< The size of header buffer in word */
- uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
-}CRYP_ConfigTypeDef;
-
-
-/**
- * @brief CRYP State Structure definition
- */
-
-typedef enum
-{
- HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
- HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
-
-/**
- * @brief CRYP handle Structure definition
- */
-
-typedef struct
-{
-
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
-
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
-
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
-
- uint32_t Phase; /*!< CRYP peripheral phase */
-
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
-}CRYP_HandleTypeDef;
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Error_Definition CRYP Error Definition
- * @{
- */
-#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
-#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
-#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
-#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
-#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
-#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
-/**
- * @}
- */
-
-
-/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
- * @{
- */
-
-#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
-#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
-#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
-#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
-#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
-#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
-#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
-#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Size CRYP Key Size
- * @{
- */
-
-#define CRYP_KEYSIZE_128B 0x00000000U
-#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
-#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
- * @{
- */
-
-#define CRYP_DATATYPE_32B 0x00000000U
-#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Interrupt CRYP Interrupt
- * @{
- */
-
-#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Flags CRYP Flags
- * @{
- */
-
-/* Flags in the SR register */
-#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
-#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
- or a key preparation (for AES decryption). */
-/* Flags in the RISR register */
-#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
- * @{
- */
-
-/**
- * @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__: specifies the CRYP handle.
- * @retval None
- */
-
-#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-
-/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
- * @arg CRYP_FLAG_IFEM: Input FIFO is empty
- * @arg CRYP_FLAG_IFNF: Input FIFO is not full
- * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
- * @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
- */
-#define CRYP_FLAG_MASK 0x0000001FU
-
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
-
-/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
- * This parameter can be one of the following values for CRYP:
- * @arg CRYP_IT_INI: Input FIFO service masked interrupt status
- * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
- * @retval The state of __INTERRUPT__ (TRUE or FALSE).
- */
-
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Enable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for CRYP:
- * @ CRYP_IT_INI : Input FIFO service interrupt mask.
- * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
- * @retval None
- */
-
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for CRYP:
- * @ CRYP_IT_INI : Input FIFO service interrupt mask.
- * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
- * @retval None
- */
-
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Include CRYP HAL Extended module */
-#include "stm32h7xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
-
-/** @addtogroup CRYP_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-
-/**
- * @}
- */
-
-/** @addtogroup CRYP_Exported_Functions_Group2
- * @{
- */
-
-/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-
-/**
- * @}
- */
-
-
-/** @addtogroup CRYP_Exported_Functions_Group3
- * @{
- */
-/* Interrupt Handler functions **********************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
- * @{
- */
-
-/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
- * @{
- */
-
-#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM) || \
- ((ALGORITHM) == CRYP_AES_CCM))
-
-#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_256B))
-
-#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
- ((DATATYPE) == CRYP_DATATYPE_16B) || \
- ((DATATYPE) == CRYP_DATATYPE_8B) || \
- ((DATATYPE) == CRYP_DATATYPE_1B))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
- * @{
- */
-
-/**
- * @}
- */
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-#endif /* CRYP */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h
deleted file mode 100644
index 387ab9b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cryp_ex.h
- * @author MCD Application Team
- * @brief Header file of CRYP HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CRYP_EX_H
-#define __STM32H7xx_HAL_CRYP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#if defined (CRYP)
-/** @addtogroup CRYPEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
- /* Private types -------------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
- * @{
- */
-
- /**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
- * @{
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* CRYP */
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h
deleted file mode 100644
index 980f2b7..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DAC_H
-#define __STM32H7xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
-
-}HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
- */
-typedef struct
-{
- DAC_TypeDef *Instance; /*!< Register base address */
-
- __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
-
- HAL_LockTypeDef Lock; /*!< DAC locking object */
-
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
- __IO uint32_t ErrorCode; /*!< DAC Error code */
-
-}DAC_HandleTypeDef;
-
-/**
- * @brief DAC Configuration sample and hold Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
- This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
-
- uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
- This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
-
- uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
- This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
- This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-}
-DAC_SampleAndHoldConfTypeDef;
-
-/**
- * @brief DAC Configuration regular Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
- This parameter can be a value of @ref DAC_SampleAndHold */
-
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-
- uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
- This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
-
- uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
- This parameter must be a value of @ref DAC_UserTrimming
- DAC_UserTrimming is either factory or user trimming */
-
- uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
- i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
- DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
-
-}DAC_ChannelConfTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_Error_Code DAC Error Code
- * @{
- */
-#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
-#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
-#define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */
-/**
- * @}
- */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
- * @{
- */
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T1_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_HR1_TRGO1 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_HR1_TRGO2 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LP1_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LP1 OUT TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LP2_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LP2 OUT TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-/**
- * @}
- */
-
- /** @defgroup DAC_output_buffer DAC output buffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)
-
- /**
- * @}
- */
-
-/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
- * @{
- */
-#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
-#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_UserTrimming DAC User Trimming
- * @{
- */
-
-#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
-#define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_SampleAndHold. Mode is Sample and hold (low power or normal)
- * @{
- */
-#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
-#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)
-
-
-/**
- * @}
- */
-
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
- * @{
- */
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment DAC data alignment
- * @{
- */
-#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition DAC flags definition
- * @{
- */
-#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_IT_definition DAC IT definition
- * @{
- */
-#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @brief Reset DAC handle state.
- * @param __HANDLE__: specifies the DAC handle.
- * @retval None
- */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __DAC_Channel__: specifies the DAC channel
- * @retval None
- */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel.
- * @param __HANDLE__: specifies the DAC handle
- * @param __DAC_Channel__: specifies the DAC channel.
- * @retval None
- */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Set DHR12R1 alignment.
- * @param __ALIGNMENT__: specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
-
-/** @brief Set DHR12R2 alignment.
- * @param __ALIGNMENT__: specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
-
-/** @brief Set DHR12RD alignment.
- * @param __ALIGNMENT__: specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief Check whether the specified DAC interrupt source is enabled or not.
- * @param __HANDLE__: DAC handle
- * @param __INTERRUPT__: DAC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the DAC flag to get.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the DAC's flag.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the DAC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-
-#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF)
-
-/**
- * @}
- */
-
-/* Include DAC HAL Extended module */
-#include "stm32h7xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*__STM32H7xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h
deleted file mode 100644
index d6fcc79..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dac_ex.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DAC_EX_H
-#define __STM32H7xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DACEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
- * @{
- */
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
- * @{
- */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
- ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
- ((TRIGGER) == DAC_TRIGGER_LP1_OUT) || \
- ((TRIGGER) == DAC_TRIGGER_LP2_OUT) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF)
-
-#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF)
-
-#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
- ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
-
-
-#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
-
-#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
-
-#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
- ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
-
-#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
- ((TRIMMING) == DAC_TRIMMING_USER))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
- /** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
-
-/**
- * @}
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
-
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32H7xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h
deleted file mode 100644
index 1f7c04b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h
+++ /dev/null
@@ -1,622 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dcmi.h
- * @author MCD Application Team
- * @brief Header file of DCMI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DCMI_H
-#define __STM32H7xx_HAL_DCMI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DCMI DCMI
- * @brief DCMI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DCMI_Exported_Types DCMI Exported Types
- * @{
- */
-/**
- * @brief HAL DCMI State structures definition
- */
-typedef enum
-{
- HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
- HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
- HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
- HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
- HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
- HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
-}HAL_DCMI_StateTypeDef;
-
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-}DCMI_CodesInitTypeDef;
-
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
- DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
- line/frame end delimiter */
-
- uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-
- uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
- This parameter can be a value of @ref DCMI_Byte_Select_Mode */
-
- uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
- This parameter can be a value of @ref DCMI_Byte_Select_Start */
-
- uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
- This parameter can be a value of @ref DCMI_Line_Select_Mode */
-
- uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
- This parameter can be a value of @ref DCMI_Line_Select_Start */
-}DCMI_InitTypeDef;
-
-/**
- * @brief DCMI handle Structure definition
- */
-typedef struct
-{
- DCMI_TypeDef *Instance; /*!< DCMI Register base address */
-
- DCMI_InitTypeDef Init; /*!< DCMI parameters */
-
- HAL_LockTypeDef Lock; /*!< DCMI locking object */
-
- __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
-
- __IO uint32_t XferCount; /*!< DMA transfer counter */
-
- __IO uint32_t XferSize; /*!< DMA transfer size */
-
- uint32_t XferTransferNumber; /*!< DMA transfer number */
-
- uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
-
- __IO uint32_t ErrorCode; /*!< DCMI Error code */
-
-}DCMI_HandleTypeDef;
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
- * @{
- */
-
-/** @defgroup DCMI_Error_Code DCMI Error Code
- * @{
- */
-#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
-#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
- * @{
- */
-#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously
- into the destination memory through the DMA */
-#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
- frame and then transfers a single frame through the DMA */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
- * @{
- */
-#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
- is synchronized with the HSYNC/VSYNC signals */
-#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
- synchronization codes embedded in the data flow */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
- * @{
- */
-#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */
-#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
- * @{
- */
-#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */
-#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
- * @{
- */
-#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */
-#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
- * @{
- */
-#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */
-#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
- * @{
- */
-#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */
-#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
-#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
- * @{
- */
-#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
- * @{
- */
-#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Window_Height DCMI Window Height
- * @{
- */
-#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
- * @{
- */
-#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
-#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
-#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
-#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
-#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Flags DCMI Flags
- * @{
- */
-
-/**
- * @brief DCMI SR register
- */
-#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
-#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
-#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
-/**
- * @brief DCMI RIS register
- */
-#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
-#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
-#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
-#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
-#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
-/**
- * @brief DCMI MIS register
- */
-#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
-#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
-#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
-#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
-#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
- * @{
- */
-#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */
-#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
-#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
-#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
- * @{
- */
-#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
-#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
- * @{
- */
-#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */
-#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
- * @{
- */
-#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
-#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
- * @{
- */
-
-/** @brief Reset DCMI handle state
- * @param __HANDLE__: specifies the DCMI handle.
- * @retval None
- */
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
-
-/**
- * @brief Enable the DCMI.
- * @param __HANDLE__: DCMI handle
- * @retval None
- */
-#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
-
-/**
- * @brief Disable the DCMI.
- * @param __HANDLE__: DCMI handle
- * @retval None
- */
-#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
-
-/* Interrupt & Flag management */
-/**
- * @brief Get the DCMI pending flag.
- * @param __HANDLE__: DCMI handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be one of the following values (no combination allowed)
- * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
- * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
- * @arg DCMI_FLAG_FNE: FIFO empty flag
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
- * @arg DCMI_FLAG_OVRRI: Overrun flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
- * @arg DCMI_FLAG_LINERI: Line flag mask
- * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
- * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
- * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
- * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
- * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
- * @retval The state of FLAG.
- */
-#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
-((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
- (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
-
-/**
- * @brief Clear the DCMI pending flags.
- * @param __HANDLE__: DCMI handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
- * @arg DCMI_FLAG_LINERI: Line flag mask
- * @retval None
- */
-#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enable the specified DCMI interrupts.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified DCMI interrupts.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified DCMI interrupt has occurred or not.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The state of INTERRUPT.
- */
-#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
- * @{
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
-void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
-void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
-HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
-
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
-uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DCMI_Private_Constants DCMI Private Constants
- * @{
- */
-#define DCMI_MIS_INDEX (0x1000) /*!< DCMI MIS register index */
-#define DCMI_SR_INDEX (0x2000) /*!< DCMI SR register index */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup DCMI_Private_Macros DCMI Private Macros
- * @{
- */
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
- ((MODE) == DCMI_MODE_SNAPSHOT))
-
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
- ((MODE) == DCMI_SYNCHRO_EMBEDDED))
-
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
- ((POLARITY) == DCMI_PCKPOLARITY_RISING))
-
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_VSPOLARITY_HIGH))
-
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_HSPOLARITY_HIGH))
-
-#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
- ((JPEG_MODE) == DCMI_JPEG_ENABLE))
-
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
-
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
- ((DATA) == DCMI_EXTEND_DATA_10B) || \
- ((DATA) == DCMI_EXTEND_DATA_12B) || \
- ((DATA) == DCMI_EXTEND_DATA_14B))
-
-#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
-
-#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
-
-#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
- ((MODE) == DCMI_BSM_OTHER) || \
- ((MODE) == DCMI_BSM_ALTERNATE_4) || \
- ((MODE) == DCMI_BSM_ALTERNATE_2))
-
-#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
- ((POLARITY) == DCMI_OEBS_EVEN))
-
-#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
- ((MODE) == DCMI_LSM_ALTERNATE_2))
-
-#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
- ((POLARITY) == DCMI_OELS_EVEN))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DCMI_Private_Functions DCMI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
deleted file mode 100644
index a55ffb9..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DEF
-#define __STM32H7xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
-{
- HAL_OK = 0x00,
- HAL_ERROR = 0x01,
- HAL_BUSY = 0x02,
- HAL_TIMEOUT = 0x03
-} HAL_StatusTypeDef;
-
-/**
- * @brief HAL Lock structures definition
- */
-typedef enum
-{
- HAL_UNLOCKED = 0x00,
- HAL_LOCKED = 0x01
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#ifndef NULL
- #define NULL (void *) 0
-#endif
-
-#define HAL_MAX_DELAY 0xFFFFFFFF
-
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0)
-
-#define UNUSED(x) ((void)(x))
-
-/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
- * - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
- * to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
- * HAL_PPP_Init() is called, the low level hardware initialization will be missed
- * (i.e. HAL_PPP_MspInit() will not be executed).
- * - When there is a need to reconfigure the low level hardware: instead of calling
- * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
- * In this later function, when the Handle's "State" field is set to 0, it will execute the function
- * HAL_PPP_MspInit() which will reconfigure the low level hardware.
- * @retval None
- */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
- #error " USE_RTOS should be 0 in the current HAL release "
-#else
- #define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0)
-
- #define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
-#endif /* USE_RTOS */
-
-#if defined ( __GNUC__ )
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif /* __weak */
- #ifndef __packed
- #define __packed __attribute__((__packed__))
- #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__GNUC__) /* GNU Compiler */
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif /* __ALIGN_BEGIN */
-#else
- #ifndef __ALIGN_END
- #define __ALIGN_END
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #endif /* __CC_ARM */
- #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
-#if defined (__GNUC__) /* GNU Compiler */
- #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
-#elif defined (__ICCARM__) /* IAR Compiler */
- #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
-#elif defined (__CC_ARM) /* ARM Compiler */
- #define ALIGN_32BYTES(buf) __align(32) buf
-#endif
-
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
-*/
-#define __RAM_FUNC HAL_StatusTypeDef
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined ( __GNUC__ )
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32H7xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h
deleted file mode 100644
index 697371b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h
+++ /dev/null
@@ -1,714 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dfsdm.h
- * @author MCD Application Team
- * @brief Header file of DFSDM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DFSDM_H
-#define __STM32H7xx_HAL_DFSDM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DFSDM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
- * @{
- */
-
-/**
- * @brief HAL DFSDM Channel states definition
- */
-typedef enum
-{
- HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, /*!< DFSDM channel not initialized */
- HAL_DFSDM_CHANNEL_STATE_READY = 0x01, /*!< DFSDM channel initialized and ready for use */
- HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF /*!< DFSDM channel state error */
-}HAL_DFSDM_Channel_StateTypeDef;
-
-/**
- * @brief DFSDM channel output clock structure definition
- */
-typedef struct
-{
- FunctionalState Activation; /*!< Output clock enable/disable */
- uint32_t Selection; /*!< Output clock is system clock or audio clock.
- This parameter can be a value of @ref DFSDM_Channel_OuputClock */
- uint32_t Divider; /*!< Output clock divider.
- This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
-}DFSDM_Channel_OutputClockTypeDef;
-
-/**
- * @brief DFSDM channel input structure definition
- */
-typedef struct
-{
- uint32_t Multiplexer; /*!< Input is external serial inputs ,internal register or ADC output.
- This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
- uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
- This parameter can be a value of @ref DFSDM_Channel_DataPacking */
- uint32_t Pins; /*!< Input pins are taken from same or following channel.
- This parameter can be a value of @ref DFSDM_Channel_InputPins */
-}DFSDM_Channel_InputTypeDef;
-
-/**
- * @brief DFSDM channel serial interface structure definition
- */
-typedef struct
-{
- uint32_t Type; /*!< SPI or Manchester modes.
- This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
- uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
- This parameter can be a value of @ref DFSDM_Channel_SpiClock */
-}DFSDM_Channel_SerialInterfaceTypeDef;
-
-/**
- * @brief DFSDM channel analog watchdog structure definition
- */
-typedef struct
-{
- uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
- This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
- uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
- This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-}DFSDM_Channel_AwdTypeDef;
-
-/**
- * @brief DFSDM channel init structure definition
- */
-typedef struct
-{
- DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
- DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
- DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
- DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
- int32_t Offset; /*!< DFSDM channel offset.
- This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
- uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-}DFSDM_Channel_InitTypeDef;
-
-/**
- * @brief DFSDM channel handle structure definition
- */
-typedef struct
-{
- DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
- DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
- HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
-}DFSDM_Channel_HandleTypeDef;
-
-/**
- * @brief HAL DFSDM Filter states definition
- */
-typedef enum
-{
- HAL_DFSDM_FILTER_STATE_RESET = 0x00, /*!< DFSDM filter not initialized */
- HAL_DFSDM_FILTER_STATE_READY = 0x01, /*!< DFSDM filter initialized and ready for use */
- HAL_DFSDM_FILTER_STATE_REG = 0x02, /*!< DFSDM filter regular conversion in progress */
- HAL_DFSDM_FILTER_STATE_INJ = 0x03, /*!< DFSDM filter injected conversion in progress */
- HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, /*!< DFSDM filter regular and injected conversions in progress */
- HAL_DFSDM_FILTER_STATE_ERROR = 0xFF /*!< DFSDM filter state error */
-}HAL_DFSDM_Filter_StateTypeDef;
-
-/**
- * @brief DFSDM filter regular conversion parameters structure definition
- */
-typedef struct
-{
- uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
- This parameter can be a value of @ref DFSDM_Filter_Trigger */
- FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
- FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
-}DFSDM_Filter_RegularParamTypeDef;
-
-/**
- * @brief DFSDM filter injected conversion parameters structure definition
- */
-typedef struct
-{
- uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
- This parameter can be a value of @ref DFSDM_Filter_Trigger */
- FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
- FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
- uint32_t ExtTrigger; /*!< External trigger.
- This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
- uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
- This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
-}DFSDM_Filter_InjectedParamTypeDef;
-
-/**
- * @brief DFSDM filter parameters structure definition
- */
-typedef struct
-{
- uint32_t SincOrder; /*!< Sinc filter order.
- This parameter can be a value of @ref DFSDM_Filter_SincOrder */
- uint32_t Oversampling; /*!< Filter oversampling ratio.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
- uint32_t IntOversampling; /*!< Integrator oversampling ratio.
- This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
-}DFSDM_Filter_FilterParamTypeDef;
-
-/**
- * @brief DFSDM filter init structure definition
- */
-typedef struct
-{
- DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
- DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
- DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
-}DFSDM_Filter_InitTypeDef;
-
-/**
- * @brief DFSDM filter handle structure definition
- */
-typedef struct
-{
- DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
- DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
- DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
- DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
- uint32_t RegularContMode; /*!< Regular conversion continuous mode */
- uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
- uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
- uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
- FunctionalState InjectedScanMode; /*!< Injected scanning mode */
- uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
- uint32_t InjConvRemaining; /*!< Injected conversions remaining */
- HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
- uint32_t ErrorCode; /*!< DFSDM filter error code */
-}DFSDM_Filter_HandleTypeDef;
-
-/**
- * @brief DFSDM filter analog watchdog parameters structure definition
- */
-typedef struct
-{
- uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
- This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
- uint32_t Channel; /*!< Analog watchdog channel selection.
- This parameter can be a values combination of @ref DFSDM_Channel_Selection */
- int32_t HighThreshold; /*!< High threshold for the analog watchdog.
- This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
- int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
- This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
- uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
- This parameter can be a values combination of @ref DFSDM_BreakSignals */
- uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
- This parameter can be a values combination of @ref DFSDM_BreakSignals */
-}DFSDM_Filter_AwdParamTypeDef;
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
- * @{
- */
-
-/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
- * @{
- */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000) /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
- * @{
- */
-#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000) /*!< Data are taken from external inputs */
-#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */
-#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
- * @{
- */
-#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000) /*!< Standard data packing mode */
-#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
-#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
- * @{
- */
-#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000) /*!< Input from pins on same channel */
-#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
- * @{
- */
-#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000) /*!< SPI with rising edge */
-#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
-#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
-#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
- * @{
- */
-#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000) /*!< External SPI clock */
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
-#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
- * @{
- */
-#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */
-#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
-#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
-#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
- * @{
- */
-#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
-#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with DFSDM0 */
-#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002) /*!< External trigger (only for injected conversion) */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
- * @{
- */
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1 and 2 */
-#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0 and 1 */
-#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
-#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
-#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1, 2 and 3 */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
- * @{
- */
-#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
-#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
-#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
- * @{
- */
-#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */
-#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
-#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
-#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
-#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
-#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
- * @{
- */
-#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000) /*!< From digital filter */
-#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
- * @{
- */
-#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
-#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
-#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_BreakSignals DFSDM break signals
- * @{
- */
-#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000) /*!< No break signal */
-#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001) /*!< Break signal 0 */
-#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002) /*!< Break signal 1 */
-#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004) /*!< Break signal 2 */
-#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008) /*!< Break signal 3 */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
- * @{
- */
-/* DFSDM Channels ------------------------------------------------------------*/
-/* The DFSDM channels are defined as follows:
- - in 16-bit LSB the channel mask is set
- - in 16-bit MSB the channel number is set
- e.g. for channel 5 definition:
- - the channel mask is 0x00000020 (bit 5 is set)
- - the channel number 5 is 0x00050000
- --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
-#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001)
-#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002)
-#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004)
-#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008)
-#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010)
-#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020)
-#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040)
-#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080)
-/**
- * @}
- */
-
-/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
- * @{
- */
-#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
-#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
-/**
- * @}
- */
-
-/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
- * @{
- */
-#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000) /*!< Analog watchdog high threshold */
-#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001) /*!< Analog watchdog low threshold */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
- * @{
- */
-
-/** @brief Reset DFSDM channel handle state.
- * @param __HANDLE__: DFSDM channel handle.
- * @retval None
- */
-#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
-
-/** @brief Reset DFSDM filter handle state.
- * @param __HANDLE__: DFSDM filter handle.
- * @retval None
- */
-#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
-
-/**
- * @}
- */
-/* End of exported macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
- * @{
- */
-
-/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
- * @{
- */
-/* Channel initialization and de-initialization functions *********************/
-HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-/**
- * @}
- */
-
-/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
- * @{
- */
-/* Channel operation functions ************************************************/
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-
-int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
-
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
-
-void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
- * @{
- */
-/* Channel state function *****************************************************/
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
-/**
- * @}
- */
-
-/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
- * @{
- */
-/* Filter initialization and de-initialization functions *********************/
-HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-/**
- * @}
- */
-
-/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
- * @{
- */
-/* Filter control functions *********************/
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel,
- uint32_t ContinuousMode);
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
- * @{
- */
-/* Filter operation functions *********************/
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- DFSDM_Filter_AwdParamTypeDef* awdParam);
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-
-int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-
-void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
-
-void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
-void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
- * @{
- */
-/* Filter state functions *****************************************************/
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
-* @{
-*/
-#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
- ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
-#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
-#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
- ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
- ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
-#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
- ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
- ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
-#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
- ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
-#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
- ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
- ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
- ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
-#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
- ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
- ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
- ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
-#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
- ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
- ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
- ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
-#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
-#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
-#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
-#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
-#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
- ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
-#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
- ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
-#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2) || \
- ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3))
-#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
- ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
- ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
-#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
- ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
- ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
- ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
- ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
- ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
-#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
-#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
-#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
- ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
-#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
-#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF)
-#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
- ((CHANNEL) == DFSDM_CHANNEL_1) || \
- ((CHANNEL) == DFSDM_CHANNEL_2) || \
- ((CHANNEL) == DFSDM_CHANNEL_3) || \
- ((CHANNEL) == DFSDM_CHANNEL_4) || \
- ((CHANNEL) == DFSDM_CHANNEL_5) || \
- ((CHANNEL) == DFSDM_CHANNEL_6) || \
- ((CHANNEL) == DFSDM_CHANNEL_7))
-#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))
-#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
- ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
-/**
-* @}
-*/
-/* End of private macros ------------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_DFSDM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
deleted file mode 100644
index c63db99..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
+++ /dev/null
@@ -1,1118 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DMA_H
-#define __STM32H7xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @brief DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Request; /*!< Specifies the request selected for the specified stream.
- This parameter can be a value of @ref DMA_Request_selection */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
- This parameter can be a value of @ref DMA_Priority_level */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
- This parameter can be a value of @ref DMA_FIFO_direct_mode
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected stream */
-
- uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_FIFO_threshold_level */
-
- uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_Memory_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-
- uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_Peripheral_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
- HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Transfer complete level structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Callbacks IDs structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
- HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
- HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- void *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
-
- void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
-
- uint32_t StreamIndex; /*!< DMA Stream Index */
-
- DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */
-
- DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
-
- uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
-
-
- DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
-
- DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */
-
- uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
-
-}DMA_HandleTypeDef;
-
-/**
- * @}
- */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @brief DMA Exported constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @brief DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
-#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */
-#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */
-#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */
-#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */
-#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
-#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */
-#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */
-#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Request_selection DMA Request selection
- * @brief DMA Request selection
- * @{
- */
-/* D2 Domain : DMAMUX1 requests */
-#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
-
-#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
-#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
-#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
-#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
-#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
-#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
-#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
-#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
-
-#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */
-#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */
-
-#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
-#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
-#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
-#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
-#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
-#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
-#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
-
-#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
-#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
-#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
-#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
-#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
-
-#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
-#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
-#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
-#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
-#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
-#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
-
-#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
-#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
-#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
-#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
-
-#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
-#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
-#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
-#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
-
-#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
-#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
-#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
-#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
-
-#define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
-#define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
-#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
-#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
-#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
-#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
-
-#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
-#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
-#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
-#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
-#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
-#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
-#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
-
-#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
-#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
-#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
-#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
-#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
-#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
-
-#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
-#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
-
-#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
-#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
-#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
-#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
-
-#define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
-#define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
-
-#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
-#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
-
-#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
-#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
-
-#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
-#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
-
-#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
-
-#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
-#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
-
-#define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
-
-#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
-#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
-#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
-#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
-
-#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
-#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
-#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
-#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
-
-#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
-#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
-#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
-#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
-
-#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
-#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
-
-#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
-#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
-
-#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
-#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
-#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
-#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
-#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
-#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
-
-#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
-#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
-#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */
-#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */
-
-#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
-#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
-#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
-#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
-
-#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
-#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
-
-#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
-#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
-
-#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
-#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
-
-#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */
-
-
-/* D3 Domain : DMAMUX2 requests */
-#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
-#define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
-#define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
-#define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
-#define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
-#define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
-#define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
-#define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
-#define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
-#define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
-#define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
-#define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
-#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
-#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
-#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
-#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
-#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
-#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @brief DMA data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @brief DMA peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @brief DMA memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @brief DMA peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @brief DMA memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @brief DMA mode
- * @{
- */
-#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
-#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @brief DMA priority levels
- * @{
- */
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
-/**
- * @}
- */
-
-/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
- * @brief DMA FIFO direct mode
- * @{
- */
-#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
- * @brief DMA FIFO level
- * @{
- */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
-#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_burst DMA Memory burst
- * @brief DMA memory burst
- * @{
- */
-#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
-#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
-#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
-#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
- * @brief DMA peripheral burst
- * @{
- */
-#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
-#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @brief DMA interrupts definition
- * @{
- */
-#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE ((uint32_t)0x00000080U)
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @brief DMA flag definitions
- * @{
- */
-#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
-#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
-#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
-#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
-#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
-#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
-#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
-#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
-#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
-#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
-#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
-#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
-#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
-#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
-#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
-#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
-#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
-#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
-#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
-#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
-/**
- * @}
- */
-
-/** @defgroup BDMA_flag_definitions BDMA flag definitions
- * @brief BDMA flag definitions
- * @{
- */
-#define BDMA_FLAG_GL0 ((uint32_t)0x00000001)
-#define BDMA_FLAG_TC0 ((uint32_t)0x00000002)
-#define BDMA_FLAG_HT0 ((uint32_t)0x00000004)
-#define BDMA_FLAG_TE0 ((uint32_t)0x00000008)
-#define BDMA_FLAG_GL1 ((uint32_t)0x00000010)
-#define BDMA_FLAG_TC1 ((uint32_t)0x00000020)
-#define BDMA_FLAG_HT1 ((uint32_t)0x00000040)
-#define BDMA_FLAG_TE1 ((uint32_t)0x00000080)
-#define BDMA_FLAG_GL2 ((uint32_t)0x00000100)
-#define BDMA_FLAG_TC2 ((uint32_t)0x00000200)
-#define BDMA_FLAG_HT2 ((uint32_t)0x00000400)
-#define BDMA_FLAG_TE2 ((uint32_t)0x00000800)
-#define BDMA_FLAG_GL3 ((uint32_t)0x00001000)
-#define BDMA_FLAG_TC3 ((uint32_t)0x00002000)
-#define BDMA_FLAG_HT3 ((uint32_t)0x00004000)
-#define BDMA_FLAG_TE3 ((uint32_t)0x00008000)
-#define BDMA_FLAG_GL4 ((uint32_t)0x00010000)
-#define BDMA_FLAG_TC4 ((uint32_t)0x00020000)
-#define BDMA_FLAG_HT4 ((uint32_t)0x00040000)
-#define BDMA_FLAG_TE4 ((uint32_t)0x00080000)
-#define BDMA_FLAG_GL5 ((uint32_t)0x00100000)
-#define BDMA_FLAG_TC5 ((uint32_t)0x00200000)
-#define BDMA_FLAG_HT5 ((uint32_t)0x00400000)
-#define BDMA_FLAG_TE5 ((uint32_t)0x00800000)
-#define BDMA_FLAG_GL6 ((uint32_t)0x01000000)
-#define BDMA_FLAG_TC6 ((uint32_t)0x02000000)
-#define BDMA_FLAG_HT6 ((uint32_t)0x04000000)
-#define BDMA_FLAG_TE6 ((uint32_t)0x08000000)
-#define BDMA_FLAG_GL7 ((uint32_t)0x10000000)
-#define BDMA_FLAG_TC7 ((uint32_t)0x20000000)
-#define BDMA_FLAG_HT7 ((uint32_t)0x40000000)
-#define BDMA_FLAG_TE7 ((uint32_t)0x80000000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state
- * @param __HANDLE__: specifies the DMA handle.
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Return the current DMA Stream FIFO filled level.
- * @param __HANDLE__: DMA handle
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
-
-/**
- * @brief Enable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) \
-((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
-(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
-
-/**
- * @brief Disable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) \
-((IS_D2_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
-(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Return the current DMA Stream transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Return the current DMA Stream half transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Return the current DMA Stream transfer error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Return the current DMA Stream FIFO error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified FIFO error flag index.
- */
-#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Return the current DMA Stream direct mode error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified direct mode error flag index.
- */
-#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Returns the current BDMA Channel Global interrupt flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
- (uint32_t)0x00000000)
-
-/**
- * @brief Get the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag.
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
- * @arg DMA_FLAG_TEIFx: Transfer error flag.
- * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
- * @arg DMA_FLAG_FEIFx: FIFO error flag.
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
-
-/**
- * @brief Clear the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag.
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
- * @arg DMA_FLAG_TEIFx: Transfer error flag.
- * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
- * @arg DMA_FLAG_FEIFx: FIFO error flag.
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
-
-
-#define D2_TO_D3_DMA_IT(__DMA_IT__) \
-((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
-(((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
-(((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
-(((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\
-((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
-((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
-((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
-(uint32_t)0x00000000)
-
-
-#define __HAL_DMA_D3_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
-(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (D2_TO_D3_DMA_IT(__INTERRUPT__)))
-
-#define __HAL_DMA_D2_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
-(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
-
-/**
- * @brief Enable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
- (__HAL_DMA_D2_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
- (__HAL_DMA_D3_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
-
-
-#define __HAL_DMA_D3_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(D2_TO_D3_DMA_IT(__INTERRUPT__)))
-
-#define __HAL_DMA_D2_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
-(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
-
-/**
- * @brief Disable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
- (__HAL_DMA_D2_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
- (__HAL_DMA_D3_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
-
-
-#define __HAL_DMA_D3_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (D2_TO_D3_DMA_IT(__INTERRUPT__))))
-
-#define __HAL_DMA_D2_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
- (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
- (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
-
-/**
- * @brief Check whether the specified DMA Stream interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval The state of DMA_IT.
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? \
- (__HAL_DMA_D2_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
- (__HAL_DMA_D3_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
-
-/**
- * @brief Writes the number of data units to be transferred on the DMA Stream.
- * @param __HANDLE__: DMA handle
- * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_D2_DMA_INSTANCE(__HANDLE__))? \
- (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
- (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param __HANDLE__: DMA handle
- *
- * @retval The number of remaining data units in the current DMA Stream transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_D2_DMA_INSTANCE(__HANDLE__))?\
- (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
- (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
-
-/**
- * @}
- */
-
-/* Include DMA HAL Extension module */
-#include "stm32h7xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @brief DMA Exported functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
- * @brief I/O operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/**
- * @}
- */
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
- * @brief DMA private defines and constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @brief DMA private macros
- * @{
- */
-
-#define IS_DMA_D2_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
-
-#define IS_BDMA_D3_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
-
-#define IS_D2_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))
-#define IS_D3_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)BDMA_Channel0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)BDMA_Channel7)))
-
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR) || \
- ((MODE) == DMA_PFCTRL))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
- ((STATE) == DMA_FIFOMODE_ENABLE))
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
- ((BURST) == DMA_MBURST_INC4) || \
- ((BURST) == DMA_MBURST_INC8) || \
- ((BURST) == DMA_MBURST_INC16))
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
- ((BURST) == DMA_PBURST_INC4) || \
- ((BURST) == DMA_PBURST_INC8) || \
- ((BURST) == DMA_PBURST_INC16))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @brief DMA private functions
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h
deleted file mode 100644
index d71c505..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h
+++ /dev/null
@@ -1,627 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma2d.h
- * @author MCD Application Team
- * @brief Header file of DMA2D HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DMA2D_H
-#define __STM32H7xx_HAL_DMA2D_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA2D DMA2D
- * @brief DMA2D HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
- * @{
- */
-#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
-
-/**
- * @brief DMA2D color Structure definition
- */
-typedef struct
-{
- uint32_t Blue; /*!< Configures the blue value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Green; /*!< Configures the green value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Red; /*!< Configures the red value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-} DMA2D_ColorTypeDef;
-
-/**
- * @brief DMA2D CLUT Structure definition
- */
-typedef struct
-{
- uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
-
- uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
- This parameter can be one value of @ref DMA2D_CLUT_CM. */
-
- uint32_t Size; /*!< Configures the DMA2D CLUT size.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
-} DMA2D_CLUTCfgTypeDef;
-
-/**
- * @brief DMA2D Init structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Configures the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_Mode. */
-
- uint32_t ColorMode; /*!< Configures the color format of the output image.
- This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
-
- uint32_t OutputOffset; /*!< Specifies the Offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
- uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
- This parameter can be one value of @ref DMA2D_Alpha_Inverted */
-
- uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
- for the output pixel format converter.
- This parameter can be one value of @ref DMA2D_RB_Swap. */
-
-} DMA2D_InitTypeDef;
-
-
-/**
- * @brief DMA2D Layer structure definition
- */
-typedef struct
-{
- uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
-
- uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
- This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
-
- uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
- This parameter can be one value of @ref DMA2D_Alpha_Mode. */
-
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
- Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- - InputAlpha[24:31] is the alpha value ALPHA[0:7]
- - InputAlpha[16:23] is the red value RED[0:7]
- - InputAlpha[8:15] is the green value GREEN[0:7]
- - InputAlpha[0:7] is the blue value BLUE[0:7]. */
-
- uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
- This parameter can be one value of @ref DMA2D_Alpha_Inverted.*/
-
- uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
- This parameter can be one value of @ref DMA2D_RB_Swap. */
-
- uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
- This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
-} DMA2D_LayerCfgTypeDef;
-
-/**
- * @brief HAL DMA2D State structures definition
- */
-typedef enum
-{
- HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
- HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
- HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
-}HAL_DMA2D_StateTypeDef;
-
-/**
- * @brief DMA2D handle Structure definition
- */
-typedef struct __DMA2D_HandleTypeDef
-{
- DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
-
- DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
-
- void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
-
- void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
-
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA2D lock. */
-
- __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
-
- __IO uint32_t ErrorCode; /*!< DMA2D error code. */
-} DMA2D_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
- * @{
- */
-
-/** @defgroup DMA2D_Error_Code DMA2D Error Code
- * @{
- */
-#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
-#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
-#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
-#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Mode DMA2D Mode
- * @{
- */
-#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
-#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
-#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
- * @{
- */
-#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
-#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
-#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
-#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
-#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
- * @{
- */
-#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
-#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
-#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
-#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
-#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
-#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
-#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
-#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
-#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
-#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
-#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
-#define DMA2D_INPUT_YCBCR ((uint32_t)0x0000000BU) /*!< YCbCr color mode */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
- * @{
- */
-#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
-#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
-#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
- * @{
- */
-#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
-#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
- * @{
- */
-#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
-#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
- * @{
- */
-#define DMA2D_NO_CSS ((uint32_t)0x00000000) /*!< No chroma sub-sampling 4:4:4 */
-#define DMA2D_CSS_422 ((uint32_t)0x00000001) /*!< chroma sub-sampling 4:2:2 */
-#define DMA2D_CSS_420 ((uint32_t)0x00000002) /*!< chroma sub-sampling 4:2:0 */
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
- * @{
- */
-#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
-#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_Interrupts DMA2D Interrupts
- * @{
- */
-#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
-#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
-#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
-#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
-#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
-#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Flags DMA2D Flags
- * @{
- */
-#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
-#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
- * @{
- */
-
-/** @brief Reset DMA2D handle state
- * @param __HANDLE__: specifies the DMA2D handle.
- * @retval None
- */
-#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
-
-/**
- * @brief Enable the DMA2D.
- * @param __HANDLE__: DMA2D handle
- * @retval None.
- */
-#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
-
-
-/* Interrupt & Flag management */
-/**
- * @brief Get the DMA2D pending flags.
- * @param __HANDLE__: DMA2D handle
- * @param __FLAG__: flag to check.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_FLAG_CE: Configuration error flag
- * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
- * @arg DMA2D_FLAG_CAE: CLUT access error flag
- * @arg DMA2D_FLAG_TW: Transfer Watermark flag
- * @arg DMA2D_FLAG_TC: Transfer complete flag
- * @arg DMA2D_FLAG_TE: Transfer error flag
- * @retval The state of FLAG.
- */
-#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-
-/**
- * @brief Clear the DMA2D pending flags.
- * @param __HANDLE__: DMA2D handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_FLAG_CE: Configuration error flag
- * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
- * @arg DMA2D_FLAG_CAE: CLUT access error flag
- * @arg DMA2D_FLAG_TW: Transfer Watermark flag
- * @arg DMA2D_FLAG_TC: Transfer complete flag
- * @arg DMA2D_FLAG_TE: Transfer error flag
- * @retval None
- */
-#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
-
-/**
- * @brief Enable the specified DMA2D interrupts.
- * @param __HANDLE__: DMA2D handle
- * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_IT_CE: Configuration error interrupt mask
- * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
- * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
- * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
- * @arg DMA2D_IT_TC: Transfer complete interrupt mask
- * @arg DMA2D_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified DMA2D interrupts.
- * @param __HANDLE__: DMA2D handle
- * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA2D_IT_CE: Configuration error interrupt mask
- * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
- * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
- * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
- * @arg DMA2D_IT_TC: Transfer complete interrupt mask
- * @arg DMA2D_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified DMA2D interrupt source is enabled or not.
- * @param __HANDLE__: DMA2D handle
- * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA2D_IT_CE: Configuration error interrupt mask
- * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
- * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
- * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
- * @arg DMA2D_IT_TC: Transfer complete interrupt mask
- * @arg DMA2D_IT_TE: Transfer error interrupt mask
- * @retval The state of INTERRUPT source.
- */
-#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
- * @{
- */
-
-/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *******************************/
-HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
-
-/**
- * @}
- */
-
-
-/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
-void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
-HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State functions ***************************************************/
-HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
-uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
- * @{
- */
-
-/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
- * @{
- */
-#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Color_Value DMA2D Color Value
- * @{
- */
-#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Offset DMA2D Offset
- * @{
- */
-#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Size DMA2D Size
- * @{
- */
-#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
-#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
- * @{
- */
-#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D maximum CLUT size */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
- * @{
- */
-#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
-#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
- ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
-#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
-#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
-#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
-#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
- ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
- ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
- ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
- ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
- ((INPUT_CM) == DMA2D_INPUT_A4) || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
-#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
- ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
- ((AlphaMode) == DMA2D_COMBINE_ALPHA))
-
-#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
- ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
-
-#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
- ((RB_Swap) == DMA2D_RB_SWAP))
-
-#define IS_DMA2D_CHROMA_SUB_SAMPLING (CSS) (((CSS) == DMA2D_NO_CSS) || \
- ((CSS) == DMA2D_CSS_422) || \
- ((CSS) == DMA2D_CSS_420))
-
-#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
-#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
-#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
-#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
-#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_DMA2D_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
deleted file mode 100644
index 3aef16e..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_DMA_EX_H
-#define __STM32H7xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
- * @brief DMAEx Exported types
- * @{
- */
-
-/**
- * @brief HAL DMA Memory definition
- */
-typedef enum
-{
- MEMORY0 = 0x00U, /*!< Memory 0 */
- MEMORY1 = 0x01U, /*!< Memory 1 */
-
-}HAL_DMA_MemoryTypeDef;
-
-/**
- * @brief HAL DMAMUX Synchronization configuration structure definition
- */
-typedef struct
-{
- uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
- This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
-
- uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
- This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
-
- FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
- This parameter can take the value ENABLE or DISABLE*/
-
-
- FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
- This parameter can take the value ENABLE or DISABLE */
-
- uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
- This parameters can be in the range 1 to 32 */
-
-}HAL_DMA_MuxSyncConfigTypeDef;
-
-
-/**
- * @brief HAL DMAMUX request generator parameters structure definition
- */
-typedef struct
-{
- uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
- This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
-
- uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
- This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
-
- uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event.
- This parameters can be in the range 1 to 32 */
-
-}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
- * @brief DMAEx Exported constants
- * @{
- */
-
-/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
- * @brief DMAEx MUX SyncSignalID selection
- * @{
- */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< D2 Domain synchronization Signal is LPTIM1 OUT */
-#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< D2 Domain synchronization Signal is LPTIM2 OUT */
-#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< D2 Domain synchronization Signal is LPTIM3 OUT */
-#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< D2 Domain synchronization Signal is EXTI0 IT */
-#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< D2 Domain synchronization Signal is TIM12 TRGO */
-
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel0 Event */
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel1 Event */
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel2 Event */
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel3 Event */
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel4 Event */
-#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel5 Event */
-#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< D3 Domain synchronization Signal is LPUART1 RX Wakeup */
-#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< D3 Domain synchronization Signal is LPUART1 TX Wakeup */
-#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< D3 Domain synchronization Signal is LPTIM2 output */
-#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< D3 Domain synchronization Signal is LPTIM3 output */
-#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< D3 Domain synchronization Signal is I2C4 Wakeup */
-#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< D3 Domain synchronization Signal is SPI6 Wakeup */
-#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< D3 Domain synchronization Signal is Comparator 1 output */
-#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< D3 Domain synchronization Signal is RTC Wakeup */
-#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< D3 Domain synchronization Signal is EXTI0 IT */
-#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< D3 Domain synchronization Signal is EXTI2 IT */
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
- * @brief DMAEx MUX SyncPolarity selection
- * @{
- */
-#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */
-#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
-#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
-#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
-
-/**
- * @}
- */
-
-
-/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
- * @brief DMAEx MUX SignalGeneratorID selection
- * @{
- */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< D2 domain Request generator Signal is LPTIM1 OUT */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< D2 domain Request generator Signal is LPTIM2 OUT */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< D2 domain Request generator Signal is LPTIM3 OUT */
-#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< D2 domain Request generator Signal is EXTI0 IT */
-#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< D2 domain Request generator Signal is TIM12 TRGO */
-
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< D3 domain Request generator Signal is DMAMUX2 Channel0 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< D3 domain Request generator Signal is DMAMUX2 Channel1 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< D3 domain Request generator Signal is DMAMUX2 Channel2 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< D3 domain Request generator Signal is DMAMUX2 Channel3 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< D3 domain Request generator Signal is DMAMUX2 Channel4 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< D3 domain Request generator Signal is DMAMUX2 Channel5 Event */
-#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< D3 domain Request generator Signal is DMAMUX2 Channel6 Event */
-#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< D3 domain Request generator Signal is LPUART1 RX Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< D3 domain Request generator Signal is LPUART1 TX Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< D3 domain Request generator Signal is LPTIM2 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< D3 domain Request generator Signal is LPTIM2 OUT */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< D3 domain Request generator Signal is LPTIM3 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< D3 domain Request generator Signal is LPTIM3 OUT */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< D3 domain Request generator Signal is LPTIM4 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< D3 domain Request generator Signal is LPTIM5 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< D3 domain Request generator Signal is I2C4 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< D3 domain Request generator Signal is SPI6 Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< D3 domain Request generator Signal is Comparator 1 output */
-#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< D3 domain Request generator Signal is Comparator 2 output */
-#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< D3 domain Request generator Signal is RTC Wakeup */
-#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< D3 domain Request generator Signal is EXTI0 */
-#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< D3 domain Request generator Signal is EXTI2 */
-#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< D3 domain Request generator Signal is I2C4 IT Event */
-#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< D3 domain Request generator Signal is SPI6 IT */
-#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< D3 domain Request generator Signal is LPUART1 Tx IT */
-#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< D3 domain Request generator Signal is LPUART1 Rx IT */
-#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< D3 domain Request generator Signal is ADC3 IT */
-#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output */
-#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< D3 domain Request generator Signal is BDMA Channel 0 IT */
-#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< D3 domain Request generator Signal is BDMA Channel 1 IT */
-
-
-/**
- * @}
- */
-
-/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
- * @brief DMAEx MUX RequestGeneneratorPolarity selection
- * @{
- */
-#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
-#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
-#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
-#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
- * @brief DMAEx Exported functions
- * @{
- */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- * @{
- */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
-
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Macros DMA Private Macros
- * @brief DMAEx private macros
- * @{
- */
-
-#define IS_D2_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
-#define IS_D3_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
-
-#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
-
-#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
-
-#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
-
-#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
- ((EVENT) == ENABLE))
-
-#define IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
-#define IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
-
-#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
-
-#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
- ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
- * @brief DMAEx Private functions
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h
deleted file mode 100644
index 597c487..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h
+++ /dev/null
@@ -1,1600 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_eth.h
- * @author MCD Application Team
- * @brief Header file of ETH HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_ETH_H
-#define STM32H7xx_HAL_ETH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ETH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-#ifndef ETH_TX_DESC_CNT
- #define ETH_TX_DESC_CNT 4
-#endif
-
-#ifndef ETH_RX_DESC_CNT
- #define ETH_RX_DESC_CNT 4
-#endif
-
-/*********************** Descriptors struct def section ************************/
-/** @defgroup ETH_Exported_Types ETH Exported Types
- * @{
- */
-
-/**
- * @brief ETH DMA Descriptor structure definition
- */
-#if defined ( __GNUC__ )
-typedef struct __attribute__((packed))
-#else
-typedef __packed struct
-#endif
-{
- uint32_t DESC0;
- uint32_t DESC1;
- uint32_t DESC2;
- uint32_t DESC3;
- uint32_t BackupAddr0; /* used to store rx buffer 1 address */
- uint32_t BackupAddr1; /* used to store rx buffer 2 address */
-}ETH_DMADescTypeDef;
-/**
- *
- */
-
-/**
- * @brief ETH Buffers List structure definition
- */
-typedef struct __ETH_BufferTypeDef
-{
- uint8_t *buffer; /*State = HAL_ETH_STATE_RESET)
-
-/**
- * @brief Enables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * enabled @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * disabled. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Gets the ETHERNET DMA IT source enabled or disabled.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
- * @retval The ETH DMA IT Source enabled or disabled
- */
-#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Gets the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
- * @retval The state of ETH DMA IT (SET or RESET)
- */
-#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clears the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
- * @retval The state of ETH DMA FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Clears the specified ETHERNET DMA flag.
-* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
- * @retval The state of ETH DMA FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
-
-/**
- * @brief Enables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
- * enabled @ref ETH_MAC_Interrupts
- * @retval None
- */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
- * enabled @ref ETH_MAC_Interrupts
- * @retval None
- */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified ETHERNET MAC flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
- * @retval The state of ETH MAC IT (SET or RESET).
- */
-#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
-
-/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
-#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000) /* !< 86 - 64 = 22 */
-
-/**
- * @brief Enable the ETH WAKEUP Exti Line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
-
-/**
- * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval EXTI ETH WAKEUP Line Status.
- */
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the ETH WAKEUP Exti flag.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
-
-
-/**
- * @brief enable rising edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
- (EXTI->RTSR3 |= (__EXTI_LINE__))
-
-/**
- * @brief enable falling edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
- (EXTI->FTSR3 |= (__EXTI_LINE__))
-
-/**
- * @brief enable falling edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
- (EXTI->FTSR3 |= (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
-
-/**
- * @}
- */
-
-/* Include ETH HAL Extension module */
-#include "stm32h7xx_hal_eth_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup ETH_Exported_Functions
- * @{
- */
-
-/** @addtogroup ETH_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de initialization functions **********************************/
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
-/**
- * @}
- */
-
-/** @addtogroup ETH_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
-
-uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *pBuffer);
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
-
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
-
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
-
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/** @addtogroup ETH_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions **********************************************/
-/* MAC & DMA Configuration APIs **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
-HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
-void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
-
-/* MAC VLAN Processing APIs ************************************************/
-void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
-
-/* MAC L2 Packet Filtering APIs **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
-
-/* MAC Power Down APIs *****************************************************/
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
-void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
-
-/**
- * @}
- */
-
-/** @addtogroup ETH_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_HAL_ETH_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
deleted file mode 100644
index 203a2cf..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_eth_ex.h
- * @author MCD Application Team
- * @brief Header file of ETH HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_ETH_EX_H
-#define STM32H7xx_HAL_ETH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ETHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
- * @{
- */
-
-/**
- * @brief ETH RX VLAN structure definition
- */
-typedef struct{
- FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
-
- uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
- This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
-
- FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
-
- FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
-
- FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
-
- FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
-
- uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
- This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
-
- uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
- This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
-
- FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
-}ETH_RxVLANConfigTypeDef;
-/**
- *
- */
-
-/**
- * @brief ETH TX VLAN structure definition
- */
-typedef struct{
- FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
-
- FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
-
- uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
- This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
-}ETH_TxVLANConfigTypeDef;
-/**
- *
- */
-
-/**
- * @brief ETH L3 filter structure definition
- */
-typedef struct{
- uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
- This parameter can be a value of @ref ETHEx_L3_Protocol */
-
- uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
- This parameter can be a value of @ref ETHEx_L3_Source_Match */
-
- uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
- This parameter can be a value of @ref ETHEx_L3_Destination_Match */
-
- uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
- This parameter can be a value from 0 to 31 */
-
- uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
- This parameter can be a value from 0 to 31 */
-
- uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
- This parameter can be a value from 0x0 to 0xFFFFFFFF */
-
- uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
- This parameter can be a value from 0 to 0xFFFFFFFF */
-
- uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
- This parameter must be a table of 4 words (4* 32 bits) */
-}ETH_L3FilterConfigTypeDef;
-/**
- *
- */
-
-/**
- * @brief ETH L4 filter structure definition
- */
-typedef struct{
- uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
- This parameter can be a value of @ref ETHEx_L4_Protocol */
-
- uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
- This parameter can be a value of @ref ETHEx_L4_Source_Match */
-
- uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
- This parameter can be a value of @ref ETHEx_L4_Destination_Match */
-
- uint32_t SourcePort; /*!< Sets the L4 filter source port
- This parameter must be a value from 0x0 to 0xFFFF */
-
- uint32_t DestinationPort; /*!< Sets the L4 filter destination port
- This parameter must be a value from 0x0 to 0xFFFF */
-}ETH_L4FilterConfigTypeDef;
-/**
- *
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
- * @{
- */
-
-/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
- * @{
- */
-#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
-#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
-#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
-#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
- * @{
- */
-#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)
-#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
- * @{
- */
-#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)
-#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
- * @{
- */
-#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
-#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
- * @{
- */
-#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
-#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
-#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
- * @{
- */
-#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
-#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
-#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
- * @{
- */
-#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
-#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
- * @{
- */
-#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
-#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
-#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
- * @{
- */
-#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
-#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
-#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
- * @{
- */
-#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
-#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
-#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
-#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
-/**
- * @}
- */
-
-/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
- * @{
- */
-#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
-#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
-#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
-#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
-/**
- * @}
- */
-
-/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
- * @{
- */
-#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
-#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
-#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
- * @{
- */
-#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
-#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
-#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
-#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
-/**
- * @}
- */
-
-/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
- * @{
- */
-#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
-#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ETHEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup ETHEx_Exported_Functions_Group1
- * @{
- */
-/* MAC ARP Offloading APIs ***************************************************/
-void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
-void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
-void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
-
-/* MAC L3 L4 Filtering APIs ***************************************************/
-void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
-void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
-
-/* MAC VLAN Processing APIs ************************************************/
-void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
-void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
-void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
-
-/* Energy Efficient Ethernet APIs *********************************************/
-void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
-void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_HAL_ETH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
deleted file mode 100644
index c650db0..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
+++ /dev/null
@@ -1,2284 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_fdcan.h
- * @author MCD Application Team
- * @brief Header file of FDCAN HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_FDCAN_H
-#define __STM32H7xx_HAL_FDCAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FDCAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
- HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
- HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
- HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
-}HAL_FDCAN_StateTypeDef;
-
-/**
- * @brief FDCAN Init structure definition
- */
-typedef struct
-{
- uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
- This parameter can be a value of @ref FDCAN_frame_format */
-
- uint32_t Mode; /*!< Specifies the FDCAN mode.
- This parameter can be a value of @ref FDCAN_operating_mode */
-
- FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
-
- FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
- This parameter can be set to ENABLE or DISABLE */
-
- FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
- divided for generating the nominal bit time quanta.
- This parameter must be a number between 1 and 512 */
-
- uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
- hardware is allowed to lengthen or shorten a bit to perform
- resynchronization.
- This parameter must be a number between 1 and 128 */
-
- uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter must be a number between 2 and 256 */
-
- uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter must be a number between 2 and 128 */
-
- uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
- divided for generating the data bit time quanta.
- This parameter must be a number between 1 and 32 */
-
- uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
- hardware is allowed to lengthen or shorten a data bit to
- perform resynchronization.
- This parameter must be a number between 1 and 16 */
-
- uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
- This parameter must be a number between 1 and 32 */
-
- uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
- This parameter must be a number between 1 and 16 */
-
- uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address.
- This parameter must be a number between 0 and 2560 */
-
- uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
- This parameter must be a number between 0 and 128 */
-
- uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
- This parameter must be a number between 0 and 64 */
-
- uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements.
- This parameter must be a number between 0 and 64 */
-
- uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
- This parameter can be a value of @ref FDCAN_data_field_size */
-
- uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements.
- This parameter must be a number between 0 and 64 */
-
- uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
- This parameter can be a value of @ref FDCAN_data_field_size */
-
- uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements.
- This parameter must be a number between 0 and 64 */
-
- uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element.
- This parameter can be a value of @ref FDCAN_data_field_size */
-
- uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements.
- This parameter must be a number between 0 and 32 */
-
- uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers.
- This parameter must be a number between 0 and 32 */
-
- uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
- This parameter must be a number between 0 and 32 */
-
- uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
- This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
-
- uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element.
- This parameter can be a value of @ref FDCAN_data_field_size */
-
-}FDCAN_InitTypeDef;
-
-/**
- * @brief FDCAN clock calibration unit structure definition
- */
-typedef struct
-{
- uint32_t ClockCalibration; /*!< Enable or disable the clock calibration.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration
- is bypassed.
- This parameter can be a value of @ref FDCAN_clock_divider */
-
- uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The
- actual configured number of periods is MinOscClkPeriods x 32.
- This parameter must be a number between 0x00 and 0xFF */
-
- uint32_t CalFieldLength; /*!< Specifies the calibration field length.
- This parameter can be a value of @ref FDCAN_calibration_field_length */
-
- uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
- This parameter must be a number between 4 and 25 */
-
- uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter.
- If set to zero the counter is disabled.
- This parameter must be a number between 0x0000 and 0xFFFF */
-
-}FDCAN_ClkCalUnitTypeDef;
-
-/**
- * @brief FDCAN filter structure definition
- */
-typedef struct
-{
- uint32_t IdType; /*!< Specifies the identifier type.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between:
- - 0 and 127, if IdType is FDCAN_STANDARD_ID
- - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t FilterType; /*!< Specifies the filter type.
- This parameter can be a value of @ref FDCAN_filter_type.
- The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
- only when IdType is FDCAN_EXTENDED_ID.
- This parameter is ignored if FilterConfig is set to
- FDCAN_FILTER_TO_RXBUFFER */
-
- uint32_t FilterConfig; /*!< Specifies the filter configuration.
- This parameter can be a value of @ref FDCAN_filter_config */
-
- uint32_t FilterID1; /*!< Specifies the filter identification 1.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t FilterID2; /*!< Specifies the filter identification 2.
- This parameter is ignored if FilterConfig is set to
- FDCAN_FILTER_TO_RXBUFFER.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the
- matching message will be stored.
- This parameter must be a number between 0 and 63.
- This parameter is ignored if FilterConfig is different
- from FDCAN_FILTER_TO_RXBUFFER */
-
- uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
- calibration messages.
- This parameter is ignored if FilterConfig is different
- from FDCAN_FILTER_TO_RXBUFFER.
- This parameter can be:
- - 0 : ordinary message
- - 1 : calibration message */
-
-}FDCAN_FilterTypeDef;
-
-/**
- * @brief FDCAN Tx header structure definition
- */
-typedef struct
-{
- uint32_t Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t IdType; /*!< Specifies the identifier type for the message that will be
- transmitted.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
- This parameter can be a value of @ref FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
- This parameter can be a value of @ref FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
- bit rate switching.
- This parameter can be a value of @ref FDCAN_bit_rate_switching */
-
- uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
- FD format.
- This parameter can be a value of @ref FDCAN_format */
-
- uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
- This parameter can be a value of @ref FDCAN_EFC */
-
- uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
- element for identification of Tx message status.
- This parameter must be a number between 0 and 0xFF */
-
-}FDCAN_TxHeaderTypeDef;
-
-/**
- * @brief FDCAN Rx header structure definition
- */
-typedef struct
-{
- uint32_t Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t IdType; /*!< Specifies the identifier type of the received message.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t RxFrameType; /*!< Specifies the the received message frame type.
- This parameter can be a value of @ref FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the received frame length.
- This parameter can be a value of @ref FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
- rate switching.
- This parameter can be a value of @ref FDCAN_bit_rate_switching */
-
- uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
- format.
- This parameter can be a value of @ref FDCAN_format */
-
- uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
- reception.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
- This parameter must be a number between:
- - 0 and 127, if IdType is FDCAN_STANDARD_ID
- - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
- Acceptance of non-matching frames may be enabled via
- HAL_FDCAN_ConfigGlobalFilter().
- This parameter can be 0 or 1 */
-
-}FDCAN_RxHeaderTypeDef;
-
-/**
- * @brief FDCAN Tx event FIFO structure definition
- */
-typedef struct
-{
- uint32_t Identifier; /*!< Specifies the identifier.
- This parameter must be a number between:
- - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
-
- uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
- This parameter can be a value of @ref FDCAN_frame_type */
-
- uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
- This parameter can be a value of @ref FDCAN_data_length_code */
-
- uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
- This parameter can be a value of @ref FDCAN_error_state_indicator */
-
- uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
- rate switching.
- This parameter can be a value of @ref FDCAN_bit_rate_switching */
-
- uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
- format.
- This parameter can be a value of @ref FDCAN_format */
-
- uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
- transmission.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
- for identification of Tx message status.
- This parameter must be a number between 0 and 0xFF */
-
- uint32_t EventType; /*!< Specifies the event type.
- This parameter can be a value of @ref FDCAN_event_type */
-
-}FDCAN_TxEventFifoTypeDef;
-
-/**
- * @brief FDCAN High Priority Message Status structure definition
- */
-typedef struct
-{
- uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
- This parameter can be:
- - 0 : Standard Filter List
- - 1 : Extended Filter List */
-
- uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
- This parameter can be a number between:
- - 0 and 127, if FilterList is 0 (Standard)
- - 0 and 63, if FilterList is 1 (Extended) */
-
- uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
- This parameter can be a value of @ref FDCAN_hp_msg_storage */
-
- uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
- message was stored.
- This parameter is valid only when MessageStorage is:
- FDCAN_HP_STORAGE_RXFIFO0
- or
- FDCAN_HP_STORAGE_RXFIFO1 */
-
-}FDCAN_HpMsgStatusTypeDef;
-
-/**
- * @brief FDCAN Protocol Status structure definition
- */
-typedef struct
-{
- uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
-
- uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
- frame with its BRS flag set.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
-
- uint32_t Activity; /*!< Specifies the FDCAN module communication state.
- This parameter can be a value of @ref FDCAN_communication_state */
-
- uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
- This parameter can be:
- - 0 : The FDCAN is in Error_Active state
- - 1 : The FDCAN is in Error_Passive state */
-
- uint32_t Warning; /*!< Specifies the FDCAN module warning status.
- This parameter can be:
- - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
- - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
-
- uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
- This parameter can be:
- - 0 : The FDCAN is not in Bus_Off state
- - 1 : The FDCAN is in Bus_Off state */
-
- uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
- This parameter can be:
- - 0 : Last received CAN FD message did not have its ESI flag set
- - 1 : Last received CAN FD message had its ESI flag set */
-
- uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
- This parameter can be:
- - 0 : Last received CAN FD message did not have its BRS flag set
- - 1 : Last received CAN FD message had its BRS flag set */
-
- uint32_t RxFDFflag; /*!< Specifies FDF flag of last received CAN FD message.
- This parameter can be:
- - 0 : Last received CAN FD message did not have its FDF flag set
- - 1 : Last received CAN FD message had its FDF flag set */
-
- uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
- This parameter can be:
- - 0 : No protocol exception event occurred since last read access
- - 1 : Protocol exception event occurred */
-
- uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
- This parameter can be a number between 0 and 127 */
-
-}FDCAN_ProtocolStatusTypeDef;
-
-/**
- * @brief FDCAN Error Counters structure definition
- */
-typedef struct
-{
- uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
- This parameter can be a number between 0 and 255 */
-
- uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
- This parameter can be a number between 0 and 127 */
-
- uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
- This parameter can be:
- - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
- - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
-
- uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
- This parameter can be a number between 0 and 127.
- This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
- or the RxErrorCnt to be incremented. The counter stops at 127; the next increment of
- TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
-
-}FDCAN_ErrorCountersTypeDef;
-
-/**
- * @brief FDCAN TT Init structure definition
- */
-typedef struct
-{
- uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode.
- This parameter can be a value of @ref FDCAN_operation_mode */
-
- uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation.
- This parameter can be a value of @ref FDCAN_TT_operation.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL0 */
-
- uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master.
- This parameter can be a value of @ref FDCAN_TT_time_master */
-
- uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
- numerator : TUR = (Numerator ± SDL) / Denominator.
- With : SDL = 2^(SyncDevLimit+5).
- This parameter must be a number between 0 and 7 */
-
- uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
- This parameter must be a number between 0 and 127 */
-
- uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization.
- This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL1 */
-
- uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after
- which the application has to serve the application watchdog.
- The application watchdog is incremented once each 256 NTUs.
- The application watchdog can be disabled by setting AppWdgLimit to 0.
- This parameter must be a number between 0 and 255.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL0 */
-
- uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering.
- This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL1 */
-
- uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration.
- This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL1 */
-
- uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity.
- This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
- This parameter is ignored if OperationMode is set to
- FDCAN_TT_COMMUNICATION_LEVEL0 */
-
- uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.
- This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */
-
- uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
- This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */
-
- uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs.
- This parameter must be a number between 1 and 16 */
-
- uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix.
- This is the sum of Tx_Triggers for exclusive, single arbitrating and
- merged arbitrating windows.
- This parameter must be a number between 0 and 4095 */
-
- uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator.
- It is adviced to set this parameter to the largest applicable value.
- This parameter must be a number between 0x10000 and 0x1FFFF */
-
- uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator.
- This parameter must be a number between 0x0001 and 0x3FFF */
-
- uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements.
- This parameter must be a number between 0 and 64 */
-
- uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger.
- This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
-
- uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger.
- This parameter can be a value of @ref FDCAN_TT_event_trig_selection */
-
-}FDCAN_TT_ConfigTypeDef;
-
-/**
- * @brief FDCAN Trigger structure definition
- */
-typedef struct
-{
- uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured.
- This parameter must be a number between 0 and 63 */
-
- uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active.
- This parameter must be a number between 0 and 0xFFFF */
-
- uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor.
- This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */
-
- uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active.
- This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
- This parameter must be a number between 0 and RepeatFactor */
-
- uint32_t TmEventInt; /*!< Enable or disable the internal time mark event.
- If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
- becomes active.
- This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */
-
- uint32_t TmEventExt; /*!< Enable or disable the external time mark event.
- If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
- trigger memory element becomes active.
- This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */
-
- uint32_t TriggerType; /*!< Specifies the trigger type.
- This parameter can be a value of @ref FDCAN_TT_Trigger_Type */
-
- uint32_t FilterType; /*!< Specifies the filter identifier type.
- This parameter can be a value of @ref FDCAN_id_type */
-
- uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
- This parameter can be a value of @ref FDCAN_Tx_location.
- This parameter is taken in consideration only if the trigger is configured for
- transmission. */
-
- uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid.
- This parameter is taken in consideration only if the trigger is configured for
- reception.
- This parameter must be a number between:
- - 0 and 127, if FilterType is FDCAN_STANDARD_ID
- - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */
-
-}FDCAN_TriggerTypeDef;
-
-/**
- * @brief FDCAN TT Operation Status structure definition
- */
-typedef struct
-{
- uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level.
- This parameter can be a value of @ref FDCAN_TT_error_level */
-
- uint32_t MasterState; /*!< Specifies the type of the TT master state.
- This parameter can be a value of @ref FDCAN_TT_master_state */
-
- uint32_t SyncState; /*!< Specifies the type of the TT synchronization state.
- This parameter can be a value of @ref FDCAN_TT_sync_state */
-
- uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase.
- This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
- This parameter can be:
- - 0 : Global time not valid
- - 1 : Global time in phase with Time Master */
-
- uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed.
- This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
- This parameter can be:
- - 0 : Local clock speed not synchronized to Time Master clock speed
- - 1 : Synchronization Deviation ≤ SDL */
-
- uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value.
- This parameter can be a number between 0 and 0xFF */
-
- uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
- This parameter can be:
- - 0 : No global time preset pending
- - 1 : Node waits for the global time preset to take effect */
-
- uint32_t GapFinished; /*!< Specifies whether a Gap is finished.
- This parameter can be:
- - 0 : Reset at the end of each reference message
- - 1 : Gap finished */
-
- uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master.
- This parameter can be a number between 0 and 0x7 */
-
- uint32_t GapStarted; /*!< Specifies whether a Gap is started.
- This parameter can be:
- - 0 : No Gap in schedule
- - 1 : Gap time after Basic Cycle has started */
-
- uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced.
- This parameter can be:
- - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
- - 1 : Reference message with Next_is_Gap = 1 received */
-
- uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State.
- This parameter can be:
- - 0 : Application Watchdog served in time
- - 1 : Failed to serve Application Watchdog in time */
-
- uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State.
- This parameter can be:
- - 0 : No external clock synchronization pending
- - 1 : Node waits for external clock synchronization to take effect */
-
- uint32_t PhaseLock; /*!< Specifies the Phase Lock State.
- This parameter can be:
- - 0 : Phase outside range
- - 1 : Phase inside range */
-
-}FDCAN_TTOperationStatusTypeDef;
-
-/**
- * @brief FDCAN Message RAM blocks
- */
-typedef struct
-{
- uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address.
- This parameter must be a 32-bit word address */
-
- uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM.
- This parameter must be a 32-bit word address */
-
-}FDCAN_MsgRamAddressTypeDef;
-
-/**
- * @brief FDCAN handle structure definition
- */
-typedef struct
-{
- FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
-
- TTCAN_TypeDef *ttcan; /*!< TT register base address */
-
- FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
-
- FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
-
- __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
-
- HAL_LockTypeDef Lock; /*!< FDCAN locking object */
-
- __IO uint32_t ErrorCode; /*!< FDCAN Error code */
-
-}FDCAN_HandleTypeDef;
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
- * @{
- */
-
-/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
- * @{
- */
-#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
-#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
-#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
-#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
-#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
-#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
-#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
-#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
-#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
-#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
-#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
-#define HAL_FDCAN_ERROR_RESEVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
-#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */
-#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
-#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */
-#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */
-#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */
-#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */
-#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */
-#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */
-#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_frame_format FDCAN Frame Format
- * @{
- */
-#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
-#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switshing */
-#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switshing */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
- * @{
- */
-#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
-#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
-#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
-#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
-#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
- * @{
- */
-#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
-#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
-#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
-#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
-#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
-#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
-#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
-#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
-#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
-#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
-#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
-#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
-#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
-#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
-#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
-#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
- * @{
- */
-#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */
-#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_calibration_state FDCAN Calibration State
- * @{
- */
-#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */
-#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */
-#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
- * @{
- */
-#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */
-#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
-#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
- * @{
- */
-#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */
-#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
-#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
-#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
-#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
-#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
-#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
-#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
- * @{
- */
-#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
-#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_id_type FDCAN ID Type
- * @{
- */
-#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
-#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_frame_type FDCAN Frame Type
- * @{
- */
-#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
-#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
- * @{
- */
-#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
-#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
-#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
-#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
-#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
-#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
-#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
-#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
-#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
-#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
-#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
-#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
-#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
-#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
-#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
-#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
- * @{
- */
-#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
-#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
- * @{
- */
-#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
-#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_format FDCAN format
- * @{
- */
-#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
-#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_EFC FDCAN Event FIFO control
- * @{
- */
-#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
-#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_filter_type FDCAN Filter Type
- * @{
- */
-#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
-#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
-#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
-#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
- * @{
- */
-#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
-#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
-#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
-#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
-#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
-#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
-#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
-#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Tx_location FDCAN Tx Location
- * @{
- */
-#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
-#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
-#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
-#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */
-#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */
-#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */
-#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */
-#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */
-#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */
-#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */
-#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
-#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
-#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
-#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
-#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
-#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
-#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
-#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
-#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
-#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
-#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
-#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
-#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
-#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
-#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
-#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
-#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
-#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
-#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
-#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
-#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
-#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_location FDCAN Rx Location
- * @{
- */
-#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
-#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
-#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */
-#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */
-#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */
-#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */
-#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */
-#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */
-#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */
-#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */
-#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */
-#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */
-#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
-#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
-#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
-#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
-#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
-#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
-#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
-#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
-#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
-#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
-#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
-#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
-#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
-#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
-#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
-#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
-#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
-#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
-#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
-#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
-#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
-#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
-#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
-#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
-#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
-#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
-#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
-#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
-#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
-#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
-#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
-#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
-#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
-#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
-#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
-#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
-#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
-#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
-#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
-#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
-#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
-#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
-#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
-#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
-#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
-#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
-#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
-#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
-#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
-#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
-#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
-#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
-#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
-#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_event_type FDCAN Event Type
- * @{
- */
-#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
-#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
- * @{
- */
-#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
-#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
-#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
-#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
- * @{
- */
-#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
-#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
-#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
-#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
-#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
-#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
-#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
-#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_communication_state FDCAN communication state
- * @{
- */
-#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
-#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
-#define FDCAN_COM_STATE_RX ((uint32_t)0x00000016U) /*!< Node is operating as receiver */
-#define FDCAN_COM_STATE_TX ((uint32_t)0x00000024U) /*!< Node is operating as transmitter */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
- * @{
- */
-#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
-#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */
-#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
- * @{
- */
-#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
-#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
- * @{
- */
-#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
-#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
-#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
- * @{
- */
-#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
-#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timestamp FDCAN timestamp
- * @{
- */
-#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
-#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
- * @{
- */
-#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
-#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
-#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
-#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
-#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
-#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
-#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
-#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
-#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
-#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
-#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
-#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
-#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
-#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
-#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
-#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
- * @{
- */
-#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
-#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
-#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
-#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
- * @{
- */
-#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */
-#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
- * @{
- */
-#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */
-#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */
-#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */
-#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */
-#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
-#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
-#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
- * @{
- */
-#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */
-#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */
-#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */
-#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */
-#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */
-#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */
-#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */
-#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */
-#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */
-#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */
-#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
- * @{
- */
-#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
-#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
- * @{
- */
-#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
-#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
- * @{
- */
-#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
-#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
-#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_operation FDCAN TT Operation
- * @{
- */
-#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */
-#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
- * @{
- */
-#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */
-#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
- * @{
- */
-#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */
-#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
- * @{
- */
-#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */
-#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
- * @{
- */
-#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */
-#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
- * @{
- */
-#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */
-#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
- * @{
- */
-#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
-#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
- * @{
- */
-#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */
-#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
-#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
- * @{
- */
-#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */
-#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */
-#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */
-#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
- * @{
- */
-#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */
-#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */
-#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */
-#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
- * @{
- */
-#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */
-#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */
-#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */
-#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
- * @{
- */
-#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */
-#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
- * @{
- */
-#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */
-#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */
-#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */
-#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
- * @{
- */
-#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */
-#define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */
-#define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */
-#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
- * @{
- */
-#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
-#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */
-#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */
-#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
- * @{
- */
-#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */
-#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
-#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */
-#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */
-/**
- * @}
- */
-
-/** @defgroup Interrupt_Masks Interrupt masks
- * @{
- */
-#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
-#define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_flags FDCAN Flags
- * @{
- */
-#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
-#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
-#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
-#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
-#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */
-#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
-#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
-#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */
-#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
-#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
-#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
-#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */
-#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
-#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
-#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
-#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */
-#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
-#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
-#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
-#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
-#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
-#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
-#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
-#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
-#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
-#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
-#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
-#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
-#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */
-#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Interrupts FDCAN Interrupts
- * @{
- */
-
-/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
- * @{
- */
-#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
-#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
-#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
- * @{
- */
-#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
-#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
- * @{
- */
-#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
-#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
- * @{
- */
-#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */
-#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
- * @{
- */
-#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
-#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
-#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
-#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
- * @{
- */
-#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
-#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
-#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
-#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
- * @{
- */
-#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
-#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
-#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
-#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
- * @{
- */
-#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
-#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
-#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
-#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
-#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
-#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
-#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
-#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
-#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTflags FDCAN TT Flags
- * @{
- */
-#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */
-#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */
-#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */
-#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */
-#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */
-#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
-#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */
-#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */
-#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */
-#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */
-#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */
-#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */
-#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */
-#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */
-#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */
-#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */
-#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */
-#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */
-#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
- * @{
- */
-
-/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
- * @{
- */
-#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */
-#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */
-#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
-#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
- * @{
- */
-#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */
-#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
- * @{
- */
-#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
- * @{
- */
-#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */
-#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
- * @{
- */
-#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */
-#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */
-#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */
-#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */
-#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */
-#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
-/**
- * @}
- */
-
-/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
- * @{
- */
-#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
-#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */
-#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */
-#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
- * @{
- */
-
-/** @brief Reset FDCAN handle state.
- * @param __HANDLE__: FDCAN handle.
- * @retval None
- */
-#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
-
-/**
- * @brief Enable the specified FDCAN interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN interrupt.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- do{ \
- (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
- FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
- }while(0)
-
-
-/**
- * @brief Disable the specified FDCAN interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN interrupt.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- do{ \
- ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
- FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
- }while(0)
-
-/**
- * @brief Check whether the specified FDCAN interrupt is set or not.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN interrupt.
- * This parameter can be one of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
-
-/**
- * @brief Clear the specified FDCAN interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: specifies the interrupts to clear.
- * This parameter can be any combination of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
-do{ \
- ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
- FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
- }while(0)
-
-/**
- * @brief Check whether the specified FDCAN flag is set or not.
- * @param __HANDLE__: FDCAN handle.
- * @param __FLAG__: FDCAN flag.
- * This parameter can be one of @arg FDCAN_flags
- * @retval None
- */
-#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
-
-/**
- * @brief Clear the specified FDCAN flags.
- * @param __HANDLE__: FDCAN handle.
- * @param __FLAG__: specifies the flags to clear.
- * This parameter can be any combination of @arg FDCAN_flags
- * @retval None
- */
-#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-do{ \
- ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
- FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \
- }while(0)
-
-/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: specifies the FDCAN interrupt source to check.
- * This parameter can be a value of @arg FDCAN_Interrupts
- * @retval None
- */
-#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
-
-/**
- * @brief Enable the specified FDCAN TT interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN TT interrupt.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts
- * @retval None
- */
-#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified FDCAN TT interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN TT interrupt.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts
- * @retval None
- */
-#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified FDCAN TT interrupt is set or not.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: FDCAN TT interrupt.
- * This parameter can be one of @arg FDCAN_TTInterrupts
- * @retval None
- */
-#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
-
-/**
- * @brief Clear the specified FDCAN TT interrupts.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: specifies the TT interrupts to clear.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts
- * @retval None
- */
-#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified FDCAN TT flag is set or not.
- * @param __HANDLE__: FDCAN handle.
- * @param __FLAG__: FDCAN TT flag.
- * This parameter can be one of @arg FDCAN_TTflags
- * @retval None
- */
-#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
-
-/**
- * @brief Clear the specified FDCAN TT flags.
- * @param __HANDLE__: FDCAN handle.
- * @param __FLAG__: specifies the TT flags to clear.
- * This parameter can be any combination of @arg FDCAN_TTflags
- * @retval None
- */
-#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
-
-/** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled.
- * @param __HANDLE__: FDCAN handle.
- * @param __INTERRUPT__: specifies the FDCAN TT interrupt source to check.
- * This parameter can be a value of @arg FDCAN_TTInterrupts
- * @retval None
- */
-#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FDCAN_Exported_Functions
- * @{
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef* hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef* hfdcan);
-void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan);
-void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group2
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef* hfdcan, FDCAN_ClkCalUnitTypeDef* sCcuConfig);
-uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan);
-uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef* hfdcan, uint32_t Counter);
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef* hfdcan, FDCAN_FilterTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
-HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
-HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
-HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
-HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
-HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
-HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
-HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
-HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group3
- * @{
- */
-/* Control functions **********************************************************/
-HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
-HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
-uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group4
- * @{
- */
-/* TT Configuration and control functions**************************************/
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef* hfdcan, FDCAN_TriggerTypeDef* sTriggerConfig);
-HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef* hfdcan, uint32_t TimePreset);
-HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef* hfdcan, uint32_t NewTURNumerator);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef* hfdcan, uint32_t Source, uint32_t Polarity);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef* hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group5
- * @{
- */
-/* Interrupts management ******************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
-HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
-HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs);
-HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
-void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef* hfdcan);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group6
- * @{
- */
-/* Callback functions *********************************************************/
-void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
-void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
-void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
-void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
-void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
-void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
-void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
-void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
-void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
-void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
-void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Exported_Functions_Group7
- * @{
- */
-/* Peripheral State functions *************************************************/
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef* hfdcan);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Types FDCAN Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
- * @{
- */
-#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
- ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
- ((FORMAT) == FDCAN_FRAME_FD_BRS ))
-#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
- ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
- ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
- ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
- ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
-#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
- ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
- ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
- ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
- ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
- ((CKDIV) == FDCAN_CLOCK_DIV10) || \
- ((CKDIV) == FDCAN_CLOCK_DIV12) || \
- ((CKDIV) == FDCAN_CLOCK_DIV14) || \
- ((CKDIV) == FDCAN_CLOCK_DIV16) || \
- ((CKDIV) == FDCAN_CLOCK_DIV18) || \
- ((CKDIV) == FDCAN_CLOCK_DIV20) || \
- ((CKDIV) == FDCAN_CLOCK_DIV22) || \
- ((CKDIV) == FDCAN_CLOCK_DIV24) || \
- ((CKDIV) == FDCAN_CLOCK_DIV26) || \
- ((CKDIV) == FDCAN_CLOCK_DIV28) || \
- ((CKDIV) == FDCAN_CLOCK_DIV30))
-#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 512))
-#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 128))
-#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 2) && ((TSEG1) <= 256))
-#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 2) && ((TSEG2) <= 128))
-#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 32))
-#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1) && ((SJW) <= 16))
-#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1) && ((TSEG1) <= 32))
-#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1) && ((TSEG2) <= 16))
-#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
-#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
-#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
- ((SIZE) == FDCAN_DATA_BYTES_12) || \
- ((SIZE) == FDCAN_DATA_BYTES_16) || \
- ((SIZE) == FDCAN_DATA_BYTES_20) || \
- ((SIZE) == FDCAN_DATA_BYTES_24) || \
- ((SIZE) == FDCAN_DATA_BYTES_32) || \
- ((SIZE) == FDCAN_DATA_BYTES_48) || \
- ((SIZE) == FDCAN_DATA_BYTES_64))
-#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
- ((MODE) == FDCAN_TX_QUEUE_OPERATION))
-#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
- ((ID_TYPE) == FDCAN_EXTENDED_ID))
-#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
- ((CONFIG) == FDCAN_FILTER_REJECT ) || \
- ((CONFIG) == FDCAN_FILTER_HP ) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
- ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER ))
-#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
- ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
- ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
- ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
- ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
- ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
- ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
- ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
- ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
- ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
- ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
- ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
- ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
- ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
- ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
- ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
-#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
- ((FIFO) == FDCAN_RX_FIFO1))
-#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
- ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
-#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
- ((TYPE) == FDCAN_FILTER_DUAL ) || \
- ((TYPE) == FDCAN_FILTER_MASK ))
-#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
- ((TYPE) == FDCAN_FILTER_DUAL ) || \
- ((TYPE) == FDCAN_FILTER_MASK ) || \
- ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
-#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
- ((TYPE) == FDCAN_REMOTE_FRAME))
-#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
- ((DLC) == FDCAN_DLC_BYTES_1 ) || \
- ((DLC) == FDCAN_DLC_BYTES_2 ) || \
- ((DLC) == FDCAN_DLC_BYTES_3 ) || \
- ((DLC) == FDCAN_DLC_BYTES_4 ) || \
- ((DLC) == FDCAN_DLC_BYTES_5 ) || \
- ((DLC) == FDCAN_DLC_BYTES_6 ) || \
- ((DLC) == FDCAN_DLC_BYTES_7 ) || \
- ((DLC) == FDCAN_DLC_BYTES_8 ) || \
- ((DLC) == FDCAN_DLC_BYTES_12) || \
- ((DLC) == FDCAN_DLC_BYTES_16) || \
- ((DLC) == FDCAN_DLC_BYTES_20) || \
- ((DLC) == FDCAN_DLC_BYTES_24) || \
- ((DLC) == FDCAN_DLC_BYTES_32) || \
- ((DLC) == FDCAN_DLC_BYTES_48) || \
- ((DLC) == FDCAN_DLC_BYTES_64))
-#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
- ((ESI) == FDCAN_ESI_PASSIVE))
-#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
- ((BRS) == FDCAN_BRS_ON ))
-#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
- ((FDF) == FDCAN_FD_CAN ))
-#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
- ((EFC) == FDCAN_STORE_TX_EVENTS))
-#define IS_FDCAN_IT(IT) (((IT) & 0xC0300000U) == RESET)
-#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == RESET)
-#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
- ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \
- ((FIFO) == FDCAN_CFG_RX_FIFO1 ))
-#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
- ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
- ((DESTINATION) == FDCAN_REJECT ))
-#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
- ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
-#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
- ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
-#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
- ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
-#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
- ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
- ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
- ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
-#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
- ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
-#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
- ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
-#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
- ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
-#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \
- ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \
- ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \
- ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
- ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
- ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \
- ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \
- ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \
- ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \
- ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \
- ((TYPE) == FDCAN_TT_END_OF_LIST ))
-#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
- ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
-#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
- ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
-#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
- ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
- ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
-#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \
- ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
-#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \
- ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
-#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
- ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
-#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
- ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
-#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
- ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
-#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
- ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
-#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
- ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
-#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \
- ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
- ((SYNC) == FDCAN_TT_SYNC_MATRIX_START ))
-#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1) && ((NTU) <= 16))
-#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000) && ((NUMERATOR) <= 0x1FFFF))
-#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001) && ((DENOMINATOR) <= 0x3FFF))
-#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4 * (DC)))
-#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8 * (DC)))
-#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
- ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
- ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
- ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
-#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
- ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
- ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
- ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
-#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFF) && ((TIME) != 0x8000))
-#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \
- ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
- ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
- ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
-#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_DISABLED ) || \
- ((POLARITY) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
-#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
- ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
- ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
- ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
- * @{
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_FDCAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
deleted file mode 100644
index 6d4e06d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
+++ /dev/null
@@ -1,665 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_FLASH_H
-#define __STM32H7xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0U,
- FLASH_PROC_SECTERASE_BANK1,
- FLASH_PROC_MASSERASE_BANK1,
- FLASH_PROC_PROGRAM_BANK1,
- FLASH_PROC_SECTERASE_BANK2,
- FLASH_PROC_MASSERASE_BANK2,
- FLASH_PROC_PROGRAM_BANK2,
- FLASH_PROC_ALLBANK_MASSERASE
-} FLASH_ProcedureTypeDef;
-
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-
- __IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */
-
- __IO uint8_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */
-
- __IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */
-
- __IO uint32_t Address; /*!< Internal variable to save address selected for program */
-
- HAL_LockTypeDef Lock; /*!< FLASH locking object */
-
- __IO uint32_t ErrorCode; /*!< FLASH error code */
-
-}FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error_Code FLASH Error Code
- * @brief FLASH Error Code
- * @{
- */
-
-#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-
-#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000001U) /*!< Write Protection Error */
-#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U) /*!< Program Sequence Error */
-#define HAL_FLASH_ERROR_STRB ((uint32_t)0x00000004U) /*!< Strobe Error */
-#define HAL_FLASH_ERROR_INC ((uint32_t)0x00000008U) /*!< Inconsistency Error */
-#define HAL_FLASH_ERROR_OPE ((uint32_t)0x00000010U) /*!< Operation Error */
-#define HAL_FLASH_ERROR_RDP ((uint32_t)0x00000020U) /*!< Read Protection Error */
-#define HAL_FLASH_ERROR_RDS ((uint32_t)0x00000040U) /*!< Read Secured Error */
-#define HAL_FLASH_ERROR_SNECC ((uint32_t)0x00000080U) /*!< Single Detection ECC */
-#define HAL_FLASH_ERROR_DBECC ((uint32_t)0x00000100U) /*!< Double Detection ECC */
-
-#define HAL_FLASH_ERROR_WRP_BANK1 ((uint32_t)0x00000001U) /*!< Write Protection Error on Bank 1 */
-#define HAL_FLASH_ERROR_PGS_BANK1 ((uint32_t)0x00000002U) /*!< Program Sequence Error on Bank 1 */
-#define HAL_FLASH_ERROR_STRB_BANK1 ((uint32_t)0x00000004U) /*!< Strobe Error on Bank 1 */
-#define HAL_FLASH_ERROR_INC_BANK1 ((uint32_t)0x00000008U) /*!< Inconsistency Error on Bank 1 */
-#define HAL_FLASH_ERROR_OPE_BANK1 ((uint32_t)0x00000010U) /*!< Operation Error on Bank 1 */
-#define HAL_FLASH_ERROR_RDP_BANK1 ((uint32_t)0x00000020U) /*!< Read Protection Error on Bank 1 */
-#define HAL_FLASH_ERROR_RDS_BANK1 ((uint32_t)0x00000040U) /*!< Read Secured Error on Bank 1 */
-#define HAL_FLASH_ERROR_SNECC_BANK1 ((uint32_t)0x00000080U) /*!< Single Detection ECC on Bank 1 */
-#define HAL_FLASH_ERROR_DBECC_BANK1 ((uint32_t)0x00000100U) /*!< Double Detection ECC on Bank 1 */
-
-#define HAL_FLASH_ERROR_WRP_BANK2 ((uint32_t)0x00001000U) /*!< Write Protection Error on Bank 2 */
-#define HAL_FLASH_ERROR_PGS_BANK2 ((uint32_t)0x00002000U) /*!< Program Sequence Error on Bank 2 */
-#define HAL_FLASH_ERROR_STRB_BANK2 ((uint32_t)0x00004000U) /*!< Strobe Error on Bank 2 */
-#define HAL_FLASH_ERROR_INC_BANK2 ((uint32_t)0x00008000U) /*!< Inconsistency Error on Bank 2 */
-#define HAL_FLASH_ERROR_OPE_BANK2 ((uint32_t)0x00010000U) /*!< Operation Error on Bank 2 */
-#define HAL_FLASH_ERROR_RDP_BANK2 ((uint32_t)0x00020000U) /*!< Read Protection Error on Bank 2 */
-#define HAL_FLASH_ERROR_RDS_BANK2 ((uint32_t)0x00040000U) /*!< Read Secured Error on Bank 2 */
-#define HAL_FLASH_ERROR_SNECC_BANK2 ((uint32_t)0x00080000U) /*!< Single Detection ECC on Bank 2 */
-#define HAL_FLASH_ERROR_DBECC_BANK2 ((uint32_t)0x00100000U) /*!< Double Detection ECC on Bank 2 */
-
-#define HAL_FLASH_ERROR_OB_CHANGE ((uint32_t)0x01000000U) /*!< Option Byte Change Error */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
- * @{
- */
-#define FLASH_TYPEPROGRAM_FLASHWORD ((uint32_t)0x03U) /*!< Program a flash word (256-bit) at a specified address */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flag_definition FLASH Flag definition
- * @brief Flag definition
- * @{
- */
-
-
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */
-#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */
-#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */
-#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */
-#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */
-#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */
-#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */
-#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */
-#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */
-#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */
-#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */
-#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */
-
-
-#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */
-#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */
-#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */
-#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */
-#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */
-#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */
-#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */
-#define FLASH_FLAG_STRBER_BANK1R FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */
-#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */
-#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */
-#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */
-#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */
-#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */
-
-
-#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
- FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | \
- FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \
- FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCE_BANK1RR | \
- FLASH_FLAG_DBECCE_BANK1RR)
-
-#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \
- FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \
- FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \
- FLASH_FLAG_ALL_ERRORS_BANK1)
-
-#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */
-#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */
-#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */
-#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */
-#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */
-#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */
-#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */
-#define FLASH_FLAG_STRBER_BANK2R (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */
-#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */
-#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */
-#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */
-#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */
-#define FLASH_FLAG_SNECCE_BANK2RR (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */
-#define FLASH_FLAG_DBECCE_BANK2RR (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */
-#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */
-
-
-#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
- FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 | \
- FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \
- FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCE_BANK2RR | \
- FLASH_FLAG_DBECCE_BANK2RR)
-
-#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \
- FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \
- FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \
- FLASH_FLAG_ALL_ERRORS_BANK2)
-
-
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
- * @brief FLASH Interrupt definition
- * @{
- */
-
-#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */
-#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */
-#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */
-#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */
-#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */
-#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */
-#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */
-#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */
-#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */
-#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */
-#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */
-
-#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
- FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
- FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \
- FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \
- FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
- FLASH_CR_CRCENDIE )
-
-#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */
-#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */
-#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */
-#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */
-#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */
-#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */
-#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */
-#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */
-#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */
-#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */
-#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */
-
-
-#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK1 | \
- FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK1 | \
- FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK1 | \
- FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK1 | \
- FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
- FLASH_CR_CRCENDIE )
-/**
- * @}
- */
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
- * @{
- */
-#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
-#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
-#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
-#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
-#define CR_PSIZE_MASK ((uint32_t)0xFFFFFFCFU)
-/**
- * @}
- */
-
-
-/** @defgroup FLASH_Keys FLASH Keys
- * @{
- */
-#define FLASH_KEY1 ((uint32_t)0x45670123U)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
-#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
-#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
-/**
- * @}
- */
-
-/** @defgroup FLASH_Sectors FLASH Sectors
- * @{
- */
-#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
-#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
-#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
-#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
-#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
-#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
-#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
-#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @{
- */
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__: FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @retval none
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH Latency
- * The value of this parameter depend on device used within the same series
- */
-#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ : FLASH interrupt
- * In case of Bank 1 This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
- * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
- * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
- * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
- * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
- * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
- * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
- * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
- * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
- * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
- * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
-
- * In case of Bank 2 This parameter can be any combination of the following values: *
- * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
- * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
- * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
- * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
- * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
- * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
- * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
- * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
- * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
- * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
- * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
- * @retval none
- */
-
-#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
-
-#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))
-
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
- __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
- __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
-
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ : FLASH interrupt
- * In case of Bank 1 This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
- * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
- * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
- * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
- * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
- * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
- * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
- * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
- * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
- * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
- * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
-
- * In case of Bank 2 This parameter can be any combination of the following values: *
- * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
- * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
- * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
- * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
- * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
- * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
- * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
- * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
- * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
- * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
- * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
-
- * @retval none
- */
-
-#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
-
-#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))
-
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
- __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
- __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
-
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param __FLAG__: specifies the FLASH flag to check.
- * In case of Bank 1 This parameter can be any combination of the following values :
- * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
- * @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
- * @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
- * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
- * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
- * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
- * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
- * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
- * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
- * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
- * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
- * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
- * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
- * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
- * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
- *
- * In case of Bank 2 This parameter can be any combination of the following values :
- * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
- * @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
- * @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
- * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
- * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
- * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
- * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
- * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
- * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
- * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
- * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
- * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
- * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
- * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
- * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
-
-#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))
-
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
- __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
-
-
-/**
- * @brief Clear the specified FLASH flag.
- * @param __FLAG__: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
- * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
- * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
- * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
- * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
- * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
- * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
- * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
- * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
- * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
- * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
- *
- * In case of Bank 2 This parameter can be any combination of the following values :
- * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
- * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
- * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
- * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
- * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
- * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
- * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
- * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
- * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
- * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
- * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
- * @retval none
- */
-
-#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
-
-#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))
-
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
- __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
-
-/**
- * @}
- */
-
-/* Include FLASH HAL Extension module */
-#include "stm32h7xx_hal_flash_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-/* Program operation functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-uint32_t HAL_FLASH_GetError(void);
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
-HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
- * @{
- */
-#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
-/**
- * @}
- */
-/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
- * @{
- */
-
-#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
-
-#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
-
-/**
- * @}
- */
-
-#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
-
-#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
-
-/** @defgroup FLASH_Address FLASH Address
- * @{
- */
-
-#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))
-#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
-
-#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
-
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
deleted file mode 100644
index 7ff35c4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32H7xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_FLASH_EX_H
-#define __STM32H7xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< Mass erase or sector Erase.
- This parameter can be a value of @ref FLASHEx_Type_Erase */
-
- uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
- This parameter must be a value of @ref FLASH_Sectors */
-
- uint32_t NbSectors; /*!< Number of sectors to be erased.
- This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
- uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
- This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
-} FLASH_EraseInitTypeDef;
-
-
-/**
- * @brief FLASH Option Bytes Program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< Option byte to be configured.
- This parameter can be a value of @ref FLASHEx_Option_Type */
-
- uint32_t WRPState; /*!< Write protection activation or deactivation.
- This parameter can be a value of @ref FLASHEx_WRP_State */
-
- uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
- The value of this parameter depend on device used within the same series */
-
- uint32_t RDPLevel; /*!< Set the read protection level.
- This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
- uint32_t BORLevel; /*!< Set the BOR Level.
- This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
-
- uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
- This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
-
- uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
- IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */
- uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
- This parameter must be a value of @ref FLASHEx_Banks */
- uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not
- when RDP level decreased from Level 1 to Level 0 or during a mass erase.
- This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
-
- uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between begin and end of a bank */
-
- uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
- This parameter must be a value between PCROP Start address and end of a bank */
-
- uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
- or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
-
- uint32_t BootAddr0; /*!< Boot Address 0.
- This parameter must be a value between begin and end of a bank */
-
- uint32_t BootAddr1; /*!< Boot Address 1.
- This parameter must be a value between begin and end of a bank */
-
- uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
- when RDP level decreased from Level 1 to Level 0 or during a mass erase.
- This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
-
- uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
- This parameter must be a value between begin and end of bank1 */
-
- uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address .
- This parameter must be a value between Start address and end of a bank1 */
-
-} FLASH_OBProgramInitTypeDef;
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
- * @{
- */
-#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
- * @{
- */
-#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Flash program/erase by 8 bits */
-#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)FLASH_CR_PSIZE_0) /*!< Flash program/erase by 16 bits */
-#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)FLASH_CR_PSIZE_1) /*!< Flash program/erase by 32 bits */
-#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)FLASH_CR_PSIZE) /*!< Flash program/erase by 64 bits */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_WRP_State FLASH WRP State
- * @{
- */
-#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Type FLASH Option Type
- * @{
- */
-#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
-#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
-#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
-#define OPTIONBYTE_PCROP ((uint32_t)0x08U) /*!< PCROP option byte configuration */
-#define OPTIONBYTE_BOR ((uint32_t)0x10U) /*!< BOR option byte configuration */
-#define OPTIONBYTE_SECURE_AREA ((uint32_t)0x20U) /*!< secure area option byte configuration */
-#define OPTIONBYTE_BOOTADD ((uint32_t)0x40U) /*!< BOOT ADD option byte configuration */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
- * @{
- */
-#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00U)
-#define OB_RDP_LEVEL_1 ((uint32_t)0x5500U)
-#define OB_RDP_LEVEL_2 ((uint32_t)0xCC00U) /*!< Warning: When enabling read protection level 2
- it s no more possible to go back to level 1 or 0 */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
- * @{
- */
-#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
-#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
- * @{
- */
-#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
- * @{
- */
-#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
- * @{
- */
-#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
-#define OB_IWDG_STOP_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP) /*!< IWDG counter active in STOP mode */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
- * @{
- */
-#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
-#define OB_IWDG_STDBY_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY) /*!< IWDG counter active in STANDBY mode */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
- * @{
- */
-#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-/**
- * @}
- */
-
-
-
-/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
- * @{
- */
-#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
-#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
-#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
-#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
-#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
-#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
-#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Latency FLASH Latency
- * @{
- */
-#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
-#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
-#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
-#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
-#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
-#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_Banks FLASH Banks
- * @{
- */
-#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
-#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
-#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
- * @{
- */
-#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000U) /*!< PCROP area is not erased when the RDP level
- is decreased from Level 1 to Level 0 or during a mass erase */
-#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PRAR_DMEP) /*!< PCROP area is erased when the RDP level is
- decreased from Level 1 to Level 0 (full mass erase) */
-
-/**
- * @}
- */
-
-
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
- * @{
- */
-#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U) /*!< Write protection of Sector0 */
-#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U) /*!< Write protection of Sector1 */
-#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U) /*!< Write protection of Sector2 */
-#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U) /*!< Write protection of Sector3 */
-#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U) /*!< Write protection of Sector4 */
-#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020U) /*!< Write protection of Sector5 */
-#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040U) /*!< Write protection of Sector6 */
-#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080U) /*!< Write protection of Sector7 */
-#define OB_WRP_SECTOR_All ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY
- * @{
- */
-#define OB_SECURITY_DISABLE ((uint32_t)0x00000U) /*!< security enabled */
-#define OB_SECURITY_ENABLE ((uint32_t)FLASH_OPTSR_SECURITY) /*!< security disabled */
-
-/**
- * @}
- */
-
-
-
-/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
- * @{
- */
-#define OB_IWDG1_SW ((uint32_t)FLASH_OPTSR_IWDG1_SW) /*!< Hardware independent watchdog 1 */
-#define OB_IWDG1_HW ((uint32_t)0x00000U) /*!< Software independent watchdog 1 */
-/**
- * @}
- */
-/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
- * @{
- */
-#define OB_STOP_RST_D1 ((uint32_t)0x0000U) /*!< Reset generated when entering the D1 to stop mode */
-#define OB_STOP_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STOP_D1) /*!< No reset generated when entering the D1 to stop mode */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1
- * @{
- */
-#define OB_STDBY_RST_D1 ((uint32_t)0x0000U) /*!< Reset generated when entering the D1 to standby mode */
-#define OB_STDBY_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STBY_D1) /*!< No reset generated when entering the D1 to standby mode */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
- * @{
- */
-#define OB_SWAP_BANK_DISABLE ((uint32_t)0x00000U) /*!< Bank swap disabled */
-#define OB_SWAP_BANK_ENABLE ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT) /*!< Bank swap enabled */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
- * @{
- */
-#define OB_IOHSLV_DISABLE ((uint32_t)0x00000000U) /*!< IOHSLV disabled */
-#define OB_IOHSLV_ENABLE ((uint32_t)FLASH_OPTSR_IO_HSLV) /*!< IOHSLV enabled */
-
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
- * @{
- */
-#define OB_BOOT_ADD0 ((uint32_t)0x01U) /*!< Select Boot Address 0 */
-#define OB_BOOT_ADD1 ((uint32_t)0x02U) /*!< Select Boot Address 1 */
-#define OB_BOOT_ADD_BOTH ((uint32_t)0x03U) /*!< Select Boot Address 0 and 1 */
-
-
-/**
- * @}
- */
-
- /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
- * @{
- */
-#define OB_USER_NRST_STOP_D1 ((uint32_t)0x0001U) /*!< Reset when entering Stop mode selection*/
-#define OB_USER_NRST_STDBY_D1 ((uint32_t)0x0002U) /*!< Reset when entering standby mode selection*/
-#define OB_USER_IWDG_STOP ((uint32_t)0x0004U) /*!< Independent watchdog counter freeze in stop mode */
-#define OB_USER_IWDG_STDBY ((uint32_t)0x0008U) /*!< Independent watchdog counter freeze in standby mode */
-#define OB_USER_ST_RAM_SIZE ((uint32_t)0x0010U) /*!< dedicated DTCM Ram size selection */
-#define OB_USER_SECURITY ((uint32_t)0x0020U) /*!< security selection */
-#define OB_USER_SWAP_BANK ((uint32_t)0x0100U) /*!< Bank swap selection */
-#define OB_USER_IOHSLV ((uint32_t)0x0200U) /*!< IO HSLV selection */
-#define OB_USER_IWDG1_SW ((uint32_t)0x0400U) /*!< Independent watchdog selection */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP
- * @{
- */
-#define OB_SECURE_RDP_NOT_ERASE ((uint32_t)0x00000000U) /*!< Secure area is not erased when the RDP level
- is decreased from Level 1 to Level 0 or during a mass erase*/
-#define OB_SECURE_RDP_ERASE ((uint32_t)FLASH_SCAR_DMES) /*!< Secure area is erased when the RDP level is
- decreased from Level 1 to Level 0 (full mass erase) */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @{
- */
-/**
- * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
- * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
- * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
- * @retval The FLASH Boot Base Adress
- */
-#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
- /**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-/* Extension Program operation functions *************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
-HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
-HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
-HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
- * @{
- */
-
-/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
- ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_4))
-
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
- ((VALUE) == OB_WRPSTATE_ENABLE))
-#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OB_USER_IWDG1_SW | OB_USER_NRST_STDBY_D1 | OB_USER_NRST_STOP_D1 |\
- OB_USER_IWDG_STOP| OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK |\
- OB_USER_ST_RAM_SIZE | OB_USER_SECURITY))
-
-
-#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
-
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1) ||\
- ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
-
-#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
-
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || \
- ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || \
- ((LATENCY) == FLASH_LATENCY_7))
-
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
- (((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \
- (((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))
-
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
-
-#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
- ((CONFIG) == OB_PCROP_RDP_ERASE))
-
-#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
- ((CONFIG) == OB_SECURE_RDP_ERASE))
-
-#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
-
-#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
-
-#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
-#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
-
-#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
-
-#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
-
-#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
-
-#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) /*User can only move the security bit from 0 to 1*/
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))
-
-#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
- ((VALUE) == OB_BOOT_ADD1) || \
- ((VALUE) == OB_BOOT_ADD_BOTH))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
- * @{
- */
-void FLASH_Erase_Sector(uint32_t Sector, uint32_t Bank, uint32_t VoltageRange);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
deleted file mode 100644
index c03ea59..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_GPIO_H
-#define __STM32H7xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode_define */
-
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
- This parameter can be a value of @ref GPIO_pull_define */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed_define */
-
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
- This parameter can be a value of @ref GPIO_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- GPIO_PIN_RESET = 0,
- GPIO_PIN_SET
-}GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define GPIO pins define
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
-
-#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode_define GPIO mode define
- * @brief GPIO Configuration Mode
- * Elements values convention: 0xX0yz00YZ
- * - X : GPIO mode or EXTI Mode
- * - y : External IT or Event trigger detection
- * - z : IO configuration on External IT or Event
- * - Y : Output type (Push Pull or Open Drain)
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)
- * @{
- */
-#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING ((uint32_t)0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING ((uint32_t)0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING ((uint32_t)0x11120000U) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING ((uint32_t)0x11220000U) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed_define GPIO speed define
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
-#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
-#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
-#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
-/**
- * @}
- */
-
- /** @defgroup GPIO_pull_define GPIO pull define
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
-#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__: specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param __EXTI_LINE__: specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extension module */
-#include "stm32h7xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
deleted file mode 100644
index 30cad7c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_GPIO_EX_H
-#define __STM32H7xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIOEx GPIOEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
- * @{
- */
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
-#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
-#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
-#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
-#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
-#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
-#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
-#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
-#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
-#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
-#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
-#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
-#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
-#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
-#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
-#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
-
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
-#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
-#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
-#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
-#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
-#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
-#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
-#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
-#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
-#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
-#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
-#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
-#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
-#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
-#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
-#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
-#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
-#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
-#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
-#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
-#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
-#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
-#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
-#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
-#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
-#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
-#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
-#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
-#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
-#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
-#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
-#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
-#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
-#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
-#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
-#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
-#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
-#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
-#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
-#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
-#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
-#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
-#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
- * @{
- */
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
- * @{
- */
-
-/**
- * @brief GPIO pin available on the platform
- */
-/* Defines the available pins per GPIOs */
-#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
- GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
- * @{
- */
-/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
- * @{
- */
-#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :\
- ((__GPIOx__) == (GPIOG))? 6U :\
- ((__GPIOx__) == (GPIOH))? 7U :\
- ((__GPIOx__) == (GPIOI))? 8U :\
- ((__GPIOx__) == (GPIOJ))? 9U : 10U)
-/**
- * @}
- */
-
-#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
- ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
- (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h
deleted file mode 100644
index 7724890..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h
+++ /dev/null
@@ -1,577 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hash.h
- * @author MCD Application Team
- * @brief Header file of HASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_HASH_H
-#define __STM32H7xx_HAL_HASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#if defined (HASH)
-
-/** @addtogroup HASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HASH_Exported_Types HASH Exported Types
- * @{
- */
-
-/**
- * @brief HASH Configuration Structure definition
- */
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
- This parameter can be a value of @ref HASH_Data_Type. */
-
- uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
-
- uint8_t* pKey; /*!< The key is used only in HMAC operation. */
-
-} HASH_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_HASH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */
- HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */
- HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */
- HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */
-}HAL_HASH_StateTypeDef;
-
-/**
- * @brief HAL phase structures definition
- */
-typedef enum
-{
- HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */
- HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in HASH processing phase */
- HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, /*!< HASH peripheral is in HMAC step 1 processing phase
- (step 1 consists in entering the inner hash function key) */
- HAL_HASH_PHASE_HMAC_STEP_2 = 0x04, /*!< HASH peripheral is in HMAC step 2 processing phase
- (step 2 consists in entering the message text) */
- HAL_HASH_PHASE_HMAC_STEP_3 = 0x05 /*!< HASH peripheral is in HMAC step 3 processing phase
- (step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
-
-/**
- * @brief HAL HASH mode suspend definitions
- */
-typedef enum
-{
- HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */
- HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */
-}HAL_HASH_SuspendTypeDef;
-
-
-/**
- * @brief HASH Handle Structure definition
- */
-typedef struct
-{
- HASH_InitTypeDef Init; /*!< HASH required parameters */
-
- uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
-
- uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
-
- uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
-
- uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
-
- uint32_t HashBuffSize; /*!< Size of buffer to be processed */
-
- __IO uint32_t HashInCount; /*!< Counter of inputted data */
-
- __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
-
- __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
-
- HAL_StatusTypeDef Status; /*!< HASH peripheral status */
-
- HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
-
- DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
-
- HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
-
- FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
-
-} HASH_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants HASH Exported Constants
- * @{
- */
-
-/** @defgroup HASH_Algo_Selection HASH algorithm selection
- * @{
- */
-#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
-#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
-#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
-#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
-/**
- * @}
- */
-
-/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
- * @{
- */
-#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
-#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
-/**
- * @}
- */
-
-/** @defgroup HASH_Data_Type HASH input data type
- * @{
- */
-#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
-#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
-#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
-#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
-/**
- * @}
- */
-
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
- * @{
- */
-#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
-/**
- * @}
- */
-
-/** @defgroup HASH_flags_definition HASH flags definitions
- * @{
- */
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
-
-/**
- * @}
- */
-
-/** @defgroup HASH_interrupts_definition HASH interrupts definitions
- * @{
- */
-#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
-
-/**
- * @}
- */
-
-/** @defgroup HASH_alias HASH API alias
- * @{
- */
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HASH_Exported_Macros HASH Exported Macros
- * @{
- */
-
-/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
- * @arg @ref HASH_FLAG_DCIS Digest calculation complete.
- * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
- * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
- * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
-
-
-/** @brief Clear the specified HASH flag.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
- * @arg @ref HASH_FLAG_DCIS Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
-
-
-/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
- * @arg @ref HASH_IT_DCI Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
- * @arg @ref HASH_IT_DCI Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief Reset HASH handle state.
- * @param __HANDLE__: HASH handle.
- * @retval None
- */
-#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
-
-/** @brief Reset HASH handle status.
- * @param __HANDLE__: HASH handle.
- * @retval None
- */
-#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
-
-/**
- * @brief Enable the multi-buffer DMA transfer mode.
- * @note This bit is set when hashing large files when multiple DMA transfers are needed.
- * @retval None
- */
-#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
-
-/**
- * @brief Disable the multi-buffer DMA transfer mode.
- * @retval None
- */
-#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
-
-
-
-/**
- * @brief Start the digest computation.
- * @retval None
- */
-#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
-
-/**
- * @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__: size in bytes of last data written in Data register.
- * @retval None
-*/
-#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
-
-/**
- * @brief Reset the HASH core.
- * @retval None
- */
-#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
-
-/**
- * @}
- */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros HASH Private Macros
- * @{
- */
-
-/**
- * @brief Return digest length in bytes.
- * @retval Digest length
- */
-#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20 : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28 : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32 : 16 ) ) )
-
-/**
- * @brief Return number of words already pushed in the FIFO.
- * @retval Number of words already pushed in the FIFO
- */
-#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
-
-/**
- * @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__: HASH input data type.
- * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
- */
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_8B) || \
- ((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in polling mode.
- * @note This check is valid only for multi-buffer HASH processing in polling mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0)
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in DMA mode.
- * @note This check is valid only for multi-buffer HASH processing in DMA mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
- * processing in DMA mode.
- * @note This check is valid only for multi-buffer HMAC processing in DMA mode.
- * @param __HANDLE__: HASH handle.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
-
-/**
- * @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__: HASH handle.
- * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
- */
-#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
-
-/**
- * @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__: HASH handle.
- * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
- */
-#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
- ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
- ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-
-/**
- * @}
- */
-
-
-/* Include HASH HAL Extended module */
-#include "stm32h7xx_hal_hash_ex.h"
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HASH_Exported_Functions HASH Exported Functions
- * @{
- */
-
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization methods **********************************/
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- * @{
- */
-
-
-/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- * @{
- */
-
-/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- * @{
- */
-
-/* HASH processing using DMA *************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- * @{
- */
-
-/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- * @{
- */
-
-/* HASH-HMAC processing using DMA ********************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
- * @{
- */
-
-
-/* Peripheral State methods **************************************************/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions -----------------------------------------------------------*/
-
-/** @addtogroup HASH_Private_Functions HASH Private Functions
- * @{
- */
-
-/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HASH */
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_HASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h
deleted file mode 100644
index 3698de4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hash_ex.h
- * @author MCD Application Team
- * @brief Header file of HASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_HASH_EX_H
-#define __STM32H7xx_HAL_HASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
- #if defined (HASH)
-
-/** @addtogroup HASHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
- * @{
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
- * @{
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
- * @{
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HASH */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_HASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h
deleted file mode 100644
index 376f609..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hcd.h
- * @author MCD Application Team
- * @brief Header file of HCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_HCD_H
-#define __STM32H7xx_HAL_HCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_usb.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HCD HCD
- * @brief HCD HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Types HCD Exported Types
- * @{
- */
-
-/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
- * @{
- */
-typedef enum
-{
- HAL_HCD_STATE_RESET = 0x00U,
- HAL_HCD_STATE_READY = 0x01U,
- HAL_HCD_STATE_ERROR = 0x02U,
- HAL_HCD_STATE_BUSY = 0x03U,
- HAL_HCD_STATE_TIMEOUT = 0x04U
-} HCD_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
-typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
-typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
- * @{
- */
-typedef struct
-{
- HCD_TypeDef *Instance; /*!< Register base address */
- HCD_InitTypeDef Init; /*!< HCD required parameters */
- HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
- HAL_LockTypeDef Lock; /*!< HCD peripheral status */
- __IO HCD_StateTypeDef State; /*!< HCD communication state */
- void *pData; /*!< Pointer Stack Handler */
-} HCD_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants HCD Exported Constants
- * @{
- */
-
-/** @defgroup HCD_Speed HCD Speed
- * @{
- */
-#define HCD_SPEED_HIGH 0U
-#define HCD_SPEED_LOW 2U
-#define HCD_SPEED_FULL 3U
-/**
- * @}
- */
-
-/** @defgroup HCD_PHY_Module HCD PHY Module
- * @{
- */
-#define HCD_PHY_ULPI 1U
-#define HCD_PHY_EMBEDDED 2U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions HCD Exported Functions
- * @{
- */
-
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping);
-
- /* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-/** @defgroup HCD_Instance_definition HCD Instance definition
- * @{
- */
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB2_OTG_FS) || \
- ((INSTANCE) == USB1_OTG_HS))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h
deleted file mode 100644
index 5b5688f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h
+++ /dev/null
@@ -1,3640 +0,0 @@
-/**
- ******************************************************************************
- * @file STM32h7xx_hal_hrtim.h
- * @author MCD Application Team
- * @brief Header file of HRTIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_HRTIM_H
-#define __STM32H7xx_HAL_HRTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HRTIM HRTIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
- * @{
- */
-/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
- * @{
- */
-#define MAX_HRTIM_TIMER 6U
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
- * @{
- */
-
-/**
- * @brief HRTIM Configuration Structure definition - Time base related parameters
- */
-typedef struct
-{
- uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance
- This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
- uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals
- This parameter can be a combination of @ref HRTIM_Synchronization_Options */
- uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
- This parameter can be a value of @ref HRTIM_Synchronization_Input_Source */
- uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
- This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
- uint32_t SyncOutputPolarity; /*!< Specifies the conditionning of the event to be sent on the external synchronization outputs
- This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
-} HRTIM_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
- HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
-} HAL_HRTIM_StateTypeDef;
-
-/**
- * @brief HRTIM Timer Structure definition
- */
-typedef struct
-{
- uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
- When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
- When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
- uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
- When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
- When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
- uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
- uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
- uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
- uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
- uint32_t DMASize; /*!< Size of the DMA transfer */
-} HRTIM_TimerParamTypeDef;
-
-/**
- * @brief HRTIM Handle Structure definition
- */
-typedef struct __HRTIM_HandleTypeDef
-{
- HRTIM_TypeDef * Instance; /*!< Register base address */
-
- HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
-
- HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
-
- DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
-} HRTIM_HandleTypeDef;
-
-/**
- * @brief Simple output compare mode configuration definition
- */
-typedef struct {
- uint32_t Period; /*!< Specifies the timer period
- The period value must be above 3 periods of the fHRTIM clock.
- Maximum value is = 0xFFDF */
- uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
- uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
- This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
- uint32_t Mode; /*!< Specifies the counter operating mode
- This parameter can be any value of @ref HRTIM_Mode */
-} HRTIM_TimeBaseCfgTypeDef;
-
-/**
- * @brief Simple output compare mode configuration definition
- */
-typedef struct {
- uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
- This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
-} HRTIM_SimpleOCChannelCfgTypeDef;
-
-/**
- * @brief Simple PWM output mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
-} HRTIM_SimplePWMChannelCfgTypeDef;
-
-/**
- * @brief Simple capture mode configuration definition
- */
-typedef struct {
- uint32_t Event; /*!< Specifies the external event triggering the capture
- This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
- This parameter can be a value of @ref HRTIM_External_Event_Polarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
- This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
- This parameter can be a value of @ref HRTIM_External_Event_Filter */
-} HRTIM_SimpleCaptureChannelCfgTypeDef;
-
-/**
- * @brief Simple One Pulse mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t OutputPolarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
- uint32_t Event; /*!< Specifies the external event triggering the pulse generation
- This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
- This parameter can be a value of @ref HRTIM_External_Event_Polarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
- This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
- This parameter can be a value of @ref HRTIM_External_Event_Filter */
-} HRTIM_SimpleOnePulseChannelCfgTypeDef;
-
-/**
- * @brief Timer configuration definition
- */
-typedef struct {
- uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master
- Specifies which interrupts requests must enabled for the timer
- This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
- or HRTIM_Timing_Unit_Interrupt_Enable */
- uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master
- Specifies which DMA requests must be enabled for the timer
- This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
- or HRTIM_Timing_Unit_DMA_Request_Enable */
- uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master
- Specifies the address of the source address of the DMA transfer */
- uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master
- Specifies the address of the destination address of the DMA transfer */
- uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master
- Specifies the size of the DMA transfer */
- uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master
- Specifies whether or not hald mode is enabled
- This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
- uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master
- Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
- This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
- uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master
- Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
- This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
- uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master
- Indicates whether or not the a DAC synchronization event is generated
- This parameter can be any value of @ref HRTIM_DAC_Synchronization */
- uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master
- Specifies whether or not register preload is enabled
- This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
- uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master
- Specifies how the update occurs with respect to a burst DMA transaction or
- update enable inputs (Slave timers only)
- This parameter can be any value of @ref HRTIM_Update_Gating */
- uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master
- Specifies how the timer behaves during a burst mode operation
- This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
- uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master
- Specifies whether or not registers update is triggered by the repetition event
- This parameter can be any valuen of @ref HRTIM_Timer_Repetition_Update */
- uint32_t PushPull; /*!< Relevant for Timer A to Timer E
- Specifies whether or not the push-pull mode is enabled
- This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
- uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E
- Specifies which fault channels are enabled for the timer
- This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
- uint32_t FaultLock; /*!< Relevant for Timer A to Timer E
- Specifies whether or not fault enabling status is write protected
- This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
- uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E
- Specifies whether or not deadtime insertion is enabled for the timer
- This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
- uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E
- Specifies the delayed protection mode
- This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
- uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E
- Specifies source(s) triggering the timer registers update
- This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
- uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E
- Specifies source(s) triggering the timer counter reset
- This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
- uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E
- Specifies whether or not registers update is triggered when the timer counter is reset
- This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
-} HRTIM_TimerCfgTypeDef;
-
-/**
- * @brief Compare unit configuration definition
- */
-typedef struct {
- uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
- the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
- the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
- uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
- This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
- uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
- CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
-} HRTIM_CompareCfgTypeDef;
-
-/**
- * @brief Capture unit configuration definition
- */
-typedef struct {
- uint32_t Trigger; /*!< Specifies source(s) triggering the capture
- This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
-} HRTIM_CaptureCfgTypeDef;
-
-/**
- * @brief Output configuration definition
- */
-typedef struct {
- uint32_t Polarity; /*!< Specifies the output polarity.
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
- This parameter can be a combination of @ref HRTIM_Output_Set_Source */
- uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
- This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
- uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
- This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
- uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
- This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
- uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled.
- This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
- uint32_t BurstModeEntryDelayed; /* !State = HAL_HRTIM_STATE_RESET)
-
-/** @brief Enables or disables the timer counter(s)
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __TIMERS__: timersto enable/disable
- * This parameter can be any combinations of the following values:
- * @arg HRTIM_TIMERID_MASTER: Master timer identifier
- * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
- * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
- * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
- * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
- * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
-
-/* The counter of a timing unit is disabled only if all the timer outputs */
-/* are disabled and no capture is configured */
-#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
-#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
-#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
-#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
-#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
-#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
- do {\
- if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
- }\
- }\
- } while(0)
-
-/** @brief Enables or disables the specified HRTIM common interrupts.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
- * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
- * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
-#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Master timer interrupts.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
-#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Timerx interrupts.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __TIMER__: specified the timing unit (Timer A to E)
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
-#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
-
-/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 enable
- * @arg HRTIM_IT_FLT4: Fault 4 enable
- * @arg HRTIM_IT_FLT5: Fault 5 enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __TIMER__: specified the timing unit (Timer A to E)
- * @param __INTERRUPT__: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clears the specified HRTIM common pending flag.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
- * @arg HRTIM_IT_FLT3: Fault 3 clear flag
- * @arg HRTIM_IT_FLT4: Fault 4 clear flag
- * @arg HRTIM_IT_FLT5: Fault 5 clear flag
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
-
-/** @brief Clears the specified HRTIM Master pending flag.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
-
-/** @brief Clears the specified HRTIM Timerx pending flag.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __TIMER__: specified the timing unit (Timer A to E)
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
- * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
-
-/* DMA HANDLING */
-/** @brief Enables or disables the specified HRTIM common interrupts.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
- * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
- * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
-#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __DMA__: specifies the DMA request to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
- * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
-#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
-
-/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
- * @param __HANDLE__: specifies the HRTIM Handle.
- * @param __TIMER__: specified the timing unit (Timer A to E)
- * @param __DMA__: specifies the DMA request to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
- * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
- * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
- * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
- * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
-#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
-
-#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
-
-#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
-
-#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
-
-/** @brief Sets the HRTIM timer Counter Register value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COUNTER__: specifies the Counter Register new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
-
-/** @brief Gets the HRTIM timer Counter Register value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval HRTIM timer Counter Register value
- */
-#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
-
-/** @brief Sets the HRTIM timer Period value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __PERIOD__: specifies the Period Register new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
-
-/** @brief Gets the HRTIM timer Period Register value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval timer Period Register
- */
-#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
-
-/** @brief Sets the HRTIM timer clock prescaler value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __PRESCALER__: specifies the clock prescaler new value.
- * This parameter can be one of the following values:
- * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
- * @retval None
- */
-#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
-
-/** @brief Gets the HRTIM timer clock prescaler value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval timer clock prescaler value
- */
-#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
-
-/** @brief Sets the HRTIM timer Compare Register value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COMPAREUNIT__: timer compare unit
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param __COMPARE__: specifies the Compare new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
- : \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
-
-/** @brief Gets the HRTIM timer Compare Register value on runtime
- * @param __HANDLE__: HRTIM Handle.
- * @param __TIMER__: HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COMPAREUNIT__: timer compare unit
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @retval Compare value
- */
-#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
- ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
- : \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HRTIM_Exported_Functions HRTIM Exported Functions
-* @{
-*/
-
-/** @addtogroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
-* @{
-*/
-
-/* Initialization and Configuration functions ********************************/
-HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
-
-void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
-
-void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
-* @{
-*/
-
-/* Simple time base related functions *****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
-* @{
-*/
-/* Simple output compare related functions ************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
-* @{
-*/
-/* Simple PWM output related functions ****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group5 Simple input capture functions
-* @{
-*/
-/* Simple capture related functions *******************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
-* @{
-*/
-/* Simple one pulse related functions *****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel,
- HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group7 Configuration functions
-* @{
-*/
-HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
- HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef* pEventCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Prescaler);
-
-HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Fault,
- HRTIM_FaultCfgTypeDef* pFaultCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Prescaler);
-
-void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Faults,
- uint32_t Enable);
-
-HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t ADCTrigger,
- HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
-* @{
-*/
-/* Waveform related functions *************************************************/
-HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef* pCompareCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- HRTIM_CaptureCfgTypeDef* pCaptureCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- uint32_t OutputLevel);
-
-HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Event,
- HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t RegistersToUpdate);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t OutputsToStart);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t OutputsToStop);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Enable);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t BurstBufferAddress,
- uint32_t BurstBufferLength);
-
-HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group9 Peripheral state functions
-* @{
-*/
-/* HRTIM peripheral state functions */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
-
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit);
-
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
-
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group10 Interrupts handling
-* @{
-*/
-/* IRQ handler */
-void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/* HRTIM events related callback functions */
-void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
-
-/* Timer events related callback functions */
-void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_HRTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
deleted file mode 100644
index d048022..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hsem.h
- * @author MCD Application Team
- * @brief Header file of HSEM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_HSEM_H
-#define __STM32H7xx_HAL_HSEM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HSEM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup HSEM_Exported_Types HSEM Exported Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HSEM_Exported_Constants HSEM Exported Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
- * @{
- */
-
-/**
- * @brief SemID to mask helper Macro.
- * @param __SEMID__: semaphore ID from 0 to 31
- * @retval Semaphore Mask.
- */
-#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
-
-
-/**
- * @brief Enables the specified HSEM interrupts.
- * @param __SEM_MASK__: semaphores Mask
- * @retval None.
- */
-#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
-/**
- * @brief Disables the specified HSEM interrupts.
- * @param __SEM_MASK__: semaphores Mask
- * @retval None.
- */
-#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
-
-/**
- * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
- * @param __SEM_MASK__: semaphores Mask
-* @retval semaphores Mask : Semaphores where an interrupt occurred.
- */
-#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
-
-/**
- * @brief Get the semaphores release status flags.
- * @param __SEM_MASK__: semaphores Mask
- * @retval semaphores Mask : Semaphores where Release flags rise.
- */
-#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
-
-/**
- * @brief Clears the HSEM Interrupt flags.
- * @param __SEM_MASK__: semaphores Mask
- * @retval None.
- */
-#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
- * @{
- */
-
-
-/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
- * @brief HSEM Take and Release functions
- * @{
- */
-
-/* HSEM semaphore take (lock) using 2-Step method ****************************/
-HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
-/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
-HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
-/* HSEM Check semaphore state Taken or not **********************************/
-uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
-/* HSEM Release **************************************************************/
-void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
-/* HSEM Release All************************************************************/
-void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t MasterID);
-
-/**
- * @}
- */
-
-/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
- * @brief HSEM Set and Get Key functions.
- * @{
- */
-/* HSEM Set Clear Key *********************************************************/
-void HAL_HSEM_SetClearKey(uint32_t Key);
-/* HSEM Get Clear Key *********************************************************/
-uint32_t HAL_HSEM_GetClearKey(void);
-/**
- * @}
- */
-
-
-/** @addtogroup HSEM_Exported_Functions_Group3
- * @brief HSEM Notification functions
- * @{
- */
-/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
-void HAL_HSEM_ActivateNotification(uint32_t SemMask);
-/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
-void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
-/* HSEM Free Callback (When a semaphore is released) *******************************/
-void HAL_HSEM_FreeCallback(uint32_t SemMask);
-/* HSEM IRQ Handler **********************************************************/
-void HAL_HSEM_IRQHandler(void);
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HSEM_Private_Types HSEM Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HSEM_Private_Variables HSEM Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HSEM_Private_Constants HSEM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HSEM_Private_Macros HSEM Private Macros
- * @{
- */
-
-#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
-
-#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
-
-#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
-
-#define IS_HSEM_MASTERID(__MASTERID__) (((__MASTERID__) == HSEM_CM7_MASTERID))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
deleted file mode 100644
index 76d5d06..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
+++ /dev/null
@@ -1,673 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_I2C_H
-#define __STM32H7xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
- * @{
- */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
- * @brief I2C Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
- section in Reference manual */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-}I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
- * @brief HAL State structure definition
- * @{
- */
-
-typedef enum
-{
- HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
- HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
- HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
- HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-
-}HAL_I2C_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
- * @brief HAL Mode structure definition
- * @{
- */
-typedef enum
-{
- HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-
-}HAL_I2C_ModeTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
- * @brief I2C Error Code definition
- * @{
- */
-#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
-#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
-/**
- * @}
- */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
- * @brief I2C handle Structure definition
- * @{
- */
-typedef struct __I2C_HandleTypeDef
-{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
- be a value of @ref I2C_XFEROPTIONS */
-
- __IO uint32_t PreviousState; /*!< I2C communication Previous state */
-
- HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
- __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
-}I2C_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
- * @{
- */
-#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
-#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-/**
- * @}
- */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
- * @{
- */
-#define I2C_DUALADDRESS_DISABLE (0x00000000U)
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-/**
- * @}
- */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
- * @{
- */
-#define I2C_OA2_NOMASK ((uint8_t)0x00U)
-#define I2C_OA2_MASK01 ((uint8_t)0x01U)
-#define I2C_OA2_MASK02 ((uint8_t)0x02U)
-#define I2C_OA2_MASK03 ((uint8_t)0x03U)
-#define I2C_OA2_MASK04 ((uint8_t)0x04U)
-#define I2C_OA2_MASK05 ((uint8_t)0x05U)
-#define I2C_OA2_MASK06 ((uint8_t)0x06U)
-#define I2C_OA2_MASK07 ((uint8_t)0x07U)
-/**
- * @}
- */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
- * @{
- */
-#define I2C_GENERALCALL_DISABLE (0x00000000U)
-#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
-/**
- * @}
- */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
- * @{
- */
-#define I2C_NOSTRETCH_DISABLE (0x00000000U)
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
- * @{
- */
-#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_XferDirection I2C Transfer Direction
- * @{
- */
-#define I2C_DIRECTION_TRANSMIT (0x00000000U)
-#define I2C_DIRECTION_RECEIVE (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
- * @{
- */
-#define I2C_RELOAD_MODE I2C_CR2_RELOAD
-#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
-#define I2C_SOFTEND_MODE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
- * @{
- */
-#define I2C_NO_STARTSTOP (0x00000000U)
-#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
- * @brief I2C Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-/**
- * @}
- */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
- * @{
- */
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_AF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-#define I2C_FLAG_DIR I2C_ISR_DIR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @brief Reset I2C handle state.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief Enable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief Disable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified I2C interrupt source is enabled or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified I2C flag is set or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
- * @arg @ref I2C_FLAG_RXNE Receive data register not empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
- * @arg @ref I2C_FLAG_TCR Transfer complete reload
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- * @arg @ref I2C_FLAG_BUSY Bus busy
- * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
- *
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- *
- * @retval None
- */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief Enable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
- * @param __HANDLE__: specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
- * @}
- */
-
-/* Include I2C HAL Extended module */
-#include "stm32h7xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* IO operation functions ****************************************************/
- /******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
- /******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
- /******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
- * @}
- */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @{
- */
-/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
- * @{
- */
-
-#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
- ((MASK) == I2C_OA2_MASK01) || \
- ((MASK) == I2C_OA2_MASK02) || \
- ((MASK) == I2C_OA2_MASK03) || \
- ((MASK) == I2C_OA2_MASK04) || \
- ((MASK) == I2C_OA2_MASK05) || \
- ((MASK) == I2C_OA2_MASK06) || \
- ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
- ((MODE) == I2C_AUTOEND_MODE) || \
- ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
- ((REQUEST) == I2C_GENERATE_START_READ) || \
- ((REQUEST) == I2C_GENERATE_START_WRITE) || \
- ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
- ((REQUEST) == I2C_NEXT_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
-#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
-#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions are defined in stm32h7xx_hal_i2c.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
deleted file mode 100644
index 5e5f942..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2c_ex.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_I2C_EX_H
-#define __STM32H7xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2CEx I2CEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
- * @{
- */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
- * @{
- */
-#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
-#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-/**
- * @}
- */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
- * @{
- */
-#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
-#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
-#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
-#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
-
-#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
-#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
-#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
-#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
- * @{
- */
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-
-#if defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
-#elif defined(SYSCFG_PMCR_I2C1_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
-#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
- * @{
- */
-/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_I2C_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h
deleted file mode 100644
index 4bacbe4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h
+++ /dev/null
@@ -1,615 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2s.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_I2S_H
-#define __STM32H7xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2S
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref I2S_MSB_LSB_transmission */
-
- uint32_t WSInversion; /*!< Control the Word Select Inversion.
- This parameter can be a value of @ref I2S_WSInversion */
-
- uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
- This parameter can be a value of @ref I2S_IO_Swap */
-
- uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data lenght
- This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
-
- uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref I2S_Fifo_Threshold */
-
- uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
- This parameter can be a value of @ref I2S_Master_Keep_IO_State */
-
- uint32_t SlaveExtendFREDetection; /*!< Control the channel length in SLAVE.
- This parameter can be a value of @ref I2S_SlaveExtendFREDetection */
-
-
-}I2S_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-}HAL_I2S_StateTypeDef;
-
-/**
- * @brief I2S handle Structure definition
- */
-typedef struct __I2S_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< I2S registers base address */
-
- I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter */
-
- void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
-
- __IO uint32_t ErrorCode; /*!< I2S Error code */
-
-}I2S_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/**
- * @defgroup I2S_Error_Defintion I2S Error Defintion
- * @brief I2S Error Code
- * @{
- */
-#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2S_ERROR_UDR (0x00000001U) /*!< I2S Underrun error */
-#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< I2S Overrun error */
-#define HAL_I2S_ERROR_FRE (0x00000004U) /*!< I2S Frame format error */
-#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_TIMEOUT (0x00000010U) /*!< Timeout error */
-#define HAL_I2S_ERROR_PRESCALER (0x00000020U) /*!< Prescaler error */
- /**
- * @}
- */
-
-/** @defgroup I2S_Mode I2S Mode
- * @{
- */
-#define I2S_MODE_SLAVE_TX (0x00000000U)
-#define I2S_MODE_SLAVE_RX (0x00000002U)
-#define I2S_MODE_MASTER_TX (0x00000004U)
-#define I2S_MODE_MASTER_RX (0x00000006U)
-#define I2S_MODE_SLAVE_FD (0x00000008U)
-#define I2S_MODE_MASTER_FD (0x0000000AU)
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard I2S Standard
- * @{
- */
-#define I2S_STANDARD_PHILIPS (0x00000000U)
-#define I2S_STANDARD_MSB (0x00000010U)
-#define I2S_STANDARD_LSB (0x00000020U)
-#define I2S_STANDARD_PCM_SHORT (0x00000030U)
-#define I2S_STANDARD_PCM_LONG (0x000000B0U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format I2S Data Format
- * @{
- */
-#define I2S_DATAFORMAT_16B (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)
-#define I2S_DATAFORMAT_24B (0x00000500U)
-#define I2S_DATAFORMAT_32B (0x00000600U)
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
- * @{
- */
-#define I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE
-#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
- * @{
- */
-#define I2S_AUDIOFREQ_192K (192000U)
-#define I2S_AUDIOFREQ_96K (96000U)
-#define I2S_AUDIOFREQ_48K (48000U)
-#define I2S_AUDIOFREQ_44K (44100U)
-#define I2S_AUDIOFREQ_32K (32000U)
-#define I2S_AUDIOFREQ_22K (22050U)
-#define I2S_AUDIOFREQ_16K (16000U)
-#define I2S_AUDIOFREQ_11K (11025U)
-#define I2S_AUDIOFREQ_8K (8000U)
-#define I2S_AUDIOFREQ_DEFAULT (2U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
- * @{
- */
-#define I2S_CPOL_LOW (0x00000000U)
-#define I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL
-/**
- * @}
- */
-
-/** @defgroup I2S_MSB_LSB_transmission I2S MSB LSB Transmission
- * @{
- */
-#define I2S_FIRSTBIT_MSB (0x00000000U)
-#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
-/**
- * @}
- */
-
-/** @defgroup I2S_WSInversion I2S Word Select Inversion
- * @{
- */
-#define I2S_WS_INVERSION_DISABLE (0x00000000U)
-#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
-/**
- * @}
- */
-
-/** @defgroup I2S_IO_Swap Control I2S IO Swap
- * @{
- */
-#define I2S_IO_SWAP_DISABLE (0x00000000U)
-#define I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
- * @{
- */
-#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)
-#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
-/**
- * @}
- */
-
-/** @defgroup I2S_Fifo_Threshold I2S Fifo Threshold
- * @{
- */
-#define I2S_FIFO_THRESHOLD_01DATA (0x00000000U)
-#define I2S_FIFO_THRESHOLD_02DATA (0x00000020U)
-#define I2S_FIFO_THRESHOLD_03DATA (0x00000040U)
-#define I2S_FIFO_THRESHOLD_04DATA (0x00000060U)
-#define I2S_FIFO_THRESHOLD_05DATA (0x00000080U)
-#define I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)
-#define I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)
-#define I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Master_Keep_IO_State Keep IO State
- * @{
- */
-#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
-#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
-/**
- * @}
- */
-
-/** @defgroup I2S_SlaveExtendFREDetection Slave Extend FRE Detection
- * @{
- */
-#define I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
-#define I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH
-/**
- * @}
- */
-
-/** @defgroup I2S_Interrupt_definition I2S Interrupt definition
- * @{
- */
-#define I2S_IT_TXE SPI_IER_TXPIE
-#define I2S_IT_RXNE SPI_IER_RXPIE
-#define I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Flag_definition I2S Flag definition
- * @{
- */
-#define I2S_FLAG_TXE SPI_SR_TXP /* I2S status flag: Tx buffer empty flag */
-#define I2S_FLAG_RXNE SPI_SR_RXP /* I2S status flag: Rx buffer not empty flag */
-#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */
-#define I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */
-#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */
-#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @brief Reset I2S handle state
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief Enable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Enable the specified I2S interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
-
-/** @brief Disable the specified I2S interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2S Handle.
- * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__: specifies the I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2S flag is set or not.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_TXE : Tx buffer empty flag
- * @arg I2S_FLAG_RXNE : Rx buffer not empty flag
- * @arg I2S_FLAG_UDR : Underrun flag
- * @arg I2S_FLAG_OVR : Overrun flag
- * @arg I2S_FLAG_FRE : TI mode frame format error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S UDR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
-
-/** @brief Clears the I2S OVR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
-
-/** @brief Clear the I2S FRE pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
-
-/* Include I2S HAL Extended module */
-#include "stm32h7xx_hal_i2s_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private I2S Private
- * @{
- */
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX) || \
- ((MODE) == I2S_MODE_SLAVE_FD) || \
- ((MODE) == I2S_MODE_MASTER_FD))
-
-#define IS_I2S_FD_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_FD) || \
- ((MODE) == I2S_MODE_MASTER_FD))
-
-#define IS_I2S_MASTER(MODE) (((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX) || \
- ((MODE) == I2S_MODE_MASTER_FD))
-
-#define IS_I2S_TX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_SLAVE_FD) || \
- ((MODE) == I2S_MODE_MASTER_FD))
-
-#define IS_I2S_RX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_RX) || \
- ((MODE) == I2S_MODE_SLAVE_FD) || \
- ((MODE) == I2S_MODE_MASTER_FD))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
-
-#define IS_I2S_FIRST_BIT(FIRSTBIT) (((FIRSTBIT) == I2S_FIRSTBIT_MSB) || \
- ((FIRSTBIT) == I2S_FIRSTBIT_LSB))
-
-#define IS_I2S_WS_INVERSION(WSINV) (((WSINV) == I2S_WS_INVERSION_DISABLE) || \
- ((WSINV) == I2S_WS_INVERSION_ENABLE))
-
-#define IS_I2S_IO_SWAP(IOSWAP) (((IOSWAP) == I2S_IO_SWAP_DISABLE) || \
- ((IOSWAP) == I2S_IO_SWAP_ENABLE))
-
-#define IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT) (((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
- ((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
-
-#define IS_I2S_FIFO_THRESHOLD(FTHLV) (((FTHLV) == I2S_FIFO_THRESHOLD_01DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_02DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_03DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_04DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_05DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_06DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_07DATA) || \
- ((FTHLV) == I2S_FIFO_THRESHOLD_08DATA))
-
-#define IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR) (((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
- ((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
-
-#define IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH) (((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE) || \
- ((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE))
-
-/**
- * @}
- */
-
-/* Define the private group ***************************************************/
-/******************************************************************************/
-/** @defgroup I2S_Private I2S Private
- * @{
- */
-/**
- * @}
- */
-/******************************************************************************/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /* __STM32H7xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h
deleted file mode 100644
index db8c0bd..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2s_ex.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_I2S_EX_H
-#define __STM32H7xx_HAL_I2S_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-/** @addtogroup I2SEx I2SEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
- * @{
- */
-
-/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
- * @{
- */
-
-/* Extended features functions *************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/* I2S Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_I2S_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h
deleted file mode 100644
index 462f68c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h
+++ /dev/null
@@ -1,848 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_irda.h
- * @author MCD Application Team
- * @brief Header file of IRDA HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_IRDA_H
-#define __STM32H7xx_HAL_IRDA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
- * @{
- */
-
-/**
- * @brief IRDA Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
- The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref IRDA_Word_Length */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref IRDA_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Transfer_Mode */
-
- uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
- to achieve low-power frequency.
- @note Prescaler value 0 is forbidden */
-
- uint16_t PowerMode; /*!< Specifies the IRDA power mode.
- This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
-
-/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
- * - gState contains IRDA state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
-
-/**
- * @brief HAL IRDA Error Code structure definition
- */
-typedef enum
-{
- HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
- HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
- HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
- HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
- HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_IRDA_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_IRDA_ERROR_BUSY = 0x20 /*!< Busy Error */
-}HAL_IRDA_ErrorTypeDef;
-
-/**
- * @brief IRDA clock sources definition
- */
-typedef enum
-{
- IRDA_CLOCKSOURCE_D2PCLK1 = 0x00, /*!< Domain2 PCLK1 clock source */
- IRDA_CLOCKSOURCE_D2PCLK2 = 0x01, /*!< Domain2 PCLK2 clock source */
- IRDA_CLOCKSOURCE_D3PCLK1 = 0x02, /*!< Domain3 PCLK1 clock source */
- IRDA_CLOCKSOURCE_PLL2Q = 0x04, /*!< PLL2Q clock source */
- IRDA_CLOCKSOURCE_HSI = 0x08, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_CSI = 0x10, /*!< CSI clock source */
- IRDA_CLOCKSOURCE_LSE = 0x20, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_PLL3Q = 0x40, /*!< PCLK2 clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x80 /*!< Undefined clock source */
-}IRDA_ClockSourceTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< IRDA registers base address */
-
- IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
- uint16_t Mask; /*!< IRDA RX RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- uint32_t ErrorCode; /*!< IRDA Error code */
-
-}IRDA_HandleTypeDef;
-
-/**
- * @brief IRDA Configuration enumeration values definition
- */
-typedef enum
-{
- IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */
- IRDA_PARITY = 0x01, /*!< IRDA frame parity */
- IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */
- IRDA_MODE = 0x03, /*!< IRDA communication mode */
- IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */
- IRDA_POWERMODE = 0x05 /*!< IRDA power mode */
-}IRDA_ControlTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
- * @{
- */
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
- * @{
- */
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Parity IRDA Parity
- * @{
- */
-#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
- * @{
- */
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
- * @{
- */
-#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_State IRDA State
- * @{
- */
-#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
-#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Mode IRDA Mode
- * @{
- */
-#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
-#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */
-#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
- * @{
- */
-#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */
-#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
- * @{
- */
-#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */
-#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
- * @{
- */
-#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Flags IRDA Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */
-#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */
-#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */
-#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */
-#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */
-#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */
-#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */
-#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
-#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
-#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
-#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Framing error */
-#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */
-#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
-#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
-#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
-#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
-#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
- * @{
- */
-#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
- * @{
- */
-#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
- * @{
- */
-
-/** @brief Reset IRDA handle state.
- * @param __HANDLE__: IRDA handle.
- * @retval None
- */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0)
-
-/** @brief Flush the IRDA DR register.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0)
-
-/** @brief Clear the specified IRDA pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref IRDA_CLEAR_PEF
- * @arg @ref IRDA_CLEAR_FEF
- * @arg @ref IRDA_CLEAR_NEF
- * @arg @ref IRDA_CLEAR_OREF
- * @arg @ref IRDA_CLEAR_TCF
- * @arg @ref IRDA_CLEAR_IDLEF
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
-
-
-/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
-
-/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
-
-/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
-
-/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
-
-/** @brief Check whether the specified IRDA flag is set or not.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref IRDA_FLAG_BUSY Busy flag
- * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
- * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
- * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
- * @arg @ref IRDA_FLAG_TC Transmission Complete flag
- * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
- * @arg @ref IRDA_FLAG_ORE OverRun Error flag
- * @arg @ref IRDA_FLAG_NE Noise Error flag
- * @arg @ref IRDA_FLAG_FE Framing Error flag
- * @arg @ref IRDA_FLAG_PE Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief Enable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-/** @brief Disable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-
-/** @brief Check whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __IT__: specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_ORE OverRun Error interrupt
- * @arg @ref IRDA_IT_NE Noise Error interrupt
- * @arg @ref IRDA_IT_FE Framing Error interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
-
-/** @brief Check whether the specified IRDA interrupt source is enabled or not.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __IT__: specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
-
-
-/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
- * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-
-/** @brief Set a specific IRDA request flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __REQ__: specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
- * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
- * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief Enable the IRDA one bit sample method.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the IRDA one bit sample method.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART/USART associated to IRDA Handle.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART/USART associated to IRDA Handle.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
- * @{
- */
-
-/** @brief Compute the mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003F ; \
- } \
- } \
-} while(0)
-
-/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
- * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
- * @retval True or False
- */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-
-/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
- * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
- * @retval True or False
- */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
-
-/**
- * @brief Ensure that IRDA frame length is valid.
- * @param __LENGTH__: IRDA frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
- ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
- ((__LENGTH__) == IRDA_WORDLENGTH_9B))
-
-/**
- * @brief Ensure that IRDA frame parity is valid.
- * @param __PARITY__: IRDA frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
- ((__PARITY__) == IRDA_PARITY_EVEN) || \
- ((__PARITY__) == IRDA_PARITY_ODD))
-
-/**
- * @brief Ensure that IRDA communication mode is valid.
- * @param __MODE__: IRDA communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
-
-/**
- * @brief Ensure that IRDA power mode is valid.
- * @param __MODE__: IRDA power mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
- ((__MODE__) == IRDA_POWERMODE_NORMAL))
-
-/**
- * @brief Ensure that IRDA state is valid.
- * @param __STATE__: IRDA state mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
- ((__STATE__) == IRDA_STATE_ENABLE))
-
-/**
- * @brief Ensure that IRDA associated UART/USART mode is valid.
- * @param __MODE__: IRDA associated UART/USART mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
- ((__MODE__) == IRDA_MODE_ENABLE))
-
-/**
- * @brief Ensure that IRDA sampling rate is valid.
- * @param __ONEBIT__: IRDA sampling rate.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that IRDA DMA TX mode is valid.
- * @param __DMATX__: IRDA DMA TX mode.
- * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
-#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
- ((__DMATX__) == IRDA_DMA_TX_ENABLE))
-
-/**
- * @brief Ensure that IRDA DMA RX mode is valid.
- * @param __DMARX__: IRDA DMA RX mode.
- * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
- ((__DMARX__) == IRDA_DMA_RX_ENABLE))
-
-/**
- * @brief Ensure that IRDA request is valid.
- * @param __PARAM__: IRDA request.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
-/**
- * @}
- */
-
-/* Include IRDA HAL Extended module */
-#include "stm32h7xx_hal_irda_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-
-/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h
deleted file mode 100644
index 19aef8a..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_irda_ex.h
- * @author MCD Application Team
- * @brief Header file of IRDA HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_IRDA_EX_H
-#define __STM32H7xx_HAL_IRDA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
- * @{
- */
-
-/** @brief Report the IRDA clock source.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __CLOCKSOURCE__: output variable.
- * @retval IRDA clocking source, written in __CLOCKSOURCE__.
- */
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART1CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART2CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART3CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
- case RCC_UART4CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_UART4CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if ((__HANDLE__)->Instance == UART5) \
- { \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
- case RCC_UART5CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART5CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_UART5CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_UART5CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART5CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART5CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
- case RCC_USART6CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART6CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART6CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART6CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART6CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART7) \
- { \
- switch(__HAL_RCC_GET_UART7_SOURCE()) \
- { \
- case RCC_UART7CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART7CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_UART7CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_UART7CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART7CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART7CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART8) \
- { \
- switch(__HAL_RCC_GET_UART8_SOURCE()) \
- { \
- case RCC_UART8CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART8CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_UART8CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_UART8CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART8CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART8CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- } while(0)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_IRDA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h
deleted file mode 100644
index 744944a..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_IWDG_H
-#define __STM32H7xx_HAL_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IWDG IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
- * @{
- */
-
-/**
- * @brief IWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
- This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
- uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
- * @brief IWDG Handle Structure definition
- */
-typedef struct
-{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
- IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-
-}IWDG_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
- * @{
- */
-#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-/**
- * @}
- */
-
-/** @defgroup IWDG_Window_option IWDG Window option
- * @{
- */
-#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the IWDG peripheral.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
- * @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
- * @{
- */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
- * @{
- */
-/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
- * @{
- */
-
-/**
- * @brief IWDG Key Register BitMask
- */
-#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
- * @{
- */
-
-/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
- * @brief Check IWDG prescaler value.
- * @param __PRESCALER__: IWDG prescaler value
- * @retval None
- */
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
- * @brief Check IWDG reload value.
- * @param __RELOAD__: IWDG reload value
- * @retval None
- */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
-
-/**
- * @brief Check IWDG window value.
- * @param __WINDOW__: IWDG window value
- * @retval None
- */
-#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h
deleted file mode 100644
index d16a11f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h
+++ /dev/null
@@ -1,570 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_jpeg.h
- * @author MCD Application Team
- * @brief Header file of JPEG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_JPEG_H
-#define __STM32H7xx_HAL_JPEG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-#include "stm32h7xx_hal_mdma.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup JPEG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup JPEG_Exported_Types JPEG Exported Types
- * @{
- */
-
-/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
- * @brief JPEG encoding configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
- This parameter can be a value of @ref JPEG_ColorSpace */
-
- uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
- This parameter can be a value of @ref JPEG_ChromaSubsampling */
-
- uint32_t ImageHeight; /*!< Image height : number of lines */
-
- uint32_t ImageWidth; /*!< Image width : number of pixels per line */
-
- uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
-
-}JPEG_ConfTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
- * @brief HAL JPEG State structure definition
- * @{
- */
-typedef enum
-{
- HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */
- HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */
- HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */
- HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */
- HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
- HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
- HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
-}HAL_JPEG_STATETypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
- * @brief JPEG handle Structure definition
- * @{
- */
-typedef struct
-{
- JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
-
- JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */
-
- uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
-
- uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
-
- __IO uint32_t JpegInCount; /*!< Internal Counter of input data */
-
- __IO uint32_t JpegOutCount; /*!< Internal Counter of output data */
-
- uint32_t InDataLength; /*!< Input Buffer Length in Bytes */
-
- uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */
-
- MDMA_HandleTypeDef *hdmain; /*!< JPEG In MDMA handle parameters */
-
- MDMA_HandleTypeDef *hdmaout; /*!< JPEG Out MDMA handle parameters */
-
- uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
-
- uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
-
- uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */
-
- uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */
-
- uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */
-
- HAL_LockTypeDef Lock; /*!< JPEG locking object */
-
- __IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */
-
- __IO uint32_t ErrorCode; /*!< JPEG Error code */
-
- __IO uint32_t Context; /*!< JPEG Internal context */
-
-}JPEG_HandleTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
- * @{
- */
-
-/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
- * @brief JPEG Error Code definition
- * @{
- */
-
-#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */
-#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
-#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
-#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
- * @brief JPEG Quantization Table Size
- * @{
- */
-#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */
-/**
- * @}
- */
-
-
-/** @defgroup JPEG_ColorSpace JPEG ColorSpace
- * @brief JPEG Color Space
- * @{
- */
-#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
-#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
-#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
- * @brief JPEG Chrominance Sampling
- * @{
- */
-#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */
-#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */
-#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_ImageQuality JPEG Image Quality
- * @brief JPEG Min and Max Image Quality
- * @{
- */
-#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */
-#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
- * @brief JPEG Interrupt definition
- * @{
- */
-#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */
-#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */
-#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */
-#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */
-#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */
-#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */
-/**
- * @}
- */
-
-/** @defgroup JPEG_Flag_definition JPEG Flag definition
- * @brief JPEG Flags definition
- * @{
- */
-#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
-#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
-#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
-#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
-#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
-#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
-#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/
-
-#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/
-/**
- * @}
- */
-
-/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
- * @brief JPEG process pause, resume definition
- * @{
- */
-#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/
-#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/
-#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
- * @{
- */
-
-/** @brief Reset JPEG handle state
- * @param __HANDLE__: specifies the JPEG handle.
- * @retval None
- */
-#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
-
-
-/**
- * @brief Enable the JPEG peripheral.
- * @param __HANDLE__: specifies the JPEG handle.
- * @retval None
- */
-#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
-
-/**
- * @brief Disable the JPEG peripheral.
- * @param __HANDLE__: specifies the JPEG handle.
- * @retval None
- */
-#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
-
-
-/**
- * @brief Check the specified JPEG status flag.
- * @param __HANDLE__: specifies the JPEG handle.
- * @param __FLAG__ : specifies the flag to check
- * This parameter can be one of the following values:
- * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
- * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
- * @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
- * @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
- * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
- * and than last data has been sent to the output FIFO
- * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
- * and the internal registers have been updated
- * @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
- *
- * @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
- */
-
-#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
-
-/**
- * @brief Clear the specified JPEG status flag.
- * @param __HANDLE__: specifies the JPEG handle.
- * @param __FLAG__ : specifies the flag to clear
- * This parameter can be one of the following values:
- * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
- * and than last data has been sent to the output FIFO
- * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
- * @retval : None
- */
-
-#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
-
-
-/**
- * @brief Enable Interrupt.
- * @param __HANDLE__: specifies the JPEG handle.
- * @param __INTERRUPT__ : specifies the interrupt to enable
- * This parameter can be one of the following values:
- * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
- * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
- * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
- * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
- * @arg JPEG_IT_EOC : End of Conversion Interrupt
- * @arg JPEG_IT_HPD : Header Parsing Done Interrupt
- *
- * @retval : No retrun
- */
-#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
-
-/**
- * @brief Disable Interrupt.
- * @param __HANDLE__: specifies the JPEG handle.
- * @param __INTERRUPT__ : specifies the interrupt to disable
- * This parameter can be one of the following values:
- * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
- * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
- * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
- * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
- * @arg JPEG_IT_EOC : End of Conversion Interrupt
- * @arg JPEG_IT_HPD : Header Parsing Done Interrupt
- *
- * @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
- * located in the same IT enable register (CR register).
- * @retval : No retrun
- */
-#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
-
-
-/**
- * @brief Get Interrupt state.
- * @param __HANDLE__: specifies the JPEG handle.
- * @param __INTERRUPT__ : specifies the interrupt to check
- * This parameter can be one of the following values:
- * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
- * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
- * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
- * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
- * @arg JPEG_IT_EOC : End of Conversion Interrupt
- * @arg JPEG_IT_HPD : Header Parsing Done Interrupt
- *
- * @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
- */
-#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup JPEG_Exported_Functions
- * @{
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
-HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
-void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
-void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group2
- * @{
- */
-/* Encoding/Decoding Configuration functions ********************************/
-HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
-HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
-HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
-HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
-HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group3
- * @{
- */
-/* JPEG processing functions **************************************/
-HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
-HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
-HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
-HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
-void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
-void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group4
- * @{
- */
-/* JPEG Decode/Encode callback functions ********************************************************/
-void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
-void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
-void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
-void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
-void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
-void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group5
- * @{
- */
-/* JPEG IRQ handler management ******************************************************/
-void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Exported_Functions_Group6
- * @{
- */
-/* Peripheral State and Error functions ************************************************/
-HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
-uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup JPEG_Private_Types JPEG Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup JPEG_Private_Defines JPEG Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup JPEG_Private_Variables JPEG Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup JPEG_Private_Constants JPEG Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup JPEG_Private_Macros JPEG Private Macros
- * @{
- */
-
-#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
- ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
- ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
-
-#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
-
-#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
- ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \
- ((COLORSPACE) == JPEG_CMYK_COLORSPACE))
-
-#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
- ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
- ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup JPEG_Private_Functions JPEG Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_JPEG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
deleted file mode 100644
index a63797c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
+++ /dev/null
@@ -1,710 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_lptim.h
- * @author MCD Application Team
- * @brief Header file of LPTIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_LPTIM_H
-#define __STM32H7xx_HAL_LPTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup LPTIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
- * @{
- */
-
-/**
- * @brief LPTIM Clock configuration definition
- */
-typedef struct
-{
- uint32_t Source; /*!< Selects the clock source.
- This parameter can be a value of @ref LPTIM_Clock_Source */
-
- uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
- This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
-}LPTIM_ClockConfigTypeDef;
-
-/**
- * @brief LPTIM Clock configuration definition
- */
-typedef struct
-{
- uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
- if the ULPTIM input is selected.
- Note: This parameter is used only when Ultra low power clock source is used.
- Note: If the polarity is configured on 'both edges', an auxiliary clock
- (one of the Low power oscillator) must be active.
- This parameter can be a value of @ref LPTIM_Clock_Polarity */
-
- uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
- Note: This parameter is used only when Ultra low power clock source is used.
- This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-
-}LPTIM_ULPClockConfigTypeDef;
-
-/**
- * @brief LPTIM Trigger configuration definition
- */
-typedef struct
-{
- uint32_t Source; /*!< Selects the Trigger source.
- This parameter can be a value of @ref LPTIM_Trigger_Source */
-
- uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
- Note: This parameter is used only when an external trigger is used.
- This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
-
- uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
- Note: This parameter is used only when an external trigger is used.
- This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
-}LPTIM_TriggerConfigTypeDef;
-
-/**
- * @brief LPTIM Initialization Structure definition
- */
-typedef struct
-{
- LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
-
- LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
-
- LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
-
- uint32_t OutputPolarity; /*!< Specifies the Output polarity.
- This parameter can be a value of @ref LPTIM_Output_Polarity */
-
- uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
- values is done immediately or after the end of current period.
- This parameter can be a value of @ref LPTIM_Updating_Mode */
-
- uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
- or each external event.
- This parameter can be a value of @ref LPTIM_Counter_Source */
-
- uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
- This parameter can be a value of @ref LPTIM_Input1_Source */
-
- uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
- Note: This parameter is used only for encoder feature so is used only
- for LPTIM1 instance.
- This parameter can be a value of @ref LPTIM_Input2_Source */
-
-}LPTIM_InitTypeDef;
-
-/**
- * @brief HAL LPTIM State structure definition
- */
-typedef enum __HAL_LPTIM_StateTypeDef
-{
- HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
-}HAL_LPTIM_StateTypeDef;
-
-/**
- * @brief LPTIM handle Structure definition
- */
-typedef struct
-{
- LPTIM_TypeDef *Instance; /*!< Register base address */
-
- LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
-
- HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
-
- HAL_LockTypeDef Lock; /*!< LPTIM locking object */
-
- __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
-
-}LPTIM_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
- * @{
- */
-
-/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
- * @{
- */
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
-#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
- * @{
- */
-#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
-#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
-#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
-#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
-#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
-#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
- * @{
- */
-
-#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
-#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
- * @{
- */
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
-#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
-#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
-#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
- * @{
- */
-
-#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
-#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
-#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
- * @{
- */
-#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
-#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
-#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
-#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
-#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
-#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
-#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
-/**
- * @}
- */
-
-/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
- * @{
- */
-#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
-#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
-#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
- * @{
- */
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
-#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
-#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
-#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
- * @{
- */
-
-#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
-#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
- * @{
- */
-
-#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
-#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
- * @{
- */
-
-#define LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000U) /*!< For LPTIM1, LPTIM2 and LPTIM3 */
-#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1_SEL0 /*!< For LPTIM1 and LPTIM2 */
-#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1_SEL1 /*!< For LPTIM2 and LPTIM2 */
-#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1) /*!< For LPTIM2 */
-#define LPTIM_INPUT1SOURCE_SAI1_FSA LPTIM_CFGR2_IN1_SEL0 /*!< For LPTIM3 */
-#define LPTIM_INPUT1SOURCE_SAI1_FSB LPTIM_CFGR2_IN1_SEL1 /*!< For LPTIM3 */
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
- * @{
- */
-
-#define LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000U) /*!< For LPTIM1 and LPTIM2 */
-#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2_SEL0 /*!< For LPTIM1 and LPTIM2 */
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
- * @{
- */
-
-#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
-#define LPTIM_FLAG_UP LPTIM_ISR_UP
-#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
-#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
-#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
-#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
-#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
- * @{
- */
-
-#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
-#define LPTIM_IT_UP LPTIM_IER_UPIE
-#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
-#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
-#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
-#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
-#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
- * @{
- */
-
-/** @brief Reset LPTIM handle state
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
-
-/**
- * @brief Enable the LPTIM peripheral.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
-
-/**
- * @brief Disable the LPTIM peripheral.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
-
-/**
- * @brief Start the LPTIM peripheral in Continuous mode.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
-/**
- * @brief Start the LPTIM peripheral in single mode.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
-
-/**
- * @brief Reset the LPTIM Counter register in synchronous mode.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
-
-/**
- * @brief Reset after read of the LPTIM Counter register in asynchronous mode.
- * @param __HANDLE__: LPTIM handle
- * @retval None
- */
-#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
-
-/**
- * @brief Write the passed parameter in the Autoreload register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Autoreload value
- * @retval None
- */
-#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
-
-/**
- * @brief Write the passed parameter in the Compare register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Compare value
- * @retval None
- */
-#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
-
-/**
- * @brief Check whether the specified LPTIM flag is set or not.
- * @param __HANDLE__: LPTIM handle
- * @param __FLAG__ : LPTIM flag to check
- * This parameter can be a value of:
- * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
- * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
- * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
- * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
- * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
- * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
- * @arg LPTIM_FLAG_CMPM : Compare match Flag.
- * @retval The state of the specified flag (SET or RESET).
- */
-#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the specified LPTIM flag.
- * @param __HANDLE__: LPTIM handle.
- * @param __FLAG__ : LPTIM flag to clear.
- * This parameter can be a value of:
- * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
- * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
- * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
- * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
- * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
- * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
- * @arg LPTIM_FLAG_CMPM : Compare match Flag.
- * @retval None.
- */
-#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
- * This parameter can be a value of:
- * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
- * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
- * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
- * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
- * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
- * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
- * @arg LPTIM_IT_CMPM : Compare match Interrupt.
- * @retval None.
- */
-#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
- /**
- * @brief Disable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
- * This parameter can be a value of:
- * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
- * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
- * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
- * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
- * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
- * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
- * @arg LPTIM_IT_CMPM : Compare match Interrupt.
- * @retval None.
- */
-#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-
- /**
- * @brief Check whether the specified LPTIM interrupt is set or not.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to check.
- * This parameter can be a value of:
- * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
- * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
- * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
- * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
- * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
- * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
- * @arg LPTIM_IT_CMPM : Compare match Interrupt.
- * @retval Interrupt status.
- */
-
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
- * @{
- */
-
-#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
- ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
-
-
-#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
-
-#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
-
-#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
- ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
-
-#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-
-#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
- ((__TRIG__) == LPTIM_TRIGSOURCE_7))
-
-#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
- ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
- ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
-
-#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
-
-#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
- ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
-
-#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
- ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
-
-#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
-
-#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
-
-#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
-
-#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
- || \
- (((__INSTANCE__) == LPTIM2) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
- || \
- (((__INSTANCE__) == LPTIM3) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))
-
-#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
- (((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)) \
- || \
- ((__INSTANCE__) == LPTIM2) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
-HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
-
-/* MSP functions *************************************************************/
-void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
-
-/* Start/Stop operation functions *********************************************/
-/* ################################# PWM Mode ################################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# One Pulse Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Set once Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################### Encoder Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# Time out Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Counter Mode ###############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* Reading operation functions ************************************************/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
-
-/* LPTIM IRQ functions *******************************************************/
-void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
-
-/* CallBack functions ********************************************************/
-void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
-
-/* Peripheral State functions ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
- * @{
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
deleted file mode 100644
index 7fdf9c5..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_ltdc.h
- * @author MCD Application Team
- * @brief Header file of LTDC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_LTDC_H
-#define __STM32H7xx_HAL_LTDC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup LTDC LTDC
- * @brief LTDC HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Types LTDC Exported Types
- * @{
- */
-#define MAX_LAYER 2U
-
-/**
- * @brief LTDC color structure definition
- */
-typedef struct
-{
- uint8_t Blue; /*!< Configures the blue value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Green; /*!< Configures the green value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Red; /*!< Configures the red value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Reserved; /*!< Reserved 0xFF */
-} LTDC_ColorTypeDef;
-
-/**
- * @brief LTDC Init structure definition
- */
-typedef struct
-{
- uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
- This parameter can be one value of @ref LTDC_HS_POLARITY */
-
- uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
- This parameter can be one value of @ref LTDC_VS_POLARITY */
-
- uint32_t DEPolarity; /*!< configures the data enable polarity.
- This parameter can be one of value of @ref LTDC_DE_POLARITY */
-
- uint32_t PCPolarity; /*!< configures the pixel clock polarity.
- This parameter can be one of value of @ref LTDC_PC_POLARITY */
-
- uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
- This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
-
- uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
- This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
-
- uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
-
- uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
-
- uint32_t TotalWidth; /*!< configures the total width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
-
- uint32_t TotalHeigh; /*!< configures the total height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
-
- LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
-} LTDC_InitTypeDef;
-
-/**
- * @brief LTDC Layer structure definition
- */
-typedef struct
-{
- uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
- uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
-
- uint32_t PixelFormat; /*!< Specifies the pixel format.
- This parameter can be one of value of @ref LTDC_Pixelformat */
-
- uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Alpha0; /*!< Configures the default alpha value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t BlendingFactor1; /*!< Select the blending factor 1.
- This parameter can be one of value of @ref LTDC_BlendingFactor1 */
-
- uint32_t BlendingFactor2; /*!< Select the blending factor 2.
- This parameter can be one of value of @ref LTDC_BlendingFactor2 */
-
- uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
-
- uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
-
- uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
- LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
-} LTDC_LayerCfgTypeDef;
-
-/**
- * @brief HAL LTDC State enumeration definition
- */
-typedef enum
-{
- HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
- HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
- HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
- HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
- HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
-}HAL_LTDC_StateTypeDef;
-
-/**
- * @brief LTDC handle Structure definition
- */
-typedef struct
-{
- LTDC_TypeDef *Instance; /*!< LTDC Register base address */
-
- LTDC_InitTypeDef Init; /*!< LTDC parameters */
-
- LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
-
- HAL_LockTypeDef Lock; /*!< LTDC Lock */
-
- __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
-
- __IO uint32_t ErrorCode; /*!< LTDC Error code */
-
-} LTDC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
- * @{
- */
-
-/** @defgroup LTDC_Error_Code LTDC Error Code
- * @{
- */
-#define HAL_LTDC_ERROR_NONE (0x00000000U) /*!< LTDC No error */
-#define HAL_LTDC_ERROR_TE (0x00000001U) /*!< LTDC Transfer error */
-#define HAL_LTDC_ERROR_FU (0x00000002U) /*!< LTDC FIFO Underrun */
-#define HAL_LTDC_ERROR_TIMEOUT (0x00000020U) /*!< LTDC Timeout error */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Layer LTDC Layer
- * @{
- */
-#define LTDC_LAYER_1 (0x00000000U) /*!< LTDC Layer 1 */
-#define LTDC_LAYER_2 (0x00000001U) /*!< LTDC Layer 2 */
-/**
- * @}
- */
-
-
-/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
- * @{
- */
-#define LTDC_HSPOLARITY_AL (0x00000000U) /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
- * @{
- */
-#define LTDC_VSPOLARITY_AL (0x00000000U) /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
- * @{
- */
-#define LTDC_DEPOLARITY_AL (0x00000000U) /*!< Data Enable, is active low. */
-#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
- * @{
- */
-#define LTDC_PCPOLARITY_IPC (0x00000000U) /*!< input pixel clock. */
-#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_SYNC LTDC SYNC
- * @{
- */
-#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
-#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
-/**
- * @}
- */
-
-/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
- * @{
- */
-#define LTDC_COLOR (0x000000FFU) /*!< Color mask */
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
- * @{
- */
-#define LTDC_BLENDING_FACTOR1_CA (0x00000400U) /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-/**
- * @}
- */
-
-/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
- * @{
- */
-#define LTDC_BLENDING_FACTOR2_CA (0x00000005U) /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
-/**
- * @}
- */
-
-/** @defgroup LTDC_Pixelformat LTDC Pixel format
- * @{
- */
-#define LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U) /*!< ARGB8888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB888 (0x00000001U) /*!< RGB888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB565 (0x00000002U) /*!< RGB565 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U) /*!< ARGB1555 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U) /*!< ARGB4444 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_L8 (0x00000005U) /*!< L8 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL44 (0x00000006U) /*!< AL44 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL88 (0x00000007U) /*!< AL88 LTDC pixel format */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Alpha LTDC Alpha
- * @{
- */
-#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
-/**
- * @}
- */
-
-/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
- * @{
- */
-#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
-#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
-
-#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
-#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
-/**
- * @}
- */
-
-/** @defgroup LTDC_Interrupts LTDC Interrupts
- * @{
- */
-#define LTDC_IT_LI LTDC_IER_LIE
-#define LTDC_IT_FU LTDC_IER_FUIE
-#define LTDC_IT_TE LTDC_IER_TERRIE
-#define LTDC_IT_RR LTDC_IER_RRIE
-/**
- * @}
- */
-
-/** @defgroup LTDC_Flags LTDC Flags
- * @{
- */
-#define LTDC_FLAG_LI LTDC_ISR_LIF
-#define LTDC_FLAG_FU LTDC_ISR_FUIF
-#define LTDC_FLAG_TE LTDC_ISR_TERRIF
-#define LTDC_FLAG_RR LTDC_ISR_RRIF
-/**
- * @}
- */
-
-/** @defgroup LTDC_Reload_Type LTDC Reload Type
- * @{
- */
-#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
-#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
- * @{
- */
-
-/** @brief Reset LTDC handle state.
- * @param __HANDLE__ LTDC handle
- * @retval None
- */
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
-
-/**
- * @brief Enable the LTDC.
- * @param __HANDLE__: LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
-
-/**
- * @brief Disable the LTDC.
- * @param __HANDLE__: LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
-
-/**
- * @brief Enable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be enabled.
- * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval None.
- */
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
-
-/**
- * @brief Disable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be disabled.
- * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval None.
- */
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
-
-/**
- * @brief Reload immediately all LTDC Layers.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
-
-/**
- * @brief Reload during vertical blanking period all LTDC Layers.
- * @param __HANDLE__ LTDC handle
- * @retval None.
- */
-#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
-
-/* Interrupt & Flag management */
-/**
- * @brief Get the LTDC pending flags.
- * @param __HANDLE__: LTDC handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
- * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-
-/**
- * @brief Clears the LTDC pending flags.
- * @param __HANDLE__: LTDC handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg LTDC_FLAG_LI: Line Interrupt flag
- * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
- * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enables the specified LTDC interrupts.
- * @param __HANDLE__: LTDC handle
- * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified LTDC interrupts.
- * @param __HANDLE__: LTDC handle
- * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval None
- */
-#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified LTDC interrupt has occurred or not.
- * @param __HANDLE__: LTDC handle
- * @param __INTERRUPT__: specifies the LTDC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg LTDC_IT_LI: Line Interrupt flag
- * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
- * @arg LTDC_IT_TE: Transfer Error interrupt flag
- * @arg LTDC_IT_RR: Register Reload Interrupt Flag
- * @retval The state of INTERRUPT (SET or RESET).
- */
-#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
-/**
- * @}
- */
-
-#if defined(DSI)
-/* Include LTDC HAL Extension module */
-#include "stm32h7xx_hal_ltdc_ex.h"
-
-#endif /*DSI*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup LTDC_Exported_Functions
- * @{
- */
-/** @addtogroup LTDC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
-void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
-void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
-HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
-HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup LTDC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
-uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LTDC_Private_Types LTDC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Variables LTDC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Constants LTDC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup LTDC_Private_Macros LTDC Private Macros
- * @{
- */
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
-#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
-#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
-#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
-#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
-#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
-#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
- ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
-#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__) (((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_CA) || \
- ((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_PAxCA))
-
-#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
-
-#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
-#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
-#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
-#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
-#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
-#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
-#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Functions LTDC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_LTDC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h
deleted file mode 100644
index 89b6673..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mdios.h
- * @author MCD Application Team
- * @brief Header file of MDIOS HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_MDIOS_H
-#define __STM32H7xx_HAL_MDIOS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MDIOS
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
- * @{
- */
-
-/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
- * @{
- */
-
-typedef enum
-{
- HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
- HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_MDIOS_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
- * @{
- */
-
-typedef struct
-{
- uint32_t PortAddress; /*!< Specifies the MDIOS port address.
- This parameter can be a value from 0 to 31 */
- uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
- This parameter can be a value of @ref MDIOS_Preamble_Check */
-}MDIOS_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
- * @{
- */
-
-typedef struct
-{
- MDIOS_TypeDef *Instance; /*!< Register base address */
-
- MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
-
- __IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
-
- HAL_LockTypeDef Lock; /*!< MDIOS Lock */
-}MDIOS_HandleTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
- * @{
- */
-
-/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check
- * @{
- */
-#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
-#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
- * @{
- */
-#define MDIOS_REG0 ((uint32_t)0x00000000U)
-#define MDIOS_REG1 ((uint32_t)0x00000001U)
-#define MDIOS_REG2 ((uint32_t)0x00000002U)
-#define MDIOS_REG3 ((uint32_t)0x00000003U)
-#define MDIOS_REG4 ((uint32_t)0x00000004U)
-#define MDIOS_REG5 ((uint32_t)0x00000005U)
-#define MDIOS_REG6 ((uint32_t)0x00000006U)
-#define MDIOS_REG7 ((uint32_t)0x00000007U)
-#define MDIOS_REG8 ((uint32_t)0x00000008U)
-#define MDIOS_REG9 ((uint32_t)0x00000009U)
-#define MDIOS_REG10 ((uint32_t)0x0000000AU)
-#define MDIOS_REG11 ((uint32_t)0x0000000BU)
-#define MDIOS_REG12 ((uint32_t)0x0000000CU)
-#define MDIOS_REG13 ((uint32_t)0x0000000DU)
-#define MDIOS_REG14 ((uint32_t)0x0000000EU)
-#define MDIOS_REG15 ((uint32_t)0x0000000FU)
-#define MDIOS_REG16 ((uint32_t)0x00000010U)
-#define MDIOS_REG17 ((uint32_t)0x00000011U)
-#define MDIOS_REG18 ((uint32_t)0x00000012U)
-#define MDIOS_REG19 ((uint32_t)0x00000013U)
-#define MDIOS_REG20 ((uint32_t)0x00000014U)
-#define MDIOS_REG21 ((uint32_t)0x00000015U)
-#define MDIOS_REG22 ((uint32_t)0x00000016U)
-#define MDIOS_REG23 ((uint32_t)0x00000017U)
-#define MDIOS_REG24 ((uint32_t)0x00000018U)
-#define MDIOS_REG25 ((uint32_t)0x00000019U)
-#define MDIOS_REG26 ((uint32_t)0x0000001AU)
-#define MDIOS_REG27 ((uint32_t)0x0000001BU)
-#define MDIOS_REG28 ((uint32_t)0x0000001CU)
-#define MDIOS_REG29 ((uint32_t)0x0000001DU)
-#define MDIOS_REG30 ((uint32_t)0x0000001EU)
-#define MDIOS_REG31 ((uint32_t)0x0000001FU)
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
- * @{
- */
-#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
-#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
-#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
-#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
-#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
-#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
-#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
-#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
-#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
-#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
-#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
-#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
-#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
-#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
-#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
-#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
-#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
-#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
-#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
-#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
-#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
-#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
-#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
-#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
-#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
-#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
-#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
-#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
-#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
-#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
-#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
-#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
-#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
- * @{
- */
-#define MDIOS_IT_WRITE MDIOS_CR_WRIE
-#define MDIOS_IT_READ MDIOS_CR_RDIE
-#define MDIOS_IT_ERROR MDIOS_CR_EIE
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags
- * @{
- */
-#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
-#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
-#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
-/**
- * @}
- */
-
- /** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line
- * @{
- */
-#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
- * @{
- */
-
-/** @brief Reset MDIOS handle state
- * @param __HANDLE__: MDIOS handle.
- * @retval None
- */
-#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
-
-/**
- * @brief Enable/Disable the MDIOS peripheral.
- * @param __HANDLE__: specifies the MDIOS handle.
- * @retval None
- */
-#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
-#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
-
-
-/**
- * @brief Enable the MDIOS device interrupt.
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg MDIOS_IT_WRITE: Register write interrupt
- * @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
- * @retval None
- */
-#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the MDIOS device interrupt.
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg MDIOS_IT_WRITE: Register write interrupt
- * @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
- * @retval None
- */
-#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/** @brief Set MDIOS slave get write register flag
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __FLAG__: specifies the write register flag
- * @retval The state of write flag
- */
-#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
-
-/** @brief MDIOS slave get read register flag
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __FLAG__: specifies the read register flag
- * @retval The state of read flag
- */
-#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
-
-/** @brief MDIOS slave get interrupt
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __FLAG__ : specifies the Error flag.
- * This parameter can be one or a combination of the following values:
- * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
- * @arg MDIOS_START_ERROR_FLAG: Register read interrupt
- * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
- * @retval The state of the error flag
- */
-#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
-
-/** @brief MDIOS slave clear interrupt
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __FLAG__ : specifies the Error flag.
- * This parameter can be one or a combination of the following values:
- * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
- * @arg MDIOS_START_ERROR_FLAG: Register read interrupt
- * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
- * @retval none
- */
-#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
-
-/**
- * @brief Checks whether the specified MDIOS interrupt is set or not.
- * @param __HANDLE__: specifies the MDIOS handle.
- * @param __INTERRUPT__ : specifies the MDIOS interrupt sources
- * This parameter can be one or a combination of the following values:
- * @arg MDIOS_IT_WRITE: Register write interrupt
- * @arg MDIOS_IT_READ: Register read interrupt
- * @arg MDIOS_IT_ERROR: Error interrupt
- * @retval The state of the interrupt source
- */
-#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
-
-/**
- * @brief Enable the MDIOS WAKEUP Exti Line.
- * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
- * This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
- * @retval None.
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR2 |= (__EXTI_LINE__))
-
-/**
- * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
- * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
- * This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
- * @retval EXTI MDIOS WAKEUP Line Status.
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 & (__EXTI_LINE__))
-
-/**
- * @brief Clear the MDIOS WAKEUP Exti flag.
- * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
- * This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
- * @retval None.
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
-
-/**
- * @brief enable rising edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * This parameter can be:
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
- (EXTI->RTSR2 |= (__EXTI_LINE__))
-
-/**
- * @brief enable falling edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * This parameter can be:
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
- (EXTI->FTSR2 |= (__EXTI_LINE__))
-
-/**
- * @brief enable falling edge interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
- * This parameter can be:
- * @arg ETH_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
- (EXTI->FTSR2 |= (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
- * This parameter can be:
- * @arg MDIOS_WAKEUP_EXTI_LINE
- * @retval None
- */
-#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
- * @{
- */
-
-/** @addtogroup MDIOS_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
-HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
-/**
- * @}
- */
-
-/** @addtogroup MDIOS_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data);
-HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData);
-
-uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
-uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
-HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
-HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
-
-HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
-void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
-/**
- * @}
- */
-
-/** @addtogroup MDIOS_Exported_Functions_Group3
- * @{
- */
-uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
-HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MDIOS_Private_Types MDIOS Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
- * @{
- */
-
-#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
-
-#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
-
-#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
- ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
-
- /**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_MDIOS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
deleted file mode 100644
index 12125b7..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mdma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_MDMA_H
-#define __STM32H7xx_HAL_MDMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MDMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup MDMA_Exported_Types MDMA Exported Types
- * @brief MDMA Exported Types
- * @{
- */
-
-/**
- * @brief MDMA Configuration Structure definition
- */
-typedef struct
-{
-
- uint32_t Request; /*!< Specifies the MDMA request.
- This parameter can be a value of @ref MDMA_Request_selection*/
-
- uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a :
- a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
- This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
-
- uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx.
- This parameter can be a value of @ref MDMA_Priority_level */
-
- uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness.
- This parameter can be a value of @ref MDMA_Endianness */
-
- uint32_t SourceInc; /*!< Specifies if the Source increment mode .
- This parameter can be a value of @ref MDMA_Source_increment_mode */
-
- uint32_t DestinationInc; /*!< Specifies if the Destination increment mode .
- This parameter can be a value of @ref MDMA_Destination_increment_mode */
-
- uint32_t SourceDataSize; /*!< Specifies the source data size.
- This parameter can be a value of @ref MDMA_Source_data_size */
-
- uint32_t DestDataSize; /*!< Specifies the destination data size.
- This parameter can be a value of @ref MDMA_Destination_data_size */
-
-
- uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode.
- This parameter can be a value of @ref MDMA_data_Alignment */
-
- uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes),
- this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
-
- uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction.
- This parameter can be a value of @ref MDMA_Source_burst
- @note : the burst may be FIXED/INCR based on SourceInc value ,
- the BURST must be programmed as to ensure that the burst size will be lower than than
- BufferTransferLength */
-
- uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
- transaction.
- This parameter can be a value of @ref MDMA_Destination_burst
- @note : the burst may be FIXED/INCR based on DestinationInc value ,
- the BURST must be programmed as to ensure that the burst size will be lower than than
- BufferTransferLength */
-
- int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset
- signed value : if > 0 then increment the next block source Address by offset from where the last block ends
- if < 0 then decrement the next block source Address by offset from where the last block ends
- if == 0, the next block source address starts from where the last block ends
- */
-
-
- int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset
- signed value : if > 0 then increment the next block destination Address by offset from where the last block ends
- if < 0 then decrement the next block destination Address by offset from where the last block ends
- if == 0, the next block destination address starts from where the last block ends
- */
-
-}MDMA_InitTypeDef;
-
-/**
- * @brief HAL MDMA linked list node structure definition
- * @note The Linked list node allows to define a new MDMA configuration
- * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
- * When CLAR register is configured to a non NULL value , each time a transfer ends,
- * a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
- */
-typedef struct
-{
- __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
- __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
- __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
- __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
- __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
- __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
- __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
- __IO uint32_t Reserved; /*!< Reserved register*/
- __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
- __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
-
-}MDMA_LinkNodeTypeDef;
-
-/**
- * @brief HAL MDMA linked list node configuration structure definition
- * @note used with HAL_MDMA_LinkedList_CreateNode function
- */
-typedef struct
-{
- MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */
- uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */
- uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */
- uint32_t BlockDataLength; /*!< The length of a block transfer in bytes */
- uint32_t BlockCount; /*!< The number of a blocks to be transfer */
-
- uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
- PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
-
- uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
- PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
-
-
-}MDMA_LinkNodeConfTypeDef;
-
-
-/**
- * @brief HAL MDMA State structure definition
- */
-typedef enum
-{
- HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */
- HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */
- HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */
- HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */
- HAL_MDMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
-
-}HAL_MDMA_StateTypeDef;
-
-/**
- * @brief HAL MDMA Level Complete structure definition
- */
-typedef enum
-{
- HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */
- HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */
- HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */
-
-}HAL_MDMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL MDMA Callbacks IDs structure definition
- */
-typedef enum
-{
- HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */
- HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */
- HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */
- HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
- HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
- HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */
-
-}HAL_MDMA_CallbackIDTypeDef;
-
-
-/**
- * @brief MDMA handle Structure definition
- */
-typedef struct __MDMA_HandleTypeDef
-{
- MDMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- MDMA_InitTypeDef Init; /*!< MDMA communication parameters */
-
-
- HAL_LockTypeDef Lock; /*!< MDMA locking object */
-
- __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */
-
- void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */
-
- void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */
-
- void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */
-
- void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */
-
- void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
-
-
- MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
- (after the initial node defined by the Init struct)
- this parameter is used internally by the MDMA driver
- to construct the liked list node
- */
-
- MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list
- this parameter is used internally by the MDMA driver
- to construct the liked list node
- */
- uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
-
- __IO uint32_t ErrorCode; /*!< MDMA Error code */
-
-} MDMA_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
- * @brief MDMA Exported constants
- * @{
- */
-
-/** @defgroup MDMA_Error_Codes MDMA Error Codes
- * @brief MDMA Error Codes
- * @{
- */
-#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */
-#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */
-#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */
-#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */
-#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */
-#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */
-#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
-#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
-#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Request_selection MDMA Request selection
- * @brief MDMA_Request_selection
- * @{
- */
-
-#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */
-#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */
-#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */
-#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */
-#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */
-#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */
-#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */
-#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */
-#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */
-#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */
-#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */
-
-#if defined(DSI)
-#define MDMA_REQUEST_DSI_TEARINGE_FFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */
-#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */
-#endif /* DSI */
-
-#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */
-
-#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode
- * @brief MDMA Transfer Trigger Mode
- * @{
- */
-#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
-#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
-#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
-#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Priority_level MDMA Priority level
- * @brief MDMA Priority level
- * @{
- */
-#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
-#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */
-#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */
-#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */
-
-/**
- * @}
- */
-
-
-/** @defgroup MDMA_Endianness MDMA Endianness
- * @brief MDMA Endianness
- * @{
- */
-#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
-#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
-#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/
-#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
- * @brief MDMA Source increment mode
- * @{
- */
-#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
-#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
-#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
-#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
- * @brief MDMA Destination increment mode
- * @{
- */
-#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
-#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
-#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
-#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Source_data_size MDMA Source data size
- * @brief MDMA Source data size
- * @{
- */
-#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
-#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
-#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
-#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Destination_data_size MDMA Destination data size
- * @brief MDMA Destination data size
- * @{
- */
-#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
-#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
-#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
-#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_data_Alignment MDMA data alignment
- * @brief MDMA MDMA data alignment
- * @{
- */
-#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
- All data are right aligned, in Little Endien mode. */
-#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
-#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
- Note : this mode is allowed only if the Source data size smaller than Destination data size */
-#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Source_burst MDMA Source burst
- * @brief MDMA Source burst
- * @{
- */
-#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
-#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
-#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
-#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
-#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
-#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
-#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
-#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_Destination_burst MDMA Destination burst
- * @brief MDMA Destination burst
- * @{
- */
-#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
-#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
-#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
-#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
-#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
-#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
-#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
-#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
- * @brief MDMA interrupt enable definitions
- * @{
- */
-#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
-#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
-#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
-#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
-#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup MDMA_flag_definitions MDMA flag definitions
- * @brief MDMA flag definitions
- * @{
- */
-#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
-#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
-#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
-#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
-#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
-#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the specified MDMA Channel.
- * @param __HANDLE__: MDMA handle
- * @retval None
- */
-#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__: MDMA handle
- * @retval None
- */
-#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
-
-/**
- * @brief Get the MDMA Channel pending flags.
- * @param __HANDLE__: MDMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg MDMA_FLAG_TE : Transfer Error flag.
- * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
- * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
- * @arg MDMA_FLAG_BT : Block Transfer complete flag.
- * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
- * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
-
-/**
- * @brief Clear the MDMA Stream pending flags.
- * @param __HANDLE__: MDMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg MDMA_FLAG_TE : Transfer Error flag.
- * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
- * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
- * @arg MDMA_FLAG_BT : Block Transfer complete flag.
- * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
- * @retval None
- */
-#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
-
-/**
- * @brief Enables the specified DMA Channel interrupts.
- * @param __HANDLE__: MDMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg MDMA_IT_TE : Transfer Error interrupt mask
- * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
- * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
- * @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
- * @retval None
- */
-#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified MDMA Channel interrupts.
- * @param __HANDLE__: MDMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg MDMA_IT_TE : Transfer Error interrupt mask
- * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
- * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
- * @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
- * @retval None
- */
-#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
- * @arg MDMA_IT_TE : Transfer Error interrupt mask
- * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
- * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
- * @arg MDMA_IT_BT : Block Transfer interrupt mask
- * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
- * @retval The state of MDMA_IT (SET or RESET).
- */
-#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MDMA_Exported_Functions MDMA Exported Functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
-
-HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
-HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/* Linked list operation functions ********************************************/
-/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
- * @brief Linked list operation functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
-HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
-HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
-HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
-
-
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
- * @brief I/O operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
-HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
-HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
-void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
-
-/**
- * @}
- */
-
-/* Peripheral State and Error functions ***************************************/
-/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
-uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MDMA_Private_Types MDMA Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup MDMA_Private_Defines MDMA Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MDMA_Private_Variables MDMA Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MDMA_Private_Constants MDMA Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MDMA_Private_Macros MDMA Private Macros
- * @{
- */
-
-#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \
- ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
- ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
- ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
-
-
-#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
- ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
- ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
- ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
-
-#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
- ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
- ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
- ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
-
-
-#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
-
-#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \
- ((__INC__) == MDMA_SRC_INC_BYTE ) || \
- ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \
- ((__INC__) == MDMA_SRC_INC_WORD ) || \
- ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
- ((__INC__) == MDMA_SRC_DEC_BYTE) || \
- ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \
- ((__INC__) == MDMA_SRC_DEC_WORD) || \
- ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
-
-#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \
- ((__INC__) == MDMA_DEST_INC_BYTE ) || \
- ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \
- ((__INC__) == MDMA_DEST_INC_WORD ) || \
- ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
- ((__INC__) == MDMA_DEST_DEC_BYTE) || \
- ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \
- ((__INC__) == MDMA_DEST_DEC_WORD) || \
- ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
-
-#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \
- ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
- ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \
- ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
-
-#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \
- ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
- ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \
- ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
-
-#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
- ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
-
-
-#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
- ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
- ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
- ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \
- ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
- ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
- ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
- ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
-
-
-#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
- ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
- ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
- ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \
- ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
- ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
- ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
- ((__BURST__) == MDMA_DEST_BURST_128BEATS))
-
- #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
- ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
- ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
- ((__MODE__) == MDMA_FULL_TRANSFER))
-
-#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
-
-#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
-
-#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
-
-#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MDMA_Private_Functions MDMA Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_MDMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h
deleted file mode 100644
index fc9c410..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h
+++ /dev/null
@@ -1,771 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mmc.h
- * @author MCD Application Team
- * @brief Header file of MMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_MMC_H
-#define STM32H7xx_HAL_MMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_sdmmc.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_Types MMC Exported Types
- * @{
- */
-
-/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
- HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
- HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
- HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
- HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
- HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
- HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
- * @{
- */
-#define MMC_InitTypeDef SDMMC_InitTypeDef
-#define MMC_TypeDef SDMMC_TypeDef
-
-/**
- * @brief MMC Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_MMC_CardInfoTypeDef;
-
-/**
- * @brief MMC handle Structure definition
- */
-typedef struct __MMC_HandleTypeDef
-{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
-
- MMC_InitTypeDef Init; /*!< MMC required parameters */
-
- HAL_LockTypeDef Lock; /*!< MMC locking object */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< MMC Tx Transfer size */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< MMC Rx Transfer size */
-
- __IO uint32_t Context; /*!< MMC transfer context */
-
- __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
-
- __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
-
- HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
- uint32_t CSD[4]; /*!< MMC card specific data table */
-
- uint32_t CID[4]; /*!< MMC card identification number table */
-
- uint32_t Ext_CSD[128];
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
-
- void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
-#endif
-}MMC_HandleTypeDef;
-
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGroup; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_MMC_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_MMC_CardCIDTypeDef;
-/**
- * @}
- */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
- HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
- HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
- HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
- HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */
- HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */
- HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */
- HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */
-
- HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
- HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
-}HAL_MMC_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
- * @{
- */
-typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-#endif
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Constants Exported Constants
- * @{
- */
-
-#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
-
-/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
- * @{
- */
-#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
- * @{
- */
-#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
- * @{
- */
-/**
- * @brief
- */
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
-#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
- * @{
- */
-#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */
-#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset MMC handle state.
- * @param __HANDLE__ : MMC handle.
- * @retval None
- */
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
-#endif
-
-/**
- * @brief Enable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
- * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
- * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval The new state of MMC FLAG (SET or RESET).
- */
-#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the MMC's pending flags.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval None
- */
-#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
- * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval The new state of MMC IT (SET or RESET).
- */
-#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Include MMC HAL Extension module */
-#include "stm32h7xx_hal_mmc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Functions MMC Exported Functions
- * @{
- */
-
-/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/* MMC callback registering/unregistering */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
- * @{
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MMC_Private_Types MMC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup MMC_Private_Defines MMC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Variables MMC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Constants MMC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MMC_Private_Macros MMC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32H7xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h
deleted file mode 100644
index fc9805c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mmc_ex.h
- * @author MCD Application Team
- * @brief Header file of SD HAL extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_MMC_EX_H
-#define STM32H7xx_HAL_MMC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup MMC_EX MMC_EX
- * @brief SD HAL extended module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
- * @{
- */
-
-/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
- * @{
- */
-typedef enum
-{
- MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
- MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */
-
-}HAL_MMCEx_DMABuffer_MemoryTypeDef;
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
- * @{
- */
-
-/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
-
-void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32H7xx_HAL_MMCEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h
deleted file mode 100644
index 1e1a531..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_nand.h
- * @author MCD Application Team
- * @brief Header file of NAND HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_NAND_H
-#define __STM32H7xx_HAL_NAND_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_fmc.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NAND
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
- * @{
- */
-
-/**
- * @brief HAL NAND State structures definition
- */
-typedef enum
-{
- HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
- * @brief NAND Memory electronic signature Structure definition
- */
-typedef struct
-{
- /*State = HAL_NAND_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* IO operation functions ****************************************************/
-
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-#define NAND_DEVICE ((uint32_t)0x80000000U)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
-
-#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
-#define NAND_CMD_READID ((uint8_t)0x90U)
-#define NAND_CMD_STATUS ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
-#define NAND_CMD_RESET ((uint8_t)0xFFU)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
-#define NAND_BUSY ((uint32_t)0x00000000U)
-#define NAND_ERROR ((uint32_t)0x00000001U)
-#define NAND_READY ((uint32_t)0x00000040U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__: NAND memory address.
- * @param __HANDLE__ : NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
-
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__: NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/**
- * @brief NAND memory Columns cycling.
- * @param __ADDRESS__: NAND memory address.
- * @retval NAND Column address cycling value.
- */
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h
deleted file mode 100644
index 8c9a975..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_nor.h
- * @author MCD Application Team
- * @brief Header file of NOR HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_NOR_H
-#define __STM32H7xx_HAL_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_fmc.h"
-
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NOR
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup NOR_Exported_Types NOR Exported Types
- * @{
- */
-
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
-}HAL_NOR_StateTypeDef;
-
-/**
- * @brief FMC NOR Status typedef
- */
-typedef enum
-{
- HAL_NOR_STATUS_SUCCESS = 0U,
- HAL_NOR_STATUS_ONGOING,
- HAL_NOR_STATUS_ERROR,
- HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef;
-
-/**
- * @brief FMC NOR ID typedef
- */
-typedef struct
-{
- uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory. */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
- These codes can be accessed by performing read operations with specific
- control signals and addresses set.They can also be accessed by issuing
- an Auto Select command. */
-}NOR_IDTypeDef;
-
-/**
- * @brief FMC NOR CFI typedef
- */
-typedef struct
-{
- /*!< Defines the information stored in the memory's Common flash interface
- which contains a description of various electrical and timing parameters,
- density information and functions supported by the memory */
-
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4;
-}NOR_CFITypeDef;
-
-/**
- * @brief NOR handle Structure definition
- */
-typedef struct
-{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
- __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
-}NOR_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup NOR_Exported_Macros NOR Exported Macros
- * @{
- */
-/** @brief Reset NOR handle state
- * @param __HANDLE__: specifies the NOR handle.
- * @retval None
- */
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
- * @{
- */
-
-/* NOR Control functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
- * @{
- */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
- * @{
- */
-/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x61U)
-#define CFI2_ADDRESS ((uint16_t)0x62U)
-#define CFI3_ADDRESS ((uint16_t)0x63U)
-#define CFI4_ADDRESS ((uint16_t)0x64U)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT ((uint16_t)0xFFFFU)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0U)
-#define NOR_MEMORY_16B ((uint8_t)0x1U)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
-#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
-#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
-#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Macros NOR Private Macros
- * @{
- */
-/**
- * @brief NOR memory address shifting.
- * @param __NOR_ADDRESS: NOR base address
- * @param __NOR_MEMORY_WIDTH_: NOR memory width
- * @param __ADDRESS__: NOR memory address
- * @retval NOR shifted address value
- */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
- ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
- * @brief NOR memory write data to specified address.
- * @param __ADDRESS__: NOR memory address
- * @param __DATA__: Data to write
- * @retval None
- */
-#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
- (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
- __DSB(); \
- } while(0)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h
deleted file mode 100644
index 68ee184..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_opamp.h
- * @author MCD Application Team
- * @brief Header file of OPAMP HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_OPAMP_H
-#define __STM32H7xx_HAL_OPAMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup OPAMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
- * @{
- */
-
-/**
- * @brief OPAMP Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t PowerMode; /*!< Specifies the power mode Normal or High Speed.
- This parameter must be a value of @ref OPAMP_PowerMode */
-
- uint32_t Mode; /*!< Specifies the OPAMP mode
- This parameter must be a value of @ref OPAMP_Mode
- mode is either Standalone, - Follower or PGA */
-
- uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & PGA modes
- - In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE
- This parameter must be a value of @ref OPAMP_InvertingInput
- - In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
- & In PGA mode i.e when mode is OPAMP_PGA_MODE
- This parameter is Not Applicable */
-
- uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
- This parameter must be a value of @ref OPAMP_NonInvertingInput */
-
- uint32_t PgaGain; /*!< Specifies the gain in PGA mode
- i.e. when mode is OPAMP_PGA_MODE.
- This parameter must be a value of @ref OPAMP_PgaGain */
-
- uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
- i.e. when mode is OPAMP_PGA_MODE
- This parameter must be a value of @ref OPAMP_PgaConnect
- Either: not connected, connected to VINM0, connected to VINM1
- (VINM0 or VINM1 are typically used for external filtering) */
-
- uint32_t UserTrimming; /*!< Specifies the trimming mode
- This parameter must be a value of @ref OPAMP_UserTrimming
- UserTrimming is either factory or user trimming.*/
-
- uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) in Normal Mode
-
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 0 and Max_Data = 31.
- 16 is typical default value */
-
- uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) in Normal Mode
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 0 and Max_Data = 31.
- 16 is typical default value */
-
- uint32_t TrimmingValuePHighSpeed; /*!< Specifies the offset trimming value (PMOS) in High Speed Mode
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 0 and Max_Data = 31.
- 16 is typical default value */
-
- uint32_t TrimmingValueNHighSpeed; /*!< Specifies the offset trimming value (NMOS) in High Speed Mode
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 0 and Max_Data = 31.
- 16 is typical default value */
-
-}OPAMP_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-
-typedef enum
-{
- HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPAMP is not yet Initialized */
-
- HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
- HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
-
- HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
- HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005 /*!< OPAMP is locked
- only system reset allows reconfiguring the opamp. */
-
-}HAL_OPAMP_StateTypeDef;
-
-/**
- * @brief OPAMP Handle Structure definition
- */
-typedef struct
-{
- OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
- OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
- HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
-
-} OPAMP_HandleTypeDef;
-
-/**
- * @brief HAl_OPAMP_TrimmingValueTypeDef definition
- */
-
-typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
- * @{
- */
-
-/** @defgroup OPAMP_Mode OPAMP Mode
- * @{
- */
-#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */
-#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
-#define OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< follower mode */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP non-inverting input connected to dedicated IO pin */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0 /*!< OPAMP non-inverting input connected internally to DAC channel */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
- * @{
- */
-
-#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP inverting input connected to dedicated IO pin */
-#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to dedicated IO pin */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
- * @{
- */
-
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the inverting input is not connected */
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2 /*!< In PGA mode, the inverting input is connected to VINM0 */
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the inverting input is connected to VINM0 or bias */
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering */
-
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
- * @{
- */
-
-#define OPAMP_PGA_GAIN_2_OR_MINUS_1 ((uint32_t)0x00000000) /*!< PGA gain could be 2 or -1 */
-#define OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0 /*!< PGA gain could be 4 or -3 */
-#define OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1 /*!< PGA gain could be 8 or -7 */
-#define OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain could be 16 or -15 */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PowerMode OPAMP PowerMode
- * @{
- */
-#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
-#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_VREF OPAMP VREF
- * @{
- */
-
-#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPAMP Vref = 3.3% VDDA */
-#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPAMP Vref = 10% VDDA */
-#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPAMP Vref = 50% VDDA */
-#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPAMP Vref = 90% VDDA */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
- * @{
- */
-#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
-#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
-
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
- * @{
- */
-#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */
-
-#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
-#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
- * @brief OPAMP Private constants and defines
- * @{
- */
-
-/* NONINVERTING bit position in OTR & HSOTR */
-#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */
-
-/* Offset trimming time: during calibration, minimum time needed between two */
-/* steps to have 1 mV accuracy. */
-/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=2ms.*/
-/* Unit: ms. */
-#define OPAMP_TRIMMING_DELAY ((uint32_t) 2)
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
- * @{
- */
-
-/** @brief Reset OPAMP handle state.
- * @param __HANDLE__: OPAMP handle.
- * @retval None
- */
-#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
- * @{
- */
-
-#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
- ((INPUT) == OPAMP_PGA_MODE) || \
- ((INPUT) == OPAMP_FOLLOWER_MODE))
-
-#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
-
-
-#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
-
-#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
- ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
- ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
- ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
-
-#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
- ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
- ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
- ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))
-
-
-#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
- ((VREF) == OPAMP_VREF_10VDDA) || \
- ((VREF) == OPAMP_VREF_50VDDA) || \
- ((VREF) == OPAMP_VREF_90VDDA))
-
-#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
- ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )
-
-
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
- ((TRIMMING) == OPAMP_TRIMMING_USER))
-
-
-#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
-
-#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
- ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
-
-/**
- * @}
- */
-
-/* Include OPAMP HAL Extended module */
-#include "stm32h7xx_hal_opamp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMP_Exported_Functions
- * @{
- */
-
-/** @addtogroup OPAMP_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
-/**
- * @}
- */
-
-/** @addtogroup OPAMP_Exported_Functions_Group2
- * @{
- */
-
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
-
-/**
- * @}
- */
-
-/** @addtogroup OPAMP_Exported_Functions_Group3
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
-HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
-
-/**
- * @}
- */
-
-/** @addtogroup OPAMP_Exported_Functions_Group4
- * @{
- */
-
-/* Peripheral State functions **************************************************/
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h
deleted file mode 100644
index ff28e82..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_opamp_ex.h
- * @author MCD Application Team
- * @brief Header file of OPAMP HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_OPAMP_EX_H
-#define __STM32H7xx_HAL_OPAMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup OPAMPEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
- * @{
- */
-
-/* Extended IO operation functions *****************************************************/
-/** @addtogroup OPAMPEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
-
-/**
- * @}
- */
-/* Peripheral Control functions ************************************************/
-/** @addtogroup OPAMPEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_OPAMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
deleted file mode 100644
index 78b14d8..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pcd.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_PCD_H
-#define __STM32H7xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_usb.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
- * @{
- */
-
-/**
- * @brief PCD State structure definition
- */
-typedef enum
-{
- HAL_PCD_STATE_RESET = 0x00U,
- HAL_PCD_STATE_READY = 0x01U,
- HAL_PCD_STATE_ERROR = 0x02U,
- HAL_PCD_STATE_BUSY = 0x03U,
- HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum
-{
- LPM_L0 = 0x00U, /* on */
- LPM_L1 = 0x01U, /* LPM L1 sleep */
- LPM_L2 = 0x02U, /* suspend */
- LPM_L3 = 0x03U, /* off */
-}PCD_LPM_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
-
-/**
- * @brief PCD Handle Structure definition
- */
-typedef struct
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
- uint32_t BESL;
- uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
- uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
-
- void *pData; /*!< Pointer to upper stack Handler */
-} PCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Include PCD HAL Extension module */
-#include "stm32h7xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup PCD_Speed PCD Speed
- * @{
- */
-#define PCD_SPEED_HIGH 0U
-#define PCD_SPEED_HIGH_IN_FULL 1U
-#define PCD_SPEED_FULL 2U
-/**
- * @}
- */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
- * @{
- */
-#define PCD_PHY_ULPI 1U
-#define PCD_PHY_EMBEDDED 2U
-/**
- * @}
- */
-
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
- * @{
- */
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE 9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE 5U
-#endif /* USBD_HS_TRDT_VALUE */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
-
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
-
-#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM43) /*!< External interrupt line 43 Connected to the USB HS EXTI Line */
-
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM44) /*!< External interrupt line 44 Connected to the USB FS EXTI Line */
-
-
-/* HS */
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
- EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-
-
-
-/* FS */
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-/** @defgroup PCD_Instance_definition PCD Instance definition
- * @{
- */
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS) || \
- ((INSTANCE) == USB2_OTG_FS))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
deleted file mode 100644
index 22ad7fc..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pcd_ex.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_PCD_EX_H
-#define __STM32H7xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCDEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-typedef enum
-{
- PCD_LPM_L0_ACTIVE = 0x00U, /* on */
- PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-
-
-typedef enum
-{
- PCD_BCD_ERROR = 0xFF,
- PCD_BCD_CONTACT_DETECTION = 0xFE,
- PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
- PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
- PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
- PCD_BCD_DISCOVERY_COMPLETED = 0x00,
-
-}PCD_BCD_MsgTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
deleted file mode 100644
index 2072ca9..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
+++ /dev/null
@@ -1,469 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_PWR_H
-#define __STM32H7xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref PWR_PVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
-#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
-#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
-#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
-#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
-#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
-#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
-#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
- * @{
- */
-#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
-#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
-#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag PWR Flag
- * @{
- */
-#define PWR_FLAG_STOP ((uint8_t)0x01U)
-#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
-#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
-#define PWR_FLAG_SB ((uint8_t)0x04U)
-#define PWR_FLAG_PVDO ((uint8_t)0x07U)
-#define PWR_FLAG_AVDO ((uint8_t)0x08U)
-#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x09U)
-#define PWR_FLAG_ACTVOS ((uint8_t)0x0AU)
-#define PWR_FLAG_BRR ((uint8_t)0x0BU)
-#define PWR_FLAG_VOSRDY ((uint8_t)0x0CU)
-#if defined(SMPS)
-#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x0DU)
-#else
-#define PWR_FLAG_SCUEN ((uint8_t)0x0DU)
-#endif /* SMPS */
-/**
- * @}
- */
-
-/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
- * @{
- */
-#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
- * @{
- */
-
-/** @brief macros configure the main internal regulator output voltage.
- * @param __REGULATOR__: specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption when the device does
- * not operate at the maximum frequency (refer to the datasheets for more details).
- * This parameter can be one of the following values:
- * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
- * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
- * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
- * @retval None
- */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
-do { \
- __IO uint32_t tmpreg = 0x00; \
- MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
- UNUSED(tmpreg); \
-} while(0)
-
-/** @brief Check PWR PVD/AVD and VOSflags are set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
- * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the AVDE bit is set.
- * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
- * scaling output selection is ready.
- * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
- * scaling output selection is ready.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @arg PWR_FLAG_SB: StandBy flag
- * @arg PWR_FLAG_STOP: STOP flag
- * @arg PWR_FLAG_SB_D1: StandBy D1 flag
- * @arg PWR_FLAG_SB_D2: StandBy D2 flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
-((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
-((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
-((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
-((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
-((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
-((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
-((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
-((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
-((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
-((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
-
-
-/** @brief Clear the PWR's flags.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_SB: StandBy flag.
- * @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
- * @retval None.
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
-
-/**
- * @brief Enable the PVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Enable event on PVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable event on PVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
-do { \
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
-} while(0);
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
-do { \
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
-} while(0);
-
-/**
- * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Clear the PVD EXTI flag.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Generates a Software interrupt on PVD EXTI line.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
-/**
- * @}
- */
-
-
-/* Include PWR HAL Extension module */
-#include "stm32h7xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions **********************************************/
-/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-
-/* Cortex System Control functions *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
- * @{
- */
-/*!< External interrupt line 16 Connected to the PVD EXTI Line */
-#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-
-/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
- * @{
- */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_NORMAL))
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
- ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
deleted file mode 100644
index 4bf5477..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pwr_ex.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_PWR_EX_H
-#define __STM32H7xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWREx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Types PWREx Exported Types
- * @{
- */
-/**
- * @brief PWREx AVD configuration structure definition
- */
-typedef struct
-{
- uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.
- This parameter can be a value of @ref PWREx_AVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWREx_AVD_Mode */
-}PWREx_AVDTypeDef;
-
-/**
- * @brief PWREx Wakeup pin configuration structure definition
- */
-typedef struct
-{
- uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
- This parameter can be a value of @ref PWREx_WakeUp_Pins */
-
- uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
- This parameter can be a value of @ref PWREx_PIN_Polarity */
-
- uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull.
- This parameter can be a value of @ref PWREx_PIN_Pull */
-}PWREx_WakeupPinTypeDef;
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
- * @{
- */
-/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
- * @{
- */
-#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN_6
-#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN_5
-#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN_4
-#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN_3
-#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN_2
-#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN_1
-/* High level and No pull */
-#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN_6
-#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN_5
-#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN_4
-#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN_3
-#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN_2
-#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN_1
-/* Low level and No pull */
-#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)
-#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)
-#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)
-#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)
-#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)
-#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)
-
-/* Wake-Up Pins EXTI register mask */
-#define PWR_EXTI_WAKEUP_PINS_MASK (uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \
- EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \
- EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
-/* Wake-Up Pins EXTI register offset */
-#define PWR_EXTI_WAKEUP_PINS_PULL_POSITION_OFFSET 23U
-
-/* Wake-Up Pins PWR register offsets */
-#define PWR_WAKEUP_PINS_POLARITY_REGISTER_OFFSET 8U
-#define PWR_WAKEUP_PINS_PULL_REGISTER_OFFSET 16U
-#define PWR_WAKEUP_PINS_PULL_POSITION_OFFSET 2U
-
-/**
- * @}
- */
-
-/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
- * @{
- */
-#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
-#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
- * @{
- */
-#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
-#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
-#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)
-/**
- * @}
- */
-
-
-/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
- * @{
- */
-#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
-#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
-#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
-#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
-#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
-#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
-/**
- * @}
- */
-
-
-/** @defgroup PWREx_Domains PWREx Domains definition
- * @{
- */
-#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)
-#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)
-#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
- * @{
- */
-#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup PWREx_D3_State PWREx D3 Domain State
- * @{
- */
-#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
-#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)
-
-/**
- * @}
- */
-
-/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
- * @{
- */
-#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
-#if defined(SMPS)
-#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /* Core domains are suppplied from the SMPS only */
-#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 1.8V output supplies the LDO which supplies the Core domains */
-#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 2.5V output supplies the LDO which supplies the Core domains */
-#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
-#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
-#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /* The SMPS 1.8V output supplies an external source which supplies the Core domains */
-#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /* The SMPS 2.5V output supplies an external source which supplies the Core domains */
-#endif /* SMPS */
-#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
-
-#if defined(SMPS)
-#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
- PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
-#else
-#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
-#endif /* SMPS */
-/**
- * @}
- */
-
-#if defined(SMPS)
-/** @defgroup HAL_PWREx_SMPS_SetOperationMode PWREx SMPS operation modes
- * @{
- */
-#define PWR_SMPS_FORCED_PWM PWR_PDR1_SMPSFPWMEN
-#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL0 PWR_PDR1_PSKSYNC
-#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL1 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR_0)
-#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL2 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR_1)
-#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL3 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR)
-#define PWR_SMPS_FAST_PULSE_SKIPPING (PWR_PDR1_FASTTRAN |PWR_PDR1_PSKSYNC)
-#define PWR_SMPS_ULTRA_FAST_PULSE_SKIPPING PWR_PDR1_FASTTRAN
-#define PWR_SMPS_MODE_MASK (PWR_PDR1_FASTTRAN | PWR_PDR1_PSKTHR | PWR_PDR1_PSKSYNC | PWR_PDR1_SMPSFPWMEN)
-/**
- * @}
- */
-#endif /* SMPS */
-
-/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
- * @{
- */
-#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
-#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
-#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
-#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
-/**
- * @}
- */
-
-/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
- * @{
- */
-#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
-#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
- * @{
- */
-#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
-#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
-#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
-/**
- * @}
- */
-
-/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
- * @{
- */
-#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
-/**
- * @}
- */
-
-/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
- * @{
- */
-#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
-#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
-#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
-/**
- * @}
- */
-
-/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
- * @{
- */
-#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
-#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
-#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
-/**
- * @}
- */
-/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
- * @{
- */
-#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
-/**
- * @}
- */
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
- * @{
- */
-
-/**
- * @brief Enable the AVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Disable the AVD EXTI Line 16
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Enable event on AVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Disable event on AVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Enable the AVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
-
-/**
- * @brief Disable the AVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
-
-/**
- * @brief Enable the AVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Disable the AVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief AVD EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
-} while(0);
-
-/**
- * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
-do { \
- __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
-} while(0);
-
-/**
- * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
- * @retval EXTI AVD Line Status.
- */
-#define __HAL_PWR_AVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @brief Clear the AVD EXTI flag.
- * @retval None.
- */
-#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
- * @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
- * @{
- */
-/* Power supply control functions */
-HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
-uint32_t HAL_PWREx_GetSupplyConfig(void);
-#if defined(SMPS)
-uint32_t HAL_PWREx_SMPS_SetOperationMode(uint32_t SMPS_Mode);
-#endif /*SMPS*/
-/* Power volatge scaling functions */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
-uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
-/**
- * @}
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
- * @{
- */
-/* System low power control functions */
-void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
-void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
-void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
-
-
-/* Flash low power control functions */
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
-/* Wakeup Pins control functions */
-void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
-void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
-uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
-HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
-/* Power Wakeup PIN IRQ Handler */
-void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
-void HAL_PWREx_WKUP1_Callback(void);
-void HAL_PWREx_WKUP2_Callback(void);
-void HAL_PWREx_WKUP3_Callback(void);
-void HAL_PWREx_WKUP4_Callback(void);
-void HAL_PWREx_WKUP5_Callback(void);
-void HAL_PWREx_WKUP6_Callback(void);
-/**
- * @}
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
- * @{
- */
-/* Backup regulator control functions */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
-/* USB regulator control functions */
-HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
-void HAL_PWREx_EnableUSBVoltageDetector(void);
-void HAL_PWREx_DisableUSBVoltageDetector(void);
-/* Battery control functions */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
-void HAL_PWREx_DisableBatteryCharging(void);
-/**
- * @}
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
- * @{
- */
-/* Power VBAT/Temperature monitoring functions */
-void HAL_PWREx_EnableMonitoring(void);
-void HAL_PWREx_DisableMonitoring(void);
-uint32_t HAL_PWREx_GetTemperatureLevel(void);
-uint32_t HAL_PWREx_GetVBATLevel(void);
-
-/* Power AVD configuration functions */
-void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
-void HAL_PWREx_EnableAVD(void);
-void HAL_PWREx_DisableAVD(void);
-
-/* Power PVD/AVD IRQ Handler */
-void HAL_PWREx_PVD_AVD_IRQHandler(void);
-void HAL_PWREx_AVDCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWREx Private Macros
- * @{
- */
-
-/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
- * @{
- */
-#if defined(SMPS)
-#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
- ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \
- ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \
- ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \
- ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
- ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
- ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \
- ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \
- ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
-
-#define IS_PWR_SMPS_MODE(MODE) (((MODE) == PWR_SMPS_FORCED_PWM) || \
- ((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL0) || \
- ((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL1) || \
- ((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL2) || \
- ((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL3) || \
- ((MODE) == PWR_SMPS_FAST_PULSE_SKIPPING) || \
- ((MODE) == PWR_SMPS_ULTRA_FAST_PULSE_SKIPPING))
-#else
-#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
- ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
-#endif /*SMPS*/
-
-#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \
- ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \
- ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
-
-#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \
- ((DOMAIN) == PWR_D2_DOMAIN) || \
- ((DOMAIN) == PWR_D3_DOMAIN))
-
-#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
- ((PIN) == PWR_WAKEUP_PIN2) || \
- ((PIN) == PWR_WAKEUP_PIN3) || \
- ((PIN) == PWR_WAKEUP_PIN4) || \
- ((PIN) == PWR_WAKEUP_PIN5) || \
- ((PIN) == PWR_WAKEUP_PIN6) || \
- ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN6_HIGH) || \
- ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN5_LOW) || \
- ((PIN) == PWR_WAKEUP_PIN6_LOW))
-
-#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
- ((POLARITY) == PWR_PIN_POLARITY_LOW))
-
-#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \
- ((PULL) == PWR_PIN_PULL_UP) || \
- ((PULL) == PWR_PIN_PULL_DOWN))
-
-#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \
- ((FLAG) == PWR_WAKEUP_FLAG2) || \
- ((FLAG) == PWR_WAKEUP_FLAG3) || \
- ((FLAG) == PWR_WAKEUP_FLAG4) || \
- ((FLAG) == PWR_WAKEUP_FLAG5) || \
- ((FLAG) == PWR_WAKEUP_FLAG6))
-
-#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
- ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
-
-#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_AVD_MODE_NORMAL))
-
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
- ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h
deleted file mode 100644
index c488c20..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_qspi.h
- * @author MCD Application Team
- * @brief Header file of QSPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_QSPI_H
-#define __STM32H7xx_HAL_QSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-#include "stm32h7xx_hal_mdma.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup QSPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Types QSPI Exported Types
- * @{
- */
-
-/**
- * @brief QSPI Init structure definition
- */
-
-typedef struct
-{
- uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
-
- uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
- This parameter can be a value between 1 and 32 */
-
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
- take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
- This parameter can be a value of @ref QSPI_SampleShifting */
-
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
- memory-mapped mode is limited to 256MB
- This parameter can be a number between 0 and 31 */
-
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
- of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
- uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
- This parameter can be a value of @ref QSPI_ClockMode */
-
- uint32_t FlashID; /* Specifies the Flash which will be used,
- This parameter can be a value of @ref QSPI_Flash_Select */
-
- uint32_t DualFlash; /* Specifies the Dual Flash Mode State
- This parameter can be a value of @ref QSPI_DualFlash_Mode */
-}QSPI_InitTypeDef;
-
-/**
- * @brief HAL QSPI State structures definition
- */
-typedef enum
-{
- HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
- HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
- HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
- HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
- HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
- HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
- HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
- HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
- HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
-}HAL_QSPI_StateTypeDef;
-
-/**
- * @brief QSPI Handle Structure definition
- */
-typedef struct
-{
- QUADSPI_TypeDef *Instance; /* QSPI registers base address */
- QSPI_InitTypeDef Init; /* QSPI communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
- __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
- __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
- __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
- __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
- MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
- __IO HAL_LockTypeDef Lock; /* Locking object */
- __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
- __IO uint32_t ErrorCode; /* QSPI Error code */
- uint32_t Timeout; /* Timeout for the QSPI memory access */
-}QSPI_HandleTypeDef;
-
-/**
- * @brief QSPI Command structure definition
- */
-typedef struct
-{
- uint32_t Instruction; /* Specifies the Instruction to be sent
- This parameter can be a value (8-bit) between 0x00 and 0xFF */
- uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
- uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
- uint32_t AddressSize; /* Specifies the Address Size
- This parameter can be a value of @ref QSPI_AddressSize */
- uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
- This parameter can be a value of @ref QSPI_AlternateBytesSize */
- uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
- This parameter can be a number between 0 and 31 */
- uint32_t InstructionMode; /* Specifies the Instruction Mode
- This parameter can be a value of @ref QSPI_InstructionMode */
- uint32_t AddressMode; /* Specifies the Address Mode
- This parameter can be a value of @ref QSPI_AddressMode */
- uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
- This parameter can be a value of @ref QSPI_AlternateBytesMode */
- uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
- This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
- This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
- until end of memory)*/
- uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
- This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
- This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
- This parameter can be a value of @ref QSPI_SIOOMode */
-}QSPI_CommandTypeDef;
-
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
- */
-typedef struct
-{
- uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFF */
- uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
- This parameter can be any value between 1 and 4 */
- uint32_t MatchMode; /* Specifies the method used for determining a match.
- This parameter can be a value of @ref QSPI_MatchMode */
- uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
- This parameter can be a value of @ref QSPI_AutomaticStop */
-}QSPI_AutoPollingTypeDef;
-
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
- */
-typedef struct
-{
- uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFF */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
- This parameter can be a value of @ref QSPI_TimeOutActivation */
-}QSPI_MemoryMappedTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
- * @{
- */
-
-/** @defgroup QSPI_ErrorCode QSPI Error Code
- * @{
- */
-#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
-/**
- * @}
- */
-
-/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
- * @{
- */
-#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!State = HAL_QSPI_STATE_RESET)
-
-/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @retval None
- */
-#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @retval None
- */
-#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-
-/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval None
- */
-#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-
-/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval None
- */
-#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Timeout interrupt
- * @arg QSPI_IT_SM: QSPI Status match interrupt
- * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
- * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
- * @arg QSPI_IT_TE: QSPI Transfer error interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __FLAG__: specifies the QSPI flag to check.
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_BUSY: QSPI Busy flag
- * @arg QSPI_FLAG_TO: QSPI Timeout flag
- * @arg QSPI_FLAG_SM: QSPI Status match flag
- * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
- * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
- * @arg QSPI_FLAG_TE: QSPI Transfer error flag
- * @retval None
- */
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
-
-/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__: specifies the QSPI Handle.
- * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
- * This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: QSPI Timeout flag
- * @arg QSPI_FLAG_SM: QSPI Status match flag
- * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
- * @arg QSPI_FLAG_TE: QSPI Transfer error flag
- * @retval None
- */
-#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup QSPI_Exported_Functions
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
-
-/* IO operation functions *****************************************************/
-/* QSPI IRQ handler method */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
-
-/* QSPI status flag polling mode */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
-
-/* QSPI memory-mapped mode */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-
-/* Callback functions in non-blocking modes ***********************************/
-void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
-
-/* QSPI indirect mode */
-void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI status flag polling mode */
-void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
-
-/* QSPI memory-mapped mode */
-void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
-
-/* Peripheral Control and State functions ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
-uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
-HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
-void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Macros QSPI Private Macros
-* @{
-*/
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
-
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
-
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
- ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
- ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-
-#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \
- ((FLASH) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
- ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
- ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
- ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
- ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
- ((MODE) == QSPI_ADDRESS_1_LINE) || \
- ((MODE) == QSPI_ADDRESS_2_LINES) || \
- ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
- ((MODE) == QSPI_DATA_1_LINE) || \
- ((MODE) == QSPI_DATA_2_LINES) || \
- ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
- ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
- ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
- ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
-
-#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
- ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
- ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
- ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
-
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
-/**
-* @}
-*/
-/* End of private macros -----------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
deleted file mode 100644
index a4ae011..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
+++ /dev/null
@@ -1,3051 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_RCC_H
-#define __STM32H7xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
-
- uint32_t PLLP; /*!< PLLP: Division factor for system clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 128
- odd division factors are not allowed */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
-
- uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
- uint32_t PLLRGE; /*!AHB3ENR, RCC_AHB3ENR_MDMAEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_FMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
-#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
-#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
-#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
-#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
-
-
-/** @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
-#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
-#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
-#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
-#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
-#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
-#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
-#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
-#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
-
-/** @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_HASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_RNG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
-#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
-#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
-#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
-#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
-#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
-#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
-
-/** @brief Enable or disable the AHB4 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_BDMA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_HSEM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
-#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
-#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
-#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
-#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
-#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
-#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
-#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
-
-
-/** @brief Enable or disable the APB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
-#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
-
-/** @brief Enable or disable the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CEC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DAC12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_UART7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_UART8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CRS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
-
-
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
-#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
-#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
-#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
-#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
-#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
-#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
-#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
-#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
-#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
-
-/** @brief Enable or disable the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USART6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
-#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
-#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
-#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
-#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
-#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
-#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
-#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
-
-/** @brief Enable or disable the APB4 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
-
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_COMP12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_VREF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_SAI4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_RTC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
-#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
-#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
-#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
-#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
-#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
-#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
-#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
-#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
-#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
-#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
-#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
-
-
-
-/** @brief Enable or disable the AHB3 peripheral reset.
- */
-
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
-#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
-#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
-#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
-#define __HAL_RCC_CPU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_CPURST))
-
-
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
-#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
-#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
-#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
-#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
-#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
-#define __HAL_RCC_CPU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_CPURST))
-
-
-
-/** @brief Force or release the AHB1 peripheral reset.
- */
-#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
-#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
-#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
-#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
-
-
-#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
-#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
-#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
-#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
-#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
-
-
-/** @brief Force or release the AHB2 peripheral reset.
- */
-#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
-#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
-
-
-/** @brief Force or release the AHB4 peripheral reset.
- */
-
-#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
-#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
-#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
-#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
-#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
-#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
-#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
-#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
-#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
-
-#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
-#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
-#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
-#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
-#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
-#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
-#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
-#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
-
-
-/** @brief Force or release the APB3 peripheral reset.
- */
-#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
-
-#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00)
-#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
-
-
-/** @brief Force or release the APB1 peripheral reset.
- */
-#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFF)
-#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFF)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
-#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
-#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
-#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
-#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
-#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
-#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
-#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
-#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
-#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
-#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
-#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
-
-#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00)
-#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
-#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
-#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
-#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
-#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
-#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
-#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
-#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
-#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
-#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
-#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
-
-/** @brief Force or release the APB2 peripheral reset.
- */
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
-#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
-#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
-#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
-#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
-#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
-#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
-#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
-#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
-#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
-#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
-#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
-
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
-#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
-#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
-#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
-#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
-#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
-#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
-#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
-#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
-#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
-#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
-
-/** @brief Force or release the APB4 peripheral reset.
- */
-
-#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
-#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
-#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
-#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
-#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
-#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
-#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
-#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
-#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
-#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
-#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
-
-
-#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00)
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
-#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
-#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
-#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
-#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
-#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
-#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
-#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
-#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
-#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
-#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
-
-
-/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- */
-
-
-#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
-#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
-#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
-#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
-#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
-#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
-
-
-#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
-#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
-#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
-#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
-#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
-#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
-
-
-
-/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
-#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
-#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
-#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
-#define __HAL_RCC_ETH1PTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1PTPLPEN))
-#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
-#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
-#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
-#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
-#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
-#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
-#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
-#define __HAL_RCC_ETH1PTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1PTPLPEN))
-#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
-#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
-#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
-#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
-
-/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
-#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
-#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
-#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
-#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
-#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
-#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
-
-/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
-#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
-#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
-#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
-#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
-#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
-#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
-#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
-#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
-
-/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
-#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
-
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
-
-#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
-
-/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
-
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
-#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
-#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
-#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
-
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
-
-
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
-#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
-#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
-#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
-#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
-#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
-
-/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
-#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
-#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
-#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
-#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
-#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
-#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
-
-/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
- * @note By default, all peripheral clocks are ENABLEd during SLEEP mode.
- */
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
-#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
-#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
-#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
-#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
-#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
-#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
-#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
-#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
-
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
-#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
-#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
-#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
-#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
-#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
-#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
-#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
-#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
-
-
-
-/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN
- * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP
- */
-
-#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
-#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
-#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
-#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
-#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
-#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
-#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
-#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
-#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
-#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
-#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
-#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
-#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
-#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
-
-
-#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
-#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
-
-#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
-#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
-#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
-#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
-#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
-#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
-#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
-#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
-#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
-#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
-#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN)
-#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN)
-#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN)
-#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN)
-
-
-#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
-#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
-
-
-/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the PLL and/or system clock.
- * @note HSI can not be stopped if it is used directly or through the PLL
- * as system clock. In this case, you have to select another source
- * of the system clock then stop the HSI.
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @param __STATE__ specifies the new state of the HSI.
- * This parameter can be one of the following values:
- * @arg RCC_HSI_OFF turn OFF the HSI oscillator
- * @arg RCC_HSI_ON turn ON the HSI oscillator
- * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
- * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
- * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
- * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_CONFIG(__STATE__) \
- MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
-
-
-/** @brief Macro to get the HSI divider.
- * @retval The HSI divider. The returned value can be one
- * of the following:
- * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset)
- * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2
- * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4
- * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8
- */
-#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after start-up
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
-
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x3F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
-
-/**
- * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
- * in STOP mode to be quickly available as kernel clock for some peripherals.
- * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
- * speed because of the HSI start-up time.
- * @note The enable of this function has not effect on the HSION bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
-#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
-
-
-/**
- * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
- * @note After enabling the HSI48, the application software should wait on
- * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
- * be used to clock the USB.
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
-
-#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
-
-/**
- * @brief Macros to enable or disable the Internal oscillator (CSI).
- * @note The CSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after
- * start-up from Reset, wakeup from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note CSI can not be stopped if it is used as system clock source.
- * In this case, you have to select another source of the system
- * clock then stop the CSI.
- * @note After enabling the CSI, the application software should wait on
- * CSIRDY flag to be set indicating that CSI clock is stable and can
- * be used as system clock source.
- * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
-#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
-
-/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal CSI RC.
- * @param __CSICalibrationValue__: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << POSITION_VAL(RCC_ICSCR_CSITRIM))
-
-/**
- * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
- * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
- * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
- * speed because of the CSI start-up time.
- * @note The enable of this function has not effect on the CSION bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
-#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
-
-
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-
-/**
- * @brief Macro to configure the External High Speed oscillator (__HSE__).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator.
- * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do { \
- if ((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if ((__STATE__) == RCC_HSE_OFF) \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- else if ((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- } while(0)
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
- * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator.
- * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if((__STATE__) == RCC_LSE_OFF) \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- else if((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- } while(0)
-/**
- * @}
- */
-
-/** @brief Macros to enable or disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-
-/** @brief Macros to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
- * a Power On Reset (POR).
- * @param __RTCCLKSource__: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFF) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
- RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
- } while (0)
-
-#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
-
-
-/** @brief Macros to force or release the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-
-/** @brief Macros to enable or disable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
-
-/**
- * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
- * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL,
- * (except the ck_pll_p of the System PLL that cannot be stopped if used as System
- * Clock.This is mainly used to save Power.
- * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
- * This parameter can be one of the following values:
- * @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ)
- * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
- * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
- * @retval None
- */
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
-
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
-
-
-/**
- * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
- * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1
- * @retval None
- */
-#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
-
-#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
-
-
-/**
- * @brief Macro to configures the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
- *
- * @param __PLLM1__: specifies the division factor for PLL VCO input clock
- * This parameter must be a number between 1 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 16 MHz.
- *
- * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 4 and 512.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 150 and 420 MHz (when in medium VCO range) or
- * between 192 and 836 MHZ (when in wide VCO range)
- *
- * @param __PLLP1__: specifies the division factor for system clock.
- * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
- *
- * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @param __PLLR1__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @retval None
- */
-
-
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
- do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \
- WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
- ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
- } while(0)
-
-
-/** @brief Macro to configure the PLLs clock source.
- * @note This function must be used only when all PLLs are disabled.
- * @param __PLLSOURCE__: specifies the PLLs entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- *
- */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
-
-
-/**
- * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
- *
- * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
- *
- * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
- * It should be a value between 0 and 8191
- * @note Warning: The software has to set correctly these bits to insure that the VCO
- * output frequency is between its valid frequency range, which is:
- * 192 to 836 MHz if PLL1VCOSEL = 0
- * 150 to 420 MHz if PLL1VCOSEL = 1.
- *
- *
- * @retval None
- */
- #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << POSITION_VAL(RCC_PLL1FRACR_FRACN1))
-
-
-/** @brief Macro to select the PLL1 reference frequency range.
- * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
- * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
- * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
- * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
-
-
-/** @brief Macro to select the PLL1 reference frequency range.
- * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz
- * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
-
-
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - RCC_CFGR_SWS_CSI: CSI used as system clock.
- * - RCC_CFGR_SWS_HSI: HSI used as system clock.
- * - RCC_CFGR_SWS_HSE: HSE used as system clock.
- * - RCC_CFGR_SWS_PLL: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
-
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
- * This parameter can be one of the following values:
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be one
- * of the following:
- * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
- * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
- * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
- * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
- * @retval None
- */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
-/**
- * @brief Macro to configure the wake up from stop clock.
- * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
- * This parameter can be one of the following values:
- * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
- * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
- * @retval None
- */
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
-
-/**
- * @brief Macro to configure the Kernel wake up from stop clock.
- * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
- * This parameter can be one of the following values:
- * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
- * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
- * @retval None
- */
-#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-/** @brief Enable RCC interrupt.
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_CSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
- * @arg RCC_IT_LSECSS: Clock security system interrupt
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_CSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
- * @arg RCC_IT_LSECSS: Clock security system interrupt
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_CSIRDY: CSI ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
- * @arg RCC_IT_HSECSS: HSE Clock Security interrupt
- * @arg RCC_IT_LSECSS: Clock security system interrupt
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__: specifies the RCC interrupt source to check.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_CSIRDY: CSI ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
- * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
- * @arg RCC_IT_HSECSS: HSE Clock Security interrupt
- * @arg RCC_IT_LSECSS: Clock security system interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
-
-
-
-/** @brief Check RCC flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSIDIV: HSI divider flag
- * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
- * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready
- * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready
- * @arg RCC_FLAG_PLLRDY: PLL1 clock ready
- * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
- * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_RMVF: Remove reset Flag
- * @arg RCC_FLAG_CPURST: CPU reset flag
- * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag
- * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag
- * @arg RCC_FLAG_BORRST: BOR reset flag
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
- * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag
- * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
- * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
- * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
- * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR : \
-((((__FLAG__) >> 5) == 3)? RCC->CSR : ((((__FLAG__) >> 5) == 4)? RCC->RSR :RCC->CIFR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
-
-
-/**
- * @}
- */
-
-#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> POSITION_VAL(RCC_PLLCKSELR_PLLSRC))
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extension module */
-#include "stm32h7xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CCSCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define CSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
-#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-
-/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
- * @{
- */
-
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
- ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
- ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
-
-#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
-
-#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
- ((PLL) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_NONE) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
-#define IS_RCC_PLLN_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
-#define IS_RCC_PLLP_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLLR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-
-#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
- ((VALUE) == RCC_PLL1_DIVQ) || \
- ((VALUE) == RCC_PLL1_DIVR))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 0x3F))
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \
- ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \
- ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \
- ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
- ((SYSCLK) == RCC_SYSCLK_DIV512))
-
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \
- ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \
- ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \
- ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
- ((HCLK) == RCC_HCLK_DIV512))
-
-#define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \
- ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \
- ((D1PCLK1) == RCC_APB3_DIV16))
-
-#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
- ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
- ((PCLK1) == RCC_APB1_DIV16))
-
-#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
- ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
- ((PCLK2) == RCC_APB2_DIV16))
-
-#define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \
- ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \
- ((D3PCLK1) == RCC_APB4_DIV16))
-
-#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSI48))
-
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
- ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \
- ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
- ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
- ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
- ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
- ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
- ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
- ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
- ((DIV) == RCC_MCODIV_15))
-
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
- ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
- ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_RMVF) || \
- ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \
- ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
- ((FLAG) == RCC_FLAG_WWDGR1ST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
- ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
-
-
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFFF)
-#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
- ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
-
-#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
- ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
deleted file mode 100644
index 358d9fd..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,3194 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_RCC_EX_H
-#define __STM32H7xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-/**
- * @brief PLL2 Clock structure definition
- */
-typedef struct
-{
-
- uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
-
- uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
- This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
-
- uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 128
- odd division factors are not allowed */
-
- uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
-
- uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
- uint32_t PLL2RGE; /*!CR, RCC_CR_PLL2ON)
-#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
-
-/**
- * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
- * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2,
- * This is mainly used to save Power.
- * @param __RCC_PLL2ClockOut__: Specifies the PLL2 clock to be outputted
- * This parameter can be one of the following values:
- * @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
- * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
- * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
- * @retval None
- */
-#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
-
-#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
-
-/**
- * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
- * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
- * @retval None
- */
-#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
-
-#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
-
-/**
- * @brief Macro to configures the PLL2 multiplication and division factors.
- * @note This function must be used only when PLL2 is disabled.
- *
- * @param __PLL2M__: specifies the division factor for PLL2 VCO input clock
- * This parameter must be a number between 1 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 16 MHz.
- *
- * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
- * This parameter must be a number between 4 and 512.
- * @note You have to set the PLL2N parameter correctly to ensure that the VCO
- * output frequency is between 150 and 420 MHz (when in medium VCO range) or
- * between 192 and 836 MHZ (when in wide VCO range)
- *
- * @param __PLL2P__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
- *
- * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @param __PLL2R__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @retval None
- */
-
-
-#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
- do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
- WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
- ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
- } while(0)
-/**
- * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
- *
- * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
- *
- * @param __RCC_PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
- * It should be a value between 0 and 8191
- * @note Warning: the software has to set correctly these bits to insure that the VCO
- * output frequency is between its valid frequency range, which is:
- * 192 to 836 MHz if PLL2VCOSEL = 0
- * 150 to 420 MHz if PLL2VCOSEL = 1.
- *
- *
- * @retval None
- */
- #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << POSITION_VAL(RCC_PLL2FRACR_FRACN2))
-
-/** @brief Macro to select the PLL2 reference frequency range.
- * @param __RCC_PLL2VCIRange__: specifies the PLL2 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
- * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
- * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
- * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
-
-
-/** @brief Macro to select the PLL2 reference frequency range.
- * @param __RCC_PLL2VCORange__: Specifies the PLL2 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
- * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
-
-/** @brief Macros to enable or disable the main PLL3.
- * @note After enabling PLL3, the application software should wait on
- * PLL3RDY flag to be set indicating that PLL3 clock is stable and can
- * be used as kernel clock source.
- * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
-#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
-
-/**
- * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
- * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
- * @retval None
- */
-#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
-
-#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
-
-/**
- * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
- * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3,
- * This is mainly used to save Power.
- * @param __RCC_PLL3ClockOut__: specifies the PLL3 clock to be outputted
- * This parameter can be one of the following values:
- * @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
- * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
- * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
- * @retval None
- */
-#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
-
-#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
-
-/**
- * @brief Macro to configures the PLL3 multiplication and division factors.
- * @note This function must be used only when PLL3 is disabled.
- *
- * @param __PLL3M__: specifies the division factor for PLL3 VCO input clock
- * This parameter must be a number between 1 and 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 16 MHz.
- *
- * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
- * This parameter must be a number between 4 and 512.
- * @note You have to set the PLL3N parameter correctly to ensure that the VCO
- * output frequency is between 150 and 420 MHz (when in medium VCO range) or
- * between 192 and 836 MHZ (when in wide VCO range)
- *
- * @param __PLL3P__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 2 and 128 (where odd numbers not allowed)
- *
- * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @param __PLL3R__: specifies the division factor for peripheral kernel clocks
- * This parameter must be a number between 1 and 128
- *
- * @retval None
- */
-
-#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
- do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
- WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
- ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
- } while(0)
-
-
-
-/**
- * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor
- *
- * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
- *
- * @param __RCC_PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
- * It should be a value between 0 and 8191
- * @note Warning: the software has to set correctly these bits to insure that the VCO
- * output frequency is between its valid frequency range, which is:
- * 192 to 836 MHz if PLL3VCOSEL = 0
- * 150 to 420 MHz if PLL3VCOSEL = 1.
- *
- *
- * @retval None
- */
- #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << POSITION_VAL(RCC_PLL3FRACR_FRACN3))
-
-/** @brief Macro to select the PLL3 reference frequency range.
- * @param __RCC_PLL3VCIRange__: specifies the PLL1 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
- * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
- * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
- * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
-
-
-/** @brief Macro to select the PLL3 reference frequency range.
- * @param __RCC_PLL3VCORange__: specifies the PLL1 input frequency range
- * This parameter can be one of the following values:
- * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
- * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
- * @retval None
- */
-#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
-/**
- * @brief Macro to Configure the SAI1 clock source.
- * @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
- * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
-
-/** @brief Macro to get the SAI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
- * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
- * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
- * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
- * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
- */
-#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
-
-/**
- * @brief Macro to Configure the SPDIFRX clock source.
- * @param __RCC_SPDIFCLKSource__: defines the SPDIFRX clock source. This clock is derived
- * from system PLL, PLL2, PLL3, or internal OSC clock
- * This parameter can be one of the following values:
- * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
- * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
- * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
- * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
- * @retval None
- */
-#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
-/**
- * @brief Macro to get the SPDIFRX clock source.
- * @retval None
- */
-#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
-
-/**
- * @brief Macro to Configure the SAI2/3 clock source.
- * @param __RCC_SAI23CLKSource__: defines the SAI2/3 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
- * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
- * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
- * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
- * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
-
-/** @brief Macro to get the SAI2/3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
- * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
- * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
- * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
- * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
- */
-#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
-
-/**
- * @brief Macro to Configure the SAI2 clock source.
- * @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
- * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
- * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
- * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
- * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
-
-/** @brief Macro to get the SAI2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
- * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
- * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
- * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
- * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
- */
-#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
-
-/**
- * @brief Macro to Configure the SAI3 clock source.
- * @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
- * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
- * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
- * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
- * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
-
-/** @brief Macro to get the SAI3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
- * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
- * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
- * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
- * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
- */
-#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
-
-/**
- * @brief Macro to Configure the SAI4A clock source.
- * @param __RCC_SAI4ACLKSource__: defines the SAI4A clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
- * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
- * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
- * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP
- * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
-
-/** @brief Macro to get the SAI4A clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
- * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
- * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
- * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP
- * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
- */
-#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
-
-/**
- * @brief Macro to Configure the SAI4B clock source.
- * @param __RCC_SAI4BCLKSource__: defines the SAI4B clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
- * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
- * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
- * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
- * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
-
-/** @brief Macro to get the SAI4B clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
- * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
- * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
- * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
- * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
- */
-#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
-
-/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
- *
- * @param __I2C123CLKSource__: specifies the I2C1/2/3 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
- */
-#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
-
-/** @brief macro to get the I2C1/2/3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
- */
-#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
-
-/** @brief macro to configure the I2C1 clock (I2C1CLK).
- *
- * @param __I2C1CLKSource__: specifies the I2C1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
- */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
-
-/** @brief macro to get the I2C1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
- * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
- */
-#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
-
-/** @brief macro to configure the I2C2 clock (I2C2CLK).
- *
- * @param __I2C2CLKSource__: specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
-
-/** @brief macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
- * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
-
-/** @brief macro to configure the I2C3 clock (I2C3CLK).
- *
- * @param __I2C3CLKSource__: specifies the I2C3 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
- */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
-
-/** @brief macro to get the I2C3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
- */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
-
-/** @brief macro to configure the I2C4 clock (I2C4CLK).
- *
- * @param __I2C4CLKSource__: specifies the I2C4 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
- */
-#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
-
-/** @brief macro to get the I2C4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
- * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
- */
-#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
-
-/** @brief macro to configure the USART1/6 clock (USART16CLK).
- *
- * @param __USART16CLKSource__: specifies the USART1/6 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
- */
-#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
-
-/** @brief macro to get the USART1/6 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
- * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
- */
-#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
-
-/** @brief macro to configure the USART234578 clock (USART234578CLK).
- *
- * @param __USART234578CLKSource__: specifies the USART2/3/4/5/7/8 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
- */
-#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
-
-/** @brief macro to get the USART2/3/4/5/7/8 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
- * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
- */
-#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the USART1 clock (USART1CLK).
- *
- * @param __USART1CLKSource__: specifies the USART1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
- */
-#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
-
-/** @brief macro to get the USART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
- * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
- */
-#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
-
-/** @brief macro to configure the USART2 clock (USART2CLK).
- *
- * @param __USART2CLKSource__: specifies the USART2 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
- */
-#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
-
-/** @brief macro to get the USART2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
- * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
- */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the USART3 clock (USART3CLK).
- *
- * @param __USART3CLKSource__: specifies the USART3 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
- */
-#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
-
-/** @brief macro to get the USART3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
- * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
- */
-#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the UART4 clock (UART4CLK).
- *
- * @param __UART4CLKSource__: specifies the UART4 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
- */
-#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
-
-/** @brief macro to get the UART4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
- * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
- */
-#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the UART5 clock (UART5CLK).
- *
- * @param __UART5CLKSource__: specifies the UART5 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
- */
-#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
-
-/** @brief macro to get the UART5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
- * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
- */
-#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the USART6 clock (USART6CLK).
- *
- * @param __USART6CLKSource__: specifies the USART6 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
- */
-#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
-
-/** @brief macro to get the USART6 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
- * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
- */
-#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
-
-/** @brief macro to configure the UART5 clock (UART7CLK).
- *
- * @param __UART7CLKSource__: specifies the UART7 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
- */
-#define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
-
-/** @brief macro to get the UART7 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
- * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
- */
-#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the UART8 clock (UART8CLK).
- *
- * @param __UART8CLKSource__: specifies the UART8 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
- */
-#define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
-
-/** @brief macro to get the UART8 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
- * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
- */
-#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
-
-/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
- *
- * @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
-
-/** @brief macro to get the LPUART1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
- * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
- */
-#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
-
-/** @brief macro to get the LPTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
- */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
-
-
-/** @brief macro to get the LPTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
- * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
- */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
-
-/** @brief macro to get the LPTIM2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
- */
-#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
-
-
-/** @brief macro to get the LPTIM2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
- * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
- */
-#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
-
-/** @brief macro to get the LPTIM3/4/5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
- */
-#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
-
-
-/** @brief macro to get the LPTIM3/4/5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
- * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
- */
-#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
-
-/** @brief macro to get the LPTIM3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
- */
-#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
-
-
-/** @brief macro to get the LPTIM3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
- * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
- */
-#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
-
-/** @brief macro to get the LPTIM4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
- */
-#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
-
-
-/** @brief macro to get the LPTIM4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
- * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
- */
-#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
-
-/** @brief macro to configure the LPTIM5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
- */
-#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
-
-
-/** @brief macro to get the LPTIM5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
- * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
- */
-#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
-
-/** @brief macro to configure the QSPI clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
- */
-#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
- MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
-
-
-/** @brief macro to get the QSPI clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
- * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
- */
-#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
-
-
-/** @brief macro to configure the FMC clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
- */
-#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
- MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
-
-
-/** @brief macro to get the FMC clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
- * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
- */
-#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
-
-/** @brief Macro to configure the USB clock (USBCLK).
- * @param __USBCLKSource__: specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
-
-/** @brief Macro to get the USB clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
- * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
- * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
-
-
-/** @brief Macro to configure the ADC clock
- * @param __ADCCLKSource__: specifies the ADC digital interface clock source.
- * This parameter can be one of the following values:
- * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
- */
-#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
-
-/** @brief Macro to get the ADC clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
- * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
- * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
- */
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
-
- /** @brief Macro to configure the SWPMI1 clock
- * @param __SWPMI1CLKSource__: specifies the SWPMI1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
- */
-#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
-
-/** @brief Macro to get the SWPMI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
- * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
- */
-#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
-
- /** @brief Macro to configure the DFSDM1 clock
- * @param __DFSDM1CLKSource__: specifies the DFSDM1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
- */
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
-
-/** @brief Macro to get the DFSDM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
- * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
- */
-#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
-
-/** @brief macro to configure the CEC clock (CECCLK).
- *
- * @param __CECCLKSource__: specifies the CEC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
- */
-#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
-
-/** @brief macro to get the CEC clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
- * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
- * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
- */
-#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
-
-
-/** @brief Macro to configure the CLKP : Oscillator clock for peripheral
- * @param __CLKPSource__: specifies Oscillator clock for peripheral
- * This parameter can be one of the following values:
- * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
- */
-#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
- MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
-
-/** @brief Macro to get the Oscillator clock for peripheral source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
- * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
- * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
- */
-#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/** @brief Macro to configure the FDCAN clock
- * @param __FDCANCLKSource__: specifies clock source for FDCAN
- * This parameter can be one of the following values:
- * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
- * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
- * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
- */
-#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
-
-/** @brief Macro to get the FDCAN clock
- * @retval The clock source can be one of the following values:
- * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
- * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
- * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
- */
-#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
-#endif /*FDCAN1 || FDCAN2*/
-/**
- * @brief Macro to Configure the SPI1/2/3 clock source.
- * @param __RCC_SPI123CLKSource__: defines the SPI1/2/3 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
-
-/** @brief Macro to get the SPI1/2/3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
- * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
- * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
- * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
- * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
- */
-#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
-
-/**
- * @brief Macro to Configure the SPI1 clock source.
- * @param __RCC_SPI1CLKSource__: defines the SPI1 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
-
-/** @brief Macro to get the SPI1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
- * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
- * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
- * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
- * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
- */
-#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
-
-/**
- * @brief Macro to Configure the SPI2 clock source.
- * @param __RCC_SPI2CLKSource__: defines the SPI2 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
-
-/** @brief Macro to get the SPI2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
- * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
- * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
- * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
- * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
- */
-#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
-
-/**
- * @brief Macro to Configure the SPI3 clock source.
- * @param __RCC_SPI3CLKSource__: defines the SPI3 clock source. This clock is derived
- * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
- * This parameter can be one of the following values:
- * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
- * @retval None
- */
-#define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
-
-/** @brief Macro to get the SPI3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
- * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
- * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
- * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
- * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
- */
-#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
-
-/**
- * @brief Macro to Configure the SPI4/5 clock source.
- * @param __RCC_SPI45CLKSource__: defines the SPI4/5 clock source. This clock is derived
- * from system PCLK, PLL2, PLL3, OSC
- * This parameter can be one of the following values:
- * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
- * @retval None
- */
-#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
-
-/** @brief Macro to get the SPI4/5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
- * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
- * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
- * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
- * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
- * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
-*/
-#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
-
-/**
- * @brief Macro to Configure the SPI4 clock source.
- * @param __RCC_SPI4CLKSource__: defines the SPI4 clock source. This clock is derived
- * from system PCLK, PLL2, PLL3, OSC
- * This parameter can be one of the following values:
- * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
- * @retval None
- */
-#define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
-
-/** @brief Macro to get the SPI4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
- * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
- * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
- * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
- * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
- * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
-*/
-#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
-
-/**
- * @brief Macro to Configure the SPI5 clock source.
- * @param __RCC_SPI5CLKSource__: defines the SPI5 clock source. This clock is derived
- * from system PCLK, PLL2, PLL3, OSC
- * This parameter can be one of the following values:
- * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
- * @retval None
- */
-#define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
-
-/** @brief Macro to get the SPI5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
- * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
- * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
- * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
- * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
- * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
-*/
-#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
-
-/**
- * @brief Macro to Configure the SPI6 clock source.
- * @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. This clock is derived
- * from system PCLK, PLL2, PLL3, OSC
- * This parameter can be one of the following values:
- * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
- * @retval None
- */
-#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
- MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
-
-/** @brief Macro to get the SPI6 clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
- * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
- * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
- * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
- * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
- * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
-*/
-#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
-
-/** @brief Macro to configure the SDMMC clock
- * @param __SDMMCCLKSource__: specifies clock source for SDMMC
- * This parameter can be one of the following values:
- * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
- * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
- */
-#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
- MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
-
-/** @brief Macro to get the SDMMC clock
- */
-#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
-
-/** @brief macro to configure the RNG clock (RNGCLK).
- *
- * @param __RNGCLKSource__: specifies the RNG clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
- */
-#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
-
-/** @brief macro to get the RNG clock source.
- * @retval The clock source can be one of the following values:
- * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
- * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
- */
-#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
-
-
-/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the HRTIM1 prescaler clock source.
- * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
- * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
- */
-#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
-
-/** @brief Macro to get the HRTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
- * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
- */
-#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
-
-/** @brief Macro to configure the Timers clocks prescalers
- * @param __PRESC__ : specifies the Timers clocks prescalers selection
- * This parameter can be one of the following values:
- * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
- * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
- * else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
- * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
- * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
- * else it is equal to 4 x Frcc_pclkx_d2
- */
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
- RCC->CFGR |= (__PRESC__); \
- }while(0)
-
-/**
- * @}
- */
-/**
- * @brief Enable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CRS interrupts.
- * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval None
- */
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
-
-/** @brief Check whether the CRS interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the CRS interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/** @brief Clear the CRS interrupt pending bits
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
- * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
- * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
- * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
- * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
- * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
- * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
- */
-/* CRS IT Error Mask */
-#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
-
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
- if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
- } \
- } while(0)
-
-/**
- * @brief Check whether the specified CRS flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @retval The new state of _FLAG_ (TRUE or FALSE).
- */
-#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the CRS specified FLAG.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
- * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
- * @arg @ref RCC_CRS_FLAG_ERR Error
- * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
- * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
- * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
- * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
- * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
- * @retval None
- */
-
-/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
-
-#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
- if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__FLAG__)); \
- } \
- } while(0)
-
- /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
- * @{
- */
-/**
- * @brief Enable the oscillator clock for frequency error counter.
- * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Disable the oscillator clock for frequency error counter.
- * @retval None
- */
-#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
-
-/**
- * @brief Enable the automatic hardware adjustment of TRIM bits.
- * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
- * @retval None
- */
-#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
-
-/**
- * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
- * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
- * of the synchronization source after pre-scaling. It is then decreased by one in order to
- * reach the expected synchronization on the zero value. The formula is the following:
- * RELOAD = (fTARGET / fSYNC) -1
- * @param __FTARGET__ Target frequency (value in Hz)
- * @param __FSYNC__ Synchronization signal frequency (value in Hz)
- * @retval None
- */
-#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
-uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
-uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
-void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
-void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
-void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group2
- * @{
- */
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
-void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
-void HAL_RCCEx_EnableLSECSS(void);
-void HAL_RCCEx_DisableLSECSS(void);
-void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
-/**
- * @}
- */
-
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
- * @{
- */
-
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-void HAL_RCCEx_CRS_IRQHandler(void);
-void HAL_RCCEx_CRS_SyncOkCallback(void);
-void HAL_RCCEx_CRS_SyncWarnCallback(void);
-void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
-void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
-
-/**
- * @}
- */
-
- /* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
- * @{
- */
-
-#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
- ((VALUE) == RCC_PLL2_DIVQ) || \
- ((VALUE) == RCC_PLL2_DIVR))
-
-#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
- ((VALUE) == RCC_PLL3_DIVQ) || \
- ((VALUE) == RCC_PLL3_DIVR))
-
-#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
- ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
-
-#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
-
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
- ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
-
-#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
-
-#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
-
-#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
-
-#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
- ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
-
-#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
-
-#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
-
-#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
-
-#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
-
-#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
-
-#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
-
-#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
-
-#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
- ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
- ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
- ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
-
-#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
- ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
-
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
-
-#define IS_RCC_SAI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
-
-#define IS_RCC_SAI23CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
-
-#define IS_RCC_SAI2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
-
-#define IS_RCC_SAI3CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
-
-#define IS_RCC_SPI123CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
-
-#define IS_RCC_SPI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
-
-#define IS_RCC_SPI2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
-
-#define IS_RCC_SPI3CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
-
-#define IS_RCC_SPI45CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \
- ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
- ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
-
-#define IS_RCC_SPI4CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \
- ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \
- ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
-
-#define IS_RCC_SPI5CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
- ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \
- ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
-
-#define IS_RCC_SPI6CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
- ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
- ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
-
-#define IS_RCC_SAI4ACLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
-
-#define IS_RCC_SAI4BCLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
- ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
- ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
-
-#define IS_RCC_PLL3M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
-#define IS_RCC_PLL3N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
-#define IS_RCC_PLL3P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLL3Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLL3R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-
-#define IS_RCC_PLL2M_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 63))
-#define IS_RCC_PLL2N_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
-#define IS_RCC_PLL2P_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLL2Q_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-#define IS_RCC_PLL2R_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
-
-#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
-
-#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
-
-#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
-
-#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
-
-#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
-
-#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
- ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \
- ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
-
-#define IS_RCC_QSPICLK(__SOURCE__) \
- (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \
- ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
-
-
-#define IS_RCC_FMCCLK(__SOURCE__) \
- (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
- ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \
- ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
-
-#if defined(FDCAN1) || defined(FDCAN2)
-#define IS_RCC_FDCANCLK(__SOURCE__) \
- (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
-#endif /*FDCAN1 || FDCAN2*/
-
-#define IS_RCC_SDMMC(__SOURCE__) \
- (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
-
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
-
-#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
-
-#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
- ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
-
-#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
- ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
-
-#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \
- ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
- ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
- ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
-
-#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
- ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
- ((SOURCE) == RCC_CECCLKSOURCE_CSI))
-
-#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \
- ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
- ((SOURCE) == RCC_CLKPSOURCE_HSE))
-#define IS_RCC_TIMPRES(VALUE) \
- (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
- ((VALUE) == RCC_TIMPRES_ACTIVATED))
-
-
-#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
-
-
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))
-
-#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
-
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
-
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
-
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
-
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
-
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
- ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h
deleted file mode 100644
index a39d50d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rng.h
- * @author MCD Application Team
- * @brief Header file of RNG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_RNG_H
-#define __STM32H7xx_HAL_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RNG RNG
- * @brief RNG HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
- * @{
- */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t ClockErrorDetection; /*!< CED Clock error detection */
-
-}RNG_InitTypeDef;
-
-/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
- * @{
- */
-typedef enum
-{
- HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
- HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
- HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
- HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
- HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
-
-}HAL_RNG_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
- * @{
- */
-typedef struct
-{
- RNG_TypeDef *Instance; /*!< Register base address */
-
- RNG_InitTypeDef Init; /*!< RNG parameters */
-
- HAL_LockTypeDef Lock; /*!< RNG locking object */
-
- __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
-
- uint32_t RandomNumber; /*!< Last Generated RNG Data */
-
-}RNG_HandleTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
- * @{
- */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
- * @{
- */
-#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
-#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
-#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
- * @{
- */
-#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
-#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
-#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
- * @{
- */
-#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection Enabled*/
-#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
- * @{
- */
-
-/** @brief Reset RNG handle state
- * @param __HANDLE__: RNG Handle
- * @retval None
- */
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-
-/**
- * @brief Enables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
- * @retval None
- */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
-
-/**
- * @brief Disables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
- * @retval None
- */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
- * @brief Check the selected RNG flag status.
- * @param __HANDLE__: RNG Handle
- * @param __FLAG__: RNG flag
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready
- * @arg RNG_FLAG_CECS: Clock error current status
- * @arg RNG_FLAG_SECS: Seed error current status
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clears the selected RNG flag status.
- * @param __HANDLE__: RNG handle
- * @param __FLAG__: RNG flag to clear
- * @note WARNING: This is a dummy macro for HAL code alignment,
- * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
- * @retval None
- */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
-
-
-
-/**
- * @brief Enables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
- * @retval None
- */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
-
-/**
- * @brief Disables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
- * @retval None
- */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_DRDY: Data ready interrupt
- * @arg RNG_IT_CEI: Clock error interrupt
- * @arg RNG_IT_SEI: Seed error interrupt
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clear the RNG interrupt status flags.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock error interrupt
- * @arg RNG_IT_SEI: Seed error interrupt
- * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
- * @retval None
- */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
- * @{
- */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
- * @{
- */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
- ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
-
-#define IS_RNG_CED(CED) (((CED) == RNG_CED_ENABLE) || \
- ((CED) == RNG_CED_DISABLE))
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h
deleted file mode 100644
index 7116b9c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h
+++ /dev/null
@@ -1,860 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_RTC_H
-#define __STM32H7xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
- * @{
- */
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
-
-}HAL_RTCStateTypeDef;
-
-/**
- * @brief RTC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
- uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
- uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
- This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
-
- uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
- This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
- uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
- This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
- uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
- This parameter corresponds to a time unit range between [0-1] Second
- with [1 Sec / SecondFraction +1] granularity */
-
- uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
- corresponding to Synchronous pre-scaler factor value (PREDIV_S)
- This parameter corresponds to a time unit range between [0-1] Second
- with [1 Sec / SecondFraction +1] granularity.
- This field will be used only by HAL_RTC_GetTime function */
-
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
- This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
- in CR register to store the operation.
- This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t Date; /*!< Specifies the RTC Date.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
- uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
- This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
- uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint32_t Alarm; /*!< Specifies the alarm .
- This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/**
- * @brief Time Handle Structure definition
- */
-typedef struct
-{
- RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
-
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
- * @{
- */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
- * @{
- */
-#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
-#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
- * @{
- */
-#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
-#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
- * @{
- */
-#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
-#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
- * @{
- */
-#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
-#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
- * @{
- */
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
- * @{
- */
-#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
-#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
-#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
- * @{
- */
-#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
-#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
- * @{
- */
-#define RTC_FORMAT_BIN ((uint32_t)0x00000000)
-#define RTC_FORMAT_BCD ((uint32_t)0x00000001)
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
-#define RTC_MONTH_MARCH ((uint8_t)0x03)
-#define RTC_MONTH_APRIL ((uint8_t)0x04)
-#define RTC_MONTH_MAY ((uint8_t)0x05)
-#define RTC_MONTH_JUNE ((uint8_t)0x06)
-#define RTC_MONTH_JULY ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
- * @{
- */
-#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
- * @{
- */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
- * @{
- */
-#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
-#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
- * @{
- */
-#define RTC_ALARM_A RTC_CR_ALRAE
-#define RTC_ALARM_B RTC_CR_ALRBE
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
- * @{
- */
-#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */
-#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */
-#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */
-#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */
-#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */
-#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */
-#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
-#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
-#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
-#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
-#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
-#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
-#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
-#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
-#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
-#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
-#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
-#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
-#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
-#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
-#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
-#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
-#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @brief Reset RTC handle state
- * @param __HANDLE__: RTC handle.
- * @retval None
- */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCA; \
- (__HANDLE__)->Instance->WPR = 0x53; \
- } while(0)
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFF; \
- } while(0)
-
-
-/**
- * @brief Enable the RTC ALARMA peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
- * @brief Disable the RTC ALARMA peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
- * @brief Enable the RTC ALARMB peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
- * @brief Disable the RTC ALARMB peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
- * @brief Enable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to check.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @arg RTC_FLAG_ALRAWF
- * @arg RTC_FLAG_ALRBWF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt is enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Clear the RTC Alarm associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @}
- */
-
-/* Include RTC HAL Extended module */
-#include "stm32h7xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RTC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group2
- * @{
- */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group3
- * @{
- */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group5
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
- * @{
- */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
-
-#define RTC_TIMEOUT_VALUE 1000
-
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
- * @{
- */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
- * @{
- */
-
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
- ((REMAP) == RTC_OUTPUT_REMAP_POS1))
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
-
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
-
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
-
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup RTC_Private_Functions
- * @{
- */
-
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h
deleted file mode 100644
index 8031f6b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1104 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rtc_ex.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_RTC_EX_H
-#define __STM32H7xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
- * @{
- */
-/**
- * @brief RTC Tamper structure definition
- */
-typedef struct
-{
- uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
-
- uint32_t Interrupt; /*!< Specifies the Tamper Interrupt.
- This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */
-
- uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
-
- uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
- This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */
-
- uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
- This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */
-
- uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
- This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
- uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
- This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
- uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
- This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
- uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
- This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
-
- uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
- This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
- * @{
- */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions
- * @{
- */
-#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
-#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
-#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
-#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
- * @{
- */
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-#define RTC_BKP_DR20 ((uint32_t)0x00000014)
-#define RTC_BKP_DR21 ((uint32_t)0x00000015)
-#define RTC_BKP_DR22 ((uint32_t)0x00000016)
-#define RTC_BKP_DR23 ((uint32_t)0x00000017)
-#define RTC_BKP_DR24 ((uint32_t)0x00000018)
-#define RTC_BKP_DR25 ((uint32_t)0x00000019)
-#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
-#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
-#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
-#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
-#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
-#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
- *
- * @{
- */
-#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
- * @{
- */
-#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
- * @{
- */
-#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
-#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
-#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
- * @{
- */
-#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
-#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
-#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
-#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
- * @{
- */
-#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
-#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
-* @{
-*/
-#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
-#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
- * @{
- */
-#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active level. */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
- * @{
- */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
- * @{
- */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
- * @{
- */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
- * @{
- */
-#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
- * @{
- */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
- * @{
- */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 8s, else 2exp18 RTCCLK seconds */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
- * @{
- */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
-#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
- * @{
- */
-#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
-#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
- * @brief Disable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
- * @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Wake Up timer interrupt is enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable the RTC Tamper1 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
-
-/**
- * @brief Disable the RTC Tamper1 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
-
-/**
- * @brief Enable the RTC Tamper2 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
-
-/**
- * @brief Disable the RTC Tamper2 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
-
-/**
- * @brief Enable the RTC Tamper3 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
-
-/**
- * @brief Disable the RTC Tamper3 input detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
-
-/**
- * @brief Enable the RTC Tamper interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: All tampers interrupts
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Tamper interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: All tampers interrupts
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
- ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
- (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt is enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP: All tampers interrupts
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F: Tamper1 flag
- * @arg RTC_FLAG_TAMP2F: Tamper2 flag
- * @arg RTC_FLAG_TAMP3F: Tamper3 flag
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F: Tamper1 flag
- * @arg RTC_FLAG_TAMP2F: Tamper2 flag
- * @arg RTC_FLAG_TAMP3F: Tamper3 flag
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
- * @brief Disable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Time Stamp interrupt is enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable the RTC internal TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
-
-/**
- * @brief Disable the RTC internal TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
-
-/**
- * @brief Get the selected RTC Internal Time Stamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_ITSF
- * @retval None
- */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Internal Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
- * This parameter can be:
- * @arg RTC_FLAG_ITSF
- * @retval None
- */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable the RTC calibration output.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
- * @brief Disable the calibration output.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
- * @brief Enable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
- * @brief Disable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
- * @brief Get the selected RTC shift operation's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_SHPF
- * @retval None
- */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable event on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable event on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-/**
- * @brief Enable event on the RTC WakeUp Timer associated D3 Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT() (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable event on the RTC WakeUp Timer associated D3 Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * This parameter can be:
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Clear the RTC WakeUp Timer associated Exti line flag.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.
- * @retval Line Status
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG() (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Clear the RTC WakeUp Timer associated D3 Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG() (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-
-/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
-/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
- * @retval Line Status
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
- * @{
- */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-
-
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/* RTC Wake-up functions ******************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/* Extended Control functions ************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group3
- * @{
- */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/* Extended RTC features functions *******************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group4
- * @{
- */
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
- * @{
- */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Wakeup event */
-
-/* Masks Definition */
-#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
- * @{
- */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
- * @{
- */
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))
-
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))
-
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-
-#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
- ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-
-#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
- ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
-
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
- ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
- ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
- ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
-
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
- ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h
deleted file mode 100644
index 11f5259..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h
+++ /dev/null
@@ -1,902 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sai.h
- * @author MCD Application Team
- * @brief Header file of SAI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SAI_H
-#define __STM32H7xx_HAL_SAI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SAI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SAI_Exported_Types SAI Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
- HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
- HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
- HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
- HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
-} HAL_SAI_StateTypeDef;
-
-/**
- * @brief SAI Callback prototype
- */
-typedef void (*SAIcallback)(void);
-
-/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
- * @brief SAI PDM Init structure definition
- * @{
- */
-typedef struct
-{
- FunctionalState Activation; /*!< Enable/Disable PDM interface */
- uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
- uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
- This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
-} SAI_PdmInitTypeDef;
-/**
- * @}
- */
-
-
-/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
- * @brief SAI Init Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
- This parameter can be a value of @ref SAI_Block_Mode */
-
- uint32_t Synchro; /*!< Specifies SAI Block synchronization
- This parameter can be a value of @ref SAI_Block_Synchronization */
-
- uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
- for BlockA and BlockB
- This parameter can be a value of @ref SAI_Block_SyncExt
- @note: If both audio blocks of same SAI are used, this parameter has
- to be set to the same value for each audio block */
-
- uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
- This parameter can be a value of @ref SAI_Block_Output_Drive
- @note this value has to be set before enabling the audio block
- but after the audio block configuration. */
-
- uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
- This parameter can be a value of @ref SAI_Block_NoDivider
- @note: If bit NOMCK in the SAI_xCR1 register is cleared, the frame length
- should be aligned to a number equal to a power of 2, from 8 to 256.
- If bit NOMCK in the SAI_xCR1 register is set, the frame length can
- take any of the values without constraint since the input clock of
- the audio block should be equal to the bit clock.
- There is no MCLK_x clock which can be output. */
-
- uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
- This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
-
- uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
- This parameter can be a value of @ref SAI_Audio_Frequency */
-
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
-
- uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
- This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
-
- uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
- This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
-
- uint32_t CompandingMode; /*!< Specifies the companding mode type.
- This parameter can be a value of @ref SAI_Block_Companding_Mode */
-
- uint32_t TriState; /*!< Specifies the companding mode type.
- This parameter can be a value of @ref SAI_TRIState_Management */
-
- SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
-
- /* This part of the structure is automatically filled if your are using the high level initialisation
- function HAL_SAI_InitProtocol */
-
- uint32_t Protocol; /*!< Specifies the SAI Block protocol.
- This parameter can be a value of @ref SAI_Block_Protocol */
-
- uint32_t DataSize; /*!< Specifies the SAI Block data size.
- This parameter can be a value of @ref SAI_Block_Data_Size */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
-
- uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
- This parameter can be a value of @ref SAI_Block_Clock_Strobing */
-} SAI_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
- * @brief SAI Frame Init structure definition
- * @{
- */
-typedef struct
-{
-
- uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
- This parameter must be a number between Min_Data = 8 and Max_Data = 256.
- @note: If master clock MCLK_x pin is declared as an output, the frame length
- should be aligned to a number equal to power of 2 in order to keep
- in an audio frame, an integer number of MCLK pulses by bit Clock. */
-
- uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
- This Parameter specifies the length in number of bit clock (SCK + 1)
- of the active level of FS signal in audio frame.
- This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
-
- uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
- This parameter can be a value of @ref SAI_Block_FS_Definition */
-
- uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
- This parameter can be a value of @ref SAI_Block_FS_Polarity */
-
- uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
- This parameter can be a value of @ref SAI_Block_FS_Offset */
-
-} SAI_FrameInitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
- * @brief SAI Block Slot Init Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
- This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
-
- uint32_t SlotSize; /*!< Specifies the Slot Size.
- This parameter can be a value of @ref SAI_Block_Slot_Size */
-
- uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
- This parameter can be a value of @ref SAI_Block_Slot_Active */
-} SAI_SlotInitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
- * @brief SAI handle Structure definition
- * @{
- */
-typedef struct __SAI_HandleTypeDef
-{
- SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
-
- SAI_InitTypeDef Init; /*!< SAI communication parameters */
-
- SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
-
- SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
-
- uint16_t XferSize; /*!< SAI transfer size */
-
- uint16_t XferCount; /*!< SAI transfer counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
-
- SAIcallback mutecallback; /*!< SAI mute callback */
-
- void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
-
- HAL_LockTypeDef Lock; /*!< SAI locking object */
-
- __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
-
- __IO uint32_t ErrorCode; /*!< SAI Error code */
-} SAI_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SAI_Exported_Constants SAI Exported Constants
- * @{
- */
-
-/** @defgroup SAI_Error_Code SAI Error Code
- * @{
- */
-#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */
-#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */
-#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */
-#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */
-#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */
-#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
-#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_SyncExt SAI External synchronisation
- * @{
- */
-#define SAI_SYNCEXT_DISABLE 0
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
-/**
- * @}
- */
-
-/** @defgroup SAI_Protocol SAI Supported protocol
- * @{
- */
-#define SAI_I2S_STANDARD 0
-#define SAI_I2S_MSBJUSTIFIED 1
-#define SAI_I2S_LSBJUSTIFIED 2
-#define SAI_PCM_LONG 3
-#define SAI_PCM_SHORT 4
-/**
- * @}
- */
-
-/** @defgroup SAI_Protocol_DataSize SAI protocol data size
- * @{
- */
-#define SAI_PROTOCOL_DATASIZE_16BIT 0
-#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
-#define SAI_PROTOCOL_DATASIZE_24BIT 2
-#define SAI_PROTOCOL_DATASIZE_32BIT 3
-/**
- * @}
- */
-
-/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
- * @{
- */
-#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
-#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
-#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
-#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
-#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
-#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
-#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
-#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
-#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
-#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
- * @{
- */
-#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)
-#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)
-/**
- * @}
- */
-
-/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
- * @{
- */
-#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)
-#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)
-#define SAI_PDM_CLOCK3_ENABLE ((uint32_t)SAI_PDMCR_CKEN3)
-#define SAI_PDM_CLOCK4_ENABLE ((uint32_t)SAI_PDMCR_CKEN4)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mode SAI Block Mode
- * @{
- */
-#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
-#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
-#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
-#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Protocol SAI Block Protocol
- * @{
- */
-#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
-#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
-#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Data_Size SAI Block Data Size
- * @{
- */
-#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
-#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
-#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
-#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
- * @{
- */
-#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
-#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
- * @{
- */
-#define SAI_CLOCKSTROBING_FALLINGEDGE 0
-#define SAI_CLOCKSTROBING_RISINGEDGE 1
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
- * @{
- */
-#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */
-#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
-#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
- * @{
- */
-#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
-#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK)
-/**
- * @}
- */
-
-
-/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
- * @{
- */
-#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
-#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
- * @{
- */
-#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
-#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
- * @{
- */
-#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
-#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
-/**
- * @}
- */
-
-
- /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
- * @{
- */
-#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
-#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
-#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
- * @{
- */
-#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
-#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
-#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
-#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
-#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
-#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
-#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
-#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
-#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
-#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
-#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
-#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
-#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
-#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
-#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
-#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
-#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
-#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
-/**
- * @}
- */
-
-/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
- * @{
- */
-#define SAI_STEREOMODE ((uint32_t)0x00000000U)
-#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
-/**
- * @}
- */
-
-/** @defgroup SAI_TRIState_Management SAI TRIState Management
- * @{
- */
-#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
-#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
- * @{
- */
-#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
-#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
-#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
- * @{
- */
-#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)
-#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
-#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
-#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
-#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
- * @{
- */
-#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)
-#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
- * @{
- */
-#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
-#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
-#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
-#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
-#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
-#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
-#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
- * @{
- */
-#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
-#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
-#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
-#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
-#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
-#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
-#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
-/**
- * @}
- */
-
-/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
- * @{
- */
-#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
-#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
-#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
-#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
-#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
-#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SAI_Exported_Macros SAI Exported Macros
- * @brief macros to handle interrupts and specific configurations
- * @{
- */
-
-/** @brief Reset SAI handle state.
- * @param __HANDLE__ specifies the SAI Handle.
- * @retval None
- */
-#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
-
-/** @brief Enable or disable the specified SAI interrupts.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
- * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
- * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
- * @arg SAI_IT_FREQ: FIFO request interrupt enable
- * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
- * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
- * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
- * @retval None
- */
-#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
-#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified SAI interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __INTERRUPT__ specifies the SAI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
- * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
- * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
- * @arg SAI_IT_FREQ: FIFO request interrupt enable
- * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
- * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
- * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SAI flag is set or not.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
- * @arg SAI_FLAG_MUTEDET: Mute detection flag.
- * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
- * @arg SAI_FLAG_FREQ: FIFO request flag.
- * @arg SAI_FLAG_CNRDY: Codec not ready flag.
- * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
- * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified SAI pending flag.
- * @param __HANDLE__ specifies the SAI Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
- * @arg SAI_FLAG_MUTEDET: Clear Mute detection
- * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
- * @arg SAI_FLAG_FREQ: Clear FIFO request
- * @arg SAI_FLAG_CNRDY: Clear Codec not ready
- * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
- * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
- *
- * @retval None
- */
-#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
-
-#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
-#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
-
- /**
- * @}
- */
-
-/* Include SAI HAL Extension module */
-#include "stm32h7xx_hal_sai_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SAI_Exported_Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-
-/** @addtogroup SAI_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
-HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
-void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
-void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
-
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-
-/** @addtogroup SAI_Exported_Functions_Group2
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
-
-/* Abort function */
-HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
-
-/* Mute management */
-HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
-HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
-HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
-
-/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
-void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
-void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
-/**
- * @}
- */
-
-/** @addtogroup SAI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
-uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup SAI_Private_Macros
- * @{
- */
-#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
- ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
- ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
-
-#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
- ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
- ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
- ((PROTOCOL) == SAI_PCM_LONG) ||\
- ((PROTOCOL) == SAI_PCM_SHORT))
-
-#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
- ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
-
-#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
- ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
-
-#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
- ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
-
-#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U))
-
-#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
- (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE | \
- SAI_PDM_CLOCK3_ENABLE | SAI_PDM_CLOCK4_ENABLE)) == 0U))
-
-#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
- ((MODE) == SAI_MODEMASTER_RX) || \
- ((MODE) == SAI_MODESLAVE_TX) || \
- ((MODE) == SAI_MODESLAVE_RX))
-
-#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
- ((PROTOCOL) == SAI_AC97_PROTOCOL) || \
- ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
-
-#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
- ((DATASIZE) == SAI_DATASIZE_10) || \
- ((DATASIZE) == SAI_DATASIZE_16) || \
- ((DATASIZE) == SAI_DATASIZE_20) || \
- ((DATASIZE) == SAI_DATASIZE_24) || \
- ((DATASIZE) == SAI_DATASIZE_32))
-
-#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
- ((BIT) == SAI_FIRSTBIT_LSB))
-
-#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
- ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
-
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
- ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
-
-#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
- ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
-
-#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
- ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
-
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
-
-#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
- ((VALUE) == SAI_LAST_SENT_VALUE))
-
-#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
- ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
- ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
- ((MODE) == SAI_ALAW_2CPL_COMPANDING))
-
-#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
- ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
-
-#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
- ((STATE) == SAI_OUTPUT_RELEASED))
-
-#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
- ((MODE) == SAI_STEREOMODE))
-
-#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
-
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
-
-#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
- ((SIZE) == SAI_SLOTSIZE_16B) || \
- ((SIZE) == SAI_SLOTSIZE_32B))
-
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
-
-#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
- ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
-
-#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
- ((POLARITY) == SAI_FS_ACTIVE_HIGH))
-
-#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
- ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
-
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63)
-
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
-
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SAI_Private_Functions SAI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SAI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h
deleted file mode 100644
index 5522bfa..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sai_ex.h
- * @author MCD Application Team
- * @brief Header file of SAI HAL extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SAI_EX_H
-#define __STM32H7xx_HAL_SAI_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SAIEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
- * @{
- */
-
-/**
- * @brief PDM microphone delay structure definition
- */
-typedef struct
-{
- uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
-
- uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
- This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
-
- uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
- This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
-}SAIEx_PdmMicDelayParamTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
- * @{
- */
-
-/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
- * @{
- */
-
-#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SAI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h
deleted file mode 100644
index 53693ef..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sd.h
- * @author MCD Application Team
- * @brief Header file of SD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_SD_H
-#define STM32H7xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_sdmmc.h"
-#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)
-#include "stm32h7xx_ll_delayblock.h"
-#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SD SD
- * @brief SD HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SD_Exported_Types SD Exported Types
- * @{
- */
-
-/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
- HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
- HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
- HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
- HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
- HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
- HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
-}HAL_SD_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
- HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
- HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
- HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
- HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
- HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
- HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
- HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
-}HAL_SD_CardStateTypedef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
- * @{
- */
-#define SD_InitTypeDef SDMMC_InitTypeDef
-#define SD_TypeDef SDMMC_TypeDef
-
-/**
- * @brief SD Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t CardVersion; /*!< Specifies the card version */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
- uint32_t CardSpeed; /*!< Specifies the card Speed */
-
-}HAL_SD_CardInfoTypeDef;
-
-/**
- * @brief SD handle Structure definition
- */
-typedef struct __SD_HandleTypeDef
-{
- SD_TypeDef *Instance; /*!< SD registers base address */
-
- SD_InitTypeDef Init; /*!< SD required parameters */
-
- HAL_LockTypeDef Lock; /*!< SD locking object */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< SD Tx Transfer size */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< SD Rx Transfer size */
-
- __IO uint32_t Context; /*!< SD transfer context */
-
- __IO HAL_SD_StateTypeDef State; /*!< SD card State */
-
- __IO uint32_t ErrorCode; /*!< SD Card Error codes */
-
- HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
-
- uint32_t CSD[4]; /*!< SD card specific data table */
-
- uint32_t CID[4]; /*!< SD card identification number table */
-
-}SD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGroup; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_SD_CardCSDTypedef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_SD_CardCIDTypedef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
- __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */
- __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
- __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
-}HAL_SD_CardStatusTypedef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
- * @{
- */
-
-#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
-
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
- * @{
- */
-#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
- * @{
- */
-#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
- * @{
- */
-#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */
-#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */
-#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
- and <104Mo/s for SDR104, Spec version 3.01 */
-
-#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */
-#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
-#define CARD_SECURED ((uint32_t)0x00000003U)
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
- * @{
- */
-#define CARD_V1_X ((uint32_t)0x00000000U)
-#define CARD_V2_X ((uint32_t)0x00000001U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset SD handle state.
- * @param __HANDLE__ : SD handle.
- * @retval None
- */
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-
-/**
- * @brief Enable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
- * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
- * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval The new state of SD FLAG (SET or RESET).
- */
-#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the SD's pending flags.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval None
- */
-#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
- * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval The new state of SD IT (SET or RESET).
- */
-#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Include SD HAL Extension module */
-#include "stm32h7xx_hal_sd_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
- * @{
- */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-
-#if (USE_SD_TRANSCEIVER != 0U)
-/* Callback to switch in 1.8V mode */
-void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
-#endif /* USE_SD_TRANSCEIVER */
-
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group4 SD card related functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32H7xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h
deleted file mode 100644
index 48732ed..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sd_ex.h
- * @author MCD Application Team
- * @brief Header file of SD HAL extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_SD_EX_H
-#define STM32H7xx_HAL_SD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SD_EX SD_EX
- * @brief SD HAL extended module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDEx_Exported_Types SDEx Exported Types
- * @{
- */
-
-/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
- * @{
- */
-typedef enum
-{
- SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
- SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */
-
-}HAL_SDEx_DMABuffer_MemoryTypeDef;
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
- * @{
- */
-
-/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
- * @{
- */
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
-
-void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* stm32h7xx_HAL_SDEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h
deleted file mode 100644
index b4098a9..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sdram.h
- * @author MCD Application Team
- * @brief Header file of SDRAM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SDRAM_H
-#define __STM32H7xx_HAL_SDRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_fmc.h"
-#include "stm32h7xx_hal_mdma.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SDRAM
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
- * @{
- */
-
-/**
- * @brief HAL SDRAM State structure definition
- */
-typedef enum
-{
- HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
- HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
- HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
- HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
- HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
- HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
-
-}HAL_SDRAM_StateTypeDef;
-
-/**
- * @brief SDRAM handle Structure definition
- */
-typedef struct
-{
- FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
-
- __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
-
- HAL_LockTypeDef Lock; /*!< SDRAM locking object */
-
- MDMA_HandleTypeDef *hmdma; /*!< Pointer MDMA handler */
-
-}SDRAM_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
- * @{
- */
-
-/** @brief Reset SDRAM handle state
- * @param __HANDLE__: specifies the SDRAM handle.
- * @retval None
- */
-#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
- * @{
- */
-
-/** @addtogroup SDRAM_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
-HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
-void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
-void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
-
-void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
-void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
-void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
-void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
-
-/**
- * @}
- */
-
-/** @addtogroup SDRAM_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-/**
- * @}
- */
-
-/** @addtogroup SDRAM_Exported_Functions_Group3
- * @{
- */
-/* SDRAM Control functions *****************************************************/
-HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
-HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
-HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
-HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
-uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
-
-/**
- * @}
- */
-
-/** @addtogroup SDRAM_Exported_Functions_Group4
- * @{
- */
-/* SDRAM State functions ********************************************************/
-HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SDRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h
deleted file mode 100644
index cc6ad2d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h
+++ /dev/null
@@ -1,1088 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smartcard.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SMARTCARD_H
-#define __STM32H7xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
- * @{
- */
-
-/**
- * @brief SMARTCARD Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
- The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits.
- This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
-
- uint16_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref SMARTCARD_Parity
- @note The parity is enabled by default (PCE is forced to 1).
- Since the WordLength is forced to 8 bits + parity, M is
- forced to 1 and the parity bit is the 9th bit. */
-
- uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref SMARTCARD_Mode */
-
- uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
- uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
- uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
- uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
-
- uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */
-
- uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
-
- uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
- in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_Enable */
-
- uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
- This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
-
- uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
- it is used to implement the Character Wait Time (CWT) and
- Block Wait Time (BWT). It is coded over 24 bits. */
-
- uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
- This parameter can be any value from 0x0 to 0xFF */
-
- uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
- receive and transmit mode). When set to 0, retransmission is
- disabled. Otherwise, its maximum value is 7 (before signalling
- an error) */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
- of @ref SMARTCARD_FIFO_mode */
-
- uint32_t TXFIFOThreshold; /*!< Specifies the TXFIFO threshold level.
- This parameter can be a value of @ref SMARTCARD_TXFIFO_threshold_level */
-
- uint32_t RXFIFOThreshold; /*!< Specifies the RXFIFO threshold level.
- This parameter can be a value of @ref SMARTCARD_RXFIFO_threshold_level */
-
-}SMARTCARD_InitTypeDef;
-
-/**
- * @brief SMARTCARD advanced features initalization structure definition
- */
-typedef struct
-{
- uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
- advanced features may be initialized at the same time. This parameter
- can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Tx_Inv */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Rx_Inv */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
- vs negative/inverted logic).
- This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref SMARTCARD_MSB_First */
-
- uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
- relevant flag is available) or once guard time period has elapsed.
- This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
-}SMARTCARD_AdvFeatureInitTypeDef;
-
-/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
- * - gState contains SMARTCARD state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
-
-/**
- * @brief HAL SMARTCARD Error Code structure definition
- */
-typedef enum
-{
- HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
- HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
- HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
- HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
- HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */
- HAL_SMARTCARD_ERROR_UDR = 0x11, /*!< SPI UnderRun error */
- HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */
-}HAL_SMARTCARD_ErrorTypeDef;
-
-/**
- * @brief SMARTCARD handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- uint32_t ErrorCode; /*!< SmartCard Error code */
-
-}SMARTCARD_HandleTypeDef;
-
-/**
- * @brief SMARTCARD clock sources
- */
-typedef enum
-{
- SMARTCARD_CLOCKSOURCE_D2PCLK1 = 0x00, /*!< Domain2 PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_D2PCLK2 = 0x01, /*!< Domain2 PCLK2 clock source */
- SMARTCARD_CLOCKSOURCE_D3PCLK1 = 0x02, /*!< Domain3 PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_PLL2Q = 0x04, /*!< PLL2Q clock source */
- SMARTCARD_CLOCKSOURCE_HSI = 0x08, /*!< HSI clock source */
- SMARTCARD_CLOCKSOURCE_CSI = 0x10, /*!< CSI clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x20, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_PLL3Q = 0x40, /*!< PCLK2 clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x80 /*!< Undefined clock source */
-}SMARTCARD_ClockSourceTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
- * @{
- */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
- * @{
- */
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
- * @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
- * @{
- */
-#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
- * @{
- */
-#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
- * @{
- */
-#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_FIFO_mode SMARTCARD FIFO mode
- * @brief SMARTCARD FIFO mode
- * @{
- */
-#define SMARTCARD_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
-#define SMARTCARD_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN) /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
- * @brief SMARTCARD TXFIFO level
- * @{
- */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000) /*!< TXFIFO threshold 1 eighth full configuration */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0) /*!< TXFIFO threshold 1 quart full configuration */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1) /*!< TXFIFO threshold half full configuration */
-#define SMARTCARD_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO threshold 3 quarts full configuration */
-#define SMARTCARD_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2) /*!< TXFIFO threshold 7 eighth full configuration */
-#define SMARTCARD_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
- * @brief SMARTCARD RXFIFO level
- * @{
- */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000) /*!< RXFIFO threshold 1 eighth full configuration */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0) /*!< RXFIFO threshold 1 quart full configuration */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1) /*!< RXFIFO threshold half full configuration */
-#define SMARTCARD_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO threshold 3 quarts full configuration */
-#define SMARTCARD_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2) /*!< RXFIFO threshold 7 eighth full configuration */
-#define SMARTCARD_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes Full */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
- * @{
- */
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
-/**
- * @}
- */
-
-
-/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
- * @{
- */
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
-#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
- * @{
- */
-#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */
-#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
- * @{
- */
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
- * @{
- */
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
- * @{
- */
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
- * @{
- */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
- * @{
- */
-#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive data flush request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
- * @{
- */
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
- * @{
- */
-#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
- * @{
- */
-#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
- * @{
- */
-#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
- * @{
- */
-
-/** @brief Reset SMARTCARD handle state.
- * @param __HANDLE__: SMARTCARD handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- } while(0)
-
-/** @brief Flush the Smartcard Data registers.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
- } while(0)
-
-/** @brief Clear the specified SMARTCARD pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
- * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
- * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
- * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
- * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
- * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
- * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
- * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
- * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
-
-/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
-
-/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
-
-/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
-
-/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
-
-/** @brief Check whether the specified Smartcard flag is set or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag
- * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
- * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
- * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
- * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
- * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
- * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
- * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
- * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
- * @arg @ref SMARTCARD_FLAG_NE Noise error flag
- * @arg @ref SMARTCARD_FLAG_FE Framing error flag
- * @arg @ref SMARTCARD_FLAG_PE Parity error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief Enable the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief Disable the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-
-/** @brief Check whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __IT__: specifies the SMARTCARD interrupt to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt
- * @arg @ref SMARTCARD_IT_NE Noise error interrupt
- * @arg @ref SMARTCARD_IT_FE Framing error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __IT__: specifies the SMARTCARD interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
-
-
-/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
- * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
- * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
- * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
- * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
- * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
- * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
- * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
- * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Clear the SMARTCARD TX FIFO empty clear flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__) __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)
-
-/** @brief Set a specific SMARTCARD request flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __REQ__: specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
- * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief Enable the SMARTCARD one bit sample method.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the SMARTCARD one bit sample method.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable the USART associated to the SMARTCARD Handle.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private macros -------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
- * @{
- */
-
-/** @brief Check the Baud rate range.
- * @param __BAUDRATE__: Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
- * divided by the smallest oversampling used on the SMARTCARD (i.e. 8).
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
-
-/** @brief Check the block length range.
- * @note The maximum SMARTCARD block length is 0xFF.
- * @param __LENGTH__: block length.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
-
-/** @brief Check the receiver timeout value.
- * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
- * @param __TIMEOUTVALUE__: receiver timeout value.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
-
-/** @brief Check the SMARTCARD autoretry counter value.
- * @note The maximum number of retransmissions is 0x7.
- * @param __COUNT__: number of retransmissions.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
-
-/**
- * @brief Ensure that SMARTCARD frame length is valid.
- * @param __LENGTH__: SMARTCARD frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-
-/**
- * @brief Ensure that SMARTCARD frame number of stop bits is valid.
- * @param __STOPBITS__: SMARTCARD frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
- ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
-
-/**
- * @brief Ensure that SMARTCARD frame parity is valid.
- * @param __PARITY__: SMARTCARD frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
- ((__PARITY__) == SMARTCARD_PARITY_ODD))
-
-/**
- * @brief Ensure that SMARTCARD communication mode is valid.
- * @param __MODE__: SMARTCARD communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
-
-/**
- * @brief Ensure that SMARTCARD frame polarity is valid.
- * @param __CPOL__: SMARTCARD frame polarity.
- * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-
-/**
- * @brief Ensure that SMARTCARD frame phase is valid.
- * @param __CPHA__: SMARTCARD frame phase.
- * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
- */
-#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-
-/**
- * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
- * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting.
- * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
- */
-#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
- ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame sampling is valid.
- * @param __ONEBIT__: SMARTCARD frame sampling.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD NACK transmission setting is valid.
- * @param __NACK__: SMARTCARD NACK transmission setting.
- * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
- */
-#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
- ((__NACK__) == SMARTCARD_NACK_DISABLE))
-
-/**
- * @brief Ensure that SMARTCARD receiver timeout setting is valid.
- * @param __TIMEOUT__: SMARTCARD receiver timeout setting.
- * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
- */
-#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD advanced features initialization is valid.
- * @param __INIT__: SMARTCARD advanced features initialization.
- * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
- SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
- SMARTCARD_ADVFEATURE_SWAP_INIT | \
- SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
- SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-
-/**
- * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
- * @param __TXINV__: SMARTCARD frame TX inversion setting.
- * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
- ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
- * @param __RXINV__: SMARTCARD frame RX inversion setting.
- * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
- ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame data inversion setting is valid.
- * @param __DATAINV__: SMARTCARD frame data inversion setting.
- * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
- ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
- * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting.
- * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
- ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame overrun setting is valid.
- * @param __OVERRUN__: SMARTCARD frame overrun setting.
- * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
- */
-#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
- ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
- * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
- * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting.
- * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
- * @brief Ensure that SMARTCARD frame MSB first setting is valid.
- * @param __MSBFIRST__: SMARTCARD frame MSB first setting.
- * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD request parameter is valid.
- * @param __PARAM__: SMARTCARD request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
-
-/**
- * @brief Ensure that SMARTCARD FIFO mode is valid.
- * @param __STATE__: SMARTCARD FIFO mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_SMARTCARD_FIFO_MODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
- ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
- * @param __THRESHOLD__: SMARTCARD TXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
-
-/**
- * @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
- * @param __THRESHOLD__: SMARTCARD RXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
-
-/**
- * @}
- */
-
-/* Include SMARTCARD HAL Extended module */
-#include "stm32h7xx_hal_smartcard_ex.h"
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
- * @{
- */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group4
- * @{
- */
-
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h
deleted file mode 100644
index e36e075..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smartcard_ex.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SMARTCARD_EX_H
-#define __STM32H7xx_HAL_SMARTCARD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARDEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
- * @{
- */
-
-/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
- * @{
- */
-#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
-#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
- * @{
- */
-#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
-#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
-#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
-#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
-#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
-#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
-#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
-#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
-#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
-#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
-#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
-#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
-#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
-#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
-#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
-#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
-#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
-#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
-#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Fullflag */
-#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
- * Elements values convention: 000ZZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5 bits)
- * - XX : Interrupt source register (2 bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZZ : Flag position in the ISR register(5 bits)
- * @{
- */
-#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */
-#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */
-#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */
-
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */
-#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */
-#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */
-
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */
-
-#define SMARTCARD_IT_RXFF ((uint16_t)0x183F)
-#define SMARTCARD_IT_TXFE ((uint16_t)0x173E)
-#define SMARTCARD_IT_RXFT ((uint16_t)0x187C)
-#define SMARTCARD_IT_TXFT ((uint16_t)0x1B77)
-#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
- * @{
- */
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
-#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
-#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
-#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< SMARTCARD TXFIFO empty clear flag */
-#define SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF /*!< SMARTCARD UnderRun Error Clear Flag */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macros -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
- * @{
- */
-
-/** @brief Report the SMARTCARD clock source.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __CLOCKSOURCE__: output variable.
- * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
- */
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART1CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART2CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART3CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
- case RCC_USART6CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
- break; \
- case RCC_USART6CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
- break; \
- case RCC_USART6CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART6CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART6CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- } while(0)
-
-/** @brief Set the Transmission Completion flag
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @retval None
- */
-#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
- do { \
- if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
- { \
- (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
- } \
- else \
- { \
- assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
- } \
- } while(0)
-
-/** @brief Return the transmission completion flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
- * @retval Transmission completion flag
- */
-#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
- (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
-
-/**
- * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
- * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
- * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
- */
-#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
- ((__TXCOMPLETE__) == SMARTCARD_TC))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation methods *******************************************************/
-
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
- * @{
- */
-
-/* Peripheral Control functions ***********************************************/
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SMARTCARD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
deleted file mode 100644
index def8987..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
+++ /dev/null
@@ -1,694 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smbus.h
- * @author MCD Application Team
- * @brief Header file of SMBUS HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SMBUS_H
-#define __STM32H7xx_HAL_SMBUS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMBUS
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
- * @{
- */
-
-/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
- * @brief SMBUS Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
- uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
- This parameter can be a value of @ref SMBUS_Analog_Filter */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
- This parameter can be a value of @ref SMBUS_addressing_mode */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref SMBUS_dual_addressing_mode */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref SMBUS_own_address2_masks. */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref SMBUS_nostretch_mode */
-
- uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
- This parameter can be a value of @ref SMBUS_packet_error_check_mode */
-
- uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
- This parameter can be a value of @ref SMBUS_peripheral_mode */
-
- uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
-} SMBUS_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_state_definition HAL state definition
- * @brief HAL State definition
- * @{
- */
-#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
-#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
-#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
- * @brief SMBUS Error Code definition
- * @{
- */
-#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
-#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
-#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
-#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
-#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
-#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
-#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
-/**
- * @}
- */
-
-/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
- * @brief SMBUS handle Structure definition
- * @{
- */
-typedef struct
-{
- I2C_TypeDef *Instance; /*!< SMBUS registers base address */
-
- SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
-
- uint16_t XferSize; /*!< SMBUS transfer size */
-
- __IO uint16_t XferCount; /*!< SMBUS transfer counter */
-
- __IO uint32_t XferOptions; /*!< SMBUS transfer options */
-
- __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
-
- HAL_LockTypeDef Lock; /*!< SMBUS locking object */
-
- __IO uint32_t State; /*!< SMBUS communication state */
-
- __IO uint32_t ErrorCode; /*!< SMBUS Error code */
-
-}SMBUS_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
- * @{
- */
-
-/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
- * @{
- */
-#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
-#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-/**
- * @}
- */
-
-/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
- * @{
- */
-#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
-#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
- * @{
- */
-
-#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
-#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
- * @{
- */
-
-#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
-#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
-#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
-#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
-#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
-#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
-#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
-#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
-/**
- * @}
- */
-
-
-/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
- * @{
- */
-#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
-#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
- * @{
- */
-#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
-#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
- * @{
- */
-#define SMBUS_PEC_DISABLE (0x00000000U)
-#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
- * @{
- */
-#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
- * @{
- */
-
-#define SMBUS_SOFTEND_MODE (0x00000000U)
-#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
-#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
-#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
-/**
- * @}
- */
-
-/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
- * @{
- */
-
-#define SMBUS_NO_STARTSTOP (0x00000000U)
-#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
- * @{
- */
-
-/* List of XferOptions in usage of :
- * 1- Restart condition when direction change
- * 2- No Restart condition in other use cases
- */
-#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
-#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
-#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
-#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
-#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
-#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
-#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
-#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
- * @brief SMBUS Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define SMBUS_IT_ERRI I2C_CR1_ERRIE
-#define SMBUS_IT_TCI I2C_CR1_TCIE
-#define SMBUS_IT_STOPI I2C_CR1_STOPIE
-#define SMBUS_IT_NACKI I2C_CR1_NACKIE
-#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
-#define SMBUS_IT_RXI I2C_CR1_RXIE
-#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
-#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
-#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
-#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
- * @brief Flag definition
- * Elements values convention: 0xXXXXYYYY
- * - XXXXXXXX : Flag mask
- * @{
- */
-
-#define SMBUS_FLAG_TXE I2C_ISR_TXE
-#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
-#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
-#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
-#define SMBUS_FLAG_AF I2C_ISR_NACKF
-#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
-#define SMBUS_FLAG_TC I2C_ISR_TC
-#define SMBUS_FLAG_TCR I2C_ISR_TCR
-#define SMBUS_FLAG_BERR I2C_ISR_BERR
-#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
-#define SMBUS_FLAG_OVR I2C_ISR_OVR
-#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
-#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
-#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
-#define SMBUS_FLAG_DIR I2C_ISR_DIR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
- * @{
- */
-
-/** @brief Reset SMBUS handle state.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-
-/** @brief Enable the specified SMBUS interrupts.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SMBUS_IT_ERRI: Errors interrupt enable
- * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
- * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
- * @arg SMBUS_IT_NACKI: NACK received interrupt enable
- * @arg SMBUS_IT_ADDRI: Address match interrupt enable
- * @arg SMBUS_IT_RXI: RX interrupt enable
- * @arg SMBUS_IT_TXI: TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief Disable the specified SMBUS interrupts.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @param __INTERRUPT__: specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SMBUS_IT_ERRI: Errors interrupt enable
- * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
- * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
- * @arg SMBUS_IT_NACKI: NACK received interrupt enable
- * @arg SMBUS_IT_ADDRI: Address match interrupt enable
- * @arg SMBUS_IT_RXI: RX interrupt enable
- * @arg SMBUS_IT_TXI: TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SMBUS_IT_ERRI: Errors interrupt enable
- * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
- * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
- * @arg SMBUS_IT_NACKI: NACK received interrupt enable
- * @arg SMBUS_IT_ADDRI: Address match interrupt enable
- * @arg SMBUS_IT_RXI: RX interrupt enable
- * @arg SMBUS_IT_TXI: TX interrupt enable
- *
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SMBUS flag is set or not.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SMBUS_FLAG_TXE: Transmit data register empty
- * @arg SMBUS_FLAG_TXIS: Transmit interrupt status
- * @arg SMBUS_FLAG_RXNE: Receive data register not empty
- * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
- * @arg SMBUS_FLAG_AF: NACK received flag
- * @arg SMBUS_FLAG_STOPF: STOP detection flag
- * @arg SMBUS_FLAG_TC: Transfer complete (master mode)
- * @arg SMBUS_FLAG_TCR: Transfer complete reload
- * @arg SMBUS_FLAG_BERR: Bus error
- * @arg SMBUS_FLAG_ARLO: Arbitration lost
- * @arg SMBUS_FLAG_OVR: Overrun/Underrun
- * @arg SMBUS_FLAG_PECERR: PEC error in reception
- * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg SMBUS_FLAG_ALERT: SMBus alert
- * @arg SMBUS_FLAG_BUSY: Bus busy
- * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
- *
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-
-/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
- * @arg SMBUS_FLAG_AF: NACK received flag
- * @arg SMBUS_FLAG_STOPF: STOP detection flag
- * @arg SMBUS_FLAG_BERR: Bus error
- * @arg SMBUS_FLAG_ARLO: Arbitration lost
- * @arg SMBUS_FLAG_OVR: Overrun/Underrun
- * @arg SMBUS_FLAG_PECERR: PEC error in reception
- * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg SMBUS_FLAG_ALERT: SMBus alert
- *
- * @retval None
- */
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Enable the specified SMBUS peripheral.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified SMBUS peripheral.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
- * @param __HANDLE__: specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
- * @{
- */
-
-#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
-
-#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
- ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
-
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
-
-#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
- ((MASK) == SMBUS_OA2_MASK01) || \
- ((MASK) == SMBUS_OA2_MASK02) || \
- ((MASK) == SMBUS_OA2_MASK03) || \
- ((MASK) == SMBUS_OA2_MASK04) || \
- ((MASK) == SMBUS_OA2_MASK05) || \
- ((MASK) == SMBUS_OA2_MASK06) || \
- ((MASK) == SMBUS_OA2_MASK07))
-
-#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
- ((CALL) == SMBUS_GENERALCALL_ENABLE))
-
-#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
- ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
-
-#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
- ((PEC) == SMBUS_PEC_ENABLE))
-
-#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
-
-
-#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
- ((REQUEST) == SMBUS_NO_STARTSTOP))
-
-
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
- IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-
-#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
-#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
-#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-
-#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-
-#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
- * @{
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup Blocking_mode_Polling Blocking mode Polling
- * @{
- */
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
- * @{
- */
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
-
-/* Peripheral State and Errors functions **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
- * @{
- */
-/* Private functions are defined in stm32h7xx_hal_smbus.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
deleted file mode 100644
index 51bb06f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
+++ /dev/null
@@ -1,568 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spdifrx.h
- * @author MCD Application Team
- * @brief Header file of SPDIFRX HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SPDIFRX_H
-#define __STM32H7xx_HAL_SPDIFRX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#if defined (SPDIFRX)
-
-/** @addtogroup SPDIFRX
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
- * @{
- */
-
-/**
- * @brief SPDIFRX Init structure definition
- */
-typedef struct
-{
- uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
- This parameter can be a value of @ref SPDIFRX_Input_Selection */
-
- uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
- This parameter can be a value of @ref SPDIFRX_Max_Retries */
-
- uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
- This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
-
- uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
- This parameter can be a value of @ref SPDIFRX_Channel_Selection */
-
- uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
- This parameter can be a value of @ref SPDIFRX_Data_Format */
-
- uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
- This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
-
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
-
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
-
- uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_V_Mask */
-
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PE_Mask */
- FunctionalState SymbolClockGen; /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
- This parameter can be set to Enable or Disable */
-
- FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
- This parameter can be set to Enable or Disable */
-} SPDIFRX_InitTypeDef;
-
-/**
- * @brief SPDIFRX SetDataFormat structure definition
- */
-typedef struct
-{
- uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
- This parameter can be a value of @ref SPDIFRX_Data_Format */
-
- uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
- This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
-
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
-
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
-
- uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_V_Mask */
-
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PE_Mask */
-
-} SPDIFRX_SetDataFormatTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */
- HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */
- HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */
- HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
- HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
- HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
-} HAL_SPDIFRX_StateTypeDef;
-
-/**
- * @brief SPDIFRX handle Structure definition
- */
-typedef struct
-{
- SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
-
- SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
-
- uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
-
- uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
-
- __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
-
- __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received.
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
- __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
-
- __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received.
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
- DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
-
- __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
-
- __IO uint32_t ErrorCode; /* SPDIFRX Error code */
-
-} SPDIFRX_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
- * @{
- */
-/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
- * @{
- */
-#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
-#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */
-#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
-#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
- * @{
- */
-#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
-#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
-#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
-#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
- * @{
- */
-#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
-#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
-#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
-#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
- * @{
- */
-#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
- * @{
- */
-#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
- * @{
- */
-#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
-#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
-* @{
-*/
-#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
- * @{
- */
-#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
- * @{
- */
-#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
-#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
- * @{
- */
-#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
-#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
-#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
- * @{
- */
-#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
-#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_State SPDIFRX State
- * @{
- */
-
-#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
-#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
-#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
- * @{
- */
-#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
-#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
-#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
-#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
-#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
-#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
-#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
- * @{
- */
-#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
-#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
-#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
-#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
-#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
-#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
-#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
-#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
-#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
- * @{
- */
-
-/** @brief Reset SPDIFRX handle state
- * @param __HANDLE__: SPDIFRX handle.
- * @retval None
- */
-#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
-
-/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @retval None
- */
-#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
-
-/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @retval None
- */
-#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
-
-
-/** @brief Enable the specified SPDIFRX peripheral (RCV State).
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @retval None
- */
-#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
-
-
-/** @brief Enable or disable the specified SPDIFRX interrupts.
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_IT_RXNE
- * @arg SPDIFRX_IT_CSRNE
- * @arg SPDIFRX_IT_PERRIE
- * @arg SPDIFRX_IT_OVRIE
- * @arg SPDIFRX_IT_SBLKIE
- * @arg SPDIFRX_IT_SYNCDIE
- * @arg SPDIFRX_IT_IFEIE
- * @retval None
- */
-#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
-#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
-
-/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_IT_RXNE
- * @arg SPDIFRX_IT_CSRNE
- * @arg SPDIFRX_IT_PERRIE
- * @arg SPDIFRX_IT_OVRIE
- * @arg SPDIFRX_IT_SBLKIE
- * @arg SPDIFRX_IT_SYNCDIE
- * @arg SPDIFRX_IT_IFEIE
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified SPDIFRX flag is set or not.
- * @param __HANDLE__: specifies the SPDIFRX Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPDIFRX_FLAG_RXNE
- * @arg SPDIFRX_FLAG_CSRNE
- * @arg SPDIFRX_FLAG_PERR
- * @arg SPDIFRX_FLAG_OVR
- * @arg SPDIFRX_FLAG_SBD
- * @arg SPDIFRX_FLAG_SYNCD
- * @arg SPDIFRX_FLAG_FERR
- * @arg SPDIFRX_FLAG_SERR
- * @arg SPDIFRX_FLAG_TERR
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg SPDIFRX_FLAG_PERR
- * @arg SPDIFRX_FLAG_OVR
- * @arg SPDIFRX_SR_SBD
- * @arg SPDIFRX_SR_SYNCD
- * @retval None
- */
-#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPDIFRX_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPDIFRX_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
-HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
-HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
-/**
- * @}
- */
-
-/** @addtogroup SPDIFRX_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
-void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
-/**
- * @}
- */
-
-/** @addtogroup SPDIFRX_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
- * @{
- */
-#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
- ((INPUT) == SPDIFRX_INPUT_IN2) || \
- ((INPUT) == SPDIFRX_INPUT_IN3) || \
- ((INPUT) == SPDIFRX_INPUT_IN0))
-
-#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
- ((RET) == SPDIFRX_MAXRETRIES_3) || \
- ((RET) == SPDIFRX_MAXRETRIES_15) || \
- ((RET) == SPDIFRX_MAXRETRIES_63))
-
-#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
- ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
-
-#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
- ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
-
-#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
- ((VAL) == SPDIFRX_VALIDITYMASK_ON))
-
-#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
- ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
-
-#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
- ((CHANNEL) == SPDIFRX_CHANNEL_B))
-
-#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
-
-#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
- ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
-
-#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
- ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
-#define IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPDIFRX */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_HAL_SPDIFRX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h
deleted file mode 100644
index 09d957b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h
+++ /dev/null
@@ -1,983 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SPI_H
-#define __STM32H7xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_Management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_Mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
-
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
- CRC Length is only used with Data8 and Data16, not other data size
- This parameter can be a value of @ref SPI_CRC_length */
-
- uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
- This parameter can be a value of @ref SPI_NSSP_Mode
- This mode is activated by the NSSP bit in the SPIx_CR2 register and
- it takes effect only if the SPI interface is configured as Motorola SPI
- master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
- CPOL setting is ignored). */
-
- uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
- considered as active one.
- This parameter can be a value of @ref SPI_NSS_Polarity */
-
- uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref SPI_Fifo_Threshold */
-
- uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
- This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
-
- uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
- This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
-
- uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
- additionally between active edge of SS and first data transaction start in master mode.
- This parameter can be a value of @ref SPI_Master_SS_Idleness */
-
- uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
- two consecutive data frames in master mode
- This parameter can be a value of @ref SPI_Master_InterData_Idleness */
-
- uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
- in order to avoid overrun condition.
- This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
-
- uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
- This parameter can be a value of @ref SPI_Master_Keep_IO_State */
-
- uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
- This parameter can be a value of @ref SPI_IO_Swap */
-
-} SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum
-{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
-} HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
-
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-} SPI_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_FIFO_Type SPI FIFO Type
- * @{
- */
-#define SPI_LOWEND_FIFO_SIZE 8U
-#define SPI_HIGHEND_FIFO_SIZE 16U
-/**
- * @}
- */
-
-/** @defgroup SPI_Error_Code SPI Error Codes
- * @{
- */
-#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
-#define HAL_SPI_ERROR_UDR (0x00000080U) /*!< Underrun error */
-#define HAL_SPI_ERROR_TIMEOUT (0x00000100U) /*!< Timeout error */
-#define HAL_SPI_ERROR_UNKNOW (0x00000200U) /*!< Unknow error */
-#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400U) /*!< Requested operation not supported */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE (0x00000000U)
-#define SPI_MODE_MASTER SPI_CFG2_MASTER
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES (0x00000000U)
-#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
-#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_4BIT (0x00000003U)
-#define SPI_DATASIZE_5BIT (0x00000004U)
-#define SPI_DATASIZE_6BIT (0x00000005U)
-#define SPI_DATASIZE_7BIT (0x00000006U)
-#define SPI_DATASIZE_8BIT (0x00000007U)
-#define SPI_DATASIZE_9BIT (0x00000008U)
-#define SPI_DATASIZE_10BIT (0x00000009U)
-#define SPI_DATASIZE_11BIT (0x0000000AU)
-#define SPI_DATASIZE_12BIT (0x0000000BU)
-#define SPI_DATASIZE_13BIT (0x0000000CU)
-#define SPI_DATASIZE_14BIT (0x0000000DU)
-#define SPI_DATASIZE_15BIT (0x0000000EU)
-#define SPI_DATASIZE_16BIT (0x0000000FU)
-#define SPI_DATASIZE_17BIT (0x00000010U)
-#define SPI_DATASIZE_18BIT (0x00000011U)
-#define SPI_DATASIZE_19BIT (0x00000012U)
-#define SPI_DATASIZE_20BIT (0x00000013U)
-#define SPI_DATASIZE_21BIT (0x00000014U)
-#define SPI_DATASIZE_22BIT (0x00000015U)
-#define SPI_DATASIZE_23BIT (0x00000016U)
-#define SPI_DATASIZE_24BIT (0x00000017U)
-#define SPI_DATASIZE_25BIT (0x00000018U)
-#define SPI_DATASIZE_26BIT (0x00000019U)
-#define SPI_DATASIZE_27BIT (0x0000001AU)
-#define SPI_DATASIZE_28BIT (0x0000001BU)
-#define SPI_DATASIZE_29BIT (0x0000001CU)
-#define SPI_DATASIZE_30BIT (0x0000001DU)
-#define SPI_DATASIZE_31BIT (0x0000001EU)
-#define SPI_DATASIZE_32BIT (0x0000001FU)
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW (0x00000000U)
-#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE (0x00000000U)
-#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CFG2_SSM
-#define SPI_NSS_HARD_INPUT (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
-/**
- * @}
- */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
- * @{
- */
-#define SPI_NSS_PULSE_DISABLE (0x00000000U)
-#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 (0x10000000U)
-#define SPI_BAUDRATEPRESCALER_8 (0x20000000U)
-#define SPI_BAUDRATEPRESCALER_16 (0x30000000U)
-#define SPI_BAUDRATEPRESCALER_32 (0x40000000U)
-#define SPI_BAUDRATEPRESCALER_64 (0x50000000U)
-#define SPI_BAUDRATEPRESCALER_128 (0x60000000U)
-#define SPI_BAUDRATEPRESCALER_256 (0x70000000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB (0x00000000U)
-#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_Mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE (0x00000000U)
-#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
- * @{
- */
-#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
-#define SPI_CRC_LENGTH_4BIT (0x00030000U)
-#define SPI_CRC_LENGTH_5BIT (0x00040000U)
-#define SPI_CRC_LENGTH_6BIT (0x00050000U)
-#define SPI_CRC_LENGTH_7BIT (0x00060000U)
-#define SPI_CRC_LENGTH_8BIT (0x00070000U)
-#define SPI_CRC_LENGTH_9BIT (0x00080000U)
-#define SPI_CRC_LENGTH_10BIT (0x00090000U)
-#define SPI_CRC_LENGTH_11BIT (0x000A0000U)
-#define SPI_CRC_LENGTH_12BIT (0x000B0000U)
-#define SPI_CRC_LENGTH_13BIT (0x000C0000U)
-#define SPI_CRC_LENGTH_14BIT (0x000D0000U)
-#define SPI_CRC_LENGTH_15BIT (0x000E0000U)
-#define SPI_CRC_LENGTH_16BIT (0x000F0000U)
-#define SPI_CRC_LENGTH_17BIT (0x00100000U)
-#define SPI_CRC_LENGTH_18BIT (0x00110000U)
-#define SPI_CRC_LENGTH_19BIT (0x00120000U)
-#define SPI_CRC_LENGTH_20BIT (0x00130000U)
-#define SPI_CRC_LENGTH_21BIT (0x00140000U)
-#define SPI_CRC_LENGTH_22BIT (0x00150000U)
-#define SPI_CRC_LENGTH_23BIT (0x00160000U)
-#define SPI_CRC_LENGTH_24BIT (0x00170000U)
-#define SPI_CRC_LENGTH_25BIT (0x00180000U)
-#define SPI_CRC_LENGTH_26BIT (0x00190000U)
-#define SPI_CRC_LENGTH_27BIT (0x001A0000U)
-#define SPI_CRC_LENGTH_28BIT (0x001B0000U)
-#define SPI_CRC_LENGTH_29BIT (0x001C0000U)
-#define SPI_CRC_LENGTH_30BIT (0x001D0000U)
-#define SPI_CRC_LENGTH_31BIT (0x001E0000U)
-#define SPI_CRC_LENGTH_32BIT (0x001F0000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
- * @{
- */
-#define SPI_FIFO_THRESHOLD_01DATA (0x00000000U)
-#define SPI_FIFO_THRESHOLD_02DATA (0x00000020U)
-#define SPI_FIFO_THRESHOLD_03DATA (0x00000040U)
-#define SPI_FIFO_THRESHOLD_04DATA (0x00000060U)
-#define SPI_FIFO_THRESHOLD_05DATA (0x00000080U)
-#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0U)
-#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0U)
-#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0U)
-#define SPI_FIFO_THRESHOLD_09DATA (0x00000100U)
-#define SPI_FIFO_THRESHOLD_10DATA (0x00000120U)
-#define SPI_FIFO_THRESHOLD_11DATA (0x00000140U)
-#define SPI_FIFO_THRESHOLD_12DATA (0x00000160U)
-#define SPI_FIFO_THRESHOLD_13DATA (0x00000180U)
-#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0U)
-#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0U)
-#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0U)
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
- * @{
- */
-#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000U)
-#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
- * @{
- */
-#define SPI_NSS_POLARITY_LOW (0x00000000U)
-#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
-/**
- * @}
- */
-
-/** @defgroup SPI_Master_Keep_IO_State Keep IO State
- * @{
- */
-#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
-#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
-/**
- * @}
- */
-
-/** @defgroup SPI_IO_Swap Control SPI IO Swap
- * @{
- */
-#define SPI_IO_SWAP_DISABLE (0x00000000U)
-#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
-/**
- * @}
- */
-
-/** @defgroup SPI_Master_SS_Idleness SPI Master SS Ideleness
- * @{
- */
-#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000U)
-#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001U)
-#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002U)
-#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003U)
-#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004U)
-#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005U)
-#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006U)
-#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007U)
-#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008U)
-#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009U)
-#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AU)
-#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BU)
-#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CU)
-#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DU)
-#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EU)
-#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FU)
-/**
- * @}
- */
-
-/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Ideleness
- * @{
- */
- #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000U)
- #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010U)
- #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020U)
- #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030U)
- #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040U)
- #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050U)
- #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060U)
- #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070U)
- #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080U)
- #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090U)
- #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0U)
- #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0U)
- #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0U)
- #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0U)
- #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0U)
- #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0U)
-/**
- * @}
- */
-
-/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
- * @{
- */
-#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000U)
-#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
-/**
- * @}
- */
-
-/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
- * @{
- */
-#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000U)
-#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
-#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
-/**
- * @}
- */
-
-/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behaviour
- * @{
- */
-#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000U)
-#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
-#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_IER_TXPIE
-#define SPI_IT_RXNE SPI_IER_RXPIE
-#define SPI_IT_EOT SPI_IER_EOTIE
-#define SPI_IT_TXTF SPI_IER_TXTFIE
-#define SPI_IT_UDR SPI_IER_UDRIE
-#define SPI_IT_OVR SPI_IER_OVRIE
-#define SPI_IT_FRE SPI_IER_TIFREIE
-#define SPI_IT_MODF SPI_IER_MODFIE
-#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_TXE SPI_SR_TXP /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_RXNE SPI_SR_RXP /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag: Underrun flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI fifo reception level */
-#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI RxFIFO Word Not Empty */
-#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI Transmission Transfer Filled flag */
-#define SPI_FLAG_EOT SPI_SR_EOT /* SPI fifo transmision complete */
-#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI transfer suspend complete */
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
- * @{
- */
-#define SPI_FRLVL_EMPTY (0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL (0x00002000U)
-#define SPI_FRLVL_HALF_FULL (0x00004000U)
-#define SPI_FRLVL_FULL (0x00006000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_TXE : Tx buffer empty flag
- * @arg SPI_FLAG_RXNE : Rx buffer not empty flag
- * @arg SPI_FLAG_UDR : Underrun flag
- * @arg SPI_FLAG_OVR : Overrun flag
- * @arg SPI_FLAG_FRE : TI mode frame format error flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF : Mode fault flag
- * @arg SPI_FLAG_FRLVL : fifo reception level
- * @arg SPI_FLAG_RXWNE : RxFIFO Word Not Empty
- * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
- * @arg SPI_FLAG_EOT : fifo transmision complete
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
-
-/** @brief Clear the SPI FRE pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
-
-/** @brief Clear the SPI UDR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
-
-/** @brief Clear the SPI EOT pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
-
-/** @brief Clear the SPI UDR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
-
-/** @brief Clear the SPI SUSP pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__: specifies the SPI Handle.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
-/**
- * @}
- */
-
-
-/* Include SPI HAL Extension module */
-#include "stm32h7xx_hal_spi_ex.h"
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE) || \
- ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
- ((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE) || \
- ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
- ((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
- ((DATASIZE) == SPI_DATASIZE_31BIT) || \
- ((DATASIZE) == SPI_DATASIZE_30BIT) || \
- ((DATASIZE) == SPI_DATASIZE_29BIT) || \
- ((DATASIZE) == SPI_DATASIZE_28BIT) || \
- ((DATASIZE) == SPI_DATASIZE_27BIT) || \
- ((DATASIZE) == SPI_DATASIZE_26BIT) || \
- ((DATASIZE) == SPI_DATASIZE_25BIT) || \
- ((DATASIZE) == SPI_DATASIZE_24BIT) || \
- ((DATASIZE) == SPI_DATASIZE_23BIT) || \
- ((DATASIZE) == SPI_DATASIZE_22BIT) || \
- ((DATASIZE) == SPI_DATASIZE_21BIT) || \
- ((DATASIZE) == SPI_DATASIZE_20BIT) || \
- ((DATASIZE) == SPI_DATASIZE_22BIT) || \
- ((DATASIZE) == SPI_DATASIZE_19BIT) || \
- ((DATASIZE) == SPI_DATASIZE_18BIT) || \
- ((DATASIZE) == SPI_DATASIZE_17BIT) || \
- ((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_15BIT) || \
- ((DATASIZE) == SPI_DATASIZE_14BIT) || \
- ((DATASIZE) == SPI_DATASIZE_13BIT) || \
- ((DATASIZE) == SPI_DATASIZE_12BIT) || \
- ((DATASIZE) == SPI_DATASIZE_11BIT) || \
- ((DATASIZE) == SPI_DATASIZE_10BIT) || \
- ((DATASIZE) == SPI_DATASIZE_9BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT) || \
- ((DATASIZE) == SPI_DATASIZE_7BIT) || \
- ((DATASIZE) == SPI_DATASIZE_6BIT) || \
- ((DATASIZE) == SPI_DATASIZE_5BIT) || \
- ((DATASIZE) == SPI_DATASIZE_4BIT))
-
-#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
- ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
- ((NSSP) == SPI_NSS_PULSE_DISABLE))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
- ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
- ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
-
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
- ((LENGTH) == SPI_CRC_LENGTH_32BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_31BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_30BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_29BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_28BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_27BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_26BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_25BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_24BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_23BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_22BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_21BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_20BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_19BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_18BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_17BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_16BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_15BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_14BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_13BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_12BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_11BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_10BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_9BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_8BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_7BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_6BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_5BIT) ||\
- ((LENGTH) == SPI_CRC_LENGTH_4BIT))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
-
-#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
- ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
- ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
-
-#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
- ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
- ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SPI_H */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h
deleted file mode 100644
index 6099729..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spi_ex.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SPI_EX_H
-#define __STM32H7xx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPIEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPIEx_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SPIEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h
deleted file mode 100644
index 37c71ea..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sram.h
- * @author MCD Application Team
- * @brief Header file of SRAM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SRAM_H
-#define __STM32H7xx_HAL_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_ll_fmc.h"
-#include "stm32h7xx_hal_mdma.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-/** @addtogroup SRAM
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
- * @{
- */
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
- HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
-
-}HAL_SRAM_StateTypeDef;
-
-/**
- * @brief SRAM handle Structure definition
- */
-typedef struct
-{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< SRAM locking object */
-
- __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
-
- MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */
-
-}SRAM_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
-
-/** @brief Reset SRAM handle state
- * @param __HANDLE__: SRAM handle
- * @retval None
- */
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
-void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
-
-/* SRAM Control functions ****************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* SRAM State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h
deleted file mode 100644
index 316b413..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h
+++ /dev/null
@@ -1,465 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_swpmi.h
- * @author MCD Application Team
- * @brief Header file of SWPMI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_SWPMI_H
-#define __STM32H7xx_HAL_SWPMI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SWPMI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SWPMI_Exported_Types SWPMI Exported Types
- * @{
- */
-
-/**
- * @brief SWPMI Init Structure definition
- */
-typedef struct
-{
- uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
- This parameter can be a value of @ref SWPMI_Voltage_Class */
-
- uint32_t BitRate; /*!< Specifies the SWPMI Bitrate.
- This parameter must be a number between 0 and 63.
- The Bitrate is computed using the following formula:
- SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
- */
-
- uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
- This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
-
- uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
- This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
-
-}SWPMI_InitTypeDef;
-
-
-/**
- * @brief HAL SWPMI State structures definition
- */
-typedef enum
-{
- HAL_SWPMI_STATE_RESET = 0x00, /*!< Peripheral Reset state */
- HAL_SWPMI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SWPMI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SWPMI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_SWPMI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_SWPMI_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SWPMI_STATE_ERROR = 0x04 /*!< Error */
-}HAL_SWPMI_StateTypeDef;
-
-/**
- * @brief SWPMI handle Structure definition
- */
-typedef struct
-{
- SWPMI_TypeDef *Instance; /* SWPMI registers base address */
-
- SWPMI_InitTypeDef Init; /* SWMPI communication parameters */
-
- uint32_t *pTxBuffPtr; /* Pointer to SWPMI Tx transfer Buffer */
-
- uint32_t TxXferSize; /* SWPMI Tx Transfer size */
-
- uint32_t TxXferCount; /* SWPMI Tx Transfer Counter */
-
- uint32_t *pRxBuffPtr; /* Pointer to SWPMI Rx transfer Buffer */
-
- uint32_t RxXferSize; /* SWPMI Rx Transfer size */
-
- uint32_t RxXferCount; /* SWPMI Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /* SWPMI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /* SWPMI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /* SWPMI object */
-
- __IO HAL_SWPMI_StateTypeDef State; /* SWPMI communication state */
-
- __IO uint32_t ErrorCode; /* SWPMI Error code */
-
-}SWPMI_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
- * @{
- */
-
-/**
- * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
- * @{
- */
-#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */
-#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */
-#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
- * @{
- */
-#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
-#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
- * @{
- */
-#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
-#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
-#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
- * @{
- */
-#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
-#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
-#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Flags SWPMI Status Flags
- * Elements values convention: 0xXXXXXXXX
- * - 0xXXXXXXXX : Flag mask in the ISR register
- * @{
- */
-#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
-#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
-#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
-#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
-#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
-#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
-#define SWPMI_FLAG_TXE SWPMI_ISR_TXE
-#define SWPMI_FLAG_TCF SWPMI_ISR_TCF
-#define SWPMI_FLAG_SRF SWPMI_ISR_SRF
-#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
-#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
-#define SWPMI_FLAG_RDYF SWPMI_ISR_RDYF
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the IER register
- * @{
- */
-#define SWPMI_IT_RDYIE SWPMI_IER_RDYIE
-#define SWPMI_IT_SRIE SWPMI_IER_SRIE
-#define SWPMI_IT_TCIE SWPMI_IER_TCIE
-#define SWPMI_IT_TIE SWPMI_IER_TIE
-#define SWPMI_IT_RIE SWPMI_IER_RIE
-#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
-#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
-#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
-#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
-#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
- * @{
- */
-
-/** @brief Reset SWPMI handle state.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @retval None
- */
-#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
-
-/**
- * @brief Enable the SWPMI peripheral.
- * @param __HANDLE__: SWPMI handle
- * @retval None
- */
-#define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
-
-/**
- * @brief Disable the SWPMI peripheral.
- * @param __HANDLE__: SWPMI handle
- * @retval None
- */
-#define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
-
-/**
- * @brief Enable/Disable the SWPMI transceiver.
- * @param __HANDLE__: SWPMI handle
- * @retval None
- */
-#define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
-#define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
-
-/** @brief Check whether the specified SWPMI flag is set or not.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
- * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
- * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
- * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
- * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
- * @arg SWPMI_FLAG_RXNE : Receive data register not empty.
- * @arg SWPMI_FLAG_TXE : Transmit data register empty.
- * @arg SWPMI_FLAG_TCF : Transfer complete flag.
- * @arg SWPMI_FLAG_SRF : Slave resume flag.
- * @arg SWPMI_FLAG_SUSP : SUSPEND flag.
- * @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified SWPMI ISR flag.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
- * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
- * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
- * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
- * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
- * @arg SWPMI_FLAG_TCF : Transfer complete flag.
- * @arg SWPMI_FLAG_SRF : Slave resume flag.
- * @arg SWPMI_FLAG_RDYF: Transceiver ready flag
- * @retval None
- */
-#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
-
-/** @brief Enable the specified SWPMI interrupt.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __INTERRUPT__: specifies the SWPMI interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SWPMI_IT_SRIE : Slave resume interrupt.
- * @arg SWPMI_IT_TCIE : Transmit complete interrupt.
- * @arg SWPMI_IT_TIE : Transmit interrupt.
- * @arg SWPMI_IT_RIE : Receive interrupt.
- * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
- * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
- * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
- * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
- * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
- * @retval None
- */
-#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
-
-/** @brief Disable the specified SWPMI interrupt.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __INTERRUPT__: specifies the SWPMI interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SWPMI_IT_SRIE : Slave resume interrupt.
- * @arg SWPMI_IT_TCIE : Transmit complete interrupt.
- * @arg SWPMI_IT_TIE : Transmit interrupt.
- * @arg SWPMI_IT_RIE : Receive interrupt.
- * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
- * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
- * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
- * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
- * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
- * @retval None
- */
-#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
-
-/** @brief Check whether the specified SWPMI interrupt has occurred or not.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __IT__: specifies the SWPMI interrupt to check.
- * This parameter can be one of the following values:
- * @arg SWPMI_IT_SRIE : Slave resume interrupt.
- * @arg SWPMI_IT_TCIE : Transmit complete interrupt.
- * @arg SWPMI_IT_TIE : Transmit interrupt.
- * @arg SWPMI_IT_RIE : Receive interrupt.
- * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
- * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
- * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
- * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
- * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
-
-/** @brief Check whether the specified SWPMI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the SWPMI Handle.
- * @param __IT__: specifies the SWPMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SWPMI_IT_SRIE : Slave resume interrupt.
- * @arg SWPMI_IT_TCIE : Transmit complete interrupt.
- * @arg SWPMI_IT_TIE : Transmit interrupt.
- * @arg SWPMI_IT_RIE : Receive interrupt.
- * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
- * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
- * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
- * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
- * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
-HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
-HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
-HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
-void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
-
-/* Peripheral Control and State functions ************************************/
-HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
-uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SWPMI_Private_Types SWPMI Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SWPMI_Private_Variables SWPMI Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SWPMI_Private_Constants SWPMI Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SWPMI_Private_Macros SWPMI Private Macros
- * @{
- */
-
-
-#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__) (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
- ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
-
-#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
-
-
-#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
- ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
-
-
-#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
- ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
deleted file mode 100644
index bea734c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
+++ /dev/null
@@ -1,1917 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_TIM_H
-#define __STM32H7xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
- * @brief Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
- * @brief Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIMEx_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- * @note Advanced timers provide TRGO2 internal line which is redirected
- * to the ADC
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct {
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Break2State; /*!< TIM Break2 State
- This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity
- This parameter can be a value of @ref TIMEx_Break2_Polarity */
- uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
- HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-typedef struct
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
-}TIM_HandleTypeDef;
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_Event_Source TIM Extended Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-
-#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) /*!< Up counting mode */
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Down counting mode */
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned counting mode 1 */
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned counting mode 2 */
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned counting mode 3 */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) /*!< Clock Division DIV1 */
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) /*!< Clock Division DIV2 */
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) /*!< Clock Division DIV4 */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) /*!< Output State disabled */
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /*!< Output State enabled */
-
-/**
- * @}
- */
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000U) /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-
-#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-
-/**
- * @}
- */
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
-
-/**
- * @}
- */
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_CC5 (TIM_SR_CC5IF)
-#define TIM_FLAG_CC6 (TIM_SR_CC6IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
-#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-
-/**
- * @}
- */
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
- * @{
- */
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
- * @{
- */
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-/** @defgroup TIM_Lock_level TIM Lock Configuration
- * @{
- */
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-
-/**
- * @}
- */
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
- * @{
- */
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET ((uint32_t)0x0000U)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-/**
- * @}
- */
-/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
- * @{
- */
-#define TIM_TRGO2_RESET ((uint32_t)0x00000000U)
-#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
-#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
-#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
- * @{
- */
-
-#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
-#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint32_t)0x0000U)
-#define TIM_TS_ITR1 ((uint32_t)0x0010U)
-#define TIM_TS_ITR2 ((uint32_t)0x0020U)
-#define TIM_TS_ITR3 ((uint32_t)0x0030U)
-#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
-#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
-#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
-#define TIM_TS_ETRF ((uint32_t)0x0070U)
-#define TIM_TS_NONE ((uint32_t)0xFFFFU)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-
-/**
- * @}
- */
-
- /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-
-#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
-#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
-#define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
-#define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state
- * @param __HANDLE__: TIM handle.
- * @retval None
- */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__: TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__: TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * _ Counter overflow underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
- * @retval None
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
-
-/* The Main Output Enable of a timer instance is disabled unconditionally */
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled uncondiotionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) ((__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE))
-
-/** @brief Enable the specified TIM interrupt.
-* @param __HANDLE__: specifies the TIM Handle.
-* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
-* This parameter can be one of the following values:
-* @arg TIM_IT_UPDATE: Update interrupt
-* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
-* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
-* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
-* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
-* @arg TIM_IT_COM: Commutation interrupt
-* @arg TIM_IT_TRIGGER: Trigger interrupt
-* @arg TIM_IT_BREAK: Break interrupt
-* @retval None
-*/
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
- /** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief Enable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief Disable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @arg TIM_DMA_BREAK: Break DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__INTERRUPT__))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__: TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __PRESC__: specifies the Prescaler new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-/**
- * @brief Set the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __COUNTER__: specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Get the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
-
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __AUTORELOAD__: specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Autoreload Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __CKD__: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1
- * @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Clock Division value on runtime.
- * @param __HANDLE__: TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
-
-/**
- * @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
-/**
- * @brief Set the TIM Capture x input polarity on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__: Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
-/**
- * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__: specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
- * @brief Get the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval None by @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_CCMR3) || \
- ((__BASE__) == TIM_DMABASE_CCR5) || \
- ((__BASE__) == TIM_DMABASE_CCR6) || \
- ((__BASE__) == TIM_DMABASE_AF1) || \
- ((__BASE__) == TIM_DMABASE_AF2) || \
- ((__BASE__) == TIM_DMABASE_TISEL))
-
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
- ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
- ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || \
- ((__CHANNEL__) == TIM_CHANNEL_4) || \
- ((__CHANNEL__) == TIM_CHANNEL_5) || \
- ((__CHANNEL__) == TIM_CHANNEL_6) || \
- ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
- ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
- ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
-
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
- ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
- ((__STATE__) == TIM_BREAK2_DISABLE))
-
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
- ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
- ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO2_OC1) || \
- ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
- ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
- ((__MODE__) == TIM_SLAVEMODE_RESET) || \
- ((__MODE__) == TIM_SLAVEMODE_GATED) || \
- ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
- ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
- ((__MODE__) == TIM_OCMODE_PWM2) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
- ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
- ((__MODE__) == TIM_OCMODE_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_TOGGLE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
- ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_NONE))
-
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
-
-#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
- ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32h7xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
- * @{
- */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
- * @{
- */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
- * @{
- */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
- * @{
- */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
- * @{
- */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- * @{
- */
-/* Interrupt Handler functions **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-* @{
-*/
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-
-/**
-* @}
-*/
-/* End of private functions --------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
deleted file mode 100644
index f8f4123..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
+++ /dev/null
@@ -1,685 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_TIM_EX_H
-#define __STM32H7xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-
-/**
- * @brief TIM Break/Break2 input configuration
- */
-typedef struct {
- uint32_t Source; /*!< Specifies the source of the timer break input.
- This parameter can be a value of @ref TIMEx_Break_Input_Source */
- uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
- This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
- uint32_t Polarity; /*!< Specifies the break input source polarity.
- This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
- Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-} TIMEx_BreakInputConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Channel TIM Extended Channel
- * @{
- */
-#define TIM_CHANNEL_1 ((uint32_t)0x0000U) /*!< TIM Channel 1*/
-#define TIM_CHANNEL_2 ((uint32_t)0x0004U) /*!< TIM Channel 2*/
-#define TIM_CHANNEL_3 ((uint32_t)0x0008U) /*!< TIM Channel 3*/
-#define TIM_CHANNEL_4 ((uint32_t)0x000CU) /*!< TIM Channel 4*/
-#define TIM_CHANNEL_5 ((uint32_t)0x0010U) /*!< TIM Channel 5*/
-#define TIM_CHANNEL_6 ((uint32_t)0x0014U) /*!< TIM Channel 6*/
-#define TIM_CHANNEL_ALL ((uint32_t)0x003CU) /*!< TIM all Channels */
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) /*!< TIM Output timing mode */
-#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) /*!< TIM Output Active mode */
-#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) /*!< TIM Output Inactive mode */
-#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM Output Toggle mode */
-#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< TIM PWM mode 1 */
-#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM PWM mode 2 */
-#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< TIM Forced Active mode */
-#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) /*!< TIM Forced Inactive mode */
-
-#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) /*!< TIM Rettrigerrable OPM mode 1 */
-#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< TIM Rettrigerrable OPM mode 2 */
-#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 1 */
-#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< TIM Asymetruc PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!< TIM Asymetruc PWM mode 2 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) /*!< TIM Clear input source connected to ETR */
-#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) /*!< TIM Clear input source connected to OCREFClear */
-#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /*!< TIM Clear input source None */
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
- * @{
- */
-#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< TIM Break2 disabled */
-#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /*!< TIM Break2 enabled */
-
-/**
- * @}
- */
-/** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
- * @{
- */
-#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) /*!< TIM Break2 polarity low */
-#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) /*!< TIM Break2 polarity high */
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR4 ((uint32_t)0x0100000) /*!< TIM Internal trigger 4 */
-#define TIM_TS_ITR5 ((uint32_t)0x0100010) /*!< TIM Internal trigger 5 */
-#define TIM_TS_ITR6 ((uint32_t)0x0100020) /*!< TIM Internal trigger 6 */
-#define TIM_TS_ITR7 ((uint32_t)0x0100030) /*!< TIM Internal trigger 7 */
-#define TIM_TS_ITR8 ((uint32_t)0x0100040) /*!< TIM Internal trigger 8 */
-
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Extended Event Source
- * @{
- */
-
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 (0x00000000U) /*!< TIM DMA Base Address is CR1 */
-#define TIM_DMABASE_CR2 (0x00000001U) /*!< TIM DMA Base Address is CR2 */
-#define TIM_DMABASE_SMCR (0x00000002U) /*!< TIM DMA Base Address is SMCR */
-#define TIM_DMABASE_DIER (0x00000003U) /*!< TIM DMA Base Address is DIER */
-#define TIM_DMABASE_SR (0x00000004U) /*!< TIM DMA Base Address is SR */
-#define TIM_DMABASE_EGR (0x00000005U) /*!< TIM DMA Base Address is EGR */
-#define TIM_DMABASE_CCMR1 (0x00000006U) /*!< TIM DMA Base Address is CCMR1 */
-#define TIM_DMABASE_CCMR2 (0x00000007U) /*!< TIM DMA Base Address is CCMR2*/
-#define TIM_DMABASE_CCER (0x00000008U) /*!< TIM DMA Base Address is CCER */
-#define TIM_DMABASE_CNT (0x00000009U) /*!< TIM DMA Base Address is CNT */
-#define TIM_DMABASE_PSC (0x0000000AU) /*!< TIM DMA Base Address is PSC */
-#define TIM_DMABASE_ARR (0x0000000BU) /*!< TIM DMA Base Address is ARR */
-#define TIM_DMABASE_RCR (0x0000000CU) /*!< TIM DMA Base Address is RCR */
-#define TIM_DMABASE_CCR1 (0x0000000DU) /*!< TIM DMA Base Address is CCR1 */
-#define TIM_DMABASE_CCR2 (0x0000000EU) /*!< TIM DMA Base Address is CCR2 */
-#define TIM_DMABASE_CCR3 (0x0000000FU) /*!< TIM DMA Base Address is CCR3 */
-#define TIM_DMABASE_CCR4 (0x00000010U) /*!< TIM DMA Base Address is CCR3 */
-#define TIM_DMABASE_BDTR (0x00000011U) /*!< TIM DMA Base Address is BDTR */
-#define TIM_DMABASE_DCR (0x00000012U) /*!< TIM DMA Base Address is DCR */
-#define TIM_DMABASE_DMAR (0x00000013U) /*!< TIM DMA Base Address is DMAR */
-#define TIM_DMABASE_AF1 (0x00000014U) /*!< TIM DMA Base Address is AF1 */
-#define TIM_DMABASE_CCMR3 (0x00000015U) /*!< TIM DMA Base Address is CCMR3 */
-#define TIM_DMABASE_CCR5 (0x00000016U) /*!< TIM DMA Base Address is CCR5 */
-#define TIM_DMABASE_CCR6 (0x00000017U) /*!< TIM DMA Base Address is CCR6 */
-#define TIM_DMABASE_AF2 (0x00000018U) /*!< TIM DMA Base Address is AF2 */
-#define TIM_DMABASE_AF3 (0x00000019U) /*!< TIM DMA Base Address is AF3 */
-#define TIM_DMABASE_TISEL (0x0000001AU) /*!< TIM DMA Base Address is TISEL */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
- * @{
- */
-#define TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */
-#define TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
-#define TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
-
-#define TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */
-#define TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
-#define TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
-
-#define TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */
-#define TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
-#define TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
-#define TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
-#define TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
-#define TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
-
-#define TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */
-#define TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
-
-#define TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */
-#define TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
-#define TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
-
-#define TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */
-#define TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
-#define TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
-#define TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
-
-#define TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */
-#define TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
-#define TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
-#define TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
-
-#define TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */
-#define TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
-#define TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
-#define TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
-
-#define TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */
-#define TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
-#define TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
-#define TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
-
-#define TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */
-#define TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
-#define TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
-#define TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
-
-#define TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
-#define TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
-#define TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
-#define TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
-
-#define TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
-#define TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
-#define TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
-#define TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
-
-#define TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
-#define TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
-
-#define TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
-#define TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
-
-#define TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
-#define TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
-#define TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
-#define TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
-
-#define TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
-#define TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
-#define TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
-#define TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
-
-#define TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
-#define TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
-#define TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
-
-#define TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
-#define TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
-#define TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
-#define TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
-#define TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
-#define TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
-#define TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
-
-#define TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
-#define TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
-#define TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
-#define TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
-
-#define TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
-#define TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
-#define TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
-
-#define TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
-#define TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
-#define TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
-#define TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
- * @{
- */
-#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
-
-
-/** @defgroup TIMEx_Break_Input TIM Extended Break input
- * @{
- */
-#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
-#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
- * @{
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
- * @{
- */
-#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
-
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
- ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
-
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
- ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
-
-#define IS_TIM_TISEL(TISEL) (((TISEL) == TIM_TIM1_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM1_TI1_COMP1_OUT) ||\
- ((TISEL) == TIM_TIM8_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM8_TI1_COMP2_OUT) ||\
- ((TISEL) == TIM_TIM2_TI4_GPIO) ||\
- ((TISEL) == TIM_TIM2_TI4_COMP1_OUT) ||\
- ((TISEL) == TIM_TIM2_TI4_COMP2_OUT) ||\
- ((TISEL) == TIM_TIM2_TI4_COMP1COMP2_OUT) ||\
- ((TISEL) == TIM_TIM3_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM3_TI1_COMP1_OUT) ||\
- ((TISEL) == TIM_TIM3_TI1_COMP2_OUT) ||\
- ((TISEL) == TIM_TIM3_TI1_COMP1COMP2_OUT) ||\
- ((TISEL) == TIM_TIM5_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM5_TI1_CAN_TMP) ||\
- ((TISEL) == TIM_TIM5_TI1_CAN_RTP) ||\
- ((TISEL) == TIM_TIM15_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM15_TI1_TIM2_CH1) ||\
- ((TISEL) == TIM_TIM15_TI1_TIM3_CH1) ||\
- ((TISEL) == TIM_TIM15_TI1_TIM4_CH1) ||\
- ((TISEL) == TIM_TIM15_TI1_RCC_LSE) ||\
- ((TISEL) == TIM_TIM15_TI1_RCC_CSI) ||\
- ((TISEL) == TIM_TIM15_TI1_RCC_MCO2) ||\
- ((TISEL) == TIM_TIM15_TI2_GPIO) ||\
- ((TISEL) == TIM_TIM15_TI2_TIM2_CH2) ||\
- ((TISEL) == TIM_TIM15_TI2_TIM3_CH2) ||\
- ((TISEL) == TIM_TIM15_TI2_TIM4_CH2) ||\
- ((TISEL) == TIM_TIM16_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM16_TI1_RCC_LSI) ||\
- ((TISEL) == TIM_TIM16_TI1_RCC_LSE) ||\
- ((TISEL) == TIM_TIM16_TI1_WKUP_IT) ||\
- ((TISEL) == TIM_TIM17_TI1_GPIO) ||\
- ((TISEL) == TIM_TIM17_TI1_SPDIF_FS) ||\
- ((TISEL) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
- ((TISEL) == TIM_TIM17_TI1_RCC_MCO1))
-
-#define IS_TIM_BKR2REMAP(BK2RREMAP) (((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKR2REMAP) == TIM_TIM1_BKR_GPIO))
-
-#define IS_TIM_BKRREMAP(BKRREMAP) (((BKRREMAP) == TIM_TIM1_BKR_GPIO) ||\
- ((BKRREMAP) == TIM_TIM1_BKR_COMP1_OUT) ||\
- ((BKRREMAP) == TIM_TIM1_BKR_COMP2_OUT) ||\
- ((BKRREMAP) == TIM_TIM1_BKR_DFSDM_BRK0) ||\
- ((BKRREMAP) == TIM_TIM8_BKR_GPIO) ||\
- ((BKRREMAP) == TIM_TIM8_BKR_COMP1_OUT) ||\
- ((BKRREMAP) == TIM_TIM8_BKR_COMP2_OUT) ||\
- ((BKRREMAP) == TIM_TIM8_BKR_DFSDM_BRK2) ||\
- ((BKRREMAP) == TIM_TIM15_BKR_GPIO) ||\
- ((BKRREMAP) == TIM_TIM15_BKR_COMP1_OUT) ||\
- ((BKRREMAP) == TIM_TIM15_BKR_COMP2_OUT) ||\
- ((BKRREMAP) == TIM_TIM15_BKR_DFSDM_BRK0) ||\
- ((BKRREMAP) == TIM_TIM16_BKR_GPIO) ||\
- ((BKRREMAP) == TIM_TIM16_BKR_COMP1_OUT) ||\
- ((BKRREMAP) == TIM_TIM16_BKR_COMP2_OUT) ||\
- ((BKRREMAP) == TIM_TIM16_BKR_DFSDM_BRK1) ||\
- ((BKRREMAP) == TIM_TIM17_BKR_GPIO) ||\
- ((BKRREMAP) == TIM_TIM17_BKR_COMP1_OUT) ||\
- ((BKRREMAP) == TIM_TIM17_BKR_COMP2_OUT) ||\
- ((BKRREMAP) == TIM_TIM17_BKR_DFSDM_BRK2))
-
-#define IS_TIM_ETRREMAP(ETRREMAP) (((ETRREMAP) == TIM_TIM1_ETR_GPIO) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD1) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD2) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD3) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD1) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD2) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD3) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_COMP1_OUT) ||\
- ((ETRREMAP) == TIM_TIM1_ETR_COMP2_OUT) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_GPIO) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD1) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD2) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD3) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD1) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD2) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD3) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_COMP1_OUT) ||\
- ((ETRREMAP) == TIM_TIM8_ETR_COMP2_OUT) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_GPIO) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_COMP1_OUT) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_COMP2_OUT) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_RCC_LSE) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSA) ||\
- ((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSB) ||\
- ((ETRREMAP) == TIM_TIM3_ETR_GPIO) ||\
- ((ETRREMAP) == TIM_TIM3_ETR_COMP1_OUT) ||\
- ((ETRREMAP) == TIM_TIM5_ETR_GPIO) ||\
- ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSA) |\
- ((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSB))
-/**
- * @}
- */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
-
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- * @{
- */
-/* Extended Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- * @{
- */
-/* Extended Peripheral State functions **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-/**
- * @}
- */
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-* @{
-*/
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-* @}
-*/
-/* End of private functions --------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
deleted file mode 100644
index d3dd6a7..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
+++ /dev/null
@@ -1,1631 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_uart.h
- * @author MCD Application Team
- * @brief Header file of UART HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_UART_H
-#define __STM32H7xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
- * @{
- */
-
-/**
- * @brief UART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following formula:
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length. */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode. */
-
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control. */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. */
-
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
-
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
- This parameter can be a value of @ref UART_Prescaler. */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
- of @ref UART_FIFO_mode. */
-
- uint32_t TXFIFOThreshold; /*!< Specifies the TXFIFO threshold level.
- This parameter can be a value of @ref UART_TXFIFO_threshold_level. */
-
- uint32_t RXFIFOThreshold; /*!< Specifies the RXFIFO threshold level.
- This parameter can be a value of @ref UART_RXFIFO_threshold_level. */
-
-}UART_InitTypeDef;
-
-/**
- * @brief UART Advanced Features initalization structure definition
- */
-typedef struct
-{
- uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
- Advanced Features may be initialized at the same time .
- This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref UART_Tx_Inv. */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref UART_Rx_Inv. */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
- vs negative/inverted logic).
- This parameter can be a value of @ref UART_Data_Inv. */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref UART_Rx_Tx_Swap. */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref UART_Overrun_Disable. */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
-
- uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
- This parameter can be a value of @ref UART_AutoBaudRate_Enable */
-
- uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
- detection is carried out.
- This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref UART_MSB_First. */
-} UART_AdvFeatureInitTypeDef;
-
-
-
-/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
- * - gState contains UART state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
-
-/**
- * @brief HAL UART Error Code structure definition
- */
-typedef enum
-{
- HAL_UART_ERROR_NONE = 0x00U, /*!< No error */
- HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */
- HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */
- HAL_UART_ERROR_FE = 0x04U, /*!< frame error */
- HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */
- HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */
-}HAL_UART_ErrorTypeDef;
-
-/**
- * @brief UART clock sources definition
- */
-typedef enum
-{
- UART_CLOCKSOURCE_D2PCLK1 = 0x00U, /*!< Domain2 PCLK1 clock source */
- UART_CLOCKSOURCE_D2PCLK2 = 0x01U, /*!< Domain2 PCLK2 clock source */
- UART_CLOCKSOURCE_D3PCLK1 = 0x02U, /*!< Domain3 PCLK1 clock source */
- UART_CLOCKSOURCE_PLL2 = 0x04U, /*!< PLL2Q clock source */
- UART_CLOCKSOURCE_HSI = 0x08U, /*!< HSI clock source */
- UART_CLOCKSOURCE_CSI = 0x10U, /*!< CSI clock source */
- UART_CLOCKSOURCE_LSE = 0x20U, /*!< LSE clock source */
- UART_CLOCKSOURCE_PLL3 = 0x40U, /*!< PLL3Q clock source */
- UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
-
-/**
- * @brief UART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< UART registers base address */
-
- UART_InitTypeDef Init; /*!< UART communication parameters */
-
- UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
-
- uint16_t Mask; /*!< UART Rx RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< UART Error code */
-
-}UART_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
- * @{
- */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
- * @{
- */
-#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
-#define UART_STOPBITS_1 ((uint32_t)0x00000000U) /*!< UART frame with 1 stop bit */
-#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup UART_Parity UART Parity
- * @{
- */
-#define UART_PARITY_NONE ((uint32_t)0x00000000U) /*!< No parity */
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
- * @{
- */
-#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) /*!< No hardware control */
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
-/**
- * @}
- */
-
-/** @defgroup UART_Mode UART Transfer Mode
- * @{
- */
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup UART_State UART State
- * @{
- */
-#define UART_STATE_DISABLE ((uint32_t)0x00000000U) /*!< UART disabled */
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
- * @{
- */
-#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) /*!< Oversampling by 16 */
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
- * @{
- */
-#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) /*!< One-bit sampling disable */
-#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Prescaler UART Prescaler
- * @{
- */
-#define UART_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< UART clock /1 */
-#define UART_PRESCALER_DIV2 ((uint32_t)0x00000001U) /*!< UART clock /2 */
-#define UART_PRESCALER_DIV4 ((uint32_t)0x00000002U) /*!< UART clock /4 */
-#define UART_PRESCALER_DIV6 ((uint32_t)0x00000003U) /*!< UART clock /6 */
-#define UART_PRESCALER_DIV8 ((uint32_t)0x00000004U) /*!< UART clock /8 */
-#define UART_PRESCALER_DIV10 ((uint32_t)0x00000005U) /*!< UART clock /10 */
-#define UART_PRESCALER_DIV12 ((uint32_t)0x00000006U) /*!< UART clock /12 */
-#define UART_PRESCALER_DIV16 ((uint32_t)0x00000007U) /*!< UART clock /16 */
-#define UART_PRESCALER_DIV32 ((uint32_t)0x00000008U) /*!< UART clock /32 */
-#define UART_PRESCALER_DIV64 ((uint32_t)0x00000009U) /*!< UART clock /64 */
-#define UART_PRESCALER_DIV128 ((uint32_t)0x0000000AU) /*!< UART clock /128 */
-#define UART_PRESCALER_DIV256 ((uint32_t)0x0000000BU) /*!< UART clock /256 */
-
-/**
- * @}
- */
-
-/** @defgroup UART_FIFO_mode UART FIFO mode
- * @brief UART FIFO mode
- * @{
- */
-#define UART_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
-#define UART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN) /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_TXFIFO_threshold_level UART TXFIFO threshold level
- * @brief UART TXFIFO level
- * @{
- */
-#define UART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U) /*!< TXFIFO reaches 1/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0) /*!< TXFIFO reaches 1/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 1/2 of its depth */
-#define UART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO reaches 3/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2) /*!< TXFIFO reaches 7/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty */
-/**
- * @}
- */
-
-/** @defgroup UART_RXFIFO_threshold_level UART RXFIFO threshold level
- * @brief UART RXFIFO level
- * @{
- */
-#define UART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U) /*!< RXFIFO reaches 1/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0) /*!< RXFIFO reaches 1/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1) /*!< RXFIFO reaches 1/2 of its depth */
-#define UART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO reaches 3/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2) /*!< RXFIFO reaches 7/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes full */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000U) /*!< Auto Baud rate detection on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
-/**
- * @}
- */
-
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
- * @{
- */
-#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN UART Local Interconnection Network mode
- * @{
- */
-#define UART_LIN_DISABLE ((uint32_t)0x00000000U) /*!< Local Interconnect Network disable */
-#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Tx UART DMA Tx
- * @{
- */
-#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Rx UART DMA Rx
- * @{
- */
-#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000U) /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
- * @{
- */
-#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000U) /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
- * @{
- */
-#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) /*!< UART wake-up on idle line */
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
-/**
- * @}
- */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
- * @{
- */
-#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
- * @{
- */
-#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) /*!< No advanced feature initialization */
-#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) /*!< TX pin active level inversion */
-#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) /*!< RX pin active level inversion */
-#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) /*!< Binary data inversion */
-#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) /*!< TX/RX pins swap */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) /*!< RX overrun disable */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) /*!< DMA disable on Reception Error */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) /*!< Auto Baud rate detection initialization */
-#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) /*!< Most significant bit sent/received first */
-/**
- * @}
- */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) /*!< RX pin active level inversion disable */
-#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
- * @{
- */
-#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
- * @{
- */
-#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) /*!< TX/RX pins swap disable */
-#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
- * @{
- */
-#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) /*!< RX overrun enable */
-#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) /*!< RX Auto Baud rate detection enable */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
- * @{
- */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) /*!< DMA enable on Reception Error */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
-/**
- * @}
- */
-
-/** @defgroup UART_MSB_First UART Advanced Feature MSB First
- * @{
- */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) /*!< Most significant bit sent/received first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000U) /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
- * @{
- */
-#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) /*!< UART address-matching LSB position in CR2 register */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
- * @{
- */
-#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000U) /*!< UART wake-up on address */
-#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
-#define UART_WAKEUP_ON_RXFIFO_THRESHOLD ((uint32_t)USART_CR3_RXFTIE) /*!< UART wake-up when the RXFIFO reaches threshold */
-#define UART_WAKEUP_ON_RXFIFO_FULL ((uint32_t)USART_CR1_RXFFIE) /*!< UART wake-up when the RXFIFO is full */
-#define UART_WAKEUP_ON_TXFIFO_THRESHOLD ((uint32_t)USART_CR3_TXFTIE) /*!< UART wake-up when the TXFIFO reaches threshold */
-#define UART_WAKEUP_ON_TXFIFO_EMPTY ((uint32_t)USART_CR1_TXFEIE) /*!< UART wake-up when the TXFIFO is empty */
-/**
- * @}
- */
-
-/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
- * @{
- */
-#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
- * @{
- */
-#define UART_IT_MASK ((uint32_t)0x001FU) /*!< UART interruptions flags mask */
-/**
- * @}
- */
-
-/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
- * @{
- */
-#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
-/**
- * @}
- */
-
-/** @defgroup UART_Flags UART Status Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
-#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
-#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */
-#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
-#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
-#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
-#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
-#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
-#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
-#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
-#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
-#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART uto Baud rate error */
-#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
-#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
-#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
-#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
-#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */
-#define UART_FLAG_TXFNF USART_ISR_TXE /*!< UART TXFIFO not full */
-#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
-#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */
-#define UART_FLAG_RXFNE USART_ISR_RXNE /*!< UART RXFIFO not empty */
-#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
-#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
-#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
-#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
-#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UART Interrupts Definition
- * Elements values convention: 000ZZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZZ : Flag position in the ISR register(5bits)
- * @{
- */
-#define UART_IT_PE ((uint32_t)0x0028U) /*!< UART parity error interruption */
-#define UART_IT_TXE ((uint32_t)0x0727U) /*!< UART transmit data register empty interruption */
-#define UART_IT_TC ((uint32_t)0x0626U) /*!< UART transmission complete interruption */
-#define UART_IT_RXNE ((uint32_t)0x0525U) /*!< UART read data register not empty interruption */
-#define UART_IT_IDLE ((uint32_t)0x0424U) /*!< UART idle interruption */
-#define UART_IT_LBD ((uint32_t)0x0846U) /*!< UART LIN break detection interruption */
-#define UART_IT_CTS ((uint32_t)0x096AU) /*!< UART CTS interruption */
-#define UART_IT_CM ((uint32_t)0x112EU) /*!< UART character match interruption */
-#define UART_IT_WUF ((uint32_t)0x1476U) /*!< UART wake-up from stop mode interruption */
-#define UART_IT_RXFF ((uint16_t)0x183FU)
-#define UART_IT_TXFE ((uint16_t)0x173EU)
-#define UART_IT_RXFT ((uint16_t)0x1A7CU)
-#define UART_IT_TXFT ((uint16_t)0x1B77U)
-
-
-/** Elements values convention: 000000000XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- */
-#define UART_IT_ERR ((uint32_t)0x0060U) /*!< UART error interruption */
-
-/** Elements values convention: 0000ZZZZ00000000b
- * - ZZZZ : Flag position in the ISR register(4bits)
- */
-#define UART_IT_ORE ((uint32_t)0x0300U) /*!< UART overrun error interruption */
-#define UART_IT_NE ((uint32_t)0x0200U) /*!< UART noise error interruption */
-#define UART_IT_FE ((uint32_t)0x0100U) /*!< UART frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
- * @{
- */
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
-#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
- * @{
- */
-
-/** @brief Reset UART handle states.
- * @param __HANDLE__: UART handle.
- * @retval None
- */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0)
-/** @brief Flush the UART Data registers.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0)
-
-/** @brief Clear the specified UART pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg UART_FLAG_WUF: Wake up from stop mode flag
- * @arg UART_FLAG_CMF: Character match flag
- * @arg UART_FLAG_RTOF: Receiver timeout flag
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_TXFE: TXFIFO Empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
- * @arg UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the UART PE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
-
-/** @brief Clear the UART FE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
-
-/** @brief Clear the UART NE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
-
-/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
-
-/** @brief Clear the UART IDLE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
-
-/** @brief Clear the UART TX FIFO empty clear flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
-
-/** @brief Check whether the specified UART flag is set or not.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg UART_FLAG_TXFT: TXFIFO threshold flag
- * @arg UART_FLAG_RXFT: RXFIFO threshold flag
- * @arg UART_FLAG_RXFF: RXFIFO Full flag
- * @arg UART_FLAG_TXFE: TXFIFO Empty flag
- * @arg UART_FLAG_REACK: Receive enable acknowledge flag
- * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg UART_FLAG_WUF: Wake up from stop mode flag
- * @arg UART_FLAG_RWU: Receiver wake up flag (if the UART in mute mode)
- * @arg UART_FLAG_SBKF: Send Break flag
- * @arg UART_FLAG_CMF: Character match flag
- * @arg UART_FLAG_BUSY: Busy flag
- * @arg UART_FLAG_ABRF: Auto Baud rate detection flag
- * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg UART_FLAG_RTOF: Receiver timeout flag
- * @arg UART_FLAG_CTS: CTS Change flag
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TXE: Transmit data register empty flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_RXNE: Receive data register not empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
- * @arg.UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __INTERRUPT__: specifies the UART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg UART_IT_RXFF : RXFIFO Full interrupt
- * @arg UART_IT_TXFE : TXFIFO Empty interrupt
- * @arg.UART_IT_RXFT : RXFIFO threshold interrupt
- * @arg UART_IT_TXFT : TXFIFO threshold interrupt
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg.UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-
-/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __INTERRUPT__: specifies the UART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg.UART_IT_RXFF : RXFIFO Full interrupt
- * @arg UART_IT_TXFE : TXFIFO Empty interrupt
- * @arg UART_IT_RXFT : RXFIFO threshold interrupt
- * @arg UART_IT_TXFT : TXFIFO threshold interrupt
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief Check whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __IT__: specifies the UART interrupt to check.
- * This parameter can be one of the following values:
- * @arg UART_IT_RXFF : RXFIFO Full interrupt
- * @arg UART_IT_TXFE : TXFIFO Empty interrupt
- * @arg UART_IT_RXFT : RXFIFO threshold interrupt
- * @arg UART_IT_TXFT : TXFIFO threshold interrupt
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Check whether the specified UART interrupt source is enabled or not.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __IT__: specifies the UART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg UART_IT_RXFF : RXFIFO Full interrupt
- * @arg UART_IT_TXFE : TXFIFO Empty interrupt
- * @arg UART_IT_RXFT : RXFIFO threshold interrupt
- * @arg UART_IT_TXFT : TXFIFO threshold interrupt
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
-
-/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg UART_CLEAR_PEF: Parity Error Clear Flag
- * @arg UART_CLEAR_FEF: Framing Error Clear Flag
- * @arg UART_CLEAR_NEF: Noise detected Clear Flag
- * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
- * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
- * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg UART_CLEAR_CMF: Character Match Clear Flag
- * @arg.UART_CLEAR_WUF: Wake Up from stop mode Clear Flag
- * @arg UART_CLEAR_TXFECF: TXFIFO empty Clear Flag
- * @retval None
- */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Set a specific UART request flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __REQ__: specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg UART_SENDBREAK_REQUEST: Send Break Request
- * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
- * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
- * @retval None
- */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
-
-/** @brief Enable the UART one bit sample method.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the UART one bit sample method.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief Enable CTS flow control.
- * @note This macro allows to enable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0)
-
-/** @brief Disable CTS flow control.
- * @note This macro allows to disable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0)
-
-/** @brief Enable RTS flow control.
- * @note This macro allows to enable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0)
-
-/** @brief Disable RTS flow control.
- * @note This macro allows to disable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0)
-
-/**
- * @}
- */
-
-/* Private variables -----------------------------------------------------*/
-/** @defgroup UART_Private_Variables UART Private Variables
- * @{
- */
-static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-/** @brief BRR division operation to set BRR register with LPUART.
- * @param __PCLK__: LPUART clock.
- * @param __BAUD__: Baud rate set by the user.
- * @param __PRESCALER__: UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __PRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__PRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__))
-
-/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
- * @param __PCLK__: UART clock.
- * @param __BAUD__: Baud rate set by the user.
- * @param __PRESCALER__: UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/UARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
-
-/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
- * @param __PCLK__: UART clock.
- * @param __BAUD__: Baud rate set by the user.
- * @param __PRESCALER__: UART prescaler value.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/UARTPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__))
-
-/** @brief Check whether or not UART instance is Low Power UART.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
- */
-#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
-
-/** @brief Check UART Baud rate.
- * @param __BAUDRATE__: Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
- */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
-
-/** @brief Check UART assertion time.
- * @param __TIME__: 5-bit value assertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/** @brief Check UART deassertion time.
- * @param __TIME__: 5-bit value deassertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/**
- * @brief Ensure that UART frame number of stop bits is valid.
- * @param __STOPBITS__: UART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
- ((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_1_5) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that LPUART frame number of stop bits is valid.
- * @param __STOPBITS__: LPUART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that UART frame parity is valid.
- * @param __PARITY__: UART frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
- ((__PARITY__) == UART_PARITY_EVEN) || \
- ((__PARITY__) == UART_PARITY_ODD))
-
-/**
- * @brief Ensure that UART hardware flow control is valid.
- * @param __CONTROL__: UART hardware flow control.
- * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
- */
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
- (((__CONTROL__) == UART_HWCONTROL_NONE) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS) || \
- ((__CONTROL__) == UART_HWCONTROL_CTS) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-
-/**
- * @brief Ensure that UART communication mode is valid.
- * @param __MODE__: UART communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
-
-/**
- * @brief Ensure that UART state is valid.
- * @param __STATE__: UART state.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
- ((__STATE__) == UART_STATE_ENABLE))
-
-/**
- * @brief Ensure that UART oversampling is valid.
- * @param __SAMPLING__: UART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == UART_OVERSAMPLING_8))
-
-/**
- * @brief Ensure that UART frame sampling is valid.
- * @param __ONEBIT__: UART frame sampling.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that UART auto Baud rate detection mode is valid.
- * @param __MODE__: UART auto Baud rate detection mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-/**
- * @brief Ensure that UART receiver timeout setting is valid.
- * @param __TIMEOUT__: UART receiver timeout setting.
- * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
- */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-/**
- * @brief Ensure that UART LIN state is valid.
- * @param __LIN__: UART LIN state.
- * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
- */
-#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
- ((__LIN__) == UART_LIN_ENABLE))
-
-/**
- * @brief Ensure that UART LIN break detection length is valid.
- * @param __LENGTH__: UART LIN break detection length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-
-/**
- * @brief Ensure that UART DMA TX state is valid.
- * @param __DMATX__: UART DMA TX state.
- * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
-#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
- ((__DMATX__) == UART_DMA_TX_ENABLE))
-
-/**
- * @brief Ensure that UART DMA RX state is valid.
- * @param __DMARX__: UART DMA RX state.
- * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
-#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
- ((__DMARX__) == UART_DMA_RX_ENABLE))
-
-/**
- * @brief Ensure that UART half-duplex state is valid.
- * @param __HDSEL__: UART half-duplex state.
- * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
- */
-#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
- ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up method is valid.
- * @param __WAKEUP__: UART wake-up method .
- * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
- */
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-/**
- * @brief Ensure that UART request parameter is valid.
- * @param __PARAM__: UART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
- ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
- ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-
-/**
- * @brief Ensure that UART advanced features initialization is valid.
- * @param __INIT__: UART advanced features initialization.
- * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
- */
-#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
- UART_ADVFEATURE_TXINVERT_INIT | \
- UART_ADVFEATURE_RXINVERT_INIT | \
- UART_ADVFEATURE_DATAINVERT_INIT | \
- UART_ADVFEATURE_SWAP_INIT | \
- UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
- UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
- UART_ADVFEATURE_MSBFIRST_INIT))
-
-/**
- * @brief Ensure that UART frame TX inversion setting is valid.
- * @param __TXINV__: UART frame TX inversion setting.
- * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
- ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX inversion setting is valid.
- * @param __RXINV__: UART frame RX inversion setting.
- * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
- ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame data inversion setting is valid.
- * @param __DATAINV__: UART frame data inversion setting.
- * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
- ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX/TX pins swap setting is valid.
- * @param __SWAP__: UART frame RX/TX pins swap setting.
- * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
- */
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
- ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-
-/**
- * @brief Ensure that UART frame overrun setting is valid.
- * @param __OVERRUN__: UART frame overrun setting.
- * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
- */
-#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
- ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
- * @brief Ensure that UART auto Baud rate state is valid.
- * @param __AUTOBAUDRATE__: UART auto Baud rate state.
- * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-/**
- * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
- * @param __DMA__: UART DMA enabling or disabling on error setting.
- * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
- * @brief Ensure that UART frame MSB first setting is valid.
- * @param __MSBFIRST__: UART frame MSB first setting.
- * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
- */
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
- * @brief Ensure that UART stop mode state is valid.
- * @param __STOPMODE__: UART stop mode state.
- * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
- ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
- * @brief Ensure that UART mute mode state is valid.
- * @param __MUTE__: UART mute mode state.
- * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
- */
-#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
- ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up selection is valid.
- * @param __WAKE__: UART wake-up selection.
- * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
- */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS ) || \
- ((__WAKE__) == UART_WAKEUP_ON_STARTBIT ) || \
- ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY ) || \
- ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_THRESHOLD ) || \
- ((__WAKE__) == UART_WAKEUP_ON_RXFIFO_FULL ) || \
- ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_THRESHOLD ) || \
- ((__WAKE__) == UART_WAKEUP_ON_TXFIFO_EMPTY ))
-
-/**
- * @brief Ensure that UART driver enable polarity is valid.
- * @param __POLARITY__: UART driver enable polarity.
- * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
- */
-#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
- ((__POLARITY__) == UART_DE_POLARITY_LOW))
-
-/**
- * @brief Ensure that LPUART frame number of stop bits is valid.
- * @param __STOPBITS__: LPUART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that UART Prescaler is valid.
- * @param __PRESCALER__: UART Prescaler value.
- * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
- */
-#define IS_UART_PRESCALER(__PRESCALER__) (((__PRESCALER__) == UART_PRESCALER_DIV1) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV2) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV4) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV6) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV8) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV10) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV12) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV16) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV32) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV64) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV128) || \
- ((__PRESCALER__) == UART_PRESCALER_DIV256))
-
-/**
- * @brief Ensure that UART FIFO mode is valid.
- * @param __STATE__: UART FIFO mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_UART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == UART_FIFOMODE_DISABLE ) || \
- ((__STATE__) == UART_FIFOMODE_ENABLE))
-
-/**
- * @brief Ensure that UART TXFIFO threshold level is valid.
- * @param __THRESHOLD__: UART TXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) ((((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8 ) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4 ) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8)) || \
- ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
-
-/**
- * @brief Ensure that UART RXFIFO threshold level is valid.
- * @param __THRESHOLD__: UART RXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) ((((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8 ) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4 ) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8)) || \
- ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
-
-/**
- * @}
- */
-
-/* Include UART HAL Extended module */
-#include "stm32h7xx_hal_uart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Errors functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
deleted file mode 100644
index d952ab3..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_uart_ex.h
- * @author MCD Application Team
- * @brief Header file of UART HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_UART_EX_H
-#define __STM32H7xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UARTEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
- * @{
- */
-
-/**
- * @brief UART wake up from stop mode parameters
- */
-typedef struct
-{
- uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
- This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
- If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
- be filled up. */
-
- uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
-
- uint8_t Address; /*!< UART/USART node address (7-bit long max). */
-} UART_WakeUpTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
- * @{
- */
-
-/** @defgroup UARTEx_Word_Length UART Word Length
- * @{
- */
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U) /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
- * @{
- */
-#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
- * @{
- */
-
-/** @brief Report the UART clock source.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __CLOCKSOURCE__: output variable.
- * @retval UART clocking source, written in __CLOCKSOURCE__.
- */
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART2CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART3CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
- case RCC_UART4CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_UART4CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if ((__HANDLE__)->Instance == UART5) \
- { \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
- case RCC_UART5CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART5CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_UART5CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_UART5CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART5CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART5CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
- case RCC_USART6CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART6CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART6CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART6CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART7) \
- { \
- switch(__HAL_RCC_GET_UART7_SOURCE()) \
- { \
- case RCC_UART7CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART7CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_UART7CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_UART7CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART7CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART7CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART8) \
- { \
- switch(__HAL_RCC_GET_UART8_SOURCE()) \
- { \
- case RCC_UART8CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_UART8CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_UART8CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_UART8CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART8CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_UART8CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == LPUART1) \
- { \
- switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
- { \
- case RCC_LPUART1CLKSOURCE_D3PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \
- break; \
- case RCC_LPUART1CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_LPUART1CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_LPUART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_LPUART1CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_LPUART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- } while(0)
-
-/** @brief Report the UART mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#define UART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003F ; \
- } \
- } \
-} while(0)
-
-
-/**
- * @brief Ensure that UART frame length is valid.
- * @param __LENGTH__: UART frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
- ((__LENGTH__) == UART_WORDLENGTH_8B) || \
- ((__LENGTH__) == UART_WORDLENGTH_9B))
-
-/**
- * @brief Ensure that UART wake-up address length is valid.
- * @param __ADDRESS__: UART wake-up address length.
- * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
- */
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
- ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_UART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
deleted file mode 100644
index 4b9dd8c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
+++ /dev/null
@@ -1,1069 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_usart.h
- * @author MCD Application Team
- * @brief Header file of USART HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_USART_H
-#define __STM3H7xx_HAL_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
- The baud rate is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((husart->Init.BaudRate))) */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USARTEx_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
- This parameter can be a value of @ref USART_Prescaler */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (DIS_NSS pin)
- or by software . This parameter can be a value
- of @ref USART_Slave_Select_management */
-
- uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
- of @ref USART_Slave_Mode */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
- of @ref USART_FIFO_mode */
-
- uint32_t TXFIFOThreshold; /*!< Specifies the TXFIFO threshold level.
- This parameter can be a value of @ref USART_TXFIFO_threshold_level */
-
- uint32_t RXFIFOThreshold; /*!< Specifies the RXFIFO threshold level.
- This parameter can be a value of @ref USART_RXFIFO_threshold_level */
-
-}USART_InitTypeDef;
-
-/**
- * @brief HAL USART State structures definition
- */
-typedef enum
-{
- HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
-
-/**
- * @brief HAL USART Error Code structure definition
- */
-typedef enum
-{
- HAL_USART_ERROR_NONE = 0x00U, /*!< No error */
- HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */
- HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */
- HAL_USART_ERROR_FE = 0x04U, /*!< frame error */
- HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */
- HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */
- HAL_USART_ERROR_UDR = 0x11U /*!< SPI UnderRun error */
-}HAL_USART_ErrorTypeDef;
-
-/**
- * @brief USART clock sources definitions
- */
-typedef enum
-{
- USART_CLOCKSOURCE_D2PCLK1 = 0x00U, /*!< Domain2 PCLK1 clock source */
- USART_CLOCKSOURCE_D2PCLK2 = 0x01U, /*!< Domain2 PCLK2 clock source */
- USART_CLOCKSOURCE_D3PCLK1 = 0x02U, /*!< Domain3 PCLK1 clock source */
- USART_CLOCKSOURCE_PLL2 = 0x04U, /*!< PLL2Q clock source */
- USART_CLOCKSOURCE_HSI = 0x08U, /*!< HSI clock source */
- USART_CLOCKSOURCE_CSI = 0x10U, /*!< CSI clock source */
- USART_CLOCKSOURCE_LSE = 0x20U, /*!< LSE clock source */
- USART_CLOCKSOURCE_PLL3 = 0x40U, /*!< PLL3Q clock source */
- USART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */
-}USART_ClockSourceTypeDef;
-
-
-/**
- * @brief USART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- USART_InitTypeDef Init; /*!< USART communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< USART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< USART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
-
- uint16_t Mask; /*!< USART Rx RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code */
-
-}USART_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
- * @{
- */
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
-#define USART_STOPBITS_1 ((uint32_t)0x00000000U) /*!< USART frame with 1 stop bit */
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_Parity USART Parity
- * @{
- */
-#define USART_PARITY_NONE ((uint32_t)0x00000000U) /*!< No parity */
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup USART_Mode USART Mode
- * @{
- */
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup USART_Over_Sampling USART Over Sampling
- * @{
- */
-#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000U) /*!< Oversampling by 16 */
-#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock USART Clock
- * @{
- */
-#define USART_CLOCK_DISABLE ((uint32_t)0x00000000U) /*!< USART clock disable */
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
- * @{
- */
-#define USART_POLARITY_LOW ((uint32_t)0x00000000U) /*!< USART Clock signal is steady Low */
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
- * @{
- */
-#define USART_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< USART frame phase on first clock transition */
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit USART Last Bit
- * @{
- */
-#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_Prescaler USART Prescaler
- * @{
- */
-#define USART_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< USART clock /1 */
-#define USART_PRESCALER_DIV2 ((uint32_t)0x00000001U) /*!< USART clock /2 */
-#define USART_PRESCALER_DIV4 ((uint32_t)0x00000002U) /*!< USART clock /4 */
-#define USART_PRESCALER_DIV6 ((uint32_t)0x00000003U) /*!< USART clock /6 */
-#define USART_PRESCALER_DIV8 ((uint32_t)0x00000004U) /*!< USART clock /8 */
-#define USART_PRESCALER_DIV10 ((uint32_t)0x00000005U) /*!< USART clock /10 */
-#define USART_PRESCALER_DIV12 ((uint32_t)0x00000006U) /*!< USART clock /12 */
-#define USART_PRESCALER_DIV16 ((uint32_t)0x00000007U) /*!< USART clock /16 */
-#define USART_PRESCALER_DIV32 ((uint32_t)0x00000008U) /*!< USART clock /32 */
-#define USART_PRESCALER_DIV64 ((uint32_t)0x00000009U) /*!< USART clock /64 */
-#define USART_PRESCALER_DIV128 ((uint32_t)0x0000000AU) /*!< USART clock /128 */
-#define USART_PRESCALER_DIV256 ((uint32_t)0x0000000BU) /*!< USART clock /256 */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Slave_Select_management USART Slave Select Management
- * @{
- */
-#define USART_NSS_HW ((uint32_t)0x00000000U) /*!< USART Hardware NSS management */
-#define USART_NSS_SW ((uint32_t)USART_CR2_DIS_NSS) /*!< USART Software NSS management */
-/**
- * @}
- */
-
-/** @defgroup USART_Slave_Mode USART Synchronous Slave mode enable
- * @{
- */
-#define USART_SLAVEMODE_DISABLE ((uint32_t)0x00000000U) /*!< USART SPI Slave Mode Enable */
-#define USART_SLAVEMODE_ENABLE ((uint32_t)USART_CR2_SLVEN) /*!< USART SPI Slave Mode Disable */
-/**
- * @}
- */
-
-
- /** @defgroup USART_FIFO_mode USART FIFO mode
- * @brief USART FIFO mode
- * @{
- */
-#define USART_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
-#define USART_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN) /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup USART_TXFIFO_threshold_level USART TXFIFO threshold level
- * @brief USART TXFIFO level
- * @{
- */
-#define USART_TXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U) /*!< TXFIFO reaches 1/8 of its depth */
-#define USART_TXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_TXFTCFG_0) /*!< TXFIFO reaches 1/4 of its depth */
-#define USART_TXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 1/2 of its depth */
-#define USART_TXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO reaches 3/4 of its depth */
-#define USART_TXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_TXFTCFG_2) /*!< TXFIFO reaches 7/8 of its depth */
-#define USART_TXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty */
-/**
- * @}
- */
-
-/** @defgroup USART_RXFIFO_threshold_level USART RXFIFO threshold level
- * @brief USART RXFIFO level
- * @{
- */
-#define USART_RXFIFO_THRESHOLD_1_8 ((uint32_t)0x00000000U) /*!< RXFIFO reaches 1/8 of its depth */
-#define USART_RXFIFO_THRESHOLD_1_4 ((uint32_t)USART_CR3_RXFTCFG_0) /*!< RXFIFO reaches 1/4 of its depth */
-#define USART_RXFIFO_THRESHOLD_1_2 ((uint32_t)USART_CR3_RXFTCFG_1) /*!< RXFIFO reaches 1/2 of its depth */
-#define USART_RXFIFO_THRESHOLD_3_4 ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO reaches 3/4 of its depth */
-#define USART_RXFIFO_THRESHOLD_7_8 ((uint32_t)USART_CR3_RXFTCFG_2) /*!< RXFIFO reaches 7/8 of its depth */
-#define USART_RXFIFO_THRESHOLD_8_8 ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes full */
-/**
- * @}
- */
-
-/** @defgroup USART_Request_Parameters USART Request Parameters
- * @{
- */
-#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */
-#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */
-#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Fullflag */
-#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */
-#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
-#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
-#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
-#define USART_FLAG_UDR USART_ISR_UDR /*!< USART SPI slave underrun error */
-#define USART_FLAG_LBDF USART_ISR_LBDF /*!< USART LIN break detection flag */
-#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
-#define USART_FLAG_TXFNF USART_ISR_TXE /*!< USART TXFIFO not full */
-#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
-#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
-#define USART_FLAG_RXFNE USART_ISR_RXNE /*!< USART RXFIFO not empty */
-#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
-#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
-#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
-#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
-#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(5bits instead of 4bits)
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028U)
-#define USART_IT_TXE ((uint16_t)0x0727U)
-#define USART_IT_TC ((uint16_t)0x0626U)
-#define USART_IT_RXNE ((uint16_t)0x0525U)
-#define USART_IT_IDLE ((uint16_t)0x0424U)
-#define USART_IT_ERR ((uint16_t)0x0060U)
-#define USART_IT_RXFF ((uint16_t)0x183FU)
-#define USART_IT_TXFE ((uint16_t)0x173EU)
-#define USART_IT_RXFT ((uint16_t)0x1A7CU)
-#define USART_IT_TXFT ((uint16_t)0x1B77U)
-
-#define USART_IT_UDR ((uint16_t)0x0D00U)
-#define USART_IT_ORE ((uint16_t)0x0300U)
-#define USART_IT_NE ((uint16_t)0x0200U)
-#define USART_IT_FE ((uint16_t)0x0100U)
-/**
- * @}
- */
-
-/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
- * @{
- */
-#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define USART_CLEAR_UDRCF USART_ICR_UDRCF /*!< UnderRun Error Clear Flag */
-#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
-/**
- * @}
- */
-
-/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
- * @{
- */
-#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @brief Reset USART handle state.
- * @param __HANDLE__: USART handle.
- * @retval None
- */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief Check whether the specified USART flag is set or not.
- * @param __HANDLE__: specifies the USART Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_TXFT: TXFIFO threshold flag
- * @arg USART_FLAG_RXFT: RXFIFO threshold flag
- * @arg USART_FLAG_RXFF: RXFIFO Full flag
- * @arg USART_FLAG_TXFE: TXFIFO Empty flag
- * @arg USART_FLAG_REACK: Receive enable ackowledge flag
- * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
- * @arg USART_FLAG_BUSY: Busy flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_UDR: UnderRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified USART pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_TXFT: TXFIFO threshold flag
- * @arg USART_FLAG_RXFT: RXFIFO threshold flag
- * @arg USART_FLAG_RXFF: RXFIFO Full flag
- * @arg USART_FLAG_TXFE: TXFIFO Empty flag
- * @arg USART_FLAG_REACK: Receive enable ackowledge flag
- * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
- * @arg USART_FLAG_WUF: Wake up from stop mode flag
- * @arg USART_FLAG_RWU: Receiver wake up flag (is the USART in mute mode)
- * @arg USART_FLAG_SBKF: Send Break flag
- * @arg USART_FLAG_CMF: Character match flag
- * @arg USART_FLAG_BUSY: Busy flag
- * @arg USART_FLAG_ABRF: Auto Baud rate detection flag
- * @arg USART_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg USART_FLAG_RTOF: Receiver timeout flag
- * @arg USART_FLAG_LBD: LIN Break detection flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-
-/** @brief Enable the specified USART interrupt.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __INTERRUPT__: specifies the USART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg USART_IT_RXFF: RXFIFO Full interrupt
- * @arg USART_IT_TXFE: TXFIFO Empty interrupt
- * @arg USART_IT_RXFT: RXFIFO threshold interrupt
- * @arg USART_IT_TXFT: TXFIFO threshold interrupt
- * @arg USART_IT_TXE : Transmit Data Register empty interrupt
- * @arg USART_IT_TC : Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE : Parity Error interrupt
- * @arg USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-/** @brief Disable the specified USART interrupt.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __INTERRUPT__: specifies the USART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg USART_IT_RXFF: RXFIFO Full interrupt
- * @arg USART_IT_TXFE: TXFIFO Empty interrupt
- * @arg USART_IT_RXFT: RXFIFO threshold interrupt
- * @arg USART_IT_TXFT: TXFIFO threshold interrupt
- * @arg USART_IT_TXE : Transmit Data Register empty interrupt
- * @arg USART_IT_TC : Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE : Parity Error interrupt
- * @arg USART_IT_ERR : Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-
-/** @brief Check whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT__: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_RXFF: RXFIFO Full interrupt
- * @arg USART_IT_TXFE: TXFIFO Empty interrupt
- * @arg USART_IT_RXFT: RXFIFO threshold interrupt
- * @arg USART_IT_TXFT: TXFIFO threshold interrupt
- * @arg USART_IT_TXE : Transmit Data Register empty interrupt
- * @arg USART_IT_TC : Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE : OverRun Error interrupt
- * @arg USART_IT_UDR : UnderRun Error interrupt
- * @arg USART_IT_NE : Noise Error interrupt
- * @arg USART_IT_FE : Framing Error interrupt
- * @arg USART_IT_PE : Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Check whether the specified USART interrupt source is enabled or not.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT__: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_RXFF: RXFIFO Full interrupt
- * @arg USART_IT_TXFE: TXFIFO Empty interrupt
- * @arg USART_IT_RXFT: RXFIFO threshold interrupt
- * @arg USART_IT_TXFT: TXFIFO threshold interrupt
- * @arg USART_IT_TXE : Transmit Data Register empty interrupt
- * @arg USART_IT_TC : Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE : OverRun Error interrupt
- * @arg USART_IT_NE : Noise Error interrupt
- * @arg USART_IT_FE : Framing Error interrupt
- * @arg USART_IT_PE : Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
- (((uint16_t)(__IT__)) & USART_IT_MASK)))
-
-
-/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt.
- * This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_UDRCF: UnderRun Error Clear Flag
- * @arg USART_CLEAR_TXFECF: TXFIFO empty Clear Flag
- * @retval None
- */
-#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Clear the USART PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_PEF)
-
-/** @brief Clear the USART FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_FEF)
-
-/** @brief Clear the USART NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_NEF)
-
-/** @brief Clear the USART ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_OREF)
-
-/** @brief Clear the USART IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_IDLEF)
-
-/** @brief Clear the USART UDR pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_UDRCF)
-
-/** @brief Clear the USART TX FIFO empty clear flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_IT((__HANDLE__), USART_CLEAR_TXFECF)
-
-
-
-/** @brief Set a specific USART request flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __REQ__: specifies the request flag to set.
- * This parameter can be one of the following values:
- * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
-
-/** @brief Enable the USART one bit sample method.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the USART one bit sample method.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable USART.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable USART.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private variables -----------------------------------------------------*/
-/** @defgroup USART_Private_Variables USART Private Variables
- * @{
- */
-static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-
-/** @brief Report the USART clock source.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __CLOCKSOURCE__: output variable.
- * @retval the USART clocking source, written in __CLOCKSOURCE__.
- */
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART1CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART2CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_D2PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART3CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
- case RCC_USART6CLKSOURCE_D2PCLK2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \
- break; \
- case RCC_USART6CLKSOURCE_PLL3: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \
- break; \
- case RCC_USART6CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART6CLKSOURCE_CSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \
- break; \
- case RCC_USART6CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- } \
- } \
- } while(0)
-
-/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
- * @param __PCLK__: USART clock.
- * @param __BAUD__: Baud rate set by the user.
- * @param __PRESCALER__: UART prescaler value.
- * @retval Division result
- */
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __PRESCALER__) (((((__PCLK__)/USARTPrescTable[(__PRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__))
-
-/** @brief Check USART Baud rate.
- * @param __BAUDRATE__: Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8).
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
-
-/**
- * @brief Ensure that USART frame number of stop bits is valid.
- * @param __STOPBITS__: USART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
- ((__STOPBITS__) == USART_STOPBITS_1) || \
- ((__STOPBITS__) == USART_STOPBITS_1_5) || \
- ((__STOPBITS__) == USART_STOPBITS_2))
-
-/**
- * @brief Ensure that USART frame parity is valid.
- * @param __PARITY__: USART frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
- ((__PARITY__) == USART_PARITY_EVEN) || \
- ((__PARITY__) == USART_PARITY_ODD))
-
-/**
- * @brief Ensure that USART communication mode is valid.
- * @param __MODE__: USART communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
-
-/**
- * @brief Ensure that USART oversampling is valid.
- * @param __SAMPLING__: USART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-
-/**
- * @brief Ensure that USART clock state is valid.
- * @param __CLOCK__: USART clock state.
- * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
- */
-#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
- ((__CLOCK__) == USART_CLOCK_ENABLE))
-
-/**
- * @brief Ensure that USART frame polarity is valid.
- * @param __CPOL__: USART frame polarity.
- * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
-#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
-
-/**
- * @brief Ensure that USART frame phase is valid.
- * @param __CPHA__: USART frame phase.
- * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
- */
-#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
-
-/**
- * @brief Ensure that USART frame last bit clock pulse setting is valid.
- * @param __LASTBIT__: USART frame last bit clock pulse setting.
- * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
- */
-#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
- ((__LASTBIT__) == USART_LASTBIT_ENABLE))
-
-/**
- * @brief Ensure that USART request parameter is valid.
- * @param __PARAM__: USART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
-
-/**
- * @brief Ensure that USART Prescaler is valid.
- * @param __PRESCALER__: USART Prescaler value.
- * @retval SET (__PRESCALER__ is valid) or RESET (__PRESCALER__ is invalid)
- */
-#define IS_USART_PRESCALER(__PRESCALER__) (((__PRESCALER__) == USART_PRESCALER_DIV1) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV2) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV4) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV6) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV8) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV10) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV12) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV16) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV32) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV64) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV128) || \
- ((__PRESCALER__) == USART_PRESCALER_DIV256))
-
-/**
- * @brief Ensure that USART NSS is valid.
- * @param __NSS__: USART Negative Slave Select pin management.
- * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
- */
-#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HW) || ((__NSS__) == USART_NSS_SW))
-
-/**
- * @brief Ensure that USART FIFO mode is valid.
- * @param __STATE__: USART FIFO mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
- ((__STATE__) == USART_FIFOMODE_ENABLE))
-
-/**
- * @brief Ensure that USART TXFIFO threshold level is valid.
- * @param __THRESHOLD__: USART TXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
-
-/**
- * @brief Ensure that USART RXFIFO threshold level is valid.
- * @param __THRESHOLD__: USART RXFIFO threshold level.
- * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
- */
-#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
- ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
- ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
- ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
- ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
- ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
-
-/**
- * @brief Ensure that USART Slave Mode is valid.
- * @param __STATE__: USART Slave Mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
- ((__STATE__) == USART_SLAVEMODE_ENABLE))
-
-/**
- * @}
- */
-
-/* Include USART HAL Extended module */
-#include "stm32h7xx_hal_usart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h
deleted file mode 100644
index d0549ae..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_usart_ex.h
- * @author MCD Application Team
- * @brief Header file of USART HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_USART_EX_H
-#define __STM32H7xx_HAL_USART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USARTEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
- * @{
- */
-
-/** @defgroup USARTEx_Word_Length USARTEx Word Length
- * @{
- */
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
- * @{
- */
-
-/** @brief Compute the USART mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__: specifies the USART Handle.
- * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#define USART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FF ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007F ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003F ; \
- } \
- } \
-} while(0)
-
-/**
- * @brief Ensure that USART frame length is valid.
- * @param __LENGTH__: USART frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
- ((__LENGTH__) == USART_WORDLENGTH_8B) || \
- ((__LENGTH__) == USART_WORDLENGTH_9B))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_USART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h
deleted file mode 100644
index 9bd8e9b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_WWDG_H
-#define __STM32H7xx_HAL_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
- * @{
- */
-
-/**
- * @brief WWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
- This parameter can be a value of @ref WWDG_Prescaler */
-
- uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
- This parameter can be a value of @ref WWDG_EWI_Mode */
-
-}WWDG_InitTypeDef;
-
-/**
- * @brief WWDG handle Structure definition
- */
-typedef struct
-{
- WWDG_TypeDef *Instance; /*!< Register base address */
-
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-
-}WWDG_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
- * @{
- */
-#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
- * @brief WWDG Flag definition
- * @{
- */
-#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
- * @{
- */
-#define WWDG_PRESCALER_1 ((uint32_t)(0x00000000U)) /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 ((uint32_t)(WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 ((uint32_t)(WWDG_CFR_WDGTB1)) /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-#define WWDG_PRESCALER_16 ((uint32_t)(WWDG_CFR_WDGTB2)) /*!< WWDG counter clock = (PCLK1/4096)/16 */
-#define WWDG_PRESCALER_32 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/32 */
-#define WWDG_PRESCALER_64 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1)) /*!< WWDG counter clock = (PCLK1/4096)/64 */
-#define WWDG_PRESCALER_128 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/128 */
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
- * @{
- */
-#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
-#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
- * @{
- */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8) || \
- ((__PRESCALER__) == WWDG_PRESCALER_16) || \
- ((__PRESCALER__) == WWDG_PRESCALER_32) || \
- ((__PRESCALER__) == WWDG_PRESCALER_64) || \
- ((__PRESCALER__) == WWDG_PRESCALER_128))
-
-#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
- ((__MODE__) == WWDG_EWI_DISABLE))
-/**
- * @}
- */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the WWDG peripheral.
- * @param __HANDLE__ WWDG handle
- * @retval None
- */
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
- * @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__ specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
- * @brief Check whether the selected WWDG interrupt has occurred or not.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the it to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief Clear the WWDG interrupt pending bits.
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified WWDG flag is set or not.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the WWDG's pending flags.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval None
- */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))
-
-/** @brief Check whether the specified WWDG interrupt source is enabled or not.
- * @param __HANDLE__ WWDG Handle.
- * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early Wakeup Interrupt
- * @retval state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/**
- * @}
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h
deleted file mode 100644
index 5da99b4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_delayblock.h
- * @author MCD Application Team
- * @brief Header file of Delay Block module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_DLYB_H
-#define __STM32H7xx_LL_DLYB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DELAYBLOCK_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
- * @{
- */
-
-
-#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */
-
-/** @defgroup DLYB_Instance DLYB Instance
- * @{
- */
-#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
- ((INSTANCE) == DLYB_SDMMC2) || \
- ((INSTANCE) == DLYB_QUADSPI))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions
- * @{
- */
-HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *dlyb);
-HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *dlyb);
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_DLYB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h
deleted file mode 100644
index efa0b71..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h
+++ /dev/null
@@ -1,1350 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_fmc.h
- * @author MCD Application Team
- * @brief Header file of FMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_FMC_H
-#define __STM32H7xx_LL_FMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FMC_LL
- * @{
- */
-
-/** @addtogroup FMC_LL_Private_Macros
- * @{
- */
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
- ((BANK) == FMC_NORSRAM_BANK2) || \
- ((BANK) == FMC_NORSRAM_BANK3) || \
- ((BANK) == FMC_NORSRAM_BANK4))
-
-#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
- ((__MODE__) == FMC_ACCESS_MODE_B) || \
- ((__MODE__) == FMC_ACCESS_MODE_C) || \
- ((__MODE__) == FMC_ACCESS_MODE_D))
-
-#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
-
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
-
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
- ((STATE) == FMC_NAND_ECC_ENABLE))
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
- ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
-
-#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
- ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
- ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
-
-#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
- ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
-
-#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
- ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
- ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
-
-#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
- ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
-
-#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
- ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
- ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
-
-/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
- * @{
- */
-#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
- * @{
- */
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time FMC Setup Time
- * @{
- */
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
- * @{
- */
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
-/**
- * @}
- */
-
-/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
-/**
- * @}
- */
-
-#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
-
-#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-/** @defgroup FMC_Data_Latency FMC Data Latency
- * @{
- */
-#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
- * @}
- */
-
-#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FMC_WRITE_BURST_ENABLE))
-
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-
-/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
- * @{
- */
-#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
- * @{
- */
-#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
- * @{
- */
-#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
- * @{
- */
-#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_CLK_Division FMC CLK Division
- * @{
- */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
- * @{
- */
-#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
- * @{
- */
-#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
- * @{
- */
-#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
- * @{
- */
-#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
- * @{
- */
-#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
- * @{
- */
-#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
- * @{
- */
-#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
- * @{
- */
-#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
- * @{
- */
-#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
- * @{
- */
-#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
- * @{
- */
-#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
- * @{
- */
-#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
- * @{
- */
-#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
- * @{
- */
-#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
-/**
- * @}
- */
-
-#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
- ((BANK) == FMC_SDRAM_BANK2))
-
-#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
- ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
-
-#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
- ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
- ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
-
-#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
- ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
-
-
-#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
- ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
- ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
-
-#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
- ((__SIZE__) == FMC_PAGE_SIZE_128) || \
- ((__SIZE__) == FMC_PAGE_SIZE_256) || \
- ((__SIZE__) == FMC_PAGE_SIZE_512) || \
- ((__SIZE__) == FMC_PAGE_SIZE_1024))
-
-#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
- ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
- * @{
- */
-#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
-#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
-#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
-
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank3
-#define FMC_SDRAM_DEVICE FMC_Bank5_6
-
-/**
- * @brief FMC NORSRAM Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
- uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
- uint32_t MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory device.
- This parameter can be a value of @ref FMC_Memory_Type */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
- uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
- uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
- uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
-
- uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
-
- uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
-
- uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
-
- uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
-
- uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
-
- uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Write_FIFO */
-
- uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FMC_Page_Size */
-
-}FMC_NORSRAM_InitTypeDef;
-
-/**
- * @brief FMC NORSRAM Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
-
- uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
-
- uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAM_TimingTypeDef;
-
-/**
- * @brief FMC NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
-
- uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
-
- uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FMC_NAND_InitTypeDef;
-
-/**
- * @brief FMC NAND Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-}FMC_NAND_PCC_TimingTypeDef;
-
-/**
- * @brief FMC SDRAM Configuration Structure definition
- */
-typedef struct
-{
- uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
- This parameter can be a value of @ref FMC_SDRAM_Bank */
-
- uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
- This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
-
- uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
- This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
-
- uint32_t MemoryDataWidth; /*!< Defines the memory device width.
- This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
-
- uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
- This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
-
- uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
- This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
-
- uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
- This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
-
- uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
- to disable the clock before changing frequency.
- This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
-
- uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
- commands during the CAS latency and stores data in the Read FIFO.
- This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
-
- uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
- This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
-}FMC_SDRAM_InitTypeDef;
-
-/**
- * @brief FMC SDRAM Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
- an active or Refresh command in number of memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
- issuing the Activate command in number of memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
- cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
- and the delay between two consecutive Refresh commands in number of
- memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
- in number of memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
- command in number of memory clock cycles.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-}FMC_SDRAM_TimingTypeDef;
-
-/**
- * @brief SDRAM command parameters structure definition
- */
-typedef struct
-{
- uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
- This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
-
- uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
- This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
-
- uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
- in auto refresh mode.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
- uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
-}FMC_SDRAM_CommandTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
- * @{
- */
-
-/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
- * @{
- */
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
- * @{
- */
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Memory_Type FMC Memory Type
- * @{
- */
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
- * @{
- */
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
- * @{
- */
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
- * @{
- */
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
- * @{
- */
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Timing FMC Wait Timing
- * @{
- */
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Operation FMC Write Operation
- * @{
- */
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal FMC Wait Signal
- * @{
- */
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Extended_Mode FMC Extended Mode
- * @{
- */
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
- * @{
- */
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Page_Size FMC Page Size
- * @{
- */
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
-#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
-#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
-#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
-#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Burst FMC Write Burst
- * @{
- */
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock FMC Continuous Clock
- * @{
- */
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_FIFO FMC Write FIFO
- * @{
- */
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Access_Mode FMC Access Mode
- * @{
- */
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
- * @{
- */
-/** @defgroup FMC_NAND_Bank FMC NAND Bank
- * @{
- */
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_feature FMC Wait feature
- * @{
- */
-#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
- * @{
- */
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
- * @{
- */
-#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC FMC ECC
- * @{
- */
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
- * @{
- */
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
- * @{
- */
-/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
- * @{
- */
-#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
- * @{
- */
-#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
-#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
- * @{
- */
-#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
-#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
- * @{
- */
-#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
- * @{
- */
-#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
- * @{
- */
-#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
-#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
-#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
- * @{
- */
-#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
- * @{
- */
-#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
-#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
- * @{
- */
-#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
- * @{
- */
-#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
-#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
-#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
- * @{
- */
-#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
-#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
-#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
-#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
-#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
-#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
- * @{
- */
-#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
-#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
-#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
- * @{
- */
-#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
-#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
-#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
- * @{
- */
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
-#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
- * @{
- */
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
-#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
-#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
- * @{
- */
-
-/**
- * @brief Enable the FMC IP.
- * @retval None
- */
-#define __FMC_ENABLE() (FMC_Bank1->BTCR[0] |= FMC_BCR1_FMCEN)
-
-/**
- * @brief Disable the FMC IP.
- * @retval None
- */
-#define __FMC_DISABLE() (FMC_Bank1->BTCR[0] &= ~FMC_BCR1_FMCEN)
-
-
-/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
-
-/**
- * @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
- * @retval None
- */
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
-
-/**
- * @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
- * @retval None
- */
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
-
-/**
- * @brief Enable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @retval None
- */
-#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
-
-/**
- * @brief Disable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @retval None
- */
-#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt FMC Interrupt
- * @brief macros to handle FMC interrupts
- * @{
- */
-
-/**
- * @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND instance
- * @param __INTERRUPT__: FMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __INTERRUPT__: FMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
-
-/**
- * @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __FLAG__: FMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
-
-/**
- * @brief Enable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
- * @retval None
- */
-#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
- * @retval None
- */
-#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
-
-/**
- * @brief Get flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
- * This parameter can be any combination of the following values:
- * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
- * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
- * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
- * This parameter can be any combination of the following values:
- * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
- * @retval None
- */
-#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
- * @{
- */
-
-/** @defgroup FMC_LL_NORSRAM NOR SRAM
- * @{
- */
-/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
- * @{
- */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_NAND NAND
- * @{
- */
-/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
- * @{
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_SDRAM SDRAM
- * @{
- */
-/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
- * @{
- */
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
-HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
-HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h
deleted file mode 100644
index 014ccef..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h
+++ /dev/null
@@ -1,1089 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_sdmmc.h
- * @author MCD Application Team
- * @brief Header file of SDMMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_LL_SDMMC_H
-#define STM32H7xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_Driver
- * @{
- */
-
-/** @addtogroup SDMMC_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
- * @{
- */
-
-/**
- * @brief SDMMC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
-
- uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
-
- uint32_t BusWide; /*!< Specifies the SDMMC bus width.
- This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
-
- uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
- This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
-
-}SDMMC_InitTypeDef;
-
-
-/**
- * @brief SDMMC Command Control structure
- */
-typedef struct
-{
- uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register. */
-
- uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
- Max_Data = 64 */
-
- uint32_t Response; /*!< Specifies the SDMMC response type.
- This parameter can be a value of @ref SDMMC_LL_Response_Type */
-
- uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
- enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
-
- uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_CPSM_State */
-}SDMMC_CmdInitTypeDef;
-
-
-/**
- * @brief SDMMC Data Control structure
- */
-typedef struct
-{
- uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
-
- uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
-
- uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
-
- uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_DPSM_State */
-}SDMMC_DataInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
- * @{
- */
-#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
-
-/**
- * @brief SDMMC Commands Index
- */
-#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
-#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
-
-/**
- * @brief Following commands are SD Card Specific commands.
- * SDMMC_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
-
-/**
- * @brief Following commands are SD Card Specific security commands.
- * SDMMC_CMD_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
-#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
-
-/**
- * @brief Masks for errors Card Status R1 (OCR Register)
- */
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
-#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
-#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
-#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
-#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
-#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
-#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
-#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
-#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
-#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
-#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
-#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
-#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
-#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
-#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
-#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
-#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
-
-/**
- * @brief Masks for R6 Response
- */
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
-#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
-#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
-
-#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
-#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
-#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
-#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
-#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
-#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
-#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
-#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
-
-#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
-
-#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
-
-#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
-
-#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
-#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
-#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
-
-#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
-
-#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
-#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
-#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
-#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
-#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
-
-#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
-#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
-
-/**
- * @brief Command Class supported
- */
-#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
-
-#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
-#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
-#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
-
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
- * @{
- */
-#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
-#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
-
-#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
- * @{
- */
-#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
-#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
-
-#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
- * @{
- */
-#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
-#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
-#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
-
-#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
- ((WIDE) == SDMMC_BUS_WIDE_4B) || \
- ((WIDE) == SDMMC_BUS_WIDE_8B))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
- * @{
- */
-#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
-#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
-
-#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
- * @{
- */
-/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
-#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
-/**
- * @}
- */
-
-
-/** @defgroup SDMMC_LL_Command_Index Command Index
- * @{
- */
-#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Response_Type Response Type
- * @{
- */
-#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
-#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
-#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
-
-#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
- ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
- ((RESPONSE) == SDMMC_RESPONSE_LONG))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
- * @{
- */
-#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
-#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
-#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
-
-#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
- ((WAIT) == SDMMC_WAIT_IT) || \
- ((WAIT) == SDMMC_WAIT_PEND))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
- * @{
- */
-#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
-#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
-
-#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
- ((CPSM) == SDMMC_CPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Response_Registers Response Register
- * @{
- */
-#define SDMMC_RESP1 ((uint32_t)0x00000000U)
-#define SDMMC_RESP2 ((uint32_t)0x00000004U)
-#define SDMMC_RESP3 ((uint32_t)0x00000008U)
-#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
-
-#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
- ((RESP) == SDMMC_RESP2) || \
- ((RESP) == SDMMC_RESP3) || \
- ((RESP) == SDMMC_RESP4))
-
-/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
- * @{
- */
-#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
-#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
-#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
-#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
-
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
- * @{
- */
-#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
- * @{
- */
-#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
-#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
-#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
-#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
-#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
-#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
-#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
- * @{
- */
-#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
-#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
-
-#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
- * @{
- */
-#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
-#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
-
-#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
- * @{
- */
-#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
-#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
-
-#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
- ((DPSM) == SDMMC_DPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
- * @{
- */
-#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
-#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
-
-#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
- * @{
- */
-#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
-#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
-#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
-#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
-#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
-#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
-#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
-#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
-#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
-#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
-#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
-#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
-#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
-#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
-#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
-#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
-#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
-#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
-#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
-#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
-#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
-#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
-#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Flags Flags
- * @{
- */
-#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
-#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
-#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
-#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
-#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
-#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
-#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
-#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
-#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
-#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
-#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
-#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
-#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
-#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
-#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
-#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
-#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
-#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
-#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
-#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
-#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
-#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
-#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
-#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
-#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
-#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
-#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
-#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
-#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
-
-#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
- SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
- SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
- SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
- SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
- SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
- SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
-
-#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
- SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
-
-#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
- SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
- SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
- SDMMC_FLAG_IDMABTC))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
- * @{
- */
-
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
- * @brief SDMMC_LL registers bit address in the alias region
- * @{
- */
-/* ---------------------- SDMMC registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
- SDMMC_CLKCR_WIDBUS |\
- SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDMMC DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
- SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
- SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
- SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
-
-/* SDMMC Initialization Frequency (400KHz max) for IP CLK 200MHz*/
-#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
-
-/* SDMMC Default Speed Frequency (25Mhz max) for IP CLK 200MHz*/
-#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)
-
-/* SDMMC High Speed Frequency (50Mhz max) for IP CLK 200MHz*/
-#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
- * @brief Enable the SDMMC device interrupt.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
- * @brief Disable the SDMMC device interrupt.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified SDMMC flag is set or not.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
- * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
- * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval The new state of SDMMC_FLAG (SET or RESET).
- */
-#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
-
-
-/**
- * @brief Clears the SDMMC pending flags.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
- * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
- * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
- * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
- * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
- * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
- * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
- * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
- * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
- * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
- * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
- * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
- * @retval None
- */
-#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
- * @brief Checks whether the specified SDMMC interrupt has occurred or not.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
- * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
- * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval The new state of SDMMC_IT (SET or RESET).
- */
-#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clears the SDMMC's interrupt pending bits.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
- * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
- * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
- * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
- * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
- * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
- * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
- * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
- * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
- * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
- * @retval None
- */
-#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
-
-/**
- * @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
-
-/**
- * @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
-
-/**
- * @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
-
-/**
- * @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
-
-/**
- * @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
-
-/**
- * @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
-
-/**
- * @brief Enable the CMDTRANS mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
-
-/**
- * @brief Disable the CMDTRANS mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
-
-/**
- * @brief Enable the CMDSTOP mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
-
-/**
- * @brief Disable the CMDSTOP mode.
- * @param __INSTANCE__ : Pointer to SDMMC register base
- * @retval None
- */
-#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
- * @{
- */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
-/**
- * @}
- */
-
-/* I/O operation functions *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
- * @{
- */
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
- * @{
- */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
-
-/* SDMMC Commands management functions */
-uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
-uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
-uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
-uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
-uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
-uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
-uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
-uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32H7xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
deleted file mode 100644
index bb1f0dc..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_usb.h
- * @author MCD Application Team
- * @brief Header file of USB Core HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_USB_H
-#define __STM32H7xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL
- * @{
- */
-
-/** @addtogroup USB_Core
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief USB Mode definition
- */
-typedef enum
-{
- USB_OTG_DEVICE_MODE = 0U,
- USB_OTG_HOST_MODE = 1U,
- USB_OTG_DRD_MODE = 2U
-
-}USB_OTG_ModeTypeDef;
-
-/**
- * @brief URB States definition
- */
-typedef enum {
- URB_IDLE = 0U,
- URB_DONE,
- URB_NOTREADY,
- URB_NYET,
- URB_ERROR,
- URB_STALL
-
-}USB_OTG_URBStateTypeDef;
-
-/**
- * @brief Host channel States definition
- */
-typedef enum {
- HC_IDLE = 0U,
- HC_XFRC,
- HC_HALTED,
- HC_NAK,
- HC_NYET,
- HC_STALL,
- HC_XACTERR,
- HC_BBLERR,
- HC_DATATGLERR
-
-}USB_OTG_HCStateTypeDef;
-
-/**
- * @brief PCD Initialization Structure definition
- */
-typedef struct
-{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t Host_channels; /*!< Host Channels number.
- This parameter Depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
-
- uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS_ */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY_ */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
-
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
-
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
-
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
-
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
-
-}USB_OTG_CfgTypeDef;
-
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
-
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t even_odd_frame; /*!< IFrame parity
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint16_t tx_fifo_num; /*!< Transmission FIFO number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-
-}USB_OTG_EPTypeDef;
-
-typedef struct
-{
- uint8_t dev_addr ; /*!< USB device address.
- This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
-
- uint8_t ch_num; /*!< Host channel number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_num; /*!< Endpoint number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
-
- uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
-
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
-
- uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
-
- uint16_t max_packet; /*!< Endpoint Max packet size.
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t data_pid; /*!< Initial data PID.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
-
- uint32_t xfer_len; /*!< Current transfer length. */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
-
- uint8_t toggle_in; /*!< IN transfer current toggle flag.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t toggle_out; /*!< OUT transfer current toggle flag
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
-
- uint32_t ErrCnt; /*!< Host channel error count.*/
-
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
- This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
-
-}USB_OTG_HCTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup USB_Core_Mode_ USB Core Mode
- * @{
- */
-#define USB_OTG_MODE_DEVICE 0U
-#define USB_OTG_MODE_HOST 1U
-#define USB_OTG_MODE_DRD 2U
-/**
- * @}
- */
-
-/** @defgroup USB_Core_Speed_ USB Core Speed
- * @{
- */
-#define USB_OTG_SPEED_HIGH 0U
-#define USB_OTG_SPEED_HIGH_IN_FULL 1U
-#define USB_OTG_SPEED_LOW 2U
-#define USB_OTG_SPEED_FULL 3U
-/**
- * @}
- */
-
-/** @defgroup USB_Core_PHY_ USB Core PHY
- * @{
- */
-#define USB_OTG_ULPI_PHY 1U
-#define USB_OTG_EMBEDDED_PHY 2U
-/**
- * @}
- */
-
-/** @defgroup USB_Core_MPS_ USB Core MPS
- * @{
- */
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
-/**
- * @}
- */
-
-/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
- * @{
- */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
- * @{
- */
-#define DCFG_FRAME_INTERVAL_80 0U
-#define DCFG_FRAME_INTERVAL_85 1U
-#define DCFG_FRAME_INTERVAL_90 2U
-#define DCFG_FRAME_INTERVAL_95 3U
-/**
- * @}
- */
-
-/** @defgroup USB_EP0_MPS_ USB EP0 MPS
- * @{
- */
-#define DEP0CTL_MPS_64 0U
-#define DEP0CTL_MPS_32 1U
-#define DEP0CTL_MPS_16 2U
-#define DEP0CTL_MPS_8 3U
-/**
- * @}
- */
-
-/** @defgroup USB_EP_Speed_ USB EP Speed
- * @{
- */
-#define EP_SPEED_LOW 0U
-#define EP_SPEED_FULL 1U
-#define EP_SPEED_HIGH 2U
-/**
- * @}
- */
-
-/** @defgroup USB_EP_Type_ USB EP Type
- * @{
- */
-#define EP_TYPE_CTRL 0U
-#define EP_TYPE_ISOC 1U
-#define EP_TYPE_BULK 2U
-#define EP_TYPE_INTR 3U
-#define EP_TYPE_MSK 3U
-/**
- * @}
- */
-
-/** @defgroup USB_STS_Defines_ USB STS Defines
- * @{
- */
-#define STS_GOUT_NAK 1U
-#define STS_DATA_UPDT 2U
-#define STS_XFER_COMP 3U
-#define STS_SETUP_COMP 4U
-#define STS_SETUP_UPDT 6U
-/**
- * @}
- */
-
-/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
- * @{
- */
-#define HCFG_30_60_MHZ 0U
-#define HCFG_48_MHZ 1U
-#define HCFG_6_MHZ 2U
-/**
- * @}
- */
-
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
- * @{
- */
-#define HPRT0_PRTSPD_HIGH_SPEED 0U
-#define HPRT0_PRTSPD_FULL_SPEED 1U
-#define HPRT0_PRTSPD_LOW_SPEED 2U
-/**
- * @}
- */
-
-#define HCCHAR_CTRL 0U
-#define HCCHAR_ISOC 1U
-#define HCCHAR_BULK 2U
-#define HCCHAR_INTR 3U
-
-#define HC_PID_DATA0 0U
-#define HC_PID_DATA2 1U
-#define HC_PID_DATA1 2U
-#define HC_PID_SETUP 3U
-
-#define GRXSTS_PKTSTS_IN 2U
-#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
-#define GRXSTS_PKTSTS_CH_HALTED 7U
-
-#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-
-/* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32H7xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
deleted file mode 100644
index 4118453..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
+++ /dev/null
@@ -1,993 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal.c
- * @author MCD Application Team
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs' categories:
- (+) Common HAL APIs
- (+) Services HAL APIs
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/**
- * @brief STM32H7xx HAL Driver version number V1.3.0
- */
-#define __STM32H7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32H7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32H7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
- |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
- |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
- |(__STM32H7xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __IO uint32_t uwTick;
-static uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Functions HAL Private Functions
- * @{
- */
-
-/** @defgroup HAL_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initializes the Flash interface the NVIC allocation and initial clock
- configuration. It initializes the systick also when timeout is needed
- and the backup domain when enabled.
- (+) De-Initializes common part of the HAL.
- (+) Configure The time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) SysTick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general purpose
- timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
- handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called automatically
- at the beginning of the program after reset by HAL_Init() or at any time
- when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at regular
- time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher priority
- (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __weak
- to make override possible in case of other implementations in user file.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is used to initialize the HAL Library; it must be the first
- * instruction to be executed in the main program (before to call any other
- * HAL function), it performs the following:
- * Configures the SysTick to generate an interrupt each 1 millisecond,
- * which is clocked by the HSI (at this stage, the clock is not yet
- * configured and thus the system is running from the internal HSI at 16 MHz).
- * Set NVIC Group Priority to 4.
- * Calls the HAL_MspInit() callback function defined in user file
- * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
- *
- * @note SysTick is used as time base for the HAL_Delay() function, the application
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Init the low level hardware */
- HAL_MspInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function de-Initializes common part of the HAL and stops the systick.
- * This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
- /* Reset of all peripherals */
- __HAL_RCC_AHB3_FORCE_RESET();
- __HAL_RCC_AHB3_RELEASE_RESET();
-
- __HAL_RCC_AHB1_FORCE_RESET();
- __HAL_RCC_AHB1_RELEASE_RESET();
-
- __HAL_RCC_AHB2_FORCE_RESET();
- __HAL_RCC_AHB2_RELEASE_RESET();
-
- __HAL_RCC_AHB4_FORCE_RESET();
- __HAL_RCC_AHB4_RELEASE_RESET();
-
- __HAL_RCC_APB3_FORCE_RESET();
- __HAL_RCC_APB3_RELEASE_RESET();
-
- __HAL_RCC_APB1L_FORCE_RESET();
- __HAL_RCC_APB1L_RELEASE_RESET();
-
- __HAL_RCC_APB1H_FORCE_RESET();
- __HAL_RCC_APB1H_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
- __HAL_RCC_APB4_FORCE_RESET();
- __HAL_RCC_APB4_RELEASE_RESET();
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
- * @note In the default implementation, SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals.
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __weak to be overwritten in case of other
- * implementation in user file.
- * @param TickPriority: Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- uwTickPrio = TickPriority;
- }
- else
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
- (+) Enable/Disable Debug module during SLEEP mode
- (+) Enable/Disable Debug module during STOP mode
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- uwTick += (uint32_t)uwTickFreq;
-}
-
-/**
- * @brief Provides a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- return uwTick;
-}
-
-/**
- * @brief This function returns a tick priority.
- * @retval tick priority
- */
-uint32_t HAL_GetTickPrio(void)
-{
- return uwTickPrio;
-}
-
-/**
- * @brief Set new tick Freq.
- * @retval Status
- */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
- HAL_StatusTypeDef status = HAL_OK;
- assert_param(IS_TICKFREQ(Freq));
-
- if (uwTickFreq != Freq)
- {
- uwTickFreq = Freq;
-
- /* Apply the new tick Freq */
- status = HAL_InitTick(uwTickPrio);
- }
-
- return status;
-}
-
-/**
- * @brief Return tick frequency.
- * @retval tick period in Hz
- */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
- return uwTickFreq;
-}
-
-/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals where uwTick
- * is incremented.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(uint32_t Delay)
-{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a freq to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait += (uint32_t)(uwTickFreq);
- }
-
- while ((HAL_GetTick() - tickstart) < wait)
- {
- }
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-{
- /* Disable SysTick Interrupt */
- SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
- * @brief Returns the HAL revision
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32H7xx_HAL_VERSION;
-}
-
-/**
- * @brief Returns the device revision identifier.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void)
-{
- return((DBGMCU->IDCODE) >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void)
-{
- return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configure the internal voltage reference buffer voltage scale.
- * @param VoltageScaling specifies the output voltage to achieve
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
- * This requires VDDA equal to or higher than 2.4 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
- * This requires VDDA equal to or higher than 2.8 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
- * This requires VDDA equal to or higher than 1.8 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
- * This requires VDDA equal to or higher than 2.1 V.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
-}
-
-/**
- * @brief Configure the internal voltage reference buffer high impedance mode.
- * @param Mode specifies the high impedance mode
- * This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
- * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
-
- MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
-}
-
-/**
- * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
- * @retval None
- */
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
-
- MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
-}
-
-/**
- * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
- * @retval HAL_OK/HAL_TIMEOUT
- */
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
-{
- uint32_t tickstart = 0;
-
- SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait for VRR bit */
- while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
- {
- if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
- *
- * @retval None
- */
-void HAL_SYSCFG_DisableVREFBUF(void)
-{
- CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-
-/**
- * @brief Ethernet PHY Interface Selection either MII or RMII
- * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
- * This parameter can be one of the following values:
- * @arg SYSCFG_ETH_MII : Select the Media Independent Interface
- * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
- * @retval None
- */
-void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
-
- MODIFY_REG(SYSCFG->PMCR, SYCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
-}
-
-
-/**
- * @brief Analog Switch control for dual analog pads.
- * @param SYSCFG_AnalogSwitch: Selects the analog pad
- * This parameter can be one or a combination of the following values:
- * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
- * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
- * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
- * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch
- * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
- * This parameter can be one or a combination of the following values:
- * @arg SYSCFG_SWITCH_PA0_OPEN
- * @arg SYSCFG_SWITCH_PA0_CLOSE
- * @arg SYSCFG_SWITCH_PA1_OPEN
- * @arg SYSCFG_SWITCH_PA1_CLOSE
- * @arg SYSCFG_SWITCH_PC2_OPEN
- * @arg SYSCFG_SWITCH_PC2_CLOSE
- * @arg SYSCFG_SWITCH_PC3_OPEN
- * @arg SYSCFG_SWITCH_PC3_CLOSE
- * @retval None
- */
-
-void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
- assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
-
- MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
-}
-
-
-/**
- * @brief Enables the booster to reduce the total harmonic distortion of the analog
- * switch when the supply voltage is lower than 2.7 V.
- * @note Activating the booster allows to guaranty the analog switch AC performance
- * when the supply voltage is below 2.7 V: in this case, the analog switch
- * performance is the same on the full voltage range
- * @retval None
- */
-void HAL_SYSCFG_EnableBOOST(void)
-{
- SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
-}
-
-/**
- * @brief Disables the booster
- * @note Activating the booster allows to guaranty the analog switch AC performance
- * when the supply voltage is below 2.7 V: in this case, the analog switch
- * performance is the same on the full voltage range
- * @retval None
- */
-void HAL_SYSCFG_DisableBOOST(void)
-{
- CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
-}
-
-
-/**
- * @brief BootCM7 address 0 configuration
- * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
- * This parameter can be one of the following values:
- * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
- * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
- * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
- * @retval None
- */
-void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
- assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
- if ( BootRegister == SYSCFG_BOOT_ADDR0 )
- {
- /* Configure CM7 BOOT ADD0 */
- MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << POSITION_VAL(SYSCFG_UR2_BOOT_ADD0)));
- }
- else
- {
- /* Configure CM7 BOOT ADD1 */
- MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
- }
-
-}
-
-
-/**
- * @brief Enables the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @retval None
- */
-void HAL_EnableCompensationCell(void)
-{
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
-}
-
-/**
- * @brief Power-down the I/O Compensation Cell.
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
- * @retval None
- */
-void HAL_DisableCompensationCell(void)
-{
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
-}
-
-
-/**
- * @brief To Enable optimize the I/O speed when the product voltage is low.
- * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
- * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
- * higher than 2.5 V might be destructive.
- * @retval None
- */
-void HAL_SYSCFG_EnableIOSpeedOptimize(void)
-{
- SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) ;
-}
-
-/**
- * @brief To Disable optimize the I/O speed when the product voltage is low.
- * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
- * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
- * higher than 2.5 V might be destructive.
- * @retval None
- */
-void HAL_SYSCFG_DisableIOSpeedOptimize(void)
-{
- CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) ;
-}
-
-/**
- * @brief Code selection for the I/O Compensation cell
- * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
- * This parameter can be one of the following values:
- * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
- * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
- * @retval None
- */
-void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
- MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
-}
-
-/**
- * @brief Code selection for the I/O Compensation cell
- * @param SYSCFG_PMOSCode: PMOS compensation code
- * This code is applied to the I/O compensation cell when the CS bit of the
- * SYSCFG_CMPCR is set
- * @param SYSCFG_NMOSCode: NMOS compensation code
- * This code is applied to the I/O compensation cell when the CS bit of the
- * SYSCFG_CMPCR is set
- * @retval None
- */
-void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
- assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
- MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
-}
-
-
-/**
- * @brief Enable the Debug Module during Domain1 SLEEP mode
- * @retval None
- */
-void HAL_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
-}
-
-/**
- * @brief Disable the Debug Module during Domain1 SLEEP mode
- * @retval None
- */
-void HAL_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
-}
-
-/**
- * @brief Enable the Debug Module during Domain1 STOP mode
- * @retval None
- */
-void HAL_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
-}
-
-/**
- * @brief Disable the Debug Module during Domain1 STOP mode
- * @retval None
- */
-void HAL_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
-}
-
-/**
- * @brief Enable the Debug Module during Domain1 STANDBY mode
- * @retval None
- */
-void HAL_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
-}
-
-/**
- * @brief Disable the Debug Module during Domain1 STANDBY mode
- * @retval None
- */
-void HAL_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
-}
-
-
-
-/**
- * @brief Enable the Debug Module during Domain3 STOP mode
- * @retval None
- */
-void HAL_EnableDomain3DBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
-}
-
-/**
- * @brief Disable the Debug Module during Domain3 STOP mode
- * @retval None
- */
-void HAL_DisableDomain3DBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
-}
-
-/**
- * @brief Enable the Debug Module during Domain3 STANDBY mode
- * @retval None
- */
-void HAL_EnableDomain3DBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
-}
-
-/**
- * @brief Disable the Debug Module during Domain3 STANDBY mode
- * @retval None
- */
-void HAL_DisableDomain3DBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
-}
-
-/**
- * @brief Set the FMC Memory Mapping Swapping config.
- * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
- FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
- * @retval HAL state
- */
-void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
-{
- /* Check the parameter */
- assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
- MODIFY_REG(FMC_Bank1->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
-}
-
-/**
- * @brief Get FMC Bank mapping mode.
- * @retval The FMC Bank mapping mode. This parameter can be
- FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
-*/
-uint32_t HAL_GetFMCMemorySwappingConfig(void)
-{
- return READ_BIT(FMC_Bank1->BTCR[0], FMC_BCR1_BMAP);
-}
-
-/**
- * @brief Configure the EXTI input event line edge
- * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
- * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
- * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
- * (EXTI_LINE0....EXTI_LINE88)excluding :line45, line81,line83 which are reserved
- * @param EXTI_Edge: Specifies EXTI line Edge used.
- * This parameter can be one of the following values :
- * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
- * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
- * @retval None
- */
-void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
-{
- /* Check the parameter */
- assert_param(IS_EXTI_CONFIG_LINE(EXTI_Line));
- assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
-
- /* Clear Rising Falling edge configuration */
- CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
-
- if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
- {
- SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
- if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
- {
- SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
- * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
- * @retval None
- */
-void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_CONFIG_LINE(EXTI_Line));
-
- SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
-}
-
-
-/**
- * @brief Clears the EXTI's line pending flags for Domain D1
- * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
- * (EXTI_LINE0....EXTI_LINE88)excluding :line45, line81,line83 which are reserved
- * @retval None
- */
-void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_D1_LINE(EXTI_Line));
- SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
-
-}
-
-/**
- * @brief Configure the EXTI input event line for Domain D1
- * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
- * (EXTI_LINE0....EXTI_LINE88)excluding :line45, line81,line83 which are reserved
- * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
- * This parameter can be one or a combination of the following values :
- * @arg EXTI_MODE_IT : Interrupt Mode selected
- * @arg EXTI_MODE_EVT : Event Mode selected
- * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
-
- * @retval None
- */
-void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
-{
- /* Check the parameter */
- assert_param(IS_EXTI_D1_LINE(EXTI_Line));
- assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
-
- if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
- {
- if( EXTI_LineCmd == DISABLE)
- {
- /* Clear EXTI line configuration */
- CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10)),(uint32_t)(1 << (EXTI_Line & 0x1F)) );
- }
- else
- {
- SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
- }
- if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
- {
- if( EXTI_LineCmd == DISABLE)
- {
- /* Clear EXTI line configuration */
- CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
- else
- {
- SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
- }
-
-}
-
-
-/**
- * @brief Configure the EXTI input event line for Domain D3
- * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
- * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
- * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53),EXTI_LINE88
- * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
- * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event.
- * This parameter can be one of the following values :
- * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
- * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
- * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
- * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
- * @retval None
- */
-void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc )
-{
-
- /* Check the parameter */
- assert_param(IS_EXTI_D3_LINE(EXTI_Line));
- assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
-
- if( EXTI_LineCmd == DISABLE)
- {
- /* Clear EXTI line configuration */
- CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20)),(uint32_t)(1 << (EXTI_Line & 0x1F)) );
- }
- else
- {
- SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20)), (uint32_t)(1 << (EXTI_Line & 0x1F)));
- }
-
-
- if ( (EXTI_Line>>4)%2 ==0)
- {
- MODIFY_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20)), \
- (uint32_t)(3 << ((EXTI_Line*2) & 0x1F)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2) & 0x1F))) ;
- }
-
- else
- {
- MODIFY_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20)), \
- (uint32_t)(3 << ((EXTI_Line*2) & 0x1F)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2) & 0x1F))) ;
- }
-
-}
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c
deleted file mode 100644
index 92babe6..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c
+++ /dev/null
@@ -1,3258 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_adc.c
- * @author MCD Application conversion
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Initialization and deinitialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of regular conversions of regular
- * using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
- * Other functions (extended functions) are available in file
- * "stm32h7xx_hal_adc_ex.c".
- @verbatim
- ==============================================================================
- ##### ADC specific features #####
- ==============================================================================
- [..]
- (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
-
- (+) Interrupt generation at the end of regular conversion and in case of
- analog watchdog or overrun events.
-
- (+) Single and continuous conversion modes.
-
- (+) Scan mode for conversion of several channels sequentially.
-
- (+) Data alignment with in-built data coherency.
-
- (+) Programmable sampling time (channel wise)
-
- (+) External trigger (timer or EXTI) with configurable polarity
-
- (+) DMA request generation for transfer of conversions data of regular group.
-
- (+) Configurable delay between conversions in Dual interleaved mode.
-
- (+) ADC channels selectable single/differential input.
-
- (+) ADC offset on regular groups.
-
- (+) ADC calibration
-
- (+) ADC conversion of regular group.
-
- (+) ADC supply requirements: 1.62 V to 3.6 V.
-
- (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
- Vdda or to an external voltage reference).
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- *** Configuration of top level parameters related to ADC ***
- ============================================================
- [..]
-
- (#) Enable the ADC interface
- (++) As prerequisite, ADC clock must be configured at RCC top level.
-
- (++) Two clock settings are mandatory:
- (+++) ADC clock (core clock, also possibly conversion clock).
-
- (+++) ADC clock (conversions clock).
- Two possible clock sources: synchronous clock derived from AHB clock
- or asynchronous clock derived from system clock, the PLL2 or the PLL3 running up to 400MHz.
-
- (+++) Example:
- Into HAL_ADC_MspInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
-
- RCC_ADCCLKSOURCE_PLL2 enable: (optional: if asynchronous clock selected)
- (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-
- (++) ADC clock source and clock prescaler are configured at ADC level with
- parameter "ClockPrescaler" using function HAL_ADC_Init().
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Configure these ADC pins in analog mode
- using function HAL_GPIO_Init()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Configure the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding ADC interruption vector
- ADCx_IRQHandler().
-
- (#) Optionally, in case of usage of DMA:
- (++) Configure the DMA (DMA channel, mode normal or circular, ...)
- using function HAL_DMA_Init().
- (++) Configure the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding DMA interruption vector
- DMAx_Channelx_IRQHandler().
-
- *** Configuration of ADC, group regular, channels parameters ***
- ================================================================
- [..]
-
-
- (#) Configure the ADC parameters (resolution, data alignment, ...)
- and regular group parameters (conversion trigger, sequencer, ...)
- using function HAL_ADC_Init().
-
- (#) Configure the channels for regular group parameters (channel number,
- channel rank into sequencer, ..., into regular group)
- using function HAL_ADC_ConfigChannel().
-
- (#) Optionally, configure the analog watchdog parameters (channels
- monitored, thresholds, ...)
- using function HAL_ADC_AnalogWDGConfig().
-
- *** Execution of ADC conversions ***
- ====================================
- [..]
-
-
- (#) Optionally, perform an automatic ADC calibration to improve the
- conversion accuracy
- using function HAL_ADCEx_Calibration_Start().
-
- (#) ADC driver can be used among three modes: polling, interruption,
- transfer by DMA.
-
- (++) ADC conversion by polling:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start()
- (+++) Wait for ADC conversion completion
- using function HAL_ADC_PollForConversion()
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop()
-
- (++) ADC conversion by interruption:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_IT()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback()
- (this function must be implemented in user program)
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_IT()
-
- (++) ADC conversion with transfer by DMA:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_DMA()
-
- [..]
-
-
- (@) Callback functions must be implemented in user program:
- (+@) HAL_ADC_ErrorCallback()
- (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
- (+@) HAL_ADC_ConvCpltCallback()
- (+@) HAL_ADC_ConvHalfCpltCallback
-
- *** Deinitialization of ADC ***
- ============================================================
- [..]
-
-
- (#) Disable the ADC interface
- (++) ADC clock can be hard reset and disabled at RCC top level.
- (++) Hard reset of ADC peripherals
- using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
- (++) ADC clock disable
- using the equivalent macro/functions as configuration step.
- (+++) Example:
- Into HAL_ADC_MspDeInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) __HAL_RCC_ADC_CLK_DISABLE(); (if not used anymore)
- RCC_ADCCLKSOURCE_CLKP restore: (optional)
- (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-
- (#) ADC pins configuration
- (++) Disable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Disable the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
- (#) Optionally, in case of usage of DMA:
- (++) Deinitialize the DMA
- using function HAL_DMA_Init().
- (++) Disable the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADC ADC
- * @brief ADC HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
-#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
- ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
- ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
- when no regular conversion is on-going */
-
-#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
- (neither regular nor injected) is on-going */
-
-#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
- ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
- ADC_CFGR2_ROVSM))
-
-#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
- ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
- conversion (neither regular nor injected) is on-going */
-
-#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
- (neither regular nor injected) is on-going */
-
-/* Delay to wait before setting ADEN once ADCAL has been reset
- must be at least 4 ADC clock cycles.
- Assuming lowest ADC clock (350 KHz according to DS), this
- 4 ADC clock cycles duration is equal to
- 4 / 350,000 = 0.011 ms.
- ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
- the 4 ADC clock cycles have elapsed while waiting for ADRDY
- to become 1 */
- #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */
- #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */
-
-/* Timeout to wait for current conversion on going to be completed. */
-/* Timeout fixed to worst case, for 1 channel. */
-/* - maximum sampling time (830.5 adc_clk) */
-/* - ADC resolution (Tsar 16 bits= 16.5 adc_clk) */
-/* - ADC clock with prescaler 256 */
-/* 823 * 256 = 210688 clock cycles max */
-/* Unit: cycles of CPU clock. */
-#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
-
-
-
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and deinitialization functions
- * @brief ADC Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and deinitialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC.
- (+) Deinitialize the ADC.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * depending on possible clock sources: PLL2/PLL3 clocks or AHB clock.
- * @note Possibility to update parameters on the fly:
- * this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned by ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @note Parameters related to common ADC registers (ADC clock mode) are set
- * only if all ADCs are disabled.
- * If this is not the case, these common parameters setting are
- * bypassed without error reporting: it can be the intended behaviour in
- * case of update of a parameter of ADC_InitTypeDef on the fly,
- * without disabling the other ADCs.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmpCFGR = 0;
- __IO uint32_t wait_loop_index = 0;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
- assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
- assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
- assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
- assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.BoostMode));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-
- if (hadc->Init.DiscontinuousConvMode == ENABLE)
- {
- assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
- }
- }
-
-
- /* DISCEN and CONT bits can not be set at the same time */
- assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
-
-
- /* Actions performed only if ADC is coming from state reset: */
- /* - Initialization of ADC MSP */
- if (hadc->State == HAL_ADC_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Initialize Lock */
- hadc->Lock = HAL_UNLOCKED;
- }
-
-
- /* - Exit from deep-power-down mode and ADC voltage regulator enable */
- /* Exit deep power down mode if still in that state */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
- {
- /* Exit deep power down mode */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-
- /* System was in deep power down mode, calibration must
- be relaunched or a previously saved calibration factor
- re-applied once the ADC voltage regulator is enabled */
- }
-
-
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
- {
- /* Enable ADC internal voltage regulator */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
- /* Delay for ADC stabilization time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles. */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
- while(wait_loop_index != 0)
- {
- wait_loop_index--;
- }
- }
-
-
- /* Verification that ADC voltage regulator is correctly enabled, whether */
- /* or not ADC is coming from state reset (if any potential problem of */
- /* clocking, voltage regulator would not be enabled). */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed and if there is no conversion on going on regular */
- /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
- /* called to update a parameter on the fly). */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
- {
-
- /* Initialize the ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Configuration of common ADC parameters */
-
- if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
- }
- else
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode clock configuration */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
- {
- /* Reset configuration of ADC common register CCR: */
- /* */
- /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
- /* according to adc->Init.ClockPrescaler. It selects the clock */
- /* source and sets the clock division factor. */
- /* */
- /* Some parameters of this register are not reset, since they are set */
- /* by other functions and must be kept in case of usage of this */
- /* function on the fly (update of a parameter of ADC_InitTypeDef */
- /* without needing to reconfigure all other ADC groups/channels */
- /* parameters): */
- /* - when multimode feature is available, multimode-related */
- /* parameters:DELAY,DUAL(set by API */
- /* HAL_ADCEx_MultiModeConfigChannel()) */
- /* - internal measurement paths: Vbat, temperature sensor, Vref */
- /* (set into HAL_ADC_ConfigChannel() or */
- /* HAL_ADCEx_InjectedConfigChannel() ) */
-
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
- }
-
-
- /* Configuration of ADC: */
- /* - resolution Init.Resolution */
- /* - external trigger to start conversion Init.ExternalTrigConv */
- /* - external trigger polarity Init.ExternalTrigConvEdge */
- /* - continuous conversion mode Init.ContinuousConvMode */
- /* - overrun Init.Overrun */
- /* - discontinuous mode Init.DiscontinuousConvMode */
- /* - discontinuous mode channel count Init.NbrOfDiscConversion */
- tmpCFGR = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
- hadc->Init.Overrun |
- hadc->Init.Resolution |
- ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) );
-
- if (hadc->Init.DiscontinuousConvMode == ENABLE)
- {
- tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
- }
-
- /* Enable external trigger if trigger selection is different of software */
- /* start. */
- /* - external trigger to start conversion Init.ExternalTrigConv */
- /* - external trigger polarity Init.ExternalTrigConvEdge */
- /* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
- /* equivalent to software start. */
- if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
- && (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
- {
- tmpCFGR |= ( hadc->Init.ExternalTrigConv | hadc->Init.ExternalTrigConvEdge);
- }
-
- /* Update Configuration Register CFGR */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Conversion data management Init.ConversionDataManagement */
- /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
- /* - Oversampling parameters Init.Oversampling */
- /* - Boost Mode BoostMode */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- tmpCFGR = ( ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
- ADC_CFGR_DMACONTREQ(hadc->Init.ConversionDataManagement) );
-
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
-
-
- if (hadc->Init.OversamplingMode == ENABLE)
- {
- assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
- assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
- assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
- assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
-
- if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
- || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
- {
- /* Multi trigger is not applicable to software-triggered conversions */
- assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
- }
-
-
- /* Configuration of Oversampler: */
- /* - Oversampling Ratio */
- /* - Right bit shift */
- /* - Leftt bit shift */
- /* - Triggered mode */
- /* - Oversampling mode (continued/resumed) */
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
- ADC_CFGR2_ROVSE |
- (hadc->Init.Oversampling.Ratio << 16) |
- hadc->Init.Oversampling.RightBitShift |
- hadc->Init.Oversampling.TriggeredMode |
- hadc->Init.Oversampling.OversamplingStopReset);
- }
- else
- {
- /* Disable Regular OverSampling */
- CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
- }
-
- /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
-
- /* Configure the BOOST Mode */
- if(hadc->Init.BoostMode == ENABLE)
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST);
- }
-
- } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-
- /* Configuration of regular group sequencer: */
- /* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
- /* Parameter "NbrOfConversion" is discarded. */
- /* Note: Scan mode is not present by hardware on this device, but */
- /* emulated by software for alignment over all STM32 devices. */
- /* - if scan mode is enabled, regular channels sequence length is set to */
- /* parameter "NbrOfConversion" */
-
- if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
- {
- /* Set number of ranks in regular group sequencer */
- MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
- }
- else
- {
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
- }
-
-
- /* Initialize the ADC state */
- /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- } /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */
-
-
- /* Return function status */
- return tmp_hal_status;
-
-}
-
-/**
- * @brief Deinitialize the ADC peripheral registers to their default reset
- * values, with deinitialization of the ADC MSP.
- * @note Keep in mind that all ADCs use the same clock: disabling
- * the clock will reset all ADCs.
- * @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
- * reducing the leakage currents and is particularly interesting before
- * entering STOP 1 or STOP 2 modes.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* No check on ADC_ConversionStop() return status, if the conversion
- stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
- ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- /* Flush register JSQR: reset the queue sequencer when injected */
- /* queue sequencer is enabled and ADC disabled. */
- /* The software and hardware triggers of the injected sequence are both */
- /* internally disabled just after the completion of the last valid */
- /* injected sequence. */
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
-
- /* Disable the ADC peripheral */
- /* No check on ADC_Disable() return status, if the ADC disabling process
- failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
- ADC_Disable(hadc);
-
-
- /* ========== Reset ADC registers ========== */
- /* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_JQOVF | ADC_IT_OVR |
- ADC_IT_JEOS | ADC_IT_JEOC |
- ADC_IT_EOS | ADC_IT_EOC |
- ADC_IT_EOSMP | ADC_IT_RDY ) );
-
- /* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_JQOVF | ADC_FLAG_OVR |
- ADC_FLAG_JEOS | ADC_FLAG_JEOC |
- ADC_FLAG_EOS | ADC_FLAG_EOC |
- ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
-
- /* Reset register CR */
- /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
- ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
- no direct reset applicable.
- Update CR register to reset value where doable by software */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
- SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-
- /* Reset register CFGR */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
- ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
- ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
- ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
- ADC_CFGR_RES | ADC_CFGR_DMNGT);
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- /* Reset register CFGR2 */
- CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
- ADC_CFGR2_OSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE );
-
- /* Reset register SMPR1 */
- CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
- ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
- ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |
- ADC_SMPR1_SMP0 );
-
- /* Reset register SMPR2 */
- CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
- ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
- ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
-
- /* Reset register LTR1 and HTR1 */
- CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
- CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
-
- /* Reset register LTR2 and HTR2*/
- CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
- CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
-
- /* Reset register LTR3 and HTR3 */
- CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR3_LT3);
- CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR3_HT3);
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
- ADC_SQR1_SQ1 | ADC_SQR1_L);
-
- /* Reset register SQR2 */
- CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
- ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
-
- /* Reset register SQR3 */
- CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
- ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
-
- /* Reset register SQR4 */
- CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-
- /* Register JSQR was reset when the ADC was disabled */
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register OFR1 */
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
- /* Reset register OFR2 */
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
- /* Reset register OFR3 */
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
- /* Reset register OFR4 */
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register AWD2CR */
- CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
-
- /* Reset register AWD3CR */
- CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
-
- /* Reset register DIFSEL */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
-
- /* Reset register CALFACT */
- CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
-
- /* ========== Reset common ADC registers ========== */
-
- /* Software is allowed to change common parameters only when all the other
- ADCs are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
- {
- /* Reset configuration of ADC common register CCR:
- - clock mode: CKMODE, PRESCEN
- - multimode related parameters(when this feature is available): DELAY, DUAL
- (set into HAL_ADCEx_MultiModeConfigChannel() )
- - internal measurement paths: Vbat, temperature sensor, Vref (set into
- HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
- */
- if((hadc->Instance == ADC1)||(hadc->Instance == ADC2))
- {
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
- }
- else
- {
- tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
- }
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
- ADC_CCR_PRESC |
- ADC_CCR_VBATEN |
- ADC_CCR_TSEN |
- ADC_CCR_VREFEN |
- ADC_CCR_DAMDF |
- ADC_CCR_DELAY |
- ADC_CCR_DUAL );
-
- }
-
- /* DeInit the low level hardware.
-
- For example:
- __HAL_RCC_ADC_FORCE_RESET();
- __HAL_RCC_ADC_RELEASE_RESET();
- __HAL_RCC_ADC_CLK_DISABLE();
-
- Keep in mind that all ADCs use the same clock: disabling
- the clock will reset all ADCs.
-
- */
- HAL_ADC_MspDeInit(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Reset injected channel configuration parameters */
- hadc->InjectionConfig.ContextQueue = 0;
- hadc->InjectionConfig.ChannelCount = 0;
-
- /* Set ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
-
- /* Return function status */
- return HAL_OK;
-
-}
-
-/**
- * @brief Initialize the ADC MSP.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspInit must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitialize the ADC MSP.
- * @param hadc: ADC handle
- * @note All ADCs use the same clock: disabling the clock will reset all ADCs.
- * @retval None
- */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspDeInit must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
- * @brief ADC IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular group.
- (+) Stop conversion of regular group.
- (+) Poll for conversion complete on regular group.
- (+) Poll for conversion event.
- (+) Get result of regular channel conversion.
- (+) Start conversion of regular group and enable interruptions.
- (+) Stop conversion of regular group and disable interruptions.
- (+) Handle ADC interrupt request
- (+) Start conversion of regular group and enable DMA transfer.
- (+) Stop conversion of regular group and disable ADC DMA transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable ADC, starts conversion of regular group.
- * @note Interruptions enabled in this function: None.
- * @note Case of multimode enabled(when multimode feature is available):
- * if ADC is Slave, ADC is enabled but conversion is not started,
- * if ADC is master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_TypeDef *tmpADC_Master;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
- /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - by default if ADC is Master or Independent
- - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
- if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion starts at next */
- /* trigger event. */
- /* Case of multimode enabled(when multimode feature is available): */
- /* - if ADC is slave and dual regular conversions are enabled, ADC is */
- /* enabled only (conversion is not started), */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
- {
- /* Multimode feature is not available or ADC Instance is Independent or Master,
- or is not Slave ADC with dual regular conversions enabled.
- Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- /* Start ADC */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* if Master ADC JAUTO bit is set, update Slave State in setting
- HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-
- } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral.
- * @note ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on ADC groups regular and injected */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-
-/**
- * @brief Wait for regular group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
- * @note Depending on hadc->Init.EOCSelection, EOS or EOC is
- * checked and cleared depending on AUTDLY bit status.
- * @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
- * DMA-managed conversions configuration: indeed, EOC is immediately
- * reset by the DMA reading the DR register when the converted data is
- * available. Therefore, EOC is set for a too short period to be
- * reliably polled.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t tmp_Flag_EOC = 0x00;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_cfgr = 0x00;
- uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
- tmp_eos_raised will be corrected
- accordingly during API execution */
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* If end of conversion selected to end of sequence conversions */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- tmp_Flag_EOC = ADC_FLAG_EOS;
- }
- /* If end of conversion selected to end of unitary conversion */
- else /* ADC_EOC_SINGLE_CONV */
- {
- /* Check that the ADC is not in a DMA-based configuration. Otherwise,
- returns an error. */
-
- /* Check whether dual regular conversions are disabled or unavailable. */
- if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
- {
- /* Check DMNGT bit in handle ADC CFGR register */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != RESET)
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
- }
- else
- {
- /* Else need to check Common register CCR DAMDF bit field. */
- /* Set pointer to the common control register */
-
- /* Pointer to the common control register */
- /* Dual ADC mode, could be only ADC1 or ADC2 */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
-
- if ((READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) == ADC_DUALMODEDATAFORMAT_32_10_BITS)
- || (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) == ADC_DUALMODEDATAFORMAT_8_BITS))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
- }
-
- /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
- tmp_Flag_EOC = ADC_FLAG_EOC;
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait until End of Conversion or Sequence flag is raised */
- while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Next, to clear the polled flag as well as to update the handle State,
- EOS is checked and the relevant configuration register is retrieved. */
- /* 1. Check whether or not EOS is set */
- if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
- {
- tmp_eos_raised = 0;
- }
- /* 2. Check whether or not hadc is the handle of a Slave ADC with dual
- regular conversions enabled. */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
- {
- /* Retrieve handle ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* Retrieve Master ADC CFGR register */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-
- /* Clear polled flag */
- if (tmp_Flag_EOC == ADC_FLAG_EOS)
- {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
- }
- else
- {
-
- /* Clear end of conversion EOC flag of regular group if low power feature */
- /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
- /* until data register is read using function HAL_ADC_GetValue(). */
- /* For regular groups, no new conversion will start before EOC is cleared.*/
- /* Note that 1. reading DR clears EOC. */
- /* 2. in multimode with dual regular conversions enabled (when */
- /* multimode feature is available), Master AUTDLY bit is */
- /* checked. */
- if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
- {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
- }
- }
-
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- /* If 1. EOS is set
- 2. conversions are software-triggered
- 3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
- Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
- 4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
- can be set */
- if ((tmp_eos_raised)
- && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Poll for ADC event.
- * @param hadc: ADC handle
- * @param EventType: the ADC event type.
- * This parameter can be one of the following values:
- * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
- * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
- * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_OVR_EVENT ADC Overrun event
- * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
- * @param Timeout: Timeout value in millisecond.
- * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
- * Indeed, the latter is reset only if hadc->Init.Overrun field is set
- * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
- * by a new converted data as soon as OVR is cleared.
- * To reset OVR flag once the preserved data is retrieved, the user can resort
- * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Check selected event flag */
- while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
-
- switch(EventType)
- {
- /* End Of Sampling event */
- case ADC_EOSMP_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
-
- /* Clear the End Of Sampling flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
-
- break;
-
- /* Analog watchdog (level out of window) event */
- /* Note: In case of several analog watchdog enabled, if needed to know */
- /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
- /* flags HAL_ADC_STATE_AWD/2/3 function. */
- /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
- /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
- /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
- case ADC_AWD_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
-
- break;
-
- /* Check analog watchdog 2 flag */
- case ADC_AWD2_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
-
- break;
-
- /* Check analog watchdog 3 flag */
- case ADC_AWD3_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
-
- break;
-
- /* Injected context queue overflow event */
- case ADC_JQOVF_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to Injected context queue overflow */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear ADC Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-
- break;
-
- /* Overrun event */
- default: /* Case ADC_OVR_EVENT */
- /* If overrun is set to overwrite previous data, overrun event is not */
- /* considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and without */
- /* overrun ") */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to overrun */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- }
- else
- {
- /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
- otherwise, data register is potentially overwritten by new converted data as soon
- as OVR is cleared. */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- }
- break;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
-* @brief Enable ADC, start conversion of regular group with interruption.
- * @note Interruptions enabled in this function according to initialization
- * setting : EOC (end of conversion), EOS (end of sequence),
- * OVR overrun.
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled(when multimode feature is available):
- * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
- * ADC Master.
- * For ADC Slave, ADC is enabled only (conversion is not started).
- * For ADC Master, ADC is enabled and multimode conversion is started.
- * @note To guarantee a proper reset of all interruptions once all the needed
- * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
- * a correct stop of the IT-based conversions.
- * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
- * interruption. If required (e.g. in case of oversampling with trigger
- * mode), the user must
- * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
- * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP);
- * before calling HAL_ADC_Start_IT().
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_TypeDef *tmpADC_Master;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
- /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - by default if ADC is Master or Independent or if multimode feature is not available
- - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
- if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* By default, disable all interruptions before enabling the desired ones */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* Enable required interruptions */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
- break;
- }
-
- /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
- ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
- behavior and no CPU time is lost for a non-processed interruption */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
- }
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion starts at next */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* - if ADC is slave and dual regular conversions are enabled, ADC is */
- /* enabled only (conversion is not started), */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) )
- {
- /* Multimode feature is not available or ADC Instance is Independent or Master,
- or is not Slave ADC with dual regular conversions enabled.
- Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-
- /* Enable as well injected interruptions in case
- HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
- allows to start regular and injected conversions when JAUTO is
- set with a single call to HAL_ADC_Start_IT() */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
- } /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- /* Start ADC */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
- }
- else
- {
- /* hadc is the handle of a Slave ADC with dual regular conversions
- enabled. Therefore, ADC_CR_ADSTART is NOT set */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* if Master ADC JAUTO bit is set, Slave injected interruptions
- are enabled nevertheless (for same reason as above) */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
- and in resetting HAL_ADC_STATE_INJ_EOC bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- /* Next, set Slave injected interruptions */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
- } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */
- } /* if (tmp_hal_status == HAL_OK) */
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable interrution of
- * end-of-conversion, disable ADC peripheral.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on ADC groups regular and injected */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for regular group */
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-/**
- * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
- * @note Interruptions enabled in this function:
- * overrun (if applicable), DMA half transfer, DMA transfer complete.
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
- * is designed for single-ADC mode only. For multimode, the dedicated
- * HAL_ADCEx_MultiModeStart_DMA() function must be used.
- * @param hadc: ADC handle
- * @param pData: Destination Buffer address.
- * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Ensure that dual regular conversions are not enabled or unavailable. */
- /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
- if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
- {
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to regular conversions only */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
- /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State,
- (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
- HAL_ADC_STATE_REG_BUSY);
-
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - by default if ADC is Master or Independent or if multimode feature is not available
- - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
- if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
- /* ADC start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* With DMA, overrun event is always considered as an error even if
- hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
- ADC_IT_OVR is enabled. */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- } /* if (tmp_hal_status == HAL_OK) */
- }
- else
- {
- tmp_hal_status = HAL_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
-
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
- * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential ADC group regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMNGT is kept) */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
- /* memory a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Disable(hadc);
- }
- else
- {
- ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY),
- HAL_ADC_STATE_READY);
- }
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading register DR automatically clears ADC flag EOC
- * (ADC group regular end of unitary conversion).
- * @note This function does not clear ADC flag EOS
- * (ADC group regular end of sequence conversion).
- * Occurrence of flag EOS rising:
- * - If sequencer is composed of 1 rank, flag EOS is equivalent
- * to flag EOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag EOC only is raised, at the end of the scan sequence
- * both flags EOC and EOS are raised.
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADC_PollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc: ADC handle
- * @retval ADC group regular conversion data
- */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: EOC flag is not cleared here by software because automatically */
- /* cleared by hardware when reading register DR. */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-
-
-/**
- * @brief Handle ADC interrupt request.
- * @param hadc: ADC handle
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_isr = hadc->Instance->ISR;
- uint32_t tmp_ier = hadc->Instance->IER;
- uint32_t tmp_cfgr = 0x0;
- uint32_t tmp_cfgr_jqm = 0x0;
-
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-
-
- /* ====== Check End of Sampling flag for regular group ===== */
- if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
- {
- /* Update state machine on end of sampling status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
- }
-
- /* End Of Sampling callback */
- HAL_ADCEx_EndOfSamplingCallback(hadc);
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
- }
-
- /* ====== Check End of Conversion or Sequence flags for regular group ===== */
- if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
- (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- }
-
- /* Disable interruption if no further conversion upcoming by regular */
- /* external trigger or by continuous mode, */
- /* and if scan sequence if completed. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
- {
- /* check CONT bit directly in handle ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* else need to check Master ADC CONT bit */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-
- /* Carry on if continuous mode is disabled */
- if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
- {
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
- {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
- /* ADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Disable ADC end of sequence conversion interrupt */
- /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
- /* in HAL_Start_IT(), it isn't disabled here because it can be used */
- /* by overrun IRQ process below. */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
- } /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */
-
- /* Conversion complete callback */
- /* Note: HAL_ADC_ConvCpltCallback can resort to
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
- interruption has been triggered by end of conversion or end of
- sequence. */
- HAL_ADC_ConvCpltCallback(hadc);
-
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
- }
-
-
- /* ========== Check End of Conversion flag for injected group ========== */
- if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
- (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
- }
-
-
- /* Check whether interruptions can be disabled only if
- - injected conversions are software-triggered when injected queue management is disabled
- OR
- - auto-injection is enabled, continuous mode is disabled (CONT = 0)
- and regular conversions are software-triggered */
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
- {
-
- /* First, retrieve proper registers to check */
- /* 1a. Are injected conversions that of a dual Slave ? */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
- {
- /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
- check JQM bit directly in ADC CFGR register */
- tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
- need to check JQM bit of Master ADC CFGR register */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
- }
- /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
- {
- /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
- check JAUTO and CONT bits directly in ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
- check JAUTO and CONT bits of Master ADC CFGR register */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-
- /* Secondly, check whether JEOC and JEOS interruptions can be disabled */
- if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
- && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc)))) )
- {
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Clear HAL_ADC_STATE_INJ_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
-
- /* Injected Conversion complete callback */
- /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
- interruption has been triggered by end of conversion or end of
- sequence. */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
-
- /* Clear injected group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
- }
-
-
- /* ========== Check Analog watchdog flag =================================================== */
-
- /* ========== Check Analog watchdog 1 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Level out of window 1 callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
- /* Clear ADC Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
- }
-
- /* ========== Check Analog watchdog 2 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Level out of window 2 callback */
- HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
- /* Clear ADC Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
- }
-
- /* ========== Check Analog watchdog 3 flag ========== */
- if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Level out of window 3 callback */
- HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
- /* Clear ADC Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
- }
-
-
- /* ========== Check Overrun flag ========== */
- if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
- {
- /* If overrun is set to overwrite previous data (default setting), */
- /* overrun event is not considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and without */
- /* overrun ") */
- /* Exception for usage with DMA overrun event always considered as an */
- /* error. */
-
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- overrun_error = 1;
- }
- else
- {
- /* Pointer to the common control register */
- if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
- }
- else
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
- }
- /* check DMA configuration, depending on MultiMode set or not */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)
- {
- if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0))
- {
- overrun_error = 1;
- }
- }
- else
- {
- /* MultiMode is enabled, Common Control Register DAMDF bits must be checked */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF) != RESET)
- {
- overrun_error = 1;
- }
- }
- }
-
- if (overrun_error == 1)
- {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to overrun */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
- }
-
- /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
- old data is preserved until OVR is reset */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-
- }
-
- /* ========== Check Injected context queue overflow flag ========== */
- if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
- {
- /* Change ADC state to overrun state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to Injected context queue overflow */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear the Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-
- /* Error callback */
- HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
- }
-
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Conversion DMA half-transfer callback in non-blocking mode
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 1 callback in non-blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief ADC error callback in non-blocking mode
- * (ADC conversion with interruption or transfer by DMA).
- * @note In case of error due to overrun when using ADC with DMA transfer
- * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
- * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
- * - If needed, restart a new ADC conversion using function
- * "HAL_ADC_Start_DMA()"
- * (this function is also clearing overrun flag)
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ErrorCallback must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on regular group
- (+) Configure the analog watchdog
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Configure a channel to be assigned to ADC group regular.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into ADC group regular,
- * following calls to this function can be used to reconfigure
- * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
- * without resetting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * Refer to comments of structure "ADC_ChannelConfTypeDef".
- * @param hadc: ADC handle
- * @param sConfig: Structure of ADC channel assigned to ADC group regular.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmpOffsetShifted;
- __IO uint32_t wait_loop_index = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
-
- /* Check offset range according to oversampling setting */
- if (hadc->Init.OversamplingMode == ENABLE)
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
- }
- else
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
- }
-
- /* Verification of channel number */
- if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- assert_param(IS_ADC_CHANNEL(sConfig->Channel));
- }
- else
- {
- if (hadc->Instance == ADC3)
- {
- assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
- }
- else if (hadc->Instance == ADC1)
- {
- assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
- }
- else
- {
- assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
- }
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel number */
- /* - Channel rank */
- /* - Preselection of ADC inputs */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* ADC channels preselction */
- hadc->Instance->PCSEL |= (1U << sConfig->Channel);
-
- /* Regular sequence configuration */
- /* Clear the old SQx bits then set the new ones for the selected rank */
- /* For Rank 1 to 4 */
- if (sConfig->Rank < 5)
- {
- MODIFY_REG(hadc->Instance->SQR1,
- ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
- ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
- }
- /* For Rank 5 to 9 */
- else if (sConfig->Rank < 10)
- {
- MODIFY_REG(hadc->Instance->SQR2,
- ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
- ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
- }
- /* For Rank 10 to 14 */
- else if (sConfig->Rank < 15)
- {
- MODIFY_REG(hadc->Instance->SQR3,
- ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
- ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
- }
- /* For Rank 15 to 16 */
- else
- {
- MODIFY_REG(hadc->Instance->SQR4,
- ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
- ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel sampling time */
- /* - Channel offset */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
-
- /* Channel sampling time configuration */
- /* Clear the old sample time then set the new one for the selected channel */
- /* For channels 10 to 18 */
- if (sConfig->Channel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel));
- }
- else /* For channels 0 to 9 */
- {
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel),
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel));
- }
-
-
- /* Configure the offset: offset enable/disable, channel, offset value, Signed saturation feature */
-
- /* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
-
- switch (sConfig->OffsetNumber)
- {
- /* Configure offset register i when applicable: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- /* - Set Right shift after offset application */
- case ADC_OFFSET_1:
- MODIFY_REG(hadc->Instance->OFR1,
- ADC_OFR_FIELDS,
- ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT1, sConfig->OffsetRightShift);
- /* Enable or disable the signed saturation bit */
- if(sConfig->OffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
- }
- break;
-
- case ADC_OFFSET_2:
- MODIFY_REG(hadc->Instance->OFR2,
- ADC_OFR_FIELDS,
- ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT2, (sConfig->OffsetRightShift)<<1);
- /* Enable or disable the signed saturation bit */
- if(sConfig->OffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
- }
- break;
-
- case ADC_OFFSET_3:
- MODIFY_REG(hadc->Instance->OFR3,
- ADC_OFR_FIELDS,
- ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT3, (sConfig->OffsetRightShift)<<2);
- /* Enable or disable the signed saturation bit */
- if(sConfig->OffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
- }
- break;
-
- case ADC_OFFSET_4:
- MODIFY_REG(hadc->Instance->OFR4,
- ADC_OFR_FIELDS,
- ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT4, (sConfig->OffsetRightShift)<<3);
- /* Enable or disable the signed saturation bit */
- if(sConfig->OffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
- }
- break;
-
- /* Case ADC_OFFSET_NONE */
- default :
- /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
- If this is the case, offset OFRx is disabled since
- sConfig->OffsetNumber = ADC_OFFSET_NONE. */
- if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
- }
- if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
- }
- if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
- }
- if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
- }
- break;
- } /* switch (sConfig->OffsetNumber) */
-
- } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Configuration of differential mode */
- if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- /* Disable differential mode (default mode: single-ended) */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
- }
- else
- {
- /* Enable differential mode */
- SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
-
- /* Sampling time configuration of channel ADC_IN+1 (negative input) */
- /* Clear the old sample time then set the new one for the selected */
- /* channel. */
- /* For channels 9 to 15 (ADC1, ADC2) or to 11 (ADC3), SMPR2 register
- must be configured */
- if (sConfig->Channel >= ADC_CHANNEL_9)
- {
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1),
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1));
- }
- else /* For channels 0 to 8, SMPR1 must be configured */
- {
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1),
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1));
- }
- }
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
- /* If internal channel selected, enable dedicated internal buffers and */
- /* paths. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_DeInit(). */
-
- /* Configuration of common ADC parameters */
- if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
- }
- else
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
- }
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
- ( (sConfig->Channel == ADC_CHANNEL_VBAT_DIV4) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
- ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
- )
- {
- /* Configuration of common ADC parameters (continuation) */
-
- /* Software is allowed to change common parameters only when all ADCs */
- /* of the common group are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
- {
- /* Enable Temperature sensor measurement path (channel 18) */
- /* Note: Temp. sensor internal channels available on ADC3 */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((hadc->Instance == ADC3)))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles. */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
- while(wait_loop_index != 0)
- {
- wait_loop_index--;
- }
- }
- /* If Channel 18 is selected, enable VBAT measurement path. */
- /* Note: VBAT internal internal channels available on ADC1 and ADC3 */
- else if ((sConfig->Channel == ADC_CHANNEL_VBAT_DIV4) && ((hadc->Instance == ADC3)))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
- }
- /* If Channel 19 is selected, enable VREFINT measurement path */
- /* Note: VBAT internal internal channels available on ADC1 only */
- else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && (hadc->Instance == ADC3))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
- }
- }
- /* If the requested internal measurement path has already been */
- /* enabled and other ADC of the common group are enabled, internal */
- /* measurement paths cannot be enabled. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- } /* if (ADC_IS_ENABLE(hadc) == RESET) */
-
- } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
-
- /* If a conversion is on going on regular group, no update on regular */
- /* channel could be done on neither of the channel configuration structure */
- /* parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-/**
- * @brief Configure the analog watchdog.
- * @note Possibility to update parameters on the fly:
- * This function initializes the selected analog watchdog, successive
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_AnalogWDGConfTypeDef".
- * @note Analog watchdog thresholds can be modified while ADC conversion
- * is on going.
- * In this case, some constraints must be taken into account:
- * the programmed threshold values are effective from the next
- * ADC EOC (end of unitary conversion).
- * Considering that registers write delay may happen due to
- * bus activity, this might cause an uncertainty on the
- * effective timing of the new programmed threshold values.
- * @param hadc: ADC handle
- * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- uint32_t tmpAWDHighThresholdShifted;
- uint32_t tmpAWDLowThresholdShifted;
-
- uint32_t tmpADCFlagAWD2orAWD3;
- uint32_t tmpADCITAWD2orAWD3;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
- assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
- assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-
- if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
- {
- assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
- }
-
-
- /* Verify if threshold is within the selected ADC resolution */
- /* Check threshold range according to oversampling setting */
- if (hadc->Init.OversamplingMode == ENABLE)
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold/(hadc->Init.Oversampling.Ratio+1U)));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold/(hadc->Init.Oversampling.Ratio+1U)));
- }
- else
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Analog watchdog channels */
- /* - Analog watchdog thresholds */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
-
- /* Analog watchdogs configuration */
- if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
- {
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog enable mode: regular and/or injected */
- /* groups, one or overall group of channels. */
- /* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
-
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
- AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
-
- /* Shift the offset with respect to the selected ADC resolution: */
- /* Thresholds have to be left-aligned on bit 15, the LSB (right bits) */
- /* are set to 0 */
- tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->LTR1, ADC_LTR2_LT2 , tmpAWDLowThresholdShifted);
- MODIFY_REG(hadc->Instance->HTR1, ADC_HTR2_HT2 , tmpAWDHighThresholdShifted);
-
- /* Clear the ADC Analog watchdog flag (in case left enabled by */
- /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
- /* or HAL_ADC_PollForEvent(). */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- /* Enable the ADC Analog watchdog interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
- }
- else
- {
- /* Disable the ADC Analog watchdog interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
- }
-
- /* Update state, clear previous result related to AWD1 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- }
- /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
- else
- {
- /* Shift the threshold with respect to the selected ADC resolution */
- /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
- tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
- {
- /* Set the Analog watchdog channel or group of channels. This also */
- /* enables the watchdog. */
- /* Note: Conditional register reset, because several channels can be */
- /* set by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
- {
- SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
- }
- else
- {
- CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
- }
-
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2, tmpAWDHighThresholdShifted);
- MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2, tmpAWDLowThresholdShifted);
-
-
- /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
- /* settings. */
- tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
- tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
-
- /* Update state, clear previous result related to AWD2 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
- }
- /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
- else
- {
- /* Set the Analog watchdog channel or group of channels. This also */
- /* enables the watchdog. */
- /* Note: Conditional register reset, because several channels can be */
- /* set by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
- {
- SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
- }
- else
- {
- CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
- }
-
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3, tmpAWDHighThresholdShifted);
- MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3, tmpAWDLowThresholdShifted);
- /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
- /* settings. */
- tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
- tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
-
- /* Update state, clear previous result related to AWD3 */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
- }
-
- /* Clear the ADC Analog watchdog flag (in case left enabled by */
- /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
- /* or HAL_ADC_PollForEvent(). */
- __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
- }
- else
- {
- __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
- }
- }
-
- }
- /* If a conversion is on going on regular or injected groups, no update */
- /* could be done on neither of the AWD configuration structure parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- * @brief ADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral state and errors functions #####
- ===============================================================================
- [..] This subsection provides functions to get in run-time the status of the
- peripheral.
- (+) Check the ADC state
- (+) Check the ADC error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the ADC handle state.
- * @note ADC state machine is managed by bitfields, ADC status must be
- * compared with states bits.
- * For example:
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
- * @param hadc: ADC handle
- * @retval ADC handle state (bitfield on 32 bits)
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Return ADC Handle state */
- return hadc->State;
-}
-
-
-/**
- * @brief Return the ADC error code.
- * @param hadc: ADC handle
- * @retval ADC error code (bitfield on 32 bits)
- */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- return hadc->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-
-/**
- * @brief Stop ADC conversion.
- * @param hadc: ADC handle
- * @param ConversionGroup: ADC group regular and/or injected.
- * This parameter can be one of the following values:
- * @arg ADC_REGULAR_GROUP ADC regular conversion type.
- * @arg ADC_INJECTED_GROUP ADC injected conversion type.
- * @arg ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
-{
- uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
- uint32_t tickstart = 0;
- uint32_t Conversion_Timeout_CPU_cycles = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
-
- /* Verification if ADC is not already stopped (on regular and injected */
- /* groups) to bypass this function if not needed. */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
- {
- /* Particular case of continuous auto-injection mode combined with */
- /* auto-delay mode. */
- /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
- /* injected group stop ADC_CR_JADSTP). */
- /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
- /* (see reference manual). */
- if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
- && (hadc->Init.ContinuousConvMode==ENABLE)
- && (hadc->Init.LowPowerAutoWait==ENABLE))
- {
- /* Use stop of regular group */
- ConversionGroup = ADC_REGULAR_GROUP;
-
- /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
- while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
- {
- if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- Conversion_Timeout_CPU_cycles ++;
- }
-
- /* Clear JEOS */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
- }
-
- /* Stop potential conversion on going on regular group */
- if (ConversionGroup != ADC_INJECTED_GROUP)
- {
- /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
- {
- /* Stop conversions on regular group */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
- }
- }
-
- /* Stop potential conversion on going on injected group */
- if (ConversionGroup != ADC_REGULAR_GROUP)
- {
- /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
- {
- /* Stop conversions on injected group */
- SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
- }
- }
-
- /* Selection of start and stop bits with respect to the regular or injected group */
- switch(ConversionGroup)
- {
- case ADC_REGULAR_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
- break;
- case ADC_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
- break;
- /* Case ADC_REGULAR_GROUP only*/
- default:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
- break;
- }
-
- /* Wait for conversion effectively stopped */
-
-
- tickstart = HAL_GetTick();
-
- while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
- {
- if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
-
- } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-
-
-/**
- * @brief Enable the selected ADC.
- * @note Prerequisite condition to use this function: ADC must be disabled
- * and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0;
-
- /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
- /* enabling phase not yet completed: flag ADC ready not yet set). */
- /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
- /* causes: ADC clock not running, ...). */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Check if conditions to enable the ADC are fulfilled */
- if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Enable the ADC peripheral */
- ADC_ENABLE(hadc);
-
-
- /* Wait for ADC effectively enabled */
- tickstart = HAL_GetTick();
-
- while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
- {
- /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
- has been cleared (after a calibration), ADEN bit is reset by the
- calibration logic.
- The workaround is to continue setting ADEN until ADRDY is becomes 1.
- Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
- 4 ADC clock cycle duration */
- ADC_ENABLE(hadc);
-
- if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable the selected ADC.
- * @note Prerequisite condition to use this function: ADC conversions must be
- * stopped.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0;
-
- /* Verification if ADC is not already disabled: */
- /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
- /* disabled. */
- if (ADC_IS_ENABLE(hadc) != RESET )
- {
- /* Check if conditions to disable the ADC are fulfilled */
- if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
- {
- /* Disable the ADC peripheral */
- ADC_DISABLE(hadc);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Wait for ADC effectively disabled */
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
- {
- if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-
-/**
- * @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
- {
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- /* Is it the end of the regular sequence ? */
- if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
- {
- /* Are conversions software-triggered ? */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Is CONT bit set ? */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
- {
- /* CONT bit is not set, no more conversions expected */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
- }
- else
- {
- /* DMA End of Transfer interrupt was triggered but conversions sequence
- is not over. If DMACFG is set to 0, conversions are stopped. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == RESET)
- {
- /* DMACFG bit is not set, conversions are stopped. */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
- }
- else /* DMA or internal error occured (or both) */
- {
- /* In case of internal error, */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* call Error Callback function */
- HAL_ADC_ErrorCallback(hadc);
- }
-
- }
-
-
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Half conversion callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Set ADC error code to DMA error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c
deleted file mode 100644
index c2a67ef..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c
+++ /dev/null
@@ -1,2537 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_adc_ex.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of injected
- * group, using 2 possible modes: polling, interruption.
- * ++ Calibration
- * +++ ADC automatic self-calibration
- * +++ Calibration factors get or set
- * ++ Multimode feature when available
- * + Control functions
- * ++ Channels configuration on injected group
- * + State functions
- * ++ Injected group queues management
- * Other functions (generic functions) are available in file
- * "stm32h7xx_hal_adc.c".
- *
- @verbatim
- ==============================================================================
- ##### ADC specific features #####
- ==============================================================================
- [..]
- (@) Sections "ADC peripheral features" and "How to use this driver" are
- available in file of generic functions "stm32h7xx_hal_adc.c".
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADCEx ADCEx
- * @brief ADC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
- * @{
- */
-#define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
- ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
- ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
- once the ADC is enabled */
-
-#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OSR |\
- ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated
- when no conversion is on-going (neither regular nor injected) */
-
-/* Fixed timeout value for ADC calibration. */
-/* Values defined to be higher than worst cases: low clock frequency, */
-/* maximum prescalers. */
-/* Ex of profile low frequency : f_ADC at 0.35 MHz (minimum value */
-/* according to Data sheet), calibration_time MAX = 112 / f_ADC */
-/* 112 / 350,000 = 0.32 ms */
-/* At maximum CPU speed (200 MHz), this means */
-/* 0.8 ms * 200 MHz = 64000 CPU cycles */
-#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /*!< ADC calibration time-out value */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
- * @{
- */
-
-
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
- (+) Perform the ADC self-calibration for single or differential ending.
- (+) Get calibration factors for single or differential ending.
- (+) Set calibration factors for single or differential ending.
-
- (+) Start conversion of injected group.
- (+) Stop conversion of injected group.
- (+) Poll for conversion complete on injected group.
- (+) Get result of injected channel conversion.
- (+) Start conversion of injected group and enable interruptions.
- (+) Stop conversion of injected group and disable interruptions.
-
- (+) When multimode feature is available, start multimode and enable DMA transfer.
- (+) Stop multimode and disable ADC DMA transfer.
- (+) Get result of multimode conversion.
-
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform an ADC automatic self-calibration
- * Calibration prerequisite: ADC must be disabled (execute this
- * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * @param hadc ADC handle
- * @param CalibrationMode: Selection of Calibration Mode
- * This parameter can be one of the following values:
- * @arg ADC_CALIB_OFFSET: ADC calibration in offset mode
- * @arg ADC_CALIB_OFFSET_LINEARITY: ADC calibration in Linear offset mode
- * @param SingleDiff: Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
- * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t WaitLoopIndex = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Calibration prerequisite: ADC must be disabled. */
-
- /* Disable the ADC (if not already disabled) */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Select calibration mode single ended or differential ended */
- MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
-
- /* Select the Linear calibration if enabled */
- MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALLIN, CalibrationMode);
-
- /* Start ADC calibration */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
-
-
- /* Wait for calibration completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
- {
- WaitLoopIndex++;
- if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Note: No need to update variable "tmp_hal_status" here: already set */
- /* to state "HAL_ERROR" by function disabling the ADC. */
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-/**
- * @brief Get the calibration factor from automatic conversion result.
- * @param hadc: ADC handle.
- * @param SingleDiff: Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
- * @retval HAL state
- */
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Return the selected ADC calibration value */
- if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
- {
- return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
- }
- else
- {
- return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
- }
-}
-
-/**
- * @brief Get the calibration factor from automatic conversion result
- * @param hadc: ADC handle
- * @param LinearCalib_Buffer: Linear calibration factor
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
-{
- uint32_t cnt = 0;
- uint32_t WaitLoopIndex = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
- ADC_Enable(hadc);
-
- for(cnt = 0; cnt < 6; cnt++)
- {
- /* Clear LINCALRDYWx */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt);
- /* Wait untill LINCALRDYWx is reset */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt))
- {
- WaitLoopIndex++;
- if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
- {
- return HAL_ERROR;
- }
- }
-
- /* Read the ADCx_CALFACT2[29:0] containing the LINCALWx*/
- *(LinearCalib_Buffer + cnt) = hadc->Instance->CALFACT2;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Set the calibration factor to overwrite automatic conversion result, ADC must be enabled and no conversion on going.
- * @param hadc: ADC handle.
- * @param SingleDiff: Selection of single-ended or differential input.
- * This parameter can be one of the following values:
- * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
- * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
- assert_param(IS_ADC_CALFACT(CalibrationFactor));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Verification of hardware constraints before modifying the calibration */
- /* factors register: ADC must be enabled, no conversion on going. */
- if ( (ADC_IS_ENABLE(hadc) != RESET) &&
- (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
- {
- /* Set the selected ADC calibration value */
- if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
- {
- MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
- }
- else
- {
- MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
- }
- }
- else
- {
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Update ADC state machine to error */
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-/**
- * @brief Set the linear calibration factor
- * @param hadc: ADC handle
- * @param LinearCalib_Buffer: Linear calibration factor
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer)
-{
- uint32_t cnt = 0;
- __IO uint32_t wait_loop_index = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* - Exit from deep-power-down mode and ADC voltage regulator enable */
- /* Exit deep power down mode if still in that state */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
- {
- /* Exit deep power down mode */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
-
- /* System was in deep power down mode, calibration must
- be relaunched or a previously saved calibration factor
- re-applied once the ADC voltage regulator is enabled */
- }
-
-
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
- {
- /* Enable ADC internal voltage regulator */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
- /* Delay for ADC stabilization time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles. */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
- while(wait_loop_index != 0)
- {
- wait_loop_index--;
- }
- }
-
-
- /* Verification that ADC voltage regulator is correctly enabled, whether */
- /* or not ADC is coming from state reset (if any potential problem of */
- /* clocking, voltage regulator would not be enabled). */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- for(cnt = 0; cnt < 6; cnt++)
- {
- /* Write the LINCALWx in ADCx_CALFACT2[29:0] */
- hadc->Instance->CALFACT2 = *(LinearCalib_Buffer + cnt);
-
- /* Set LINCALRDYWx */
- SET_BIT(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt);
-
- /* Wait untill LINCALRDYWx is set */
- while(HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_LINCALRDYW6 >> cnt))
- {
- wait_loop_index++;
- if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
- {
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Enable ADC, start conversion of injected group.
- * @note Interruptions enabled in this function: None.
- * @note Case of multimode enabled when multimode feature is available:
- * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
- * then for ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
- {
- return HAL_BUSY;
- }
- else
- {
-
- /* In case of software trigger detection enabled, JQDIS must be set
- (which can be done only if ADSTART and JADSTART are both cleared).
- If JQDIS is not set at that point, returns an error
- - since software trigger detection is disabled. User needs to
- resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
- the queue is empty */
- if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
- && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
-
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Check if a regular conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC error code field related to injected conversions only */
- CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
- }
- else
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
- /* Update ADC state */
- /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
-
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - by default if ADC is Master or Independent or if multimode feature is not available
- - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
- if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Enable conversion of injected group, if automatic injected conversion */
- /* is disabled. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (when multimode feature is available): */
- /* if ADC is slave, */
- /* - ADC is enabled only (conversion is not started). */
- /* - if multimode only concerns regular conversion, ADC is enabled */
- /* and conversion is started. */
- /* If ADC is master or independent, */
- /* - ADC is enabled and conversion is started. */
-
- /* Are injected conversions that of a dual Slave ? */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
- {
- /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
- set ADSTART only if JAUTO is cleared */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
- }
- }
- else
- {
- /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
- ADSTART is not set */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- } /* if (tmp_hal_status == HAL_OK) */
-
- /* Return function status */
- return tmp_hal_status;
- } /* if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
-}
-
-/**
- * @brief Stop conversion of injected channels and disable ADC peripheral if
- * no regular conversion is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note In case of multimode enabled (when multimode feature is available),
- * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @param hadc: ADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if injected conversions are effectively stopped */
- /* and if no conversion on regular group is on-going */
- if (tmp_hal_status == HAL_OK)
- {
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else
- {
- /* Clear HAL_ADC_STATE_INJ_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-
-/**
- * @brief Wait for injected group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
- * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
- * checked and cleared depending on AUTDLY bit status.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t tmp_Flag_End = 0x00;
- ADC_TypeDef *tmpADC_Master;
- uint32_t tmp_cfgr = 0x00;
- uint32_t tmp_cfgr_jqm_autdly = 0x00;
- uint32_t tmp_jeos_raised = 0x01; /* by default, assume that JEOS is set,
- tmp_jeos_raised will be corrected
- accordingly during API execution */
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* If end of sequence selected */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- tmp_Flag_End = ADC_FLAG_JEOS;
- }
- else /* end of conversion selected */
- {
- tmp_Flag_End = ADC_FLAG_JEOC;
- }
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait until End of Conversion or Sequence flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Next, to clear the polled flag as well as to update the handle State,
- JEOS is checked and the relevant configuration registers are retrieved.
- JQM, JAUTO and CONT bits will have to be read for the State update,
- AUTDLY for JEOS clearing. */
- /* 1. Check whether or not JEOS is set */
- if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
- {
- tmp_jeos_raised = 0;
- }
- /* 2. Check whether or not hadc is the handle of a Slave ADC with dual
- injected conversions enabled. */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
- {
- /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
- check JQM and AUTDLY bits directly in ADC CFGR register */
- tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
- need to check JQM and AUTDLY bits of Master ADC CFGR register */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
- }
- /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
- regular conversions enabled. */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
- {
- /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
- check JAUTO and CONT bits directly in ADC CFGR register */
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
- check JAUTO and CONT bits of Master ADC CFGR register */
- tmpADC_Master = ADC_MASTER_REGISTER(hadc);
- tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
- }
-
-
-
- /* Clear polled flag */
- if (tmp_Flag_End == ADC_FLAG_JEOS)
- {
- /* Clear end of sequence JEOS flag of injected group if low power feature */
- /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
- /* For injected groups, no new conversion will start before JEOS is */
- /* cleared. */
- /* Note that 1. reading ADCx_JDRy clears JEOC. */
- /* 2. in MultiMode with dual injected conversions enabled, */
- /* Master AUTDLY bit must be checked */
-
- if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
- {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
- }
- }
- else
- {
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
- }
-
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
- /* Are injected conversions over ? This is the case if JEOS is set AND
- - injected conversions are software-triggered when injected queue management is disabled
- OR
- - autoinjection is enabled, continuous mode is disabled,
- and regular conversions are software-triggered */
-
- if (tmp_jeos_raised)
- {
- if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))
- && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc))) ))
- {
- /* Clear HAL_ADC_STATE_INJ_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- }
-
-
-
- /* Return API HAL status */
- return HAL_OK;
-}
-
-
-
-/**
- * @brief Enable ADC, start conversion of injected group with interruption.
- * @note Interruptions enabled in this function according to initialization
- * setting : JEOC (end of conversion) or JEOS (end of sequence)
- * @note Case of multimode enabled (when multimode feature is enabled):
- * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
- * then for ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
- {
- return HAL_BUSY;
- }
- else
- {
-
- /* In case of software trigger detection enabled, JQDIS must be set
- (which can be done only if ADSTART and JADSTART are both cleared).
- If JQDIS is not set at that point, returns an error
- - since software trigger detection is disabled. User needs to
- resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
- the queue is empty */
- if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
- && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Check if a regular conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC error code field related to injected conversions only */
- CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
- }
- else
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
- }
- /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
-
- /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- - by default if ADC is Master or Independent
- - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
- if (ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Enable ADC Injected context queue overflow interrupt if this feature */
- /* is enabled. */
- if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
- {
- __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
- }
-
- /* Enable ADC end of conversion interrupt */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
- break;
- }
-
- /* Enable conversion of injected group, if automatic injected conversion */
- /* is disabled. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled: */
- /* if ADC is slave, */
- /* - ADC is enabled only (conversion is not started). */
- /* - if multimode only concerns regular conversion, ADC is enabled */
- /* and conversion is started. */
- /* If ADC is master or independent, */
- /* - ADC is enabled and conversion is started. */
-
- /* Are injected conversions that of a dual Slave ? */
- if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
- {
- /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
- set ADSTART only if JAUTO is cleared */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
- }
- }
- else
- {
- /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
- ADSTART is not set */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-}
-
-/**
- * @brief Stop conversion of injected channels, disable interruption of
- * end-of-conversion, disable ADC peripheral if no regular conversion
- * is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note Case of multimode enabled (when multimode feature is available):
- * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
- * then for ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if injected conversions are effectively stopped */
- /* and if no conversion on the other group (regular group) is intended to */
- /* continue. */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for injected channels */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
-
- if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else
- {
- /* Clear HAL_ADC_STATE_INJ_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-/**
- * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
- * @note Multimode must have been previously configured using
- * HAL_ADCEx_MultiModeConfigChannel() function.
- * Interruptions enabled in this function:
- * overrun, DMA half transfer, DMA transfer complete.
- * Each of these interruptions has its dedicated callback function.
- * @note State field of Slave ADC handle is not updated in this configuration:
- * user should not rely on it for information related to Slave regular
- * conversions.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @param pData: Destination Buffer address.
- * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_HandleTypeDef tmphadcSlave;
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
- {
- return HAL_BUSY;
- }
- else
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
-
- /* Enable the ADC peripherals: master and slave (in case if not already */
- /* enabled previously) */
- tmp_hal_status = ADC_Enable(hadc);
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Enable(&tmphadcSlave);
- }
-
- /* Start multimode conversion of ADCs pair */
- if (tmp_hal_status == HAL_OK)
- {
- /* Update Master State */
- /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
-
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
- }
-}
-
-/**
- * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
- * @note Multimode is kept enabled after this function. MultiMode DMA bits
- * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
- * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
- * resort to HAL_ADCEx_DisableMultiMode() API.
- * @note In case of DMA configured in circular mode, function
- * HAL_ADC_Stop_DMA() must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* 1. Stop potential multimode conversion on going, on regular and injected groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
- tickstart = HAL_GetTick();
-
- while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
- ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
- {
- if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop */
- /* while DMA transfer is on going) */
- /* Note: DMA channel of ADC slave should be stopped after this function */
- /* with HAL_ADC_Stop_DMA() API. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status == HAL_ERROR)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-
-
- /* 2. Disable the ADC peripherals: master and slave */
- /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
- /* memory a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- /* Check if ADC are effectively disabled */
- if ((ADC_Disable(hadc) == HAL_OK) &&
- (ADC_Disable(&tmphadcSlave) == HAL_OK) )
- {
- tmp_hal_status = HAL_OK;
- }
- }
- else
- {
- ADC_Disable(hadc);
- ADC_Disable(&tmphadcSlave);
- }
- /* Change ADC state (ADC master) */
- /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-/**
- * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
- * @param hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
- * @retval The converted data values.
- */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
-
- /* Return the multi mode conversion value */
- return tmpADC_Common->CDR;
-}
-
-
-/**
- * @brief Get ADC injected group conversion result.
- * @note Reading register JDRx automatically clears ADC flag JEOC
- * (ADC group injected end of unitary conversion).
- * @note This function does not clear ADC flag JEOS
- * (ADC group injected end of sequence conversion)
- * Occurrence of flag JEOS rising:
- * - If sequencer is composed of 1 rank, flag JEOS is equivalent
- * to flag JEOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag JEOC only is raised, at the end of the scan sequence
- * both flags JEOC and EOS are raised.
- * Flag JEOS must not be cleared by this function because
- * it would not be compliant with low power features
- * (feature low power auto-wait, not available on all STM32 families).
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc: ADC handle
- * @param InjectedRank: the converted ADC injected rank.
- * This parameter can be one of the following values:
- * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
- * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
- * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
- * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
- * @retval ADC group injected conversion data
- */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
- uint32_t tmp_jdr = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
-
- /* Get ADC converted value */
- switch(InjectedRank)
- {
- case ADC_INJECTED_RANK_4:
- tmp_jdr = hadc->Instance->JDR4;
- break;
- case ADC_INJECTED_RANK_3:
- tmp_jdr = hadc->Instance->JDR3;
- break;
- case ADC_INJECTED_RANK_2:
- tmp_jdr = hadc->Instance->JDR2;
- break;
- case ADC_INJECTED_RANK_1:
- default:
- tmp_jdr = hadc->Instance->JDR1;
- break;
- }
-
- /* Return ADC converted value */
- return tmp_jdr;
-}
-
-/**
- * @brief Injected conversion complete callback in non-blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
- */
-}
-
-
-/**
- * @brief Injected context queue overflow callback.
- * @note This callback is called if injected context queue is enabled
- (parameter "QueueInjectedContext" in injected channel configuration)
- and if a new injected context is set when queue is full (maximum 2
- contexts).
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 2 callback in non-blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 3 callback in non-blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
- */
-}
-
-
-/**
- * @brief End Of Sampling callback in non-blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral if no
- * conversion is on going on injected group.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if regular conversions are effectively stopped
- and if no injected conversions are on-going */
- if (tmp_hal_status == HAL_OK)
- {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on injected group is stopped, but ADC not disabled since */
- /* conversion on regular group is still running. */
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-/**
- * @brief Stop ADC conversion of ADC groups regular and injected,
- * disable interrution of end-of-conversion,
- * disable ADC peripheral if no conversion is on going
- * on injected group.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped
- and if no injected conversion is on-going */
- if (tmp_hal_status == HAL_OK)
- {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Disable all regular-related interrupts */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable ADC peripheral if no injected conversions are on-going */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- tmp_hal_status = ADC_Disable(hadc);
- /* if no issue reported */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral if no conversion is on going
- * on injected group.
- * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
- * For multimode (when multimode feature is available),
- * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential regular conversion on going */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped
- and if no injected conversion is on-going */
- if (tmp_hal_status == HAL_OK)
- {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Disable ADC DMA */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
- /* memory a potential failing status. */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Disable(hadc);
- }
- else
- {
- ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-
-/**
- * @brief Stop DMA-based MultiMode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
- * @note MultiMode is kept enabled after this function. MultiMode DMA bits
- * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
- * MultiMode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
- * resort to HAL_ADCEx_DisableMultiMode() API.
- * @note In case of DMA configured in circular mode, function
- * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* 1. Stop potential multimode conversion on going, on regular groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Clear HAL_ADC_STATE_REG_BUSY bit */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
- tickstart = HAL_GetTick();
-
- while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
- ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
- {
- if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop */
- /* while DMA transfer is on going) */
- /* Note: DMA channel of ADC slave should be stopped after this function */
- /* with HAL_ADCEx_RegularStop_DMA() API. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-
-
- /* 2. Disable the ADC peripherals: master and slave if no injected */
- /* conversion is on-going. */
- /* Update "tmp_hal_status " only if DMA channel disabling passed, to keep in */
- /* memory a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- tmp_hal_status = ADC_Disable(hadc);
- if (tmp_hal_status == HAL_OK)
- {
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
- {
- tmp_hal_status = ADC_Disable(&tmphadcSlave);
- }
- }
- }
-
- if (tmp_hal_status == HAL_OK)
- {
- /* Both Master and Slave ADC's could be disabled. Update Master State */
- /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
- }
- else
- {
- /* injected (Master or Slave) conversions are still on-going,
- no Master State change */
- }
-
- }
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
- * @brief ADC Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on injected group
- (+) Configure multimode when multimode feature is available
- (+) Enable or Disable Injected Queue
- (+) Disable ADC voltage regulator
- (+) Enter ADC deep-power-down mode
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure a channel to be assigned to ADC group injected.
- * @note Possibility to update parameters on the fly:
- * This function initializes injected group, following calls to this
- * function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * Refer to comments of structure "ADC_InjectionConfTypeDef".
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be disabled using function
- * HAL_ADC_DeInit().
- * @note Caution: For Injected Context Queue use, a context must be fully
- * defined before start of injected conversion. All channels are configured
- * consecutively for the same ADC instance. Therefore, the number of calls to
- * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
- * InjectedNbrOfConversion for each context.
- * - Example 1: If 1 context is intended to be used (or if there is no use of the
- * Injected Queue Context feature) and if the context contains 3 injected ranks
- * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
- * called once for each channel (i.e. 3 times) before starting a conversion.
- * This function must not be called to configure a 4th injected channel:
- * it would start a new context into context queue.
- * - Example 2: If 2 contexts are intended to be used and each of them contains
- * 3 injected ranks (InjectedNbrOfConversion = 3),
- * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
- * for each context (3 channels x 2 contexts = 6 calls). Conversion can
- * start once the 1st context is set, that is after the first three
- * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
- * @param hadc: ADC handle
- * @param sConfigInjected: Structure of ADC injected group and ADC channel for
- * injected group.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmpOffsetShifted;
- uint32_t WaitLoopIndex = 0;
-
-
- uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
- assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
- assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
- assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- }
-
- /* Check offset range according to oversampling setting */
- if (hadc->Init.OversamplingMode == ENABLE)
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U)));
- }
- else
- {
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
- }
-
- /* JDISCEN and JAUTO bits can't be set at the same time */
- assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
-
- /* DISCEN and JAUTO bits can't be set at the same time */
- assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
-
- /* Only rank 1 can be configured if there is only one conversion or if Scan conversion mode is disabled */
- assert_param(!(((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || (sConfigInjected->InjectedNbrOfConversion == 1) ) && (sConfigInjected->InjectedRank != ADC_INJECTED_RANK_1)));
-
-
- /* Verification of channel number.
- For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
- channels 16 to 18 can be only used in single-ended mode.
- For ADC3, channels 1 to 11 are available in differential mode,
- channels 12 to 18 can only be used in single-ended mode. */
- if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else
- {
- if (hadc->Instance == ADC3)
- {
- assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else if(hadc->Instance == ADC2)
- {
- assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else
- {
- assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
- }
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
-
- /* Configuration of Injected group sequencer. */
- /* Hardware constraint: Must fully define injected context register JSQR */
- /* before make it entering into injected sequencer queue. */
- /* */
- /* - if scan mode is disabled: */
- /* * Injected channels sequence length is set to 0x00: 1 channel */
- /* converted (channel on injected rank 1) */
- /* Parameter "InjectedNbrOfConversion" is discarded. */
- /* * Injected context register JSQR setting is simple: register is fully */
- /* defined on one call of this function (for injected rank 1) and can */
- /* be entered into queue directly. */
- /* - if scan mode is enabled: */
- /* * Injected channels sequence length is set to parameter */
- /* "InjectedNbrOfConversion". */
- /* * Injected context register JSQR setting more complex: register is */
- /* fully defined over successive calls of this function, for each */
- /* injected channel rank. It is entered into queue only when all */
- /* injected ranks have been set. */
- /* Note: Scan mode is not present by hardware on this device, but used */
- /* by software for alignment over all STM32 devices. */
-
- if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
- (sConfigInjected->InjectedNbrOfConversion == 1) )
- {
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer: fixed to 1st rank */
- /* (scan mode disabled, only rank 1 used) */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
- /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
-
- if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
- {
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
- && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
- {
- tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
- sConfigInjected->ExternalTrigInjecConv |
- sConfigInjected->ExternalTrigInjecConvEdge );
- }
- else
- {
- tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
- }
-
-
- MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
- /* For debug and informative reasons, hadc handle saves JSQR setting */
- hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
-
- }
- }
- else
- {
- /* Case of scan mode enabled, several channels to set into injected group */
- /* sequencer. */
- /* */
- /* Procedure to define injected context register JSQR over successive */
- /* calls of this function, for each injected channel rank: */
- /* 1. Start new context and set parameters related to all injected */
- /* channels: injected sequence length and trigger. */
-
- /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
- /* call of the context under setting */
- if (hadc->InjectionConfig.ChannelCount == 0)
- {
- /* Initialize number of channels that will be configured on the context */
- /* being built */
- hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
- /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
- call, this context will be written in JSQR register at the last call.
- At this point, the context is merely reset */
- hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
-
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
-
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
- && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
- {
- tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
- sConfigInjected->ExternalTrigInjecConv |
- sConfigInjected->ExternalTrigInjecConvEdge );
- }
- else
- {
- tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
- }
-
-
- } /* if (hadc->InjectionConfig.ChannelCount == 0) */
-
-
- /* 2. Continue setting of context under definition with parameter */
- /* related to each channel: channel rank sequence */
- /* Clear the old JSQx bits for the selected rank */
- tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
-
- /* Set the JSQx bits for the selected rank */
- tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
-
- /* Decrease channel count */
- hadc->InjectionConfig.ChannelCount--;
-
-
- /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
- call, aggregate the setting to those already built during the previous
- HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
- hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
-
- /* 4. End of context setting: if this is the last channel set, then write context
- into register JSQR and make it enter into queue */
- if (hadc->InjectionConfig.ChannelCount == 0)
- {
- MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
- }
-
-
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on injected group: */
- /* - Injected context queue: Queue disable (active context is kept) or */
- /* enable (context decremented, up to 2 contexts queued) */
- /* - Injected discontinuous mode: can be enabled only if auto-injected */
- /* mode is disabled. */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* ADC channels preselection */
- hadc->Instance->PCSEL |= (1U << sConfigInjected->InjectedChannel);
-
- /* If auto-injected mode is disabled: no constraint */
- if (sConfigInjected->AutoInjectedConv == DISABLE)
- {
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
- ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
- }
- /* If auto-injected mode is enabled: Injected discontinuous setting is */
- /* discarded. */
- else
- {
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
- }
-
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Automatic injected conversion: can be enabled if injected group */
- /* external triggers are disabled. */
- /* - Channel sampling time */
- /* - Channel offset */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- /* If injected group external triggers are disabled (set to injected */
- /* software start): no constraint */
- if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
- || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
- {
- if (sConfigInjected->AutoInjectedConv == ENABLE)
- {
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- }
- }
- /* If Automatic injected conversion was intended to be set and could not */
- /* due to injected group external triggers enabled, error is reported. */
- else
- {
- if (sConfigInjected->AutoInjectedConv == ENABLE)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- else
- {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
- }
- }
-
- if (sConfigInjected->InjecOversamplingMode == ENABLE)
- {
- assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
- assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
-
- /* JOVSE must be reset in case of triggered regular mode */
- assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
-
- /* Configuration of Injected Oversampler: */
- /* - Oversampling Ratio */
- /* - Right bit shift */
- /* - Left bit shift */
-
- /* Enable OverSampling mode */
-
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
- ADC_CFGR2_JOVSE |
- sConfigInjected->InjecOversampling.Ratio |
- sConfigInjected->InjecOversampling.RightBitShift);
- }
- else
- {
- /* Disable Regular OverSampling */
- CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
- }
- /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, sConfigInjected->InjectedLeftBitShift);
-
- /* Sampling time configuration of the selected channel */
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
- {
- /* Clear the old sample time and set the new one */
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
- }
- else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
- {
- /* Clear the old sample time and set the new one */
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel),
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
- }
-
-
- /* Configure the offset: offset enable/disable, channel, offset value */
-
- /* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
-
- switch (sConfigInjected->InjectedOffsetNumber)
- {
- case ADC_OFFSET_1:
- /* Configure offset register 1: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- MODIFY_REG(hadc->Instance->OFR1,
- ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH,
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT1, sConfigInjected-> InjectedOffsetRightShift);
- /* Enable or disable the signed saturation bit */
- if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
- }
- break;
-
- case ADC_OFFSET_2:
- /* Configure offset register 2: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- /* - Set Right shift after offset application */
- MODIFY_REG(hadc->Instance->OFR2,
- ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH,
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT2, sConfigInjected-> InjectedOffsetRightShift<<1);
- /* Enable or disable the signed saturation bit */
- if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
- }
- break;
-
- case ADC_OFFSET_3:
- /* Configure offset register 3: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- /* - Set Right shift after offset application */
- MODIFY_REG(hadc->Instance->OFR3,
- ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH,
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT3, sConfigInjected-> InjectedOffsetRightShift<<2);
- /* Enable or disable the signed saturation bit */
- if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
- }
- break;
-
- case ADC_OFFSET_4:
- /* Configure offset register 1: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- MODIFY_REG(hadc->Instance->OFR4,
- ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH,
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_RSHIFT4, sConfigInjected-> InjectedOffsetRightShift<<3);
- /* Enable or disable the signed saturation bit */
- if(sConfigInjected->InjectedOffsetSignedSaturation != DISABLE)
- {
- SET_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
- }
- else
- {
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
- }
- break;
-
- /* Case ADC_OFFSET_NONE */
- default :
- break;
- }
-
- } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Configuration of differential mode */
- if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- /* Disable differential mode (default mode: single-ended) */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else
- {
- /* Enable differential mode */
- SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
-
- /* Sampling time configuration of channel ADC_IN+1 (negative input) */
- /* For channels 9 to 15 for ADC1, ADC2, 9 to 11 for ADC3 */
- if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
- {
- /* Clear the old sample time and set the new one */
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
- }
- else /* For channels 0 to 8 */
- {
- /* Clear the old sample time and set the new one */
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1));
- }
- }
-
-
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
- /* internal measurement paths enable: If internal channel selected, */
- /* enable dedicated internal buffers and path. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_deInit(). */
-
- /* Configuration of common ADC parameters */
-
- if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
- }
- else
- {
- /* Pointer to the common control register */
- tmpADC_Common = ADC3_COMMON_REGISTER(hadc);
- }
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
- ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT_DIV4) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
- ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
- )
- {
- /* Configuration of common ADC parameters (continuation) */
- /* Software is allowed to change common parameters only when all ADCs */
- /* of the common group are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
- {
- /* If Channel 17 is selected, enable Temp. sensor measurement path */
- /* Note: Temp. sensor internal channels available only on ADC3 */
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
- (hadc->Instance == ADC3))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-
- /* Delay for temperature sensor stabilization time */
- while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_US)
- {
- WaitLoopIndex++;
- }
- }
- /* If Channel 18 is selected, enable VBAT measurement path */
- /* Note: VBAT internal internal channels available only on ADC3 */
- else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT_DIV4) &&
- (hadc->Instance == ADC3))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
- }
- /* If Channel 0 is selected, enable VREFINT measurement path */
- /* Note: VREFINT internal channels available only on ADC3 */
- else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
- (hadc->Instance == ADC3))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
- }
- else
- {
- /* Discrepancy found out between ADC instance and internal
- channel request */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- tmp_hal_status = HAL_ERROR;
- }
- }
- /* If the requested internal measurement path has already been enabled */
- /* and other ADC of the common group are enabled, internal */
- /* measurement paths cannot be enabled. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- } /* if (ADC_IS_ENABLE(hadc) == RESET) */
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-/**
- * @brief Enable ADC multimode and configure multimode parameters
- * @note Possibility to update parameters on the fly:
- * This function initializes multimode parameters, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
- * the ADCs.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_MultiModeTypeDef".
- * @note To move back configuration from multimode to single mode, ADC must
- * be reset (using function HAL_ADC_Init() ).
- * @param hadc: Master ADC handle
- * @param multimode : Structure of ADC multimode configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_MODE(multimode->Mode));
- if(multimode->Mode != ADC_MODE_INDEPENDENT)
- {
- assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
- assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Multimode DATA Format configuration */
- if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
- {
-
- /* Pointer to the common control register */
- tmpADC_Common = ADC12_COMMON_REGISTER(hadc);
-
- /* If multimode is selected, configure all multimode paramaters. */
- /* Otherwise, reset multimode parameters (can be used in case of */
- /* transition from multimode to independent mode). */
- if(multimode->Mode != ADC_MODE_INDEPENDENT)
- {
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Multimode delay */
- /* Note: Delay range depends on selected resolution: */
- /* from 1 to 9 clock cycles for 16 bits */
- /* from 1 to 9 clock cycles for 14 bits, */
- /* from 1 to 8 clock cycles for 12 bits */
- /* from 1 to 6 clock cycles for 10 and 8 bits */
- /* If a higher delay is selected, it will be clipped to maximum delay */
- /* range */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
- {
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
- multimode->Mode | multimode->TwoSamplingDelay );
- }
- }
- else /* ADC_MODE_INDEPENDENT */
- {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Multimode delay */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
- {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
- }
- }
- }
- /* If one of the ADC sharing the same common group is enabled, no update */
- /* could be done on neither of the multimode structure parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status ;
-}
-
-
-
-/**
- * @brief Enable Injected Queue
- * @note This function resets CFGR register JQDIS bit in order to enable the
- * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
- * are both equal to 0 to ensure that no regulart nor injected
- * conversion is ongoing.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
-{
- /* Parameter can be set only if no conversion is on-going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
-
- /* Update state, clear previous result related to injected queue overflow */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable Injected Queue
- * @note This function sets CFGR register JQDIS bit in order to disable the
- * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
- * are both equal to 0 to ensure that no regulart nor injected
- * conversion is ongoing.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
-{
- /* Parameter can be set only if no conversion is on-going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-
-/**
- * @brief Disable ADC voltage regulator.
- * @note Disabling voltage regulator allows to save power. This operation can
- * be carried out only when ADC is disabled.
- * @note To enable again the voltage regulator, the user is expected to
- * resort to HAL_ADC_Init() API.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
-{
- /* ADVREGEN can be written only when the ADC is disabled */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enter ADC deep-power-down mode
- * @note This mode is achieved in setting DEEPPWD bit and allows to save power
- * in reducing leakage currents. It is particularly interesting before
- * entering STOP1 or STOP2 modes.
- * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
- * ADC voltage regulator. This means that this API encompasses
- * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
- * calibration is lost.
- * @note To exit the ADC deep-power-down mode, the user is expected to
- * resort to HAL_ADC_Init() API as well as to relaunch a calibration
- * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
- * saved calibration factor.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
-{
- /* DEEPPWD can be written only when the ADC is disabled */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
deleted file mode 100644
index fac0f0f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
+++ /dev/null
@@ -1,663 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cec.c
- * @author MCD Application Team
- * @brief CEC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Definition Multimedia Interface
- * Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization function
- * + IO operation function
- * + Peripheral Control function
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The CEC HAL driver can be used as follow:
-
- (#) Declare a CEC_HandleTypeDef handle structure.
- (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
- (##) Enable the CEC interface clock.
- (##) CEC pins configuration:
- (+++) Enable the clock for the CEC GPIOs.
- (+++) Configure these CEC pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
- and HAL_CEC_Receive_IT() APIs):
- (+++) Configure the CEC interrupt priority.
- (+++) Enable the NVIC CEC IRQ handle.
- (+++) The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
-
- (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
- in case of Bit Rising Error, Error-Bit generation conditions, device logical
- address and Listen mode in the hcec Init structure.
-
- (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- [..]
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_CEC_MspInit() API.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CEC CEC
- * @brief HAL CEC module driver
- * @{
- */
-#ifdef HAL_CEC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Functions CEC Exported Functions
- * @{
- */
-
-/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the CEC
- (+) The following parameters need to be configured:
- (++) SignalFreeTime
- (++) Tolerance
- (++) BRERxStop (RX stopped or not upon Bit Rising Error)
- (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
- (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
- (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
- (++) SignalFreeTimeOption (SFT Timer start definition)
- (++) OwnAddress (CEC device address)
- (++) ListenMode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CEC mode according to the specified
- * parameters in the CEC_InitTypeDef and creates the associated handle.
- * @param hcec: CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
- assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
- assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
- assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
- assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
- assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
- assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
- assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
- assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
- assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
-
- if(hcec->gState == HAL_CEC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcec->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_CEC_MspInit(hcec);
- }
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- /* Write to CEC Control Register */
- hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
- hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
- hcec->Init.ListenMode;
-
- /* Enable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
- /* Enable the CEC Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->RxState = HAL_CEC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the CEC peripheral
- * @param hcec: CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if(hcec == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CEC_MspDeInit(hcec);
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- /* Clear Flags */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
-
- /* Disable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_RESET;
- hcec->RxState = HAL_CEC_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the Own Address of the CEC device
- * @param hcec: CEC handle
- * @param CEC_OwnAddress: The CEC own address.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
-{
- /* Check the parameters */
- assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
-
- if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
- {
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
- {
- hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
- }
- else
- {
- hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
- }
-
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief CEC MSP Init
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC MSP DeInit
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the CEC data transfers.
-
- (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
-
- (#) The communication is performed using Interrupts.
- These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated CEC IRQ when using Interrupt mode.
- The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_CEC_ErrorCallback() user callback will be executed when a communication
- error is detected
-
- (#) API's with Interrupt are :
- (+) HAL_CEC_Transmit_IT()
- (+) HAL_CEC_IRQHandler()
-
- (#) A set of User Callbacks are provided:
- (+) HAL_CEC_TxCpltCallback()
- (+) HAL_CEC_RxCpltCallback()
- (+) HAL_CEC_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send data in interrupt mode
- * @param hcec: CEC handle
- * @param InitiatorAddress: Initiator address
- * @param DestinationAddress: destination logical address
- * @param pData: pointer to input byte data buffer
- * @param Size: amount of data to be sent in bytes (without counting the header).
- * 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
-{
- /* if the IP isn't already busy and if there is no previous transmission
- already pending due to arbitration lost */
- if (hcec->gState == HAL_CEC_STATE_READY)
- {
- if((pData == NULL ) && (Size > 0))
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
- assert_param(IS_CEC_ADDRESS(InitiatorAddress));
- assert_param(IS_CEC_MSGSIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hcec);
- hcec->pTxBuffPtr = pData;
- hcec->gState = HAL_CEC_STATE_BUSY_TX;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
-
- /* in case of no payload (Size = 0), sender is only pinging the system;
- Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
- if (Size == 0)
- {
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
- /* send header block */
- hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
- /* Set TX Start of Message (TXSOM) bit */
- __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Get size of the received frame.
- * @param hcec: CEC handle
- * @retval Frame size
- */
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
-{
- return hcec->RxXferSize;
-}
-
-/**
- * @brief Change Rx Buffer.
- * @param hcec: CEC handle
- * @param Rxbuffer: Rx Buffer
- * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
- * @retval Frame size
- */
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
-{
- hcec->Init.RxBuffer = Rxbuffer;
-}
-
-/**
- * @brief This function handles CEC interrupt requests.
- * @param hcec: CEC handle
- * @retval None
- */
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
-{
- /* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg = 0;
- reg = hcec->Instance->ISR;
-
- /*----------------------- Arbitration Lost Management ----------------------*/
- /* CEC TX arbitration error interrupt occurred -----------------------------*/
- if((reg & CEC_FLAG_ARBLST) != RESET)
- {
- hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
- }
-
- /*------------------------------ Rx Management -----------------------------*/
- /* CEC RX byte received interrupt -----------------------------------------*/
- if((reg & CEC_FLAG_RXBR) != RESET)
- {
- /* reception is starting */
- hcec->RxState = HAL_CEC_STATE_BUSY_RX;
- hcec->RxXferSize++;
- /* read received byte */
- *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
- }
-
- /* CEC RX end received interrupt ------------------------------------------*/
- if((reg & CEC_FLAG_RXEND) != RESET)
- {
- /* clear IT */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
-
- /* Rx process is completed, restore hcec->RxState to Ready */
- hcec->RxState = HAL_CEC_STATE_READY;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
- hcec->RxXferSize = 0;
- }
-
- /*------------------------------ Tx Management -----------------------------*/
- /* CEC TX byte request interrupt -------------------------------------------*/
- if((reg & CEC_FLAG_TXBR) != RESET)
- {
- if (hcec->TxXferCount == 0)
- {
- /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- }
- else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- hcec->TxXferCount--;
- }
- /* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- }
-
- /* CEC TX end interrupt ----------------------------------------------------*/
- if((reg & CEC_FLAG_TXEND) != RESET)
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
-
- /* Tx process is ended, restore hcec->gState to Ready */
- hcec->gState = HAL_CEC_STATE_READY;
- /* Call the Process Unlocked before calling the Tx call back API to give the
- possibility to start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hcec);
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- HAL_CEC_TxCpltCallback(hcec);
- }
-
- /*------------------------- Rx/Tx Error Management -------------------------*/
- if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
- {
- hcec->ErrorCode = reg;
- __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
-
- if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
- {
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- hcec->RxXferSize = 0;
- hcec->RxState = HAL_CEC_STATE_READY;
- }
- else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
- {
- /* Set the CEC state ready to be able to start again the process */
- hcec->gState = HAL_CEC_STATE_READY;
- }
-
- /* Error Call Back */
- HAL_CEC_ErrorCallback(hcec);
- }
-}
-
-/**
- * @brief Tx Transfer completed callback
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback
- * @param hcec: CEC handle
- * @param RxFrameSize: Size of frame
- * @retval None
- */
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- UNUSED(RxFrameSize);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC error callbacks
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
- * @brief CEC control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CEC.
- (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
-@endverbatim
- * @{
- */
-/**
- * @brief return the CEC state
- * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC module.
- * @retval HAL state
- */
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hcec->gState;
- temp2 = hcec->RxState;
-
- return (HAL_CEC_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-* @brief Return the CEC error code
-* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC.
-* @retval CEC Error Code
-*/
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
-{
- return hcec->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_CEC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c
deleted file mode 100644
index 0c38b46..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c
+++ /dev/null
@@ -1,848 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_comp.c
- * @author MCD Application Team
- * @brief COMP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the COMP peripheral:
- * + Initialization and de-initialization functions
- * + Start/Stop operation functions in polling mode
- * + Start/Stop operation functions in interrupt mode
- * + Peripheral control functions
- * + Peripheral state functions
- @verbatim
- ================================================================================
- ##### COMP Peripheral features #####
- ================================================================================
-
- [..]
- The STM32H7xx device family integrates two analog comparators instances
- COMP1 and COMP2:
- (#) The COMP input minus (inverting input) and input plus (non inverting input)
- can be set to internal references or to GPIO pins
- (refer to GPIO list in reference manual).
-
- (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
- and can be redirected to other peripherals: GPIO pins (in mode
- alternate functions for comparator), timers.
- (refer to GPIO list in reference manual).
-
- (#) Pairs of comparators instances can be combined in window mode
- (2 consecutive instances odd and even COMP and COMP).
-
- (#) The comparators have interrupt capability through the EXTI controller
- with wake-up from sleep and stop modes:
- (++) COMP1 is internally connected to EXTI Line 20
- (++) COMP2 is internally connected to EXTI Line 21
-
- [..]
- From the corresponding IRQ handler, the right interrupt source can be retrieved
- using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
-
-
-
- ##### How to use this driver #####
- ================================================================================
- [..]
- This driver provides functions to configure and program the comparator instances of
- STM32H7xx devices.
-
- To use the comparator, perform the following steps:
-
- (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
- (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
- using HAL_GPIO_Init().
- (++) If needed, configure the GPIO connected to comparator output in alternate function mode
- using HAL_GPIO_Init().
- (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
- selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
- interrupt vector using HAL_NVIC_EnableIRQ() function.
-
- (#) Configure the comparator using HAL_COMP_Init() function:
- (++) Select the input minus (inverting input)
- (++) Select the input plus (non-inverting input)
- (++) Select the hysteresis
- (++) Select the blanking source
- (++) Select the output polarity
- (++) Select the power mode
- (++) Select the window mode
- -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
- to enable internal control clock of the comparators.
- However, this is a legacy strategy.
- Therefore, for compatibility anticipation, it is recommended to
- implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
- In STM32H7,COMP clock enable __HAL_RCC_COMP12_CLK_ENABLE() must
- be implemented by user in "HAL_COMP_MspInit()".
- (#) Reconfiguration on-the-fly of comparator can be done by calling again
- function HAL_COMP_Init() with new input structure parameters values.
-
- (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
- with the interrupt through NVIC of the CPU.
- Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
- mode will stay disabled.
-
- (#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
- functions to manage comparator outputs(output level or events)
-
- (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
- to disable the interrupt too.
-
- (#) De-initialize the comparator using HAL_COMP_DeInit() function.
-
- (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
- The only way to unlock the comparator is a device hardware reset.
- @endverbatim
- ******************************************************************************
-
- Table 1. COMP inputs and output for STM32H7xx devices
- +---------------------------------------------------------+
- | | | COMP1 | COMP2 |
- |----------------|----------------|-----------|-----------|
- | | IO1 | PB0 | PE9 |
- | Input plus | IO2 | PB2 | PE11 |
- | | | | |
- |----------------|----------------|-----------------------|
- | | 1/4 VrefInt | Available | Available |
- | | 1/2 VrefInt | Available | Available |
- | | 3/4 VrefInt | Available | Available |
- | Input minus | VrefInt | Available | Available |
- | | DAC1 channel 1 | Available | Available |
- | | DAC1 channel 2 | Available | Available |
- | | IO1 | PB1 | PE10 |
- | | IO2 | PC4 | PE7 |
- | | | | |
- | | | | |
- | | | | |
- +---------------------------------------------------------+
- | Output | | PC5 (1) | PE8 (1) |
- | | | PE12 (1) | PE13 (1) |
- | | | TIM (2) | TIM (2) |
- +---------------------------------------------------------+
- (1) GPIO must be set to alternate function for comparator
- (2) Comparators output to timers is set in timers instances.
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup COMP COMP
- * @brief COMP HAL module driver
- * @{
- */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup COMP_Private_Constants
- * @{
- */
-
-/* Delay for COMP startup time. */
-/* Note: Delay required to reach propagation delay specification. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define COMP_DELAY_STARTUP_US ((uint32_t) 80U) /*!< Delay for COMP startup time */
-
-/* Delay for COMP voltage scaler stabilization time. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART_SCALER"). */
-/* Unit: us */
-#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
-
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Functions COMP Exported Functions
- * @{
- */
-
-/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and de-initialization functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions to initialize and de-initialize comparators
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the COMP according to the specified
- * parameters in the COMP_InitTypeDef and initialize the associated handle.
- * @note If the selected comparator is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param hcomp: COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
-{
- uint32_t tmp_csr = 0;
- uint32_t exti_line = 0;
- uint32_t comp_voltage_scaler_not_initialized = 0;
- __IO uint32_t wait_loop_index = 0;
-
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
- assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
- assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
- assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
- assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
- assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
- assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
- assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
- assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
-
- if(hcomp->State == HAL_COMP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcomp->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_COMP_MspInit(hcomp);
- }
- /* Memorize voltage scaler state before initialization */
- comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) == 0);
-
- /* Set COMP parameters */
- /* Set INMSEL bits according to hcomp->Init.InvertingInput value */
- /* Set INPSEL bits according to hcomp->Init.NonInvertingInput value */
- /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */
- /* Set HYST bits according to hcomp->Init.Hysteresis value */
- /* Set POLARITY bit according to hcomp->Init.OutputPol value */
- /* Set POWERMODE bits according to hcomp->Init.Mode value */
-
- tmp_csr = (hcomp->Init.InvertingInput | \
- hcomp->Init.NonInvertingInput | \
- hcomp->Init.BlankingSrce | \
- hcomp->Init.Hysteresis | \
- hcomp->Init.OutputPol | \
- hcomp->Init.Mode );
-
- /* Set parameters in COMP register */
- /* Note: Update all bits except read-only, lock and enable bits */
- MODIFY_REG(hcomp->Instance->CFGR,
- COMP_CFGRx_PWRMODE | COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
- COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST |
- COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN,
- tmp_csr
- );
-
- /* Set window mode */
- /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
- /* instances. Therefore, this function can update another COMP */
- /* instance that the one currently selected. */
- if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
- {
- SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
- }
- else
- {
- CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE);
- }
- /* Delay for COMP scaler bridge voltage stabilization */
- /* Apply the delay if voltage scaler bridge is enabled for the first time */
- if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0) &&
- (comp_voltage_scaler_not_initialized != 0) )
- {
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles.*/
-
- wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
-
- while(wait_loop_index != 0)
- {
- wait_loop_index --;
- }
- }
-
- /* Get the EXTI line corresponding to the selected COMP instance */
- exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
-
- /* Manage EXTI settings */
- if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
- {
- /* Configure EXTI rising edge */
- if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
- {
- SET_BIT(EXTI->RTSR1, exti_line);
- }
- else
- {
- CLEAR_BIT(EXTI->RTSR1, exti_line);
- }
-
- /* Configure EXTI falling edge */
- if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
- {
- SET_BIT(EXTI->FTSR1, exti_line);
- }
- else
- {
- CLEAR_BIT(EXTI->FTSR1, exti_line);
- }
- /* Clear COMP EXTI pending bit (if any) */
- WRITE_REG(EXTI_D1->PR1, exti_line);
-
- /* Configure EXTI event mode */
- if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
- {
- SET_BIT(EXTI_D1->EMR1, exti_line);
- }
- else
- {
- CLEAR_BIT(EXTI_D1->EMR1, exti_line);
- }
-
- /* Configure EXTI interrupt mode */
- if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
- {
- SET_BIT(EXTI_D1->IMR1, exti_line);
- }
- else
- {
- CLEAR_BIT(EXTI_D1->IMR1, exti_line);
- }
- }
- else
- {
- /* Disable EXTI event mode */
- CLEAR_BIT(EXTI_D1->EMR1, exti_line);
-
- /* Disable EXTI interrupt mode */
- CLEAR_BIT(EXTI_D1->IMR1, exti_line);
- }
- /* Set HAL COMP handle state */
- /* Note: Transition from state reset to state ready, */
- /* otherwise (coming from state ready or busy) no state update. */
- if (hcomp->State == HAL_COMP_STATE_RESET)
- {
-
- hcomp->State = HAL_COMP_STATE_READY;
- }
-
- }
-
- return status;
-}
-
-/**
- * @brief DeInitialize the COMP peripheral.
- * @note Deinitialization cannot be performed if the COMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- /* Set COMP_CFGR register to reset value */
- WRITE_REG(hcomp->Instance->CFGR, 0x00000000);
-
- /* DeInit the low level hardware */
- HAL_COMP_MspDeInit(hcomp);
-
- /* Set HAL COMP handle state */
- hcomp->State = HAL_COMP_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcomp);
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the COMP MSP.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the COMP MSP.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
- * @brief Start-Stop operation functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start a Comparator instance without interrupt.
- (+) Stop a Comparator instance without interrupt.
- (+) Start a Comparator instance with interrupt generation.
- (+) Stop a Comparator instance with interrupt generation.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
-{
- __IO uint32_t wait_loop_index = 0;
-
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if(hcomp->State == HAL_COMP_STATE_READY)
- {
- /* Enable the selected comparator */
- SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
-
- /* Set HAL COMP handle state */
- hcomp->State = HAL_COMP_STATE_BUSY;
-
- /* Delay for COMP startup time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles. */
-
- wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
- while(wait_loop_index != 0)
- {
- wait_loop_index--;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Stop the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if((hcomp->State == HAL_COMP_STATE_BUSY) ||
- (hcomp->State == HAL_COMP_STATE_READY) )
- {
-
- /* Disable the selected comparator */
- CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
-
- /* Set HAL COMP handle state */
- hcomp->State = HAL_COMP_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Enable the interrupt and start the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
-{
-
- __IO uint32_t wait_loop_index = 0;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
- /* Set HAL COMP handle state */
- if(hcomp->State == HAL_COMP_STATE_READY)
- {
-
- /* Enable the selected comparator */
- SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN);
- /* Enable the Interrupt comparator */
- SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
-
- hcomp->State = HAL_COMP_STATE_BUSY;
- /* Delay for COMP startup time */
- /* Wait loop initialization and execution */
- /* Note: Variable divided by 2 to compensate partially */
- /* CPU processing cycles. */
-
- wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
- while(wait_loop_index != 0)
- {
- wait_loop_index--;
- }
-
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable the interrupt and Stop the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
- /* Disable the EXTI Line interrupt mode */
- CLEAR_BIT(EXTI_D1->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
- /* Disable the Interrupt comparator */
- CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
-
- status = HAL_COMP_Stop(hcomp);
-
- return status;
-
-}
-
-/**
- * @brief Comparator IRQ Handler.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
-{
- /* Get the EXTI line corresponding to the selected COMP instance */
- uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
-
-
- /* Check COMP EXTI flag */
- if(READ_BIT(EXTI_D1->PR1, exti_line) != RESET)
- {
- /* Check whether comparator is in independent or window mode */
- if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != RESET)
- {
- /* Clear COMP EXTI line pending bit of the pair of comparators */
- /* in window mode. */
- /* Note: Pair of comparators in window mode can both trig IRQ when */
- /* input voltage is changing from "out of window" area */
- /* (low or high ) to the other "out of window" area (high or low).*/
- /* Both flags must be cleared to call comparator trigger */
- /* callback is called once. */
- WRITE_REG(EXTI_D1->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
- }
- else
- {
- /* Clear COMP EXTI line pending bit */
- WRITE_REG(EXTI_D1->PR1, exti_line);
- }
-
- /* COMP trigger user callback */
- HAL_COMP_TriggerCallback(hcomp);
- }
-
- /* Get COMP interrupt source */
- if (__HAL_COMP_GET_IT_SOURCE(hcomp, COMP_IT_EN) != RESET)
- {
-
- if((__HAL_COMP_GET_FLAG( COMP_FLAG_C1I)) != RESET)
- {
- /* Clear the COMP channel 1 interrupt flag */
- __HAL_COMP_CLEAR_C1IFLAG();
-
- /* Disable COMP interrupt */
- __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
-
- }
- if((__HAL_COMP_GET_FLAG( COMP_FLAG_C2I)) != RESET)
- {
- /* Clear the COMP channel 2 interrupt flag */
- __HAL_COMP_CLEAR_C2IFLAG();
-
- /* Disable COMP interrupt */
- __HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
-
- }
-
- /* Change COMP state */
- hcomp->State = HAL_COMP_STATE_READY;
-
- /* COMP trigger user callback */
- HAL_COMP_TriggerCallback(hcomp);
- }
-
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
- * @brief Management functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the comparators.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected comparator configuration.
- * @note A system reset is required to unlock the comparator configuration.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
- /* Set HAL COMP handle state */
- hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
- }
-
- if(status == HAL_OK)
- {
- /* Set the lock bit corresponding to selected comparator */
- __HAL_COMP_LOCK(hcomp);
- }
-
- return status;
-}
-
-/**
- * @brief Return the output level (high or low) of the selected comparator.
- * @note The output level depends on the selected polarity.
- * If the polarity is not inverted:
- * - Comparator output is low when the input plus is at a lower
- * voltage than the input minus
- * - Comparator output is high when the input plus is at a higher
- * voltage than the input minus
- * If the polarity is inverted:
- * - Comparator output is high when the input plus is at a lower
- * voltage than the input minus
- * - Comparator output is low when the input plus is at a higher
- * voltage than the input minus
- * @param hcomp COMP handle
- * @retval Returns the selected comparator output level:
- * @arg @ref COMP_OUTPUT_LEVEL_LOW
- * @arg @ref COMP_OUTPUT_LEVEL_HIGH
- *
- */
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
-{
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if (hcomp->Instance == COMP1)
- {
- return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
- }
- else
- {
- return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1);
- }
-}
-
-/**
- * @brief Comparator callback.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_TriggerCallback should be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the COMP handle state.
- * @param hcomp COMP handle
- * @retval HAL state
- */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
-{
- /* Check the COMP handle allocation */
- if(hcomp == NULL)
- {
- return HAL_COMP_STATE_RESET;
- }
-
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- /* Return HAL COMP handle state */
- return hcomp->State;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
deleted file mode 100644
index f308d30..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
+++ /dev/null
@@ -1,529 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cortex.c
- * @author MCD Application Team
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
- function according to the following table.
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
- (#) please refer to programming manual for details in how to configure priority.
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
- The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest preemption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure Systick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base.
-
- (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
- is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
- inside the stm32h7xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX HAL module driver
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts
- Systick functionalities
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Sets the priority grouping field (preemption priority and subpriority)
- * using the required unlock sequence.
- * @param PriorityGroup The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Sets the priority of an interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @param PreemptPriority The preemption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority
- * @param SubPriority the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enables a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiates a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void)
-{
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- * Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-void HAL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
-
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU and clear the control register*/
- MPU->CTRL = 0;
-}
-
-/**
- * @brief Enables the MPU
- * @param MPU_Control Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Ensure MPU setting take effects */
- __DSB();
- __ISB();
-}
-/**
- * @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Gets the priority of an interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @param PriorityGroup the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
- * @brief Sets Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC
- * and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval status - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if pending else 0 */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
- * @retval status - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if active else 0 */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param CLKSource specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
- {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }
- else
- {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief This function handles SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void)
-{
- HAL_SYSTICK_Callback();
-}
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-
-/**
-* @brief Returns the current CPU ID.
-* @retval CPU identifier
-*/
-uint32_t HAL_GetCurrentCPUID(void)
-{
- return CM7_CPUID;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c
deleted file mode 100644
index 618b288..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c
+++ /dev/null
@@ -1,523 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_crc.c
- * @author MCD Application Team
- * @brief CRC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ===============================================================================
- ##### CRC How to use this driver #####
- ===============================================================================
- [..]
-
- (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-
- (#) Initialize CRC calculator
- (++) specify generating polynomial (IP default or non-default one)
- (++) specify initialization value (IP default or non-default one)
- (++) specify input data format
- (++) specify input or output data inversion mode if any
-
- (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
- input data buffer starting with the previously computed CRC as
- initialization value
-
- (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
- input data buffer starting with the defined initialization value
- (default or non-default) to initiate CRC calculation
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRC CRC
- * @brief CRC HAL module driver.
- * @{
- */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRC according to the specified parameters
- in the CRC_InitTypeDef and create the associated handle
- (+) DeInitialize the CRC peripheral
- (+) Initialize the CRC MSP
- (+) DeInitialize CRC MSP
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the CRC according to the specified
- * parameters in the CRC_InitTypeDef and create the associated handle.
- * @param hcrc: CRC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- if(hcrc->State == HAL_CRC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcrc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_CRC_MspInit(hcrc);
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* check whether or not non-default generating polynomial has been
- * picked up by user */
- assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
- if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
- {
- /* initialize IP with default generating polynomial */
- WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
- }
- else
- {
- /* initialize CRC IP with generating polynomial defined by user */
- if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
-
- /* check whether or not non-default CRC initial value has been
- * picked up by user */
- assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
- if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
- {
- WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
- }
- else
- {
- WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
- }
-
-
- /* set input data inversion mode */
- assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
-
- /* set output data inversion mode */
- assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
-
- /* makes sure the input data format (bytes, halfwords or words stream)
- * is properly specified by user */
- assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the CRC peripheral.
- * @param hcrc: CRC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- /* Check the CRC peripheral state */
- if(hcrc->State == HAL_CRC_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC calculation unit */
- __HAL_CRC_DR_RESET(hcrc);
-
- /* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
-
- /* DeInit the low level hardware */
- HAL_CRC_MspDeInit(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_RESET;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the CRC MSP.
- * @param hcrc: CRC handle
- * @retval None
- */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CRC_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the CRC MSP.
- * @param hcrc: CRC handle
- * @retval None
- */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CRC_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Group2 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- using combination of the previous CRC value and the new one.
-
- or
-
- (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- independently of the previous CRC value.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- * starting with the previously computed CRC as initialization value.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length (number of bytes if pBuffer
- * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
- * number of words if pBuffer type is * uint32_t).
- * @note By default, the API expects a uint32_t pointer as input buffer parameter.
- * Input buffer pointers with other types simply need to be cast in uint32_t
- * and the API will internally adjust its input data processing based on the
- * handle field hcrc->InputDataFormat.
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- switch (hcrc->InputDataFormat)
- {
- case CRC_INPUTDATA_FORMAT_WORDS:
- /* Enter Data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
- temp = hcrc->Instance->DR;
- break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
- break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
- break;
- default:
- break;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return temp;
-}
-
-/**
- * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- * starting with hcrc->Instance->INIT as initialization value.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length (number of bytes if pBuffer
- * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
- * number of words if pBuffer type is * uint32_t).
- * @note By default, the API expects a uint32_t pointer as input buffer parameter.
- * Input buffer pointers with other types simply need to be cast in uint32_t
- * and the API will internally adjust its input data processing based on the
- * handle field hcrc->InputDataFormat.
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
- * written in hcrc->Instance->DR) */
- __HAL_CRC_DR_RESET(hcrc);
-
- switch (hcrc->InputDataFormat)
- {
- case CRC_INPUTDATA_FORMAT_WORDS:
- /* Enter 32-bit input data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
- temp = hcrc->Instance->DR;
- break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
- /* Specific 8-bit input data handling */
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
- break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
- /* Specific 16-bit input data handling */
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
- break;
- default:
- break;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return temp;
-}
-
-/**
- * @brief Enter 8-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0; /* input data buffer index */
-
- /* Processing time optimization: 4 bytes are entered in a row with a single word write,
- * last bytes must be carefully fed to the CRC calculator to ensure a correct type
- * handling by the IP */
- for(i = 0; i < (BufferLength/4); i++)
- {
- hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
- }
- /* last bytes specific handling */
- if((BufferLength%4) != 0)
- {
- if(BufferLength%4 == 1)
- {
- *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
- }
- if(BufferLength%4 == 2)
- {
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
- }
- if(BufferLength%4 == 3)
- {
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
- *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
- }
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-/**
- * @brief Enter 16-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0; /* input data buffer index */
-
- /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
- * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
- * a correct type handling by the IP */
- for(i = 0; i < (BufferLength/2); i++)
- {
- hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
- }
- if((BufferLength%2) != 0)
- {
- *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the CRC state.
- * @param hcrc: CRC handle
- * @retval HAL state
- */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
- return hcrc->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c
deleted file mode 100644
index e573bc5..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_crc_ex.c
- * @author MCD Application Team
- * @brief Extended CRC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CRC peripheral:
- * + Initialization/de-initialization functions
- *
- @verbatim
- ==============================================================================
- ##### CRC specific features #####
- ==============================================================================
- [..]
- (#) Polynomial configuration.
- (#) Input data reverse mode.
- (#) Output data reverse mode.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRCEx
- * @brief CRC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup CRCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup CRCEx_Exported_Functions_Group1
- * @brief Extended CRC features functions
- *
-@verbatim
- ===============================================================================
- ##### CRC Extended features functions #####
- ===============================================================================
- [..]
-This subsection provides function allowing to:
- (+) Set CRC polynomial if different from default one.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the CRC polynomial if different from default one.
- * @param hcrc: CRC handle
- * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
- * This parameter is written in normal representation, e.g.
- * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
- * @param PolyLength: CRC polynomial length
- * This parameter can be one of the following values:
- * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
- * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
- * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
- * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
-{
- uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
-
- /* Check the parameters */
- assert_param(IS_CRC_POL_LENGTH(PolyLength));
-
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
- {
- }
-
- switch (PolyLength)
- {
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- return HAL_ERROR;
- }
-
- /* set generating polynomial */
- WRITE_REG(hcrc->Instance->POL, Pol);
-
- /* set generating polynomial size */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the Reverse Input data mode.
- * @param hcrc: CRC handle
- * @param InputReverseMode: Input Data inversion mode
- * This parameter can be one of the following values:
- * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
- * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
-{
- /* Check the parameters */
- assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* set input data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the Reverse Output data mode.
- * @param hcrc: CRC handle
- * @param OutputReverseMode: Output Data inversion mode
- * This parameter can be one of the following values:
- * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
- * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
-{
- /* Check the parameters */
- assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* set output data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c
deleted file mode 100644
index 8fbb5da..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c
+++ /dev/null
@@ -1,3707 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cryp.c
- * @author MCD Application Team
- * @brief CRYP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Cryptography (CRYP) peripheral:
- * + Initialization and de-initialization functions
- * + AES processing functions
- * + DES processing functions
- * + TDES processing functions
- * + DMA callback functions
- * + CRYP IRQ handler management
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The CRYP HAL driver can be used in CRYP IP as follows:
-
- (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
- (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
- (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
- (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
- (+++) Configure and enable two DMA streams one for managing data transfer from
- memory to peripheral (input stream) and another stream for managing data
- transfer from peripheral to memory (output stream)
- (+++) Associate the initialized DMA handle to the CRYP DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
-
- (#)Initialize the CRYP according to the specified parameters :
- (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
- (##) The key size: 128, 192 or 256.
- (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
- (##) The initialization vector (counter). It is not used in ECB mode.
- (##) The key buffer used for encryption/decryption.
- (##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize The size of header buffer in word.
- (##) The B0 block is the first authentication block used only in AES CCM mode.
-
- (#)Three processing (encryption/decryption) functions are available:
- (##) Polling mode: encryption and decryption APIs are blocking functions
- i.e. they process the data and wait till the processing is finished,
- e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt,
- e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
- (##) DMA mode: encryption and decryption APIs are not blocking functions
- i.e. the data transfer is ensured by DMA,
- e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
-
- (#)When the processing function is called at first time after HAL_CRYP_Init()
- the CRYP peripheral is configured and processes the buffer in input.
- At second call, no need to Initialize the CRYP, user have to get current configuration via
- HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
- new parametres, finally user can start encryption/decryption.
-
- (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-
- [..]
- The cryptographic processor supports following standards:
- (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
- (##)64-bit data block processing
- (##) chaining modes supported :
- (+++) Electronic Code Book(ECB)
- (+++) Cipher Block Chaining (CBC)
- (##) keys length supported :64-bit, 128-bit and 192-bit.
- (#) The advanced encryption standard (AES) supported by CRYP1:
- (##)128-bit data block processing
- (##) chaining modes supported :
- (+++) Electronic Code Book(ECB)
- (+++) Cipher Block Chaining (CBC)
- (+++) Counter mode (CTR)
- (+++) Galois/counter mode (GCM/GMAC)
- (+++) Counter with Cipher Block Chaining-Message(CCM)
- (##) keys length Supported :
- (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
-
- [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
- (#) Algorithm supported :
- (##) Galois/counter mode (GCM)
- (##) Galois message authentication code (GMAC) :is exactly the same as
- GCM algorithm composed only by an header.
- (#) Four phases are performed in GCM :
- (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
- (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
- computation only.
- (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
- encryption + data XORing. It works in a similar way for ciphertext (C).
- (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
- (#) structure of message construction in GCM is defined as below :
- (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
- (##) The authenticated header A (also knows as Additional Authentication Data AAD)
- this part of the message is only authenticated, not encrypted.
- (##) The plaintext message P is both authenticated and encrypted as ciphertext.
- GCM standard specifies that ciphertext has same bit length as the plaintext.
- (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
- (on 64 bits)
-
- [..] This section describe The AES Counter with Cipher Block Chaining-Message
- Authentication Code (CCM) supported by both CRYP1 IP:
- (#) Specific parameters for CCM :
-
- (##) B0 block : According to NIST Special Publication 800-38C,
- The first block B0 is formatted as follows, where l(m) is encoded in
- most-significant-byte first order(see below table 3)
-
- (+++) Q: a bit string representation of the octet length of P (plaintext)
- (+++) q The octet length of the binary representation of the octet length of the payload
- (+++) A nonce (N), n The octet length of the where n+q=15.
- (+++) Flags: most significant octet containing four flags for control information,
- (+++) t The octet length of the MAC.
- (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
- the associated data length expressed in bytes (a) defined as below:
- (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
- (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
- (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
- (##) CTRx block : control blocks
- (+++) Generation of CTR1 from first block B0 information :
- equal to B0 with first 5 bits zeroed and most significant bits storing octet
- length of P also zeroed, then incremented by one ( see below Table 4)
- (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
-
- (#) Four phases are performed in CCM for CRYP1 IP:
- (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
- (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
- computation only.
- (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
- encryption + data XORing. It works in a similar way for ciphertext (C).
- (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
-
- @endverbatim
-
- Table 1. Initial Counter Block (ICB)
- +-------------------------------------------------------+
- | Initialization vector (IV) | Counter |
- |----------------|----------------|-----------|---------|
- 127 95 63 31 0
-
-
- Bit Number Register Contents
- ---------- --------------- -----------
- 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
- 95 ...64 CRYP_IV1L[31:0] B0[95:64]
- 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
- 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
-
- Table 2. GCM last block definition
-
- +-------------------------------------------------------------------+
- | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
- |-----------|--------------------|-----------|----------------------|
- | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
- |-----------|--------------------|-----------|----------------------|
-
- Table 3. B0 block
- Octet Number Contents
- ------------ ---------
- 0 Flags
- 1 ... 15-q Nonce N
- 16-q ... 15 Q
-
- the Flags field is formatted as follows:
-
- Bit Number Contents
- ---------- ----------------------
- 7 Reserved (always zero)
- 6 Adata
- 5 ... 3 (t-2)/2
- 2 ... 0 [q-1]3
-
- Table 4. CTRx block
- Bit Number Register Contents
- ---------- --------------- -----------
- 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
- bit 0 that is set to 1
- 95 ...64 CRYP_IV1L[31:0] B0[95:64]
- 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
- 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
-
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#if defined (CRYP)
-
-/** @defgroup CRYP CRYP
- * @brief CRYP HAL module driver.
- * @{
- */
-
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Defines
- * @{
- */
-#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
-
-#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
-#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
-
-#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
-#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
-#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
-
-
- /* CTR1 information to use in CCM algorithm */
-#define CRYP_CCM_CTR1_0 0x07FFFFFFU
-#define CRYP_CCM_CTR1_1 0xFFFFFF00U
-#define CRYP_CCM_CTR1_2 0x00000001U
-
-
-/**
- * @}
- */
-
-
-/* Private macro -------------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Macros
- * @{
- */
-
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0)
-
-#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
-
-
-/**
- * @}
- */
-
-/* Private struct -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions_prototypes
- * @{
- */
-
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
-static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
-
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief CRYP Initialization and Configuration functions.
- *
-@verbatim
- ========================================================================================
- ##### Initialization, de-initialization and Set and Get configuration functions #####
- ========================================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP
- (+) DeInitialize the CRYP
- (+) Initialize the CRYP MSP
- (+) DeInitialize the CRYP MSP
- (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
- Parameters which are configured in This section are :
- (++) Key size
- (++) Data Type : 32,16, 8 or 1bit
- (++) AlgoMode : for CRYP1 IP
- ECB and CBC in DES/TDES Standard
- ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
- (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
-
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the CRYP according to the specified
- * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
- assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
-
- if(hcryp->State == HAL_CRYP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcryp->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
- }
-
- /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
- /* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = CRYP_PHASE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the CRYP peripheral.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Set the default CRYP phase */
- hcryp->Phase = CRYP_PHASE_READY;
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
- hcryp->CrypHeaderCount =0;
-
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the CRYP according to the specified
- * parameters in the CRYP_ConfigTypeDef
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
- /* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
- assert_param(IS_CRYP_DATATYPE(pConf->DataType));
- assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Set CRYP parameters */
- hcryp->Init.DataType = pConf->DataType;
- hcryp->Init.pKey = pConf->pKey;
- hcryp->Init.Algorithm = pConf->Algorithm;
- hcryp->Init.KeySize = pConf->KeySize;
- hcryp->Init.pInitVect = pConf->pInitVect;
- hcryp->Init.Header = pConf->Header;
- hcryp->Init.HeaderSize = pConf->HeaderSize;
- hcryp->Init.B0 = pConf->B0;
-
- /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type, AlgoMode and operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = CRYP_PHASE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get CRYP Configuration parameters in associated handle.
- * @param pConf: pointer to a CRYP_ConfigTypeDef structure
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
- /* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
- {
- return HAL_ERROR;
- }
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Get CRYP parameters */
- pConf->DataType = hcryp->Init.DataType;
- pConf->pKey = hcryp->Init.pKey;
- pConf->Algorithm = hcryp->Init.Algorithm;
- pConf->KeySize = hcryp->Init.KeySize ;
- pConf->pInitVect = hcryp->Init.pInitVect;
- pConf->Header = hcryp->Init.Header ;
- pConf->HeaderSize = hcryp->Init.HeaderSize;
- pConf->B0 = hcryp->Init.B0;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-/**
- * @brief Initializes the CRYP MSP.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes CRYP MSP.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
- * @brief CRYP processing functions.
- *
-@verbatim
- ==============================================================================
- ##### Encrypt Decrypt functions #####
- ==============================================================================
- [..] This section provides API allowing to Encrypt/Decrypt Data following
- Standard DES/TDES or AES, and Algorithm configured by the user:
- (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
- (++) Electronic Code Book(ECB)
- (++) Cipher Block Chaining (CBC)
- (+) Standard AES supported by CRYP1 IP , list of Algorithm supported:
- (++) Electronic Code Book(ECB)
- (++) Cipher Block Chaining (CBC)
- (++) Counter mode (CTR)
- (++) Cipher Block Chaining (CBC)
- (++) Counter mode (CTR)
- (++) Galois/counter mode (GCM)
- (++) Counter with Cipher Block Chaining-Message(CCM)
- [..] Three processing functions are available:
- (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
- (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
- (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Encryption mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word.
- * @param Output: Pointer to the output buffer(ciphertext)
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
-{
- uint32_t algo = 0U;
- HAL_StatusTypeDef state;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set Encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Statrt DES/TDES encryption process */
- state = CRYP_TDES_Process(hcryp,Timeout);
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- state = CRYP_AES_Encrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM encryption */
- state = CRYP_AESGCM_Process(hcryp, Timeout);
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- state = CRYP_AESCCM_Process(hcryp,Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- if (state == HAL_OK)
- {
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Decryption mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word.
- * @param Output: Pointer to the output buffer(plaintext)
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
-{
- HAL_StatusTypeDef state;
- uint32_t algo = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set Decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DES/TDES decryption process */
- state = CRYP_TDES_Process(hcryp, Timeout);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- state = CRYP_AES_Decrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- state = CRYP_AESGCM_Process (hcryp, Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- state = CRYP_AESCCM_Process(hcryp, Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- if (state == HAL_OK)
- {
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Encryption in interrupt mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word
- * @param Output: Pointer to the output buffer(ciphertext)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
-{
- uint32_t algo = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP to start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- CRYP_AES_Encrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM:
-
- CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Decryption in itnterrupt mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word.
- * @param Output: Pointer to the output buffer(plaintext)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
-{
- uint32_t algo = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP and start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- CRYP_AES_Decrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCMdecryption */
- CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Encryption in DMA mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word.
- * @param Output: Pointer to the output buffer(ciphertext)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
-{
- uint32_t algo = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM encryption */
- CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Decryption in DMA mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word
- * @param Output: Pointer to the output buffer(plaintext)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
-{
- uint32_t algo = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Change state Busy */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
- hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
- hcryp->Size = Size;
-
- /* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- CRYP_AES_Decrypt_DMA(hcryp);
- break;
-
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- CRYP_AESGCM_Process_DMA (hcryp) ;
-
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
- * @brief CRYP IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### CRYP IRQ handler management #####
- ==============================================================================
-[..] This section provides CRYP IRQ handler and callback functions.
- (+) HAL_CRYP_IRQHandler CRYP interrupt request
- (+) HAL_CRYP_InCpltCallback input data transfer complete callback
- (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
- (+) HAL_CRYP_ErrorCallback CRYP error callback
- (+) HAL_CRYP_GetState return the CRYP state
- (+) HAL_CRYP_GetError return the CRYP error code
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles cryptographic interrupt request.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t CurrentMode = 0U;
-
- /*put CRYP_IT_OUTI flag status in CurrentMode variable*/
- CurrentMode = __HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI);
-
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != RESET)| (CurrentMode != RESET))
- {
- if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- CRYP_TDES_IT(hcryp); /* DES or TDES*/
- }
- else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
- {
- CRYP_AES_IT(hcryp); /*AES*/
- }
-
- else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
- {
- /* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
- }
-}
-
-/**
- * @brief Return the CRYP error code.
- * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for the CRYP IP
- * @retval CRYP error code
- */
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
-{
- return hcryp->ErrorCode;
-}
-
-/**
- * @brief Returns the CRYP state.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval HAL state
- */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
- return hcryp->State;
-}
-
-/**
- * @brief Input FIFO transfer completed callback.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval None
- */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Output FIFO transfer completed callback.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval None
- */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief CRYP error callback.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval None
- */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions
- * @{
- */
-
-/**
- * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
-
- uint32_t temp = 0U; /* Temporary CrypOutBuff */
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Start processing*/
- while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Write plain data and get cipher data */
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
-
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state & errorCode*/
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- }
- }
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t temp = 0U; /* Temporary CrypOutBuff */
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != RESET) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != RESET))
-
- {
- /* Write input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
- if(hcryp->CrypInCount == hcryp->Size)
- {
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Call the input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != RESET)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != RESET))
- {
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == hcryp->Size)
- {
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
- return HAL_OK;
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: specify Timeout value
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Write plain Ddta and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
- }
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0U)
- {
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Decryption in ECB/CBC & CTR mode with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
-{
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
- {
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
- }
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
- {
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- if(count-- == 0U)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
- if(hcryp->Size != 0)
- {
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Process locked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
- {
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- }
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0)
- {
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief DMA CRYP input data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP output data process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output FIFO request by resetting
- the DOEN bit in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
- if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
- {
- /* Disable CRYP (not allowed in GCM)*/
- __HAL_CRYP_DISABLE(hcryp);
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Change the CRYP peripheral state */
- hcryp->State= HAL_CRYP_STATE_READY;
-
- /* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
- /* Call error callback */
- HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
- * @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param inputaddr: address of the input buffer
- * @param Size: size of the input buffer, must be a multiple of 16.
- * @param outputaddr: address of the output buffer
- * @retval None
- */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-
- /* Set the DMA input error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-
- /* Set the DMA output error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Enable the input DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size);
-
- /* Enable the output DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size);
-
- /* Enable In/Out DMA request */
- hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
-}
-
-/**
- * @brief Process Data: Write Input data in polling mode and used in AES functions.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: Specify Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
-
- uint32_t temp = 0U; /* Temporary CrypOutBuff */
-
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
-
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state & error code*/
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handle CRYP block input/output data handling under interruption.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t temp = 0U; /* Temporary CrypOutBuff */
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != RESET) && (hcryp->CrypInCount < hcryp->Size))
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->CrypInCount == hcryp->Size)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Call the input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == hcryp->Size)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call output transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Writes Key in Key registers.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key: Pointer to Key buffer
- * @param KeySize: Size of Key
- * @retval None
- */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t KeySize)
-{
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
-
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t payloadlength = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /****************************** Init phase **********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /*************************Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Write input data and get output Data */
- if ((hcryp->Size % 4U) == 0U)
- {
- while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state & error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- }
- else
- {
- payloadlength = (((hcryp->Size)/4U)*4U) ;
-
- /*Write input block in the IN FIFO without last block */
- while((hcryp->CrypInCount < payloadlength) && (hcryp->CrypOutCount < payloadlength))
- {
- /* Write input Data and get output Data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
- 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount =0U;
-
- /******************************* Init phase *********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /***************************** Header phase *********************************/
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
- uint32_t payloadlength = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /*************************** Init phase ************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- if(hcryp->Size != 0U)
- {
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 4U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
- {
- payloadlength = (hcryp->Size)+(4-(hcryp->Size)%4U) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), payloadlength, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- }
- else
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief AES CCM encryption/decryption processing in polling mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t payloadlength =0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /********************** Init phase ******************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write B0 packet into CRYP_DR*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
-
- /************************* Header phase *************************************/
- /* Header block(B1) : associated data length expressed in bytes concatenated
- with Associated Data (A)*/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
- {
- return HAL_ERROR;
- }
- /********************** Payload phase ***************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Write input data and get output data */
- if((hcryp->Size % 4U) == 0U)
- {
- while((hcryp->CrypInCount < hcryp->Size) && (hcryp->CrypOutCount < hcryp->Size))
- {
- /* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- }
- else
- {
- if(hcryp->Size > 4U)
- {
- payloadlength = (((hcryp->Size)/4)*4) ;
- /*Write input block in the IN FIFO without last block */
- while((hcryp->CrypInCount < payloadlength) && (hcryp->CrypOutCount < payloadlength))
- {
- /* Write input data and get output data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- }
- /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
- 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief AES CCM encryption/decryption process in interrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /************ Init phase ************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DR*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
- }
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief AES CCM encryption/decryption process in DMA mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t payloadlength = 0U;
- __IO uint32_t count = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /************************** Init phase **************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DR*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
- }
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /********************* Header phase *****************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- if(hcryp->Size != 0U)
- {
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 4U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else
- {
- payloadlength = (hcryp->Size)+(4-(hcryp->Size %4)) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), payloadlength, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- }
- else /*Size = 0*/
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the payload phase in iterrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval state
- */
-static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t loopcounter = 0U;
- uint32_t temp = 0U; /* Temporary CrypOutBuff */
-
- /***************************** Payload phase *******************************/
-
- if(hcryp->Size == 0U)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- else if ((hcryp->Size) - (hcryp->CrypInCount) >= 4)
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->Size == hcryp->CrypInCount)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Call the input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- if(hcryp->CrypOutCount < hcryp->Size)
- {
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if (hcryp->Size == hcryp->CrypOutCount)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call output transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
- }
- else if ((hcryp->Size %4U )!= 0U)
- {
- /* Size should be %4 otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
-
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Size %4 ); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET)
- {
- for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer */
- temp= hcryp->Instance->DOUT;
-
- /*get CrypOutBuff from temporary buffer */
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
- hcryp->CrypOutCount++;
- }
- }
- if(hcryp->CrypOutCount >= hcryp->Size)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call output transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Sets the header phase in polling mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
- * @param Timeout: Timeout value
- * @retval state
- */
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t loopcounter = 0U;
-
- /***************************** Header phase for GCM/GMAC or CCM *********************************/
-
- if((hcryp->Init.HeaderSize != 0U))
- {
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- /* Wait for CCF IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Wait until the complete message has been processed */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the header phase when using DMA in process
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
-{
- __IO uint32_t count = 0U;
- uint32_t loopcounter = 0U;
-
- /***************************** Header phase for GCM/GMAC or CCM *********************************/
- if((hcryp->Init.HeaderSize != 0U))
- {
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4 ))); loopcounter+=4)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- /* Wait for IFEM to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
- }
- /* Wait until the complete message has been processed */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- if(count-- == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the header phase in interrupt mode
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t loopcounter = 0U;
-
- /***************************** Header phase *********************************/
-
- if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else if ((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)
-
- { /* HeaderSize %4, no padding */
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- else
- {
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Workaround used for GCM/CCM mode.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: Timeout value
- * @retval None
- */
-static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
-{
- uint32_t plength = 0U;
- uint32_t iv1temp = 0U;
- uint32_t temp[4] = {0};
- uint32_t temp2[4]= {0};
- uint32_t intermediate_data[4]={0};
- uint32_t index = 0U;
-
- /* Workaround 2, case GCM encryption */
- if (hcryp->Init.Algorithm == CRYP_AES_GCM)
- {
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
- {/*Workaround in order to properly compute authentication tags while doing
- a GCM encryption with the last block of payload size inferior to 128 bits*/
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
- by 1 and reinsert the result in CRYP_IV1R register*/
- hcryp->Instance->IV1RR = 0x5U;
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
- /* Enable CRYP to start the final phase */
- __HAL_CRYP_ENABLE(hcryp);
- }
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < (hcryp->Size % 4); index ++)
- {
- /* Write the last input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
- while(index < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0U;
- index++;
- }
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
- {
- for(index=0U; index< 4U;index++)
- {
- /* Read the output block from the output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
-
- /* Intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /*workaround in order to properly compute authentication tags while doing
- a GCM encryption with the last block of payload size inferior to 128 bits*/
- /* Change the AES mode to GCM mode and Select Final phase */
- /* configured CHMOD GCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
-
- /* configured final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- for (index=0U; index < (hcryp->Size % 4U); index ++)
- {
- /*Write the intermediate_data in the IN FIFO */
- hcryp->Instance->DIN=intermediate_data[index];
- }
- while(index < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- index++;
- }
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET)
- {
- for( index=0U; index< 4U;index++)
- {
- intermediate_data[index]=hcryp->Instance->DOUT;
- }
- }
- }
- } /* End of GCM encryption */
- else{ /* Workaround 2, case CCM decryption, in order to properly compute
- authentication tags while doing a CCM decryption with the last block
- of payload size inferior to 128 bits*/
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
- {
- iv1temp = hcryp->Instance->CSGCMCCM7R;
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- temp[0]= hcryp->Instance->CSGCMCCM0R;
- temp[1]= hcryp->Instance->CSGCMCCM1R;
- temp[2]= hcryp->Instance->CSGCMCCM2R;
- temp[3]= hcryp->Instance->CSGCMCCM3R;
-
- hcryp->Instance->IV1RR= iv1temp;
-
- /* Configured CHMOD CTR */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
- /* Enable CRYP to start the final phase */
- __HAL_CRYP_ENABLE(hcryp);
- }
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < (hcryp->Size % 4); index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
- while(index < 4)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0;
- index++;
- }
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != RESET) && (hcryp->CrypOutCount < hcryp->Size))
- {
- for(index=0U; index< 4U;index++)
- {
- /* Read the Output block from the Output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
-
- /*intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
- {
- temp2[0]= hcryp->Instance->CSGCMCCM0R;
- temp2[1]= hcryp->Instance->CSGCMCCM1R;
- temp2[2]= hcryp->Instance->CSGCMCCM2R;
- temp2[3]= hcryp->Instance->CSGCMCCM3R;
-
- /* configured CHMOD CCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
-
- /* configured Header phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
-
- plength=(hcryp->Init.B0[3] & 0x000000FFU);
-
- /*set to zero the bits corresponding to the padded bits*/
- for(index = (hcryp->Size % 4U); index<4U; index ++)
- {
- intermediate_data[index] =0U;
- }
-
- if ((plength %4U)==1U)
- {
- intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFF000000U;
- }
- if ((plength %4U)==2U)
- {
- intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFFFF0000U;
- }
- if ((plength %4U)==3U)
- {
- intermediate_data[(hcryp->Size % 4U)-1U] = intermediate_data[(hcryp->Size % 4U)-1U] & 0xFFFFFF00U;
- }
- ;
- for(index=0U; index < 4U ; index ++)
- {
- intermediate_data[index] ^= temp[index];
- intermediate_data[index] ^= temp2[index];
- }
- for(index = 0U; index < 4U; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DIN = intermediate_data[index] ;
- }
-
- /* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
- }
- } /* End of CCM WKA*/
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-}
-
-
-/**
- * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-/**
- * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-
-/**
- * @}
- */
-#endif /* CRYP*/
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c
deleted file mode 100644
index 3717bfd..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_cryp_ex.c
- * @author MCD Application Team
- * @brief Extended CRYP HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of CRYP extension peripheral:
- * + Extended AES processing functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
- Encryption/Decryption to get the authentication messages.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#if defined (CRYP)
-/** @defgroup CRYPEx CRYPEx
- * @brief CRYP Extension HAL module driver.
- * @{
- */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_Defines
- * @{
- */
-
-#define CRYP_PHASE_INIT 0x00000000U
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
-
-#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
-#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
-
-#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
-#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
-
- /* CTR0 information to use in CCM algorithm */
-#define CRYP_CCM_CTR0_0 0x07FFFFFFU
-#define CRYP_CCM_CTR0_3 0xFFFFFF00U
-
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-
-
-/* Exported functions---------------------------------------------------------*/
-/** @addtogroup CRYPEx_Exported_Functions
- * @{
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief CRYPEx Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### Extended AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to generate the authentication
- TAG in Polling mode
- (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
- (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
- they should be used after Encrypt/Decrypt operation.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief generate the GCM authentication TAG.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param AuthTag: Pointer to the authentication buffer
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint64_t headerlength = hcryp->Init.HeaderSize * 32U; /* Header length in bits */
- uint64_t inputlength = (hcryp->Size) * 32U; /* input length in bits */
- uint32_t tagaddr = (uint32_t)AuthTag;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = CRYPEx_PHASE_FINAL;
- }
- else /* Initialization phase has not been performed*/
- {
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Sequence error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- /*ALGODIR bit must be set to ‘0’.*/
- hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the number of bits in header (64 bits) followed by the number of bits
- in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = (uint32_t)(headerlength);
- hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = (uint32_t)(inputlength);
- }
-
- /* Wait for OFNE flag to be raised */
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
-
- /* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
-
- /* Disable the peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief AES CCM Authentication TAG generation.
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param AuthTag: Pointer to the authentication buffer
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tagaddr = (uint32_t)AuthTag;
- uint32_t ctr0 [4]={0};
- uint32_t ctr0addr = (uint32_t)ctr0;
- uint32_t tickstart = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = CRYPEx_PHASE_FINAL;
- }
- else /* Initialization phase has not been performed*/
- {
- /* Disable the peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Sequence error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase & ALGODIR bit must be set to ‘0’. */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the counter block in the IN FIFO, CTR0 information from B0
- data has to be swapped according to the DATATYPE*/
- ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
- ctr0[1]=hcryp->Init.B0[1];
- ctr0[2]=hcryp->Init.B0[2];
- ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
-
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);;
- }
- /* Wait for OFNE flag to be raised */
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the CRYP peripheral Clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
-
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- }
- else
- {
- /* Busy error code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
- return HAL_ERROR;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-/**
- * @}
- */
-#endif /* CRYP*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
deleted file mode 100644
index 770eb29..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
+++ /dev/null
@@ -1,1176 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dac.c
- * @author MCD Application Team
- * @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Digital to Analog Converter (DAC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- *
- @verbatim
- ==============================================================================
- ##### DAC Peripheral features #####
- ==============================================================================
- [..]
- *** DAC Channels ***
- ====================
- [..]
- STM32H7 devices integrate two 12-bit Digital Analog Converters.
-
- The 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode):
- (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
- peripherals (ex. OPAMPs, comparators).
- (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
- peripherals (ex. OPAMPs, comparators).
-
- *** DAC Triggers ***
- ====================
- [..]
- Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
- and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
- [..]
- Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
- The used pin (GPIOx_PIN_9) must be configured in input mode.
-
-
- (#) Timers TRGO:TIM1,TIM2,TIM4, TIM5, TIM6, TIM7,TIM8 and TIM15
- (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
-
- (#) Timers TRGO: HRTIM1,LPTIM1,LPTIM2
- (DAC_TRIGGER_HR1_TRGO1,DAC_TRIGGER_HR1_TRGO2,DAC_TRIGGER_LP1_OUT,DAC_TRIGGER_LP2_OUT)
- (#) Software using DAC_TRIGGER_SOFTWARE
-
- *** DAC Buffer mode feature ***
- ===============================
- [..]
- Each DAC channel integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
- [..]
- (@) Refer to the device datasheet for more details about output
- impedance value with and without output buffer.
-
- *** DAC connect feature ***
- ===============================
- [..]
- Each DAC channel can be connected internally.
- To connect, use
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
-
- *** GPIO configurations guidelines ***
- ====================================
- [..]
- When a DAC channel is used (ex channel1 on PA4) and the other is not
- (ex channel2 on PA5 is configured in Analog and disabled).
- Channel1 may disturb channel2 as coupling effect.
- Note that there is no coupling on channel2 as soon as channel2 is turned on.
- Coupling on adjacent channel could be avoided as follows:
- when unused PA5 is configured as INPUT PULL-UP or DOWN.
- PA5 is configured in ANALOG just before it is turned on.
-
- *** DAC Sample and Hold feature ***
- ===================================
- [..]
- For each converter, 2 modes are supported: normal mode and
- "sample and hold" mode (i.e. low power mode).
- In the sample and hold mode, the DAC core converts data, then holds the
- converted voltage on a capacitor. When not converting, the DAC cores and
- buffer are completely turned off between samples and the DAC output is
- tri-stated, therefore reducing the overall power consumption. A new
- stabilization period is needed before each new conversion.
- [..]
- The sample and hold allow setting internal or external voltage @
- low power consumption cost (output value can be at any given rate either
- by CPU or DMA).
- [..]
- The Sample and hold block and registers uses either LSI & run in
- several power modes: run mode, sleep mode & stop mode.
-
- To enable Sample and Hold mode ,enable LSI using HAL_RCC_OscConfig with
- RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters.
-
- Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE
- & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
- DAC_HoldTime & DAC_RefreshTime.
-
-
- *** DAC calibration feature ***
- ===================================
- [..]
- (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
- (++) Calibration aims at correcting some offset of output buffer.
- (++) The DAC uses either factory calibration settings OR user defined
- calibration (trimming) settings (i.e. trimming mode).
- (++) The user defined settings can be figured out using self calibration
- handled by HAL_DACEx_SelfCalibrate.
- (++) HAL_DACEx_SelfCalibrate:
- (+++) Runs automatically the calibration.
- (+++) Enables the user trimming mode
- (+++) Updates a structure with trimming values with fresh calibration
- results.
- The user may store the calibration results for larger
- (ex monitoring the trimming as a function of temperature
- for instance)
-
- *** DAC wave generation feature ***
- ===================================
- [..]
- Both DAC channels can be used to generate:
- (#) Noise wave
- (#) Triangle wave
-
- *** DAC data format ***
- =======================
- [..]
- The DAC data format can be:
- (#) 8-bit right alignment using DAC_ALIGN_8B_R
- (#) 12-bit left alignment using DAC_ALIGN_12B_L
- (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
- *** DAC data value to voltage correspondence ***
- ================================================
- [..]
- The analog output voltage on each DAC channel pin is determined
- by the following equation:
- [..]
- DAC_OUTx = VREF+ * DOR / 4095
- (+) with DOR is the Data Output Register
- [..]
- VREF+ is the input voltage reference (refer to the device datasheet)
- [..]
- e.g. To set DAC_OUT1 to 0.7V:
- (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- *** DMA requests ***
- =====================
- [..]
- A DMA request can be generated when an external trigger (but not
- a software trigger) occurs if DMA requests are enabled using
- HAL_DAC_Start_DMA().
- DMA requests are mapped as following:
- (#) DAC channel1: mapped on DMA_REQUEST_DAC1
- (#) DAC channel2: mapped on DMA_REQUEST_DAC2
- [..]
- -@- For Dual mode and specific signal (Triangle and noise) generation please
- refer to Extended Features Driver description
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) DAC APB clock must be enabled to get write access to DAC
- registers using HAL_DAC_Init()
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
- (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
- (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
-
- *** Calibration mode IO operation ***
- ======================================
- [..]
- (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
- (+) Run the calibration using HAL_DACEx_SelfCalibrate()
- (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
- (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion.
- (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2().
- (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1.
- (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
- HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()and
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1().
- (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
- *** DAC HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DAC HAL driver.
-
- (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
- (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
- (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
- (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
- [..]
- (@) You can refer to the DAC HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DAC DAC
- * @brief DAC driver modules
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DAC_Private_Constants DAC Private Constants
- * @{
- */
-#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
- * @{
- */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
- * @{
- */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DAC.
- (+) De-initialize the DAC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct and initialize the associated handle.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- if(hdac->State == HAL_DAC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdac->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_DAC_MspInit(hdac);
- }
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitialize the DAC peripheral registers to their default reset values.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_DAC_MspDeInit(hdac);
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Set the specified data holding register value for DAC channel.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable DAC and start conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- if(Channel == DAC_CHANNEL_1)
- {
-
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
- }
- }
- else
- {
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
- {
- /* Enable the selected DAC software conversion*/
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
- }
- }
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable DAC and stop conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable DAC and start conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData: The destination peripheral Buffer address.
- * @param Length: The length of data to be transferred from memory to DAC peripheral
- * @param Alignment: Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
- }
- else
- {
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
- /* Enable the selected DAC channel2 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Case of use of channel 2 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
- break;
- default:
- break;
- }
- }
-
- /* Enable the DMA Stream */
- if(Channel == DAC_CHANNEL_1)
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- }
- else
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
-
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable DAC and stop conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Disable the DMA stream */
- /* Channel1 is used */
- if (Channel == DAC_CHANNEL_1)
- {
- /* Disable the DMA stream */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
- }
- else /* Channel2 is used for */
- {
- /* Disable the DMA stream */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
- }
-
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Handle DAC interrupt request
- * This function uses the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
- {
- /* Check underrun flag of DAC channel 1 */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to chanel1 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
- }
- }
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
- {
- /* Check underrun flag of DAC channel 1 */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to channel2 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Error callback */
- HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
- }
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Alignment: Specifies the data alignment.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)hdac->Instance;
- if(Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
- }
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
- }
-
- /* Set the DAC channel selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Get result of conversion.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Return the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Returns the DAC channel data output register value */
- if(Channel == DAC_CHANNEL_1)
- {
- return hdac->Instance->DOR1;
- }
- else
- {
- return hdac->Instance->DOR2;
- }
-}
-/**
- * @brief Configure the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- uint32_t tickstart = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
- assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
- if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
- {
- assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
- }
- assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
- if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
- {
- assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
- assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
- assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
- }
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
- /* Sample on old configuration */
- {
- /* SampleTime */
- if (Channel == DAC_CHANNEL_1)
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
-
- /* SHSR1 can be written when BWST1 equals RESET */
- while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
- {
- /* Update error code */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdac->State = HAL_DAC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
- HAL_Delay(1);
- hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
- }
- else /* Channel 2 */
- {
- /* SHSR2 can be written when BWST2 equals RESET */
-
- while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
- {
- /* Update error code */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdac->State = HAL_DAC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
- HAL_Delay(1);
- hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
- }
- /* HoldTime */
- hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<DAC_UserTrimming == DAC_TRIMMING_USER)
- /* USER TRIMMING */
- {
- /* Get the DAC CCR value */
- tmpreg1 = hdac->Instance->CCR;
- /* Clear trimming value */
- tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
- /* Configure for the selected trimming offset */
- tmpreg2 = sConfig->DAC_TrimmingValue;
- /* Calculate CCR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << Channel;
- /* Write to DAC CCR */
- hdac->Instance->CCR = tmpreg1;
- }
- /* else factory trimming is used (factory setting are available at reset)*/
- /* SW Nothing has nothing to do */
-
- /* Get the DAC MCR value */
- tmpreg1 = hdac->Instance->MCR;
- /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
- tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
- /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
- tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
- /* Calculate MCR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << Channel;
- /* Write to DAC MCR */
- hdac->Instance->MCR = tmpreg1;
-
- /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
- CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
-
- /* Get the DAC CR value */
- tmpreg1 = hdac->Instance->CR;
- /* Clear TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
- /* Configure for the selected DAC channel: trigger */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- tmpreg2 = (sConfig->DAC_Trigger);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << Channel;
-
- /* Write to DAC CR */
- hdac->Instance->CR = tmpreg1;
-
- /* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DAC state.
- (+) Check the DAC Errors.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the DAC handle state
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL state
- */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
- /* Return DAC handle state */
- return hdac->State;
-}
-
-/**
- * @brief Return the DAC error code
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval DAC Error Code
- */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
- return hdac->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup DAC_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DAC_ConvCpltCallbackCh1(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DAC_ErrorCallbackCh1(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c
deleted file mode 100644
index c229dfe..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dac_ex.c
- * @author MCD Application Team
- * @brief Extended DAC HAL module driver.
- * This file provides firmware functions to manage the extended
- * functionalities of DAC peripheral.
- *
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
- Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
- HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
- (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
- (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
- (+) HAL_DACEx_SetUserTrimming to set user trimming value.
- (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
- after reset, user setting if HAL_DACEx_SetUserTrimming have been used
- at least one time after reset).
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DACEx DACEx
- * @brief DAC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
- * @{
- */
-
-/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion with triangle wave generation.
- (+) Start conversion with noise wave generation.
- (+) Start self calibration.
- (+) Set user trimming mode.
- (+) Get result of dual mode conversion.
-
-@endverbatim
- * @{
- */
-
-
-
-/**
- * @brief Enable or disable the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude: Select max triangle amplitude.
- * This parameter can be one of the following values:
- * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
- * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
- * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
- * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
- * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
- * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
- * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
- * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
- * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
- * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
- * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
- * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the triangle wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable or disable the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
- * This parameter can be one of the following values:
- * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the noise wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-
-/**
- * @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Alignment: Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * DAC_ALIGN_8B_R: 8bit right data alignment selected
- * DAC_ALIGN_12B_L: 12bit left data alignment selected
- * DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (Alignment == DAC_ALIGN_8B_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)hdac->Instance;
- tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Conversion complete callback in non-blocking mode for Channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Run the self calibration of one DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig: DAC channel configuration structure.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
- * @retval HAL status
- * @note Calibration runs about 7 ms.
- */
-
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- __IO uint32_t tmp = 0;
- uint32_t trimmingvalue = 0;
- uint32_t delta;
-
- /* store/restore channel configuration structure purpose */
- uint32_t oldmodeconfiguration = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Check the DAC handle allocation */
- /* Check if DAC running */
- if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Store configuration */
- oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
-
- /* Disable the selected DAC channel */
- CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
-
- /* Set mode in MCR for calibration */
- MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
-
- /* Set DAC Channel1 DHR register to the middle value */
-
- tmp = (uint32_t)hdac->Instance;
- if(Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
- }
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
- }
- *(__IO uint32_t *) tmp = 0x0800;
-
- /* Enable the selected DAC channel calibration */
- /* i.e. set DAC_CR_CENx bit */
- SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvalue = 16;
- delta = 8;
- while (delta != 0)
- {
- /* Set candidate trimming */
- MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->SR & (DAC_SR_CAL_FLAG1<>= 1;
- }
-
- /* Still need to check if right calibration is current value or one step below */
- /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
- /* Set candidate trimming */
- MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->SR & (DAC_SR_CAL_FLAG1<Instance->CCR, (DAC_CCR_OTRIM1<Instance->CR), (DAC_CR_CEN1 << Channel));
-
- sConfig->DAC_TrimmingValue = trimmingvalue;
- sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
-
- /* Restore configuration */
- MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Set the trimming mode and trimming value (user trimming mode applied).
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure updated with new DAC trimming value.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param NewTrimmingValue: DAC new trimming value
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
-
- /* Check the DAC handle allocation */
- if(hdac == NULL)
- {
- status = HAL_ERROR;
- }
- else
- {
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Set new trimming */
- MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<DAC_UserTrimming = DAC_TRIMMING_USER;
- sConfig->DAC_TrimmingValue = NewTrimmingValue;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- }
- return status;
-}
-
-
-/**
- * @brief Return the DAC trimming value.
- * @param hdac : DAC handle
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval Trimming value : range: 0->31
- *
- */
-
-uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
- uint32_t trimmingvalue = 0;
-
- /* Check the DAC handle allocation */
- /* And not in Reset state */
- if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Retrieve trimming */
- trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
- }
- return trimmingvalue;
-}
-/**
- * @}
- */
-
-
-/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
- uint32_t tmp = 0;
-
- tmp |= hdac->Instance->DOR1;
-
- tmp |= hdac->Instance->DOR2 << 16;
-
- /* Returns the DAC channel data output register value */
- return tmp;
-}
-
-/**
- * @}
- */
-
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx private functions
- * @brief Extended private functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DACEx_ConvCpltCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-}
-
-/**
- * @brief DMA error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DACEx_ErrorCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c
deleted file mode 100644
index 07887bb..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c
+++ /dev/null
@@ -1,901 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dcmi.c
- * @author MCD Application Team
- * @brief DCMI HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of the Digital Camera Interface (DCMI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The sequence below describes how to use this driver to capture image
- from a camera module connected to the DCMI Interface.
- This sequence does not take into account the configuration of the
- camera module, which should be made before to configure and enable
- the DCMI to capture images.
-
- (#) Program the required configuration through following parameters:
- horizontal and vertical polarity, pixel clock polarity, Capture Rate,
- Synchronization Mode, code of the frame delimiter and data width
- using HAL_DCMI_Init() function.
-
- (#) Configure the selected DMA stream to transfer Data from DCMI DR
- register to the destination memory buffer.
-
- (#) Program the required configuration through following parameters:
- DCMI mode, destination memory Buffer address and the data length
- and enable capture using HAL_DCMI_Start_DMA() function.
-
- (#) Optionally, configure and Enable the CROP feature to select a rectangular
- window from the received image using HAL_DCMI_ConfigCrop()
- and HAL_DCMI_EnableCrop() functions
-
- (#) The capture can be stopped using HAL_DCMI_Stop() function.
-
- (#) To control DCMI state you can use the function HAL_DCMI_GetState().
-
- *** DCMI HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DCMI HAL driver.
-
- (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
- (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
- (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
- (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
- (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
- (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
- (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
-
- [..]
- (@) You can refer to the DCMI HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-/** @defgroup DCMI DCMI
- * @brief DCMI HAL module driver
- * @{
- */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
-
-#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
-#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
-
-#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
-#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
-#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
- * @{
- */
-
-/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DCMI
- (+) De-initialize the DCMI
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the DCMI according to the specified
- * parameters in the DCMI_InitTypeDef and create the associated handle.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
-{
- /* Check the DCMI peripheral state */
- if(hdcmi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check function parameters */
- assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
- assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
- assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
- assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
- assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
- assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
- assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
- assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
-
- assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
- assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
- assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
- assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
-
- if(hdcmi->State == HAL_DCMI_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_DCMI_MspInit(hdcmi);
- }
-
- /* Change the DCMI state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
- /* Configures the HS, VS, DE and PC polarity */
- hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
- DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
- DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
- DCMI_CR_LSM | DCMI_CR_OELS);
-
- hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
- hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
- hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
- hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
- hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
- hdcmi->Init.LineSelectStart);
-
- if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
- {
- hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
- ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
- ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
- ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
-
- }
-
- /* Enable the Line, Vsync, Error and Overrun interrupts */
- __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
-
- /* Update error code */
- hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-
- /* Initialize the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the DCMI peripheral registers to their default reset
- * values.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
-{
- /* DeInit the low level hardware */
- HAL_DCMI_MspDeInit(hdcmi);
-
- /* Update error code */
- hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-
- /* Initialize the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdcmi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DCMI MSP.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdcmi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the DCMI MSP.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdcmi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure destination address and data length and
- Enables DCMI DMA request and enables DCMI capture
- (+) Stop the DCMI capture.
- (+) Handles DCMI interrupt request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables DCMI DMA request and enables DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
- * @param pData: The destination memory Buffer address (LCD Frame buffer).
- * @param Length: The length of capture to be transferred.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
-{
- /* Initialize the second memory address */
- uint32_t SecondMemAddress = 0;
-
- /* Check function parameters */
- assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
-
- /* Process Locked */
- __HAL_LOCK(hdcmi);
-
- /* Lock the DCMI peripheral state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Enable DCMI by setting DCMIEN bit */
- __HAL_DCMI_ENABLE(hdcmi);
-
- /* Configure the DCMI Mode */
- hdcmi->Instance->CR &= ~(DCMI_CR_CM);
- hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
-
- /* Set the DMA memory0 conversion complete callback */
- hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
-
- /* Set the DMA error callback */
- hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
-
- /* Set the dma abort callback */
- hdcmi->DMA_Handle->XferAbortCallback = NULL;
-
- /* Reset transfer counters value */
- hdcmi->XferCount = 0;
- hdcmi->XferTransferNumber = 0;
-
- if(Length <= 0xFFFF)
- {
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
- }
- else /* DCMI_DOUBLE_BUFFER Mode */
- {
- /* Set the DMA memory1 conversion complete callback */
- hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
-
- /* Initialize transfer parameters */
- hdcmi->XferCount = 1;
- hdcmi->XferSize = Length;
- hdcmi->pBuffPtr = pData;
-
- /* Get the number of buffer */
- while(hdcmi->XferSize > 0xFFFF)
- {
- hdcmi->XferSize = (hdcmi->XferSize/2);
- hdcmi->XferCount = hdcmi->XferCount*2;
- }
-
- /* Update DCMI counter and transfer number*/
- hdcmi->XferCount = (hdcmi->XferCount - 2);
- hdcmi->XferTransferNumber = hdcmi->XferCount;
-
- /* Update second memory address */
- SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
-
- /* Start DMA multi buffer transfer */
- HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
- }
-
- /* Enable Capture */
- hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
-
- /* Release Lock */
- __HAL_UNLOCK(hdcmi);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable DCMI DMA request and Disable DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
-{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdcmi);
-
- /* Lock the DCMI peripheral state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Disable Capture */
- hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
-
- /* Check if the DCMI capture effectively disabled */
- do
- {
- if (count-- == 0)
- {
- /* Update error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-
- status = HAL_TIMEOUT;
- break;
- }
- }
- while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
-
- /* Disable the DCMI */
- __HAL_DCMI_DISABLE(hdcmi);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdcmi->DMA_Handle);
-
- /* Update error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
-
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Suspend DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
-{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdcmi);
-
- if(hdcmi->State == HAL_DCMI_STATE_BUSY)
- {
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
-
- /* Disable Capture */
- hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
-
- /* Check if the DCMI capture effectively disabled */
- do
- {
- if (count-- == 0)
- {
- /* Update error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- status = HAL_TIMEOUT;
- break;
- }
- }
- while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Resume DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
-{
- /* Process locked */
- __HAL_LOCK(hdcmi);
-
- if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
- {
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Disable Capture */
- hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handles DCMI interrupt request.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for the DCMI.
- * @retval None
- */
-void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
-{
- uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
-
- /* Synchronization error interrupt management *******************************/
- if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
- {
- /* Clear the Synchronization error flag */
- __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
-
- /* Update error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
-
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_ERROR;
-
- /* Set the synchronization error callback */
- hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
-
- /* Abort the DMA Transfer */
- HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
- }
- /* Overflow interrupt management ********************************************/
- if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
- {
- /* Clear the Overflow flag */
- __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
-
- /* Update error code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
-
- /* Change DCMI state */
- hdcmi->State = HAL_DCMI_STATE_ERROR;
-
- /* Set the overflow callback */
- hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
-
- /* Abort the DMA Transfer */
- HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
- }
- /* Line Interrupt management ************************************************/
- if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
- {
- /* Clear the Line interrupt flag */
- __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
-
- /* Line interrupt Callback */
- HAL_DCMI_LineEventCallback(hdcmi);
- }
- /* VSYNC interrupt management ***********************************************/
- if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
- {
- /* Clear the VSYNC flag */
- __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
-
- /* VSYNC Callback */
- HAL_DCMI_VsyncEventCallback(hdcmi);
- }
- /* FRAME interrupt management ***********************************************/
- if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
- {
- /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
- if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
- {
- /* Disable the Line, Vsync, Error and Overrun interrupts */
- __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
- }
-
- /* Disable the Frame interrupt */
- __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
-
- /* Clear the End of Frame flag */
- __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
-
- /* Frame Callback */
- HAL_DCMI_FrameEventCallback(hdcmi);
- }
-}
-
-/**
- * @brief Error DCMI callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdcmi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Line Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_LineEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief VSYNC Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdcmi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_VsyncEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Frame Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval None
- */
-__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdcmi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DCMI_FrameEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-[..] This section provides functions allowing to:
- (+) Configure the CROP feature.
- (+) Enable/Disable the CROP feature.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the DCMI CROP coordinate.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @param YSize: DCMI Line number
- * @param XSize: DCMI Pixel per line
- * @param X0: DCMI window X offset
- * @param Y0: DCMI window Y offset
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
-{
- /* Process Locked */
- __HAL_LOCK(hdcmi);
-
- /* Lock the DCMI peripheral state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
- assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
- assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
- assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
-
- /* Configure CROP */
- hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
- hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
-
- /* Initialize the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Crop feature.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
-{
- /* Process Locked */
- __HAL_LOCK(hdcmi);
-
- /* Lock the DCMI peripheral state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Disable DCMI Crop feature */
- hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
-
- /* Change the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the Crop feature.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
-{
- /* Process Locked */
- __HAL_LOCK(hdcmi);
-
- /* Lock the DCMI peripheral state */
- hdcmi->State = HAL_DCMI_STATE_BUSY;
-
- /* Enable DCMI Crop feature */
- hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
-
- /* Change the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdcmi);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DCMI state.
- (+) Get the specific DCMI error flag.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DCMI state
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @retval HAL state
- */
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
-{
- return hdcmi->State;
-}
-
-/**
-* @brief Return the DCMI error code
-* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
-* @retval DCMI Error Code
-*/
-uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
-{
- return hdcmi->ErrorCode;
-}
-
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DCMI_Private_Functions DCMI Private Functions
- * @{
- */
- /**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp = 0;
-
- DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(hdcmi->XferCount != 0)
- {
- /* Update memory 0 address location */
- tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT);
- if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
- {
- tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
- hdcmi->XferCount--;
- }
- /* Update memory 1 address location */
- else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0)
- {
- tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
- hdcmi->XferCount--;
- }
- }
- /* Update memory 0 address location */
- else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0)
- {
- ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr;
- }
- /* Update memory 1 address location */
- else if((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0)
- {
- tmp = hdcmi->pBuffPtr;
- ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4*hdcmi->XferSize));
- hdcmi->XferCount = hdcmi->XferTransferNumber;
- }
-
- /* Check if the frame is transferred */
- if(hdcmi->XferCount == hdcmi->XferTransferNumber)
- {
- /* Enable the Frame interrupt */
- __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
-
- /* When snapshot mode, set dcmi state to ready */
- if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
- {
- hdcmi->State= HAL_DCMI_STATE_READY;
- }
- }
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
-{
- DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
- {
- /* Initialize the DCMI state*/
- hdcmi->State = HAL_DCMI_STATE_READY;
-
- /* Set DCMI Error Code */
- hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
- }
-
- /* DCMI error Callback */
- HAL_DCMI_ErrorCallback(hdcmi);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_DCMI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c
deleted file mode 100644
index cc27821..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c
+++ /dev/null
@@ -1,3014 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dfsdm.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Digital Filter for Sigma-Delta Modulators
- * (DFSDM) peripherals:
- * + Initialization and configuration of channels and filters
- * + Regular channels configuration
- * + Injected channels configuration
- * + Regular/Injected Channels DMA Configuration
- * + Interrupts and flags management
- * + Analog watchdog feature
- * + Short-circuit detector feature
- * + Extremes detector feature
- * + Clock absence detector feature
- * + Break generation on analog watchdog or short-circuit event
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- *** Channel initialization ***
- ==============================
- [..]
- (#) User has first to initialize channels (before filters initialization).
- (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
- (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
- (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
- (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (#) Configure the output clock, input, serial interface, analog watchdog,
- offset and data right bit shift parameters for this channel using the
- HAL_DFSDM_ChannelInit() function.
-
- *** Channel clock absence detector ***
- ======================================
- [..]
- (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
- HAL_DFSDM_ChannelCkabStart_IT().
- (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
- absence.
- (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
- clock absence is detected.
- (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
- HAL_DFSDM_ChannelCkabStop_IT().
- (#) Please note that the same mode (polling or interrupt) has to be used
- for all channels because the channels are sharing the same interrupt.
- (#) Please note also that in interrupt mode, if clock absence detector is
- stopped for one channel, interrupt will be disabled for all channels.
-
- *** Channel short circuit detector ***
- ======================================
- [..]
- (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
- or HAL_DFSDM_ChannelScdStart_IT().
- (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
- circuit.
- (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
- short circuit is detected.
- (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
- or HAL_DFSDM_ChannelScdStop_IT().
- (#) Please note that the same mode (polling or interrupt) has to be used
- for all channels because the channels are sharing the same interrupt.
- (#) Please note also that in interrupt mode, if short circuit detector is
- stopped for one channel, interrupt will be disabled for all channels.
-
- *** Channel analog watchdog value ***
- =====================================
- [..]
- (#) Get analog watchdog filter value of a channel using
- HAL_DFSDM_ChannelGetAwdValue().
-
- *** Channel offset value ***
- =====================================
- [..]
- (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
-
- *** Filter initialization ***
- =============================
- [..]
- (#) After channel initialization, user has to init filters.
- (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
- (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- Please note that DFSDMz_FLT0 global interrupt could be already
- enabled if interrupt is used for channel.
- (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
- with DFSDMz filter handle using __HAL_LINKDMA().
- (#) Configure the regular conversion, injected conversion and filter
- parameters for this filter using the HAL_DFSDM_FilterInit() function.
-
- *** Filter regular channel conversion ***
- =========================================
- [..]
- (#) Select regular channel and enable/disable continuous mode using
- HAL_DFSDM_FilterConfigRegChannel().
- (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
- HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
- HAL_DFSDM_FilterRegularMsbStart_DMA().
- (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
- the end of regular conversion.
- (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
- at the end of regular conversion.
- (#) Get value of regular conversion and corresponding channel using
- HAL_DFSDM_FilterGetRegularValue().
- (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
- HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
- half transfer and at the transfer complete. Please note that
- HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
- circular mode.
- (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
- HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
-
- *** Filter injected channels conversion ***
- ===========================================
- [..]
- (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
- (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
- HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
- HAL_DFSDM_FilterInjectedMsbStart_DMA().
- (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
- the end of injected conversion.
- (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
- at the end of injected conversion.
- (#) Get value of injected conversion and corresponding channel using
- HAL_DFSDM_FilterGetInjectedValue().
- (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
- HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
- half transfer and at the transfer complete. Please note that
- HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
- circular mode.
- (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
- HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
-
- *** Filter analog watchdog ***
- ==============================
- [..]
- (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
- (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
- (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
-
- *** Filter extreme detector ***
- ===============================
- [..]
- (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
- (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
- (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
- (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
-
- *** Filter conversion time ***
- ==============================
- [..]
- (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#ifdef HAL_DFSDM_MODULE_ENABLED
-/** @defgroup DFSDM DFSDM
- * @brief DFSDM HAL driver module
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup DFSDM_Private_Define DFSDM Private Define
- * @{
- */
-#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
-#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
-#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
-#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
-#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
-#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
-#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8
-#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
-#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
-#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
-#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
-#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
-#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCDF)
-#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
-#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
-#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
-#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
-#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
-#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
-#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
-#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
-#define DFSDM_MSB_MASK 0xFFFF0000
-#define DFSDM_LSB_MASK 0x0000FFFF
-#define DFSDM_CKAB_TIMEOUT 5000
-#define DFSDM1_CHANNEL_NUMBER 8
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DFSDM_Private_Variables DFSDM Private Variables
- * @{
- */
-__IO uint32_t v_dfsdm1ChannelCounter = 0;
-DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DFSDM_Private_Functions DFSDM Private Functions
- * @{
- */
-static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
-static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
-static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
-static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
-static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
-static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
-static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
-static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
- * @{
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
- * @brief Channel initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Channel initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the DFSDM channel.
- (+) De-initialize the DFSDM channel.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DFSDM channel according to the specified parameters
- * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Check DFSDM Channel handle */
- if(hdfsdm_channel == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
- assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
- assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
- assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
- assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
- assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
- assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
- assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
- assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
- assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
-
- /* Check that channel has not been already initialized */
- if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
- {
- return HAL_ERROR;
- }
-
- /* Call MSP init function */
- HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
-
- /* Update the channel counter */
- v_dfsdm1ChannelCounter++;
-
- /* Configure output serial clock and enable global DFSDM interface only for first channel */
- if(v_dfsdm1ChannelCounter == 1)
- {
- assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
- /* Set the output serial clock source */
- DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
- DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
-
- /* Reset clock divider */
- DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
- if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
- {
- assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
- /* Set the output clock divider */
- DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
- DFSDM_CHCFGR1_CLK_DIV_OFFSET);
- }
-
- /* enable the DFSDM global interface */
- DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
- }
-
- /* Set channel input parameters */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
- DFSDM_CHCFGR1_CHINSEL);
- hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
- hdfsdm_channel->Init.Input.DataPacking |
- hdfsdm_channel->Init.Input.Pins);
-
- /* Set serial interface parameters */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
- hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
- hdfsdm_channel->Init.SerialInterface.SpiClock);
-
- /* Set analog watchdog parameters */
- hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
- hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
- ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
-
- /* Set channel offset and right bit shift */
- hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
- hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
- (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
-
- /* Enable DFSDM channel */
- hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
-
- /* Set DFSDM Channel to ready state */
- hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
-
- /* Store channel handle in DFSDM channel handle table */
- a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-initialize the DFSDM channel.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Check DFSDM Channel handle */
- if(hdfsdm_channel == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check that channel has not been already deinitialized */
- if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Disable the DFSDM channel */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
-
- /* Update the channel counter */
- v_dfsdm1ChannelCounter--;
-
- /* Disable global DFSDM at deinit of last channel */
- if(v_dfsdm1ChannelCounter == 0)
- {
- DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
- }
-
- /* Call MSP deinit function */
- HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
-
- /* Set DFSDM Channel in reset state */
- hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
-
- /* Reset channel handle in DFSDM channel handle table */
- a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval None
- */
-__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_channel);
-
- /* NOTE : This function should not be modified, when the function is needed,
- the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
- */
-}
-
-/**
- * @brief De-initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval None
- */
-__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_channel);
-
- /* NOTE : This function should not be modified, when the function is needed,
- the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
- * @brief Channel operation functions
- *
-@verbatim
- ==============================================================================
- ##### Channel operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Manage clock absence detector feature.
- (+) Manage short circuit detector feature.
- (+) Get analog watchdog value.
- (+) Modify offset value.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to start clock absence detection in polling mode.
- * @note Same mode has to be used for all channels.
- * @note If clock is not available on this channel during 5 seconds,
- * clock absence detection will not be activated and function
- * will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Get channel number from channel instance */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
- {
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
-
- /* Check the Timeout */
- if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
- {
- /* Set timeout status */
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- /* Start clock absence detection */
- hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the clock absence detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
- uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get channel number from channel instance */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait clock absence detection */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear clock absence detection flag */
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
-
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop clock absence detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop clock absence detection */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
-
- /* Clear clock absence flag */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start clock absence detection in interrupt mode.
- * @note Same mode has to be used for all channels.
- * @note If clock is not available on this channel during 5 seconds,
- * clock absence detection will not be activated and function
- * will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Get channel number from channel instance */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
- {
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
-
- /* Check the Timeout */
- if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
- {
- /* Set timeout status */
- status = HAL_TIMEOUT;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- /* Activate clock absence detection interrupt */
- DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
-
- /* Start clock absence detection */
- hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Clock absence detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval None
- */
-__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_channel);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief This function allows to stop clock absence detection in interrupt mode.
- * @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop clock absence detection */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
-
- /* Clear clock absence flag */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
-
- /* Disable clock absence detection interrupt */
- DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start short circuit detection in polling mode.
- * @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
- * This parameter can be a values combination of @ref DFSDM_BreakSignals.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
- uint32_t Threshold,
- uint32_t BreakSignal)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
- assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
- assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Configure threshold and break signals */
- hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
- Threshold);
-
- /* Start short circuit detection */
- hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the short circuit detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
- uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get channel number from channel instance */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait short circuit detection */
- while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear short circuit detection flag */
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
-
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop short circuit detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop short circuit detection */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
-
- /* Clear short circuit detection flag */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start short circuit detection in interrupt mode.
- * @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
- * This parameter can be a values combination of @ref DFSDM_BreakSignals.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
- uint32_t Threshold,
- uint32_t BreakSignal)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
- assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
- assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Activate short circuit detection interrupt */
- DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
-
- /* Configure threshold and break signals */
- hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
- Threshold);
-
- /* Start short circuit detection */
- hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Short circuit detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval None
- */
-__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_channel);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief This function allows to stop short circuit detection in interrupt mode.
- * @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channel;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop short circuit detection */
- hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
-
- /* Clear short circuit detection flag */
- channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
-
- /* Disable short circuit detection interrupt */
- DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get channel analog watchdog value.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval Channel analog watchdog value.
- */
-int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
-}
-
-/**
- * @brief This function allows to modify channel offset value.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Offset : DFSDM channel offset.
- * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
- int32_t Offset)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
- assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
-
- /* Check DFSDM channel state */
- if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Modify channel offset */
- hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
- hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
- * @brief Channel state function
- *
-@verbatim
- ==============================================================================
- ##### Channel state function #####
- ==============================================================================
- [..] This section provides function allowing to:
- (+) Get channel handle state.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to get the current DFSDM channel handle state.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @retval DFSDM channel state.
- */
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
-{
- /* Return DFSDM channel handle state */
- return hdfsdm_channel->State;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
- * @brief Filter initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Filter initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the DFSDM filter.
- (+) De-initialize the DFSDM filter.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DFSDM filter according to the specified parameters
- * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Check DFSDM Channel handle */
- if(hdfsdm_filter == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
- assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
- assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
- assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
- assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
- assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
- assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
- assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
- assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
-
- /* Check parameters compatibility */
- if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
- ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
- (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
- {
- return HAL_ERROR;
- }
-
- /* Initialize DFSDM filter variables with default values */
- hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
- hdfsdm_filter->InjectedChannelsNbr = 1;
- hdfsdm_filter->InjConvRemaining = 1;
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
-
- /* Call MSP init function */
- HAL_DFSDM_FilterMspInit(hdfsdm_filter);
-
- /* Set regular parameters */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
- if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
- }
- else
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
- }
-
- if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
- }
- else
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
- }
-
- /* Set injected parameters */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
- if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
- {
- assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
- assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
- hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
- }
-
- if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
- }
- else
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
- }
-
- if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
- }
- else
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
- }
-
- /* Set filter parameters */
- hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
- hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
- ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
- (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
-
- /* Store regular and injected triggers and injected scan mode*/
- hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
- hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
- hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
- hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
-
- /* Enable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
- /* Set DFSDM filter to ready state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-initializes the DFSDM filter.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Check DFSDM filter handle */
- if(hdfsdm_filter == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Disable the DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
- /* Call MSP deinit function */
- HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
-
- /* Set DFSDM filter in reset state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the function is needed,
- the HAL_DFSDM_FilterMspInit could be implemented in the user file.
- */
-}
-
-/**
- * @brief De-initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the function is needed,
- the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
- * @brief Filter control functions
- *
-@verbatim
- ==============================================================================
- ##### Filter control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Select channel and enable/disable continuous mode for regular conversion.
- (+) Select channels for injected conversion.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to select channel and to enable/disable
- * continuous mode for regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channel for regular conversion.
- * This parameter can be a value of @ref DFSDM_Channel_Selection.
- * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
- * This parameter can be a value of @ref DFSDM_ContinuousMode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel,
- uint32_t ContinuousMode)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
- assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Configure channel and continuous mode for regular conversion */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
- if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
- {
- hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
- DFSDM_FLTCR1_RCONT);
- }
- else
- {
- hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
- }
- /* Store continuous mode information */
- hdfsdm_filter->RegularContMode = ContinuousMode;
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select channels for injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels for injected conversion.
- * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Configure channel for injected conversion */
- hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
- /* Store number of injected channels */
- hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
- /* Update number of injected channels remaining */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
- * @brief Filter operation functions
- *
-@verbatim
- ==============================================================================
- ##### Filter operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular/injected channel.
- (+) Poll for the end of regular/injected conversion.
- (+) Stop conversion of regular/injected channel.
- (+) Start conversion of regular/injected channel and enable interrupt.
- (+) Call the callback functions at the end of regular/injected conversions.
- (+) Stop conversion of regular/injected channel and disable interrupt.
- (+) Start conversion of regular/injected channel and enable DMA transfer.
- (+) Stop conversion of regular/injected channel and disable DMA transfer.
- (+) Start analog watchdog and enable interrupt.
- (+) Call the callback function when analog watchdog occurs.
- (+) Stop analog watchdog and disable interrupt.
- (+) Start extreme detector.
- (+) Stop extreme detector.
- (+) Get result of regular channel conversion.
- (+) Get result of injected channel conversion.
- (+) Get extreme detector maximum and minimum values.
- (+) Get conversion time.
- (+) Handle DFSDM interrupt request.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to start regular conversion in polling mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
- {
- /* Start regular conversion */
- DFSDM_RegConvStart(hdfsdm_filter);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the end of regular conversion.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait end of regular conversion */
- while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
- /* Check if overrun occurs */
- if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
- {
- /* Update error code and call error callback */
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
- HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
-
- /* Clear regular overrun flag */
- hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
- }
- /* Update DFSDM filter state only if not continuous conversion and SW trigger */
- if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
- {
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
- }
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop regular conversion in polling mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- DFSDM_RegConvStop(hdfsdm_filter);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in interrupt mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
- {
- /* Enable interrupts for regular conversions */
- hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
-
- /* Start regular conversion */
- DFSDM_RegConvStart(hdfsdm_filter);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop regular conversion in interrupt mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Disable interrupts for regular conversions */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
-
- /* Stop regular conversion */
- DFSDM_RegConvStop(hdfsdm_filter);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in DMA mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if injected conversion is ongoing.
- * Please note that data on buffer will contain signed regular conversion
- * value on 24 most significant bits and corresponding channel on 3 least
- * significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- int32_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check destination address and length */
- if((pData == NULL) || (Length == 0))
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is enabled for regular conversion */
- else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
- (Length != 1))
- {
- status = HAL_ERROR;
- }
- else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check DFSDM filter state */
- else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
- {
- /* Set callbacks on DMA handler */
- hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
- hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
- hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
- DFSDM_DMARegularHalfConvCplt : NULL;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start regular conversion */
- DFSDM_RegConvStart(hdfsdm_filter);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in DMA mode and to get
- * only the 16 most significant bits of conversion.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if injected conversion is ongoing.
- * Please note that data on buffer will contain signed 16 most significant
- * bits of regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- int16_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check destination address and length */
- if((pData == NULL) || (Length == 0))
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is enabled for regular conversion */
- else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
- (Length != 1))
- {
- status = HAL_ERROR;
- }
- else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check DFSDM filter state */
- else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
- {
- /* Set callbacks on DMA handler */
- hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
- hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
- hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
- DFSDM_DMARegularHalfConvCplt : NULL;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start regular conversion */
- DFSDM_RegConvStart(hdfsdm_filter);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop regular conversion in DMA mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- DFSDM_RegConvStop(hdfsdm_filter);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get regular conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of regular conversion.
- * @retval Regular conversion value
- */
-int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t *Channel)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(Channel != NULL);
-
- /* Get value of data register for regular channel */
- reg = hdfsdm_filter->Instance->FLTRDATAR;
-
- /* Extract channel and regular conversion value */
- *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
- value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
-
- /* return regular conversion value */
- return value;
-}
-
-/**
- * @brief This function allows to start injected conversion in polling mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
- {
- /* Start injected conversion */
- DFSDM_InjConvStart(hdfsdm_filter);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the end of injected conversion.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait end of injected conversions */
- while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
- /* Check if overrun occurs */
- if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
- {
- /* Update error code and call error callback */
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
- HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
-
- /* Clear injected overrun flag */
- hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
- }
-
- /* Update remaining injected conversions */
- hdfsdm_filter->InjConvRemaining--;
- if(hdfsdm_filter->InjConvRemaining == 0)
- {
- /* Update DFSDM filter state only if trigger is software */
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
- }
-
- /* end of injected sequence, reset the value */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
- }
-
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop injected conversion in polling mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop injected conversion */
- DFSDM_InjConvStop(hdfsdm_filter);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start injected conversion in interrupt mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
- {
- /* Enable interrupts for injected conversions */
- hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
-
- /* Start injected conversion */
- DFSDM_InjConvStart(hdfsdm_filter);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop injected conversion in interrupt mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Disable interrupts for injected conversions */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
-
- /* Stop injected conversion */
- DFSDM_InjConvStop(hdfsdm_filter);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start injected conversion in DMA mode.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if regular conversion is ongoing.
- * Please note that data on buffer will contain signed injected conversion
- * value on 24 most significant bits and corresponding channel on 3 least
- * significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- int32_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check destination address and length */
- if((pData == NULL) || (Length == 0))
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is enabled for injected conversion */
- else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
- (Length > hdfsdm_filter->InjConvRemaining))
- {
- status = HAL_ERROR;
- }
- else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check DFSDM filter state */
- else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
- {
- /* Set callbacks on DMA handler */
- hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
- hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
- hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
- DFSDM_DMAInjectedHalfConvCplt : NULL;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start injected conversion */
- DFSDM_InjConvStart(hdfsdm_filter);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start injected conversion in DMA mode and to get
- * only the 16 most significant bits of conversion.
- * @note This function should be called only when DFSDM filter instance is
- * in idle state or if regular conversion is ongoing.
- * Please note that data on buffer will contain signed 16 most significant
- * bits of injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- int16_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check destination address and length */
- if((pData == NULL) || (Length == 0))
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is enabled for injected conversion */
- else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
- (Length > hdfsdm_filter->InjConvRemaining))
- {
- status = HAL_ERROR;
- }
- else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check DFSDM filter state */
- else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
- {
- /* Set callbacks on DMA handler */
- hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
- hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
- hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
- DFSDM_DMAInjectedHalfConvCplt : NULL;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start injected conversion */
- DFSDM_InjConvStart(hdfsdm_filter);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop injected conversion in DMA mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
- {
- /* Set DFSDM filter in error state */
- hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- DFSDM_InjConvStop(hdfsdm_filter);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get injected conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of injected conversion.
- * @retval Injected conversion value
- */
-int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t *Channel)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(Channel != NULL);
-
- /* Get value of data register for injected channel */
- reg = hdfsdm_filter->Instance->FLTJDATAR;
-
- /* Extract channel and injected conversion value */
- *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
- value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
-
- /* return regular conversion value */
- return value;
-}
-
-/**
- * @brief This function allows to start filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param awdParam : DFSDM filter analog watchdog parameters.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- DFSDM_Filter_AwdParamTypeDef *awdParam)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
- assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
- assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
- assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
- assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
- assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Set analog watchdog data source */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
- hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
-
- /* Set thresholds and break signals */
- hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
- hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
- awdParam->HighBreakSignal);
- hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
- hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
- awdParam->LowBreakSignal);
-
- /* Set channels and interrupt for analog watchdog */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
- hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
- DFSDM_FLTCR2_AWDIE);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Reset channels for analog watchdog and deactivate interrupt */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
-
- /* Clear all analog watchdog flags */
- hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
-
- /* Reset thresholds and break signals */
- hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
- hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
-
- /* Reset analog watchdog data source */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels where extreme detector is enabled.
- * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Set channels for extreme detector */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
- hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t reg1;
- __IO uint32_t reg2;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Check DFSDM filter state */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Reset channels for extreme detector */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
-
- /* Clear extreme detector values */
- reg1 = hdfsdm_filter->Instance->FLTEXMAX;
- reg2 = hdfsdm_filter->Instance->FLTEXMIN;
- UNUSED(reg1); /* To avoid GCC warning */
- UNUSED(reg2); /* To avoid GCC warning */
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get extreme detector maximum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
- * @retval Extreme detector maximum value
- * This value is between Min_Data = -8388608 and Max_Data = 8388607.
- */
-int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t *Channel)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(Channel != NULL);
-
- /* Get value of extreme detector maximum register */
- reg = hdfsdm_filter->Instance->FLTEXMAX;
-
- /* Extract channel and extreme detector maximum value */
- *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
- value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
-
- /* return extreme detector maximum value */
- return value;
-}
-
-/**
- * @brief This function allows to get extreme detector minimum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
- * @retval Extreme detector minimum value
- * This value is between Min_Data = -8388608 and Max_Data = 8388607.
- */
-int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t *Channel)
-{
- uint32_t reg = 0;
- int32_t value = 0;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
- assert_param(Channel != NULL);
-
- /* Get value of extreme detector minimum register */
- reg = hdfsdm_filter->Instance->FLTEXMIN;
-
- /* Extract channel and extreme detector minimum value */
- *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
- value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
-
- /* return extreme detector minimum value */
- return value;
-}
-
-/**
- * @brief This function allows to get conversion time value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval Conversion time value
- * @note To get time in second, this value has to be divided by DFSDM clock frequency.
- */
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- uint32_t reg = 0;
- uint32_t value = 0;
-
- /* Check parameters */
- assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
-
- /* Get value of conversion timer register */
- reg = hdfsdm_filter->Instance->FLTCNVTIMR;
-
- /* Extract conversion time value */
- value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
-
- /* return extreme detector minimum value */
- return value;
-}
-
-/**
- * @brief This function handles the DFSDM interrupts.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Check if overrun occurs during regular conversion */
- if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
- {
- /* Clear regular overrun flag */
- hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
-
- /* Update error code */
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
-
- /* Call error callback */
- HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
- }
- /* Check if overrun occurs during injected conversion */
- else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
- {
- /* Clear injected overrun flag */
- hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
-
- /* Update error code */
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
-
- /* Call error callback */
- HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
- }
- /* Check if end of regular conversion */
- else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
- {
- /* Call regular conversion complete callback */
- HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
-
- /* End of conversion if mode is not continuous and software trigger */
- if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
- {
- /* Disable interrupts for regular conversions */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
-
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
- }
- }
- /* Check if end of injected conversion */
- else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
- {
- /* Call injected conversion complete callback */
- HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
-
- /* Update remaining injected conversions */
- hdfsdm_filter->InjConvRemaining--;
- if(hdfsdm_filter->InjConvRemaining == 0)
- {
- /* End of conversion if trigger is software */
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- /* Disable interrupts for injected conversions */
- hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
-
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
- }
- /* end of injected sequence, reset the value */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
- }
- }
- /* Check if analog watchdog occurs */
- else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
- {
- uint32_t reg = 0;
- uint32_t threshold = 0;
- uint32_t channel = 0;
-
- /* Get channel and threshold */
- reg = hdfsdm_filter->Instance->FLTAWSR;
- threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
- if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
- {
- reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
- }
- while((reg & 1) == 0)
- {
- channel++;
- reg = reg >> 1;
- }
- /* Clear analog watchdog flag */
- hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
- (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
- (1 << channel);
-
- /* Call analog watchdog callback */
- HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
- }
- /* Check if clock absence occurs */
- else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
- ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
- {
- uint32_t reg = 0;
- uint32_t channel = 0;
-
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
-
- while(channel < DFSDM1_CHANNEL_NUMBER)
- {
- /* Check if flag is set and corresponding channel is enabled */
- if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
- {
- /* Check clock absence has been enabled for this channel */
- if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
- {
- /* Clear clock absence flag */
- hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
-
- /* Call clock absence callback */
- HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
- }
- }
- channel++;
- reg = reg >> 1;
- }
- }
- /* Check if short circuit detection occurs */
- else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
- ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
- ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
- {
- uint32_t reg = 0;
- uint32_t channel = 0;
-
- /* Get channel */
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
- while((reg & 1) == 0)
- {
- channel++;
- reg = reg >> 1;
- }
-
- /* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
-
- /* Call short circuit detection callback */
- HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
- }
-}
-
-/**
- * @brief Regular conversion complete callback.
- * @note In interrupt mode, user has to read conversion value in this function
- * using HAL_DFSDM_FilterGetRegularValue.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Half regular conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Injected conversion complete callback.
- * @note In interrupt mode, user has to read conversion value in this function
- * using HAL_DFSDM_FilterGetInjectedValue.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Half injected conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Filter analog watchdog callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
- * @param Threshold : Low or high threshold has been reached.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel, uint32_t Threshold)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
- UNUSED(Channel);
- UNUSED(Threshold);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Error callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdfsdm_filter);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
- * @brief Filter state functions
- *
-@verbatim
- ==============================================================================
- ##### Filter state functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Get the DFSDM filter state.
- (+) Get the DFSDM filter error.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to get the current DFSDM filter handle state.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval DFSDM filter state.
- */
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- /* Return DFSDM filter handle state */
- return hdfsdm_filter->State;
-}
-
-/**
- * @brief This function allows to get the current DFSDM filter error.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval DFSDM filter error code.
- */
-uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
-{
- return hdfsdm_filter->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
- * @{
- */
-
-/**
- * @brief DMA half transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get DFSDM filter handle */
- DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call regular half conversion complete callback */
- HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
-}
-
-/**
- * @brief DMA transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get DFSDM filter handle */
- DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call regular conversion complete callback */
- HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
-}
-
-/**
- * @brief DMA half transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get DFSDM filter handle */
- DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call injected half conversion complete callback */
- HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
-}
-
-/**
- * @brief DMA transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get DFSDM filter handle */
- DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call injected conversion complete callback */
- HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
-}
-
-/**
- * @brief DMA error callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Get DFSDM filter handle */
- DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Update error code */
- hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
-
- /* Call error callback */
- HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
-}
-
-/**
- * @brief This function allows to get the number of injected channels.
- * @param Channels : bitfield of injected channels.
- * @retval Number of injected channels.
- */
-static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
-{
- uint32_t nbChannels = 0;
- uint32_t tmp;
-
- /* Get the number of channels from bitfield */
- tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
- while(tmp != 0)
- {
- if((tmp & 1) != 0)
- {
- nbChannels++;
- }
- tmp = (uint32_t) (tmp >> 1);
- }
- return nbChannels;
-}
-
-/**
- * @brief This function allows to get the channel number from channel instance.
- * @param Instance : DFSDM channel instance.
- * @retval Channel number.
- */
-static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
-{
- uint32_t channel = 0xFF;
-
- /* Get channel from instance */
- if(Instance == DFSDM1_Channel0)
- {
- channel = 0;
- }
- else if(Instance == DFSDM1_Channel1)
- {
- channel = 1;
- }
- else if(Instance == DFSDM1_Channel2)
- {
- channel = 2;
- }
- else if(Instance == DFSDM1_Channel3)
- {
- channel = 3;
- }
- else if(Instance == DFSDM1_Channel4)
- {
- channel = 4;
- }
- else if(Instance == DFSDM1_Channel5)
- {
- channel = 5;
- }
- else if(Instance == DFSDM1_Channel6)
- {
- channel = 6;
- }
- else if(Instance == DFSDM1_Channel7)
- {
- channel = 7;
- }
-
- return channel;
-}
-
-/**
- * @brief This function allows to really start regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
-{
- /* Check regular trigger */
- if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- /* Software start of regular conversion */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
- }
- else /* synchronous trigger */
- {
- /* Disable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
- /* Set RSYNC bit in DFSDM_FLTCR1 register */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
-
- /* Enable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
- /* If injected conversion was in progress, restart it */
- if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
- {
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
- }
- /* Update remaining injected conversions */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
- }
- }
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
- HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
-}
-
-/**
- * @brief This function allows to really stop regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
-{
- /* Disable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
- /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
- if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
- }
-
- /* Enable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
- /* If injected conversion was in progress, restart it */
- if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
- {
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
- }
- /* Update remaining injected conversions */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
- }
-
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
-}
-
-/**
- * @brief This function allows to really start injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
-{
- /* Check injected trigger */
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
- {
- /* Software start of injected conversion */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
- }
- else /* external or synchronous trigger */
- {
- /* Disable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
- {
- /* Set JSYNC bit in DFSDM_FLTCR1 register */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
- }
- else /* external trigger */
- {
- /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
- hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
- }
-
- /* Enable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
- /* If regular conversion was in progress, restart it */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
- }
- }
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
- HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
-}
-
-/**
- * @brief This function allows to really stop injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @retval None
- */
-static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
-{
- /* Disable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
-
- /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
- if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
- {
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
- }
- else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
- {
- /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
- hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
- }
-
- /* Enable DFSDM filter */
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
-
- /* If regular conversion was in progress, restart it */
- if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
- {
- hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
- }
-
- /* Update remaining injected conversions */
- hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1;
-
- /* Update DFSDM filter state */
- hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
-}
-
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
deleted file mode 100644
index 080e2b5..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
+++ /dev/null
@@ -1,1937 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma.c
- * @author MCD Application Team
- * @brief DMA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Stream
- (except for internal SRAM/FLASH memories: no initialization is
- necessary) please refer to Reference manual for connection between peripherals
- and DMA requests .
-
- (#) For a given Stream, program the required configuration through the following parameters:
- Transfer Direction, Source and Destination data formats,
- Circular, Normal or peripheral flow control mode, Stream Priority level,
- Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
- Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred. In this
- case the DMA interrupt is configured
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of DMA handle structure).
- [..]
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
- detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
- -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
- possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
- Half-Word data size for the peripheral to access its data register and set Word data size
- for the Memory to gain in access time. Each two half words will be packed and written in
- a single access to a Word in the Memory).
-
- -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
- and Destination. In this case the Peripheral Data Size will be applied to both Source
- and Destination.
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DMA HAL driver.
-
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
- (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register */
- __IO uint32_t Reserved0;
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
-} DMA_Base_Registers;
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Constants
- * @{
- */
- #define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
-
-/*D2 DMA to D3 DMA conversion*/
-#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
-#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */
-#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */
-
-#define D2_TO_D3_DMA_DIRECTION(__D2_DMA_DIRECTION__) (((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
- ((__D2_DMA_DIRECTION__)== DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
- BDMA_PERIPH_TO_MEMORY)
-
-#define D2_TO_D3_DMA_PERIPHERAL_INC(__D2_PERIPHERAL_INC__) ((__D2_PERIPHERAL_INC__) >> 3U)
-#define D2_TO_D3_DMA_MEMORY_INC(__D2_MEMORY_INC__) ((__D2_MEMORY_INC__) >> 3U)
-
-#define D2_TO_D3_DMA_PDATA_SIZE(__D2_PDATA_SIZE__) ((__D2_PDATA_SIZE__) >> 3U)
-#define D2_TO_D3_DMA_MDATA_SIZE(__D2_MDATA_SIZE__) ((__D2_MDATA_SIZE__) >> 3U)
-
-/*BDMA doesn't support Peripheral flow control mode , force to normal in this case */
-#define D2_TO_D3_DMA_MODE(__D2_MODE__) (((__D2_MODE__) >> 3U) & BDMA_CCR_CIRC)
-
-#define D2_TO_D3_DMA_PRIORITY(__D2_PRIORITY__) ((__D2_PRIORITY__) >> 4U)
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Stream source
- and destination incrementation and data sizes, transfer direction,
- circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
- The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and create the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t registerValue = 0U;
- uint32_t tickstart = HAL_GetTick();
- DMA_Base_Registers *regs = NULL;
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream , D2 domain*/
- {
-
- assert_param(IS_DMA_D2_REQUEST(hdma->Init.Request));
- assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
- /* Check the memory burst, peripheral burst and FIFO threshold parameters only
- when FIFO mode is enabled */
- if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
- {
- assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
- assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
- assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
- }
-
- /* Allocate lock resource */
- __HAL_UNLOCK(hdma);
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Check if the DMA Stream is effectively disabled */
- while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Get the CR register value */
- registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR;
-
- /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
- registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
- DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
- DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
- DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
-
- /* Prepare the DMA Stream configuration */
- registerValue |= hdma->Init.Direction |
- hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
- if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
- {
- /* Get memory burst and peripheral burst */
- registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
- }
-
- /* Write to DMA Stream CR register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
-
- /* Get the FCR register value */
- registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;
-
- /* Clear Direct mode and FIFO threshold bits */
- registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
- /* Prepare the DMA Stream FIFO configuration */
- registerValue |= hdma->Init.FIFOMode;
-
- /* the FIFO threshold is not used when the FIFO mode is disabled */
- if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
- {
- /* Get the FIFO threshold */
- registerValue |= hdma->Init.FIFOThreshold;
-
- /* Check compatibility between FIFO threshold level and size of the memory burst */
- /* for INCR4, INCR8, INCR16 */
- if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
- {
- if (DMA_CheckFifoParam(hdma) != HAL_OK)
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Write to DMA Stream FCR */
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue;
-
- /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
- DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
- regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-
- /* Clear all interrupt flags */
- regs->IFCR = 0x3FU << hdma->StreamIndex;
- }
- else if(IS_D3_DMA_INSTANCE(hdma) != RESET) /*Init.Request));
-
- /* Allocate lock resource */
- __HAL_UNLOCK(hdma);
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
- registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \
- BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \
- BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
-
- /* Prepare the DMA Channel configuration */
- registerValue |= D2_TO_D3_DMA_DIRECTION(hdma->Init.Direction) |
- D2_TO_D3_DMA_PERIPHERAL_INC(hdma->Init.PeriphInc) |
- D2_TO_D3_DMA_MEMORY_INC(hdma->Init.MemInc) |
- D2_TO_D3_DMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
- D2_TO_D3_DMA_MDATA_SIZE(hdma->Init.MemDataAlignment) |
- D2_TO_D3_DMA_MODE(hdma->Init.Mode) |
- D2_TO_D3_DMA_PRIORITY(hdma->Init.Priority);
-
- /* Write to DMA Channel CR register */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
-
- /* calculation of the channel index */
- hdma->StreamIndex = (((uint32_t)hdma->Instance - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
-
- }
- else
- {
- hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
- hdma->State = HAL_DMA_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
- */
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
- {
- /* if memory to memory force the request to 0*/
- hdma->Init.Request = DMA_REQUEST_MEM2MEM;
- }
-
-
- /* Set peripheral request to DMAMUX channel */
- hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Initialize parameters for DMAMUX request generator :
- if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
- */
-
- if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
- {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
- else
- {
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
- }
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the DMA peripheral
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
- DMA_Base_Registers *regs = NULL;
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the DMA peripheral state */
- if(hdma->State == HAL_DMA_STATE_BUSY)
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- return HAL_ERROR;
- }
-
- /* Disable the selected DMA Streamx */
- __HAL_DMA_DISABLE(hdma);
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream , D2 domain*/
- {
- /* Reset DMA Streamx control register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U;
-
- /* Reset DMA Streamx number of data to transfer register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U;
-
- /* Reset DMA Streamx peripheral address register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U;
-
- /* Reset DMA Streamx memory 0 address register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U;
-
- /* Reset DMA Streamx memory 1 address register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U;
-
- /* Reset DMA Streamx FIFO control register */
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U;
-
- /* Get DMA steam Base Address */
- regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-
- /* Clear all interrupt flags at correct offset within the register */
- regs->IFCR = 0x3FU << hdma->StreamIndex;
- }
- else if(IS_D3_DMA_INSTANCE(hdma) != RESET) /*D3 domain BDMA*/
- {
-
- /* Reset DMA Channel control register */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U;
-
- /* Reset DMA Channel Number of Data to Transfer register */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
-
- /* Reset DMA Channel peripheral address register */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U;
-
- /* Reset DMA Channel memory address register */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = 0U;
-
- /* Clear all flags */
- BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
- }
-
- /* Initialize parameters for DMAMUX channel :
- DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
- DMA_CalcDMAMUXChannelBaseAndMask(hdma);
-
- if(hdma->DMAmuxChannel != 0U)
- {
- /* Resett he DMAMUX channel that corresponds to the DMA stream */
- hdma->DMAmuxChannel->CCR = 0U;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- }
-
- if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
- {
- /* Initialize parameters for DMAMUX request generator :
- DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
- */
- DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
-
- /* Reset the DMAMUX request generator register*/
- hdma->DMAmuxRequestGen->RGCR = 0U;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
- hdma->DMAmuxRequestGenStatusMask = 0U;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Register and Unregister DMA callbacks
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- status = HAL_ERROR;
- }
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- /* Enable Common interrupts*/
- MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /*Enable Half Transfer IT if corresponding Callback is set*/
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
- }
- }
- else /* D3 Domain BDMA */
- {
- /* Enable Common interrupts*/
- MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /*Enable Half Transfer IT if corresponding Callback is set*/
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
- }
- }
-
- /* Check if DMAMUX Synchronization is enabled*/
- if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
- {
- /* Enable DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
- }
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
- /* enable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
-
- }
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Aborts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- *
- * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
- * effectively disabled is added. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- /* calculate DMA base and stream number */
- DMA_Base_Registers *regs = NULL;
- __IO uint32_t *enableRegister = NULL;
-
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the DMA peripheral state */
- if(hdma->State != HAL_DMA_STATE_BUSY)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- else
- {
- /* Disable all the transfer interrupts */
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
- {
- /* Disable DMA All Interrupts */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
-
- regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
- enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR));
- }
- else /* D3 domain BDMA*/
- {
- /* Disable DMA All Interrupts */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
-
- enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));
- }
-
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
-
- /* Check if the DMA Stream is effectively disabled */
- while(((*enableRegister) & DMA_SxCR_EN) != RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Clear all interrupt flags at correct offset within the register */
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
- {
- regs->IFCR = 0x3FU << hdma->StreamIndex;
- }
- else /* D3 domain BDMA*/
- {
- BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
- }
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hdma->State != HAL_DMA_STATE_BUSY)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- return HAL_ERROR;
- }
- else
- {
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2*/
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- }
- else /* D3 Domain BDMA */
- {
- /* Disable DMA All Interrupts */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* disable the DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear all flags */
- BDMA->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex));
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
- /* disable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param CompleteLevel: Specifies the DMA level complete.
- * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
- * This model could be used for debug purpose.
- * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t cpltlevel_mask = 0U;
- uint32_t tickstart = HAL_GetTick();
-
- /* IT status register */
- __IO uint32_t *isr_reg = NULL;
- /* IT clear flag register */
- __IO uint32_t *ifcr_reg = NULL;
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* No transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- /* Polling mode not supported in circular mode and double buffering mode */
- if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != RESET)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Transfer Complete flag */
- cpltlevel_mask = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
- }
- else
- {
- /* Half Transfer Complete flag */
- cpltlevel_mask = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
- }
-
- isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
- ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
- }
- else /* D3 Domain BDMA */
- {
- /* Polling mode not supported in circular mode */
- if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != RESET)
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Transfer Complete flag */
- cpltlevel_mask = BDMA_FLAG_TC0 << hdma->StreamIndex;
- }
- else
- {
- /* Half Transfer Complete flag */
- cpltlevel_mask = BDMA_FLAG_HT0 << hdma->StreamIndex;
- }
-
- isr_reg = &(BDMA->ISR);
- ifcr_reg = &(BDMA->IFCR);
- }
-
- while((((*isr_reg) & cpltlevel_mask) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
- {
- /* Check for the Timeout (Not applicable in circular mode)*/
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- HAL_DMA_Abort(hdma); /* if timeout then abort the current transfer */
-
- /*
- Note that the Abort function will
- - Clear the transfer error flags
- - Unlock
- - Set the State
- */
-
- return HAL_ERROR;
- }
- }
-
- /*Check for DMAMUX Request generator (if used) overrun status */
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
- if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
- {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
- }
- }
-
- /* Check for DMAMUX Synchronization overrun */
- if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
- {
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
- }
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
- /* Clear the transfer error flag */
- (*ifcr_reg) = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
- }
-
- if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
- /* Clear the FIFO error flag */
- (*ifcr_reg) = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
- }
-
- if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
- /* Clear the Direct Mode error flag */
- (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
- }
- }
- else /* D3 Domain BDMA */
- {
- if((RESET != (BDMA->ISR & (BDMA_FLAG_TE0 << hdma->StreamIndex))))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- BDMA->IFCR |= ((BDMA_ISR_GIF0) << (hdma->StreamIndex));
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
- }
- }
- }
-
-
- if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
- {
- if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
- {
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- HAL_DMA_Abort(hdma);
-
- /*
- Note that the Abort function will
- - Disable the DMA
- - Clear the transfer error flags
- - Unlock
- - Set the State
- */
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
- }
-
- return HAL_ERROR;
- }
- }
-
- /* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Clear the half transfer and transfer complete flags */
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
- }
- else /* D3 Domain BDMA */
- {
- BDMA->IFCR |= (BDMA_FLAG_TC0 << hdma->StreamIndex);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- hdma->State = HAL_DMA_STATE_READY;
- }
- else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
- {
- /* Clear the half transfer and transfer complete flags */
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
- }
- else /* D3 Domain BDMA */
- {
- BDMA->IFCR |= (BDMA_FLAG_HT0 << hdma->StreamIndex);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Handles DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmpisr = 0U;
- __IO uint32_t *ccr_reg = NULL;
- __IO uint32_t count = 0U;
- uint32_t timeout = SystemCoreClock / 9600U;
-
- /* calculate DMA base and stream number */
- DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
- tmpisr = regs->ISR;
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /*D2 domain DMA : DMA1 or DMA2*/
- {
- /* Transfer Error Interrupt management ***************************************/
- if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
- {
- /* Disable the transfer error interrupt */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE);
-
- /* Clear the transfer error flag */
- regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_TE;
- }
- }
- /* FIFO Error Interrupt management ******************************************/
- if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
- {
- /* Clear the FIFO error flag */
- regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_FE;
- }
- }
- /* Direct Mode Error Interrupt management ***********************************/
- if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
- {
- /* Clear the direct mode error flag */
- regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_DME;
- }
- }
- /* Half Transfer Complete Interrupt management ******************************/
- if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
- {
- /* Clear the half transfer complete flag */
- regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
- /* Multi_Buffering mode enabled */
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
- {
- /* Current memory buffer used is Memory 0 */
- if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == RESET)
- {
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
- /* Current memory buffer used is Memory 1 */
- else
- {
- if(hdma->XferM1HalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferM1HalfCpltCallback(hdma);
- }
- }
- }
- else
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == RESET)
- {
- /* Disable the half transfer interrupt */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
- }
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
- }
- }
- /* Transfer Complete Interrupt management ***********************************/
- if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
- {
- /* Clear the transfer complete flag */
- regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-
- if(HAL_DMA_STATE_ABORT == hdma->State)
- {
- /* Disable all the transfer interrupts */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
-
- if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
- {
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
- }
-
- /* Clear all interrupt flags at correct offset within the register */
- regs->IFCR = 0x3FU << hdma->StreamIndex;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- return;
- }
-
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
- {
- /* Current memory buffer used is Memory 0 */
- if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == RESET)
- {
- if(hdma->XferM1CpltCallback != NULL)
- {
- /* Transfer complete Callback for memory1 */
- hdma->XferM1CpltCallback(hdma);
- }
- }
- /* Current memory buffer used is Memory 1 */
- else
- {
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete Callback for memory0 */
- hdma->XferCpltCallback(hdma);
- }
- }
- }
- /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
- else
- {
- if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == RESET)
- {
- /* Disable the transfer complete interrupt */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
- }
- }
-
- /* manage error case */
- if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
- {
- if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
- {
- hdma->State = HAL_DMA_STATE_ABORT;
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
-
- do
- {
- if (++count > timeout)
- {
- break;
- }
- }
- while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != RESET)
- {
- /* Change the DMA state to error if DMA disable fails */
- hdma->State = HAL_DMA_STATE_ERROR;
- }
- else
- {
- /* Change the DMA state to Ready if DMA disable success */
- hdma->State = HAL_DMA_STATE_READY;
- }
- }
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
- else if(IS_D3_DMA_INSTANCE(hdma) != RESET) /*D3 domain BDMA */
- {
- ccr_reg = &(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR);
-
- /* Half Transfer Complete Interrupt management ******************************/
- if ((RESET != (BDMA->ISR & (BDMA_FLAG_HT0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_HTIE)))
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if(((*ccr_reg) & BDMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- (*ccr_reg) &= ~BDMA_CCR_HTIE;
- }
- /* Clear the half transfer complete flag */
- BDMA->IFCR |= (BDMA_ISR_HTIF0 << hdma->StreamIndex);
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* but in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
-
- /* Transfer Complete Interrupt management ***********************************/
- else if ((RESET != (BDMA->ISR & (BDMA_FLAG_TC0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_TCIE)))
- {
- if(((*ccr_reg) & BDMA_CCR_CIRC) == 0U)
- {
- /* Disable TE & TC */
- (*ccr_reg) &= ~(BDMA_CCR_TEIE | BDMA_CCR_TCIE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
- /* Clear the transfer complete flag */
- BDMA->IFCR |= (BDMA_ISR_TCIF0 << hdma->StreamIndex);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
-
- /* Transfer Error Interrupt management **************************************/
- else if (( RESET != (BDMA->ISR & (BDMA_FLAG_TE0 << hdma->StreamIndex))) && (RESET != ((*ccr_reg) & BDMA_CCR_TEIE)))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Disable ALL DMA IT */
- (*ccr_reg) &= ~(BDMA_CCR_TEIE | BDMA_CCR_TCIE | BDMA_CCR_HTIE);
-
- /* Clear all flags */
- BDMA->IFCR |= (BDMA_ISR_GIF0 << hdma->StreamIndex);
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-}
-
-/**
- * @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
- * a DMA_HandleTypeDef structure as parameter.
- * @param pCallback: pointer to private callbacsk function which has pointer to
- * a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
-{
-
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_M1CPLT_CB_ID:
- hdma->XferM1CpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
- hdma->XferM1HalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the DMA peripheral handle */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_M1CPLT_CB_ID:
- hdma->XferM1CpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
- hdma->XferM1HalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferM1CpltCallback = NULL;
- hdma->XferM1HalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3
- *
-@verbatim
- ===============================================================================
- ##### State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the DMA state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
- return hdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* calculate DMA base and stream number */
- DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- if(IS_D2_DMA_INSTANCE(hdma) != RESET) /* D2 Domain DMA : DMA1 or DMA2 */
- {
- /* Clear all interrupt flags at correct offset within the register */
- regs->IFCR = 0x3FU << hdma->StreamIndex;
-
- /* Clear DBM bit */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
- /* Configure DMA Stream data length */
- ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
-
- /* Peripheral to Memory */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
-
- /* Configure DMA Stream source address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
- }
- /* Memory to Peripheral */
- else
- {
- /* Configure DMA Stream source address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
-
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
- }
- }
- else if(IS_D3_DMA_INSTANCE(hdma)) /* D3 Domain BDMA */
- {
- /* Clear all flags */
- BDMA->IFCR |= (BDMA_ISR_GIF0 << hdma->StreamIndex);
-
- /* Configure DMA Channel data length */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
-
- /* Peripheral to Memory */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Channel destination address */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = SrcAddress;
- }
- /* Memory to Peripheral */
- else
- {
- /* Configure DMA Channel source address */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- ((BDMA_Channel_TypeDef *)hdma->Instance)->CMAR = DstAddress;
- }
- }
-}
-
-/**
- * @brief Returns the DMA Stream base address depending on stream number
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval Stream base address
- */
-static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
-{
- uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
-
- /* lookup table for necessary bitshift of flags within status registers */
- static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
- hdma->StreamIndex = flagBitshiftOffset[stream_number];
-
- if (stream_number > 3U)
- {
- /* return pointer to HISR and HIFCR */
- hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
- }
- else
- {
- /* return pointer to LISR and LIFCR */
- hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
- }
-
- return hdma->StreamBaseAddress;
-}
-
-/**
- * @brief Check compatibility between FIFO threshold level and size of the memory burst
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Memory Data size equal to Byte */
- if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
- {
- switch (hdma->Init.FIFOThreshold)
- {
- case DMA_FIFO_THRESHOLD_1QUARTERFULL:
- case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-
- if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
- {
- status = HAL_ERROR;
- }
- break;
-
- case DMA_FIFO_THRESHOLD_HALFFULL:
- if (hdma->Init.MemBurst == DMA_MBURST_INC16)
- {
- status = HAL_ERROR;
- }
- break;
-
- case DMA_FIFO_THRESHOLD_FULL:
- break;
-
- default:
- break;
- }
- }
-
- /* Memory Data size equal to Half-Word */
- else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- switch (hdma->Init.FIFOThreshold)
- {
- case DMA_FIFO_THRESHOLD_1QUARTERFULL:
- case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
- status = HAL_ERROR;
- break;
-
- case DMA_FIFO_THRESHOLD_HALFFULL:
- if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
- {
- status = HAL_ERROR;
- }
- break;
-
- case DMA_FIFO_THRESHOLD_FULL:
- if (hdma->Init.MemBurst == DMA_MBURST_INC16)
- {
- status = HAL_ERROR;
- }
- break;
-
- default:
- break;
- }
- }
-
- /* Memory Data size equal to Word */
- else
- {
- switch (hdma->Init.FIFOThreshold)
- {
- case DMA_FIFO_THRESHOLD_1QUARTERFULL:
- case DMA_FIFO_THRESHOLD_HALFFULL:
- case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
- status = HAL_ERROR;
- break;
-
- case DMA_FIFO_THRESHOLD_FULL:
- if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
- {
- status = HAL_ERROR;
- }
- break;
-
- default:
- break;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
-{
- uint32_t stream_number = 0U;
- uint32_t stream_baseaddress = (uint32_t)hdma->Instance;
-
- if((stream_baseaddress <= ((uint32_t)BDMA_Channel7) ) && \
- (stream_baseaddress >= ((uint32_t)BDMA_Channel0)))
- {
- /*BDMA Channels are connected to DMAMUX2 channels*/
- stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
- hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
- hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
- hdma->DMAmuxChannelStatusMask = 1U << stream_number;
- }
- else
- {
- /*DMA1/DMA2 Streams are connected to DMAMUX1 channels*/
- stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
-
- if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
- (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
- {
- stream_number += 8U;
- }
- hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
- hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
- hdma->DMAmuxChannelStatusMask = 1U << stream_number;
- }
-}
-
-/**
- * @brief Updates the DMA handle with the DMAMUX request generator params
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
-{
- uint32_t stream_baseaddress = (uint32_t)hdma->Instance;
- uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
-
- if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
- {
- if((stream_baseaddress <= ((uint32_t)BDMA_Channel7) ) && \
- (stream_baseaddress >= ((uint32_t)BDMA_Channel0)))
- {
- /*BDMA Channels are connected to DMAMUX2 request generator blocks*/
- hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
-
- hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
- }
- else
- {
- /*DMA1 and DMA2 Streams use DMAMUX1 request generator blocks*/
- hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
-
- hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
- }
-
- hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U);
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c
deleted file mode 100644
index 2977971..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c
+++ /dev/null
@@ -1,1750 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma2d.c
- * @author MCD Application Team
- * @brief DMA2D HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the DMA2D peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Program the required configuration through the following parameters:
- the transfer mode, the output color mode and the output offset using
- HAL_DMA2D_Init() function.
-
- (#) Program the required configuration through the following parameters:
- the input color mode, the input color, the input alpha value, the alpha mode,
- the red/blue swap mode, the inverted alpha mode and the input offset using
- HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (#) Configure pdata parameter (explained hereafter), destination and data length
- and enable the transfer using HAL_DMA2D_Start().
- (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
- user can specify the value of timeout according to his end application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (#) Configure pdata parameter, destination and data length and enable
- the transfer using HAL_DMA2D_Start_IT().
- (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
- (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback (member
- of DMA2D handle structure).
- (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
- XferErrorCallback.
-
- -@- In Register-to-Memory transfer mode, pdata parameter is the register
- color, in Memory-to-memory or Memory-to-Memory with pixel format
- conversion pdata is the source address.
-
- -@- Configure the foreground source address, the background source address,
- the destination and data length then Enable the transfer using
- HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
- in interrupt mode.
-
- -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
- are used if the memory to memory with blending transfer mode is selected.
-
- (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
- mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
-
- (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
-
- (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
- consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
- and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
- HAL_DMA2D_DisableDeadTime().
-
- (#) The transfer can be suspended, resumed and aborted using the following
- functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
-
- (#) The CLUT loading can be suspended, resumed and aborted using the following
- functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
- HAL_DMA2D_CLUTLoading_Abort().
-
- (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
-
- (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
-
- *** DMA2D HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DMA2D HAL driver :
-
- (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
- (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
- (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
- (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
- (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
- (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
-
- [..]
- (@) You can refer to the DMA2D HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA2D DMA2D
- * @brief DMA2D HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
- * @{
- */
-
-/** @defgroup DMA2D_TimeOut DMA2D Time Out
- * @{
- */
-#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
-#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Shifts DMA2D Shifts
- * @{
- */
-#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
-#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
-
-#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
-#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
-
-#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
-#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
-#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
-
-#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
-#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
-#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
-
-#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
-
-#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
-#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
-
-#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
-#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
-
-#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
-
-#define DMA2D_POSITION_FGPFCCR_CSS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS) /*!< Required left shift to set foreground Chroma sub-sampling */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup DMA2D_Private_Functions_Prototypes
- * @{
- */
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
- * @{
- */
-
-/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DMA2D
- (+) De-initialize the DMA2D
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA2D according to the specified
- * parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
- assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
- assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
- assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
-
- if(hdma2d->State == HAL_DMA2D_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdma2d->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_DMA2D_MspInit(hdma2d);
- }
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* DMA2D CR register configuration -------------------------------------------*/
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
-
- /* DMA2D OPFCCR register configuration ---------------------------------------*/
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
-
- /* DMA2D OOR register configuration ------------------------------------------*/
- MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
-
- /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
-
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
-
-
- /* Update error code */
- hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
-
- /* Initialize the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the DMA2D peripheral registers to their default reset
- * values.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval None
- */
-
-HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
-{
-
- /* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Abort DMA2D transfer if any */
- if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
- {
- if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
- {
- /* Issue when aborting DMA2D transfer */
- return HAL_ERROR;
- }
- }
- else
- {
- /* Abort background CLUT loading if any */
- if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
- {
- if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
- {
- /* Issue when aborting background CLUT loading */
- return HAL_ERROR;
- }
- }
- else
- {
- /* Abort foreground CLUT loading if any */
- if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
- {
- if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
- {
- /* Issue when aborting foreground CLUT loading */
- return HAL_ERROR;
- }
- }
- }
- }
-
-
-
- /* Carry on with de-initialization of low level hardware */
- HAL_DMA2D_MspDeInit(hdma2d);
-
- /* Reset DMA2D control registers*/
- hdma2d->Instance->CR = 0;
- hdma2d->Instance->FGOR = 0;
- hdma2d->Instance->BGOR = 0;
- hdma2d->Instance->FGPFCCR = 0;
- hdma2d->Instance->BGPFCCR = 0;
- hdma2d->Instance->OPFCCR = 0;
-
- /* Update error code */
- hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
-
- /* Initialize the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval None
- */
-__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma2d);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_DMA2D_MspInit can be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval None
- */
-__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma2d);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_DMA2D_MspDeInit can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the pdata, destination address and data size then
- start the DMA2D transfer.
- (+) Configure the source for foreground and background, destination address
- and data size then start a MultiBuffer DMA2D transfer.
- (+) Configure the pdata, destination address and data size then
- start the DMA2D transfer with interrupt.
- (+) Configure the source for foreground and background, destination address
- and data size then start a MultiBuffer DMA2D transfer with interrupt.
- (+) Abort DMA2D transfer.
- (+) Suspend DMA2D transfer.
- (+) Resume DMA2D transfer.
- (+) Enable CLUT transfer.
- (+) Configure CLUT loading then start transfer in polling mode.
- (+) Configure CLUT loading then start transfer in interrupt mode.
- (+) Abort DMA2D CLUT loading.
- (+) Suspend DMA2D CLUT loading.
- (+) Resume DMA2D CLUT loading.
- (+) Poll for transfer complete.
- (+) handle DMA2D interrupt request.
- (+) Transfer watermark callback.
- (+) CLUT Transfer Complete callback.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
- * Memory-to-Memory or Memory-to-Memory with pixel format
- * conversion mode is selected, or configure
- * the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LINE(Height));
- assert_param(IS_DMA2D_PIXEL(Width));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
-
- /* Enable the Peripheral */
- __HAL_DMA2D_ENABLE(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Start the DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
- * the Memory-to-Memory or Memory-to-Memory with pixel format
- * conversion mode is selected, or configure
- * the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LINE(Height));
- assert_param(IS_DMA2D_PIXEL(Width));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
-
- /* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
-
- /* Enable the Peripheral */
- __HAL_DMA2D_ENABLE(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Start the multi-source DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LINE(Height));
- assert_param(IS_DMA2D_PIXEL(Width));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure DMA2D Stream source2 address */
- WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
-
- /* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
-
- /* Enable the Peripheral */
- __HAL_DMA2D_ENABLE(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LINE(Height));
- assert_param(IS_DMA2D_PIXEL(Width));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure DMA2D Stream source2 address */
- WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
-
- /* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
-
- /* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
-
- /* Enable the Peripheral */
- __HAL_DMA2D_ENABLE(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort the DMA2D Transfer.
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
-{
- uint32_t tickstart = 0;
-
- /* Abort the DMA2D transfer */
- /* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing ‘0’ has no
- effect on START bitvalue). */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the DMA2D is effectively disabled */
- while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
-
- /* Change the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Suspend the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
-{
- uint32_t tickstart = 0;
-
- /* Suspend the DMA2D transfer */
- /* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing ‘0’ has no
- effect on START bitvalue). */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the DMA2D is effectively suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
- {
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
- {
- hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
- }
- else
- {
- /* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
- CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Check the SUSP and START bits */
- if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
- {
- /* Ongoing transfer is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
- }
-
- /* Resume the DMA2D transfer */
- /* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing ‘0’ has no
- effect on START bitvalue). */
- CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Enable the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- if(LayerIdx == 0)
- {
- /* Enable the background CLUT loading */
- SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
- }
- else
- {
- /* Enable the foreground CLUT loading */
- SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Start DMA2D CLUT Loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
- * the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
- assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
- {
- /* Write background CLUT memory address */
- WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write background CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
-
- /* Enable the CLUT loading for the background */
- SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
- }
- /* Configure the CLUT of the foreground DMA2D layer */
- else
- {
- /* Write foreground CLUT memory address */
- WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write foreground CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
-
- /* Enable the CLUT loading for the foreground */
- SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Start DMA2D CLUT Loading with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
- * the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
- assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
- {
- /* Write background CLUT memory address */
- WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write background CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
-
- /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
-
- /* Enable the CLUT loading for the background */
- SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
- }
- /* Configure the CLUT of the foreground DMA2D layer */
- else
- {
- /* Write foreground CLUT memory address */
- WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write foreground CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
-
- /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
-
- /* Enable the CLUT loading for the foreground */
- SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort the DMA2D CLUT loading.
- * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
- uint32_t tickstart = 0;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
- uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */
-
-
- /* Abort the CLUT loading */
- SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
-
- /* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1)
- {
- reg = &(hdma2d->Instance->FGPFCCR);
- }
-
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the CLUT loading is aborted */
- while((*reg & mask) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
-
- /* Change the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Suspend the DMA2D CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
- uint32_t tickstart = 0;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
- uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */
-
-
- /* Suspend the CLUT loading */
- SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
-
- /* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1)
- {
- reg = &(hdma2d->Instance->FGPFCCR);
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the CLUT loading is suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((*reg & mask) == mask))
- {
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((*reg & mask) != RESET)
- {
- hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
- }
- else
- {
- /* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
- CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA2D CLUT loading.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
- /* Check the SUSP and START bits for background or foreground CLUT loading */
- if(LayerIdx == 0)
- {
- /* Background CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
- {
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
- }
- }
- else
- {
- /* Foreground CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
- {
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
- }
- }
-
- /* Resume the CLUT loading */
- CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
-
- return HAL_OK;
-}
-
-
-/**
-
- * @brief Polling for transfer complete or CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- __IO uint32_t isrflags = 0x0;
-
- /* Polling for DMA2D transfer */
- if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
- {
- isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
- {
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
- {
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
- }
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
- {
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
- }
- /* Clear the transfer and configuration error flags */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Polling for CLUT loading (foreground or background) */
- if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
- ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
- {
- isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
- {
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
- {
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
- }
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
- {
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
- }
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
- {
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
- }
- /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
-
- /* Change DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
-
- /* Change the DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Clear the transfer complete and CLUT loading flags */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-/**
- * @brief Handle DMA2D interrupt request.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL status
- */
-void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
-{
- uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
- uint32_t crflags = READ_REG(hdma2d->Instance->CR);
-
- /* Transfer Error Interrupt management ***************************************/
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
- {
- if ((crflags & DMA2D_IT_TE) != RESET)
- {
- /* Disable the transfer Error interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
-
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
-
- /* Clear the transfer error flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- if(hdma2d->XferErrorCallback != NULL)
- {
- /* Transfer error Callback */
- hdma2d->XferErrorCallback(hdma2d);
- }
- }
- }
- /* Configuration Error Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
- {
- if ((crflags & DMA2D_IT_CE) != RESET)
- {
- /* Disable the Configuration Error interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
-
- /* Clear the Configuration error flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
-
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- if(hdma2d->XferErrorCallback != NULL)
- {
- /* Transfer error Callback */
- hdma2d->XferErrorCallback(hdma2d);
- }
- }
- }
- /* CLUT access Error Interrupt management ***********************************/
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
- {
- if ((crflags & DMA2D_IT_CAE) != RESET)
- {
- /* Disable the CLUT access error interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
-
- /* Clear the CLUT access error flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
-
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- if(hdma2d->XferErrorCallback != NULL)
- {
- /* Transfer error Callback */
- hdma2d->XferErrorCallback(hdma2d);
- }
- }
- }
- /* Transfer watermark Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_TW) != RESET)
- {
- if ((crflags & DMA2D_IT_TW) != RESET)
- {
- /* Disable the transfer watermark interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
-
- /* Clear the transfer watermark flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
-
- /* Transfer watermark Callback */
- HAL_DMA2D_LineEventCallback(hdma2d);
- }
- }
- /* Transfer Complete Interrupt management ************************************/
- if ((isrflags & DMA2D_FLAG_TC) != RESET)
- {
- if ((crflags & DMA2D_IT_TC) != RESET)
- {
- /* Disable the transfer complete interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
-
- /* Clear the transfer complete flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
-
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- if(hdma2d->XferCpltCallback != NULL)
- {
- /* Transfer complete Callback */
- hdma2d->XferCpltCallback(hdma2d);
- }
- }
- }
- /* CLUT Transfer Complete Interrupt management ******************************/
- if ((isrflags & DMA2D_FLAG_CTC) != RESET)
- {
- if ((crflags & DMA2D_IT_CTC) != RESET)
- {
- /* Disable the CLUT transfer complete interrupt */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
-
- /* Clear the CLUT transfer complete flag */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
-
- /* Update error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
-
- /* Change DMA2D state */
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- /* CLUT Transfer complete Callback */
- HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
- }
- }
-
-}
-
-/**
- * @brief Transfer watermark callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval None
- */
-__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma2d);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_DMA2D_LineEventCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief CLUT Transfer Complete callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval None
- */
-__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma2d);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the DMA2D foreground or background layer parameters.
- (+) Configure the DMA2D CLUT transfer.
- (+) Configure the line watermark
- (+) Configure the dead time value.
- (+) Enable or disable the dead time value functionality.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the DMA2D Layer according to the specified
- * parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
-{
- DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
-
- uint32_t regMask = 0, regValue = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
- if(hdma2d->Init.Mode != DMA2D_R2M)
- {
- assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
- if(hdma2d->Init.Mode != DMA2D_M2M)
- {
- assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
- }
- }
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* DMA2D BGPFCR register configuration -----------------------------------*/
- /* Prepare the value to be written to the BGPFCCR register */
-
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | \
- (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) | \
- (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
-
- regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS;
-
- if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
- {
- regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
- }
- else
- {
- regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
- }
-
- /* Configure the background DMA2D layer */
- if(LayerIdx == 0)
- {
- /* Write DMA2D BGPFCCR register */
- MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
-
- /* DMA2D BGOR register configuration -------------------------------------*/
- WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
-
- /* DMA2D BGCOLR register configuration -------------------------------------*/
- if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
- {
- WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
- }
- }
- /* Configure the foreground DMA2D layer */
- else
- {
- if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
- {
- regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_POSITION_FGPFCCR_CSS);
- regMask |= DMA2D_FGPFCCR_CSS;
- }
-
- /* Write DMA2D FGPFCCR register */
- MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
-
- /* DMA2D FGOR register configuration -------------------------------------*/
- WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
-
- /* DMA2D FGCOLR register configuration -------------------------------------*/
- if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
- {
- WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
- }
- }
- /* Initialize the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
- * the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
- * This parameter can be one of the following values:
- * 0(background) / 1(foreground)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
- assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
- {
- /* Write background CLUT memory address */
- WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write background CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
- }
- /* Configure the CLUT of the foreground DMA2D layer */
- else
- {
- /* Write foreground CLUT memory address */
- WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
-
- /* Write foreground CLUT size and CLUT color mode */
- MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
- }
-
- /* Set the DMA2D state to Ready*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Configure the line watermark.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
- * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
- * @note The transfer watermark interrupt is disabled once it has occurred.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
-{
- /* Check the parameters */
- assert_param(IS_DMA2D_LINEWATERMARK(Line));
-
- /* Process locked */
- __HAL_LOCK(hdma2d);
-
- /* Change DMA2D peripheral state */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Sets the Line watermark configuration */
- WRITE_REG(hdma2d->Instance->LWR, Line);
-
- /* Enable the Line interrupt */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
-
- /* Initialize the DMA2D state*/
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Process Locked */
- __HAL_LOCK(hdma2d);
-
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Set DMA2D_AMTCR EN bit */
- SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
-
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
-{
- /* Process Locked */
- __HAL_LOCK(hdma2d);
-
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Clear DMA2D_AMTCR EN bit */
- CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
-
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure dead time.
- * @note The dead time value represents the guaranteed minimum number of cycles between
- * two consecutive transactions on the AHB bus.
- * @param hdma2d: DMA2D handle.
- * @param DeadTime: dead time value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
-{
- /* Process Locked */
- __HAL_LOCK(hdma2d);
-
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
-
- /* Set DMA2D_AMTCR DT field */
- MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
-
- hdma2d->State = HAL_DMA2D_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma2d);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Get the DMA2D state
- (+) Get the DMA2D error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DMA2D state
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the DMA2D.
- * @retval HAL state
- */
-HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
-{
- return hdma2d->State;
-}
-
-/**
- * @brief Return the DMA2D error code
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for DMA2D.
- * @retval DMA2D Error Code
- */
-uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
-{
- return hdma2d->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
- * @{
- */
-
-/**
- * @brief Set the DMA2D transfer parameters.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
- * the configuration information for the specified DMA2D.
- * @param pdata: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param Width: The width of data to be transferred from source to destination.
- * @param Height: The height of data to be transferred from source to destination.
- * @retval HAL status
- */
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
-{
- uint32_t tmp = 0;
- uint32_t tmp1 = 0;
- uint32_t tmp2 = 0;
- uint32_t tmp3 = 0;
- uint32_t tmp4 = 0;
-
- /* Configure DMA2D data size */
- MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
-
- /* Configure DMA2D destination address */
- WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
-
- /* Register to memory DMA2D mode selected */
- if (hdma2d->Init.Mode == DMA2D_R2M)
- {
- tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
- tmp2 = pdata & DMA2D_OCOLR_RED_1;
- tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
- tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
-
- /* Prepare the value to be written to the OCOLR register according to the color mode */
- if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
- {
- tmp = (tmp3 | tmp2 | tmp1| tmp4);
- }
- else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
- {
- tmp = (tmp3 | tmp2 | tmp4);
- }
- else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
- {
- tmp2 = (tmp2 >> 19);
- tmp3 = (tmp3 >> 10);
- tmp4 = (tmp4 >> 3 );
- tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
- }
- else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
- {
- tmp1 = (tmp1 >> 31);
- tmp2 = (tmp2 >> 19);
- tmp3 = (tmp3 >> 11);
- tmp4 = (tmp4 >> 3 );
- tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
- }
- else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
- {
- tmp1 = (tmp1 >> 28);
- tmp2 = (tmp2 >> 20);
- tmp3 = (tmp3 >> 12);
- tmp4 = (tmp4 >> 4 );
- tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
- }
- /* Write to DMA2D OCOLR register */
- WRITE_REG(hdma2d->Instance->OCOLR, tmp);
- }
- else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
- {
- /* Configure DMA2D source address */
- WRITE_REG(hdma2d->Instance->FGMAR, pdata);
- }
-}
-
-/**
- * @}
- */
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
deleted file mode 100644
index 96db000..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_dma_ex.c
- * @author MCD Application Team
- * @brief DMA Extension HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of the DMA Extension peripheral:
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The DMA Extension HAL driver can be used as follows:
- (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
- for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-
- (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
- (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
- Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
- to respectively enable/disable the request generator.
-
- (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
- the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
- As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
- called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
- (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-
- -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
- -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
- -@- In Multi (Double) buffer mode, it is possible to update the base address for
- the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
- -@- Multi (Double) buffer mode is only possible with D2 DMAs i.e DMA1 or DMA2. not BDMA.
- Multi (Double) buffer mode is not possible with D3 BDMA.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMAEx DMAEx
- * @brief DMA Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private Constants ---------------------------------------------------------*/
-#define DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE) /*!< Required for left shift of the DMAMUX SYNC enable/disable */
-#define DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE) /*!< Required for left shift of the DMAMUX SYNC EVENT enable/disable */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMAEx_Private_Functions
- * @{
- */
-
-static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup DMAEx_Exported_Functions
- * @{
- */
-
-
-/** @addtogroup DMAEx_Exported_Functions_Group1
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and
- Start MultiBuffer DMA transfer
- (+) Configure the source, destination address and data length and
- Start MultiBuffer DMA transfer with interrupt
- (+) Change on the fly the memory0 or memory1 address.
- (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
- (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
- (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
- to respectively enable/disable the request generator.
- (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
- the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Starts the multi_buffer DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t *ifcRegister_Base = NULL; /* DMA Stream Interrupt Clear register */
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Memory-to-memory transfer not supported in double buffering mode */
- /* double buffering mode not supported for BDMA (D3 DMA) */
- if ( (IS_D2_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Enable the double buffer mode */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
-
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
-
- /* Configure the source, destination address and the data length */
- DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Calculate the interrupt clear flag register (IFCR) base address */
- ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
-
- /* Clear all flags */
- *ifcRegister_Base = 0x3FU << hdma->StreamIndex;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Enable the peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- status = HAL_ERROR;
- }
- }
- return status;
-}
-
-/**
- * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t *ifcRegister_Base = NULL; /* DMA Stream Interrupt Clear register */
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Memory-to-memory transfer not supported in double buffering mode */
- /* double buffering mode not supported for BDMA (D3 DMA) */
- if( (IS_D2_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Enable the Double buffer mode */
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
-
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
-
- /* Configure the source, destination address and the data length */
- DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Calculate the interrupt clear flag register (IFCR) base address */
- ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
-
- /* Clear all flags */
- *ifcRegister_Base = 0x3FU << hdma->StreamIndex;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- }
-
- /* Enable Common interrupts*/
- MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
- ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /*Enable Half Transfer IT if corresponding Callback is set*/
- ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
- }
-
- /* Check if DMAMUX Synchronization is enabled*/
- if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0)
- {
- /* Enable DMAMUX sync overrun IT*/
- hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
- }
-
- if(hdma->DMAmuxRequestGen != 0U)
- {
- /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
- /* enable the request gen overrun IT*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
- }
-
- /* Enable the peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- status = HAL_ERROR;
- }
- return status;
-}
-
-/**
- * @brief Change the memory0 or memory1 address on the fly.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param Address: The new address
- * @param memory: the memory to be changed, This parameter can be one of
- * the following values:
- * MEMORY0 /
- * MEMORY1
- * @note The MEMORY0 address can be changed only when the current transfer use
- * MEMORY1 and the MEMORY1 address can be changed only when the current
- * transfer use MEMORY0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
-{
- if(memory == MEMORY0)
- {
- /* change the memory0 address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
- }
- else
- {
- /* change the memory1 address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
-{
- uint32_t syncSignalID = 0;
- uint32_t syncPolarity = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
- assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
- assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
-
- if(pSyncConfig->SyncEnable == ENABLE)
- {
- assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
-
- if(IS_D2_DMA_INSTANCE(hdma) != 0U)
- {
- assert_param(IS_D2_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
- }
- else
- {
- assert_param(IS_D3_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
- }
- syncSignalID = pSyncConfig->SyncSignalID;
- syncPolarity = pSyncConfig->SyncPolarity;
- }
-
- /*Check if the DMA state is ready */
- if(hdma->State == HAL_DMA_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Disable the synchronization and event generation before applying a new config */
- CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
-
- /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
- MODIFY_REG( hdma->DMAmuxChannel->CCR, \
- (~DMAMUX_CxCR_DMAREQ_ID) , \
- (syncSignalID << POSITION_VAL(DMAMUX_CxCR_SYNC_ID)) | \
- ((pSyncConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_CxCR_NBREQ)) | \
- syncPolarity | (pSyncConfig->SyncEnable << DMAMUX_POSITION_CxCR_SE) | \
- (pSyncConfig->EventEnable << DMAMUX_POSITION_CxCR_EGE));
-
- /* Process Locked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- }
- else
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* Return error status */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
- * contains the request generator parameters.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-
- if(IS_D2_DMA_INSTANCE(hdma) != 0U)
- {
- assert_param(IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
- }
- else
- {
- assert_param(IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
- }
-
-
- assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
- assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if(hdma->DMAmuxRequestGen == 0U)
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-
- /* error status */
- status = HAL_ERROR;
- }
- else if((hdma->State == HAL_DMA_STATE_READY) && ((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0))
- {
- /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
-
- /* Process Locked */
- __HAL_LOCK(hdma);
-
- /* Set the request generator new parameters*/
- hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
- ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_NBREQ))| \
- pRequestGeneratorConfig->Polarity;
- /* Process Locked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
- }
- else
- {
- /* Set the error code to busy */
- hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
-
- /* error status */
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
-{
- /* Check the parameters */
- assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
- {
-
- /* Enable the request generator*/
- hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
-{
- /* Check the parameters */
- assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-
- /* check if the DMA state is ready
- and DMA is using a DMAMUX request generator block
- */
- if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
- {
-
- /* Disable the request generator*/
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handles DMAMUX interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- /* Check for DMAMUX Synchronization overrun */
- if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
- {
- /* Disable the synchro overrun interrupt */
- hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
-
- /* Clear the DMAMUX synchro overrun flag */
- hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
-
- if(hdma->DMAmuxRequestGen != 0)
- {
- /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
- if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
- {
- /* Disable the request gen overrun interrupt */
- hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
-
- /* Clear the DMAMUX request generator overrun flag */
- hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
-
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMAEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Set the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Configure DMA Stream data length */
- ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
-
- /* Peripheral to Memory */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
-
- /* Configure DMA Stream source address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
- }
- /* Memory to Peripheral */
- else
- {
- /* Configure DMA Stream source address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
-
- /* Configure DMA Stream destination address */
- ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
deleted file mode 100644
index a86345d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
+++ /dev/null
@@ -1,2601 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_eth.c
- * @author MCD Application Team
- * @brief ETH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Ethernet (ETH) peripheral:
- * + Initialization and deinitialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The ETH HAL driver can be used as follows:
-
- (#)Declare a ETH_HandleTypeDef handle structure, for example:
- ETH_HandleTypeDef heth;
-
- (#)Fill parameters of Init structure in heth handle
-
- (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
-
- (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
- (##) Enable the Ethernet interface clock using
- (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE()
- (+++) __HAL_RCC_ETH1TX_CLK_ENABLE()
- (+++) __HAL_RCC_ETH1RX_CLK_ENABLE()
-
- (##) Initialize the related GPIO clocks
- (##) Configure Ethernet pinout
- (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
-
- (#) Ethernet data reception is asynchronous, so call the following API
- to start the listening mode:
- (##) HAL_ETH_Start():
- This API starts the MAC and DMA transmission and reception process,
- without enabling end of transfer interrupts, in this mode user
- has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
- (##) HAL_ETH_Start_IT():
- This API starts the MAC and DMA transmission and reception process,
- end of transfer interrupts are enabled in this mode,
- HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
-
- (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
- occurred), user can call the following APIs to get received data:
- (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
- (##) HAL_ETH_GetRxDataLength(): Get received frame length
- (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
- please refer to ETH_RxPacketInfo typedef structure
-
- (#) For transmission path, two APIs are available:
- (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
- (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
- HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
-
- (#) Communication with an external PHY device:
- (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
- (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
-
- (#) Configure the Ethernet MAC after ETH peripheral initialization
- (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
- (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
-
- (#) Configure the Ethernet DMA after ETH peripheral initialization
- (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
- (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
-
- -@- The PTP protocol offload APIs are not supported in this driver.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ETH ETH
- * @brief ETH HAL module driver
- * @{
- */
-#ifdef HAL_ETH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup ETH_Private_Constants ETH Private Constants
- * @{
- */
-#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
-#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
-#define ETH_MACPFR_MASK ((uint32_t)0x800007FFU)
-#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
-#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
-#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
-#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
-#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
-
-#define ETH_DMAMR_MASK ((uint32_t)0x00007802U)
-#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
-#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
-#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
-#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
-#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
- ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
- ETH_MACPCSR_RWKPFE)
-
-/* Timeout values */
-#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
-#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
-
-#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
- ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
- ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
-
-#define ETH_MAC_US_TICK ((uint32_t)1000000U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ETH_Private_Macros ETH Private Macros
- * @{
- */
-/* Helper macros for TX descriptor handling */
-#define INCR_TX_DESC_INDEX(inx, offset) do {\
- (inx) += (offset);\
- if ((inx) >= ETH_TX_DESC_CNT){\
- (inx) = ((inx) - ETH_TX_DESC_CNT);}\
-} while (0)
-
-/* Helper macros for RX descriptor handling */
-#define INCR_RX_DESC_INDEX(inx, offset) do {\
- (inx) += (offset);\
- if ((inx) >= ETH_RX_DESC_CNT){\
- (inx) = ((inx) - ETH_RX_DESC_CNT);}\
-} while (0)
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ETH_Private_Functions ETH Private Functions
- * @{
- */
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
-static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
-static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup ETH_Exported_Functions ETH Exported Functions
- * @{
- */
-
-/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- deinitialize the ETH peripheral:
-
- (+) User must Implement HAL_ETH_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO and NVIC ).
-
- (+) Call the function HAL_ETH_Init() to configure the selected device with
- the selected configuration:
- (++) MAC address
- (++) Media interface (MII or RMII)
- (++) Rx DMA Descriptors Tab
- (++) Tx DMA Descriptors Tab
- (++) Length of Rx Buffers
-
- (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
- for each Rx DMA Descriptor
-
- (+) Call the function HAL_ETH_DeInit() to restore the default configuration
- of the selected ETH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the Ethernet peripheral registers.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
-{
- uint32_t tickstart;
-
- if(heth == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the ETH peripheral state */
- if(heth->gState == HAL_ETH_STATE_RESET)
- {
- /* Init the low level hardware : GPIO, CLOCK, NVIC. */
- HAL_ETH_MspInit(heth);
- }
-
- heth->gState = HAL_ETH_STATE_BUSY;
-
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
- {
- HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
- }
- else
- {
- HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
- }
-
- /* Ethernet Software reset */
- /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
- /* After reset all the registers holds their respective reset values */
- SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for software reset */
- while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR))
- {
- if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
- {
- /* Set Error Code */
- heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
- /* Set State as Error */
- heth->gState = HAL_ETH_STATE_ERROR;
- /* Return Error */
- return HAL_ERROR;
- }
- }
-
- /*------------------ MDIO CSR Clock Range Configuration --------------------*/
- ETH_MAC_MDIO_ClkConfig(heth);
-
- /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
- WRITE_REG(heth->Instance->MAC1USTCR, ((HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1));
-
- /*------------------ MAC, MTL and DMA default Configuration ----------------*/
- ETH_MACDMAConfig(heth);
-
- /* SET DSL to 64 bit */
- MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
-
- /* Set Receive Buffers Length (must be a multiple of 4) */
- if ((heth->Init.RxBuffLen % 4) != 0)
- {
- /* Set Error Code */
- heth->ErrorCode = HAL_ETH_ERROR_PARAM;
- /* Set State as Error */
- heth->gState = HAL_ETH_STATE_ERROR;
- /* Return Error */
- return HAL_ERROR;
- }
- else
- {
- MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
- }
-
- /*------------------ DMA Tx Descriptors Configuration ----------------------*/
- ETH_DMATxDescListInit(heth);
-
- /*------------------ DMA Rx Descriptors Configuration ----------------------*/
- ETH_DMARxDescListInit(heth);
-
- /*--------------------- ETHERNET MAC Address Configuration ------------------*/
- /* Set MAC addr bits 32 to 47 */
- heth->Instance->MACA0HR = ((heth->Init.MACAddr[5] << 8) | heth->Init.MACAddr[4]);
- /* Set MAC addr bits 0 to 31 */
- heth->Instance->MACA0LR = ((heth->Init.MACAddr[3] << 24) | (heth->Init.MACAddr[2] << 16) | (heth->Init.MACAddr[1] << 8) | heth->Init.MACAddr[0]);
-
- heth->ErrorCode = HAL_ETH_ERROR_NONE;
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the ETH peripheral.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
-{
- /* Set the ETH peripheral state to BUSY */
- heth->gState = HAL_ETH_STATE_BUSY;
-
- /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
- HAL_ETH_MspDeInit(heth);
-
- /* Set ETH HAL state to Disabled */
- heth->gState= HAL_ETH_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Assign memory buffers to a DMA Rx descriptor
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Index : index of the DMA Rx descriptor
- * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
- * @param pBuffer1: address of buffer 1
- * @param pBuffer2: address of buffer 2 if available
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
-{
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
-
- if((pBuffer1 == NULL) || (Index >= ETH_RX_DESC_CNT))
- {
- /* Set Error Code */
- heth->ErrorCode = HAL_ETH_ERROR_PARAM;
- /* Return Error */
- return HAL_ERROR;
- }
-
- /* write buffer address to RDES0 */
- WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
- /* store buffer address */
- WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
- /* set buffer address valid bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
- if(pBuffer2 != NULL)
- {
- /* write buffer 2 address to RDES1 */
- WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
- /* store buffer 2 address */
- WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
- /* set buffer 2 address valid bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
- /* set OWN bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
- * @brief ETH Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the ETH
- data transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables Ethernet MAC and DMA reception and transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
-{
- if(heth->gState == HAL_ETH_STATE_READY)
- {
- heth->gState = HAL_ETH_STATE_BUSY;
-
- /* Enable the MAC transmission */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
- /* Enable the MAC reception */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
- /* Set the Flush Transmit FIFO bit */
- SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
-
- /* Enable the DMA transmission */
- SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
-
- /* Enable the DMA reception */
- SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
-
- /* Clear Tx and Rx process stopped flags */
- heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
-
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_BUSY_RX;
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
-{
- uint32_t descindex = 0, counter;
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
-
- if(heth->gState == HAL_ETH_STATE_READY)
- {
- heth->gState = HAL_ETH_STATE_BUSY;
-
- /* Set IOC bit to all Rx descriptors */
- for(counter= 0; counter < ETH_RX_DESC_CNT; counter++)
- {
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- INCR_RX_DESC_INDEX(descindex, 1);
- dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
- }
-
- /* save IT mode to ETH Handle */
- heth->RxDescList.ItMode = 1U;
-
- /* Enable the MAC transmission */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
- /* Enable the MAC reception */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
- /* Set the Flush Transmit FIFO bit */
- SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
-
- /* Enable the DMA transmission */
- SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
-
- /* Enable the DMA reception */
- SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
-
- /* Clear Tx and Rx process stopped flags */
- heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
-
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_BUSY_RX;
-
- /* Enable ETH DMA interrupts:
- - Tx complete interrupt
- - Rx complete interrupt
- - Fatal bus interrupt
- */
- __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
- ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Stop Ethernet MAC and DMA reception/transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
-{
- if(heth->gState != HAL_ETH_STATE_RESET)
- {
- /* Set the ETH peripheral state to BUSY */
- heth->gState = HAL_ETH_STATE_BUSY;
-
- /* Disable the DMA transmission */
- CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
-
- /* Disable the DMA reception */
- CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
-
- /* Disable the MAC reception */
- CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
-
- /* Set the Flush Transmit FIFO bit */
- SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
-
- /* Disable the MAC transmission */
- CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
-{
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
- uint32_t index;
-
- if(heth->gState != HAL_ETH_STATE_RESET)
- {
- /* Set the ETH peripheral state to BUSY */
- heth->gState = HAL_ETH_STATE_BUSY;
-
- /* Disable intrrupts:
- - Tx complete interrupt
- - Rx complete interrupt */
- __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
-
- /* Disable the DMA transmission */
- CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
-
- /* Disable the DMA reception */
- CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
-
- /* Disable the MAC reception */
- CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
-
- /* Set the Flush Transmit FIFO bit */
- SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
-
- /* Disable the MAC transmission */
- CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
- /* Clear IOC bit to all Rx descriptors */
- for(index = 0; index < ETH_RX_DESC_CNT; index++)
- {
- CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- }
-
- heth->RxDescList.ItMode = 0U;
-
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sends an Ethernet Packet in polling mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pTxConfig: Hold the configuration of packet to be transmitted
- * @param Timeout: timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
-{
- uint32_t tickstart;
- const ETH_DMADescTypeDef *dmatxdesc;
-
- if(pTxConfig == NULL)
- {
- heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(heth->gState == HAL_ETH_STATE_READY)
- {
- /* Config DMA Tx descriptor by Tx Packet info */
- if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
- {
- /* Set the ETH error code */
- heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
-
- /* Incr current tx desc index */
- INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1);
-
- /* Start transmission */
- /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
- WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
-
- tickstart = HAL_GetTick();
-
- /* Wait for data to be transmitted or timeout occured */
- while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
- {
- if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
- {
- heth->ErrorCode |= HAL_ETH_ERROR_DMA;
- heth->DMAErrorCode = heth->Instance->DMACSR;
- /* Set ETH HAL State to Ready */
- heth->gState = HAL_ETH_STATE_ERROR;
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
- {
- heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
- heth->gState = HAL_ETH_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Set ETH HAL State to Ready */
- heth->gState = HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sends an Ethernet Packet in interrupt mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pTxConfig: Hold the configuration of packet to be transmitted
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
-{
- if(pTxConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- if(heth->gState == HAL_ETH_STATE_READY)
- {
- /* Config DMA Tx descriptor by Tx Packet info */
- if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
- {
- heth->ErrorCode = HAL_ETH_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Incr current tx desc index */
- INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1);
-
- /* Start transmission */
- /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
- WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
-
- return HAL_OK;
-
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Checks for received Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval 1: A Packet is received
- * 0: no Packet received
- */
-uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
-{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->CurRxDesc;
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- uint32_t descscancnt = 0;
- uint32_t appdesccnt = 0, firstappdescidx = 0;
-
- if(dmarxdesclist->AppDescNbr != 0)
- {
- /* data already received by not yet processed*/
- return 0;
- }
-
- /* Check if descriptor is not owned by DMA */
- while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < ETH_RX_DESC_CNT))
- {
- descscancnt++;
-
- /* Check if last descriptor */
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
- {
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt += 1U;
-
- if(appdesccnt == 1)
- {
- WRITE_REG(firstappdescidx, descidx);
- }
-
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1);
-
- /* Check for Context descriptor */
- /* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
- if((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) &&
- (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET))
- {
- /* Increment the number of descriptors to be passed to the application */
- dmarxdesclist->AppContextDesc = 1;
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1);
- }
-
- /* Fill information to Rx descriptors list */
- dmarxdesclist->CurRxDesc = descidx;
- dmarxdesclist->FirstAppDesc = firstappdescidx;
- dmarxdesclist->AppDescNbr = appdesccnt;
-
- /* Return function status */
- return 1;
- }
- /* Check if first descriptor */
- else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
- {
- WRITE_REG(firstappdescidx, descidx);
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt = 1U;
-
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- /* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- }
- /* It should be an intermediate descriptor */
- else
- {
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt += 1U;
-
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- /* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- }
- }
-
- /* Build Descriptors if an incomplete Packet is received */
- if(appdesccnt > 0)
- {
- descidx = firstappdescidx;
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
- for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
- {
- WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
- WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
- if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
- {
- WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
-
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
- if(dmarxdesclist->ItMode != ((uint32_t)RESET))
- {
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- }
-
- /* Increment rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1);
- /* Get descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- }
- }
-
- /* Fill information to Rx descriptors list: No received Packet */
- dmarxdesclist->AppDescNbr = 0U;
-
- return 0;
-}
-
-/**
- * @brief This function gets the buffer address of last received Packet.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
-{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- uint32_t index, accumulatedlen = 0, lastdesclen;
- __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- ETH_BufferTypeDef *rxbuff = RxBuffer;
-
- if(dmarxdesclist->AppDescNbr ==0)
- {
- if(HAL_ETH_IsRxDataAvailable(heth) == 0)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- }
-
- /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
- for(index = 0; index < (dmarxdesclist->AppDescNbr - 1); index++)
- {
- /* Both rx descriptor buffers are valid */
- if(dmarxdesc->BackupAddr1 != 0)
- {
- if(rxbuff == NULL)
- {
- return HAL_ERROR;
- }
-
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
- rxbuff->len = heth->Init.RxBuffLen;
-
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
-
- if(rxbuff == NULL)
- {
- return HAL_ERROR;
- }
-
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
- rxbuff->len = heth->Init.RxBuffLen;
- }
- /* Only buffer 1 address is valid */
- else
- {
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
- rxbuff->len = heth->Init.RxBuffLen;
- }
-
- /* get total length until this descriptor */
- accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
-
- /* Increment to next descriptor */
- INCR_RX_DESC_INDEX(descidx, 1);
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
- /* Point to next buffer */
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
- }
-
- /* Get last descriptor buffers */
- if(rxbuff == NULL)
- {
- return HAL_ERROR;
- }
-
- /* last descriptor data length */
- lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
-
- /* data is in only one buffer */
- if(lastdesclen <= heth->Init.RxBuffLen)
- {
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
- rxbuff->len = lastdesclen;
- }
- /* data is in two buffers */
- else if(dmarxdesc->BackupAddr1 != 0)
- {
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
- rxbuff->len = heth->Init.RxBuffLen;
-
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
-
- if(rxbuff == NULL)
- {
- return HAL_ERROR;
- }
-
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
- rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
- }
- else /* Buffer 2 not valid*/
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function gets the length of last received Packet.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Length: parameter to hold Rx packet length
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
-{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- __IO const ETH_DMADescTypeDef *dmarxdesc;
-
- if(dmarxdesclist->AppDescNbr ==0)
- {
- if(HAL_ETH_IsRxDataAvailable(heth) == 0)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- }
-
- /* Get index of last descriptor */
- INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr-1));
- /* Point to last descriptor */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
- *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param RxPacketInfo: parameter to hold info of received buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
-{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- __IO const ETH_DMADescTypeDef *dmarxdesc;
-
- if(dmarxdesclist->AppDescNbr ==0)
- {
- if(HAL_ETH_IsRxDataAvailable(heth) == 0)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- }
-
- /* Get index of last descriptor */
- INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
- /* Point to last descriptor */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
- if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
- {
- RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
- }
- else
- {
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V))
- {
-
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
- {
- RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
- RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
- }
- else
- {
- RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
- }
- }
-
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V))
- {
- /* Get Payload type */
- RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
- /* Get Header type */
- RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
- /* Get Checksum status */
- RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
- }
-
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V))
- {
- RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
- RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
- RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
- }
- }
-
- /* Get the segment count */
- WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
-
- return HAL_OK;
-}
-
-/**
-* @brief This function gives back Rx Desc of the last received Packet
-* to the DMA, so ETH DMA will be able to use these descriptors
-* to receive next Packets.
-* It should be called after processing the received Packet.
-* @param heth: pointer to a ETH_HandleTypeDef structure that contains
-* the configuration information for ETHERNET module
-* @retval HAL status.
-*/
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
-{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descindex = dmarxdesclist->FirstAppDesc;
- __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
- uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
- uint32_t descscan;
-
- if(dmarxdesclist->AppDescNbr ==0)
- {
- /* No Rx descriptors to build */
- return HAL_ERROR;
- }
-
- if(dmarxdesclist->AppContextDesc != 0U)
- {
- /* A context descriptor is available */
- totalappdescnbr += 1;
- }
-
- for(descscan =0; descscan < totalappdescnbr; descscan++)
- {
- WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
- WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
- if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
- {
- WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
-
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
- if(dmarxdesclist->ItMode != 0U)
- {
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- }
-
- if(descscan < (dmarxdesclist->AppDescNbr -1))
- {
- /* Increment rx descriptor index */
- INCR_RX_DESC_INDEX(descindex, 1);
- /* Get descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
- }
- }
-
- /* Set the Tail pointer address to the last rx descriptor hold by the app */
- WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
-
- /* reset the Application desc number */
- WRITE_REG(dmarxdesclist->AppDescNbr, 0);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief This function handles ETH interrupt request.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
-{
- /* Packet received */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
- {
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
- {
- /* Call this function to update handle fields */
- if(HAL_ETH_IsRxDataAvailable(heth) == 1)
- {
- /* Receive complete callback */
- HAL_ETH_RxCpltCallback(heth);
- }
-
- /* Clear the Eth DMA Rx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
- }
- }
-
- /* Packet transmitted */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
- {
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
- {
- /* Transfer complete callback */
- HAL_ETH_TxCpltCallback(heth);
-
- /* Clear the Eth DMA Tx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
- }
- }
-
-
- /* ETH DMA Error */
- if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
- {
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
- {
- heth->ErrorCode |= HAL_ETH_ERROR_DMA;
-
- /* if fatal bus error occured */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
- {
- /* Get DMA error code */
- heth->DMAErrorCode = __HAL_ETH_DMA_GET_IT(heth, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
-
- /* Disable all interrupts */
- __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
-
- /* Set HAL state to ERROR */
- heth->gState = HAL_ETH_STATE_ERROR;
- }
- else
- {
- /* Get DMA error status */
- heth->DMAErrorCode = __HAL_ETH_DMA_GET_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
-
- /* Clear the interrupt summary flag */
- __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
- }
-
- /* Ethernet Error callback */
- HAL_ETH_DMAErrorCallback(heth);
- }
- }
-
- /* ETH MAC Error IT */
- if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
- {
- /* Get MAC Rx Tx status and clear Status register pending bit */
- heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
-
- heth->gState = HAL_ETH_STATE_ERROR;
-
- /* Ethernet PMT callback */
- HAL_ETH_MACErrorCallback(heth);
-
- heth->MACErrorCode = (uint32_t)(0x0U);
- }
-
- /* ETH PMT IT */
- if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
- {
- /* Get MAC Wake-up source and clear the status register pending bit */
- heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
-
- /* Ethernet PMT callback */
- HAL_ETH_PMTCallback(heth);
-
- heth->MACWakeUpEvent = (uint32_t)(0x0U);
- }
-
- /* ETH EEE IT */
- if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
- {
- /* Get MAC LPI interrupt source and clear the status register pending bit */
- heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
-
- /* Ethernet EEE callback */
- HAL_ETH_EEECallback(heth);
-
- heth->MACLPIEvent = (uint32_t)(0x0U);
- }
-
- /* check ETH WAKEUP exti flag */
- if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != RESET)
- {
- /* Clear ETH WAKEUP Exti pending bit */
- __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
- /* ETH WAKEUP interrupt user callback */
- HAL_ETH_WakeUpCallback(heth);
- }
-}
-
-/**
- * @brief Tx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Ethernet DMA transfer error callbacks
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_DMAErrorCallback could be implemented in the user file
- */
-}
-
-/**
-* @brief Ethernet MAC transfer error callbacks
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MACErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Ethernet Power Management module IT callback
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_PMTCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Energy Efficient Etherent IT callback
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_EEECallback could be implemented in the user file
- */
-}
-
-/**
- * @brief ETH WAKEUP interrupt callback
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_WakeUpCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Read a PHY register
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param PHYAddr: PHY port address, must be a value from 0 to 31
- * @param PHYReg: PHY register address, must be a value from 0 to 31
- * @param pRegValue: parameter to hold read value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
-{
- uint32_t tmpreg, tickstart;
-
- /* Check for the Busy flag */
- if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
- {
- return HAL_ERROR;
- }
-
- /* Get the MACMDIOAR value */
- WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
-
- /* Prepare the MDIO Address Register value
- - Set the PHY device address
- - Set the PHY register address
- - Set the read mode
- - Set the MII Busy bit */
-
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
- SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
-
- /* Write the result value into the MDII Address register */
- WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
-
- tickstart = HAL_GetTick();
-
- /* Wait for the Busy flag */
- while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
- {
- if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
- {
- return HAL_ERROR;
- }
- }
-
- /* Get MACMIIDR value */
- WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Writes to a PHY register.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param PHYAddr: PHY port address, must be a value from 0 to 31
- * @param PHYReg: PHY register address, must be a value from 0 to 31
- * @param RegValue: the value to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
-{
- uint32_t tmpreg, tickstart;
-
- /* Check for the Busy flag */
- if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
- {
- return HAL_ERROR;
- }
-
- /* Get the MACMDIOAR value */
- WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
-
- /* Prepare the MDIO Address Register value
- - Set the PHY device address
- - Set the PHY register address
- - Set the write mode
- - Set the MII Busy bit */
-
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
- SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
-
-
- /* Give the value to the MII data register */
- WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
-
- /* Write the result value into the MII Address register */
- WRITE_REG(ETH->MACMDIOAR, tmpreg);
-
- tickstart = HAL_GetTick();
-
- /* Wait for the Busy flag */
- while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB))
- {
- if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
- {
- return HAL_ERROR;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
- * @brief ETH control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the ETH
- peripheral.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Get the configuration of the MAC and MTL subsystems.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
- * the configuration of the MAC.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
-{
- if (macconf == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Get MAC parameters */
- macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
- macconf->DeferralCheck = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4);
- macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
- macconf->RetryTransmission = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8));
- macconf->CarrierSenseDuringTransmit = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9);
- macconf->ReceiveOwn = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10));
- macconf->CarrierSenseBeforeTransmit = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11);
- macconf->LoopbackMode = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12);
- macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
- macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
- macconf->JumboPacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16);
- macconf->Jabber = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17));
- macconf->Watchdog = (FunctionalState)(!(READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19));
- macconf->AutomaticPadCRCStrip = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20);
- macconf->CRCStripTypePacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21);
- macconf->Support2KPacket = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22);
- macconf->GiantPacketSizeLimitControl = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23);
- macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
- macconf->ChecksumOffload = (FunctionalState)(READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27);
- macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
-
- macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
- macconf->CRCCheckingRxPackets = (FunctionalState)(!(READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16));
- macconf->SlowProtocolDetect = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17);
- macconf->UnicastSlowProtocolPacketDetect = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18);
- macconf->ExtendedInterPacketGap = (FunctionalState)(READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24);
- macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
-
-
- macconf->ProgrammableWatchdog = (FunctionalState)(READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8);
- macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
-
- macconf->TransmitFlowControl = (FunctionalState)(READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1);
- macconf->ZeroQuantaPause = (FunctionalState)(!(READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7));
- macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
- macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
-
-
- macconf->ReceiveFlowControl = (FunctionalState)READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE);
- macconf->UnicastPausePacketDetect = (FunctionalState)(READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1);
-
- macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
-
- macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
- macconf->ForwardRxUndersizedGoodPacket = (FunctionalState)(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3);
- macconf->ForwardRxErrorPacket = (FunctionalState)(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4);
- macconf->DropTCPIPChecksumErrorPacket = (FunctionalState)(!(READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6));
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the configuration of the DMA.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
- * the configuration of the ETH DMA.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
-{
- if (dmaconf == NULL)
- {
- return HAL_ERROR;
- }
-
- dmaconf->AddressAlignedBeats = (FunctionalState)(READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12);
- dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
- dmaconf->RebuildINCRxBurst = (FunctionalState)(READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15);
-
- dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
-
- dmaconf->PBLx8Mode = (FunctionalState)(READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16);
- dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
-
- dmaconf->FlushRxPacket = (FunctionalState)(READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31);
- dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
-
- dmaconf->SecondPacketOperate = (FunctionalState)(READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4);
- dmaconf->TCPSegmentation = (FunctionalState)(READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12);
- dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the MAC configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains
- * the configuration of the MAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
-{
- if(macconf == NULL)
- {
- return HAL_ERROR;
- }
-
- if(heth->RxState == HAL_ETH_STATE_READY)
- {
- ETH_SetMACConfig(heth, macconf);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Set the ETH DMA configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
- * the configuration of the ETH DMA.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
-{
- if(dmaconf == NULL)
- {
- return HAL_ERROR;
- }
-
- if(heth->RxState == HAL_ETH_STATE_READY)
- {
- ETH_SetDMAConfig(heth, dmaconf);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configures the Clock range of ETH MDIO interface.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
-{
- uint32_t tmpreg, hclk;
-
- /* Get the ETHERNET MACMDIOAR value */
- tmpreg = (heth->Instance)->MACMDIOAR;
-
- /* Clear CSR Clock Range bits */
- tmpreg &= ~ETH_MACMDIOAR_CR;
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- /* Set CR bits depending on hclk value */
- if((hclk >= 20000000)&&(hclk < 35000000))
- {
- /* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
- }
- else if((hclk >= 35000000)&&(hclk < 60000000))
- {
- /* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
- }
- else if((hclk >= 60000000)&&(hclk < 100000000))
- {
- /* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
- }
- else if((hclk >= 100000000)&&(hclk < 150000000))
- {
- /* CSR Clock Range between 100-150 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
- }
- else /* (hclk >= 150000000)&&(hclk <= 200000000) */
- {
- /* CSR Clock Range between 150-200 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
- }
-
- /* Configure the CSR Clock Range */
- (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
-}
-
-/**
- * @brief Set the ETH MAC (L2) Filters configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
- * the configuration of the ETH MAC filters.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
-{
- uint32_t filterconfig;
-
- if(pFilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- filterconfig = (pFilterConfig->PromiscuousMode |
- ((uint32_t)pFilterConfig->HashUnicast << 1) |
- ((uint32_t)pFilterConfig->HashMulticast << 2) |
- ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
- ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
- ((uint32_t)!pFilterConfig->BroadcastFilter << 5) |
- ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
- ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
- ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
- ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
- pFilterConfig->ControlPacketsFilter);
-
- MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the ETH MAC (L2) Filters configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
- * the configuration of the ETH MAC filters.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
-{
- if(pFilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- pFilterConfig->PromiscuousMode = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR));
- pFilterConfig->HashUnicast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1);
- pFilterConfig->HashMulticast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2);
- pFilterConfig->DestAddrInverseFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3);
- pFilterConfig->PassAllMulticast = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4);
- pFilterConfig->BroadcastFilter = (FunctionalState)(!(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5));
- pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
- pFilterConfig->SrcAddrInverseFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8);
- pFilterConfig->SrcAddrFiltering = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9);
- pFilterConfig->HachOrPerfectFilter = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10);
- pFilterConfig->ReceiveAllMode = (FunctionalState)(READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the source MAC Address to be matched.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param AddrNbr: The MAC address to configure
- * This parameter must be a value of the following:
- * ETH_MAC_ADDRESS1
- * ETH_MAC_ADDRESS2
- * ETH_MAC_ADDRESS3
- * @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
-{
- uint32_t macaddrhr, macaddrlr;
-
- if(pMACAddr == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Get mac addr high reg offset */
- macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
- /* Get mac addr low reg offset */
- macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
-
- /* Set MAC addr bits 32 to 47 */
- (*(__IO uint32_t *)macaddrhr) = ((pMACAddr[5] << 8) | pMACAddr[4]);
- /* Set MAC addr bits 0 to 31 */
- (*(__IO uint32_t *)macaddrlr) = ((pMACAddr[3] << 24) | (pMACAddr[2] << 16) | (pMACAddr[1] << 8) | pMACAddr[0]);
-
- /* Enable address and set source address bit */
- (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the ETH Hash Table Value.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pHashTable: pointer to a table of two 32 bit values, that contains
- * the 64 bits of the hash table.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
-{
- if(pHashTable == NULL)
- {
- return HAL_ERROR;
- }
-
- heth->Instance->MACHT0R = pHashTable[0];
- heth->Instance->MACHT1R = pHashTable[1];
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the VLAN Identifier for Rx packets
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param ComparisonBits: 12 or 16 bit comparison mode
- must be a value of @ref ETH_VLAN_Tag_Comparison
- * @param VLANIdentifier: VLAN Identifier value
- * @retval None
- */
-void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
-{
- if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
- {
- MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
- CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
- }
- else
- {
- MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
- SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
- }
-}
-
-/**
- * @brief Enters the Power down mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
- * that contains the Power Down configration
- * @retval None.
- */
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
-{
- uint32_t powerdownconfig;
-
- powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
- ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
- ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
- ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
- ETH_MACPCSR_PWRDWN);
-
- /* Enable PMT interrupt */
- __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
-
- MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
-}
-
-/**
- * @brief Exits from the Power down mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None.
- */
-void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
-{
- /* clear wake up sources */
- CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
-
- if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN))
- {
- /* Exit power down mode */
- CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
- }
-
- /* Disable PMT interrupt */
- __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
-}
-
-/**
- * @brief Set the WakeUp filter.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pFilter: pointer to filter registers values
- * @param Count: number of filter registers, must be from 1 to 8.
- * @retval None.
- */
-HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
-{
- uint32_t regindex;
-
- if(pFilter == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Reset Filter Pointer */
- SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
-
- /* Wake up packet filter config */
- for(regindex = 0; regindex < Count; regindex++)
- {
- /* Write filter regs */
- WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief ETH State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of
- ETH communication process, return Peripheral Errors occurred during communication
- process
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the ETH state.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL state
- */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
-{
- uint32_t gstate, rxstate;
- gstate = heth->gState;
- rxstate = heth->RxState;
-
- return (HAL_ETH_StateTypeDef)(gstate | rxstate);
-}
-
-/**
- * @brief Returns the ETH error code
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval ETH Error Code
- */
-uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
-{
- return heth->ErrorCode;
-}
-
-/**
- * @brief Returns the ETH DMA error code
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval ETH DMA Error Code
- */
-uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
-{
- return heth->DMAErrorCode;
-}
-
-/**
- * @brief Returns the ETH MAC error code
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval ETH MAC Error Code
- */
-uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
-{
- return heth->MACErrorCode;
-}
-
-/**
- * @brief Returns the ETH MAC WakeUp event source
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval ETH MAC WakeUp event source
- */
-uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
-{
- return heth->MACWakeUpEvent;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
-{
- uint32_t macregval;
-
- /*------------------------ MACCR Configuration --------------------*/
- macregval =(macconf->InterPacketGapVal |
- macconf->SourceAddrControl |
- (uint32_t)(macconf->ChecksumOffload << 27) |
- (uint32_t)(macconf->GiantPacketSizeLimitControl << 23) |
- (uint32_t)(macconf->Support2KPacket << 22) |
- (uint32_t)(macconf->CRCStripTypePacket << 21) |
- (uint32_t)(macconf->AutomaticPadCRCStrip << 20) |
- (uint32_t)(!macconf->Watchdog << 19) |
- (uint32_t)(!macconf->Jabber << 17) |
- (uint32_t)(macconf->JumboPacket << 16) |
- macconf->Speed |
- macconf->DuplexMode |
- (uint32_t)(macconf->LoopbackMode << 12) |
- (uint32_t)(macconf->CarrierSenseBeforeTransmit << 11)|
- (uint32_t)(!macconf->ReceiveOwn << 10)|
- (uint32_t)(macconf->CarrierSenseDuringTransmit << 9)|
- (uint32_t)(!macconf->RetryTransmission << 8)|
- macconf->BackOffLimit |
- (uint32_t)(macconf->DeferralCheck << 4)|
- macconf->PreambleLength);
-
- /* Write to MACCR */
- MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
-
- /*------------------------ MACECR Configuration --------------------*/
- macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
- (uint32_t)(macconf->ExtendedInterPacketGap << 24)|
- (uint32_t)(macconf->UnicastSlowProtocolPacketDetect << 18)|
- (uint32_t)(macconf->SlowProtocolDetect << 17)|
- (uint32_t)(!macconf->CRCCheckingRxPackets << 16) |
- macconf->GiantPacketSizeLimit);
-
- /* Write to MACECR */
- MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
-
- /*------------------------ MACWTR Configuration --------------------*/
- macregval = ((uint32_t)(macconf->ProgrammableWatchdog << 8) |
- macconf->WatchdogTimeout);
-
- /* Write to MACWTR */
- MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
-
- /*------------------------ MACTFCR Configuration --------------------*/
- macregval = ((uint32_t)(macconf->TransmitFlowControl << 1) |
- macconf->PauseLowThreshold |
- (uint32_t)(!macconf->ZeroQuantaPause << 7) |
- (macconf->PauseTime << 16));
-
- /* Write to MACTFCR */
- MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
-
- /*------------------------ MACRFCR Configuration --------------------*/
- macregval = ((uint32_t)macconf->ReceiveFlowControl |
- (uint32_t)(macconf->UnicastPausePacketDetect << 1));
-
- /* Write to MACRFCR */
- MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
-
- /*------------------------ MTLTQOMR Configuration --------------------*/
- /* Write to MTLTQOMR */
- MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
-
- /*------------------------ MTLRQOMR Configuration --------------------*/
- macregval = (macconf->ReceiveQueueMode |
- (uint32_t)(!macconf->DropTCPIPChecksumErrorPacket << 6) |
- (uint32_t)(macconf->ForwardRxErrorPacket << 4) |
- (uint32_t)(macconf->ForwardRxUndersizedGoodPacket << 3));
-
- /* Write to MTLRQOMR */
- MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
-}
-
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
-{
- uint32_t dmaregval;
-
- /*------------------------ DMAMR Configuration --------------------*/
- MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
-
- /*------------------------ DMASBMR Configuration --------------------*/
- dmaregval = ((uint32_t)(dmaconf->AddressAlignedBeats << 12) |
- dmaconf->BurstMode |
- (uint32_t)(dmaconf->RebuildINCRxBurst << 15));
-
- MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
-
- /*------------------------ DMACCR Configuration --------------------*/
- dmaregval = ((uint32_t)(dmaconf->PBLx8Mode <<16) |
- dmaconf->MaximumSegmentSize);
-
- MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
-
- /*------------------------ DMACTCR Configuration --------------------*/
- dmaregval = (dmaconf->TxDMABurstLength |
- (uint32_t)(dmaconf->SecondPacketOperate << 4)|
- (uint32_t)(dmaconf->TCPSegmentation << 12));
-
- MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
-
- /*------------------------ DMACRCR Configuration --------------------*/
- dmaregval = ((uint32_t)(dmaconf->FlushRxPacket << 31) |
- dmaconf->RxDMABurstLength);
-
- /* Write to DMACRCR */
- MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
-}
-
-/**
- * @brief Configures Ethernet MAC and DMA with default parameters.
- * called by HAL_ETH_Init() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
-{
- ETH_MACConfigTypeDef macDefaultConf;
- ETH_DMAConfigTypeDef dmaDefaultConf;
-
- /*--------------- ETHERNET MAC registers default Configuration --------------*/
- macDefaultConf.AutomaticPadCRCStrip = ENABLE;
- macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
- macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
- macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
- macDefaultConf.ChecksumOffload = ENABLE;
- macDefaultConf.CRCCheckingRxPackets = ENABLE;
- macDefaultConf.CRCStripTypePacket = ENABLE;
- macDefaultConf.DeferralCheck = DISABLE;
- macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
- macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
- macDefaultConf.ExtendedInterPacketGap = DISABLE;
- macDefaultConf.ExtendedInterPacketGapVal = 0x0;
- macDefaultConf.ForwardRxErrorPacket = DISABLE;
- macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
- macDefaultConf.GiantPacketSizeLimit = 0x618;
- macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
- macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
- macDefaultConf.Jabber = ENABLE;
- macDefaultConf.JumboPacket = DISABLE;
- macDefaultConf.LoopbackMode = DISABLE;
- macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
- macDefaultConf.PauseTime = 0x0;
- macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
- macDefaultConf.ProgrammableWatchdog = DISABLE;
- macDefaultConf.ReceiveFlowControl = DISABLE;
- macDefaultConf.ReceiveOwn = ENABLE;
- macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
- macDefaultConf.RetryTransmission = ENABLE;
- macDefaultConf.SlowProtocolDetect = DISABLE;
- macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
- macDefaultConf.Speed = ETH_SPEED_100M;
- macDefaultConf.Support2KPacket = DISABLE;
- macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
- macDefaultConf.TransmitFlowControl = DISABLE;
- macDefaultConf.UnicastPausePacketDetect = DISABLE;
- macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
- macDefaultConf.Watchdog = ENABLE;
- macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB;
- macDefaultConf.ZeroQuantaPause = ENABLE;
-
- /* MAC default configuration */
- ETH_SetMACConfig(heth, &macDefaultConf);
-
- /*--------------- ETHERNET DMA registers default Configuration --------------*/
- dmaDefaultConf.AddressAlignedBeats = ENABLE;
- dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
- dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
- dmaDefaultConf.FlushRxPacket = DISABLE;
- dmaDefaultConf.PBLx8Mode = DISABLE;
- dmaDefaultConf.RebuildINCRxBurst = DISABLE;
- dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
- dmaDefaultConf.SecondPacketOperate = DISABLE;
- dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
- dmaDefaultConf.TCPSegmentation = DISABLE;
- dmaDefaultConf.MaximumSegmentSize = 536;
-
- /* DMA default configuration */
- ETH_SetDMAConfig(heth, &dmaDefaultConf);
-}
-
-/**
- * @brief Configures the Clock range of SMI interface.
- * called by HAL_ETH_Init() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
-{
- uint32_t tmpreg, hclk;
-
- /* Get the ETHERNET MACMDIOAR value */
- tmpreg = (heth->Instance)->MACMDIOAR;
-
- /* Clear CSR Clock Range bits */
- tmpreg &= ~ETH_MACMDIOAR_CR;
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- /* Set CR bits depending on hclk value */
- if((hclk >= 20000000)&&(hclk < 35000000))
- {
- /* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
- }
- else if((hclk >= 35000000)&&(hclk < 60000000))
- {
- /* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
- }
- else if((hclk >= 60000000)&&(hclk < 100000000))
- {
- /* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
- }
- else if((hclk >= 100000000)&&(hclk < 150000000))
- {
- /* CSR Clock Range between 100-150 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
- }
- else /* (hclk >= 150000000)&&(hclk <= 200000000) */
- {
- /* CSR Clock Range between 150-200 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
- }
-
- /* Configure the CSR Clock Range */
- (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
-}
-
-/**
- * @brief Initializes the DMA Tx descriptors.
- * called by HAL_ETH_Init() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
-{
- ETH_DMADescTypeDef *dmatxdesc;
- uint32_t i;
-
- /* Fill each DMATxDesc descriptor with the right values */
- for(i=0; i < ETH_TX_DESC_CNT; i++)
- {
- dmatxdesc = heth->Init.TxDesc + i;
-
- WRITE_REG(dmatxdesc->DESC0, 0x0);
- WRITE_REG(dmatxdesc->DESC1, 0x0);
- WRITE_REG(dmatxdesc->DESC2, 0x0);
- WRITE_REG(dmatxdesc->DESC3, 0x0);
-
- WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
- }
-
- heth->TxDescList.CurTxDesc = 0;
-
- /* Set Transmit Descriptor Ring Length */
- WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
-
- /* Set Transmit Descriptor List Address */
- WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
-
- /* Set Transmit Descriptor Tail pointer */
- WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
-}
-
-/**
- * @brief Initializes the DMA Rx descriptors in chain mode.
- * called by HAL_ETH_Init() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
-{
- ETH_DMADescTypeDef *dmarxdesc;
- uint32_t i;
-
- for(i = 0; i < ETH_RX_DESC_CNT; i++)
- {
- dmarxdesc = heth->Init.RxDesc + i;
-
- WRITE_REG(dmarxdesc->DESC0, 0x0);
- WRITE_REG(dmarxdesc->DESC1, 0x0);
- WRITE_REG(dmarxdesc->DESC2, 0x0);
- WRITE_REG(dmarxdesc->DESC3, 0x0);
- WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
- WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
-
- /* Set Rx descritors adresses */
- WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
- }
-
- WRITE_REG(heth->RxDescList.CurRxDesc, 0);
- WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
- WRITE_REG(heth->RxDescList.AppDescNbr, 0);
- WRITE_REG(heth->RxDescList.ItMode, 0);
- WRITE_REG(heth->RxDescList.AppContextDesc, 0);
-
- /* Set Receive Descriptor Ring Length */
- WRITE_REG(heth->Instance->DMACRDRLR, (ETH_RX_DESC_CNT - 1));
-
- /* Set Receive Descriptor List Address */
- WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
-
- /* Set Receive Descriptor Tail pointer Address */
- WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)heth->Init.RxDesc + ((ETH_RX_DESC_CNT - 1)*sizeof(ETH_DMADescTypeDef))));
-}
-
-/**
- * @brief Prepare Tx DMA descriptor before transmission.
- * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pTxConfig: Tx packet configuration
- * @param ItMode: Enable or disable Tx EOT interrept
- * @retval Status
- */
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
-{
- ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
- uint32_t descidx = dmatxdesclist->CurTxDesc;
- uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
- uint32_t descnbr = 0, idx;
- ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
- ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
-
- /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
- {
- return HAL_ETH_ERROR_BUSY;
- }
-
- /***************************************************************************/
- /***************** Context descriptor configuration (Optional) **********/
- /***************************************************************************/
- /* If VLAN tag is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG))
- {
- /* Set vlan tag value */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
- /* Set vlan tag valid bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
- /* Set the descriptor as the vlan input source */
- SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
-
- /* if inner VLAN is enabled */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG))
- {
- /* Set inner vlan tag value */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
- /* Set inner vlan tag valid bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
-
- /* Set Vlan Tag control */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
-
- /* Set the descriptor as the inner vlan input source */
- SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
- /* Enable double VLAN processing */
- SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
- }
- }
-
- /* if tcp segementation is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
- {
- /* Set MSS value */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
- /* Set MSS valid bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
- }
-
- if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG)) || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO)))
- {
- /* Set as context descriptor */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
- /* Set own bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
- /* Increment current tx descriptor index */
- INCR_TX_DESC_INDEX(descidx, 1);
- /* Get current descriptor address */
- dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
- descnbr += 1U;
-
- /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
- {
- dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
- /* Clear own bit */
- CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
-
- return HAL_ETH_ERROR_BUSY;
- }
- }
-
- /***************************************************************************/
- /***************** Normal descriptors configuration *****************/
- /***************************************************************************/
-
- descnbr += 1U;
-
- /* Set header or buffer 1 address */
- WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
- /* Set header or buffer 1 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
-
- if(txbuffer->next != NULL)
- {
- txbuffer = txbuffer->next;
- /* Set buffer 2 address */
- WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
- /* Set buffer 2 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
- }
- else
- {
- WRITE_REG(dmatxdesc->DESC1, 0x0);
- /* Set buffer 2 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0);
- }
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
- {
- /* Set TCP Header length */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
- /* Set TCP payload length */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
- /* Set TCP Segmentation Enabled bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
- }
- else
- {
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM))
- {
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
- }
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD))
- {
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
- }
- }
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG))
- {
- /* Set Vlan Tag control */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
- }
-
- /* Mark it as First Descriptor */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
- /* Mark it as NORMAL descriptor */
- CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
- /* set OWN bit of FIRST descriptor */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
-
- /* If source address insertion/replacement is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC))
- {
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
- }
-
- /* only if the packet is splitted into more than one descriptors > 1 */
- while (txbuffer->next != NULL)
- {
- /* Increment current tx descriptor index */
- INCR_TX_DESC_INDEX(descidx, 1);
- /* Get current descriptor address */
- dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
- /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
- {
- descidx = firstdescidx;
- dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
- /* clear previous desc own bit */
- for(idx = 0; idx < descnbr; idx ++)
- {
- CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
-
- /* Increment current tx descriptor index */
- INCR_TX_DESC_INDEX(descidx, 1);
- /* Get current descriptor address */
- dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- }
-
- return HAL_ETH_ERROR_BUSY;
- }
-
- descnbr += 1U;
-
- /* Get the next Tx buffer in the list */
- txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
-
- /* Set header or buffer 1 address */
- WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
- /* Set header or buffer 1 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
-
- if (txbuffer->next != NULL)
- {
- /* Get the next Tx buffer in the list */
- txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
- /* Set buffer 2 address */
- WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
- /* Set buffer 2 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
- }
- else
- {
- WRITE_REG(dmatxdesc->DESC1, 0x0);
- /* Set buffer 2 Length */
- MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0);
- }
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO))
- {
- /* Set TCP payload length */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
- /* Set TCP Segmentation Enabled bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
- }
- else
- {
- /* Set the packet length */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
-
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM))
- {
- /* Checksum Insertion Control */
- MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
- }
- }
-
- /* Set Own bit */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
- /* Mark it as NORMAL descriptor */
- CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
- }
-
- if(ItMode != ((uint32_t)RESET))
- {
- /* Set Interrupt on completition bit */
- SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
- }
- else
- {
- /* Clear Interrupt on completition bit */
- CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
- }
-
- /* Mark it as LAST descriptor */
- SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
-
- dmatxdesclist->CurTxDesc = descidx;
-
- /* Return function status */
- return HAL_ETH_ERROR_NONE;
-}
-
-#endif /* HAL_ETH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
deleted file mode 100644
index bac9378..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_eth_ex.c
- * @author MCD Application Team
- * @brief ETH HAL Extended module driver.
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ETHEx ETHEx
- * @brief ETH HAL Extended module driver
- * @{
- */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
- * @{
- */
-#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
- ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
- ETH_MACL3L4CR_L4DPIM)
-
-#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
- ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
- ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
- ETH_MACL3L4CR_L3HDBM)
-
-#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
- ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
- ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
- ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
- ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
- ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
-
-#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
- ETH_MACVIR_VLP | ETH_MACVIR_VLC)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
- * @{
- */
-
-/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure ARP offload module
- (+) Configure L3 and L4 filters
- (+) Configure Extended VLAN features
- (+) Configure Energy Efficient Ethernet module
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables ARP Offload.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
-{
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
-}
-
-/**
- * @brief Disables ARP Offload.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
-{
- CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
-}
-
-/**
- * @brief Set the ARP Match IP address
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param IpAddress: IP Address to be matched for incoming ARP requests
- * @retval None
- */
-void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
-{
- WRITE_REG(heth->Instance->MACARPAR, IpAddress);
-}
-
-/**
- * @brief Configures the L4 Filter, this function allow to:
- * set the layer 4 protocol to be matched (TCP or UDP)
- * enable/disable L4 source/destination port perfect/inverse match.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Filter: L4 filter to configured, this parameter must be one of the following
- * ETH_L4_FILTER_0
- * ETH_L4_FILTER_1
- * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
- * that contains L4 filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
-{
- __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
- if(pL4FilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Write configuration to (MACL3L4C0R + filter )register */
- MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
- pL4FilterConfig->SrcPortFilterMatch |
- pL4FilterConfig->DestPortFilterMatch));
-
- configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
-
- /* Write configuration to (MACL4A0R + filter )register */
- MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
- (pL4FilterConfig->DestinationPort << 16)));
-
- /* Enable L4 filter */
- SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the L4 Filter, this function allow to:
- * set the layer 4 protocol to be matched (TCP or UDP)
- * enable/disable L4 source/destination port perfect/inverse match.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Filter: L4 filter to configured, this parameter must be one of the following
- * ETH_L4_FILTER_0
- * ETH_L4_FILTER_1
- * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
- * that contains L4 filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
-{
- if(pL4FilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
- pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
- pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
-
- /* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
- pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the L3 Filter, this function allow to:
- * set the layer 3 protocol to be matched (IPv4 or IPv6)
- * enable/disable L3 source/destination port perfect/inverse match.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Filter: L3 filter to configured, this parameter must be one of the following
- * ETH_L3_FILTER_0
- * ETH_L3_FILTER_1
- * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
- * that contains L3 filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
-{
- __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
- if(pL3FilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Write configuration to (MACL3L4C0R + filter )register */
- MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
- pL3FilterConfig->SrcAddrFilterMatch |
- pL3FilterConfig->DestAddrFilterMatch |
- (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
- (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
-
- /* Check if IPv6 protocol is selected */
- if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
- {
- /* Set the IPv6 address match */
- /* Set Bits[31:0] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
- /* Set Bits[63:32] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
- /* update Bits[95:64] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
- /* update Bits[127:96] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
- }
- else /* IPv4 protocol is selected */
- {
- /* Set the IPv4 source address match */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
- /* Set the IPv4 destination address match */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the L3 Filter, this function allow to:
- * set the layer 3 protocol to be matched (IPv4 or IPv6)
- * enable/disable L3 source/destination port perfect/inverse match.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Filter: L3 filter to configured, this parameter must be one of the following
- * ETH_L3_FILTER_0
- * ETH_L3_FILTER_1
- * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
- * that will contain the L3 filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
-{
- if(pL3FilterConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
- pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
- pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
- pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
- pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
-
- if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
- {
- pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
- pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
- pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
- pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
- }
- else
- {
- pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
- pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables L3 and L4 filtering process.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None.
- */
-void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
-{
- /* Enable L3/L4 filter */
- SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
-}
-
-/**
- * @brief Disables L3 and L4 filtering process.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None.
- */
-void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
-{
- /* Disable L3/L4 filter */
- CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
-}
-
-/**
- * @brief Get the VLAN Configuration for Receive Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
- * that will contain the VLAN filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
-{
- if(pVlanConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- pVlanConfig->InnerVLANTagInStatus = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31);
- pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
- pVlanConfig->InnerVLANTag = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27);
- pVlanConfig->DoubleVLANProcessing = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26);
- pVlanConfig->VLANTagHashTableMatch = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25);
- pVlanConfig->VLANTagInStatus = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24);
- pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
- pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
- pVlanConfig->VLANTagInverceMatch = (FunctionalState)(READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the VLAN Configuration for Receive Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
- * that contains VLAN filter configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
-{
- if(pVlanConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Write config to MACVTR */
- MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, ((uint32_t)(pVlanConfig->InnerVLANTagInStatus << 31) |
- pVlanConfig->StripInnerVLANTag |
- (uint32_t)(pVlanConfig->InnerVLANTag << 27) |
- (uint32_t)(pVlanConfig->DoubleVLANProcessing << 26) |
- (uint32_t)(pVlanConfig->VLANTagHashTableMatch << 25) |
- (uint32_t)(pVlanConfig->VLANTagInStatus << 24) |
- pVlanConfig->StripVLANTag |
- pVlanConfig->VLANTypeCheck |
- (uint32_t)(pVlanConfig->VLANTagInverceMatch << 17)));
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the VLAN Hash Table
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param VLANHashTable: VLAN hash table 16 bit value
- * @retval None
- */
-void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
-{
- MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
-}
-
-/**
- * @brief Get the VLAN Configuration for Transmit Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
- * ETH_OUTER_TX_VLANTAG
- * ETH_INNER_TX_VLANTAG
- * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
- * that will contain the Tx VLAN filter configuration.
- * @retval HAL Status.
- */
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
-{
- if (pVlanConfig == NULL)
- {
- return HAL_ERROR;
- }
-
- if(VLANTag == ETH_INNER_TX_VLANTAG)
- {
- pVlanConfig->SourceTxDesc = (FunctionalState)(READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20);
- pVlanConfig->SVLANType = (FunctionalState)(READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19);
- pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
- }
- else
- {
- pVlanConfig->SourceTxDesc = (FunctionalState)(READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20);
- pVlanConfig->SVLANType = (FunctionalState)(READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19);
- pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
- }
-
- return HAL_OK;;
-}
-
-/**
- * @brief Set the VLAN Configuration for Transmit Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
- * ETH_OUTER_TX_VLANTAG
- * ETH_INNER_TX_VLANTAG
- * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
- * that contains Tx VLAN filter configuration.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
-{
- if(VLANTag == ETH_INNER_TX_VLANTAG)
- {
- MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, ((uint32_t)(pVlanConfig->SourceTxDesc << 20) |
- (uint32_t)(pVlanConfig->SVLANType << 19) |
- pVlanConfig->VLANTagControl));
- /* Enable Double VLAN processing */
- SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
- }
- else
- {
- MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, ((uint32_t)(pVlanConfig->SourceTxDesc << 20) |
- (uint32_t)(pVlanConfig->SVLANType << 19) |
- pVlanConfig->VLANTagControl));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the VLAN Tag Identifier for Transmit Packets.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
- * ETH_OUTER_TX_VLANTAG
- * ETH_INNER_TX_VLANTAG
- * @param VLANIdentifier: VLAN Identifier 16 bit value
- * @retval None
- */
-void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
-{
- if(VLANTag == ETH_INNER_TX_VLANTAG)
- {
- MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
- }
- else
- {
- MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
- }
-}
-
-/**
- * @brief Enables the VLAN Tag Filtering process.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None.
- */
-void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
-{
- /* Enable VLAN processing */
- SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
-}
-
-/**
- * @brief Disables the VLAN Tag Filtering process.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None.
- */
-void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
-{
- /* Disable VLAN processing */
- CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
-}
-
-/**
- * @brief Enters the Low Power Idle (LPI) mode
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param TxAutomate: Enable/Disbale automate enter/exit LPI mode.
- * @param TxClockStop: Enable/Disbale Tx clock stop in LPI mode.
- * @retval None
- */
-void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
-{
- /* Enable LPI Interrupts */
- __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
-
- /* Write to LPI Control register: Enter low power mode */
- MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
- ((uint32_t)TxClockStop << 21) |
- ETH_MACLCSR_LPIEN));
-}
-
-/**
- * @brief Exits the Low Power Idle (LPI) mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
-{
- /* Clear the LPI Config and exit low power mode */
- CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
-
- /* Enable LPI Interrupts */
- __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
-}
-
-
-/**
- * @brief Returns the ETH MAC LPI event
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval ETH MAC WakeUp event
- */
-uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
-{
- return heth->MACLPIEvent;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_ETH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
deleted file mode 100644
index c4b4c6a..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
+++ /dev/null
@@ -1,4773 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_fdcan.c
- * @author MCD Application Team
- * @brief FDCAN HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Flexible DataRate Controller Area Network
- * (FDCAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Configuration and Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
-
- (#) If needed , configure the reception filters and optional features using
- the following configuration functions:
- (++) HAL_FDCAN_ConfigClockCalibration
- (++) HAL_FDCAN_ConfigFilter
- (++) HAL_FDCAN_ConfigGlobalFilter
- (++) HAL_FDCAN_ConfigExtendedIdMask
- (++) HAL_FDCAN_ConfigRxFifoOverwrite
- (++) HAL_FDCAN_ConfigFifoWatermark
- (++) HAL_FDCAN_ConfigRamWatchdog
- (++) HAL_FDCAN_ConfigTimestampCounter
- (++) HAL_FDCAN_EnableTimestampCounter
- (++) HAL_FDCAN_DisableTimestampCounter
- (++) HAL_FDCAN_ConfigTimeoutCounter
- (++) HAL_FDCAN_EnableTimeoutCounter
- (++) HAL_FDCAN_DisableTimeoutCounter
- (++) HAL_FDCAN_ConfigTxDelayCompensation
- (++) HAL_FDCAN_EnableTxDelayCompensation
- (++) HAL_FDCAN_DisableTxDelayCompensation
- (++) HAL_FDCAN_TT_ConfigOperation
- (++) HAL_FDCAN_TT_ConfigReferenceMessage
- (++) HAL_FDCAN_TT_ConfigTrigger
-
- (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
- the node is active on the bus: it can send and receive messages.
-
- (#) The following Tx control functions can only be called when the FDCAN
- module is started:
- (++) HAL_FDCAN_AddMessageToTxFifoQ
- (++) HAL_FDCAN_EnableTxBufferRequest
- (++) HAL_FDCAN_AbortTxRequest
-
- (#) When a message is received into the FDCAN message RAM, it can be
- retrieved using the HAL_FDCAN_GetRxMessage function.
-
- (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
- it to initialization mode and re-enabling access to configuration
- registers through the configuration functions listed here above.
-
- (#) All other control functions can be called any time after initialization
- phase, no matter if the FDCAN module is started or stoped.
-
- *** Polling mode operation ***
- ==============================
-
- [..]
- (#) Reception and transmission states can be monitored via the following
- functions:
- (++) HAL_FDCAN_IsRxBufferMessageAvailable
- (++) HAL_FDCAN_IsTxBufferMessagePending
- (++) HAL_FDCAN_GetRxFifoFillLevel
- (++) HAL_FDCAN_GetTxFifoFreeLevel
-
- *** Interrupt mode operation ***
- ================================
- [..]
- (#) There are two interrupt lines: line 0 and 1.
- By default, all interrupts are assigned to line 0. Interrupt lines
- can be configured using HAL_FDCAN_ConfigInterruptLines function.
-
- (#) Notifications are activated using HAL_FDCAN_ActivateNotification
- function. Then, the process can be controlled through one of the
- available user callbacks: HAL_FDCAN_xxxCallback.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FDCAN FDCAN
- * @brief FDCAN HAL module driver
- * @{
- */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FDCAN_Private_Constants
- * @{
- */
-#define FDCAN_TIMEOUT_VALUE 10
-
-#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
-#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
-#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
-#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO | \
- FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
-#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
-#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
-#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
-#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
- FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
-#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
-
-#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
-#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
-#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
-#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
-#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
-#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
-#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
-#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
-#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
-#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
-#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
-#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
-#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
-#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
-static const uint8_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FDCAN_Private_Functions_Prototypes
- * @{
- */
-static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static HAL_StatusTypeDef FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
- * @{
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the FDCAN.
- (+) De-initialize the FDCAN.
- (+) Enter FDCAN peripheral in power down mode.
- (+) Exit power down mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FDCAN peripheral according to the specified
- * parameters in the FDCAN_InitTypeDef structure.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef* hfdcan)
-{
- uint32_t tickstart = 0U;
-
- /* Check FDCAN handle */
- if(hfdcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check FDCAN instance */
- if(hfdcan->Instance == FDCAN1)
- {
- hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100);
- }
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
- assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
- assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
- assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
- assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
- assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
- assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
- if(hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
- {
- assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
- assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
- assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
- assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
- }
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128));
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64));
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64));
- if(hfdcan->Init.RxFifo0ElmtsNbr > 0)
- {
- assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
- }
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64));
- if(hfdcan->Init.RxFifo1ElmtsNbr > 0)
- {
- assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
- }
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64));
- if(hfdcan->Init.RxBuffersNbr > 0)
- {
- assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
- }
- assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32));
- assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32));
- if(hfdcan->Init.TxFifoQueueElmtsNbr > 0)
- {
- assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
- }
- if((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0)
- {
- assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
- }
-
- if(hfdcan->State == HAL_FDCAN_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hfdcan->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_FDCAN_MspInit(hfdcan);
- }
-
- /* Exit from Sleep mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check Sleep mode acknowledge */
- while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
- {
- if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Request initialisation */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the INIT bit into CCCR register is set */
- while((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable configuration change */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
-
- /* Set the no automatic retransmission */
- if(hfdcan->Init.AutoRetransmission == ENABLE)
- {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
- }
- else
- {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
- }
-
- /* Set the transmit pause feature */
- if(hfdcan->Init.TransmitPause == ENABLE)
- {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
- }
- else
- {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
- }
-
- /* Set the Protocol Exception Handling */
- if(hfdcan->Init.ProtocolException == ENABLE)
- {
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
- }
- else
- {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
- }
-
- /* Set FDCAN Frame Format */
- MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
-
- /* Set FDCAN Operating Mode:
- | Normal | Restricted | Bus | Internal | External
- | | Operation | Monitoring | LoopBack | LoopBack
- CCCR.TEST | 0 | 0 | 0 | 1 | 1
- CCCR.MON | 0 | 0 | 1 | 1 | 0
- TEST.LBCK | 0 | 0 | 0 | 1 | 1
- CCCR.ASM | 0 | 1 | 0 | 0 | 0
- */
- if(hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
- {
- /* Enable Restricted Operation mode */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
- }
- else if(hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
- {
- if(hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
- {
- /* Enable write access to TEST register */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
-
- /* Enable LoopBack mode */
- SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
-
- if(hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
- {
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
- }
- }
- else
- {
- /* Enable bus monitoring mode */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
- }
- }
-
- /* Set the nominal bit timing register */
- hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1) << 25) | \
- (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1) << 8) | \
- ((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1) | \
- (((uint32_t)hfdcan->Init.NominalPrescaler - 1) << 16));
-
- /* If FD operation with BRS is selected, set the data bit timing register */
- if(hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
- {
- hfdcan->Instance->DBTP = (((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1) | \
- (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1) << 8) | \
- (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1) << 4) | \
- (((uint32_t)hfdcan->Init.DataPrescaler - 1) << 16));
- }
-
- if(hfdcan->Init.TxFifoQueueElmtsNbr > 0)
- {
- /* Select between Tx FIFO and Tx Queue operation modes */
- SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
- }
-
- /* Configure Tx element size */
- if((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0)
- {
- MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
- }
-
- /* Configure Rx FIFO 0 element size */
- if(hfdcan->Init.RxFifo0ElmtsNbr > 0)
- {
- MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, CvtEltSize[hfdcan->Init.RxFifo0ElmtSize]);
- }
-
- /* Configure Rx FIFO 1 element size */
- if(hfdcan->Init.RxFifo1ElmtsNbr > 0)
- {
- MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << 4));
- }
-
- /* Configure Rx buffer element size */
- if(hfdcan->Init.RxBuffersNbr > 0)
- {
- MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << 8));
- }
-
- /* By default operation mode is set to Event-driven communication.
- If Time-triggered communication is needed, user should call the
- HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
- if(hfdcan->Instance == FDCAN1)
- {
- CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
- }
-
- /* Calculate each RAM block address */
- FDCAN_CalcultateRamBlockAddresses(hfdcan);
-
- /* Initialize the error code */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Initialize the FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the FDCAN peripheral registers to their default reset values.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef* hfdcan)
-{
- /* Check FDCAN handle */
- if(hfdcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
-
- /* Stop the FDCAN module */
- HAL_FDCAN_Stop(hfdcan);
-
- /* DeInit the low level hardware */
- HAL_FDCAN_MspDeInit(hfdcan);
-
- /* Reset the FDCAN ErrorCode */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FDCAN MSP.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the FDCAN MSP.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Enter FDCAN peripheral in sleep mode.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t tickstart = 0U;
-
- /* Request clock stop */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FDCAN is ready for power down */
- while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == RESET)
- {
- if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Exit power down mode.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t tickstart = 0U;
-
- /* Reset clock stop request */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FDCAN exits sleep mode */
- while((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
- {
- if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enter normal operation */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
- * @brief FDCAN Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Configuration functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_ConfigClockCalibration : Configure the FDCAN clock calibration unit
- (+) HAL_FDCAN_GetClockCalibrationState : Get the clock calibration state
- (+) HAL_FDCAN_ResetClockCalibrationState : Reset the clock calibration state
- (+) HAL_FDCAN_GetClockCalibrationCounter : Get the clock calibration counters values
- (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters
- (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter
- (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask
- (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode
- (+) HAL_FDCAN_ConfigFifoWatermark : Configure the FIFO watermark
- (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
- (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter
- (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter
- (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter
- (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value
- (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero
- (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter
- (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
- (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter
- (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value
- (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value
- (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation
- (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation
- (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the FDCAN clock calibration unit according to the specified
- * parameters in the FDCAN_ClkCalUnitTypeDef structure.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param sCcuConfig: pointer to an FDCAN_ClkCalUnitTypeDef structure that
- * contains the clock calibration information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef* hfdcan, FDCAN_ClkCalUnitTypeDef* sCcuConfig)
-{
- /* Check function parameters */
- assert_param(IS_FUNCTIONAL_STATE(sCcuConfig->ClockCalibration));
- if(sCcuConfig->ClockCalibration == DISABLE)
- {
- assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
- }
- else
- {
- assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFF));
- assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
- assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4));
- assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25));
- assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFF));
- }
-
- /* FDCAN1 should be initialized in order to use clock calibration */
- if(hfdcan->Instance != FDCAN1)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- if(sCcuConfig->ClockCalibration == DISABLE)
- {
- /* Bypass clock calibration */
- SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
-
- /* Configure clock divider */
- MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
- }
- else /* sCcuConfig->ClockCalibration == ENABLE */
- {
- /* Clock calibration unit generates time quanta clock */
- CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
-
- /* Configure clock calibration unit */
- MODIFY_REG(FDCAN_CCU->CCFG,
- (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
- (sCcuConfig->TimeQuantaPerBitTime | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << 8)));
-
- /* Configure the start value of the calibration watchdog counter */
- MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get the clock calibration state.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval State: clock calibration state (can be a value of @arg FDCAN_calibration_state)
- */
-uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan)
-{
- return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
-}
-
-/**
- * @brief Reset the clock calibration state.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef* hfdcan)
-{
- /* Calibration software reset */
- SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Get the clock calibration counter value.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param Counter: clock calibration counter.
- * This parameter can be a value of @arg FDCAN_calibration_counter.
- * @retval Value: clock calibration counter value
- */
-uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef* hfdcan, uint32_t Counter)
-{
- if(Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
- {
- return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> 18);
- }
- else if(Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
- {
- return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
- }
- else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
- {
- return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> 16);
- }
-}
-
-/**
- * @brief Configure the FDCAN reception filter according to the specified
- * parameters in the FDCAN_FilterTypeDef structure.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param sFilterConfig: pointer to an FDCAN_FilterTypeDef structure that
- * contains the filter configuration information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef* hfdcan, FDCAN_FilterTypeDef* sFilterConfig)
-{
- uint32_t FilterElementW1;
- uint32_t FilterElementW2;
- uint32_t *FilterAddress;
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check function parameters */
- assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
- assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
- if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
- {
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1));
- }
-
- if(sFilterConfig->IdType == FDCAN_STANDARD_ID)
- {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1)));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FF));
- if(sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
- {
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FF));
- assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
- }
-
- /* Build filter element */
- if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
- {
- FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27) |
- (sFilterConfig->FilterID1 << 16) |
- (sFilterConfig->IsCalibrationMsg << 8) |
- sFilterConfig->RxBufferIndex );
- }
- else
- {
- FilterElementW1 = ((sFilterConfig->FilterType << 30) |
- (sFilterConfig->FilterConfig << 27) |
- (sFilterConfig->FilterID1 << 16) |
- sFilterConfig->FilterID2 );
- }
-
- /* Calculate filter address */
- FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4));
-
- /* Write filter element to the message RAM */
- *FilterAddress = FilterElementW1;
- }
- else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
- {
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1)));
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFF));
- if(sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
- {
- assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFF));
- assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
- }
-
- /* Build first word of filter element */
- FilterElementW1 = ((sFilterConfig->FilterConfig << 29) | sFilterConfig->FilterID1);
-
- /* Build second word of filter element */
- if(sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
- {
- FilterElementW2 = sFilterConfig->RxBufferIndex;
- }
- else
- {
- FilterElementW2 = ((sFilterConfig->FilterType << 30) | sFilterConfig->FilterID2);
- }
-
- /* Calculate filter address */
- FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4 * 2));
-
- /* Write filter element to the message RAM */
- *FilterAddress++ = FilterElementW1;
- *FilterAddress = FilterElementW2;
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the FDCAN global filter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param NonMatchingStd: Defines how received messages with 11-bit IDs that
- do not match any element of the filter list are treated.
- This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
- * @param NonMatchingExt: Defines how received messages with 29-bit IDs that
- do not match any element of the filter list are treated.
- This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
- * @param RejectRemoteStd: Enable or disable the remote standard frames rejection.
- This parameter can be set to ENABLE or DISABLE.
- * @param RejectRemoteExt: Enable or disable the remote extended frames rejection.
- This parameter can be set to ENABLE or DISABLE.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
- uint32_t NonMatchingStd,
- uint32_t NonMatchingExt,
- uint32_t RejectRemoteStd,
- uint32_t RejectRemoteExt)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
- assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
- assert_param(IS_FUNCTIONAL_STATE(RejectRemoteStd));
- assert_param(IS_FUNCTIONAL_STATE(RejectRemoteExt));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure global filter */
- hfdcan->Instance->GFC = ((NonMatchingStd << 4U) | (NonMatchingExt << 2U) | (RejectRemoteStd << 1U) | RejectRemoteExt);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the extended ID mask.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param Mask: Extended ID Mask.
- This parameter must be a number between 0 and 0x1FFFFFFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFF));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure the extended ID mask */
- hfdcan->Instance->XIDAM = Mask;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the Rx FIFO operation mode.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo: Rx FIFO.
- * This parameter can be one of the following values:
- * @arg FDCAN_RX_FIFO0: Rx FIFO 0
- * @arg FDCAN_RX_FIFO1: Rx FIFO 1
- * @param OperationMode: operation mode.
- * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_RX_FIFO(RxFifo));
- assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- if(RxFifo == FDCAN_RX_FIFO0)
- {
- /* Select FIFO 0 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
- }
- else /* RxFifo == FDCAN_RX_FIFO1 */
- {
- /* Select FIFO 1 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the FIFO watermark.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param FIFO: select the FIFO to be configured.
- * This parameter can be a value of @arg FDCAN_FIFO_watermark.
- * @param Watermark: level for FIFO watermark interrupt.
- * This parameter must be a number between:
- * - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
- * - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
- if(FIFO == FDCAN_CFG_TX_EVENT_FIFO)
- {
- assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32));
- }
- else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
- {
- assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64));
- }
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Set the level for FIFO watermark interrupt */
- if(FIFO == FDCAN_CFG_TX_EVENT_FIFO)
- {
- MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << 24));
- }
- else if(FIFO == FDCAN_CFG_RX_FIFO0)
- {
- MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << 24));
- }
- else /* FIFO == FDCAN_CFG_RX_FIFO1 */
- {
- MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << 24));
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the RAM watchdog.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param CounterStartValue: Start value of the Message RAM Watchdog Counter,
- * This parameter must be a number between 0x00 and 0xFF,
- * with the reset value of 0x00 the counter is disabled.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFF));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure the RAM watchdog counter start value */
- MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the timestamp counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimestampPrescaler: Timestamp Counter Prescaler.
- * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure prescaler */
- MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the timestamp counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimestampOperation: Timestamp counter operation.
- * This parameter can be a value of @arg FDCAN_Timestamp.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Enable timestamp counter */
- MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the timestamp counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Disable timestamp counter */
- CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get the timestamp counter value.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Value: Timestamp counter value
- */
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- return (uint16_t)(hfdcan->Instance->TSCV);
-}
-
-/**
- * @brief Reset the timestamp counter to zero.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- if((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
- {
- /* Reset timestamp counter.
- Actually any write operation to TSCV clears the counter */
- CLEAR_REG(hfdcan->Instance->TSCV);
- }
- else
- {
- /* Update error code.
- Unable to reset external counter */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the timeout counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimeoutOperation: Timeout counter operation.
- * This parameter can be a value of @arg FDCAN_Timeout_Operation.
- * @param TimeoutPeriod: Start value of the timeout down-counter.
- * This parameter must be a number between 0x0000 and 0xFFFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
- assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFF));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Select timeout operation and configure period */
- MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << 16)));
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the timeout counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Enable timeout counter */
- SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the timeout counter.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Disable timeout counter */
- CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get the timeout counter value.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Value: Timeout counter value
- */
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- return (uint16_t)(hfdcan->Instance->TOCV);
-}
-
-/**
- * @brief Reset the timeout counter to its start value.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
-{
- if((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) != FDCAN_TIMEOUT_CONTINUOUS)
- {
- /* Reset timestamp counter to start value */
- CLEAR_REG(hfdcan->Instance->TOCV);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Unable to reset counter: controlled only by FIFO empty state */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the transmitter delay compensation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TdcOffset: Transmitter Delay Compensation Offset.
- * This parameter must be a number between 0x00 and 0xFF.
- * @param TdcFilter: Transmitter Delay Compensation Filter Window Length.
- * This parameter must be a number between 0x00 and 0xFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0xFF));
- assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0xFF));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure TDC offset and filter window */
- hfdcan->Instance->TDCR = (TdcFilter | (TdcOffset << 8));
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the transmitter delay compensation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Enable transmitter delay compensation */
- SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable the transmitter delay compensation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Disable transmitter delay compensation */
- CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
-@verbatim
- ==============================================================================
- ##### Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_Start : Start the FDCAN module
- (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
- (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
- (+) HAL_FDCAN_AddMessageToTxBuffer : Add a message to a dedicated Tx buffer
- (+) HAL_FDCAN_EnableTxBufferRequest : Enable transmission request
- (+) HAL_FDCAN_AbortTxRequest : Abort transmission request
- (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
- (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
- (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
- (+) HAL_FDCAN_GetProtocolStatus : Get protocol status
- (+) HAL_FDCAN_GetErrorCounters : Get error counter values
- (+) HAL_FDCAN_IsRxBufferMessageAvailable : Check if a new message is received in the selected Rx buffer
- (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer
- (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
- (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
- (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
- (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the FDCAN module.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Change FDCAN peripheral state */
- hfdcan->State = HAL_FDCAN_STATE_BUSY;
-
- /* Request leave initialisation */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Reset the FDCAN ErrorCode */
- hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Stop the FDCAN module and enable access to configuration registers.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
- {
- /* Request initialisation */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
-
- /* Wait until the INIT bit into CCCR register is set */
- while((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable configuration change */
- SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
-
- /* Change FDCAN peripheral state */
- hfdcan->State = HAL_FDCAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
- * @param pTxData: pointer to a buffer containing the payload of the Tx frame.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
-{
- uint32_t PutIndex;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
- if(pTxHeader->IdType == FDCAN_STANDARD_ID)
- {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FF));
- }
- else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
- {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFF));
- }
- assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
- assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
- assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
- assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
- assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
- assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFF));
-
- if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
- {
- /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
- if((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Check that the Tx FIFO/Queue is not full */
- if((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Retrieve the Tx FIFO PutIndex */
- PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> 16);
-
- /* Add the message to the Tx FIFO/Queue */
- FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
-
- /* Activate the corresponding transmission request */
- hfdcan->Instance->TXBAR = (1 << PutIndex);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Add a message to a dedicated Tx buffer
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
- * @param pTxData: pointer to a buffer containing the payload of the Tx frame.
- * @param BufferIndex: index of the buffer to be configured.
- * This parameter can be a value of @arg FDCAN_Tx_location.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
- if(pTxHeader->IdType == FDCAN_STANDARD_ID)
- {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FF));
- }
- else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
- {
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFF));
- }
- assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
- assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
- assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
- assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
- assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
- assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
- assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFF));
- assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the selected buffer has an allocated area into the RAM */
- if(POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> 16))
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Check that there is no transmittion request pending for the selected buffer */
- if((hfdcan->Instance->TXBRP & BufferIndex) != 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
-
- return HAL_ERROR;
- }
- else
- {
- /* Add the message to the Tx buffer */
- FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable transmission request.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndex: buffer index.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
- {
- /* Add transmission request */
- hfdcan->Instance->TXBAR = BufferIndex;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Abort transmission request
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndex: buffer index.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
-{
- if(hfdcan->State == HAL_FDCAN_STATE_BUSY)
- {
- /* Add cancellation request */
- hfdcan->Instance->TXBCR = BufferIndex;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxLocation: Location of the received message to be read.
- This parameter can be a value of @arg FDCAN_Rx_location.
- * @param pRxHeader: pointer to a FDCAN_RxHeaderTypeDef structure.
- * @param pRxData: pointer to a buffer where the payload of the Rx frame will be stored.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
-{
- uint32_t *RxAddress;
- uint8_t *pData;
- uint32_t ByteCounter;
- uint32_t GetIndex = 0;
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if(RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
- {
- /* Check that the Rx FIFO 0 has an allocated area into the RAM */
- if((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Check that the Rx FIFO 0 is not empty */
- if((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Calculate Rx FIFO 0 element address */
- GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> 8);
- RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4));
- }
- }
- else if(RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
- {
- /* Check that the Rx FIFO 1 has an allocated area into the RAM */
- if((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Check that the Rx FIFO 0 is not empty */
- if((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Calculate Rx FIFO 1 element address */
- GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> 8);
- RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4));
- }
- }
- else /* Rx element is assigned to a dedicated Rx buffer */
- {
- /* Check that the selected buffer has an allocated area into the RAM */
- if(RxLocation >= hfdcan->Init.RxBuffersNbr)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Calculate Rx buffer address */
- RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4));
- }
- }
-
- /* Retrieve IdType */
- pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
-
- /* Retrieve Identifier */
- if(pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
- {
- pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
- }
- else /* Extended ID element */
- {
- pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
- }
-
- /* Retrieve RxFrameType */
- pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
-
- /* Retrieve ErrorStateIndicator */
- pRxHeader->ErrorStateIndicator = (*RxAddress++ & FDCAN_ELEMENT_MASK_ESI);
-
- /* Retrieve RxTimestamp */
- pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
-
- /* Retrieve DataLength */
- pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
-
- /* Retrieve BitRateSwitch */
- pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
-
- /* Retrieve FDFormat */
- pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
-
- /* Retrieve FilterIndex */
- pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
-
- /* Retrieve NonMatchingFrame */
- pRxHeader->IsFilterMatchingFrame = ((*RxAddress++ & FDCAN_ELEMENT_MASK_ANMF) >> 31);
-
- /* Retrieve Rx payload */
- pData = (uint8_t *)RxAddress;
- for(ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
- {
- *pRxData++ = *pData++;
- }
-
- if(RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
- {
- /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
- hfdcan->Instance->RXF0A = GetIndex;
- }
- else if(RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
- {
- /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
- hfdcan->Instance->RXF1A = GetIndex;
- }
- else /* Rx element is assigned to a dedicated Rx buffer */
- {
- /* Clear the New Data flag of the current Rx buffer */
- if(RxLocation < FDCAN_RX_BUFFER32)
- {
- hfdcan->Instance->NDAT1 = (1 << RxLocation);
- }
- else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
- {
- hfdcan->Instance->NDAT2 = (1 << (RxLocation - 0x20));
- }
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxEvent: pointer to a FDCAN_TxEventFifoTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
-{
- uint32_t *TxEventAddress;
- uint32_t GetIndex;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the Tx Event FIFO has an allocated area into the RAM */
- if((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Check that the Tx event FIFO is not empty */
- if((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
-
- /* Calculate Tx event FIFO element address */
- GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> 8);
- TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2 * 4));
-
- /* Retrieve IdType */
- pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
-
- /* Retrieve Identifier */
- if(pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
- {
- pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
- }
- else /* Extended ID element */
- {
- pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
- }
-
- /* Retrieve RxFrameType */
- pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
-
- /* Retrieve ErrorStateIndicator */
- pTxEvent->ErrorStateIndicator = (*TxEventAddress++ & FDCAN_ELEMENT_MASK_ESI);
-
- /* Retrieve RxTimestamp */
- pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
-
- /* Retrieve DataLength */
- pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
-
- /* Retrieve BitRateSwitch */
- pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
-
- /* Retrieve FDFormat */
- pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
-
- /* Retrieve EventType */
- pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
-
- /* Retrieve MessageMarker */
- pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
-
- /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
- hfdcan->Instance->TXEFA = GetIndex;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get high priority message status.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param HpMsgStatus: pointer to an FDCAN_HpMsgStatusTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
-{
- HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> 15);
- HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> 8);
- HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
- HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Get protocol status.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ProtocolStatus: pointer to an FDCAN_ProtocolStatusTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
-{
- uint32_t StatusReg;
-
- /* Read the protocol status register */
- StatusReg = READ_REG(hfdcan->Instance->PSR);
-
- /* Fill the protocol status structure */
- ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
- ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> 8);
- ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
- ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> 5);
- ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> 6);
- ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> 7);
- ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> 11);
- ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> 12);
- ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> 13);
- ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> 14);
- ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> 16);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Get error counter values.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ErrorCounters: pointer to an FDCAN_ErrorCountersTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
-{
- uint32_t CountersReg;
-
- /* Read the error counters register */
- CountersReg = READ_REG(hfdcan->Instance->ECR);
-
- /* Fill the error counters structure */
- ErrorCounters->TxErrorCnt = (CountersReg & FDCAN_ECR_TEC);
- ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> 8);
- ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> 15);
- ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> 16);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Check if a new message is received in the selected Rx buffer.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxBufferIndex: Rx buffer index.
- * This parameter must be a number between 0 and 63.
- * @retval Status:
- * - 0 : No new message on RxBufferIndex.
- * - 1 : New message received on RxBufferIndex.
- */
-uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63));
-
- /* Check new message reception on the selected buffer */
- if(((RxBufferIndex < 32) && ((hfdcan->Instance->NDAT1 & (1 << RxBufferIndex)) == 0)) ||
- ((RxBufferIndex >= 32) && ((hfdcan->Instance->NDAT2 & (1 << (RxBufferIndex - 0x20))) == 0)))
- {
- return 0;
- }
-
- /* Clear the New Data flag of the current Rx buffer */
- if(RxBufferIndex < 32)
- {
- hfdcan->Instance->NDAT1 = (1 << RxBufferIndex);
- }
- else /* 32 <= RxBufferIndex <= 63 */
- {
- hfdcan->Instance->NDAT2 = (1 << (RxBufferIndex - 0x20));
- }
-
- return 1;
-}
-
-/**
- * @brief Check if a transmission request is pending on the selected Tx buffer.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TxBufferIndex: Tx buffer index.
- * This parameter can be a value of @arg FDCAN_Tx_location.
- * @retval Status:
- * - 0 : No pending transmission request on RxBufferIndex.
- * - 1 : Pending transmission request on RxBufferIndex.
- */
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TX_LOCATION(TxBufferIndex));
-
- /* Check pending transmittion request on the selected buffer */
- if((hfdcan->Instance->TXBRP & TxBufferIndex) == 0)
- {
- return 0;
- }
- return 1;
-}
-
-/**
- * @brief Return Rx FIFO fill level.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo: Rx FIFO.
- * This parameter can be one of the following values:
- * @arg FDCAN_RX_FIFO0: Rx FIFO 0
- * @arg FDCAN_RX_FIFO1: Rx FIFO 1
- * @retval Level: Rx FIFO fill level.
- */
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
-{
- uint32_t FillLevel;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_RX_FIFO(RxFifo));
-
- if(RxFifo == FDCAN_RX_FIFO0)
- {
- FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
- }
- else /* RxFifo == FDCAN_RX_FIFO1 */
- {
- FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
- }
-
- /* Return Rx FIFO fill level */
- return FillLevel;
-}
-
-/**
- * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
- * elements starting from Tx FIFO GetIndex.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Level: Tx FIFO free level.
- */
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t FreeLevel;
-
- FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
-
- /* Return Tx FIFO free level */
- return FreeLevel;
-}
-
-/**
- * @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval Status:
- * - 0 : Normal FDCAN operation.
- * - 1 : Restricted Operation Mode active.
- */
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t OperationMode;
-
- /* Get Operation Mode */
- OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> 2);
-
- return OperationMode;
-}
-
-/**
- * @brief Exit Restricted Operation Mode.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
-{
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Exit Restricted Operation mode */
- CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
- * @brief TT Configuration and control functions
- *
-@verbatim
- ==============================================================================
- ##### TT Configuration and control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_TT_ConfigOperation : Initialize TT operation parameters
- (+) HAL_FDCAN_TT_ConfigReferenceMessage : Configure the reference message
- (+) HAL_FDCAN_TT_ConfigTrigger : Configure the FDCAN trigger
- (+) HAL_FDCAN_TT_SetGlobalTime : Schedule global time adjustment
- (+) HAL_FDCAN_TT_SetClockSynchronization : Schedule TUR numerator update
- (+) HAL_FDCAN_TT_ConfigStopWatch : Configure stop watch source and polarity
- (+) HAL_FDCAN_TT_ConfigRegisterTimeMark : Configure register time mark pulse generation
- (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse : Enable register time mark pulse generation
- (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse : Disable register time mark pulse generation
- (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse : Enable trigger time mark pulse generation
- (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse : Disable trigger time mark pulse generation
- (+) HAL_FDCAN_TT_EnableHardwareGapControl : Enable gap control by input pin fdcan1_evt
- (+) HAL_FDCAN_TT_DisableHardwareGapControl : Disable gap control by input pin fdcan1_evt
- (+) HAL_FDCAN_TT_EnableTimeMarkGapControl : Enable gap control (finish only) by register time mark interrupt
- (+) HAL_FDCAN_TT_DisableTimeMarkGapControl : Disable gap control by register time mark interrupt
- (+) HAL_FDCAN_TT_SetNextIsGap : Transmit next reference message with Next_is_Gap = "1"
- (+) HAL_FDCAN_TT_SetEndOfGap : Finish a Gap by requesting start of reference message
- (+) HAL_FDCAN_TT_ConfigExternalSyncPhase : Configure target phase used for external synchronization
- (+) HAL_FDCAN_TT_EnableExternalSynchronization : Synchronize the phase of the FDCAN schedule to an external schedule
- (+) HAL_FDCAN_TT_DisableExternalSynchronization : Disable external schedule synchronization
- (+) HAL_FDCAN_TT_GetOperationStatus : Get TT operation status
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize TT operation parameters.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTTParams: pointer to a FDCAN_TT_ConfigTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
-{
- uint32_t tickstart = 0U;
- uint32_t RAMcounter;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
- assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
- assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
- assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7));
- assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127));
- assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64));
- assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
- assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
- assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
- if(pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
- {
- assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
- }
- if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
- assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255));
- assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
- assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
- assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095));
- }
- if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
- {
- assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
- assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
- assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
- assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
- }
- else
- {
- assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
- }
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Stop local time in order to enable write access to the other bits of TURCF register */
- CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the ELT bit into TURCF register is reset */
- while((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Configure TUR (Time Unit Ratio) */
- MODIFY_REG(hfdcan->ttcan->TURCF,
- (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
- ((pTTParams->TURNumerator - 0x10000) | (pTTParams->TURDenominator << 16)));
-
- /* Enable local time */
- SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
-
- /* Configure TT operation */
- MODIFY_REG(hfdcan->ttcan->TTOCF,
- (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
- (pTTParams->OperationMode | \
- pTTParams->TimeMaster | \
- (pTTParams->SyncDevLimit << 5) | \
- (pTTParams->InitRefTrigOffset << 8)));
- if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- MODIFY_REG(hfdcan->ttcan->TTOCF,
- (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
- (pTTParams->GapEnable | \
- (pTTParams->AppWdgLimit << 16) | \
- pTTParams->EvtTrigPolarity));
- }
- if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
- {
- MODIFY_REG(hfdcan->ttcan->TTOCF,
- (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
- (pTTParams->ExternalClkSync | \
- pTTParams->GlobalTimeFilter | \
- pTTParams->ClockCalibration));
- }
-
- /* Configure system matrix limits */
- MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
- if(pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- MODIFY_REG(hfdcan->ttcan->TTMLM,
- (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
- (((pTTParams->TxEnableWindow - 1) << 8) | (pTTParams->ExpTxTrigNbr << 16)));
- }
- if(pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
- {
- MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
- }
-
- /* Configure input triggers: Stop watch and Event */
- MODIFY_REG(hfdcan->ttcan->TTTS,
- (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
- (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
-
- /* Configure trigger memory start address */
- hfdcan->msgRam.TTMemorySA = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4;
- MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (hfdcan->msgRam.TTMemorySA << 2));
-
- /* Trigger memory elements number */
- MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << 16));
-
- /* Recalculate End Address */
- hfdcan->msgRam.TTMemorySA = SRAMCAN_BASE + (hfdcan->msgRam.TTMemorySA * 4);
- hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2 * 4);
-
- if(hfdcan->msgRam.EndAddress > 0x4000B5FC) /* Last address of the Message RAM */
- {
- /* Update error code.
- Message RAM overflow */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Flush the allocated Message RAM area */
- for(RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4)
- {
- *(__IO uint32_t *)(RAMcounter) = 0x00000000;
- }
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the reference message.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param IdType: Identifier Type.
- * This parameter can be a value of @arg FDCAN_id_type.
- * @param Identifier: Reference Identifier.
- * This parameter must be a number between:
- * - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- * - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
- * @param Payload: Enable or disable the additional payload.
- * This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
- * This parameter is ignored in case of time slaves.
- * If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
- * following elements are taken from Tx Buffer 0:
- * - MessageMarker
- * - TxEventFifoControl
- * - DataLength
- * - Data Bytes (payload):
- * - bytes 2-8, for Level 1
- * - bytes 5-8, for Level 0 and Level 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_ID_TYPE(IdType));
- if(IdType == FDCAN_STANDARD_ID)
- {
- assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FF));
- }
- else /* IdType == FDCAN_EXTENDED_ID */
- {
- assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFF));
- }
- assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Configure reference message identifier type, identifier and payload */
- if(IdType == FDCAN_EXTENDED_ID)
- {
- MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
- }
- else /* IdType == FDCAN_STANDARD_ID */
- {
- MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the FDCAN trigger according to the specified
- * parameters in the FDCAN_TriggerTypeDef structure.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param sTriggerConfig: pointer to an FDCAN_TriggerTypeDef structure that
- * contains the trigger configuration information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef* hfdcan, FDCAN_TriggerTypeDef* sTriggerConfig)
-{
- uint32_t CycleCode;
- uint32_t MessageNumber;
- uint32_t TriggerElementW1;
- uint32_t TriggerElementW2;
- uint32_t *TriggerAddress;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63));
- assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFF));
- assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
- if(sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
- {
- assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1)));
- }
- assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
- assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
- assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
- assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
- if((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE ) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED ))
- {
- assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
- }
- if(sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
- {
- if(sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
- {
- assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63));
- }
- else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
- {
- assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127));
- }
- }
-
- if(hfdcan->State == HAL_FDCAN_STATE_READY)
- {
- /* Calculate cycle code */
- if(sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
- {
- CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
- }
- else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
- {
- CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
- }
-
- /* Build first word of trigger element */
- TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
- (CycleCode << 8) | \
- sTriggerConfig->TmEventInt | \
- sTriggerConfig->TmEventExt | \
- sTriggerConfig->TriggerType);
-
- /* Select message number depending on trigger type (transmission or reception) */
- if(sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
- {
- MessageNumber = sTriggerConfig->FilterIndex;
- }
- else if((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE ) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
- (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED ))
- {
- MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
- }
- else
- {
- MessageNumber = 0U;
- }
-
- /* Build second word of trigger element */
- TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
-
- /* Calculate trigger address */
- TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4 * 2));
-
- /* Write trigger element to the message RAM */
- *TriggerAddress++ = TriggerElementW1;
- *TriggerAddress = TriggerElementW2;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Schedule global time adjustment for the next reference message.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimePreset: time preset value.
- * This parameter must be a number between:
- * - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
- * or:
- * - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef* hfdcan, uint32_t TimePreset)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the external clock synchronization is enabled */
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- /* Check that no global time preset is pending */
- if((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
-
- return HAL_ERROR;
- }
-
- /* Configure time preset */
- MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, TimePreset);
-
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Schedule time preset to take effect by the next reference message */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Schedule TUR numerator update for the next reference message.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param NewTURNumerator: new value of the TUR numerator.
- * This parameter must be a number between 0x10000 and 0x1FFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef* hfdcan, uint32_t NewTURNumerator)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the external clock synchronization is enabled */
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- /* Check that no external clock synchronization is pending */
- if((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
-
- return HAL_ERROR;
- }
-
- /* Configure new TUR numerator */
- MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000));
-
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Schedule TUR numerator update by the next reference message */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure stop watch source and polarity.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param Source: stop watch source.
- * This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
- * @param Polarity: stop watch polarity.
- * This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef* hfdcan, uint32_t Source, uint32_t Polarity)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
- assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Select stop watch source and polarity */
- MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure register time mark pulse generation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TimeMarkSource: time mark source.
- * This parameter can be a value of @arg FDCAN_TT_time_mark_source.
- * @param TimeMarkValue: time mark value (reference).
- * This parameter must be a number between 0 and 0xFFFF.
- * @param RepeatFactor: repeat factor of the cycle for which the time mark is valid.
- * This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
- * @param StartCycle: index of the first cycle in which the time mark becomes valid.
- * This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
- * This parameter must be a number between 0 and RepeatFactor.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef* hfdcan,
- uint32_t TimeMarkSource, uint32_t TimeMarkValue,
- uint32_t RepeatFactor, uint32_t StartCycle)
-{
- uint32_t Counter = 0U;
- uint32_t CycleCode;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
- assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFF));
- assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
- if(RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
- {
- assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1)));
- }
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable the time mark compare function */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
-
- if(TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
- {
- /* Calculate cycle code */
- if(RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
- {
- CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
- }
- else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
- {
- CycleCode = RepeatFactor + StartCycle;
- }
-
- Counter = 0U;
-
- /* Wait until the LCKM bit into TTTMK register is reset */
- while((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Configure time mark value and cycle code */
- hfdcan->ttcan->TTTMK = (TimeMarkValue | (CycleCode << 16));
-
- Counter = 0U;
-
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Update the register time mark compare source */
- MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable register time mark pulse generation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable register time mark pulse generation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable trigger time mark pulse generation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable trigger time mark pulse generation.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable gap control by input pin fdcan1_evt.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable gap control by pin fdcan1_evt */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable gap control by input pin fdcan1_evt.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable gap control by pin fdcan1_evt */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable gap control (finish only) by register time mark interrupt.
- * The next register time mark interrupt (TTIR.RTMI = "1") will finish
- * the Gap and start the reference message.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable gap control by register time mark interrupt */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable gap control by register time mark interrupt.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable gap control by register time mark interrupt */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Transmit next reference message with Next_is_Gap = "1".
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the node is configured for external event-synchronized TT operation */
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Set Next is Gap */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Finish a Gap by requesting start of reference message.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that the node is configured for external event-synchronized TT operation */
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
-
- if((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Set Finish Gap */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code.
- Feature not supported for TT Level 0 */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure target phase used for external synchronization by event
- * trigger input pin fdcan1_evt.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TargetPhase: defines target value of cycle time when a rising edge
- * of fdcan1_evt is expected.
- * This parameter must be a number between 0 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFF));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Check that no external schedule synchronization is pending */
- if((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
-
- return HAL_ERROR;
- }
-
- /* Configure cycle time target phase */
- MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << 16));
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Synchronize the phase of the FDCAN schedule to an external schedule
- * using event trigger input pin fdcan1_evt.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Enable external synchronization */
- SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable external schedule synchronization.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t Counter = 0U;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Wait until the LCKC bit into TTOCN register is reset */
- while((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != RESET)
- {
- /* Check for the Timeout */
- if(Counter++ > FDCAN_TIMEOUT_VALUE)
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
-
- /* Change FDCAN state */
- hfdcan->State = HAL_FDCAN_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Disable external synchronization */
- CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Get TT operation status.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TTOpStatus: pointer to an FDCAN_TTOperationStatusTypeDef structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
-{
- uint32_t TTStatusReg;
-
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
-
- /* Read the TT operation status register */
- TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
-
- /* Fill the TT operation status structure */
- TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
- TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
- TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
- TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> 6);
- TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> 7);
- TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> 8);
- TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> 22);
- TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> 23);
- TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> 24);
- TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> 27);
- TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> 28);
- TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> 29);
- TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> 30);
- TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> 31);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
- * @brief Interrupts management
- *
-@verbatim
- ==============================================================================
- ##### Interrupts management #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1
- (+) HAL_FDCAN_TT_ConfigInterruptLines : Assign TT interrupts to either Interrupt line 0 or 1
- (+) HAL_FDCAN_ActivateNotification : Enable interrupts
- (+) HAL_FDCAN_DeactivateNotification : Disable interrupts
- (+) HAL_FDCAN_TT_ActivateNotification : Enable TT interrupts
- (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
- (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Assign interrupts to either Interrupt line 0 or 1.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ITList: indicates which interrupts will be assigned to the selected interrupt line.
- * This parameter can be any combination of @arg FDCAN_Interrupts.
- * @param InterruptLine: Interrupt line.
- * This parameter can be a value of @arg FDCAN_Interrupt_Line.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_IT(ITList));
- assert_param(IS_FDCAN_IT_LINE(InterruptLine));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Assign list of interrupts to the selected line */
- if(InterruptLine == FDCAN_INTERRUPT_LINE0)
- {
- CLEAR_BIT(hfdcan->Instance->ILS, ITList);
- }
- else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
- {
- SET_BIT(hfdcan->Instance->ILS, ITList);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Assign TT interrupts to either Interrupt line 0 or 1.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TTITList: indicates which interrupts will be assigned to the selected interrupt line.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts.
- * @param InterruptLine: Interrupt line.
- * This parameter can be a value of @arg FDCAN_Interrupt_Line.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
- assert_param(IS_FDCAN_TT_IT(TTITList));
- assert_param(IS_FDCAN_IT_LINE(InterruptLine));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Assign list of interrupts to the selected line */
- if(InterruptLine == FDCAN_INTERRUPT_LINE0)
- {
- CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
- }
- else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
- {
- SET_BIT(hfdcan->ttcan->TTILS, TTITList);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable interrupts.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ActiveITs: indicates which interrupts will be enabled.
- * This parameter can be any combination of @arg FDCAN_Interrupts.
- * @param BufferIndexes: Tx Buffer Indexes.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * This parameter is ignored if ActiveITs does not include one of the following:
- * - FDCAN_IT_TX_COMPLETE
- * - FDCAN_IT_TX_ABORT_COMPLETE
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_IT(ActiveITs));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Enable Interrupt lines */
- if((ActiveITs & hfdcan->Instance->ILS) == RESET)
- {
- /* Enable Interrupt line 0 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
- }
- else if((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
- {
- /* Enable Interrupt line 1 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
- }
- else
- {
- /* Enable Interrupt lines 0 and 1 */
- hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
- }
-
- if((ActiveITs & FDCAN_IT_TX_COMPLETE) != RESET)
- {
- /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
- but interrupt will only occure if TC is enabled in IE register */
- SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
- }
-
- if((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
- {
- /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
- but interrupt will only occure if TCF is enabled in IE register */
- SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
- }
-
- /* Enable the selected interrupts */
- __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable interrupts.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param InactiveITs: indicates which interrupts will be disabled.
- * This parameter can be any combination of @arg FDCAN_Interrupts.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_IT(InactiveITs));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Disable the selected interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable TT interrupts.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ActiveTTITs: indicates which TT interrupts will be enabled.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Enable Interrupt lines */
- if((ActiveTTITs & hfdcan->ttcan->TTILS) == RESET)
- {
- /* Enable Interrupt line 0 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
- }
- else if((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
- {
- /* Enable Interrupt line 1 */
- SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
- }
- else
- {
- /* Enable Interrupt lines 0 and 1 */
- hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
- }
-
- /* Enable the selected TT interrupts */
- __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Disable TT interrupts.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param InactiveTTITs: indicates which TT interrupts will be disabled.
- * This parameter can be any combination of @arg FDCAN_TTInterrupts.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
-{
- /* Check function parameters */
- assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
-
- if((hfdcan->State == HAL_FDCAN_STATE_READY) || (hfdcan->State == HAL_FDCAN_STATE_BUSY))
- {
- /* Disable the selected TT interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
-
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handles FDCAN interrupt request.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t ClkCalibrationITs;
- uint32_t TxEventFifoITs;
- uint32_t RxFifo0ITs;
- uint32_t RxFifo1ITs;
- uint32_t ErrStatus;
- uint32_t TransmittedBuffers;
- uint32_t AbortedBuffers;
- uint32_t TTSchedSyncITs;
- uint32_t TTTimeMarkITs;
- uint32_t TTGlobTimeITs;
- uint32_t TTDistErrors;
- uint32_t TTFatalErrors;
- uint32_t SWTime;
- uint32_t SWCycleCount;
-
- ClkCalibrationITs = (FDCAN_CCU->IR << 30);
- ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
- TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
- TxEventFifoITs &= hfdcan->Instance->IE;
- RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
- RxFifo0ITs &= hfdcan->Instance->IE;
- RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
- RxFifo1ITs &= hfdcan->Instance->IE;
- ErrStatus = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
- ErrStatus &= hfdcan->Instance->IE;
-
- /* High Priority Message interrupt management *******************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
- {
- /* Disable the High Priority Message interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG);
-
- /* Clear the High Priority Message flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
-
- /* High Priority Message Callback */
- HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
- }
- }
-
- /* Transmission Abort interrupt management **********************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
- {
- /* Disable the Transmission Cancellation interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE);
-
- /* List of aborted monitored buffers */
- AbortedBuffers = hfdcan->Instance->TXBCF;
- AbortedBuffers &= hfdcan->Instance->TXBCIE;
-
- /* Disable the Tx Buffer Cancellation Finished Interrupt */
- CLEAR_BIT(hfdcan->Instance->TXBCIE, AbortedBuffers);
-
- /* Clear the Transmission Cancellation flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
-
- /* Transmission Cancellation Callback */
- HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
- }
- }
-
- /* Clock calibration unit interrupts management *****************************/
- if(ClkCalibrationITs != 0U)
- {
- /* Disable the Clock Calibration interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, ClkCalibrationITs);
-
- /* Clear the Clock Calibration flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
-
- /* Clock Calibration Callback */
- HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
- }
-
- /* Tx event FIFO interrupts management **************************************/
- if(TxEventFifoITs != 0U)
- {
- /* Disable the Tx Event FIFO interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, TxEventFifoITs);
-
- /* Clear the Tx Event FIFO flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
-
- /* Tx Event FIFO Callback */
- HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
- }
-
- /* Rx FIFO 0 interrupts management ******************************************/
- if(RxFifo0ITs != 0U)
- {
- /* Disable the Rx FIFO 0 interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, RxFifo0ITs);
-
- /* Clear the Rx FIFO 0 flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
-
- /* Rx FIFO 0 Callback */
- HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
- }
-
- /* Rx FIFO 1 interrupts management ******************************************/
- if(RxFifo1ITs != 0U)
- {
- /* Disable the Rx FIFO 1 interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, RxFifo1ITs);
-
- /* Clear the Rx FIFO 1 flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
-
- /* Rx FIFO 1 Callback */
- HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
- }
-
- /* Tx FIFO empty interrupt management ***************************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
- {
- /* Disable the Tx FIFO empty interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_FIFO_EMPTY);
-
- /* Clear the Tx FIFO empty flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
-
- /* Tx FIFO empty Callback */
- HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
- }
- }
-
- /* Transmission Complete interrupt management *******************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != RESET)
- {
- /* Disable the Transmission Complete interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TX_COMPLETE);
-
- /* List of transmitted monitored buffers */
- TransmittedBuffers = hfdcan->Instance->TXBTO;
- TransmittedBuffers &= hfdcan->Instance->TXBTIE;
-
- /* Disable the Tx Buffer Transmission Interrupt */
- CLEAR_BIT(hfdcan->Instance->TXBTIE, TransmittedBuffers);
-
- /* Clear the Transmission Complete flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
-
- /* Transmission Complete Callback */
- HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
- }
- }
-
- /* Rx Buffer New Message interrupt management *******************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
- {
- /* Disable the Rx Buffer New Message interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE);
-
- /* Clear the Rx Buffer New Message flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
-
- /* Rx Buffer New Message Callback */
- HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
- }
- }
-
- /* Timestamp Wraparound interrupt management ********************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
- {
- /* Disable the Timestamp Wraparound interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND);
-
- /* Clear the Timestamp Wraparound flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
-
- /* Timestamp Wraparound Callback */
- HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
- }
- }
-
- /* Timeout Occurred interrupt management ************************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
- {
- /* Disable the Timeout Occurred interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED);
-
- /* Clear the Timeout Occurred flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
-
- /* Timeout Occurred Callback */
- HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
- }
- }
-
- /* Message RAM access failure interrupt management **************************/
- if(__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
- {
- if(__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
- {
- /* Disable the Timeout Occurred interrupt */
- __HAL_FDCAN_DISABLE_IT(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE);
-
- /* Clear the Timeout Occurred flag */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
-
- /* Update error code */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
- }
- }
-
- /* Error interrupts management **********************************************/
- if(ErrStatus != 0U)
- {
- /* Disable the Error interrupts */
- __HAL_FDCAN_DISABLE_IT(hfdcan, ErrStatus);
-
- /* Clear the Error flags */
- __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrStatus);
-
- /* Update error code */
- hfdcan->ErrorCode |= ErrStatus;
- }
-
- if((hfdcan->Instance == FDCAN1) && \
- ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0))
- {
- TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
- TTSchedSyncITs &= hfdcan->ttcan->TTIE;
- TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
- TTTimeMarkITs &= hfdcan->ttcan->TTIE;
- TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
- TTGlobTimeITs &= hfdcan->ttcan->TTIE;
- TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
- TTDistErrors &= hfdcan->ttcan->TTIE;
- TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
- TTFatalErrors &= hfdcan->ttcan->TTIE;
-
- /* TT Schedule Synchronization interrupts management **********************/
- if(TTSchedSyncITs != 0U)
- {
- /* Disable the TT Schedule Synchronization interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTSchedSyncITs);
-
- /* Clear the TT Schedule Synchronization flags */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
-
- /* TT Schedule Synchronization Callback */
- HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
- }
-
- /* TT Time Mark interrupts management *************************************/
- if(TTTimeMarkITs != 0U)
- {
- /* Disable the TT Time Mark interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTTimeMarkITs);
-
- /* Clear the TT Time Mark flags */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
-
- /* TT Time Mark Callback */
- HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
- }
-
- /* TT Stop Watch interrupt management *************************************/
- if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
- {
- if(__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != RESET)
- {
- /* Disable the TT Stop Watch interrupt */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, FDCAN_TT_IT_STOP_WATCH);
-
- /* Retrieve Stop watch Time and Cycle count */
- SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> 16);
- SWCycleCount = hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV;
-
- /* Clear the TT Stop Watch flag */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
-
- /* TT Stop Watch Callback */
- HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
- }
- }
-
- /* TT Global Time interrupts management ***********************************/
- if(TTGlobTimeITs != 0U)
- {
- /* Disable the TT Global Time interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTGlobTimeITs);
-
- /* Clear the TT Global Time flags */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
-
- /* TT Global Time Callback */
- HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
- }
-
- /* TT Disturbing Error interrupts management ******************************/
- if(TTDistErrors != 0U)
- {
- /* Disable the TT Disturbing Error interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTDistErrors);
-
- /* Clear the TT Disturbing Error flags */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
-
- /* Update error code */
- hfdcan->ErrorCode |= TTDistErrors;
- }
-
- /* TT Fatal Error interrupts management ***********************************/
- if(TTFatalErrors != 0U)
- {
- /* Disable the TT Fatal Error interrupts */
- __HAL_FDCAN_TT_DISABLE_IT(hfdcan, TTFatalErrors);
-
- /* Clear the TT Fatal Error flags */
- __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
-
- /* Update error code */
- hfdcan->ErrorCode |= TTFatalErrors;
- }
- }
-
- if(hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
- {
- /* Error Callback */
- HAL_FDCAN_ErrorCallback(hfdcan);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
- * @brief FDCAN Callback functions
- *
-@verbatim
- ==============================================================================
- ##### Callback functions #####
- ==============================================================================
- [..]
- This subsection provides the following callback functions:
- (+) HAL_FDCAN_ClockCalibrationCallback
- (+) HAL_FDCAN_TxEventFifoCallback
- (+) HAL_FDCAN_RxFifo0Callback
- (+) HAL_FDCAN_RxFifo1Callback
- (+) HAL_FDCAN_TxFifoEmptyCallback
- (+) HAL_FDCAN_TxBufferCompleteCallback
- (+) HAL_FDCAN_TxBufferAbortCallback
- (+) HAL_FDCAN_RxBufferNewMessageCallback
- (+) HAL_FDCAN_HighPriorityMessageCallback
- (+) HAL_FDCAN_TimestampWraparoundCallback
- (+) HAL_FDCAN_TimeoutOccurredCallback
- (+) HAL_FDCAN_ErrorCallback
- (+) HAL_FDCAN_TTSchedSyncCallback
- (+) HAL_FDCAN_TTTimeMarkCallback
- (+) HAL_FDCAN_TTStopWatchCallback
- (+) HAL_FDCAN_TTGlobalTimeCallback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Clock Calibration callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param ClkCalibrationITs: indicates which Clock Calibration interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(ClkCalibrationITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Event callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TxEventFifoITs: indicates which Tx Event FIFO interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(TxEventFifoITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx FIFO 0 callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo0ITs: indicates which Rx FIFO 0 interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(RxFifo0ITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx FIFO 1 callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param RxFifo1ITs: indicates which Rx FIFO 1 interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(RxFifo1ITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx FIFO Empty callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Transmission Complete callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndexes: Indexes of the transmitted buffers.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval None
- */
-__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(BufferIndexes);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Transmission Cancellation callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param BufferIndexes: Indexes of the aborted buffers.
- * This parameter can be any combination of @arg FDCAN_Tx_location.
- * @retval None
- */
-__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(BufferIndexes);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Buffer New Message callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timestamp Wraparound callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timeout Occurred callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief High Priority Message callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Error callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval None
- */
-__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TT Schedule Synchronization callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TTSchedSyncITs: indicates which TT Schedule Synchronization interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(TTSchedSyncITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TTSchedSyncCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TT Time Mark callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TTTimeMarkITs: indicates which TT Schedule Synchronization interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(TTTimeMarkITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TTTimeMarkCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TT Stop Watch callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param SWTime: Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
- * edge (as configured via HAL_FDCAN_TTConfigStopWatch).
- * This parameter is a number between 0 and 0xFFFF.
- * @param SWCycleCount: Cycle count value captured together with SWTime.
- * This parameter is a number between 0 and 0x3F.
- * @retval None
- */
-__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(SWTime);
- UNUSED(SWCycleCount);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TTStopWatchCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TT Global Time callback.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param TTGlobTimeITs: indicates which TT Global Time interrupts are signalled.
- * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
- * @retval None
- */
-__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hfdcan);
- UNUSED(TTGlobTimeITs);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FDCAN_TTGlobalTimeCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
- * @brief FDCAN Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) HAL_FDCAN_GetState() : Return the FDCAN state.
- (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Return the FDCAN state
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL state
- */
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef* hfdcan)
-{
- /* Return FDCAN state */
- return hfdcan->State;
-}
-
-/**
- * @brief Return the FDCAN error code
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval FDCAN Error Code
- */
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
-{
- /* Return FDCAN error code */
- return hfdcan->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FDCAN_Private_Functions
- * @{
- */
-
-/**
- * @brief Calculate each RAM block start address and size
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @retval HAL status
- */
-static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
-{
- uint32_t RAMcounter;
-
- hfdcan->msgRam.StandardFilterSA = hfdcan->Init.MessageRAMOffset;
-
- /* Standard filter list start address */
- MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (hfdcan->msgRam.StandardFilterSA << 2));
-
- /* Standard filter elements number */
- MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << 16));
-
- /* Extended filter list start address */
- hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + hfdcan->Init.StdFiltersNbr;
- MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (hfdcan->msgRam.ExtendedFilterSA << 2));
-
- /* Extended filter elements number */
- MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << 16));
-
- /* Rx FIFO 0 start address */
- hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2);
- MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (hfdcan->msgRam.RxFIFO0SA << 2));
-
- /* Rx FIFO 0 elements number */
- MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << 16));
-
- /* Rx FIFO 1 start address */
- hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
- MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (hfdcan->msgRam.RxFIFO1SA << 2));
-
- /* Rx FIFO 1 elements number */
- MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << 16));
-
- /* Rx buffer list start address */
- hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
- MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (hfdcan->msgRam.RxBufferSA << 2));
-
- /* Tx event FIFO start address */
- hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
- MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (hfdcan->msgRam.TxEventFIFOSA << 2));
-
- /* Tx event FIFO elements number */
- MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << 16));
-
- /* Tx buffer list start address */
- hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2);
- MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (hfdcan->msgRam.TxBufferSA << 2));
-
- /* Dedicated Tx buffers number */
- MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << 16));
-
- /* Tx FIFO/queue start address */
- hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize);
-
- /* Tx FIFO/queue elements number */
- MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << 24));
-
- hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4);
- hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4);
- hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2 * 4);
- hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4);
- hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4);
- hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4);
- hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2 * 4);
- hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4);
-
- hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4);
-
- if(hfdcan->msgRam.EndAddress > 0x4000B5FC) /* Last address of the Message RAM */
- {
- /* Update error code.
- Message RAM overflow */
- hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
-
- return HAL_ERROR;
- }
- else
- {
- /* Flush the allocated Message RAM area */
- for(RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4)
- {
- *(__IO uint32_t *)(RAMcounter) = 0x00000000;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Copy Tx message to the message RAM.
- * @param hfdcan: pointer to an FDCAN_HandleTypeDef structure that contains
- * the configuration information for the specified FDCAN.
- * @param pTxHeader: pointer to a FDCAN_TxHeaderTypeDef structure.
- * @param pTxData: pointer to a buffer containing the payload of the Tx frame.
- * @param BufferIndex: index of the buffer to be configured.
- * @retval HAL status
- */
-static HAL_StatusTypeDef FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
-{
- uint32_t TxElementW1;
- uint32_t TxElementW2;
- uint32_t *TxAddress;
- uint32_t ByteCounter;
-
- /* Build first word of Tx header element */
- if(pTxHeader->IdType == FDCAN_STANDARD_ID)
- {
- TxElementW1 = (pTxHeader->ErrorStateIndicator |
- FDCAN_STANDARD_ID |
- pTxHeader->TxFrameType |
- (pTxHeader->Identifier << 18));
- }
- else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
- {
- TxElementW1 = (pTxHeader->ErrorStateIndicator |
- FDCAN_EXTENDED_ID |
- pTxHeader->TxFrameType |
- pTxHeader->Identifier);
- }
-
- /* Build second word of Tx header element */
- TxElementW2 = ((pTxHeader->MessageMarker << 24) |
- pTxHeader->TxEventFifoControl |
- pTxHeader->FDFormat |
- pTxHeader->BitRateSwitch |
- pTxHeader->DataLength);
-
- /* Calculate Tx element address */
- TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4));
-
- /* Write Tx element header to the message RAM */
- *TxAddress++ = TxElementW1;
- *TxAddress++ = TxElementW2;
-
- /* Write Tx payload to the message RAM */
- for(ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4)
- {
- *TxAddress++ = ((pTxData[ByteCounter+3] << 24) |
- (pTxData[ByteCounter+2] << 16) |
- (pTxData[ByteCounter+1] << 8) |
- pTxData[ByteCounter]);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
deleted file mode 100644
index 7b84a25..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_flash.c
- * @author MCD Application Team
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral Errors functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
-
- [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory operations
- and the read and write protection mechanisms.
-
-
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Option bytes programming
- (+) Error code correction (ECC) : Data in flash are 266-bits word
- (10 bits added per double word)
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the FLASH
- memory of all STM32H7xx devices.
-
- (#) FLASH Memory IO Programming functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Program functions: double word only
- (++) There Two modes of programming :
- (+++) Polling mode using HAL_FLASH_Program() function
- (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-
- (#) Interrupts and flags management functions :
- (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
- (++) Callback functions are called when the flash operations are finished :
- HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
- HAL_FLASH_OperationErrorCallback()
- (++) Get error flag status by calling HAL_FLASH_GetError()
-
- (#) Option bytes management functions :
- (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
- HAL_FLASH_OB_Lock() functions
- (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
- In this case, a reset is generated
- [..]
- In addition to these functions, this driver includes a set of macros allowing
- to handle the following operations:
- (+) Set the latency
- (+) Enable/Disable the FLASH interrupts
- (+) Monitor the FLASH flags status
- [..]
- (@) For any Flash memory program operation (erase or program), the CPU clock frequency
- (HCLK) must be at least 1MHz.
- (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
- a Flash memory operation.
- (@) Any attempt to read the Flash memory while it is being written or erased, causes the
- bus to stall. Read operations are processed correctly once the program operation has
- completed. This means that code or data fetches cannot be performed while a write/erase
- operation is ongoing
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Constants
- * @{
- */
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-FLASH_ProcessTypeDef pFlash;
-/* Private function prototypes -----------------------------------------------*/
-static void FLASH_SetErrorCode(uint32_t Bank);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions FLASH Private functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
- ===============================================================================
- ##### Programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the FLASH
- program operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program flash word of 256 bits at a specified address
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param FlashAddress specifies the address to be programmed.
- * @param DataAddress specifies the address of data (256 bits) to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- __IO uint64_t *dest_addr = (__IO uint64_t *)FlashAddress;
- __IO uint64_t *src_addr = (__IO uint64_t*)((uint32_t)DataAddress);
- uint32_t bank;
- uint8_t row_index = 4;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
-
- if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
- {
- bank = FLASH_BANK_1;
- }
- else
- {
- bank = FLASH_BANK_2;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
-
- if(status == HAL_OK)
- {
- if(bank == FLASH_BANK_1)
- {
- /* Clear bank 1 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_QW_BANK1 | FLASH_FLAG_WBNE_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
-
- /* Set PG bit */
- SET_BIT(FLASH->CR1, FLASH_CR_PG);
- }
- else
- {
- /* Clear bank 2 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_QW_BANK2 | FLASH_FLAG_WBNE_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
-
- /* Set PG bit */
- SET_BIT(FLASH->CR2, FLASH_CR_PG);
- }
-
- /* Program the 256 bits flash word */
- do
- {
- *dest_addr++ = *src_addr++;
- } while (--row_index != 0);
-
- __DSB();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
-
- if(bank == FLASH_BANK_1)
- {
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
- }
-
- /* If the program operation is completed, disable the PG*/
- CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
- }
- else
- {
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
- }
-
- /* If the program operation is completed, disable the PG */
- CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Program flash words of 256 bits at a specified address with interrupt enabled.
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param FlashAddress specifies the address to be programmed.
- * @param DataAddress specifies the address of data (256 bits) to be programmed
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint64_t DataAddress)
-{
- HAL_StatusTypeDef status = HAL_OK;
- __IO uint64_t *dest_addr = (__IO uint64_t*)FlashAddress;
- __IO uint64_t *src_addr = (__IO uint64_t*)((uint32_t)DataAddress);
- uint32_t bank;
- uint8_t row_index = 4;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
-
- if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
- {
- bank = FLASH_BANK_1;
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
- }
- else
- {
- bank = FLASH_BANK_2;
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
- }
-
- /* Set internal variables used by the IRQ handler */
- pFlash.Address = FlashAddress;
-
- if(bank == FLASH_BANK_1)
- {
- /* Clear bank 1 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
-
- /* Set PG bit */
- SET_BIT(FLASH->CR1, FLASH_CR_PG);
-
- /* Enable End of Operation and Error interrupts for Bank 1 */
- __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
- FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
- }
- else
- {
- /* Clear bank 2 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
-
- /* Set PG bit */
- SET_BIT(FLASH->CR2, FLASH_CR_PG);
-
- /* Enable End of Operation and Error interrupts for Bank2*/
- __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
- FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
- }
-
- /* Program the 256 bits flash word */
- do
- {
- *dest_addr++ = *src_addr++;
- } while (--row_index != 0);
-
- return status;
-}
-
-/**
- * @brief This function handles FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void)
-{
- uint32_t temp;
-
- /* Check FLASH Bank1 End of Operation flag */
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
- {
- /*Nb of sector to erased can be decreased*/
- pFlash.NbSectorsToErase--;
-
- /* Check if there are still sectors to erase*/
- if(pFlash.NbSectorsToErase != 0)
- {
- temp = pFlash.Sector;
- /*Indicate user which sector has been erased*/
- HAL_FLASH_EndOfOperationCallback(temp);
-
- /* Clear pending flags (if any) */
- /* Clear bank 1 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
-
- /*Increment sector number*/
- temp = ++pFlash.Sector;
- FLASH_Erase_Sector(temp, FLASH_BANK_1/*pFlash.Bank*/, pFlash.VoltageForErase);
- }
- else
- {
- /*No more sectors to Erase, user callback can be called.*/
- /*Reset Sector and stop Erase sectors procedure*/
- pFlash.Sector = temp = 0xFFFFFFFF;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
- }
- }
- else
- {
- if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK1) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
- {
- /*MassErase ended. Return the selected bank*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_BANK1)
- {
- /*Program ended. Return the selected address*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
-
- if((pFlash.ProcedureOnGoing != FLASH_PROC_SECTERASE_BANK2) && \
- (pFlash.ProcedureOnGoing != FLASH_PROC_MASSERASE_BANK2)&& \
- (pFlash.ProcedureOnGoing != FLASH_PROC_PROGRAM_BANK2))
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
- }
- }
- }
-
- /* Check FLASH Bank2 End of Operation flag */
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
- {
- /*Nb of sector to erased can be decreased*/
- pFlash.NbSectorsToErase--;
-
- /* Check if there are still sectors to erase*/
- if(pFlash.NbSectorsToErase != 0)
- {
- temp = pFlash.Sector;
- /*Indicate user which sector has been erased*/
- HAL_FLASH_EndOfOperationCallback(temp);
-
- /* Clear pending flags (if any) */
- /* Clear bank 2 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
-
- /*Increment sector number*/
- temp = ++pFlash.Sector;
- FLASH_Erase_Sector(temp, FLASH_BANK_2 /*pFlash.Bank*/, pFlash.VoltageForErase);
- }
- else
- {
- /*No more sectors to Erase, user callback can be called.*/
- /*Reset Sector and stop Erase sectors procedure*/
- pFlash.Sector = temp = 0xFFFFFFFF;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
- }
- }
- else
- {
- if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK2) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
- {
- /*MassErase ended. Return the selected bank*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
- }
- else
- {
- /*Program ended. Return the selected address*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
-
- if((pFlash.ProcedureOnGoing != FLASH_PROC_SECTERASE_BANK1) && \
- (pFlash.ProcedureOnGoing != FLASH_PROC_MASSERASE_BANK1)&& \
- (pFlash.ProcedureOnGoing != FLASH_PROC_PROGRAM_BANK1))
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
- }
- }
- }
-
- /* Check FLASH Bank1 operation error flags */
- if(__HAL_FLASH_GET_FLAG_BANK1((FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
- FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1)) != RESET)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
- {
- /*return the faulty sector*/
- temp = pFlash.Sector;
- pFlash.Sector = 0xFFFFFFFF;
- }
- else if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK1) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
- {
- /*return the faulty bank*/
- temp = FLASH_BANK_1;
- }
- else
- {
- /*return the faulty address*/
- temp = pFlash.Address;
- }
-
- /*Save the Error code*/
- FLASH_SetErrorCode(FLASH_BANK_1);
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG_BANK1((FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
- FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1));
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH Bank2 operation error flags */
- if(__HAL_FLASH_GET_FLAG_BANK2((FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
- FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2)) != RESET)
-
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
- {
- /*return the faulty sector*/
- temp = pFlash.Sector;
- pFlash.Sector = 0xFFFFFFFF;
- }
- else if((pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE_BANK2) || (pFlash.ProcedureOnGoing == FLASH_PROC_ALLBANK_MASSERASE))
- {
- /*return the faulty bank*/
- temp = FLASH_BANK_2;
- }
- else
- {
- /*return the faulty address*/
- temp = pFlash.Address;
- }
-
- /*Save the Error code*/
- FLASH_SetErrorCode(FLASH_BANK_2);
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG_BANK2((FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
- FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2));
-
- /*Stop the procedure ongoing*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
- {
- /* Disable Bank1 Operation and Error source interrupt */
- __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
- FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
-
- /* Disable Bank2 Operation and Error source interrupt */
- __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
- FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-
-}
-
-/**
- * @brief FLASH end of operation interrupt callback
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase Bank number which has been requested to erase
- * Sectors Erase: Sector which has been erased
- * (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
- * Program Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: Bank number which has been requested to erase
- * Sectors Erase: Sector number which returned an error
- * Program: Address which was selected for data program
- * @retval None
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
- if((READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != RESET) && (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != RESET))
- {
- /* Authorize the FLASH A Registers access */
- WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
-
- /* Authorize the FLASH B Registers access */
- WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Locks the FLASH control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH A Registers access */
- SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
-
- /* Set the LOCK Bit to lock the FLASH B Registers access */
- SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
- if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != RESET)
- {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Lock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
- /* Set the OPTLOCK Bit to lock the FLASH A and B Option Byte Registers access */
- SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Set OPTSTRT Bit */
- SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
-
- /* Wait for OB change operation to be completed */
- status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Peripheral State and Errors functions
- * @brief Peripheral Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval HAL_FLASH_ERRORCode The returned value can be:
- * @arg HAL_FLASH_ERROR_NONE: No error set
- *
- * @arg HAL_FLASH_ERROR_WRP_BANK1: Write Protection Error on Bank 1
- * @arg HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1
- * @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
- * @arg HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1
- * @arg HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1
- * @arg HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1
- * @arg HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1
- * @arg HAL_FLASH_ERROR_SNECC_BANK1: SNECC Error on Bank 1
- * @arg HAL_FLASH_ERROR_DBECC_BANK1: Double Detection ECC on Bank 1
- *
- * @arg HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2
- * @arg HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2
- * @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
- * @arg HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2
- * @arg HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2
- * @arg HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2
- * @arg HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2
- * @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
- * @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
-*/
-
-uint32_t HAL_FLASH_GetError(void)
-{
- return pFlash.ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout
- * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
-{
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t bsyflag, errorflag = 0;
- uint32_t timeout = HAL_GetTick() + Timeout;
-
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
-
- if(Bank == FLASH_BANK_1)
- {
- bsyflag = FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_QW_BANK1;
-
- if((FLASH->OPTCR & FLASH_OPTCR_SWAP_BANK) == 0)
- {
- bsyflag |= FLASH_FLAG_WBNE_BANK1;
- }
- else
- {
- bsyflag |= FLASH_FLAG_WBNE_BANK2;
- }
- }
- else
- {
- bsyflag = FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_QW_BANK2;
-
- if((FLASH->OPTCR & FLASH_OPTCR_SWAP_BANK) == 0)
- {
- bsyflag |= FLASH_FLAG_WBNE_BANK2;
- }
- else
- {
- bsyflag |= FLASH_FLAG_WBNE_BANK1;
- }
- }
-
- while(__HAL_FLASH_GET_FLAG(bsyflag))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- if((Bank == FLASH_BANK_1) && ((FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1) != RESET))
- {
- errorflag = FLASH_FLAG_ALL_ERRORS_BANK1;
- }
- else if((Bank == FLASH_BANK_2) && ((FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2 & 0x7FFFFFFF) != RESET))
- {
- errorflag = FLASH_FLAG_ALL_ERRORS_BANK2;
- }
-
- if(errorflag != 0)
- {
- /*Save the error code*/
- FLASH_SetErrorCode(Bank);
-
- /* Clear error programming flags */
- __HAL_FLASH_CLEAR_FLAG(errorflag);
-
- return HAL_ERROR;
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-}
-
-/**
- * @brief Wait for a FLASH Option Bytes change operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
-{
- uint32_t timeout = HAL_GetTick() + Timeout;
-
- /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset.*/
- while(FLASH->OPTSR_CUR & FLASH_OPTSR_OPT_BUSY)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if(HAL_GetTick() >= timeout)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- if(FLASH->OPTSR_CUR & FLASH_OPTSR_OPTCHANGEERR)
- {
- /*Save the error code*/
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
-
- /*Clear the OB error flag*/
- FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
-
- return HAL_ERROR;
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-}
-
-/**
- * @brief Set the specific FLASH error flag.
- * @retval None
- */
-static void FLASH_SetErrorCode(uint32_t Bank)
-{
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- if(Bank == FLASH_BANK_1)
- {
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_WRPERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_PGSERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_STRBER_BANK1R))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_STRB_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_INCERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_INC_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_OPERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPE_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDPERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_RDP_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDSERR_BANK1))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_RDS_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_SNECCE_BANK1RR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_SNECC_BANK1;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_DBECCE_BANK1RR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_DBECC_BANK1;
- }
- }
- else if(Bank == FLASH_BANK_2)
- {
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_WRPERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_PGSERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_STRBER_BANK2R))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_STRB_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_INCERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_INC_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_OPERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPE_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDPERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_RDP_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_RDSERR_BANK2))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_RDS_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_SNECCE_BANK2RR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_SNECC_BANK2;
- }
- if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_DBECCE_BANK2RR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_DBECC_BANK2;
- }
- }
-}
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
deleted file mode 100644
index 43a6fbc..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1372 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_flash_ex.c
- * @author MCD Application Team
- * @brief Extended FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH extension peripheral:
- * + Extended programming operations functions
- *
- @verbatim
- ==============================================================================
- ##### Flash Extension features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
- devices contains the following additional features
-
- (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
- capability (RWW)
- (+) Dual bank memory organization
- (+) PCROP protection for all banks
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32H7xx devices. It includes
- (#) FLASH Memory Erase functions:
- (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
- HAL_FLASH_Lock() functions
- (++) Erase function: Erase sector, erase all sectors
- (++) There are two modes of erase :
- (+++) Polling Mode using HAL_FLASHEx_Erase()
- (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-
- (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
- (++) Set/Reset the write protection per bank
- (++) Set the Read protection Level
- (++) Set the BOR level
- (++) Program the user Option Bytes
- (++) PCROP protection configuration and control per bank
- (++) Secure area configuration and control per bank
- (++) Core Boot address configuration
-
- (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1 and HAL_FLASHEx_Unlock_Bank1 functions
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH HAL Extension module driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Constants
- * @{
- */
-#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern FLASH_ProcessTypeDef pFlash;
-
-/* Private function prototypes -----------------------------------------------*/
-
-static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
-void FLASH_Erase_Sector(uint32_t Sector, uint32_t Bank, uint32_t VoltageRange);
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
-static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
-static uint32_t FLASH_OB_GetRDP(void);
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
-static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
-static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
-static uint32_t FLASH_OB_GetBOR(void);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
-static uint32_t FLASH_OB_GetUser(void);
-static HAL_StatusTypeDef FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
-static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
-static HAL_StatusTypeDef FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
-static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
-
-
-
-
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
- * @{
- */
-
-/** @defgroup FLASHEx_Group1 Extended IO operation functions
- * @brief Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### Extended programming operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the Extension FLASH
- programming operations Operations.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory sectors
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @param[out] SectorError pointer to variable that
- * contains the configuration information on faulty sector in case of error
- * (0xFFFFFFFF means that all the sectors have been correctly erased)
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t index = 0;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
- assert_param(IS_VOLTAGERANGE(pEraseInit->VoltageRange));
- assert_param(IS_FLASH_BANK(pEraseInit->Banks));
-
-
- /* Wait for last operation to be completed */
- if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- }
-
- if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- if(status == HAL_OK)
- {
- /*Initialization of SectorError variable*/
- *SectorError = 0xFFFFFFFF;
-
- if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
-
- /* Wait for last operation to be completed */
- if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- /* if the erase operation is completed, disable the Bank1 BER Bit */
- FLASH->CR1 &= (~FLASH_CR_BER);
- }
- if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- /* if the erase operation is completed, disable the Bank2 BER Bit */
- FLASH->CR2 &= (~FLASH_CR_BER);
- }
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(pEraseInit->Banks));
- assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
- /* Erase by sector by sector to be done*/
- for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
- {
- FLASH_Erase_Sector(index, pEraseInit->Banks, pEraseInit->VoltageRange);
-
- if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
-
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
- }
- if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
- }
-
- if(status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty sector*/
- *SectorError = index;
- break;
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
- assert_param(IS_VOLTAGERANGE(pEraseInit->VoltageRange));
- assert_param(IS_FLASH_BANK(pEraseInit->Banks));
-
- if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Clear bank 1 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK1);
-
- /* Enable End of Operation and Error interrupts for Bank 1 */
- __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
- FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
- }
- if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Clear bank 2 pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_ALL_ERRORS_BANK2);
-
- /* Enable End of Operation and Error interrupts for Bank 2 */
- __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
- FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
- }
-
- if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- if(pEraseInit->Banks == FLASH_BANK_1)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
- }
- else if(pEraseInit->Banks == FLASH_BANK_2)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
- }
-
- FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
- }
- else
- {
- /* Erase by sector to be done*/
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(pEraseInit->Banks));
- assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
- if(pEraseInit->Banks == FLASH_BANK_1)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
- }
-
- pFlash.NbSectorsToErase = pEraseInit->NbSectors;
- pFlash.Sector = pEraseInit->Sector;
- pFlash.VoltageForErase = pEraseInit->VoltageRange;
-
- /*Erase 1st sector and wait for IT*/
- FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
- }
-
- return status;
-}
-
-/**
- * @brief Program option bytes
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /*Write protection configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
- {
- assert_param(IS_WRPSTATE(pOBInit->WRPState));
- assert_param(IS_FLASH_BANK(pOBInit->Banks));
-
- if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
- {
- /*Enable of Write protection on the selected Sector*/
- status = FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
- }
- else
- {
- /*Disable of Write protection on the selected Sector*/
- status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
- }
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Read protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
- {
- /* Configure the Read protection level */
- status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* User Configuration */
- if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
- {
- /* Configure the user option bytes */
- status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* PCROP Configuration */
- if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
- {
- assert_param(IS_FLASH_BANK(pOBInit->Banks));
-
- /*Configure the Proprietary code readout protection */
- status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
-
- }
-
- /*BOR Level configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
- {
- status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /*Boot Address configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
- {
- status = FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
- /*Bank1 secure area configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
- {
- status = FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
- if(status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option byte configuration
- * @note The parameter Banks of the pOBInit structure must be exclusively FLASH_BANK_1 or FLASH_BANK_2
- as this parameter is use to get the given Bank WRP, PCROP and secured area.
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(pOBInit->Banks));
- pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \
- OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
- OPTIONBYTE_BOR | OPTIONBYTE_BOOTADD | \
- OPTIONBYTE_SECURE_AREA);
-
- /* Get write protection on the selected area */
- FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
-
- /* Get Read protection level */
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /* Get the user option bytes */
- pOBInit->USERConfig = FLASH_OB_GetUser();
-
- /* Get the Proprietary code readout protection */
- FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
-
- /*Get BOR Level*/
- pOBInit->BORLevel = FLASH_OB_GetBOR();
-
- /*Get Boot Address*/
- FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
- /*Get Bank Secure area*/
- FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
-}
-
-/**
- * @brief Unlock the FLASH Bank1 control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
-{
- if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH A Registers access */
- WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Locks the FLASH Bank1 control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
-{
- /* Set the LOCK Bit to lock the FLASH A Registers access */
- SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Bank2 control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
-{
- if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH A Registers access */
- WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Locks the FLASH Bank2 control registers access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
-{
- /* Set the LOCK Bit to lock the FLASH A Registers access */
- SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
- return HAL_OK;
-}
-
-/**
- * @brief Full erase of FLASH memory sectors
- * @param VoltageRange The device program/erase parallelism.
- * This parameter can be one of the following values:
- * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
- * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
- * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
- * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
- *
- * @param Banks Banks to be erased
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Bank1 to be erased
- * @arg FLASH_BANK_2: Bank2 to be erased
- * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
- *
- * @retval HAL Status
- */
-static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
-
- /* Flash Mass Erase */
- if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
- {
- /* reset Program/erase VoltageRange for Bank1 */
- FLASH->CR1 &= (~FLASH_CR_PSIZE);
- /* Bank1 will be erased, and set voltage range*/
- FLASH->CR1 |= FLASH_CR_BER | VoltageRange;
-
- FLASH->OPTCR |= FLASH_OPTCR_MER;
-
- }
- else
- {
- /* Proceed to erase Flash Bank */
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* reset Program/erase VoltageRange for Bank1 */
- FLASH->CR1 &= (~FLASH_CR_PSIZE);
-
- /* Bank1 will be erased, and set voltage range*/
- FLASH->CR1 |= FLASH_CR_BER | VoltageRange;
- FLASH->CR1 |= FLASH_CR_START;
- }
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* reset Program/erase VoltageRange for Bank2 */
- FLASH->CR2 &= (~FLASH_CR_PSIZE);
-
- /* Bank2 will be erased, and set voltage range*/
- FLASH->CR2 |= FLASH_CR_BER | VoltageRange;
- FLASH->CR2 |= FLASH_CR_START;
- }
- }
-}
-
-/**
- * @brief Erase the specified FLASH memory sector
- * @param Sector FLASH sector to erase
- * @param Banks Banks to be erased
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: Bank1 to be erased
- * @arg FLASH_BANK_2: Bank2 to be erased
- * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
- * @param VoltageRange The device program/erase parallelism.
- * This parameter can be one of the following values:
- * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
- * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
- * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
- * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 62 bits
- *
- * @retval None
- */
-void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
-{
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
- assert_param(IS_VOLTAGERANGE(VoltageRange));
- assert_param(IS_FLASH_SECTOR(Sector));
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* reset Program/erase VoltageRange for Bank1 */
- FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
-
- FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << POSITION_VAL(FLASH_CR_SNB)));
-
- FLASH->CR1 |= FLASH_CR_START;
- }
-
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* reset Program/erase VoltageRange for Bank2 */
- FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
-
- FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << POSITION_VAL(FLASH_CR_SNB)));
-
- FLASH->CR2 |= FLASH_CR_START;
- }
-}
-
-/**
- * @brief Enable the write protection of the desired bank1 or bank 2 sectors
- * @param WRPSector specifies the sector(s) to be write protected.
- * This parameter can be one of the following values:
- * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_0 or OB_WRP_SECTOR_All
- *
- * @param Banks the specific bank to apply WRP sectors
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: WRP enable on specified bank1 sectors
- * @arg FLASH_BANK_2: WRP enable on specified bank2 sectors
- * @arg FLASH_BANK_BOTH: WRP enable bank1 and bank2 specified sectors
- *
- * @retval HAL FLASH State
- */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
-
- if(status == HAL_OK)
- {
- FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
- }
- }
-
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
- }
- }
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- }
-
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- return status;
-}
-
-/**
- * @brief Disable the write protection of the desired bank1 or bank 2 sectors
- * @param WRPSector specifies the sector(s) to disable write protection.
- * This parameter can be one of the following values:
- * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
- *
- * @param Banks the specific bank to apply WRP sectors
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: WRP disable on specified bank1 sectors
- * @arg FLASH_BANK_2: WRP disable on specified bank2 sectors
- * @arg FLASH_BANK_BOTH: WRP disable bank1 and bank2 specified sectors
- *
- * @retval HAL FLASH State
- */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
- assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
-
- if(status == HAL_OK)
- {
- FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
- }
- }
-
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
- }
- }
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- }
-
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- return status;
-}
-
-/**
- * @brief Get the write protection of the given bank1 or bank 2 sectors
- * @param WRPState gives the write protection state on the given bank .
- * This parameter can be one of the following values:
- * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
-
- * @param WRPSector gives the write protected sector(s) on the given bank .
- * This parameter can be one of the following values:
- * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
- *
- * @param Bank the specific bank to apply WRP sectors
- * This parameter can be exclusively one of the following values:
- * @arg FLASH_BANK_1: Get bank1 WRP sectors
- * @arg FLASH_BANK_2: Get bank2 WRP sectors
- * @arg FLASH_BANK_BOTH: note allowed in this functions
- *
- * @retval HAL FLASH State
- */
-static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
-{
- uint32_t regvalue = 0;
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- regvalue = FLASH->WPSN_CUR1;
- }
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- regvalue = FLASH->WPSN_CUR2;
- }
-
- (*WRPSector) = (~(regvalue & FLASH_WPSN_WRPSN)) & FLASH_WPSN_WRPSN;
- if(*WRPSector == 0)
- {
- (*WRPState) = OB_WRPSTATE_DISABLE;
- }
- else
- {
- (*WRPState) = OB_WRPSTATE_ENABLE;
- }
-}
-
-/**
- * @brief Set the read protection level.
- *
- * @note To configure the RDP level, the option lock bit OPTLOCK must be
- * cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the RDP level, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
- * to go back to level 1 or 0 !!!
- *
- * @param RDPLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(RDPLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- /* Configure the RDP level in the option bytes register */
- MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- return status;
-}
-
-/**
- * @brief Get the read protection level.
- * @retval RDPLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- */
-static uint32_t FLASH_OB_GetRDP(void)
-{
- return (FLASH->OPTSR_CUR & FLASH_OPTSR_RDP);
-}
-
-/**
- * @brief Program the FLASH User Option Byte.
- *
- * @note To configure the user option bytes, the option lock bit OPTLOCK must
- * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
- *
- * @note To validate the user option bytes, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- *
- * @param UserType The FLASH User Option Bytes to be modified :
- * a combination of @arg FLASH_OB_USER_Type
- *
- * @param UserConfig The FLASH User Option Bytes values:
- * IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
- * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
- * ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
-{
- uint32_t optr_reg_val = 0;
- uint32_t optr_reg_mask = 0;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_USER_TYPE(UserType));
-
- /* Wait for OB change operation to be completed */
- status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- if((UserType & OB_USER_IWDG1_SW) != RESET)
- {
- /* IWDG_HW option byte should be modified */
- assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
-
- /* Set value and mask for IWDG_HW option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
- optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
- }
- if((UserType & OB_USER_NRST_STOP_D1) != RESET)
- {
- /* NRST_STOP option byte should be modified */
- assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
-
- /* Set value and mask for NRST_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
- optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
- }
-
- if((UserType & OB_USER_NRST_STDBY_D1) != RESET)
- {
- /* NRST_STDBY option byte should be modified */
- assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
-
- /* Set value and mask for NRST_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
- optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
- }
-
- if((UserType & OB_USER_IWDG_STOP) != RESET)
- {
- /* IWDG_STOP option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
-
- /* Set value and mask for IWDG_STOP option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
- optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
- }
-
- if((UserType & OB_USER_IWDG_STDBY) != RESET)
- {
- /* IWDG_STDBY option byte should be modified */
- assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
-
- /* Set value and mask for IWDG_STDBY option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
- optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
- }
-
- if((UserType & OB_USER_SECURITY) != RESET)
- {
- /* SECURITY option byte should be modified */
- assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
-
- /* Set value and mask for ePcROP_EN option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
- optr_reg_mask |= FLASH_OPTSR_SECURITY;
- }
- if((UserType & OB_USER_SWAP_BANK) != RESET)
- {
- /* SWAP_BANK_OPT option byte should be modified */
- assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
-
- /* Set value and mask for SWAP_BANK_OPT option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
- optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
- }
-
- if((UserType & OB_USER_IOHSLV) != RESET)
- {
- /* IOHSLV_OPT option byte should be modified */
- assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
-
- /* Set value and mask for IOHSLV_OPT option byte */
- optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
- optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
- }
-
- /* Configure the option bytes register */
- MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
- }
-
- return status;
-}
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values
- * IWDG_SW(Bit4), WWDG_SW(Bit 5), nRST_STOP(Bit 6), nRST_STDY(Bit 7),
- * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
- * ePcROP_EN(Bit 21), SWAP_BANK_OPT(Bit 31) .
- */
-static uint32_t FLASH_OB_GetUser(void)
-{
- uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
- userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
-
- return userConfig;
-}
-
-/**
- * @brief Configure the Proprietary code readout protection of the desired addresses
- *
- * @note To configure the PCROP options, the option lock bit OPTLOCK must be
- * cleared with the call of the HAL_FLASH_OB_Unlock() function.
- * @note To validate the PCROP options, the option bytes must be reloaded
- * through the call of the HAL_FLASH_OB_Launch() function.
- *
- * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
- * when RDP level decreased from Level 1 to Level 0.
- * This parameter must be a value of @arg FLASH_OB_PCROP_RDP enumeration
- *
- * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection
- * This parameter can be an address between begin and end of the bank
- *
- * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection
- * This parameter can be an address between PCROPStartAddr and end of the bank
- *
- * @param Banks the specific bank to apply PCROP sectors
- * This parameter can be one of the following values:
- * @arg FLASH_BANK_1: PCROP on specified bank1 area
- * @arg FLASH_BANK_2: PCROP on specified bank2 area
- * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
- *
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
- assert_param(IS_OB_PCROP_RDP(PCROPConfig));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(PCROPStartAddr));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(PCROPEndAddr));
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE,FLASH_BANK_1);
-
- if(status == HAL_OK)
- {
- /* Configure the Proprietary code readout protection */
- FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8);
-
- FLASH->PRAR_PRG1 |= (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << POSITION_VAL(FLASH_PRAR_PROT_AREA_END)) ;
-
- FLASH->PRAR_PRG1 |= PCROPConfig;
-
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- }
- }
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE,FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8);
-
- FLASH->PRAR_PRG2 |= (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << POSITION_VAL(FLASH_PRAR_PROT_AREA_END)) ;
-
- FLASH->PRAR_PRG2 |= PCROPConfig;
-
- /* Wait for last operation to be completed */
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Get the Proprietary code readout protection configuration on a given Bank
- *
- * @param PCROPConfig gives if the PCROP area for the given Bank shall be erased or not
- * when RDP level decreased from Level 1 to Level 0 or during a mass erase.
- *
- * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
- *
- * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
- *
- * @param Bank the specific bank to apply PCROP sectors
- * This parameter can be exclusively one of the following values:
- * @arg FLASH_BANK_1: PCROP on specified bank1 area
- * @arg FLASH_BANK_2: PCROP on specified bank2 area
- * @arg FLASH_BANK_BOTH: is not allowed here
- *
- * @retval HAL Status
- */
-static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank)
-{
- uint32_t regvalue = 0;
- uint32_t bankBase = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- regvalue = FLASH->PRAR_CUR1;
- bankBase = FLASH_BANK1_BASE;
- }
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- regvalue = FLASH->PRAR_CUR2;
- bankBase = FLASH_BANK2_BASE;
- }
-
-
- (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP);
-
- (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
- (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> POSITION_VAL(FLASH_PRAR_PROT_AREA_END) ;
- (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
-}
-
-/**
- * @brief Set the BOR Level.
- * @param Level specifies the Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- assert_param(IS_OB_BOR_LEVEL(Level));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- /* Configure BOR_LEV option byte */
- MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level );
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- return status;
-}
-
-/**
- * @brief Get the BOR Level.
- * @retval The Option Bytes BOR Reset Level.
- * This parameter can be one of the following values:
- * @arg OB_BOR_LEVEL1: Supply voltage ranges from 1.69V - 1.8V
- * @arg OB_BOR_LEVEL2: Supply voltage ranges from 1.94V - 2.1V
- * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.30V - 2.49V
- */
-static uint32_t FLASH_OB_GetBOR(void)
-{
- return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
-}
-
-/**
- * @brief Set Boot address
- * @param BootOption Boot address option byte to be programmed,
- * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
- (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
- *
- * @param BootAddress0 Specifies the Boot Address 0
- * @param BootAddress1 Specifies the Boot Address 1
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
- {
- /* Check the parameters */
- assert_param(IS_BOOT_ADDRESS(BootAddress0));
-
- /* Configure BOOT ADD0 */
- MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
- }
-
- if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
- {
- /* Check the parameters */
- assert_param(IS_BOOT_ADDRESS(BootAddress1));
-
- /* Configure BOOT ADD1 */
- MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1 );
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
-
- return status;
-}
-
-/**
- * @brief Get Boot address
- * @param BootAddress0 Specifies the Boot Address 0.
- * @param BootAddress1 Specifies the Boot Address 1.
- * @retval HAL Status
- */
-static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
-{
- uint32_t regvalue = 0;
-
- regvalue = FLASH->BOOT_CUR;
-
- (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
-
- (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
-
-}
-
-/**
- * @brief Set secure area configuration
- * @param SecureAreaConfig specify if the secure area will be deleted or not during next mass-erase,
- *
- * @param SecureAreaStartAddr Specifies the secure area start address
- * @param SecureAreaEndAddr Specifies the secure area end address
- * @param Banks Specifies the Bank
- * @retval HAL Status
- */
-static HAL_StatusTypeDef FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
- assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
-
- if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
- {
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
-
- if(status == HAL_OK)
- {
- /* Configure the secure area */
- FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8);
-
- FLASH->SCAR_PRG1 |= (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << POSITION_VAL(FLASH_SCAR_SEC_AREA_END)) ;
-
- FLASH->SCAR_PRG1 |= (SecureAreaConfig & FLASH_SCAR_DMES);
-
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
-
- }
- }
- if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
- {
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
- assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
-
- if(status == HAL_OK)
- {
- /* Configure the secure area */
- FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8);
-
- FLASH->SCAR_PRG2 |= (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << POSITION_VAL(FLASH_SCAR_SEC_AREA_END)) ;
-
- FLASH->SCAR_PRG2 |= (SecureAreaConfig & FLASH_SCAR_DMES);
-
- status |= FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Set secure area configuration
- * @param SecureAreaConfig specify if the secure area will be deleted or not during next mass-erase,
- *
- * @param SecureAreaStartAddr Specifies the secure area start address
- * @param SecureAreaEndAddr Specifies the secure area end address
- * @param Bank Specifies the Bank
- * @retval HAL Status
- */
-static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
-{
- uint32_t regvalue = 0;
- uint32_t bankBase = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
- {
- regvalue = FLASH->SCAR_CUR1;
- bankBase = FLASH_BANK1_BASE;
- }
-
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
- {
- regvalue = FLASH->SCAR_CUR2;
- bankBase = FLASH_BANK2_BASE;
- }
-
- (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
- (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
- (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> POSITION_VAL(FLASH_SCAR_SEC_AREA_END) ;
- (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
-
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
- * @}
- */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
deleted file mode 100644
index cfd2bb2..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_gpio.c
- * @author MCD Application Team
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
- port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
- in several modes:
- (+) Input mode
- (+) Analog mode
- (+) Output mode
- (+) Alternate function mode
- (+) External interrupt/event lines
-
- [..]
- During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- [..]
- All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- [..]
- In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
-
- [..]
- All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- [..]
- The external interrupt/event controller consists of up to 23 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
- structure.
- (++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure.
- (++) In alternate mode is selection, the alternate function connected to the IO
- is configured through "Alternate" member from GPIO_InitTypeDef structure.
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member from
- GPIO_InitTypeDef structure select the type (interrupt or event) and
- the corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
- HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE ((uint32_t)0x00000003)
-#define ANALOG_MODE ((uint32_t)0x00000008)
-#define EXTI_MODE ((uint32_t)0x10000000)
-#define GPIO_MODE_IT ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT ((uint32_t)0x00020000)
-#define RISING_EDGE ((uint32_t)0x00100000)
-#define FALLING_EDGE ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
-
-#define GPIO_NUMBER ((uint32_t)16)
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize and de-initialize the GPIOs
- to be ready for use.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
- * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- uint32_t position = 0x00;
- uint32_t ioposition = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t temp = 0x00;
- EXTI_Core_TypeDef * EXTI_Ptr = EXTI_D1;
-
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
- if(iocurrent == ioposition)
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- GPIOx->AFR[position >> 3] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- GPIOx->MODER = temp;
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- temp |= (GPIO_Init->Speed << (position * 2));
- GPIOx->OSPEEDR = temp;
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- GPIOx->OTYPER = temp;
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- temp |= ((GPIO_Init->Pull) << (position * 2));
- GPIOx->PUPDR = temp;
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
-
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- temp = SYSCFG->EXTICR[position >> 2];
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- SYSCFG->EXTICR[position >> 2] = temp;
-
- /* Clear EXTI line configuration */
- temp = EXTI_Ptr->IMR1;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- temp |= iocurrent;
- }
- EXTI_Ptr->IMR1 = temp;
-
- temp = EXTI_Ptr->EMR1;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- temp |= iocurrent;
- }
- EXTI_Ptr->EMR1 = temp;
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR1;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- {
- temp |= iocurrent;
- }
- EXTI->RTSR1 = temp;
-
- temp = EXTI->FTSR1;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- {
- temp |= iocurrent;
- }
- EXTI->FTSR1 = temp;
- }
- }
- }
-}
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
-{
- uint32_t position;
- uint32_t ioposition = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (GPIO_Pin) & ioposition;
-
- if(iocurrent == ioposition)
- {
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO in Analog Mode */
- GPIOx->MODER |= (GPIO_MODER_MODER0 << (position * 2));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
- /*------------------------- EXTI Mode Configuration --------------------*/
- tmp = SYSCFG->EXTICR[position >> 2];
- tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
- if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
- {
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
- /* Clear EXTI line configuration */
- EXTI_D1->IMR1 &= ~((uint32_t)iocurrent);
- EXTI_D1->EMR1 &= ~((uint32_t)iocurrent);
-
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR1 &= ~((uint32_t)iocurrent);
- EXTI->FTSR1 &= ~((uint32_t)iocurrent);
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_PIN_x where x can be (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
- {
- bitstatus = GPIO_PIN_SET;
- }
- else
- {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- *
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @param PinState: specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- {
- GPIOx->BSRRL = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRRH = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Toggles the specified GPIO pins.
- * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
- * @param GPIO_Pin: specifies the port bit to be locked.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
- * @retval None
- */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- tmp |= GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-
-
-}
-
-/**
- * @brief EXTI line detection callback.
- * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c
deleted file mode 100644
index cf71021..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c
+++ /dev/null
@@ -1,2661 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32H7xx_hal_hash.c
- * @author MCD Application Team
- * @brief HASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the HASH peripheral:
- * + Initialization and de-initialization methods
- * + HASH or HMAC processing in polling mode
- * + HASH or HMAC processing in interrupt mode
- * + HASH or HMAC processing in DMA mode
- * + Peripheral State methods
- * + HASH or HMAC processing suspension/resumption
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The HASH HAL driver can be used as follows:
-
- (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
- (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
- (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
- (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
- (+++) Enable the DMAx interface clock using
- __DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream to manage data transfer from
- memory to peripheral (input stream). Managing data transfer from
- peripheral to memory can be performed only using CPU.
- (+++) Associate the initialized DMA handle to the HASH DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: use
- HAL_NVIC_SetPriority() and
- HAL_NVIC_EnableIRQ()
-
- (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
- (##) resorts to HAL_HASH_MspInit() for low-level initialization,
- (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
-
- (#)Three processing schemes are available:
- (##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished,
- e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
- (##) Interrupt mode: processing APIs are not blocking functions
- i.e. they process the data under interrupt,
- e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
- (##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA,
- e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
- for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
- is then required to retrieve the digest.
-
- (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
- initialized and processes the buffer fed in input. When the input data have all been
- fed to the IP, the digest computation can start.
-
- (#)Multi-buffer processing is possible in polling and DMA mode.
- (##) In polling mode, only multi-buffer HASH processing is possible.
- API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
- well the computed digest.
-
- (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
-
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
- Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
- same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
- API HAL_HASH_xxx_Finish().
-
- (+++) HMAC processing (requires to resort to extended functions):
- after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
- starts step 2.
- The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
- point, the HMAC processing is still carrying out step 2.
- Then, step 2 for the last input buffer and step 3 are carried out by a single call
- to HAL_HMACEx_xxx_Step2_3_DMA().
-
- The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
-
-
- (#)Context swapping.
- (##) Two APIs are available to suspend HASH or HMAC processing:
- (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
- (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
-
- (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
- to save in memory the IP context. This context can be restored afterwards
- to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
-
- (##) Once the HASH IP has been restored to the same configuration as that at suspension
- time, processing can be restarted with the same API call (same API, same handle,
- same parameters) as done before the suspension. Relevant parameters to restart at
- the proper location are internally saved in the HASH handle.
-
- (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#if defined (HASH)
-
-/** @defgroup HASH HASH
- * @brief HASH HAL module driver.
- * @{
- */
-
-#ifdef HAL_HASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup HASH_Private_Constants HASH Private Constants
- * @{
- */
-
-/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
- * @{
- */
-#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */
-#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register */
-/**
- * @}
- */
-
-/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
- * @{
- */
-#define HASH_NUMBER_OF_CSR_REGISTERS 54 /*!< Number of Context Swap Registers */
-/**
- * @}
- */
-
-/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
- * @{
- */
-#define HASH_TIMEOUTVALUE 1000 /*!< Time-out value */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
- * @{
- */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
-static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
-static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions HASH Exported Functions
- * @{
- */
-
-/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief HASH Initialization, configuration and call-back functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the HASH according to the specified parameters
- in the HASH_InitTypeDef and create the associated handle
- (+) DeInitialize the HASH peripheral
- (+) Initialize the HASH MCU Specific Package (MSP)
- (+) DeInitialize the HASH MSP
-
- [..] This section provides as well call back functions definitions for user
- code to manage:
- (+) Input data transfer to IP completion
- (+) Calculated digest retrieval completion
- (+) Error management
-
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the HASH according to the specified parameters in the
- HASH_HandleTypeDef and create the associated handle.
- * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
- * other configuration bits are set by HASH or HMAC processing APIs.
- * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
- * multi-buffer HASH processing, user needs to resort to
- * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
- * relevant APIs manage themselves the MDMAT bit.
- * @param hhash: HASH handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
-{
- /* Check the hash handle allocation */
- if(hhash == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-
- if(hhash->State == HAL_HASH_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hhash->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_HASH_MspInit(hhash);
- }
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Reset HashInCount, HashITCounter and HashBuffSize */
- hhash->HashInCount = 0;
- hhash->HashBuffSize = 0;
- hhash->HashITCounter = 0;
- /* Reset digest calculation bridle (MDMAT bit control) */
- hhash->DigestCalculationDisable = RESET;
- /* Set phase to READY */
- hhash->Phase = HAL_HASH_PHASE_READY;
-
- /* Set the data type and reset MDMAT bit */
- MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType);
-
- /* Reset HASH handle status */
- hhash->Status = HAL_OK;
-
- /* Set the HASH state to Ready */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the HASH peripheral.
- * @param hhash: HASH handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
-{
- /* Check the HASH handle allocation */
- if(hhash == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Set the default HASH phase */
- hhash->Phase = HAL_HASH_PHASE_READY;
-
- /* Reset HashInCount, HashITCounter and HashBuffSize */
- hhash->HashInCount = 0;
- hhash->HashBuffSize = 0;
- hhash->HashITCounter = 0;
- /* Reset digest calculation bridle (MDMAT bit control) */
- hhash->DigestCalculationDisable = RESET;
-
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_HASH_MspDeInit(hhash);
-
- /* Reset HASH handle status */
- hhash->Status = HAL_OK;
-
- /* Set the HASH state to Ready */
- hhash->State = HAL_HASH_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the HASH MSP.
- * @param hhash: HASH handle.
- * @retval None
- */
-__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_HASH_MspInit() can be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitialize the HASH MSP.
- * @param hhash: HASH handle.
- * @retval None
- */
-__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_HASH_MspDeInit() can be implemented in the user file.
- */
-}
-
-/**
- * @brief Input data transfer complete call back.
- * @note HAL_HASH_InCpltCallback() is called when the complete input message
- * has been fed to the IP. This API is invoked only when input data are
- * entered under interruption or thru DMA.
- * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
- * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
- * to the IP.
- * @param hhash: HASH handle.
- * @retval None
- */
-__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_HASH_InCpltCallback() can be implemented in the user file.
- */
-}
-
-/**
- * @brief Digest computation complete call back.
- * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
- * relevant with DMA.
- * @param hhash: HASH handle.
- * @retval None
- */
-__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_HASH_DgstCpltCallback() can be implemented in the user file.
- */
-}
-
-/**
- * @brief Error callback.
- * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
- * to retrieve the error type.
- * @param hhash: HASH handle.
- * @retval None
- */
-__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- HAL_HASH_ErrorCallback() can be implemented in the user file.
- */
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- * @brief HASH processing functions using polling mode.
- *
-@verbatim
- ===============================================================================
- ##### Polling mode HASH processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) MD5
- (++) HAL_HASH_MD5_Start()
- (++) HAL_HASH_MD5_Accumulate()
- (+) SHA1
- (++) HAL_HASH_SHA1_Start()
- (++) HAL_HASH_SHA1_Accumulate()
-
- [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
-
- [..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
- to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASH_xxx_Start().
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief If not already done, initialize the HASH peripheral in MD5 mode then
- * processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
- * HASH signature once all buffers have been entered. Wrap-up of input
- * buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_MD5_Start().
- * @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
- * to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
- * processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
- * HASH signature once all buffers have been entered. Wrap-up of input
- * buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_SHA1_Start().
- * @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
- * to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- * @brief HASH processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### Interruption mode HASH processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) MD5
- (++) HAL_HASH_MD5_Start_IT()
- (+) SHA1
- (++) HAL_HASH_SHA1_Start_IT()
-
- [..] API HAL_HASH_IRQHandler() manages each HASH interruption.
-
- [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
- HMAC processing mode.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
-}
-
-
-/**
- * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @brief Handle HASH interrupt request.
- * @param hhash: HASH handle.
- * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
- * @note In case of error reported during the HASH interruption processing,
- * HAL_HASH_ErrorCallback() API is called so that user code can
- * manage the error. The error type is available in hhash->Status field.
- * @retval None
- */
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
-{
- hhash->Status = HASH_IT(hhash);
- if (hhash->Status != HAL_OK)
- {
- HAL_HASH_ErrorCallback(hhash);
- /* After error handling by code user, reset HASH handle HAL status */
- hhash->Status = HAL_OK;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- * @brief HASH processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### DMA mode HASH processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) MD5
- (++) HAL_HASH_MD5_Start_DMA()
- (++) HAL_HASH_MD5_Finish()
- (+) SHA1
- (++) HAL_HASH_SHA1_Start_DMA()
- (++) HAL_HASH_SHA1_Finish()
-
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
- to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
- HAL_HASH_xxx_Finish().
-
- [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
- the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
- reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
- retrieved thanks to HAL_HASH_xxx_Finish().
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
- * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
- * be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief Return the computed digest in MD5 mode.
- * @note The API waits for DCIS to be set then reads the computed digest.
- * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
- * HMAC MD5 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
- * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
- * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
- * be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-
-/**
- * @brief Return the computed digest in SHA1 mode.
- * @note The API waits for DCIS to be set then reads the computed digest.
- * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
- * HMAC SHA1 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- * @brief HMAC processing functions using polling mode.
- *
-@verbatim
- ===============================================================================
- ##### Polling mode HMAC processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (++) HAL_HMAC_MD5_Start()
- (+) SHA1
- (++) HAL_HMAC_SHA1_Start()
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- * @brief HMAC processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### Interrupt mode HMAC processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (++) HAL_HMAC_MD5_Start_IT()
- (+) SHA1
- (++) HAL_HMAC_SHA1_Start_IT()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
- * read the computed digest in interrupt mode.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
- * read the computed digest in interrupt mode.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @}
- */
-
-
-
-/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- * @brief HMAC processing functions using DMA modes.
- *
-@verbatim
- ===============================================================================
- ##### DMA mode HMAC processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (++) HAL_HMAC_MD5_Start_DMA()
- (+) SHA1
- (++) HAL_HMAC_SHA1_Start_DMA()
-
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
- user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
- with HAL_HASH_xxx_Finish().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
- * the computed digest.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note If MDMAT bit is set before calling this function (multi-buffer
- * HASH processing case), the input buffer size (in bytes) must be
- * a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * For the processing of the last buffer of the thread, MDMAT bit must
- * be reset and the buffer length (in bytes) doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
- * the computed digest.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note If MDMAT bit is set before calling this function (multi-buffer
- * HASH processing case), the input buffer size (in bytes) must be
- * a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * For the processing of the last buffer of the thread, MDMAT bit must
- * be reset and the buffer length (in bytes) doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State methods #####
- ===============================================================================
- [..]
- This section permits to get in run-time the state and the peripheral handle
- status of the peripheral:
- (+) HAL_HASH_GetState()
- (+) HAL_HASH_GetStatus()
-
- [..]
- Additionally, this subsection provides functions allowing to save and restore
- the HASH or HMAC processing context in case of calculation suspension:
- (+) HAL_HASH_ContextSaving()
- (+) HAL_HASH_ContextRestoring()
-
- [..]
- This subsection provides functions allowing to suspend the HASH processing
- (+) when input are fed to the IP by software
- (++) HAL_HASH_SwFeed_ProcessSuspend()
- (+) when input are fed to the IP by DMA
- (++) HAL_HASH_DMAFeed_ProcessSuspend()
-
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the HASH handle state.
- * @note The API yields the current state of the handle (BUSY, READY,...).
- * @param hhash: HASH handle.
- * @retval HAL HASH state
- */
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
-{
- return hhash->State;
-}
-
-
-/**
- * @brief Return the HASH HAL status.
- * @note The API yields the HAL status of the handle: it is the result of the
- * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
- * @param hhash: HASH handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
-{
- return hhash->Status;
-}
-
-/**
- * @brief Save the HASH context in case of processing suspension.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
- * is saved.
- * @note The IMR, STR, CR then all the CSR registers are saved
- * in that order. Only the r/w bits are read to be restored later on.
- * @note By default, all the context swap registers (there are
- * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
- * @note pMemBuffer points to a buffer allocated by the user. The buffer size
- * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
- * @retval None
- */
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
-{
- uint32_t mem_ptr = (uint32_t)pMemBuffer;
- uint32_t csr_ptr = (uint32_t)HASH->CSR;
- uint32_t i = 0;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* Save IMR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
- mem_ptr+=4;
- /* Save STR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
- mem_ptr+=4;
- /* Save CR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
- mem_ptr+=4;
- /* By default, save all CSRs registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
- {
- *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
- mem_ptr+=4;
- csr_ptr+=4;
- }
-}
-
-
-/**
- * @brief Restore the HASH context in case of processing resumption.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
- * is stored.
- * @note The IMR, STR, CR then all the CSR registers are restored
- * in that order. Only the r/w bits are restored.
- * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
- * of those) are restored (all of them have been saved by default
- * beforehand).
- * @retval None
- */
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
-{
- uint32_t mem_ptr = (uint32_t)pMemBuffer;
- uint32_t csr_ptr = (uint32_t)HASH->CSR;
- uint32_t i = 0;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhash);
-
- /* Restore IMR register content */
- WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4;
- /* Restore STR register content */
- WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4;
- /* Restore CR register content */
- WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4;
-
- /* Reset the HASH processor before restoring the Context
- Swap Registers (CSR) */
- __HAL_HASH_INIT();
-
- /* By default, restore all CSR registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--)
- {
- WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4;
- csr_ptr+=4;
- }
-}
-
-
-/**
- * @brief Initiate HASH processing suspension when in polling or interruption mode.
- * @param hhash: HASH handle.
- * @note Set the handle field SuspendRequest to the appropriate value so that
- * the on-going HASH processing is suspended as soon as the required
- * conditions are met. Note that the actual suspension is carried out
- * by the functions HASH_WriteData() in polling mode and HASH_IT() in
- * interruption mode.
- * @retval None
- */
-void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
-{
- /* Set Handle Suspend Request field */
- hhash->SuspendRequest = HAL_HASH_SUSPEND;
-}
-
-/**
- * @brief Suspend the HASH processing when in DMA mode.
- * @param hhash: HASH handle.
- * @note When suspension attempt occurs at the very end of a DMA transfer and
- * all the data have already been entered in the IP, hhash->State is
- * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
- * recommended to wrap-up the processing in reading the digest as usual.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
-{
- uint32_t tmp_remaining_DMATransferSize_inWords = 0x0;
- uint32_t tmp_initial_DMATransferSize_inWords = 0x0;
-
- if (hhash->State == HAL_HASH_STATE_READY)
- {
- return HAL_ERROR;
- }
- else
- {
- /* Set State as suspended (it may be required to update it if suspension failed).
- The context saving operations must be carried out to be able to resume later on. */
- hhash->State = HAL_HASH_STATE_SUSPENDED;
-
- /* Clear DMAE bit */
- CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
-
- /* Wait for DMAS to be reset */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable DMA channel */
- HAL_DMA_Abort(hhash->hdmain);
-
- /* At this point, DMA interface is disabled and no transfer is on-going */
- /* Retrieve from the DMA handle how many words remain to be written */
- tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
- if (tmp_remaining_DMATransferSize_inWords == 0)
- {
- /* All the DMA transfer is actually done. Suspension occurred at the very end
- of the transfer. Either the digest computation is about to start (HASH case)
- or processing is about to move from one step to another (HMAC case).
- In both cases, the processing can't be suspended at this point. It is
- safer to
- - retrieve the low priority block digest before starting the high
- priority block processing (HASH case)
- - re-attempt a new suspension (HMAC case)
- */
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
-
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
-
- /* Compute how many words were supposed to be transferred by DMA */
- tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ? (hhash->HashInCount+3)/4: hhash->HashInCount/4);
- /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
- hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
- /* And store in HashInCount the remaining size to transfer (in bytes) */
- hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords;
-
- }
-
- return HAL_OK;
-
- }
-}
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Private_Functions HASH Private Functions
- * @{
- */
-
-/**
- * @brief DMA HASH Input Data transfer completion callback.
- * @param hdma: DMA handle.
- * @note In case of HMAC processing, HASH_DMAXferCplt() initiates
- * the next DMA transfer for the following HMAC step.
- * @retval None
- */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0x0;
- uint32_t buffersize = 0x0;
-
- if (hhash->State != HAL_HASH_STATE_SUSPENDED)
- {
-
- /* Disable the DMA transfer */
- CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
-
- if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET)
- {
- /* If no HMAC processing, input data transfer is now over */
-
- /* Change the HASH state to ready */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete call back */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* HMAC processing: depending on the current HMAC step and whether or
- not multi-buffer processing is on-going, the next step is initiated
- and MDMAT bit is set. */
-
-
- if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
- {
- /* This is the end of HMAC processing */
-
- /* Change the HASH state to ready */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete call back
- (note that the last DMA transfer was that of the key
- for the outer HASH operation). */
- HAL_HASH_InCpltCallback(hhash);
-
- return;
- }
- else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
- {
- inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
- buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
-
- /* In case of suspension request, save the new starting parameters */
- hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
- hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
-
- /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
- if (hhash->DigestCalculationDisable != RESET)
- {
- /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
- no digest calculation will be triggered at the end of the input buffer feeding to the IP */
- __HAL_HASH_SET_MDMAT();
- }
- }
- else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- if (hhash->DigestCalculationDisable != RESET)
- {
- /* No automatic move to Step 3 as a new message buffer will be fed to the IP
- (case of multi-buffer HMAC processing):
- DCAL must not be set.
- Phase remains in Step 2, MDMAT remains set at this point.
- Change the HASH state to ready and call Input data transfer complete call back. */
- hhash->State = HAL_HASH_STATE_READY;
- HAL_HASH_InCpltCallback(hhash);
- return ;
- }
- else
- {
- /* Digest calculation is not disabled (case of single buffer input or last buffer
- of multi-buffer HMAC processing) */
- inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */
- buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
- /* In case of suspension request, save the new starting parameters */
- hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
- hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
- }
- }
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(buffersize);
-
-
- /* Set the HASH DMA transfert completion call back */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
-
- /* Enable DMA requests */
- SET_BIT(HASH->CR, HASH_CR_DMAE);
- }
- }
-
- return;
-}
-
-/**
- * @brief DMA HASH communication error callback.
- * @param hdma: DMA handle.
- * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
- * can contain user code to manage the error.
- * @retval None
- */
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if (hhash->State != HAL_HASH_STATE_SUSPENDED)
- {
- /* Set HASH state to ready to prevent any blocking issue in user code
- present in HAL_HASH_ErrorCallback() */
- hhash->State= HAL_HASH_STATE_READY;
- /* Set HASH handle status to error */
- hhash->Status = HAL_ERROR;
- HAL_HASH_ErrorCallback(hhash);
- /* After error handling by code user, reset HASH handle HAL status */
- hhash->Status = HAL_OK;
-
- }
-}
-
-/**
- * @brief Feed the input buffer to the HASH IP.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to input buffer.
- * @param Size: the size of input buffer in bytes.
- * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
- * or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
- * suspension time is stored in the handle for resumption later on.
- * @retval HAL status
- */
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t buffercounter;
- __IO uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
- {
- /* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size))
- {
- /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
- in the input buffer */
- if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- /* Reset SuspendRequest */
- hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
-
- /* Depending whether the key or the input data were fed to the IP, the feeding point
- reached at suspension time is not saved in the same handle fields */
- if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
- {
- /* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4);
- }
- else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
- {
- /* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4);
- }
- else
- {
- /* Unexpected phase: unlock process and report error */
- hhash->State = HAL_HASH_STATE_READY;
- __HAL_UNLOCK(hhash);
- return HAL_ERROR;
- }
-
- /* Set the HASH state to Suspended and exit to stop entering data */
- hhash->State = HAL_HASH_STATE_SUSPENDED;
-
- return HAL_OK;
- } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
- } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
- } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
-
- /* At this point, all the data have been entered to the IP: exit */
- return HAL_OK;
-}
-
-/**
- * @brief Retrieve the message digest.
- * @param pMsgDigest: pointer to the computed digest.
- * @param Size: message digest size in bytes.
- * @retval None
- */
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- /* Read the message digest */
- case 16: /* MD5 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
- case 20: /* SHA1 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- case 28: /* SHA224 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- break;
- case 32: /* SHA256 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
- break;
- default:
- break;
- }
-}
-
-
-
-/**
- * @brief Handle HASH processing Timeout.
- * @param hhash: HASH handle.
- * @param Flag: specifies the HASH flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_HASH_GET_FLAG(Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set State to Ready to be able to restart later on */
- hhash->State = HAL_HASH_STATE_READY;
- /* Store time out issue in handle status */
- hhash->Status = HAL_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_HASH_GET_FLAG(Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set State to Ready to be able to restart later on */
- hhash->State = HAL_HASH_STATE_READY;
- /* Store time out issue in handle status */
- hhash->Status = HAL_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief HASH processing in interruption mode.
- * @param hhash: HASH handle.
- * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
- * or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
- * suspension time is stored in the handle for resumption later on.
- * @retval HAL status
- */
-static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
-{
- if (hhash->State == HAL_HASH_STATE_BUSY)
- {
- /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
- if(hhash->HashITCounter == 0)
- {
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* HASH state set back to Ready to prevent any issue in user code
- present in HAL_HASH_ErrorCallback() */
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
- else if (hhash->HashITCounter == 1)
- {
- /* This is the first call to HASH_IT, the first input data are about to be
- entered in the IP. A specific processing is carried out at this point to
- start-up the processing. */
- hhash->HashITCounter = 2;
- }
- else
- {
- /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
- the HASH processing or the end of the current step for HMAC processing. */
- hhash->HashITCounter = 3;
- }
-
- /* If digest is ready */
- if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the digest */
- HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
-
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete call back */
- HAL_HASH_DgstCpltCallback(hhash);
-
- return HAL_OK;
- }
-
- /* If IP ready to accept new data */
- if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (hhash->HashInCount != 0))
- {
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
- /* Reset SuspendRequest */
- hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_SUSPENDED;
-
- return HAL_OK;
- }
-
- /* Enter input data in the IP thru HASH_Write_Block_Data() call and
- check whether the digest calculation has been triggered */
- if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
- {
- /* Call Input data transfer complete call back
- (called at the end of each step for HMAC) */
- HAL_HASH_InCpltCallback(hhash);
-
- if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
- {
- /* Wait until IP is not busy anymore */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
- {
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- return HAL_TIMEOUT;
- }
- /* Initialization start for HMAC STEP 2 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
- __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
- hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
- hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
- }
- else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /* Wait until IP is not busy anymore */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
- {
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- return HAL_TIMEOUT;
- }
- /* Initialization start for HMAC STEP 3 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
- hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
- hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
- }
- } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
- } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Write a block of data in HASH IP in interruption mode.
- * @param hhash: HASH handle.
- * @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
- * @retval HAL status
- */
-static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
-{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
- uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
-
- /* If there are more than 64 bytes remaining to be entered */
- if(hhash->HashInCount > 64)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register
- (16 32-bit words, or 64 bytes are entered) */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* If this is the start of input data entering, an additional word
- must be entered to start up the HASH processing */
- if(hhash->HashITCounter == 2)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- if(hhash->HashInCount >= 68)
- {
- /* There are still data waiting to be entered in the IP.
- Decrement buffer counter and set pointer to the proper
- memory location for the next data entering round. */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- /* All the input buffer has been fed to the HW. */
- hhash->HashInCount = 0;
- }
- }
- else
- {
- /* 64 bytes have been entered and there are still some remaining:
- Decrement buffer counter and set pointer to the proper
- memory location for the next data entering round.*/
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* 64 or less bytes remain to be entered. This is the last
- data entering round. */
-
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < (inputcounter+3)/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Return indication that digest calculation has started:
- this return value triggers the call to Input data transfer
- complete call back as well as the proper transition from
- one step to another in HMAC mode. */
- ret = HASH_DIGEST_CALCULATION_STARTED;
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- }
-
- /* Return whether or digest calculation has started */
- return ret;
-}
-
-/**
- * @brief HMAC processing in polling mode.
- * @param hhash: HASH handle.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
-{
- /* Ensure first that Phase is correct */
- if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* HMAC Step 1 processing */
- if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
- {
- /************************** STEP 1 ******************************************/
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in Data register */
- if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
- {
- return hhash->Status;
- }
-
- /* Check whether or not key entering process has been suspended */
- if (hhash->State == HAL_HASH_STATE_SUSPENDED)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Stop right there and return function status */
- return HAL_OK;
- }
-
- /* No processing suspension at this point: set DCAL bit. */
- __HAL_HASH_START_DIGEST();
-
- /* Wait for BUSY flag to be cleared */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Move from Step 1 to Step 2 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
-
- }
-
- /* HMAC Step 2 processing.
- After phase check, HMAC_Processing() may
- - directly start up from this point in resumption case
- if the same Step 2 processing was suspended previously
- - or fall through from the Step 1 processing carried out hereabove */
- if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /************************** STEP 2 ******************************************/
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
-
- /* Write input buffer in Data register */
- if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK)
- {
- return hhash->Status;
- }
-
- /* Check whether or not data entering process has been suspended */
- if (hhash->State == HAL_HASH_STATE_SUSPENDED)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Stop right there and return function status */
- return HAL_OK;
- }
-
- /* No processing suspension at this point: set DCAL bit. */
- __HAL_HASH_START_DIGEST();
-
- /* Wait for BUSY flag to be cleared */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Move from Step 2 to Step 3 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
- /* In case Step 1 phase was suspended then resumed,
- set again Key input buffers and size before moving to
- next step */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey;
- hhash->HashKeyCount = hhash->Init.KeySize;
- }
-
-
- /* HMAC Step 3 processing.
- After phase check, HMAC_Processing() may
- - directly start up from this point in resumption case
- if the same Step 3 processing was suspended previously
- - or fall through from the Step 2 processing carried out hereabove */
- if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
- {
- /************************** STEP 3 ******************************************/
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in Data register */
- if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK)
- {
- return hhash->Status;
- }
-
- /* Check whether or not key entering process has been suspended */
- if (hhash->State == HAL_HASH_STATE_SUSPENDED)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Stop right there and return function status */
- return HAL_OK;
- }
-
- /* No processing suspension at this point: start the Digest calculation. */
- __HAL_HASH_START_DIGEST();
-
- /* Wait for DCIS flag to be set */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Read the message digest */
- HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
- }
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the HASH peripheral, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
-{
- uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
- uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */
-
- /* Initiate HASH processing in case of start or resumption */
- if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Check if initialization phase has not been already performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
- input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
- Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
- }
- else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
- {
- /* if the IP has already been initialized, two cases are possible */
-
- /* Process resumption time ... */
- if (hhash->State == HAL_HASH_STATE_SUSPENDED)
- {
- /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
- to the API input parameters but to those saved beforehand by HASH_WriteData()
- when the processing was suspended */
- pInBuffer_tmp = hhash->pHashInBuffPtr;
- Size_tmp = hhash->HashInCount;
- }
- /* ... or multi-buffer HASH processing end */
- else
- {
- /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
- input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer;
- Size_tmp = Size;
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
- }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- }
- else
- {
- /* Phase error */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
-
- /* Write input buffer in Data register */
- if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
- {
- return hhash->Status;
- }
-
- /* If the process has not been suspended, carry on to digest calculation */
- if (hhash->State != HAL_HASH_STATE_SUSPENDED)
- {
- /* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Wait for DCIS flag to be set */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief If not already done, initialize the HASH peripheral then
- * processes pInBuffer.
- * @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
-{
- uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
- uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */
-
- /* Make sure the input buffer size (in bytes) is a multiple of 4 */
- assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
-
-
- /* Initiate HASH processing in case of start or resumption */
- if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* If resuming the HASH processing */
- if (hhash->State == HAL_HASH_STATE_SUSPENDED)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
- to the API input parameters but to those saved beforehand by HASH_WriteData()
- when the processing was suspended */
- pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
- Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
-
- }
- else
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
- input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
- Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
-
- /* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- }
-
- /* Write input buffer in Data register */
- if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK)
- {
- return hhash->Status;
- }
-
- /* If the process has not been suspended, move the state to Ready */
- if (hhash->State != HAL_HASH_STATE_SUSPENDED)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-
-
-}
-
-
-/**
- * @brief Initialize the HASH peripheral, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
-{
-
- /* If State is ready or suspended, start or resume IT-based HASH processing */
- if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Initialize IT counter */
- hhash->HashITCounter = 1;
-
- /* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
-
- hhash->HashInCount = Size; /* Counter used to keep track of number of data
- to be fed to the IP */
- hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at
- the next interruption */
- /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
- the information describing where the HASH process is stopped.
- These variables are used later on to resume the HASH processing at the
- correct location. */
-
- hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-
-/**
- * @brief Initialize the HASH peripheral then initiate a DMA transfer
- * to feed the input buffer to the IP.
- * @note If MDMAT bit is set before calling this function (multi-buffer
- * HASH processing case), the input buffer size (in bytes) must be
- * a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * For the processing of the last buffer of the thread, MDMAT bit must
- * be reset and the buffer length (in bytes) doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
-{
- uint32_t inputaddr;
- uint32_t inputSize = 0x0;
-
- /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
- (case of multi-buffer HASH processing) */
- assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
-
- /* If State is ready or suspended, start or resume DMA-based HASH processing */
- if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ( (pInBuffer == NULL ) || (Size == 0) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or PROCESS (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* If not a resumption case */
- if (hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed.
- If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
- API is processing a new input data message in case of multi-buffer HASH
- computation. */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
- }
-
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */
- inputSize = Size; /* DMA transfer size (in bytes) */
-
- /* In case of suspension request, save the starting parameters */
- hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */
- hhash->HashInCount = Size; /* DMA transfer size (in bytes) */
-
- }
- /* If resumption case */
- else
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Resumption case, inputaddr and inputSize are not set to the API input parameters
- but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
- processing was suspended */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
- inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
- }
-
- /* Set the HASH DMA transfert complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
-
- /* Enable DMA requests */
- SET_BIT(HASH->CR, HASH_CR_DMAE);
-
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-/**
- * @brief Return the computed digest.
- * @note The API waits for DCIS to be set then reads the computed digest.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Check parameter */
- if (pOutBuffer == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state to busy */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Wait for DCIS flag to be set */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
- /* Change the HASH state to ready */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
-{
-
- /* If State is ready or suspended, start or resume polling-based HASH processing */
- if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64)
- {
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- /* Set the phase to Step 1 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- /* Resort to hhash internal fields to feed the IP.
- Parameters will be updated in case of suspension to contain the proper
- information at resumption time. */
- hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
- hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */
- hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */
- hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
- hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */
- }
-
- /* Carry out HMAC processing */
- return HMAC_Processing(hhash, Timeout);
-
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
-{
- /* If State is ready or suspended, start or resume IT-based HASH processing */
- if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Initialize IT counter */
- hhash->HashITCounter = 1;
-
- /* Check if initialization phase has already be performed */
- if (hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64)
- {
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
-
- /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
- to feed the IP whatever the HMAC step.
- Lines below are set to start HMAC Step 1 processing where key is entered first. */
- hhash->HashInCount = hhash->Init.KeySize; /* Key size */
- hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
-
- /* Store input and output parameters in handle fields to manage steps transition
- or possible HMAC suspension/resumption */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
- hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */
- hhash->HashBuffSize = Size; /* Input message size (in bytes) */
- hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
-
- /* Configure the number of valid bits in last word of the key */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Set the phase to Step 1 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- }
- else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
- {
- /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
-
- }
- else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /* Restart IT-based HASH processing after Step 2 suspension */
-
- }
- else
- {
- /* Error report as phase incorrect */
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
- * be a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * Only the length of the last buffer of the thread doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
- * @retval HAL status
- */
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
-{
- uint32_t inputaddr;
- uint32_t inputSize = 0x0;
-
- /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
- is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
- assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
-
- /* If State is ready or suspended, start or resume DMA-based HASH processing */
- if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED))
- {
- /* Check input parameters */
- if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or one of HMAC PROCESS steps (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
- {
- hhash->State = HAL_HASH_STATE_READY;
- return HAL_ERROR;
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* If not a case of resumption after suspension */
- if (hhash->State == HAL_HASH_STATE_READY)
- {
- /* Check whether or not initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
- At the same time, ensure MDMAT bit is cleared. */
- if(hhash->Init.KeySize > 64)
- {
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
-
- /* Store input aparameters in handle fields to manage steps transition
- or possible HMAC suspension/resumption */
- hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
- hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
- hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
- hhash->HashBuffSize = Size; /* input data size (in bytes) */
-
- /* Set DMA input parameters */
- inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
- inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
-
- /* Configure the number of valid bits in last word of the key */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Set the phase to Step 1 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-
- }
- else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /* Process a new input data message in case of multi-buffer HMAC processing
- (this is not a resumption case) */
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save input parameters to be able to manage possible suspension/resumption */
- hhash->HashInCount = Size; /* Input message address */
- hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
-
- /* Set DMA input parameters */
- inputaddr = (uint32_t)pInBuffer; /* Input message address */
- inputSize = Size; /* Input message size in bytes */
-
- if (hhash->DigestCalculationDisable == RESET)
- {
- /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
- __HAL_HASH_RESET_MDMAT();
- __HAL_HASH_SET_NBVALIDBITS(inputSize);
- }
- }
- else
- {
- /* Phase not aligned with handle READY state */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_ERROR;
- }
- }
- else
- {
- /* Resumption case (phase may be Step 1, 2 or 3) */
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Set DMA input parameters at resumption location;
- inputaddr and inputSize are not set to the API input parameters
- but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
- processing was suspended. */
- inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */
- inputSize = hhash->HashInCount; /* Input message size in bytes */
- }
-
-
- /* Set the HASH DMA transfert complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4));
- /* Enable DMA requests */
- SET_BIT(HASH->CR, HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_HASH_MODULE_ENABLED */
-/**
- * @}
- */
-#endif /* HASH */
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c
deleted file mode 100644
index 833953c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c
+++ /dev/null
@@ -1,930 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hash_ex.c
- * @author MCD Application Team
- * @brief Extended HASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the HASH peripheral for SHA-224 and SHA-256
- * alogrithms:
- * + HASH or HMAC processing in polling mode
- * + HASH or HMAC processing in interrupt mode
- * + HASH or HMAC processing in DMA mode
- * Additionally, this file provides functions to manage HMAC
- * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
- * and SHA-256.
- *
- *
- @verbatim
- ===============================================================================
- ##### HASH peripheral extended features #####
- ===============================================================================
- [..]
- The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
- the same way as for SHA-1 or MD-5 algorithms.
- (#) Three modes are available.
- (##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished,
- e.g. HAL_HASHEx_xxx_Start()
- (##) Interrupt mode: processing APIs are not blocking functions
- i.e. they process the data under interrupt,
- e.g. HAL_HASHEx_xxx_Start_IT()
- (##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA,
- e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
- HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
-
- (#)Multi-buffer processing is possible in polling and DMA mode.
- (##) In polling mode, only multi-buffer HASH processing is possible.
- API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
- well the computed digest.
-
- (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
-
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
- Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
- same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
- API HAL_HASHEx_xxx_Finish().
-
- (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
- extended functions): after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
- starts step 2.
- The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
- point, the HMAC processing is still carrying out step 2.
- Then, step 2 for the last input buffer and step 3 are carried out by a single call
- to HAL_HMACEx_xxx_Step2_3_DMA().
-
- The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
- MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_HASH_MODULE_ENABLED
-
-#if defined (HASH)
-
-/** @defgroup HASHEx HASHEx
- * @brief HASH HAL extended module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
- * @{
- */
-
-
-/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
- * @brief HASH extended processing functions using polling mode.
- *
-@verbatim
- ===============================================================================
- ##### Polling mode HASH extended processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HASHEx_SHA224_Start()
- (++) HAL_HASHEx_SHA224_Accumulate()
- (+) SHA256
- (++) HAL_HASHEx_SHA256_Start()
- (++) HAL_HASHEx_SHA256_Accumulate()
-
- [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
-
- [..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
- to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASHEx_xxx_Start().
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
- * processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
- * HASH signature once all buffers have been entered. Wrap-up of input
- * buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA224_Start().
- * @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
- * to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
- * processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
- * HASH signature once all buffers have been entered. Wrap-up of input
- * buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA256_Start().
- * @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
- * to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
- * @brief HASH extended processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### Interruption mode HASH extended processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HASHEx_SHA224_Start_IT()
- (+) SHA256
- (++) HAL_HASHEx_SHA256_Start_IT()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
- * read the computed digest in interruption mode.
- * @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
- * @brief HASH extended processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### DMA mode HASH extended processing functionss #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HASHEx_SHA224_Start_DMA()
- (++) HAL_HASHEx_SHA224_Finish()
- (+) SHA256
- (++) HAL_HASHEx_SHA256_Start_DMA()
- (++) HAL_HASHEx_SHA256_Finish()
-
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
- to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
- HAL_HASHEx_xxx_Finish().
-
- [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
- the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
- reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
- retrieved thanks to HAL_HASHEx_xxx_Finish().
-
-@endverbatim
- * @{
- */
-
-
-
-
-/**
- * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
- * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
- * be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Return the computed digest in SHA224 mode.
- * @note The API waits for DCIS to be set then reads the computed digest.
- * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
- * HMAC SHA224 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
- * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
- * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
- * be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @brief Return the computed digest in SHA256 mode.
- * @note The API waits for DCIS to be set then reads the computed digest.
- * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
- * HMAC SHA256 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
- * @brief HMAC extended processing functions using polling mode.
- *
-@verbatim
- ===============================================================================
- ##### Polling mode HMAC extended processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HMACEx_SHA224_Start()
- (+) SHA256
- (++) HAL_HMACEx_SHA256_Start()
-
-@endverbatim
- * @{
- */
-
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
- * read the computed digest.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
- * @brief HMAC extended processing functions using interruption mode.
- *
-@verbatim
- ===============================================================================
- ##### Interrupt mode HMAC extended processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HMACEx_SHA224_Start_IT()
- (+) SHA256
- (++) HAL_HMACEx_SHA256_Start_IT()
-
-@endverbatim
- * @{
- */
-
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
- * read the computed digest in interrupt mode.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
- * read the computed digest in interrupt mode.
- * @note Digest is available in pOutBuffer.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
-}
-
-
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### DMA mode HMAC extended processing functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (++) HAL_HMACEx_SHA224_Start_DMA()
- (+) SHA256
- (++) HAL_HMACEx_SHA256_Start_DMA()
-
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
- user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
- with HAL_HASHEx_xxx_Finish().
-
-
-@endverbatim
- * @{
- */
-
-
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
- * the computed digest.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note If MDMAT bit is set before calling this function (multi-buffer
- * HASH processing case), the input buffer size (in bytes) must be
- * a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * For the processing of the last buffer of the thread, MDMAT bit must
- * be reset and the buffer length (in bytes) doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
- * the computed digest.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note If MDMAT bit is set before calling this function (multi-buffer
- * HASH processing case), the input buffer size (in bytes) must be
- * a multiple of 4 otherwise, the HASH digest computation is corrupted.
- * For the processing of the last buffer of the thread, MDMAT bit must
- * be reset and the buffer length (in bytes) doesn't have to be a
- * multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions in multi-buffer DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### Multi-buffer DMA mode HMAC extended processing functions #####
- ===============================================================================
- [..] This section provides functions to manage HMAC multi-buffer
- DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
- (+) MD5
- (++) HAL_HMACEx_MD5_Step1_2_DMA()
- (++) HAL_HMACEx_MD5_Step2_DMA()
- (++) HAL_HMACEx_MD5_Step2_3_DMA()
- (+) SHA1
- (++) HAL_HMACEx_SHA1_Step1_2_DMA()
- (++) HAL_HMACEx_SHA1_Step2_DMA()
- (++) HAL_HMACEx_SHA1_Step2_3_DMA()
- (+) SHA256
- (++) HAL_HMACEx_SHA224_Step1_2_DMA()
- (++) HAL_HMACEx_SHA224_Step2_DMA()
- (++) HAL_HMACEx_SHA224_Step2_3_DMA()
- (+) SHA256
- (++) HAL_HMACEx_SHA256_Step1_2_DMA()
- (++) HAL_HMACEx_SHA256_Step2_DMA()
- (++) HAL_HMACEx_SHA256_Step2_3_DMA()
-
- [..] User must first start-up the multi-buffer DMA-based HMAC computation in
- calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
- intiates step 2 with the first input buffer.
-
- [..] The following buffers are next fed to the IP with a call to the API
- HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
- to this API.
-
- [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
- HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
- buffer to the IP then carries out step 3.
-
- [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
- SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
-
- [..] If only two buffers need to be consecutively processed, a call to
- HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
- is sufficient.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
- * step 2 consists in writing the message text.
- * @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
- * the message buffer feeding, allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = SET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief MD5 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
- * @note The API carries on the HMAC step 2, applied to the buffer entered as input
- * parameter. DCAL bit is not automatically set after the message buffer feeding,
- * allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- if (hhash->DigestCalculationDisable != SET)
- {
- return HAL_ERROR;
- }
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-/**
- * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
- * step 3 consists in writing the outer hash function key.
- * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
- * parameter (the input buffer must be the last one of the multi-buffer thread)
- * then carries out HMAC step 3.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
- * the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = RESET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-
-/**
- * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
- * step 2 consists in writing the message text.
- * @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
- * the message buffer feeding, allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = SET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
- * @note The API carries on the HMAC step 2, applied to the buffer entered as input
- * parameter. DCAL bit is not automatically set after the message buffer feeding,
- * allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- if (hhash->DigestCalculationDisable != SET)
- {
- return HAL_ERROR;
- }
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
- * step 3 consists in writing the outer hash function key.
- * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
- * parameter (the input buffer must be the last one of the multi-buffer thread)
- * then carries out HMAC step 3.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
- * the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = RESET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
- * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
- * step 2 consists in writing the message text.
- * @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
- * the message buffer feeding, allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = SET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
- * @note The API carries on the HMAC step 2, applied to the buffer entered as input
- * parameter. DCAL bit is not automatically set after the message buffer feeding,
- * allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- if (hhash->DigestCalculationDisable != SET)
- {
- return HAL_ERROR;
- }
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
- * step 3 consists in writing the outer hash function key.
- * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
- * parameter (the input buffer must be the last one of the multi-buffer thread)
- * then carries out HMAC step 3.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
- * the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = RESET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
-}
-
-/**
- * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
- * step 2 consists in writing the message text.
- * @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
- * the message buffer feeding, allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = SET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
- * @note The API carries on the HMAC step 2, applied to the buffer entered as input
- * parameter. DCAL bit is not automatically set after the message buffer feeding,
- * allowing other messages DMA transfers to occur.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- if (hhash->DigestCalculationDisable != SET)
- {
- return HAL_ERROR;
- }
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
- * step 3 consists in writing the outer hash function key.
- * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
- * parameter (the input buffer must be the last one of the multi-buffer thread)
- * then carries out HMAC step 3.
- * @note Same key is used for the inner and the outer hash functions; pointer to key and
- * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @note Once the DMA transfers are finished (indicated by hhash->State set back
- * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
- * the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
- hhash->DigestCalculationDisable = RESET;
- return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HASH */
-
-#endif /* HAL_HASH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c
deleted file mode 100644
index 54fa914..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c
+++ /dev/null
@@ -1,1232 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hcd.c
- * @author MCD Application Team
- * @brief HCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#)Declare a HCD_HandleTypeDef handle structure, for example:
- HCD_HandleTypeDef hhcd;
-
- (#)Fill parameters of Init structure in HCD handle
-
- (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
-
- (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
- (##) Enable the HCD/USB Low Level interface clock using the following macros
- (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
- (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
-
- (##) Initialize the related GPIO clocks
- (##) Configure HCD pin-out
- (##) Configure HCD NVIC interrupt
-
- (#)Associate the Upper USB Host stack to the HAL HCD Driver:
- (##) hhcd.pData = phost;
-
- (#)Enable HCD transmission and reception:
- (##) HAL_HCD_Start();
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HCD HCD
- * @brief HCD HAL module driver
- * @{
- */
-
-#ifdef HAL_HCD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function ----------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
-static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Functions HCD Exported Functions
- * @{
- */
-
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the host driver.
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
-{
- /* Check the HCD handle allocation */
- if(hhcd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
-
- hhcd->State = HAL_HCD_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_HCD_MspInit(hhcd);
-
- /* Disable the Interrupts */
- __HAL_HCD_DISABLE(hhcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hhcd->Instance, hhcd->Init);
-
- /* Force Host Mode*/
- USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
-
- /* Init Host */
- USB_HostInit(hhcd->Instance, hhcd->Init);
-
- hhcd->State= HAL_HCD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @param epnum: Endpoint number.
- * This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
- * This parameter can be a value from 0 to 255
- * @param speed: Current device speed.
- * This parameter can be one of these values:
- * HCD_SPEED_HIGH: High speed mode,
- * HCD_SPEED_FULL: Full speed mode,
- * HCD_SPEED_LOW: Low speed mode
- * @param ep_type: Endpoint Type.
- * This parameter can be one of these values:
- * EP_TYPE_CTRL: Control type,
- * EP_TYPE_ISOC: Isochronous type,
- * EP_TYPE_BULK: Bulk type,
- * EP_TYPE_INTR: Interrupt type
- * @param mps: Max Packet Size.
- * This parameter can be a value from 0 to32K
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(hhcd);
-
- hhcd->hc[ch_num].dev_addr = dev_address;
- hhcd->hc[ch_num].max_packet = mps;
- hhcd->hc[ch_num].ch_num = ch_num;
- hhcd->hc[ch_num].ep_type = ep_type;
- hhcd->hc[ch_num].ep_num = epnum & 0x7F;
- hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
- hhcd->hc[ch_num].speed = speed;
-
- status = USB_HC_Init(hhcd->Instance,
- ch_num,
- epnum,
- dev_address,
- speed,
- ep_type,
- mps);
- __HAL_UNLOCK(hhcd);
-
- return status;
-}
-
-/**
- * @brief Halt a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(hhcd);
- USB_HC_Halt(hhcd->Instance, ch_num);
- __HAL_UNLOCK(hhcd);
-
- return status;
-}
-
-/**
- * @brief DeInitialize the host driver.
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
-{
- /* Check the HCD handle allocation */
- if(hhcd == NULL)
- {
- return HAL_ERROR;
- }
-
- hhcd->State = HAL_HCD_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_HCD_MspDeInit(hhcd);
-
- __HAL_HCD_DISABLE(hhcd);
-
- hhcd->State = HAL_HCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the HCD MSP.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the HCD MSP.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief HCD IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USB Host Data
- Transfer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Submit a new URB for processing.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @param direction: Channel number.
- * This parameter can be one of these values:
- * 0 : Output / 1 : Input
- * @param ep_type: Endpoint Type.
- * This parameter can be one of these values:
- * EP_TYPE_CTRL: Control type/
- * EP_TYPE_ISOC: Isochronous type/
- * EP_TYPE_BULK: Bulk type/
- * EP_TYPE_INTR: Interrupt type/
- * @param token: Endpoint Type.
- * This parameter can be one of these values:
- * 0: HC_PID_SETUP / 1: HC_PID_DATA1
- * @param pbuff: pointer to URB data
- * @param length: Length of URB data
- * @param do_ping: activate do ping protocol (for high speed only).
- * This parameter can be one of these values:
- * 0 : do ping inactive / 1 : do ping active
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping)
-{
- hhcd->hc[ch_num].ep_is_in = direction;
- hhcd->hc[ch_num].ep_type = ep_type;
-
- if(token == 0)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
-
- /* Manage Data Toggle */
- switch(ep_type)
- {
- case EP_TYPE_CTRL:
- if((token == 1) && (direction == 0)) /*send data */
- {
- if ( length == 0 )
- { /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1;
- }
-
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
- }
- }
- break;
-
- case EP_TYPE_BULK:
- if(direction == 0)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
-
- break;
- case EP_TYPE_INTR:
- if(direction == 0)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- break;
-
- case EP_TYPE_ISOC:
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
- }
-
- hhcd->hc[ch_num].xfer_buff = pbuff;
- hhcd->hc[ch_num].xfer_len = length;
- hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0 ;
- hhcd->hc[ch_num].ch_num = ch_num;
- hhcd->hc[ch_num].state = HC_IDLE;
-
- return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
-}
-
-/**
- * @brief Handle HCD interrupt request.
- * @param hhcd: HCD handle
- * @retval None
- */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t i = 0 , interrupt = 0;
-
- /* ensure that we are in device mode */
- if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
- {
- /* avoid spurious interrupt */
- if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
- {
- return;
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
- }
-
- /* Handle Host Disconnect Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
- {
-
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- /* Handle Host Port Interrupts */
- HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
- }
-
- /* Handle Host Port Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
- {
- HCD_Port_IRQHandler (hhcd);
- }
-
- /* Handle Host SOF Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
- {
- HAL_HCD_SOF_Callback(hhcd);
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
- }
-
- /* Handle Host channel Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
- {
- interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
- for (i = 0; i < hhcd->Init.Host_channels ; i++)
- {
- if (interrupt & (1 << i))
- {
- if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
- {
- HCD_HC_IN_IRQHandler (hhcd, i);
- }
- else
- {
- HCD_HC_OUT_IRQHandler (hhcd, i);
- }
- }
- }
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
- }
-
- /* Handle Rx Queue Level Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- HCD_RXQLVL_IRQHandler (hhcd);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
- }
-}
-
-/**
- * @brief SOF callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_SOF_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Connection Event callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Connect_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disconnection Event callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Disconnect_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Notify URB state change callback.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @param urb_state:
- * This parameter can be one of these values:
- * URB_IDLE/
- * URB_DONE/
- * URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
- * URB_STALL/
- * @retval None
- */
-__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- UNUSED(chnum);
- UNUSED(urb_state);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief Management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the HCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the host driver.
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
- __HAL_HCD_ENABLE(hhcd);
- USB_DriveVbus(hhcd->Instance, 1);
- __HAL_UNLOCK(hhcd);
- return HAL_OK;
-}
-
-/**
- * @brief Stop the host driver.
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
- USB_StopHost(hhcd->Instance);
- __HAL_UNLOCK(hhcd);
- return HAL_OK;
-}
-
-/**
- * @brief Reset the host port.
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
-{
- return (USB_ResetPort(hhcd->Instance));
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the HCD handle state.
- * @param hhcd: HCD handle
- * @retval HAL state
- */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
-{
- return hhcd->State;
-}
-
-/**
- * @brief Return URB state for a channel.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval URB state.
- * This parameter can be one of these values:
- * URB_IDLE/
- * URB_DONE/
- * URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
- * URB_STALL
- */
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].urb_state;
-}
-
-
-/**
- * @brief Return the last host transfer size.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval last transfer size in byte
- */
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].xfer_count;
-}
-
-/**
- * @brief Return the Host Channel state.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval Host channel state
- * This parameter can be one of these values:
- * HC_IDLE/
- * HC_XFRC/
- * HC_HALTED/
- * HC_NYET/
- * HC_NAK/
- * HC_STALL/
- * HC_XACTERR/
- * HC_BBLERR/
- * HC_DATATGLERR
- */
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].state;
-}
-
-/**
- * @brief Return the current Host frame number.
- * @param hhcd: HCD handle
- * @retval Current Host frame number
- */
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
-{
- return (USB_GetCurrentFrame(hhcd->Instance));
-}
-
-/**
- * @brief Return the Host enumeration speed.
- * @param hhcd: HCD handle
- * @retval Enumeration speed
- */
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
-{
- return (USB_GetHostSpeed(hhcd->Instance));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup HCD_Private_Functions
- * @{
- */
-/**
- * @brief Handle Host Channel IN interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval none
- */
-static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0;
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].state = HC_STALL;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- USB_HC_Halt(hhcd->Instance, chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- hhcd->hc[chnum].state = HC_DATATGLERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- }
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
- {
-
- if (hhcd->Init.dma_enable)
- {
- hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
- (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
- }
-
- hhcd->hc[chnum].state = HC_XFRC;
- hhcd->hc[chnum].ErrCnt = 0;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
-
-
- if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-
- }
- else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
- {
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
- hhcd->hc[chnum].urb_state = URB_DONE;
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
- hhcd->hc[chnum].toggle_in ^= 1;
-
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
- {
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
- if(hhcd->hc[chnum].state == HC_XFRC)
- {
- hhcd->hc[chnum].urb_state = URB_DONE;
- }
-
- else if (hhcd->hc[chnum].state == HC_STALL)
- {
- hhcd->hc[chnum].urb_state = URB_STALL;
- }
-
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
- {
- if(hhcd->hc[chnum].ErrCnt++ > 3)
- {
- hhcd->hc[chnum].ErrCnt = 0;
- hhcd->hc[chnum].urb_state = URB_ERROR;
- }
- else
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- }
- else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
- {
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- }
-}
-
-/**
- * @brief Handle Host Channel OUT interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval none
- */
-static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0;
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
-
- if( hhcd->hc[chnum].do_ping == 1)
- {
- hhcd->hc[chnum].state = HC_NYET;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
- {
- hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt= 0;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
-
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
- {
- hhcd->hc[chnum].ErrCnt = 0;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
- hhcd->hc[chnum].state = HC_XFRC;
-
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_STALL;
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- hhcd->hc[chnum].ErrCnt = 0;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_XACTERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- hhcd->hc[chnum].state = HC_DATATGLERR;
- }
-
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
- {
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
- if(hhcd->hc[chnum].state == HC_XFRC)
- {
- hhcd->hc[chnum].urb_state = URB_DONE;
- if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
- {
- hhcd->hc[chnum].toggle_out ^= 1;
- }
- }
- else if (hhcd->hc[chnum].state == HC_NAK)
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- else if (hhcd->hc[chnum].state == HC_NYET)
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- hhcd->hc[chnum].do_ping = 0;
- }
-
- else if (hhcd->hc[chnum].state == HC_STALL)
- {
- hhcd->hc[chnum].urb_state = URB_STALL;
- }
-
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
- {
- if(hhcd->hc[chnum].ErrCnt++ > 3)
- {
- hhcd->hc[chnum].ErrCnt = 0;
- hhcd->hc[chnum].urb_state = URB_ERROR;
- }
- else
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
-
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
-}
-
-/**
- * @brief Handle Rx Queue Level interrupt requests.
- * @param hhcd: HCD handle
- * @retval none
- */
-static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0;
- uint32_t pktsts;
- uint32_t pktcnt;
- uint32_t temp = 0;
- uint32_t tmpreg = 0;
-
- temp = hhcd->Instance->GRXSTSP ;
- channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
- pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
- pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-
- switch (pktsts)
- {
- case GRXSTS_PKTSTS_IN:
- /* Read the data into the host buffer. */
- if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
- {
-
- USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-
- /*manage multiple Xfer */
- hhcd->hc[channelnum].xfer_buff += pktcnt;
- hhcd->hc[channelnum].xfer_count += pktcnt;
-
- if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
- {
- /* re-activate the channel when more packets are expected */
- tmpreg = USBx_HC(channelnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(channelnum)->HCCHAR = tmpreg;
- hhcd->hc[channelnum].toggle_in ^= 1;
- }
- }
- break;
-
- case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
- break;
- case GRXSTS_PKTSTS_IN_XFER_COMP:
- case GRXSTS_PKTSTS_CH_HALTED:
- default:
- break;
- }
-}
-
-/**
- * @brief Handle Host Port interrupt requests.
- * @param hhcd: HCD handle
- * @retval None
- */
-static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- __IO uint32_t hprt0, hprt0_dup;
-
- /* Handle Host Port Interrupts */
- hprt0 = USBx_HPRT0;
- hprt0_dup = USBx_HPRT0;
-
- hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- /* Check whether Port Connect detected */
- if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
- {
- if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- HAL_HCD_Connect_Callback(hhcd);
- }
- hprt0_dup |= USB_OTG_HPRT_PCDET;
-
- }
-
- /* Check whether Port Enable Changed */
- if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
- {
- hprt0_dup |= USB_OTG_HPRT_PENCHNG;
-
- if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
- {
- if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
- {
- if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
- {
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
- }
- else
- {
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
- }
- }
- else
- {
- if(hhcd->Init.speed == HCD_SPEED_FULL)
- {
- USBx_HOST->HFIR = (uint32_t)60000;
- }
- }
- HAL_HCD_Connect_Callback(hhcd);
-
- if(hhcd->Init.speed == HCD_SPEED_HIGH)
- {
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- }
- }
- else
- {
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- }
- }
-
- /* Check For an overcurrent */
- if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
- {
- hprt0_dup |= USB_OTG_HPRT_POCCHNG;
- }
-
- /* Clear Port Interrupts */
- USBx_HPRT0 = hprt0_dup;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_HCD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c
deleted file mode 100644
index a96082e..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c
+++ /dev/null
@@ -1,7836 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hrtim.c
- * @author MCD Application Team
- * @brief HRTIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Resolution Timer (HRTIM) peripheral:
- * + HRTIM Initialization
- * + Timer Time Base Unit Configuration
- * + Simple Time Base Start/Stop
- * + Simple Time Base Start/Stop Interrupt
- * + Simple Time Base Start/Stop DMA Request
- * + Simple Output Compare/PWM Channel Configuration
- * + Simple Output Compare/PWM Channel Start/Stop Interrupt
- * + Simple Output Compare/PWM Channel Start/Stop DMA Request
- * + Simple Input Capture Channel Configuration
- * + Simple Input Capture Channel Start/Stop Interrupt
- * + Simple Input Capture Channel Start/Stop DMA Request
- * + Simple One Pulse Channel Configuration
- * + Simple One Pulse Channel Start/Stop Interrupt
- * + HRTIM External Synchronization Configuration
- * + HRTIM Burst Mode Controller Configuration
- * + HRTIM Burst Mode Controller Enabling
- * + HRTIM External Events Conditioning Configuration
- * + HRTIM Faults Conditioning Configuration
- * + HRTIM Faults Enabling
- * + HRTIM ADC trigger Configuration
- * + Waveform Timer Configuration
- * + Waveform Event Filtering Configuration
- * + Waveform Dead Time Insertion Configuration
- * + Waveform Chopper Mode Configuration
- * + Waveform Compare Unit Configuration
- * + Waveform Capture Unit Configuration
- * + Waveform Output Configuration
- * + Waveform Counter Start/Stop
- * + Waveform Counter Start/Stop Interrupt
- * + Waveform Counter Start/Stop DMA Request
- * + Waveform Output Enabling
- * + Waveform Output Level Set/Get
- * + Waveform Output State Get
- * + Waveform Burst DMA Operation Configuration
- * + Waveform Burst DMA Operation Start
- * + Waveform Timer Counter Software Reset
- * + Waveform Capture Software Trigger
- * + Waveform Burst Mode Controller Software Trigger
- * + Waveform Timer Pre-loadable Registers Update Enabling
- * + Waveform Timer Pre-loadable Registers Software Update
- * + Waveform Timer Delayed Protection Status Get
- * + Waveform Timer Burst Status Get
- * + Waveform Timer Push-Pull Status Get
- * + Peripheral State Get
- @verbatim
- ==============================================================================
- ##### Simple mode v.s. waveform mode #####
-==============================================================================
- [..] The HRTIM HAL API is split into 2 categories:
- (#)Simple functions: these functions allow for using a HRTIM timer as a
- general purpose timer with high resolution capabilities.
- Following simple modes are proposed:
- (+)Output compare mode
- (+)PWM output mode
- (+)Input capture mode
- (+)One pulse mode
- HRTIM simple modes are managed through the set of functions named
- HAL_HRTIM_Simple. These functions are similar in name and usage
- to the one defined for the TIM peripheral. When a HRTIM timer operates in
- simple mode, only a very limited set of HRTIM features are used.
- (#)Waveform functions: These functions allow taking advantage of the HRTIM
- flexibility to produce numerous types of control signal. When a HRTIM timer
- operates in waveform mode, all the HRTIM features are accessible without
- any restriction. HRTIM waveform modes are managed through the set of
- functions named HAL_HRTIM_Waveform
-
-==============================================================================
- ##### How to use this driver #####
-==============================================================================
- [..]
- (#)Initialize the HRTIM low level resources by implementing the
- HAL_HRTIM_MspInit() function:
- (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
- (##)Connect HRTIM pins to MCU I/Os
- (+++) Enable the clock for the HRTIM GPIOs using the following
- function: __GPIOx_CLK_ENABLE()
- (+++) Configure these GPIO pins in Alternate Function mode using
- HAL_GPIO_Init()
- (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
- (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++)Initialize the DMA handle
- (+++)Associate the initialized DMA handle to the appropriate DMA
- handle of the HRTIM handle using __HAL_LINKDMA()
- (+++)Initialize the DMA channel using HAL_DMA_Init()
- (+++)Configure the priority and enable the NVIC for the transfer
- complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
- and HAL_NVIC_EnableIRQ()
- (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
- (+++)Configure the priority and enable the NVIC for the concerned
- HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
-
- (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
- structure (field of the HRTIM handle) specifies which global interrupt of
- whole HRTIM must be enabled (Burst mode period, System fault, Faults).
- It also contains the HRTIM external synchronization configuration. HRTIM
- can act as a master (generating a synchronization signal) or as a slave
- (waiting for a trigger to be synchronized).
-
- (#) Configure HRTIM resources shared by all HRTIM timers
- (##)Burst Mode Controller:
- (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
- controller: operating mode (continuous or -shot mode), clock
- (source, prescaler) , trigger(s), period, idle duration.
- (##)External Events Conditionning:
- (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
- external event channel: source, polarity, edge-sensitivity.
- External event can be used as triggers (timer reset, input
- capture, burst mode, ADC triggers, delayed protection, …)
- They can also be used to set or reset timer outputs. Up to
- 10 event channels are available.
- (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
- event sampling clock (used for digital filtering).
- (##)Fault Conditionning:
- (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
- fault channel: source, polarity, edge-sensitivity. Fault
- channels are used to disable the outputs in case of an
- abnormal operation. Up to 5 fault channels are available.
- (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
- sampling clock (used for digital filtering).
- (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
- circuitry. By default all fault inputs are disabled.
- (##)ADC trigger:
- (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
- the update of the ADC trigger register and the ADC trigger.
- 4 independent triggers are available to start both the regular
- and the injected sequencers of the 2 ADCs
-
- (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
- function must be called whatever the HRTIM timer operating mode is
- (simple v.s. waveform). It configures mainly:
- (##)The HRTIM timer counter operating mode (continuous, one shot)
- (##)The HRTIM timer clock prescaler
- (##)The HRTIM timer period
- (##)The HRTIM timer repetition counter
-
- (#) If the HRTIM timer operates in simple mode:
- (##)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
- HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
- HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
- (##)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
- HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
- HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
- HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
- (##)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
- HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
- HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
- HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
- (##)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
- HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
- HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
- HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
- (##)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
- HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
- HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
-
- (#) If the HRTIM timer operates in waveform mode:
- (##)Completes waveform timer configuration
- (+++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM
- timer operating in wave form mode mainly consists in:
- - Enabling the HRTIM timer interrupts and DMA requests,
- - Enabling the half mode for the HRTIM timer,
- - Defining how the HRTIM timer reacts to external
- synchronization input,
- - Enabling the push-pull mode for the HRTIM timer,
- - Enabling the fault channels for the HRTIM timer,
- - Enabling the deadtime insertion for the HRTIM timer,
- - Setting the delayed protection mode for the HRTIM timer
- (source and outputs on which the delayed protection are applied),
- - Specifying the HRTIM timer update and reset triggers,
- - Specifying the HRTIM timer registers update policy (preload enabling, …).
- (+++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
- event blanking and windowingcircuitry of a HRTIM timer:
- - Blanking: to mask external events during a defined
- time period
- - Windowing: to enable external events only during
- a defined time period
- (+++)HAL_HRTIM_DeadTimeConfig(): configures the deadtime insertion
- unit for a HRTIM timer. Allows to generate a couple of
- complementary signals from a single reference waveform,
- with programmable delays between active state.
- (+++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
- the high-frequency carrier signal added on top of the timing
- unit output. Chopper mode can be enabled or disabled for each
- timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
- (+++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
- controller. Allows having multiple HRTIM registers updated
- with a single DMA request. The burst DMA operation is started
- by calling HAL_HRTIM_BurstDMATransfer().
- (+++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
- of a HRTIM timer. This operation consists in setting the
- compare value and possibly specifying the auto delayed mode
- for compare units 2 and 4 (allows to have compare events
- generated relatively to capture events). Note that when auto
- delayed mode is needed, the capture unit associated to the
- compare unit must be configured separately.
- (+++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
- of a HRTIM timer. This operation consists in specifying the
- source(s) triggering the capture (timer register update event,
- external event, timer output set/reset event, other HRTIM
- timer related events).
- (+++)HAL_HRTIM_WaveformOutputConfig(): configuration HRTIM timer
- output manly consists in:
- - Setting the output polarity (active high or active low),
- - Defining the set/reset crossbar for the output,
- - Specifying the fault level (active or inactive) in IDLE
- and FAULT states.,
- (##)Set waveform timer output(s) level
- (+++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
- active or inactive level. For example, when deadtime insertion
- is enabled it is necessary to force the output level by software
- to have the outputs in a complementary state as soon as the RUN mode is entered.
- (##)Enable/Disable waveform timer output(s)
- (+++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
- (##)Start/Stop waveform HRTIM timer(s).
- (+++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
- (+++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
- (+++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
-
- (##)Burst mode controller enabling:
- (+++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
- burst mode controller.
-
- (##)Some HRTIM operations can be triggered by software:
- (+++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
- trigs the burst operation.
- (+++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
- capture of the HRTIM timer counter.
- (+++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
- update of the pre-loadable registers of the HRTIM timer ()
- (+++)HAL_HRTIM_SoftwareReset():calling this function resets the
- HRTIM timer counter.
-
- (##)Some functions can be used anytime to retrieve HRTIM timer related
- information
- (+++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
- capture register of the designated capture unit.
- (+++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
- (ACTIVE/INACTIVE) of the designated timer output.
- (+++)HAL_HRTIM_WaveformGetOutputState():returns actual state
- (IDLE/RUN/FAULT) of the designated timer output.
- (+++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
- (ACTIVE/INACTIVE) of the designated output when the delayed
- protection was triggered.
- (+++)HAL_HRTIM_GetBurstStatus(): returns the actual status
- (ACTIVE/INACTIVE) of the burst mode controller.
- (+++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
- is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
- the push-pull indicates on which output the signal is currently
- active (e.g signal applied on output 1 and output 2 forced
- inactive or vice versa).
- (+++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
- is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
- the idle push-pull status indicates during which period the
- delayed protection request occurred (e.g. protection occurred
- when the output 1 was active and output 2 forced inactive or
- vice versa).
-
- (##)Some functions can be used anytime to retrieve actual HRTIM status
- (+++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
-
-/** @defgroup HRTIM HRTIM
- * @brief HRTIM HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup HRTIM_Private_Defines HRTIM Private Define
- * @{
- */
-#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
- HRTIM_FLTR_FLT2EN |\
- HRTIM_FLTR_FLT3EN |\
- HRTIM_FLTR_FLT4EN | \
- HRTIM_FLTR_FLT5EN)
-
-#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
- HRTIM_TIMUPDATETRIGGER_TIMER_A |\
- HRTIM_TIMUPDATETRIGGER_TIMER_B |\
- HRTIM_TIMUPDATETRIGGER_TIMER_C |\
- HRTIM_TIMUPDATETRIGGER_TIMER_D |\
- HRTIM_TIMUPDATETRIGGER_TIMER_E)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HRTIM_Private_Variables HRTIM Private Variables
- * @{
- */
-static uint32_t TimerIdxToTimerId[] =
-{
- HRTIM_TIMERID_TIMER_A,
- HRTIM_TIMERID_TIMER_B,
- HRTIM_TIMERID_TIMER_C,
- HRTIM_TIMERID_TIMER_D,
- HRTIM_TIMERID_TIMER_E,
- HRTIM_TIMERID_MASTER,
-};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HRTIM_Private_Functions HRTIM Private Functions
- * @{
- */
-static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * pCompareCfg);
-
-static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event);
-
-static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg);
-
-static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef * pEventCfg);
-
-static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event);
-
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
-
-static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
-
-static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
- * @{
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Time Base Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize a HRTIM instance
- (+) De-initialize a HRTIM instance
- (+) Initialize the HRTIM MSP
- (+) De-initialize the HRTIM MSP
- (+) Configure the time base unit of a HRTIM timer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
-{
- uint8_t timer_idx;
- uint32_t hrtim_mcr;
-
- /* Check the HRTIM handle allocation */
- if(hhrtim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
- assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Initialize the DMA handles */
- hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
-
- /* HRTIM output synchronization configuration (if required) */
- if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
- assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
-
- /* The synchronization output initialization procedure must be done prior
- to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
- */
- if (hhrtim->Instance == HRTIM1)
- {
- /* Enable the HRTIM peripheral clock */
- __HAL_RCC_HRTIM1_CLK_ENABLE();
- }
-
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the event to be sent on the synchronization output */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
- hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
-
- /* Set the polarity of the synchronization output */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
- hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- }
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_HRTIM_MspInit(hhrtim);
-
- /* HRTIM input synchronization configuration (if required) */
- if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
-
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the synchronization input source */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
- hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- }
-
- /* Initialize the HRTIM state*/
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Initialize the lock status of the HRTIM HAL API */
- __HAL_UNLOCK(hhrtim);
-
- /* Tnitialize timer related parameters */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx <= HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
- hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
- hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
- hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
- hhrtim->TimerParam[timer_idx].DMASrcAddress = 0;
- hhrtim->TimerParam[timer_idx].DMASize = 0;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-initializes a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
-{
- /* Check the HRTIM handle allocation */
- if(hhrtim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_HRTIM_MspDeInit(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief MSP initialization for a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_HRTIM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief MSP initialization for a for a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_HRTIM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Configures the time base unit of a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimeBaseCfg: pointer to the time base configuration structure
- * @note This function must be called prior starting the timer
- * @note The time-base unit initialization parameters specify:
- * The timer counter operating mode (continuous, one shot),
- * The timer clock prescaler,
- * The timer period,
- * The timer repetition counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
- assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure master timer time base unit */
- HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
- }
- else
- {
- /* Configure timing unit time base unit */
- HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
- }
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
- * @brief Simple time base mode functions.
- *
-@verbatim
- ===============================================================================
- ##### Simple time base mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start simple time base
- (+) Stop simple time base
- (+) Start simple time base and enable interrupt
- (+) Stop simple time base and disable interrupt
- (+) Start simple time base and enable DMA transfer
- (+) Stop simple time base and disable DMA transfer
- -@- When a HRTIM timer operates in simple time base mode, the timer
- counter counts from 0 to the period value.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the counter of a timer operating in basic time base mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in basic time base mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of a timer operating in simple time base mode
- * (Timer repetition interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the repetition interrupt */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in simple time base mode
- * (Timer repetition interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the repetition interrupt */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of a timer operating in simple time base mode
- * (Timer repetition DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
- * from source to destination
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- if(hhrtim->State == HAL_HRTIM_STATE_READY)
- {
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Set the DMA transfer completed callback */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
- }
- else
- {
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer repetition DMA request */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in simple time base mode
- * (Timer repetition DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Disable the DMA */
- HAL_DMA_Abort(hhrtim->hdmaMaster);
-
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
- }
- else
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
- * @brief Simple output compare functions
- *
-@verbatim
- ===============================================================================
- ##### Simple output compare functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple output channel
- (+) Start simple output compare
- (+) Stop simple output compare
- (+) Start simple output compare and enable interrupt
- (+) Stop simple output compare and disable interrupt
- (+) Start simple output compare and enable DMA transfer
- (+) Stop simple output compare and disable DMA transfer
- -@- When a HRTIM timer operates in simple output compare mode
- the output level is set to a programmable value when a match
- is found between the compare register and the counter.
- Compare unit 1 is automatically associated to output 1
- Compare unit 2 is automatically associated to output 2
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output in simple output compare mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOCChannelCfg: pointer to the simple output compare output configuration structure
- * @note When the timer operates in simple output compare mode:
- * Output 1 is implicitly controlled by the compare unit 1
- * Output 2 is implicitly controlled by the compare unit 2
- * Output Set/Reset crossbar is set according to the selected output compare mode:
- * Toggle: SETxyR = RSTxyR = CMPy
- * Active: SETxyR = CMPy, RSTxyR = 0
- * Inactive: SETxy =0, RSTxy = CMPy
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg = {0};
- HRTIM_OutputCfgTypeDef OutputCfg = {0};
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
- assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- }
-
- CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
- OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- switch (pSimpleOCChannelCfg->Mode)
- {
- case HRTIM_BASICOCMODE_TOGGLE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = OutputCfg.SetSource;
- }
- break;
- case HRTIM_BASICOCMODE_ACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
- }
- break;
- case HRTIM_BASICOCMODE_INACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
- }
- else
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
- }
- OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
- }
- break;
- }
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- OCChannel,
- &OutputCfg);
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * (Interrupt is enabled (see note note below)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @note Interrupt enabling depends on the chosen output compare mode
- * Output toggle: compare match interrupt is enabled
- * Output set active: output set interrupt is enabled
- * Output set inactive: output reset interrupt is enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t interrupt;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the interrupt to enable (depends on the output compare mode) */
- interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Enable the timer interrupt (depends on the output compare mode) */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * (Interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t interrupt;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Get the interrupt to disable (depends on the output compare mode) */
- interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Disable the timer interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * (DMA request is enabled (see note below)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
- * from source to destination
- * @note DMA request enabling depends on the chosen output compare mode
- * Output toggle: compare match DMA request is enabled
- * Output set active: output set DMA request is enabled
- * Output set inactive: output reset DMA request is enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
- uint32_t dma_request;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Get the DMA request to enable */
- dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * (DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- DMA_HandleTypeDef * hdma;
- uint32_t dma_request;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Get the DMA request to disable */
- dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Disable the timer DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
- * @brief Simple PWM output functions
-
-@verbatim
- ===============================================================================
- ##### Simple PWM output functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple PWM output channel
- (+) Start simple PWM output
- (+) Stop simple PWM output
- (+) Start simple PWM output and enable interrupt
- (+) Stop simple PWM output and disable interrupt
- (+) Start simple PWM output and enable DMA transfer
- (+) Stop simple PWM output and disable DMA transfer
- -@- When a HRTIM timer operates in simple PWM output mode
- the output level is set to a programmable value when a match is
- found between the compare register and the counter and reset when
- the timer period is reached. Duty cycle is determined by the
- comparison value.
- Compare unit 1 is automatically associated to output 1
- Compare unit 2 is automatically associated to output 2
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output in simple PWM mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimplePWMChannelCfg: pointer to the simple PWM output configuration structure
- * @note When the timer operates in simple PWM output mode:
- * Output 1 is implicitly controlled by the compare unit 1
- * Output 2 is implicitly controlled by the compare unit 2
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * @note When Simple PWM mode is used the registers preload mechanism is
- * enabled (otherwise the behavior is not guaranteed).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
- uint32_t hrtim_timcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- }
-
- CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
- OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- PWMChannel,
- &OutputCfg);
-/* Enable the registers preload mechanism */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
- hrtim_timcr |= HRTIM_TIMCR_PREEN;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * (The compare interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Enable the timer interrupt (depends on the PWM output) */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * (The compare interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Disable the timer interrupt (depends on the PWM output) */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * (The compare DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
- * from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer DMA request */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * (The compare DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the timer DMA request */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
- }
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
- * @brief Simple input capture functions
-
-@verbatim
- ===============================================================================
- ##### Simple input capture functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple input capture channel
- (+) Start simple input capture
- (+) Stop simple input capture
- (+) Start simple input capture and enable interrupt
- (+) Stop simple input capture and disable interrupt
- (+) Start simple input capture and enable DMA transfer
- (+) Stop simple input capture and disable DMA transfer
- -@- When a HRTIM timer operates in simple input capture mode
- the Capture Register (HRTIM_CPT1/2xR) is used to latch the
- value of the timer counter counter after a transition detected
- on a given external event input.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures a simple capture
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Capture unit
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pSimpleCaptureChannelCfg: pointer to the simple capture configuration structure
- * @note When the timer operates in simple capture mode the capture is trigerred
- * by the designated external event and GPIO input is implicitly used as event source.
- * The cature can be triggered by a rising edge, a falling edge or both
- * edges on event channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
-{
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
- assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
- pSimpleCaptureChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
- pSimpleCaptureChannelCfg->EventFilter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
- EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_EventConfig(hhrtim,
- pSimpleCaptureChannelCfg->Event,
- &EventCfg);
-
- /* Memorize capture trigger (will be configured when the capture is started */
- HRTIM_CaptureUnitConfig(hhrtim,
- TimerIdx,
- CaptureChannel,
- pSimpleCaptureChannelCfg->Event);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a simple capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- * @note The external event triggering the capture is available for all timing
- * units. It can be used directly and is active as soon as the timing
- * unit counter is enabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a simple capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a basic capture on the designed capture unit
- * (Capture interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
-
- /* Enable the capture unit 1 interrupt */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
-
- /* Enable the capture unit 2 interrupt */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a basic capture on the designed capture unit
- * (Capture interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 1 interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 2 interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
- }
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a basic capture on the designed capture unit
- * (Capture DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
- * from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- /* Set the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
-
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- /* Set the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a basic capture on the designed capture unit
- * (Capture DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- /* Reset the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 1 DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- /* Reset the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 2 DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
- }
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
- * @brief Simple one pulse functions
-
-@verbatim
- ===============================================================================
- ##### Simple one pulse functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure one pulse channel
- (+) Start one pulse generation
- (+) Stop one pulse generation
- (+) Start one pulse generation and enable interrupt
- (+) Stop one pulse generation and disable interrupt
- -@- When a HRTIM timer operates in simple one pulse mode
- the timer counter is started in response to transition detected
- on a given external event input to generate a pulse with a
- programmable length after a programmable delay.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output simple one pulse mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
- * @note When the timer operates in basic one pulse mode:
- * the timer counter is implicitely started by the reset event,
- * the reset of the timer counter is triggered by the designated external event
- * GPIO input is implicitly used as event source,
- * Output 1 is implicitly controlled by the compare unit 1,
- * Output 2 is implicitly controlled by the compare unit 2.
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * @retval HAL status
- * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
- * outputs, the reset event related configuration data provided in the
- * second call will override the reset event related configuration data
- * provided in the first call.
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel,
- HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
- assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
- pSimpleOnePulseChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
- pSimpleOnePulseChannelCfg->EventFilter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- }
-
- CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
- OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- OnePulseChannel,
- &OutputCfg);
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
- EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_EventConfig(hhrtim,
- pSimpleOnePulseChannelCfg->Event,
- &EventCfg);
-
- /* Configure the timer reset register */
- HRTIM_TIM_ResetConfig(hhrtim,
- TimerIdx,
- pSimpleOnePulseChannelCfg->Event);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the simple one pulse signal generation on the designed output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the simple one pulse signal generation on the designed output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the simple one pulse signal generation on the designed output
- * (The compare interrupt is enabled (pulse start)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
-
- /* Enable the timer interrupt (depends on the OnePulse output) */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the simple one pulse signal generation on the designed output
- * (The compare interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
-
- /* Disable the timer interrupt (depends on the OnePulse output) */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
- * @brief HRTIM configuration functions
-
-@verbatim
- ===============================================================================
- ##### HRTIM configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the HRTIM
- resources shared by all the HRTIM timers operating in waveform mode:
- (+) Configure the burst mode controller
- (+) Configure an external event conditionning
- (+) Configure the external events sampling clock
- (+) Configure a fault conditionning
- (+) Enable or disable fault inputs
- (+) Configure the faults sampling clock
- (+) Configure an ADC trigger
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the burst mode feature of the HRTIM
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pBurstModeCfg: pointer to the burst mode configuration structure
- * @retval HAL status
- * @note This function must be called before starting the burst mode
- * controller
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
-{
- uint32_t hrtim_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
- assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
- assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
- assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
- assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Set the burst mode operating mode */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
- hrtim_bmcr |= pBurstModeCfg->Mode;
-
- /* Set the burst mode clock source */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
- hrtim_bmcr |= pBurstModeCfg->ClockSource;
-
- /* Set the burst mode prescaler */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
- hrtim_bmcr |= pBurstModeCfg->Prescaler;
-
- /* Enable/disable burst mode registers preload */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
- hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
-
- /* Set the burst mode trigger */
- hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
-
- /* Set the burst mode compare value */
- hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
-
- /* Set the burst mode period */
- hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the conditioning of an external event
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Event: external event to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pEventCfg: pointer to the event conditioning configuration structure
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef* pEventCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
- assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
- assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
- assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the event channel */
- HRTIM_EventConfig(hhrtim, Event, pEventCfg);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the external event conditioning block prescaler
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Prescaler: Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
- * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
- * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
- * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Prescaler)
-{
- uint32_t hrtim_eecr3;
-
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the external event prescaler */
- hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
- hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
- hrtim_eecr3 |= Prescaler;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the conditioning of fault input
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Fault: fault input to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param pFaultCfg: pointer to the fault conditioning configuration structure
- * @note This function must be called before starting the timer and before
- * enabling faults inputs
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Fault,
- HRTIM_FaultCfgTypeDef* pFaultCfg)
-{
- uint32_t hrtim_fltinr1;
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Fault));
- assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
- assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
- assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
- assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure fault channel */
- hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
-
- switch (Fault)
- {
- case HRTIM_FAULT_1:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
- hrtim_fltinr1 |= pFaultCfg->Polarity;
- hrtim_fltinr1 |= pFaultCfg->Source;
- hrtim_fltinr1 |= pFaultCfg->Filter;
- hrtim_fltinr1 |= pFaultCfg->Lock;
- }
- break;
- case HRTIM_FAULT_2:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 8);
- hrtim_fltinr1 |= (pFaultCfg->Source << 8);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 8);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 8);
- }
- break;
- case HRTIM_FAULT_3:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 16);
- hrtim_fltinr1 |= (pFaultCfg->Source << 16);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 16);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 16);
- }
- break;
- case HRTIM_FAULT_4:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 24);
- hrtim_fltinr1 |= (pFaultCfg->Source << 24);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 24);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 24);
- }
- break;
- case HRTIM_FAULT_5:
- {
- hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
- hrtim_fltinr2 |= pFaultCfg->Polarity;
- hrtim_fltinr2 |= pFaultCfg->Source;
- hrtim_fltinr2 |= pFaultCfg->Filter;
- hrtim_fltinr2 |= pFaultCfg->Lock;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the fault conditioning block prescaler
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Prescaler: Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
- * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
- * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
- * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
- * @retval HAL status
- * @note This function must be called before starting the timer and before
- * enabling faults inputs
- */
-HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Prescaler)
-{
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the external event prescaler */
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
- hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
- hrtim_fltinr2 |= Prescaler;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the HRTIMx Fault mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Faults: fault input(s) to enable or disable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param Enable: Fault(s) enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
- * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
- * @retval None
- */
-void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Faults,
- uint32_t Enable)
-{
- uint32_t hrtim_fltinr1;
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Faults));
- assert_param(IS_HRTIM_FAULTMODECTL(Enable));
-
- /* Configure fault channel */
- hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
-
- if ((Faults & HRTIM_FAULT_1) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
- hrtim_fltinr1 |= Enable;
- }
- if ((Faults & HRTIM_FAULT_2) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
- hrtim_fltinr1 |= (Enable << 8);
- }
- if ((Faults & HRTIM_FAULT_3) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
- hrtim_fltinr1 |= (Enable << 16);
- }
- if ((Faults & HRTIM_FAULT_4) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
- hrtim_fltinr1 |= (Enable << 24);
- }
- if ((Faults & HRTIM_FAULT_5) != RESET)
- {
- hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
- hrtim_fltinr2 |= Enable;
- }
-
- /* Update the HRTIMx registers */
- hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-}
-
-/**
- * @brief Configures both the ADC trigger register update source and the ADC
- * trigger source.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param ADCTrigger: ADC trigger to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
- * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
- * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
- * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
- * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t ADCTrigger,
- HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
-{
- uint32_t hrtim_cr1;
-
- /* Check parameters */
- assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
- assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the ADC trigger update source */
- hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
-
- switch (ADCTrigger)
- {
- case HRTIM_ADCTRIGGER_1:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
- hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
-
- /* Set the ADC trigger 1 source */
- hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_2:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC);
-
- /* Set the ADC trigger 2 source */
- hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_3:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC);
-
- /* Set the ADC trigger 3 source */
- hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_4:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC);
-
- /* Set the ADC trigger 4 source */
- hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
- }
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
- * @brief HRTIM timer configuration and control functions
-
-@verbatim
- ===============================================================================
- ##### HRTIM timer configuration and control functions #####
- ===============================================================================
- [..] This section provides functions used to configure and control a
- HRTIM timer operating in waveform mode:
- (+) Configure HRTIM timer general behavior
- (+) Configure HRTIM timer event filtering
- (+) Configure HRTIM timer deadtime insertion
- (+) Configure HRTIM timer chopper mode
- (+) Configure HRTIM timer burst DMA
- (+) Configure HRTIM timer compare unit
- (+) Configure HRTIM timer capture unit
- (+) Configure HRTIM timer output
- (+) Set HRTIM timer output level
- (+) Enable HRTIM timer output
- (+) Disable HRTIM timer output
- (+) Start HRTIM timer
- (+) Stop HRTIM timer
- (+) Start HRTIM timer and enable interrupt
- (+) Stop HRTIM timer and disable interrupt
- (+) Start HRTIM timer and enable DMA transfer
- (+) Stop HRTIM timer and disable DMA transfer
- (+) Enable or disable the burst mode controller
- (+) Start the burst mode controller (by software)
- (+) Trigger a Capture (by software)
- (+) Update the HRTIM timer preloadable registers (by software)
- (+) Reset the HRTIM timer counter (by software)
- (+) Start a burst DMA transfer
- (+) Enable timer register update
- (+) Disable timer register update
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the general behavior of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimerCfg: pointer to the timer configuration structure
- * @note When the timer operates in waveform mode, all the features supported by
- * the HRTIM are available without any limitation.
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Relevant for all HRTIM timers, including the master */
- assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
- assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
- assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
- assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
- assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
- assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
- assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
- assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
- assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
-
- /* Configure master timer */
- HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
- }
- else
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
- assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
- assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
- assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
- assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
- assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
- assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
- pTimerCfg->DeadTimeInsertion));
- assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
- pTimerCfg->DelayedProtectionMode));
- assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
- assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
- assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
-
- /* Configure timing unit */
- HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
- }
-
- /* Update timer parameters */
- hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
- hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
- hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
- hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
- hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
-
- /* Force a software update */
- HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Event: external event for which timer event filtering must be configured
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event,
- HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
-{
- uint32_t hrtim_eefr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_EVENT(Event));
- assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
- assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer event filtering capabilities */
- switch (Event)
- {
- case HRTIM_EVENT_NONE:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0;
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0;
- }
- break;
- case HRTIM_EVENT_1:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
- hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
- hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the deadtime insertion feature for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pDeadTimeCfg: pointer to the deadtime insertion configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
-{
- uint32_t hrtim_dtr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
-
- /* Clear timer deadtime configuration */
- hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
- HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
- HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
-
- /* Set timer deadtime configuration */
- hrtim_dtr |= pDeadTimeCfg->Prescaler;
- hrtim_dtr |= pDeadTimeCfg->RisingValue;
- hrtim_dtr |= pDeadTimeCfg->RisingSign;
- hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
- hrtim_dtr |= pDeadTimeCfg->RisingLock;
- hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16);
- hrtim_dtr |= pDeadTimeCfg->FallingSign;
- hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
- hrtim_dtr |= pDeadTimeCfg->FallingLock;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the chopper mode feature for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pChopperModeCfg: pointer to the chopper mode configuration structure
- * @retval HAL status
- * @note This function must be called before configuring the timer output(s)
- */
-HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
-{
- uint32_t hrtim_chpr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
- assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
- assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
-
- /* Clear timer chopper mode configuration */
- hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
-
- /* Set timer choppe mode configuration */
- hrtim_chpr |= pChopperModeCfg->CarrierFreq;
- hrtim_chpr |= (pChopperModeCfg->DutyCycle);
- hrtim_chpr |= (pChopperModeCfg->StartPulse);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the burst DMA controller for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param RegistersToUpdate: registers to be written by DMA
- * This parameter can be any combination of the following values:
- * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
- * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
- * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
- * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
- * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
- * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
- * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
- * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
- * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
- * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
- * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
- * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
- * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
- * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
- * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
- * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
- * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
- * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
- * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
- * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
- * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t RegistersToUpdate)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the burst DMA timer update register */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_MASTER:
- {
- hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
- }
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the compare unit of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CompareUnit: Compare unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param pCompareCfg: pointer to the compare unit configuration structure
- * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
- * application has to configure separately the capture unit. Capture unit
- * to configure in that case depends on the compare unit auto delayed mode
- * is applied to (see below):
- * Auto delayed on output compare 2: capture unit 1 must be configured
- * Auto delayed on output compare 4: capture unit 2 must be configured
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef* pCompareCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the compare unit */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
- }
- break;
- }
- }
- else
- {
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
-
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- /* DELCMP2 bitfield must be reset when reprogrammed from one value */
- /* to the other to reinitialize properly the auto-delayed mechanism */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
-
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- /* DELCMP4 bitfield must be reset when reprogrammed from one value */
- /* to the other to reinitialize properly the auto-delayed mechanism */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2);
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- }
- }
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the capture unit of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pCaptureCfg: pointer to the compare unit configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- HRTIM_CaptureCfgTypeDef* pCaptureCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
- }
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the output of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pOutputCfg: pointer to the timer output configuration structure
- * @retval HAL status
- * @note This function must be called before configuring the timer and after
- * configuring the deadtime insertion feature (if required).
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
- assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
- assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
- assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
- assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the timer output */
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- Output,
- pOutputCfg);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Forces the timer output to its active or inactive state
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param OutputLevel: indicates whether the output is forced to its active or inactive level
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
- * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
- * @retval HAL status
- * @note The 'software set/reset trigger' bit in the output set/reset registers
- * is automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- uint32_t OutputLevel)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
- }
- }
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output enabling.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param OutputsToStart: Timer output(s) to enable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t OutputsToStart)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the HRTIM outputs */
- hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output disabling.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param OutputsToStop: Timer output(s) to disable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t OutputsToStop)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the HRTIM outputs */
- hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_TIMER_A
- * @arg HRTIM_TIMERID_TIMER_B
- * @arg HRTIM_TIMERID_TIMER_C
- * @arg HRTIM_TIMERID_TIMER_D
- * @arg HRTIM_TIMERID_TIMER_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
- * to the timers to start are enabled within this function.
- * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
- * function.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable HRTIM interrupts (if required) */
- __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
-
- /* Enable master timer related interrupts (if required) */
- if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
- {
- __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
- }
-
- /* Enable timing unit related interrupts (if required) */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].InterruptRequests);
- }
- }
-
- /* Enable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- * @note All enabled timer related interrupts are disabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* ++ WA */
- __IO uint32_t delai = (uint32_t)(0x17F);
- /* -- WA */
-
- uint8_t timer_idx;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable HRTIM interrupts (if required) */
- __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
-
- /* Disable master timer related interrupts (if required) */
- if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
- {
- /* Interrupts enable flag must be cleared one by one */
- __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
- }
-
- /* Disable timing unit related interrupts (if required) */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
- }
- }
-
- /* ++ WA */
- do { delai--; } while (delai != 0);
- /* -- WA */
-
- /* Disable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
- * @retval HAL status
- * @note This function enables the dma request(s) mentionned in the timer
- * configuration data structure for every timers to start.
- * @note The source memory address, the destination memory address and the
- * size of each DMA transfer are specified at timer configuration time
- * (see HAL_HRTIM_WaveformTimerConfig)
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
- {
- /* Set the DMA error callback */
- hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hhrtim->hdmaMaster,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
- }
-
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0))
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma,
- hhrtim->TimerParam[timer_idx].DMASrcAddress,
- hhrtim->TimerParam[timer_idx].DMADstAddress,
- hhrtim->TimerParam[timer_idx].DMASize);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].DMARequests);
- }
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- * @note All enabled timer related DMA requests are disabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
- {
- /* Disable the DMA */
- HAL_DMA_Abort(hhrtim->hdmaMaster);
-
- /* Disable the DMA request(s) */
- __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
- }
-
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0))
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the DMA request(s) */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].DMARequests);
- }
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the HRTIM burst mode controller.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Enable: Burst mode controller enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
- * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
- * @retval HAL status
- * @note This function must be called after starting the timer(s)
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Enable)
-{
- uint32_t hrtim_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODECTL(Enable));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable/Disable the burst mode controller */
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
- hrtim_bmcr &= ~(HRTIM_BMCR_BME);
- hrtim_bmcr |= Enable;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the burst mode operation.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
-{
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Software trigger of the burst mode controller */
- hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers a software capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- * @note The 'software capture' bit in the capure configuration register is
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force a software capture on concerned capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
- }
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the update of the registers of one or several timers
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: timers concerned with the software register update
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- * @note The 'software update' bits in the HRTIM conrol register 2 register are
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR2 |= Timers;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the reset of one or several timers
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: timers concerned with the software counter reset
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERRESET_MASTER
- * @arg HRTIM_TIMERRESET_TIMER_A
- * @arg HRTIM_TIMERRESET_TIMER_B
- * @arg HRTIM_TIMERRESET_TIMER_C
- * @arg HRTIM_TIMERRESET_TIMER_D
- * @arg HRTIM_TIMERRESET_TIMER_E
- * @retval HAL status
- * @note The 'software reset' bits in the HRTIM conrol register 2 are
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERRESET(Timers));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer(s) registers reset */
- hhrtim->Instance->sCommonRegs.CR2 = Timers;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts a burst DMA operation to update HRTIM control registers content
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param BurstBufferAddress: address of the buffer the HRTIM control registers
- * content will be updated from.
- * @param BurstBufferLength: size (in WORDS) of the burst buffer.
- * @retval HAL status
- * @note The TimerIdx parameter determines the dma channel to be used by the
- * DMA burst controller (see below)
- * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t BurstBufferAddress,
- uint32_t BurstBufferLength)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_BurstDMACplt;
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma,
- BurstBufferAddress,
- (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
- BurstBufferLength);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the transfer from preload to active registers for one
- * or several timing units (including master timer).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer(s) concerned by the register preload enabling command
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
- }
-
-/**
- * @brief Disables the transfer from preload to active registers for one
- * or several timing units (including master timer).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer(s) concerned by the register preload disabling command
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
- }
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
- * @brief Peripheral State functions
-
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..] This section provides functions used to get HRTIM or HRTIM timer
- specific information:
- (+) Get HRTIM HAL state
- (+) Get captured value
- (+) Get HRTIM timer output level
- (+) Get HRTIM timer output state
- (+) Get delayed protection status
- (+) Get burst status
- (+) Get current push-pull status
- (+) Get idle push-pull status
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the HRTIM HAL state
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval HAL state
- */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
-{
- /* Return ADC state */
- return hhrtim->State;
-}
-
-/**
- * @brief Returns actual value of the capture register of the designated capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval Captured value
- */
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- uint32_t captured_value = 0;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- /* Read captured value */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
- }
- break;
- }
-
- return captured_value;
-}
-
-/**
- * @brief Returns actual level (active or inactive) of the designated output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output level
- * @note Returned output level is taken before the output stage (chopper,
- * polarity).
- */
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- }
-
- return output_level;
-}
-
-/**
- * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output state
- */
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t output_bit = 0;
- uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Set output state according to output control status and output disable status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- {
- output_bit = HRTIM_OENR_TA1OEN;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- {
- output_bit = HRTIM_OENR_TA2OEN;
- }
- break;
- case HRTIM_OUTPUT_TB1:
- {
- output_bit = HRTIM_OENR_TB1OEN;
- }
- break;
- case HRTIM_OUTPUT_TB2:
- {
- output_bit = HRTIM_OENR_TB2OEN;
- }
- break;
- case HRTIM_OUTPUT_TC1:
- {
- output_bit = HRTIM_OENR_TC1OEN;
- }
- break;
- case HRTIM_OUTPUT_TC2:
- {
- output_bit = HRTIM_OENR_TC2OEN;
- }
- break;
- case HRTIM_OUTPUT_TD1:
- {
- output_bit = HRTIM_OENR_TD1OEN;
- }
- break;
- case HRTIM_OUTPUT_TD2:
- {
- output_bit = HRTIM_OENR_TD2OEN;
- }
- break;
- case HRTIM_OUTPUT_TE1:
- {
- output_bit = HRTIM_OENR_TE1OEN;
- }
- break;
- case HRTIM_OUTPUT_TE2:
- {
- output_bit = HRTIM_OENR_TE2OEN;
- }
- break;
- }
-
- if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
- {
- /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
- output_state = HRTIM_OUTPUTSTATE_RUN;
- }
- else
- {
- if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
- {
- /* Output is disabled: output in FAULT state */
- output_state = HRTIM_OUTPUTSTATE_FAULT;
- }
- else
- {
- /* Output is disabled: output in IDLE state */
- output_state = HRTIM_OUTPUTSTATE_IDLE;
- }
- }
-
- return(output_state);
-}
-
-/**
- * @brief Returns the level (active or inactive) of the designated output
- * when the delayed protection was triggered.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
- * @retval Delayed protection status
- */
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the delayed protection status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
- {
- /* Output 1 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 1 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
- {
- /* Output 2 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 2 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- }
-
- return delayed_protection_status;
-}
-
-/**
- * @brief Returns the actual status (active or inactive) of the burst mode controller
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval Burst mode controller status
- */
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
-{
- uint32_t burst_mode_status;
-
- /* Read burst mode status */
- burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
-
- return burst_mode_status;
-}
-
-/**
- * @brief Indicates on which output the signal is currently active (when the
- * push pull mode is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval Burst mode controller status
- */
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- uint32_t current_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
-
- return current_pushpull_status;
-}
-
-
-/**
- * @brief Indicates on which output the signal was applied, in push-pull mode,
- balanced fault mode or delayed idle mode, when the protection was triggered.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval Idle Push Pull Status
- */
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- uint32_t idle_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
-
- return idle_pushpull_status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
- * @brief Functions called when HRTIM generates an interrupt
- * 7 interrupts can be generated by the master timer:
- * - Master timer registers update
- * - Synchronization event received
- * - Master timer repetition event
- * - Master Compare 1 to 4 event
- * 14 interrupts can be generated by each timing unit:
- * - Delayed protection triggered
- * - Counter reset or roll-over event
- * - Output 1 and output 2 reset (transition active to inactive)
- * - Output 1 and output 2 set (transition inactive to active)
- * - Capture 1 and 2 events
- * - Timing unit registers update
- * - Repetition event
- * - Compare 1 to 4 event
- * 8 global interrupts are generated for the whole HRTIM:
- * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
- * - Burst mode period completed
- *
-@verbatim
- ===============================================================================
- ##### HRTIM interrupts handling #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the HRTIM
- interrupts:
- (+) HRTIM interrupt handler
- (+) Callback function called when Fault1 interrupt occurs
- (+) Callback function called when Fault2 interrupt occurs
- (+) Callback function called when Fault3 interrupt occurs
- (+) Callback function called when Fault4 interrupt occurs
- (+) Callback function called when Fault5 interrupt occurs
- (+) Callback function called when system Fault interrupt occurs
- (+) Callback function called when burst mode period interrupt occurs
- (+) Callback function called when synchronization input interrupt occurs
- (+) Callback function called when a timer register update interrupt occurs
- (+) Callback function called when a timer repetition interrupt occurs
- (+) Callback function called when a compare 1 match interrupt occurs
- (+) Callback function called when a compare 2 match interrupt occurs
- (+) Callback function called when a compare 3 match interrupt occurs
- (+) Callback function called when a compare 4 match interrupt occurs
- (+) Callback function called when a capture 1 interrupt occurs
- (+) Callback function called when a capture 2 interrupt occurs
- (+) Callback function called when a delayed protection interrupt occurs
- (+) Callback function called when a timer counter reset interrupt occurs
- (+) Callback function called when a timer output 1 set interrupt occurs
- (+) Callback function called when a timer output 1 reset interrupt occurs
- (+) Callback function called when a timer output 2 set interrupt occurs
- (+) Callback function called when a timer output 2 reset interrupt occurs
- (+) Callback function called when a timer output 2 reset interrupt occurs
- (+) Callback function called upon completion of a burst DMA transfer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles HRTIM interrupt request.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be any value of @ref HRTIM_Timer_Index
- * @retval None
- */
-void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* HRTIM interrupts handling */
- if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
- {
- HRTIM_HRTIM_ISR(hhrtim);
- }
- else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Master related interrupts handling */
- HRTIM_Master_ISR(hhrtim);
- }
- else
- {
- /* Timing unit related interrupts handling */
- HRTIM_Timer_ISR(hhrtim, TimerIdx);
- }
-
-}
-
-/**
- * @brief Callback function invoked when a fault 1 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle * @retval None
- * @retval None
- */
-__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault1Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 2 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault2Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 3 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault3Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 4 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault4Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 5 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault5Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a system fault interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the end of the burst mode period is reached
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a synchronization input event is received
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when timer registers are updated
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when timer repetition period has elapsed
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 1 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 2 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- */
-__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 3 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 4 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x capture 1 event occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x capture 2 event occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the delayed idle or balanced idle mode is
- * entered
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x counter reset/roll-over
- * event occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 1 is set
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 1 is reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 2 is set
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 2 is reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a DMA burst transfer is completed
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a DMA error occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_ErrorCallback could be implenetd in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
- * @{
- */
-
-/**
- * @brief Configures the master timer time base
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pTimeBaseCfg: pointer to the time base configuration structure
- * @retval None
- */
-static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- uint32_t hrtim_mcr;
-
- /* Configure master timer */
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the prescaler ratio */
- hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
- hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
-
- /* Set the operating mode */
- hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
- hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
- hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) time base
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param pTimeBaseCfg: pointer to the time base configuration structure
- * @retval None
- */
-static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx ,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- uint32_t hrtim_timcr;
-
- /* Configure master timing unit */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
-
- /* Set the prescaler ratio */
- hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
- hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
-
- /* Set the operating mode */
- hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
- hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
- hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
-}
-
-/**
- * @brief Configures the master timer in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pTimerCfg: pointer to the timer configuration data structure
- * @retval None
- */
-static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- uint32_t hrtim_mcr;
- uint32_t hrtim_bmcr;
-
- /* Configure master timer */
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Enable/Disable the half mode */
- hrtim_mcr &= ~(HRTIM_MCR_HALF);
- hrtim_mcr |= pTimerCfg->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
- hrtim_mcr |= pTimerCfg->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
- hrtim_mcr |= pTimerCfg->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
- hrtim_mcr |= pTimerCfg->DACSynchro;
-
- /* Enable/Disable preload meachanism for timer registers */
- hrtim_mcr &= ~(HRTIM_MCR_PREEN);
- hrtim_mcr |= pTimerCfg->PreloadEnable;
-
- /* Master timer registers update handling */
- hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
- hrtim_mcr |= (pTimerCfg->UpdateGating << 2);
-
- /* Enable/Disable registers update on repetition */
- hrtim_mcr &= ~(HRTIM_MCR_MREPU);
- hrtim_mcr |= pTimerCfg->RepetitionUpdate;
-
- /* Set the timer burst mode */
- hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
- hrtim_bmcr |= pTimerCfg->BurstMode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param pTimerCfg: pointer to the timer configuration data structure
- * @retval None
- */
-static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- uint32_t hrtim_timcr;
- uint32_t hrtim_timfltr;
- uint32_t hrtim_timoutr;
- uint32_t hrtim_timrstr;
- uint32_t hrtim_bmcr;
-
- /* UPDGAT bitfield must be reset before programming a new value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
-
- /* Configure timing unit (Timer A to Timer E) */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
- hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
- hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
- hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Enable/Disable the half mode */
- hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
- hrtim_timcr |= pTimerCfg->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
- hrtim_timcr |= pTimerCfg->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
- hrtim_timcr |= pTimerCfg->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
- hrtim_timcr |= pTimerCfg->DACSynchro;
-
- /* Enable/Disable preload meachanism for timer registers */
- hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
- hrtim_timcr |= pTimerCfg->PreloadEnable;
-
- /* Timing unit registers update handling */
- hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
- hrtim_timcr |= pTimerCfg->UpdateGating;
-
- /* Enable/Disable registers update on repetition */
- hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
- if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
- {
- hrtim_timcr |= HRTIM_TIMCR_TREPU;
- }
-
- /* Set the push-pull mode */
- hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
- hrtim_timcr |= pTimerCfg->PushPull;
-
- /* Enable/Disable registers update on timer counter reset */
- hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
- hrtim_timcr |= pTimerCfg->ResetUpdate;
-
- /* Set the timer update trigger */
- hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
- hrtim_timcr |= pTimerCfg->UpdateTrigger;
-
-
- /* Enable/Disable the fault channel at timer level */
- hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
- hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
-
- /* Lock/Unlock fault sources at timer level */
- hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
- hrtim_timfltr |= pTimerCfg->FaultLock;
-
- /* The deadtime cannot be used simultaneously with the push-pull mode */
- if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
- {
- /* Enable/Disable dead time insertion at timer level */
- hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
- hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
- }
-
- /* Enable/Disable delayed protection at timer level
- Delayed Idle is available whatever the timer operating mode (regular, push-pull)
- Balanced Idle is only available in push-pull mode
- */
- if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
- && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
- || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
- {
- hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
- hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
- }
-
- /* Set the timer counter reset trigger */
- hrtim_timrstr = pTimerCfg->ResetTrigger;
-
- /* Set the timer burst mode */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 1);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 2);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 3);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 4);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
- }
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-}
-
-/**
- * @brief Configures a compare unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param CompareUnit: Compare unit identifier
- * @param pCompareCfg: pointer to the compare unit configuration data structure
- * @retval None
- */
-static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * pCompareCfg)
-{
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure the compare unit of the master timer */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
- }
- break;
- }
- }
- else
- {
- /* Configure the compare unit of the timing unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
- }
- break;
- }
- }
-}
-
-/**
- * @brief Configures a capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param CaptureUnit: Capture unit identifier
- * @param Event: Event reference
- * @retval None
- */
-static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event)
-{
- uint32_t CaptureTrigger = 0xFFFFFFFFU;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
- }
- break;
- }
-
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
- }
- break;
- }
-}
-
-/**
- * @brief Configures the output of a timing unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param Output: timing unit output identifier
- * @param pOutputCfg: pointer to the output configuration data structure
- * @retval None
- */
-static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- uint32_t hrtim_outr;
- uint32_t hrtim_dtr;
-
- uint32_t shift = 0xFFFFFFFFU;
-
- hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
- hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
-
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Set the output set/reset crossbar */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
-
- shift = 0;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Set the output set/reset crossbar */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
-
- shift = 16;
- }
- break;
- }
-
- /* Clear output config */
- hrtim_outr &= ~((HRTIM_OUTR_POL1 |
- HRTIM_OUTR_IDLM1 |
- HRTIM_OUTR_IDLES1|
- HRTIM_OUTR_FAULT1|
- HRTIM_OUTR_CHP1 |
- HRTIM_OUTR_DIDL1) << shift);
-
- /* Set the polarity */
- hrtim_outr |= (pOutputCfg->Polarity << shift);
-
- /* Set the IDLE mode */
- hrtim_outr |= (pOutputCfg->IdleMode << shift);
-
- /* Set the IDLE state */
- hrtim_outr |= (pOutputCfg->IdleLevel << shift);
-
- /* Set the FAULT state */
- hrtim_outr |= (pOutputCfg->FaultLevel << shift);
-
- /* Set the chopper mode */
- hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
-
- /* Set the burst mode entry mode : deadtime insertion when entering the idle
- state during a burst mode operation is allowed only under the following
- conditions:
- - the outputs is active during the burst mode (IDLES=1)
- - positive deadtimes (SDTR/SDTF set to 0)
- */
- if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
- ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
- ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
- {
- hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
- }
-
- /* Update HRTIM register */
- hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
-}
-
-/**
- * @brief Configures an external event channel
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Event: Event channel identifier
- * @param pEventCfg: pointer to the event channel configuration data structure
- * @retval None
- */
-static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef *pEventCfg)
-{
- uint32_t hrtim_eecr1;
- uint32_t hrtim_eecr2;
- uint32_t hrtim_eecr3;
-
- /* Configure external event channel */
- hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
- hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
- hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
- hrtim_eecr1 |= pEventCfg->Source;
- hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
- hrtim_eecr1 |= pEventCfg->Sensitivity;
- /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE1FAST bit) */
- hrtim_eecr1 |= pEventCfg->FastMode;
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 6);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
- /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE2FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 6);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 12);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
- /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE3FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 12);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 18);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
- /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE4FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 18);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 24);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
- /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE5FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 24);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
- hrtim_eecr2 |= pEventCfg->Source;
- hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
- hrtim_eecr2 |= pEventCfg->Sensitivity;
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
- hrtim_eecr3 |= pEventCfg->Filter;
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 6);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
- hrtim_eecr3 |= (pEventCfg->Filter << 6);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 12);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
- hrtim_eecr3 |= (pEventCfg->Filter << 12);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 18);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
- hrtim_eecr3 |= (pEventCfg->Filter << 18);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 24);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
- hrtim_eecr3 |= (pEventCfg->Filter << 24);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the timer counter reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param Event: Event channel identifier
- * @retval None
- */
-static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event)
-{
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
- }
- break;
- }
-}
-
-/**
- * @brief Returns the interrupt to enable or disable according to the
- * OC mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Interrupt to enable or disable
- */
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t hrtim_set;
- uint32_t hrtim_reset;
- uint32_t interrupt = 0;
-
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Retreives actual OC mode and set interrupt accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- interrupt = HRTIM_TIM_IT_CMP1;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- interrupt = HRTIM_TIM_IT_SET1;
- }
- else if ((hrtim_set == 0) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- interrupt = HRTIM_TIM_IT_RST1;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Retreives actual OC mode and set interrupt accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- interrupt = HRTIM_TIM_IT_CMP2;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- interrupt = HRTIM_TIM_IT_SET2;
- }
- else if ((hrtim_set == 0) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- interrupt = HRTIM_TIM_IT_RST2;
- }
- }
- break;
- }
-
- return interrupt;
-}
-
-/**
- * @brief Returns the DMA request to enable or disable according to the
- * OC mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval DMA request to enable or disable
- */
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t hrtim_set;
- uint32_t hrtim_reset;
- uint32_t dma_request = 0;
-
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Retreives actual OC mode and set dma_request accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- dma_request = HRTIM_TIM_DMA_CMP1;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- dma_request = HRTIM_TIM_DMA_SET1;
- }
- else if ((hrtim_set == 0) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- dma_request = HRTIM_TIM_DMA_RST1;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Retreives actual OC mode and set dma_request accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- dma_request = HRTIM_TIM_DMA_CMP2;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- dma_request = HRTIM_TIM_DMA_SET2;
- }
- else if ((hrtim_set == 0) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- dma_request = HRTIM_TIM_DMA_RST2;
- }
- }
- break;
- }
-
- return dma_request;
-}
-
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
-
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- hdma = hhrtim->hdmaMaster;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hdma = hhrtim->hdmaTimerA;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hdma = hhrtim->hdmaTimerB;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hdma = hhrtim->hdmaTimerC;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hdma = hhrtim->hdmaTimerD;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hdma = hhrtim->hdmaTimerE;
- }
- break;
- }
-
- return hdma;
-}
-
-static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
-{
- uint32_t timed_idx = 0xFFFFFFFF;
-
- if (hdma->Init.Request == DMA_REQUEST_HRTIM_MASTER)
- {
- timed_idx = HRTIM_TIMERINDEX_MASTER;
- }
- else if (hdma->Init.Request == DMA_REQUEST_HRTIM_TIMER_A)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_A;
- }
- else if (hdma->Init.Request == DMA_REQUEST_HRTIM_TIMER_B)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_B;
- }
- else if (hdma->Init.Request == DMA_REQUEST_HRTIM_TIMER_C)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_C;
- }
- else if (hdma->Init.Request == DMA_REQUEST_HRTIM_TIMER_D)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_D;
- }
- else if (hdma->Init.Request == DMA_REQUEST_HRTIM_TIMER_E)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_E;
- }
-
- return timed_idx;
-}
-
-/**
- * @brief Forces an immediate transfer from the preload to the active
- * registers.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @retval None
- */
-static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
- }
- break;
- }
-}
-
-
-/**
- * @brief HRTIM interrupts service routine
- * @param hhrtim: pointer to HAL HRTIM handle
- * @retval None
- */
-static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Fault 1 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
-
- /* Invoke Fault 1 event callback */
- HAL_HRTIM_Fault1Callback(hhrtim);
- }
- }
-
- /* Fault 2 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
-
- /* Invoke Fault 2 event callback */
- HAL_HRTIM_Fault2Callback(hhrtim);
- }
- }
-
- /* Fault 3 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
-
- /* Invoke Fault 3 event callback */
- HAL_HRTIM_Fault3Callback(hhrtim);
- }
- }
-
- /* Fault 4 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
-
- /* Invoke Fault 4 event callback */
- HAL_HRTIM_Fault4Callback(hhrtim);
- }
- }
-
- /* Fault 5 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
-
- /* Invoke Fault 5 event callback */
- HAL_HRTIM_Fault5Callback(hhrtim);
- }
- }
-
- /* System fault event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
-
- /* Invoke System fault event callback */
- HAL_HRTIM_SystemFaultCallback(hhrtim);
- }
- }
-}
-
-/**
-* @brief Master timer interrupts service routine
-* @param hhrtim: pointer to HAL HRTIM handle
-* @retval None
-*/
-static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Burst mode period event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
-
- /* Invoke Burst mode period event callback */
- HAL_HRTIM_BurstModePeriodCallback(hhrtim);
- }
- }
-
- /* Master timer compare 1 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
-
- /* Invoke compare 1 event callback */
- HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 2 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
-
- /* Invoke compare 2 event callback */
- HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 3 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
-
- /* Invoke compare 3 event callback */
- HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 4 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
-
- /* Invoke compare 4 event callback */
- HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer repetition event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
-
- /* Invoke repetition event callback */
- HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Synchronization input event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
-
- /* Invoke synchronization event callback */
- HAL_HRTIM_SynchronizationEventCallback(hhrtim);
- }
- }
-
- /* Master timer registers update event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
-
- /* Invoke registers update event callback */
- HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-}
-
-/**
- * @brief Timer interrupts service routine
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
-*/
-static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Timer compare 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
-
- /* Invoke compare 1 event callback */
- HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
-
- /* Invoke compare 2 event callback */
- HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 3 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
-
- /* Invoke compare 3 event callback */
- HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 4 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
-
- /* Invoke compare 4 event callback */
- HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer repetition event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
-
- /* Invoke repetition event callback */
- HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer registers update event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
-
- /* Invoke registers update event callback */
- HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer capture 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
-
- /* Invoke capture 1 event callback */
- HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer capture 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
-
- /* Invoke capture 2 event callback */
- HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 1 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
-
- /* Invoke ouput 1 set event callback */
- HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 1 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
-
- /* Invoke ouput 1 reset event callback */
- HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 2 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
-
- /* Invoke ouput 2 set event callback */
- HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 2 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
-
- /* Invoke ouput 2 reset event callback */
- HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
-
- /* Invoke timer reset callback */
- HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Delayed protection event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
-
- /* Invoke delayed protection callback */
- HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
- }
- }
-}
-
-/**
- * @brief DMA callback invoked upon master timer related DMA request completion
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
- {
- HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
- {
- HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
- {
- HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
- {
- HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
- {
- HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
- {
- HAL_HRTIM_SynchronizationEventCallback(hrtim);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
- {
- HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
-}
-
-/**
- * @brief DMA callback invoked upon timer A..E related DMA request completion
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
-{
- uint8_t timer_idx;
-
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- timer_idx = GetTimerIdxFromDMAHandle(hdma);
-
- if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
- {
- HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
- {
- HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
- {
- HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
- {
- HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
- {
- HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
- {
- HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
- {
- HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
- {
- HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
- {
- HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
- {
- HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
- {
- HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
- {
- HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
- {
- HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
- {
- HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
- }
-}
-
-/**
-* @brief DMA error callback
-* @param hdma: pointer to DMA handle.
-* @retval None
-*/
-static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_HRTIM_ErrorCallback(hrtim);
-}
-
-/**
- * @brief DMA callback invoked upon burst DMA transfer completion
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
deleted file mode 100644
index 5f1c598..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_hsem.c
- * @author MCD Application Team
- * @brief HSEM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the semaphore peripheral:
- * + Semaphore Take function (2-Step Procedure) , non blocking
- * + Semaphore FastTake function (1-Step Procedure) , non blocking
- * + Semaphore Status check
- * + Semaphore Clear Key Set and Get
- * + Release and release all functions
- * + Semaphore notification enabling and disabling and callnack functions
- * + IRQ handler management
- *
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
- (++) the semaphore ID from 0 to 31
- (++) the process ID from 0 to 255
- (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
- (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
- (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
- (++) the semaphore ID from 0_ID to 31
- (++) It returns 1 if the given semaphore is taken otherwise (Free) zero.
- (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
- (++) the semaphore ID from 0 to 31
- (++) the process ID from 0 to 255:
- (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
- may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
- semaphore remains taken (locked).
-
- (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
- This function takes as parameters :
- (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
- HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
- (++) the Master ID:
- (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
- to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
- Key or the MasterID doesn't match, semaphores remains taken (locked).
-
- (#)Semaphores Release all key functions:
- (++) HAL_HSEM_SetClearKey() to set semaphore release all Key
- (++) HAL_HSEM_GetClearKey() to get release all Key
- (#)Semaphores notification functions :
- (++) HAL_HSEM_ActivateNotification to activate a notification callback on
- a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
- the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
- semaphores (bitfield).
-
- (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
- (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
- Used by the notification functions
- *** HSEM HAL driver macros list ***
- =============================================
- [..] Below the list of most used macros in HSEM HAL driver.
-
- (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
- [..] Example of use :
- [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
- [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
- (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
- (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
- (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
- (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
- (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HSEM HSEM
- * @brief HSEM HAL module driver
- * @{
- */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
- * @{
- */
-
-/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
- * @brief HSEM Take and Release functions
- *
-@verbatim
- ==============================================================================
- ##### HSEM Take and Release functions #####
- ==============================================================================
-[..] This section provides functions allowing to:
- (+) Take a semaphore with 2 Step method
- (+) Fast Take a semaphore with 1 Step method
- (+) Check semaphore state Taken or not
- (+) Release a semaphore
- (+) Release all semaphore at once
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Take a semaphore in 2 Step mode.
- * @param SemID: semaphore ID from 0 to 31
- * @param ProcessID: Process ID from 0 to 255
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
-{
- /* Check the parameters */
- assert_param(IS_HSEM_SEMID(SemID));
- assert_param(IS_HSEM_PROCESSID(ProcessID));
-
- /* First step write R register with MasterID, processID and take bit=1*/
- HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
-
- /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
- if(HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
- {
- /*take success when MasterID and ProcessID match and take bit set*/
- return HAL_OK;
- }
-
- /* Semaphore take fails*/
- return HAL_ERROR;
-}
-
-/**
- * @brief Fast Take a semaphore with 1 Step mode.
- * @param SemID: semaphore ID from 0 to 31
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
-{
- /* Check the parameters */
- assert_param(IS_HSEM_SEMID(SemID));
-
- /* Read the RLR register to take the semaphore */
- if(HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
- {
- /*take success when MasterID match and take bit set*/
- return HAL_OK;
- }
-
- /* Semaphore take fails */
- return HAL_ERROR;
-}
-
-/**
- * @brief Check semaphore state Taken or not.
- * @param SemID: semaphore ID
- * @retval HAL HSEM state
- */
-uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
-{
- return ((HSEM->R[SemID] & HSEM_R_LOCK) != 0U);
-}
-
-
-/**
- * @brief Release a semaphore.
- * @param SemID: semaphore ID from 0 to 31
- * @param ProcessID: Process ID from 0 to 255
- * @retval None
-*/
-void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
-{
- /* Check the parameters */
- assert_param(IS_HSEM_SEMID(SemID));
- assert_param(IS_HSEM_PROCESSID(ProcessID));
-
- /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
- HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
-
-}
-
-/**
- * @brief Release All semaphore used by a given Master .
- * @param Key: Semaphore Key , value from 0 to 0xFFFF
- * @param MasterID: MasterID of the CPU that is using semaphores to be Released
- * @retval None
-*/
-void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t MasterID)
-{
- assert_param(IS_HSEM_KEY(Key));
- assert_param(IS_HSEM_MASTERID(MasterID));
-
- HSEM->CR = (((Key << POSITION_VAL(HSEM_KEYR_KEY)) & HSEM_CR_KEY ) | ((MasterID << POSITION_VAL(HSEM_CR_MASTERID)) & HSEM_CR_MASTERID));
-}
-
-/**
- * @}
- */
-
-/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
- * @brief HSEM Set and Get Key functions.
- *
-@verbatim
- ==============================================================================
- ##### HSEM Set and Get Key functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Set semaphore Key
- (+) Get semaphore Key
-@endverbatim
-
- * @{
- */
-
-/**
- * @brief Set semaphore Key .
- * @param Key: Semaphore Key , value from 0 to 0xFFFF
- * @retval None
-*/
-void HAL_HSEM_SetClearKey(uint32_t Key)
-{
- assert_param(IS_HSEM_KEY(Key));
-
- MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << POSITION_VAL(HSEM_KEYR_KEY)));
-
-}
-
-/**
- * @brief Get semaphore Key .
- * @retval Semaphore Key , value from 0 to 0xFFFF
-*/
-uint32_t HAL_HSEM_GetClearKey(void)
-{
- return (HSEM->KEYR >> POSITION_VAL(HSEM_KEYR_KEY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
- * @brief HSEM Notification functions.
- *
-@verbatim
- ==============================================================================
- ##### HSEM IRQ handler management and Notification functions #####
- ==============================================================================
-[..] This section provides HSEM IRQ handler and Notification function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Activate Semaphore release Notification for a given Semaphores Mask .
- * @param SemMask: Mask of Released semaphores
- * @retval Semaphore Key
-*/
-void HAL_HSEM_ActivateNotification(uint32_t SemMask)
-{
- /*Activate interrupt for CM7 Master */
- HSEM->IER |= SemMask;
-}
-
-/**
- * @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
- * @param SemMask: Mask of Released semaphores
- * @retval Semaphore Key
-*/
-void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
-{
-
- /*Deactivate interrupt for CM7 Master */
- HSEM->IER &= ~SemMask;
-}
-
-/**
- * @brief This function handles HSEM interrupt request.
- * @retval None
-*/
-void HAL_HSEM_IRQHandler(void)
-{
- uint32_t statusreg = 0U;
-
- /* Get the list of masked freed semaphores*/
- statusreg = HSEM->MISR;
-
- /*Disable Interrupts*/
- HSEM->IER &= ~((uint32_t)statusreg);
-
- /*Clear Flags*/
- HSEM->ICR |= ((uint32_t)statusreg);
-
-
- /* Call FreeCallback */
- HAL_HSEM_FreeCallback(statusreg);
-}
-
-/**
- * @brief Semaphore Released Callback.
- * @param SemMask: Mask of Released semaphores
- * @retval None
- */
-__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(SemMask);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HSEM_FreeCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_HSEM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
deleted file mode 100644
index b734dc8..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
+++ /dev/null
@@ -1,4837 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2c.c
- * @author MCD Application Team
- * @brief I2C HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Inter Integrated Circuit (I2C) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The I2C HAL driver can be used as follows:
-
- (#) Declare a I2C_HandleTypeDef handle structure, for example:
- I2C_HandleTypeDef hi2c;
-
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
- (##) Enable the I2Cx interface clock
- (##) I2C pins configuration
- (+++) Enable the clock for the I2C GPIOs
- (+++) Configure I2C pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the I2Cx interrupt priority
- (+++) Enable the NVIC I2C IRQ Channel
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
- (+++) Enable the DMAx interface clock using
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx stream
- (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx stream
-
- (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
- Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
- (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
- *** Polling mode IO MEM operation ***
- =====================================
- [..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
-
- *** Interrupt mode IO sequential operation ***
- ===================================
- [..]
- (@) These interfaces allow to manage a sequential transfer with a repeated start condition
- when a direction change during transfer
- [..]
- (+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
- (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition
- (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
- (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and without a final stop condition in both cases
- (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and with a final stop condition in both cases
-
- (+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** Interrupt mode IO MEM operation ***
- =======================================
- [..]
- (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** DMA mode IO MEM operation ***
- =================================
- [..]
- (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
- *** I2C HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in I2C HAL driver.
-
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
- [..]
- (@) You can refer to the I2C HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2C I2C
- * @brief I2C HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
- * @{
- */
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */
-#define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE 255U
-#define SlaveAddr_SHIFT 7U
-#define SlaveAddr_MSK 0x06U
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT ((uint32_t)0x00000001U)
-#define I2C_XFER_RX_IT ((uint32_t)0x00000002U)
-#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U)
-
-#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011U)
-#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012U)
-#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (((__HANDLE__)->Instance == I2C4)? \
- ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \
- ((uint32_t)(((BDMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) : \
- ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR))))
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-/* Private functions to handle IT transfer */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
-
-/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-/* Private functions to flush TXDR register */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-
-/* Private functions to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- deinitialize the I2Cx peripheral:
-
- (+) User must Implement HAL_I2C_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2C_Init() to configure the selected device with
- the selected configuration:
- (++) Clock Timing
- (++) Own Address 1
- (++) Addressing mode (Master, Slave)
- (++) Dual Addressing mode
- (++) Own Address 2
- (++) Own Address 2 Mask
- (++) General call mode
- (++) Nostretch mode
-
- (+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and initialize the associated handle.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if(hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
- assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
- assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
- assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
- assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
- assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
- if(hi2c->State == HAL_I2C_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2c->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2C_MspInit(hi2c);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
- /* Configure I2Cx: Frequency range */
- hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Disable Own Address1 before set the Own Address1 configuration */
- hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- /* Configure I2Cx: Own Address1 and ack own address1 mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
-
- /*---------------------------- I2Cx CR2 Configuration ----------------------*/
- /* Configure I2Cx: Addressing Master mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
- }
- /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
- hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
- /* Disable Own Address2 before set the Own Address2 configuration */
- hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
-
- /* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
-
- /*---------------------------- I2Cx CR1 Configuration ----------------------*/
- /* Configure I2Cx: Generalcall and NoStretch mode */
- hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
- /* Enable the selected I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the I2C peripheral.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if(hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the I2C Peripheral Clock */
- __HAL_I2C_DISABLE(hi2c);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_I2C_MspDeInit(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the I2C MSP.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the I2C MSP.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2C data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2C_Master_Transmit()
- (++) HAL_I2C_Master_Receive()
- (++) HAL_I2C_Slave_Transmit()
- (++) HAL_I2C_Slave_Receive()
- (++) HAL_I2C_Mem_Write()
- (++) HAL_I2C_Mem_Read()
- (++) HAL_I2C_IsDeviceReady()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2C_Master_Transmit_IT()
- (++) HAL_I2C_Master_Receive_IT()
- (++) HAL_I2C_Slave_Transmit_IT()
- (++) HAL_I2C_Slave_Receive_IT()
- (++) HAL_I2C_Mem_Write_IT()
- (++) HAL_I2C_Mem_Read_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2C_Master_Transmit_DMA()
- (++) HAL_I2C_Master_Receive_DMA()
- (++) HAL_I2C_Slave_Transmit_DMA()
- (++) HAL_I2C_Slave_Receive_DMA()
- (++) HAL_I2C_Mem_Write_DMA()
- (++) HAL_I2C_Mem_Read_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
- (++) HAL_I2C_MasterTxCpltCallback()
- (++) HAL_I2C_MasterRxCpltCallback()
- (++) HAL_I2C_SlaveTxCpltCallback()
- (++) HAL_I2C_SlaveRxCpltCallback()
- (++) HAL_I2C_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
- }
-
- while(hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
- {
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
-
- while(hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
- /* If 10bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
- }
-
- /* Wait until DIR flag is set Transmitter mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- while(hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
-
- /* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
- /* Wait until DIR flag is reset Receiver mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- while(hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferCount--;
- }
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferCount--;
- }
-
- /* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
-
- do
- {
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
- {
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
-
- }while(hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
-
- do
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }while(hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Checks if target device is ready for communication.
- * @note This function is used with Memory devices
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param Trials: Number of trials
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- __IO uint32_t I2C_Trials = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- do
- {
- /* Generate Start */
- hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set or a NACK flag is set*/
- tickstart = HAL_GetTick();
- while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Device is ready */
- hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check if the NACKF flag has not been set */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
- {
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Device is ready */
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Clear STOP Flag, auto generated with autoend*/
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials++ == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
- }while(I2C_Trials < Trials);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If size > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
-
- /* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = I2C_GENERATE_START_READ;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
-
- /* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @arg I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave TX state to RX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Enable the Address Match interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
- /* Disable Address listen mode only if a transfer is not ongoing */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Disable the Address Match interrupt */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master/host I2C process communication with Interrupt.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Set State at HAL_I2C_STATE_ABORT */
- hi2c->State = HAL_I2C_STATE_ABORT;
-
- /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
- /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- return HAL_OK;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief This function handles I2C event interrupt request.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- /* Get current IT Flags and IT sources value */
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
- /* I2C events treatment -------------------------------------*/
- if(hi2c->XferISR != NULL)
- {
- hi2c->XferISR(hi2c, itflags, itsources);
- }
-}
-
-/**
- * @brief This function handles I2C error interrupt request.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
- /* I2C Bus error interrupt occurred ------------------------------------*/
- if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
- }
-
- /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
- }
-
- /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
- }
-
- /* Call the Error Callback in case of Error detected */
- if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
- {
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @arg I2C_XferOptions_definition
- * @param AddrMatchCode: Address Match Code
- * @retval None
- */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AddrCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ListenCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Tx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Rx Transfer completed callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C error callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C abort callback.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State, Mode and Error functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2C handle state.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL state
- */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
- /* Return I2C handle state */
- return hi2c->State;
-}
-
-/**
- * @brief Returns the I2C Master, Slave, Memory or no mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL mode
- */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->Mode;
-}
-
-/**
-* @brief Return the I2C error code.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags: Interrupt flags to handle.
- * @param ITSources: Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- uint16_t devaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- /* No need to generate STOP, it is automatically done */
- /* Error callback will be send during stop flag treatment */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
- else
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- }
- else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- if(hi2c->XferCount == 0U)
- {
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate a stop condition in case of no transfer option */
- if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
- }
- }
- }
- else
- {
- /* Wrong size Status regarding TC flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
-
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags: Interrupt flags to handle.
- * @param ITSources: Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if(hi2c->XferCount == 0U)
- {
- if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
- }
- else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- else
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
- {
- if(hi2c->XferCount > 0U)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
-
- if((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
- {
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- }
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
- {
- I2C_ITAddrCplt(hi2c, ITFlags);
- }
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
- /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hi2c->XferCount > 0U)
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
- else
- {
- if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
- {
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- }
- }
-
- /* Check if STOPF is set */
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags: Interrupt flags to handle.
- * @param ITSources: Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- uint16_t devaddress = 0U;
- uint32_t xfermode = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* No need to generate STOP, it is automatically done */
- /* But enable STOP interrupt, to treat it */
- /* Error callback will be send during stop flag treatment */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- /* Disable TC interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
- if(hi2c->XferCount != 0U)
- {
- /* Recover Slave address */
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- /* Prepare the new XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Set the new XferSize in Nbytes register */
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Enable DMA Request */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags: Interrupt flags to handle.
- * @param ITSources: Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0 */
- /* So clear Flag NACKF only */
- if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param Timeout: Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
-return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
- * @param MemAddress: Internal memory address
- * @param MemAddSize: Size of internal memory address
- * @param Timeout: Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TC flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief I2C Address complete process callback.
- * @param hi2c: I2C handle.
- * @param ITFlags: Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- uint8_t transferdirection = 0U;
- uint16_t slaveaddrcode = 0U;
- uint16_t ownadd1code = 0U;
- uint16_t ownadd2code = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ITFlags);
-
- /* In case of Listen state, need to inform upper layer of address match code event */
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- transferdirection = I2C_GET_DIR(hi2c);
- slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
- ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
- ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
-
- /* If 10bits addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
- {
- slaveaddrcode = ownadd1code;
- hi2c->AddrEventCount++;
- if(hi2c->AddrEventCount == 2U)
- {
- /* Reset Address Event counter */
- hi2c->AddrEventCount = 0U;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- else
- {
- slaveaddrcode = ownadd2code;
-
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- /* else 7 bits addressing mode is selected */
- else
- {
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- /* Else clear address flag only */
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
-}
-
-/**
- * @brief I2C Master sequential complete process.
- * @param hi2c: I2C handle.
- * @retval None
- */
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* No Generate Stop, to permit restart mode */
- /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Slave sequential complete process.
- * @param hi2c: I2C handle.
- * @retval None
- */
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
-
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Master complete process.
- * @param hi2c: I2C handle.
- * @param ITFlags: Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = NULL;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- if((ITFlags & I2C_FLAG_AF) != RESET)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set acknowledge error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
- }
-}
-
-/**
- * @brief I2C Slave complete process.
- * @param hi2c: I2C handle.
- * @param ITFlags: Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
-
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* If a DMA is ongoing, Update handle size context */
- if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
- {
- hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
- }
-
- /* All data are not transferred, so set error code accordingly */
- if(hi2c->XferCount != 0U)
- {
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- /* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
- if((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
- }
- }
- else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
- }
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Slave Rx Complete callback */
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Slave Tx Complete callback */
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Listen complete process.
- * @param hi2c: I2C handle.
- * @param ITFlags: Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Reset handle parameters */
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
- if((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
- /* Disable all Interrupts*/
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
-}
-
-/**
- * @brief I2C interrupts error process.
- * @param hi2c: I2C handle.
- * @param ErrorCode: Error code to handle.
- * @retval None
- */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
-{
- /* Reset handle parameters */
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferCount = 0U;
-
- /* Set new error code */
- hi2c->ErrorCode |= ErrorCode;
-
- /* Disable Interrupts */
- if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- /* Disable all interrupts, except interrupts related to LISTEN state */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* keep HAL_I2C_STATE_LISTEN if set */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = I2C_Slave_ISR_IT;
- }
- else
- {
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* If state is an abort treatment on goind, don't change state */
- /* This change will be do later */
- if(hi2c->State != HAL_I2C_STATE_ABORT)
- {
- /* Set HAL_I2C_STATE_READY */
- hi2c->State = HAL_I2C_STATE_READY;
- }
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = NULL;
- }
-
- /* Abort DMA TX transfer if any */
- if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- /* Abort DMA RX transfer if any */
- else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- else if(hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_ErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Tx data register flush process.
- * @param hi2c: I2C handle.
- * @retval None
- */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
-{
- /* If a pending TXIS flag is set */
- /* Write a dummy data in TXDR to clear it */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
- {
- hi2c->Instance->TXDR = 0x00U;
- }
-
- /* Flush TX register if not empty */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
- }
-}
-
-/**
- * @brief DMA I2C master transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
-}
-
-/**
- * @brief DMA I2C slave transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
- * @brief DMA I2C master receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
-}
-
-/**
- * @brief DMA I2C slave receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
- * @brief DMA I2C communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-}
-
-/**
- * @brief DMA I2C communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if(hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_ErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief This function handles I2C Communication Timeout.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag: Specifies the I2C flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check if a STOPF is detected */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles Acknowledge failed detection during an I2C Communication.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- /* Wait until STOP Flag is reset */
- /* AutoEnd should be initiate after AF */
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param hi2c: I2C handle.
- * @param DevAddress: Specifies the slave address to be programmed.
- * @param Size: Specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param Mode: New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_RELOAD_MODE: Enable Reload mode .
- * @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
- * @arg I2C_SOFTEND_MODE: Enable Software end mode.
- * @param Request: New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
- * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
- * @arg I2C_GENERATE_START_READ: Generate Restart for read request.
- * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
- * @retval None
- */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_TRANSFER_MODE(Mode));
- assert_param(IS_TRANSFER_REQUEST(Request));
-
- /* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
-}
-
-/**
- * @brief Manage the enabling of Interrupts.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
- {
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
- }
-
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
- }
-
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
- }
-
- /* Enable interrupts only at the end */
- /* to avoid the risk of I2C interrupt handle execution before */
- /* all interrupts requested done */
- __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
-}
-
-/**
- * @brief Manage the disabling of Interrupts.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Disable TC and TXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Disable TC and RXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Disable ADDR, NACK and STOP interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
-
- /* Disable interrupts only at the end */
- /* to avoid a breaking situation like at "t" time */
- /* all disable interrupts request are not done */
- __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
deleted file mode 100644
index 0942dce..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2c_ex.c
- * @author MCD Application Team
- * @brief I2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2C Extended peripheral:
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### I2C peripheral Extended features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the I2C interface for STM32H7XX
- devices contains the following additional features
-
- (+) Possibility to disable or enable Analog Noise Filter
- (+) Use of a configured Digital Noise Filter
- (+) Disable or enable wakeup from Stop modes
- (+) Disable or enable Fast Mode Plus
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure Noise Filter and Wake Up Feature
- (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
- (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
- (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
- (++) HAL_I2CEx_EnableWakeUp()
- (++) HAL_I2CEx_DisableWakeUp()
- (#) Configure the enable or disable of fast mode plus driving capability using the functions :
- (++) HAL_I2CEx_EnableFastModePlus()
- (++) HAL_I2CEx_DisableFastModePlus()
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2CEx I2CEx
- * @brief I2C Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure Noise Filters
- (+) Configure Wake Up Feature
- (+) Configure Fast Mode Plus
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure I2C Analog noise filter.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param AnalogFilter: New state of the Analog filter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Reset I2Cx ANOFF bit */
- hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
- /* Set analog filter bit*/
- hi2c->Instance->CR1 |= AnalogFilter;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure I2C Digital noise filter.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Get the old register value */
- tmpreg = hi2c->Instance->CR1;
-
- /* Reset I2Cx DNF bits [11:8] */
- tmpreg &= ~(I2C_CR1_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= DigitalFilter << 8U;
-
- /* Store the new register value */
- hi2c->Instance->CR1 = tmpreg;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable I2C wakeup from stop mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable I2C wakeup from stop mode.
- * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus: Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @retval None
- */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Enable fast mode plus driving capability for selected pin */
- SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
-}
-
-/**
- * @brief Disable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus: Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @retval None
- */
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Disable fast mode plus driving capability for selected pin */
- CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
deleted file mode 100644
index 8ac79cd..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
+++ /dev/null
@@ -1,1841 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_i2s.c
- * @author MCD Application Team
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Integrated Interchip Sound (I2S) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The I2S HAL driver can be used as follow:
-
- (#) Declare a I2S_HandleTypeDef handle structure.
- (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
- (##) I2S pins configuration:
- (+++) Enable the clock for the I2S GPIOs.
- (+++) Configure these I2S pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
- and HAL_I2S_Receive_IT() APIs).
- (+++) Configure the I2Sx interrupt priority.
- (+++) Enable the NVIC I2S IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
- and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Channel.
- (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Channel.
-
- (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
- using HAL_I2S_Init() function.
-
- -@- The specific I2S interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
- -@- Make sure that either:
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
-
- Three mode of operations are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
- *** I2S HAL driver macros list ***
- ===================================
- [..]
- Below the list of most used macros in I2S HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
- (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
- (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
- [..]
- (@) You can refer to the I2S HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-/** @addtogroup I2S
- * @brief I2S HAL module driver
- * @{
- */
-
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2S_Private
- * @{
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-
-static void I2S_TxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2S_TxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2S_RxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2S_RxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2S_CloseRx_ISR(I2S_HandleTypeDef *hi2s);
-static void I2S_CloseTx_ISR(I2S_HandleTypeDef *hi2s);
-
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
-
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2S_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Standard
- (++) Data Format
- (++) MCLK Output
- (++) Audio frequency
- (++) Polarity
- (++) First Bit
- (++) WS Inversion
- (++) IO Swap
- (++) Data 24Bit Alignment
- (++) Fifo Threshold
- (++) Alternate function GPIOs state
- (++) Channel length in SLAVE
-
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2S according to the specified parameters
- * in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
- uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U, i2sclk = 0U;
-
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
- assert_param(IS_I2S_MODE(hi2s->Init.Mode));
- assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
- assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
- assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
- assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
- assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
- assert_param(IS_I2S_IO_SWAP(hi2s->Init.IOSwap));
- assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
- assert_param(IS_I2S_FIFO_THRESHOLD(hi2s->Init.FifoThreshold));
- assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
- assert_param(IS_I2S_SLAVE_EXTEND_FRE_DETECTION(hi2s->Init.SlaveExtendFREDetection));
-
- if(hi2s->State == HAL_I2S_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2s->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
- }
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Clear I2S configuration register */
- CLEAR_REG(hi2s->Instance->I2SCFGR);
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd */
- if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
- {
- i2sodd = 0U;
- i2sdiv = 2U;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- /* Set I2S Packet Length value*/
- if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 32U;
- }
- else
- {
- /* Packet length is 16 bits */
- packetlength = 16U;
- }
-
- /* I2S standard */
- if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
- {
- /* In I2S standard packet lenght is multiplied by 2 */
- packetlength = packetlength * 2U;
- }
-
- /* Get the source clock value: based on System Clock value */
- /* SPI1,SPI2 and SPI3 share the same source clock */
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
- }
- else
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
- }
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit I2SCFGR register */
- i2sodd = (uint32_t)(i2sodd << 24U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- /* Set the error code */
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
- return HAL_ERROR;
- }
-
- /* Check if the SPI2S is disabled to edit I2SCFGR and CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
- }
-
- /* Clear and configure SPI2S I2SCFGR register */
- MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \
- SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_FIXCH | \
- SPI_I2SCFGR_WSINV | SPI_I2SCFGR_DATFMT | \
- SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD | \
- SPI_I2SCFGR_MCKOE), \
- (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
- hi2s->Init.Standard | hi2s->Init.DataFormat | \
- hi2s->Init.CPOL | hi2s->Init.SlaveExtendFREDetection | \
- hi2s->Init.WSInversion | hi2s->Init.Data24BitAlignment | \
- (uint32_t)(i2sdiv << 16U) | (uint32_t)(i2sodd) | \
- hi2s->Init.MCLKOutput));
-
- /* Clear and configure SPI2S CFG1 register */
- MODIFY_REG(hi2s->Instance->CFG1, SPI_CFG1_FTHLV, (uint32_t)(hi2s->Init.FifoThreshold << 5U));
-
- /* Unlock the AF configuration to configure CFG2 register*/
- CLEAR_BIT(hi2s->Instance->CR1 , SPI_CR1_IOLOCK);
-
- /* Clear and configure SPI2S CFG2 register */
- MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST | SPI_CFG2_IOSWP , (hi2s->Init.FirstBit | hi2s->Init.IOSwap));
-
- /* Insure that AFCNTR is managed only by Master */
- if (IS_I2S_MASTER(hi2s->Init.Mode))
- {
- /* Alternate function GPIOs control */
- MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
- }
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State= HAL_I2S_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the I2S peripheral
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Disable the I2S Peripheral Clock */
- __HAL_I2S_DISABLE(hi2s);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_I2S_MspDeInit(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief I2S MSP Init
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S MSP DeInit
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2S_Transmit()
- (++) HAL_I2S_Receive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2S_Transmit_IT()
- (++) HAL_I2S_Receive_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2S_Transmit_DMA()
- (++) HAL_I2S_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2S_TxCpltCallback()
- (++) HAL_I2S_TxHalfCpltCallback()
- (++) HAL_I2S_RxCpltCallback()
- (++) HAL_I2S_RxHalfCpltCallback()
- (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of frames to be sent.
- * @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t isDataFormat16B = 2U;
-
- /* Check Mode parameter */
- assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- /* Check the Data Format value */
- if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- isDataFormat16B = 0U;
- }
- else
- {
- isDataFormat16B = 1U;
- }
-
- if(!isDataFormat16B)
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->pTxBuffPtr = pData;
-
- /* Check if the SPI2S is already enabled */
- if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if(IS_I2S_MASTER(hi2s->Init.Mode))
- {
- hi2s->Instance->CR1 |= SPI_CR1_CSTART;
- }
-
- /* Transmit data in 32 Bit mode */
- if (!isDataFormat16B)
- {
- while (hi2s->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE))
- {
- *((__IO uint32_t*)&hi2s->Instance->TXDR) = *((uint32_t*)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount -= 2U;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
- }
- /* Transmit data in 16 Bit mode */
- else
- {
- while (hi2s->TxXferCount > 0U)
- {
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE))
- {
- if ((hi2s->TxXferCount > 1U) && (hi2s->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint32_t*)&hi2s->Instance->TXDR) = *((uint32_t*)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount -= 2U;
- }
- else
- {
- *((__IO uint16_t*)&hi2s->Instance->TXDR) = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
- }
-
- /* Wait until TXE flag is set, to confirm the end of the transaction */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of frames to be sent.
- * @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
- * @note This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t isDataFormat16B = 2U;
-
- /* Check Mode parameter */
- assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- /* Check the Data Format value */
- if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- isDataFormat16B = 0U;
- }
- else
- {
- isDataFormat16B = 1U;
- }
-
- if(!isDataFormat16B)
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->pRxBuffPtr = pData;
-
- /* Check if the SPI2S is already enabled */
- if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if(IS_I2S_MASTER(hi2s->Init.Mode))
- {
- hi2s->Instance->CR1 |= SPI_CR1_CSTART;
- }
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Receive data in 32 Bit mode */
- if ((!isDataFormat16B))
- {
- /* Transfer loop */
- while (hi2s->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE))
- {
- *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
- }
- /* Receive data in 16 Bit mode */
- else
- {
- /* Transfer loop */
- while (hi2s->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE))
- {
- if (hi2s->Instance->SR & I2S_FLAG_RXWNE)
- {
- *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount-=2;
- }
- else
- {
- *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint16_t);
- hi2s->RxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if((pData == NULL) || (Size == 0U))
- {
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- if (hi2s->State == HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set the transaction information */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pTxBuffPtr = pData;
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hi2s->pRxBuffPtr = NULL;
- hi2s->RxXferSize = 0U;
- hi2s->RxXferCount = 0U;
- hi2s->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
- {
- hi2s->TxISR = I2S_TxISR_32BIT;
- }
- else
- {
- hi2s->TxISR = I2S_TxISR_16BIT;
- }
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if (IS_I2S_MASTER(hi2s->Init.Mode))
- {
- /* Master transfer start */
- SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
- * between Master and Slave otherwise the I2S interrupt should be optimized.
- * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Set the transaction information */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pRxBuffPtr = pData;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hi2s->pTxBuffPtr = NULL;
- hi2s->TxXferSize = 0U;
- hi2s->TxXferCount = 0U;
- hi2s->TxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
- {
- hi2s->RxISR = I2S_RxISR_32BIT;
- }
- else
- {
- hi2s->RxISR = I2S_RxISR_16BIT;
- }
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if (IS_I2S_MASTER(hi2s->Init.Mode))
- {
- /* Master transfer start */
- SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Transmit data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_TX_MODE(hi2s->Init.Mode));
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Set the I2S Tx DMA Half transfert complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
- /* Set the I2S Tx DMA transfert complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize);
-
- /* Check if the I2S Tx request is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_RX_MODE(hi2s->Init.Mode));
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pRxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set the I2S Rx DMA Half transfert complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfert complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
-
- /* Check if the I2S Rx request is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable the I2S DMA Tx & Rx requests */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable the I2S DMA Tx & Rx requests */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable the I2S DMA Tx & Rx requests */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Enable the I2S DMA Tx & Rx requests */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
- }
-
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable the I2S Tx/Rx DMA requests */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable the I2S Tx/Rx DMA requests */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Abort the I2S DMA Channel tx */
- if(hi2s->hdmatx != NULL)
- {
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmatx);
- }
- /* Abort the I2S DMA Channel rx */
- if(hi2s->hdmarx != NULL)
- {
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmarx);
- HAL_DMA_Abort(hi2s->hdmarx);
- }
-
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- uint32_t itsource = hi2s->Instance->IER;
- uint32_t i2ssr = hi2s->Instance->SR;
-
- /* I2S in mode Receiver ------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
- ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((itsource & I2S_IT_RXNE) != RESET))
- {
- hi2s->RxISR(hi2s);
- return;
- }
-
- /* I2S in mode Transmitter ---------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((itsource & I2S_IT_RXNE) != RESET))
- {
- hi2s->TxISR(hi2s);
- return;
- }
-
- /* I2S interrupt error -------------------------------------------------*/
- if((itsource & I2S_IT_ERR) != RESET)
- {
- /* I2S Overrun error interrupt occured ---------------------------------*/
- if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- }
-
- /* I2S Underrun error interrupt occured --------------------------------*/
- if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- }
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call the Error Callback */
- HAL_I2S_ErrorCallback(hi2s);
- }
-}
-
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- while ((__HAL_I2S_GET_FLAG(hi2s, Flag) ? SET : RESET) != State)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Tx Transfer Half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S error callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2S state
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL state
- */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->State;
-}
-
-/**
- * @brief Return the I2S error code
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval I2S Error Code
- */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup I2S_Private
- * @{
- */
-/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- hi2s->TxXferCount = 0U;
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- hi2s->RxXferCount = 0U;
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- HAL_I2S_RxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_RxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_RxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- *((uint16_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
- hi2s->pRxBuffPtr += sizeof(uint16_t);
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- I2S_CloseRx_ISR(hi2s);
- }
-}
-
-/**
- * @brief Manage the 32-bit receive in Interrupt context.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_RxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- I2S_CloseRx_ISR(hi2s);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_TxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint16_t);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- I2S_CloseTx_ISR(hi2s);
- }
-}
-
-/**
- * @brief Handle the data 32-bit transmit in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_TxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount--;
-
- if (hi2s->TxXferCount == 0U)
- {
- I2S_CloseTx_ISR(hi2s);
- }
-}
-
-/**
- * @brief Handle the end of the RX transaction.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_CloseRx_ISR(I2S_HandleTypeDef *hi2s)
-{
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Clear underrun flag in 1 Line communication mode because transmitted is not feeded */
- if (IS_I2S_FD_MODE(hi2s->Init.Mode))
- {
- *((__IO uint8_t *)&hi2s->Instance->TXDR) = 0x01U;
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- if (hi2s->ErrorCode == HAL_I2S_ERROR_NONE)
- {
- HAL_I2S_RxCpltCallback(hi2s);
- }
- else
- {
- HAL_I2S_ErrorCallback(hi2s);
- }
-}
-
-/**
- * @brief Handle the end of the TX transaction.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_CloseTx_ISR(I2S_HandleTypeDef *hi2s)
-{
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (IS_I2S_FD_MODE(hi2s->Init.Mode))
- {
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
- if (hi2s->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_I2S_ErrorCallback(hi2s);
- }
- else
- {
- HAL_I2S_TxCpltCallback(hi2s);
- }
-}
-
-/**
- * @}
- */
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c
deleted file mode 100644
index c4b8af4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c
+++ /dev/null
@@ -1,927 +0,0 @@
- /**
- ******************************************************************************
- * @file stm32h7xx_hal_i2s_ex.c
- * @author MCD Application Team
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2S extension peripheral:
- * + IO operation functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### I2S Extension features #####
- ==============================================================================
- [..]
- (+) In I2S full duplex mode, SPI2S peripheral is able to manage sending and receiving
- data simultaneously using two data lines.
- @endverbatim
-
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
- (+) At full duplex transfer end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2SEx_TxRxHalfCpltCallback
- (+) At full duplex transfer end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
- (+) At the end of half transfer HAL_I2SEx_TxRxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At the end of transfer HAL_I2S_TxRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-/** @defgroup I2SEx I2SEx
- * @brief I2S Extended HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
- * @{
- */
-typedef enum
-{
- I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
- I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
-}I2S_UseTypeDef;
-/**
- * @}
- */
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
-static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
-
-static void I2SEx_2linesTxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2SEx_2linesTxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2SEx_2linesRxISR_16BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2SEx_2linesRxISR_32BIT(struct __I2S_HandleTypeDef *hi2s);
-static void I2SEx_CloseRxTx_ISR(I2S_HandleTypeDef *hi2s);
-
-static HAL_StatusTypeDef I2SEx_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
- * @brief I2SEx IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions#####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2SEx_TransmitReceive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2SEx_TransmitReceive_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2SEx_TransmitReceive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2SEx_TxRxCpltCallback()
- (++) HAL_I2SEx_TxRxErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer
- * @param pRxData: a 16-bit pointer to the Receive data buffer
- * @param Size: number of frames to be sent
- * @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t isDataFormat16B = 2U;
-
- /* Check Mode parameter */
- assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
-
- if((pTxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- /* Check the Data Format value */
- if (((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B) ||
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- isDataFormat16B = 0U;
- }
- else
- {
- isDataFormat16B = 1U;
- }
-
- if(!isDataFormat16B)
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
-
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
-
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- /* Check if the SPI2S is already enabled */
- if((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if(IS_I2S_MASTER(hi2s->Init.Mode))
- {
- hi2s->Instance->CR1 |= SPI_CR1_CSTART;
- }
-
- /* Transmit and Receive data in 32 Bit mode */
- if (!isDataFormat16B)
- {
- while ((hi2s->TxXferCount > 0U) || (hi2s->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((hi2s->TxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)))
- {
- *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount --;
- }
-
- /* Check RXNE flag */
- if ((hi2s->RxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)))
- {
- *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount --;
- }
-
- /* Timeout Management */
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
- /* Transmit and Receive data in 16 Bit mode */
- else
- {
- while ((hi2s->TxXferCount > 0U) || (hi2s->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((hi2s->TxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)))
- {
- if ( (hi2s->TxXferCount > 1U) && (hi2s->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount-=2;
- }
- else
- {
- *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint16_t);
- hi2s->TxXferCount--;
- }
- }
-
- /* Check RXNE flag */
- if ((hi2s->RxXferCount > 0U) && (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)))
- {
- if (hi2s->Instance->SR & I2S_FLAG_RXWNE)
- {
- *((uint32_t *)hi2s->pRxBuffPtr) = *((__IO uint32_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount-=2;
- }
- else
- {
- *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
- hi2s->pRxBuffPtr += sizeof(uint16_t);
- hi2s->RxXferCount--;
- }
- }
-
- /* Timeout Management */
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
- }
- }
-
- /* Wait until TXE flag is set, to confirm the end of the transaction */
- if (I2SEx_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- __HAL_UNLOCK(hi2s);
- return HAL_ERROR;
- }
-
- if (hi2s->State == HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
- /* Set the transaction information */
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->pTxBuffPtr = pTxData;
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hi2s->pRxBuffPtr = pRxData;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if (hi2s->Init.DataFormat > I2S_DATAFORMAT_16B)
- {
- hi2s->RxISR = I2SEx_2linesRxISR_32BIT;
- hi2s->TxISR = I2SEx_2linesTxISR_32BIT;
- }
- else
- {
- hi2s->RxISR = I2SEx_2linesRxISR_16BIT;
- hi2s->TxISR = I2SEx_2linesTxISR_16BIT;
- }
-
- /* Check if the I2S is already enabled */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- if (IS_I2S_MASTER(hi2s->Init.Mode))
- {
- /* Master transfer start */
- SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of frames to be sent.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
- /* Check Mode parameter */
- assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));
-
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
-
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
-
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set the I2S Rx DMA Half transfert complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
-
- /* Set the I2S Rx DMA transfert complete callback */
- hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
-
- /* Check if the I2S Rx requests are already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
- /* Set the I2S Tx DMA transfer callbacks as NULL because the communication closing
- is performed in DMA reception callbacks */
- hi2s->hdmatx->XferHalfCpltCallback = NULL;
- hi2s->hdmatx->XferCpltCallback = NULL;
- hi2s->hdmatx->XferErrorCallback = NULL;
-
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize);
-
- /* Check if the I2S Tx requests are already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Enable Tx/Rx DMA Request */
- SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Tx/Rx Transfer half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx/Rx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-
-/**
- * @brief DMA I2S transmit receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
- {
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable Tx/Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN);
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
-
- if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
- {
- HAL_I2S_ErrorCallback(hi2s);
- return;
- }
- }
- HAL_I2SEx_TxRxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S transmit receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Check if the SPI2S is disabled to edit CFG1 register */
- if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
-
- /* Enable SPI peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module.
- * @retval None
- */
-static void I2SEx_2linesRxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Receive data in 16 Bit mode */
- *((uint16_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
- hi2s->pRxBuffPtr += sizeof(uint16_t);
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
-
- if (hi2s->TxXferCount == 0U)
- {
- I2SEx_CloseRxTx_ISR(hi2s);
- }
- }
-}
-
-/**
- * @brief Rx 32-bit handler for Transmit and Receive in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module.
- * @retval None
- */
-static void I2SEx_2linesRxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Receive data in 32 Bit mode */
- *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
- hi2s->pRxBuffPtr += sizeof(uint32_t);
- hi2s->RxXferCount--;
-
- if (hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
-
- if (hi2s->TxXferCount == 0U)
- {
- I2SEx_CloseRxTx_ISR(hi2s);
- }
- }
-}
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module.
- * @retval None
- */
-static void I2SEx_2linesTxISR_16BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint16_t);
- hi2s->TxXferCount--;
-
- /* Enable CRC Transmission */
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable TXE interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
-
- if (hi2s->RxXferCount == 0U)
- {
- I2SEx_CloseRxTx_ISR(hi2s);
- }
- }
-}
-
-/**
- * @brief Tx 32-bit handler for Transmit and Receive in Interrupt mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module.
- * @retval None
- */
-static void I2SEx_2linesTxISR_32BIT(struct __I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data in 32 Bit mode */
- *((__IO uint32_t *)&hi2s->Instance->TXDR) = *((uint32_t *)hi2s->pTxBuffPtr);
- hi2s->pTxBuffPtr += sizeof(uint32_t);
- hi2s->TxXferCount--;
-
- /* Enable CRC Transmission */
- if (hi2s->TxXferCount == 0U)
- {
- /* Disable TXE interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
-
- if (hi2s->RxXferCount == 0U)
- {
- I2SEx_CloseRxTx_ISR(hi2s);
- }
- }
-}
-
-/**
- * @brief Handle the end of the RXTX transaction.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module.
- * @retval None
- */
-static void I2SEx_CloseRxTx_ISR(I2S_HandleTypeDef *hi2s)
-{
- /* Disable ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_TXE | I2S_IT_ERR));
-
- if (hi2s->ErrorCode == HAL_I2S_ERROR_NONE)
- {
- if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_RxCpltCallback(hi2s);
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_ErrorCallback(hi2s);
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2SEx_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(State == RESET)
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c
deleted file mode 100644
index 8448dbf..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c
+++ /dev/null
@@ -1,2283 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_irda.c
- * @author MCD Application Team
- * @brief IRDA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the IrDA (Infrared Data Association) Peripheral
- * (IRDA)
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The IRDA HAL driver can be used as follows:
-
- (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
- (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
- in setting the associated USART or UART in IRDA mode:
- (++) Enable the USARTx/UARTx interface clock.
- (++) USARTx/UARTx pins configuration:
- (+++) Enable the clock for the USARTx/UARTx GPIOs.
- (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
- (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
- (+++) Configure the USARTx/UARTx interrupt priority.
- (+++) Enable the NVIC USARTx/UARTx IRQ handle.
- (+++) The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
- (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
- and HAL_IRDA_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
- the normal or low power mode and the clock prescaler in the hirda handle Init structure.
-
- (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_IRDA_MspInit() API.
-
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
- (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
- (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
- *** IRDA HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IRDA HAL driver.
-
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
- (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
- (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
- (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
- (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
- (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
-
- [..]
- (@) You can refer to the IRDA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup IRDA IRDA
- * @brief HAL IRDA module driver
- * @{
- */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
- * @{
- */
-#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
-#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx
- in asynchronous IRDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- (++) Power mode
- (++) Prescaler setting
- (++) Receiver/transmitter modes
-
- [..]
- The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
- (details for the procedures are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible IRDA frame formats are listed in the
- following table.
-
- Table 1. IRDA frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | IRDA frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and initialize the associated handle.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the IRDA handle */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- if(hirda->gState == HAL_IRDA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hirda->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_IRDA_MspInit(hirda);
- }
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* Disable the Peripheral to update the configuration registers */
- __HAL_IRDA_DISABLE(hirda);
-
- /* Set the IRDA Communication parameters */
- if (IRDA_SetConfig(hirda) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-
- /* set the UART/USART in IRDA mode */
- hirda->Instance->CR3 |= USART_CR3_IREN;
-
- /* Enable the Peripheral */
- __HAL_IRDA_ENABLE(hirda);
-
- /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
- return (IRDA_CheckIdleState(hirda));
-}
-
-/**
- * @brief DeInitialize the IRDA peripheral.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the IRDA handle */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_IRDA_MspDeInit(hirda);
- /* Disable the Peripheral */
- __HAL_IRDA_DISABLE(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_RESET;
- hirda->RxState = HAL_IRDA_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the IRDA MSP.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the IRDA MSP.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the IRDA data transfers.
-
- [..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
-
- (#) There are two modes of transfer:
- (++) Blocking mode: the communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: the communication is performed using Interrupts
- or DMA, these API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_IRDA_Transmit()
- (++) HAL_IRDA_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_IRDA_Transmit_IT()
- (++) HAL_IRDA_Receive_IT()
- (++) HAL_IRDA_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_IRDA_Transmit_DMA()
- (++) HAL_IRDA_Receive_DMA()
- (++) HAL_IRDA_DMAPause()
- (++) HAL_IRDA_DMAResume()
- (++) HAL_IRDA_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
- (++) HAL_IRDA_TxHalfCpltCallback()
- (++) HAL_IRDA_TxCpltCallback()
- (++) HAL_IRDA_RxHalfCpltCallback()
- (++) HAL_IRDA_RxCpltCallback()
- (++) HAL_IRDA_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_IRDA_Abort()
- (+) HAL_IRDA_AbortTransmit()
- (+) HAL_IRDA_AbortReceive()
- (+) HAL_IRDA_Abort_IT()
- (+) HAL_IRDA_AbortTransmit_IT()
- (+) HAL_IRDA_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_IRDA_AbortCpltCallback()
- (+) HAL_IRDA_AbortTransmitCpltCallback()
- (+) HAL_IRDA_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Specify timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0)
- {
- hirda->TxXferCount--;
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pData += 2;
- }
- else
- {
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
- }
- }
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @param Timeout: Specify timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
- uhMask = hirda->Mask;
-
- /* Check data remaining to be received */
- while(hirda->RxXferCount > 0)
- {
- hirda->RxXferCount--;
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2;
- }
- else
- {
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the IRDA Transmit Data Register Empty Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the IRDA transmit DMA channel */
- HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @note When the IRDA parity is enabled (PCE = 1) the received data contains
- * the parity bit (MSB position).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the IRDA DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- /* Enable the IRDA DMA Tx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the IRDA DMA Rx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
- HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
-
- /* Stop IRDA DMA Tx request if ongoing */
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmatx);
- }
-
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmarx);
- }
-
- IRDA_EndRxTransfer(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
-{
- uint32_t abortcplt = 1;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
- }
- else
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
- }
- else
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
- {
- /* IRDA Tx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0;
- }
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
- {
- /* IRDA Rx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1;
- }
- else
- {
- abortcplt = 0;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1)
- {
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
- hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle IRDA interrupt request.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
- uint32_t isrflags = READ_REG(hirda->Instance->ISR);
- uint32_t cr1its = READ_REG(hirda->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
- {
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(hirda->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
- {
- /* IRDA parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
- }
-
- /* IRDA frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- }
-
- /* IRDA noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- }
-
- /* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- }
-
- /* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
- {
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the IRDA state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- IRDA_EndRxTransfer(hirda);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- IRDA_Transmit_IT(hirda);
- return;
- }
-
- /* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- IRDA_EndTransmit_IT(hirda);
- return;
- }
-
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer complete callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA error callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Receive Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief IRDA State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of IrDA
- communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
- of the IRDA peripheral handle.
- (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
- communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the IRDA handle state.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL state
- */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
- /* Return IRDA handle state */
- uint32_t temp1= 0x00, temp2 = 0x00;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
-
- return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the IRDA handle error code.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval IRDA Error Code
- */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
- return hirda->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @brief Configure the IRDA peripheral.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tmpreg = 0x00000000;
- IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
- PLL2_ClocksTypeDef pll2_clocks;
- PLL3_ClocksTypeDef pll3_clocks;
-
- /* Check the communication parameters */
- assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
- assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
- assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
- assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
- assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
- assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Configure the IRDA Word Length, Parity and transfer Mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
- tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
-
- MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- IRDA_GETCLOCKSOURCE(hirda, clocksource);
- switch (clocksource)
- {
- case IRDA_CLOCKSOURCE_D2PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_D2PCLK2:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_PLL2Q:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- hirda->Instance->BRR = (uint16_t)((pll2_clocks.PLL2_Q_Frequency + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_PLL3Q:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- hirda->Instance->BRR = (uint16_t)((pll3_clocks.PLL3_Q_Frequency + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_CSI:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- return ret;
-}
-
-/**
- * @brief Check the IRDA Idle State.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the IRDA ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the IRDA state*/
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle IRDA Communication Timeout.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param Flag: specifies the IRDA flag to check.
- * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
- * @param Tickstart: tick start value.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda: IRDA handle.
- * @retval None
- */
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-}
-
-/**
- * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
- * @param hirda: IRDA handle.
- * @retval None
- */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-/**
- * @brief DMA IRDA transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- hirda->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else
- {
- HAL_IRDA_TxCpltCallback(hirda);
- }
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_IRDA_TxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- hirda->RxXferCount = 0;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_IRDA_RxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- hirda->RxXferCount = 0U;
- hirda->TxXferCount = 0U;
-
- /* Stop IRDA DMA Tx request if ongoing */
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
- {
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- IRDA_EndRxTransfer(hirda);
- }
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
-
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hirda->RxXferCount = 0;
- hirda->TxXferCount = 0;
-
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
- {
- if(hirda->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
- {
- if(hirda->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hirda->TxXferCount = 0;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef*)hdma)->Parent;
-
- hirda->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Transmit_IT().
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- if(hirda->TxXferCount == 0)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- hirda->pTxBuffPtr += 2;
- }
- else
- {
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
- }
- hirda->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable the IRDA Transmit Complete Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Tx process is ended, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data in non-blocking mode.
- * Function is called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Receive_IT().
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
- uint16_t uhMask = hirda->Mask;
-
- /* Check that a Rx process is ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
-
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- hirda->pRxBuffPtr +=2;
- }
- else
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
- }
-
- if(--hirda->RxXferCount == 0)
- {
- /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c
deleted file mode 100644
index ee4f120..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_iwdg.c
- * @author MCD Application Team
- * @brief IWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and Start functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### IWDG Generic features #####
- ==============================================================================
- [..]
- (+) The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
-
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
- disabled. The counter starts counting down from the reset value (0xFFF).
- When it reaches the end of count value (0x000) a reset signal is
- generated (IWDG reset).
-
- (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
-
- (+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
- reset occurs.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the IWDG counter either continues to work normally or stops, depending
- on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
-
- [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
- IWDG_WINR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
- value will be loaded in the IWDG counter each time the watchdog is
- reloaded, then the IWDG will start counting down from this value.
- (++) Wait for status flags to be reset
- (++) Depending on window parameter:
- (+++) If Window Init parameter is same as Window register value,
- nothing more is done but reload counter value in order to exit
- function withy exact time base.
- (+++) Else modify Window register. This will automatically reload
- watchdog counter.
-
- (#) Then the application program must refresh the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- HAL_IWDG_Refresh() function.
-
- *** IWDG HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IWDG HAL driver:
- (+) __HAL_IWDG_START: Enable the IWDG peripheral
- (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
- the reload register
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-/** @addtogroup IWDG
- * @brief IWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
- * @{
- */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to LSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48u
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Start functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters in the
- IWDG_InitTypeDef of associated handle.
- (+) Manage Window option.
- (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
- is reloaded in order to exit function with correct time base.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the IWDG according to the specified parameters in the
- * IWDG_InitTypeDef and start watchdog. Before exiting function,
- * watchdog is refreshed in order to have correct time base.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
- uint32_t tickstart;
-
- /* Check the IWDG handle allocation */
- if(hiwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
- assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
- assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
- assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
-
- /* Enable IWDG. LSI is turned on automaticaly */
- __HAL_IWDG_START(hiwdg);
-
- /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
- 0x5555 in KR */
- IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
- /* Write to IWDG registers the Prescaler & Reload values to work with */
- hiwdg->Instance->PR = hiwdg->Init.Prescaler;
- hiwdg->Instance->RLR = hiwdg->Init.Reload;
-
- /* Check pending flag, if previous update not done, return timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
- {
- if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If window parameter is different than current value, modify window
- register */
- if(hiwdg->Instance->WINR != hiwdg->Init.Window)
- {
- /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
- even if window feature is disabled, Watchdog will be reloaded by writing
- windows register */
- hiwdg->Instance->WINR = hiwdg->Init.Window;
- }
- else
- {
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Refresh the IWDG.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Refresh the IWDG.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
deleted file mode 100644
index 4924da6..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
+++ /dev/null
@@ -1,3459 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_jpeg.c
- * @author MCD Application Team
- * @brief JPEG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the JPEG encoder/decoder peripheral:
- * + Initialization and de-initialization functions
- * + JPEG processing functions encoding and decoding
- * + JPEG decoding Getting Info and encoding configuration setting
- * + JPEG enable/disable header parsing functions (for decoding)
- * + JPEG Input/Output Buffer configuration.
- * + JPEG callback functions
- * + JPEG Abort/Pause/Resume functions
- * + JPEG custom quantization tables setting functions
- * + IRQ handler management
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
- Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.
-
- (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
- the encoding parameters (mandatory before calling the encoding function).
- the application can change the encoding parameter "ImageQuality" from
- 1 to 100 to obtain a more or less quality (visual quality vs the original row image),
- and inversely more or less jpg file size.
-
- (#) Note that for decoding operation the JPEG peripheral output data are organized in
- YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
- ISO/IEC 10918-1 standard.
- It is up to the application to transform these YCbCr blocks to RGB data that can be display.
-
- Respectively, for Encoding operation the JPEG peripheral input should be organized
- in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
- MCU blocks transformation before feeding the JPEG peripheral with data.
-
- (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
- a JPEG encoding/decoding operation in polling method (blocking).
-
- (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
- a JPEG encoding/decoding operation with Interrupt method (not blocking).
-
- (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
- a JPEG encoding/decoding operation with DMA method (not blocking).
-
- (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
- is a JPEG decoding to provide the application with JPEG image parameters.
- This callback is asserted when the JPEG peripheral successfully parse the
- JPEG header.
-
- (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
- operations to inform the application that the input buffer has been
- consumed by the peripheral and to ask for a new data chunk if the operation
- (encoding/decoding) has not been complete yet.
-
- (++) This CallBack should be implemented in the application side. It should
- call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
- or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
- to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
- application to provide a new input data chunk.
- Once the application succeed getting new data and if the input has been paused,
- the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
- input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
- If the application has ended feeding the HAL JPEG with input data (no more input data), the application
- Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
- with the parameter InDataLength set to zero.
-
- (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
- to the application to provide the input data (for encoding or decoding) by chunks.
- If the new input data chunk is not available (because data should be read from an input file
- for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
- Once the new input data chunk is available ( read from a file for example), the application
- can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
- then resume the JPEG HAL input by calling function HAL_JPEG_Resume.
-
- (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
- any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available.
- However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
- (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
- Transferring the previous chunk buffer to the JPEG peripheral.
-
- (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
- has filled the given output buffer with the given size.
-
- (++) This CallBack should be implemented in the application side. It should
- call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
- with the new output buffer location and size to be used to store next data chunk.
- if the application is not ready to provide the output chunk location then it can
- call the function HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
- to inform the JPEG HAL driver that it shall pause output data. Once the application
- is ready to receive the new data chunk (output buffer location free or available) it should call
- the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
- with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
- to inform the HAL that it shall resume outputting data in the given output buffer.
-
- (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
- the application to receive data from the JPEG peripheral by chunks. when a chunk
- is received, the application can pause the HAL JPEG output data to be able to process
- these received data (YCbCr to RGB conversion in case of decoding or data storage in case
- of encoding).
-
- (++) The application can call functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
- any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
- However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
- (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
- Transferring the previous chunk buffer from the JPEG peripheral to the application.
-
- (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
- ended the current JPEG encoding operation, and all output data has been transmitted
- to the application.
-
- (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
- ended the current JPEG decoding operation. and all output data has been transmitted
- to the application.
-
- (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
- the current operation. the application can call the function "HAL_JPEG_GetError"
- to retrieve the error codes.
-
- (#) By default the HAL JPEG driver uses the default quantization tables
- as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
- User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
- Note that for decoding the quantization tables are automatically extracted from
- the JPEG header.
-
- (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()
-
- *** JPEG HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in JPEG HAL driver.
-
- (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
- (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral.
- (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral.
- (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag.
- (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag.
- (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt.
- (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt.
- (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled).
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup JPEG JPEG
- * @brief JPEG HAL module driver.
- * @{
- */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
-
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup JPEG_Private_Constants
- * @{
- */
-#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
-#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
-#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/
-
-#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
-#define JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/
-
-#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
-
-#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/
-#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/
-#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */
-
-#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */
-#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */
-#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */
-#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */
-
-
-#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */
-
-#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */
-#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */
-
-#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */
-
-#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */
-
-#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */
-#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */
-/**
- * @}
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/** @addtogroup JPEG_Private_Types
- * @{
- */
-
-/*
- JPEG Huffman Table Structure definition :
- This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification
- */
-typedef struct
-{
- /* These two fields directly represent the contents of a JPEG DHT marker */
- uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
-
- uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
-
-
-}JPEG_ACHuffTableTypeDef;
-
-typedef struct
-{
- /* These two fields directly represent the contents of a JPEG DHT marker */
- uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */
-
- uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
-
-
-}JPEG_DCHuffTableTypeDef;
-
-typedef struct
-{
- uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */
-
- uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */
-
-}JPEG_AC_HuffCodeTableTypeDef;
-
-typedef struct
-{
- uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */
-
- uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */
-
-}JPEG_DC_HuffCodeTableTypeDef;
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup JPEG_Private_Variables
- * @{
- */
-
-static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =
-{
- { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/
-
- { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */
-
-};
-
-static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =
-{
- { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/
-
- { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */
-};
-
-static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =
-{
- { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/
-
- { 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */
- 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
- 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
- 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
- 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
- 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
- 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
- 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
- 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
- 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
- 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
- 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
- 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
- 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
- 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
- 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
- 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
- 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
- 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
- 0xf9, 0xfa }
-};
-
-static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =
-{
- { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/
-
- { 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */
- 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
- 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
- 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
- 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
- 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
- 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
- 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
- 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
- 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
- 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
- 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
- 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
- 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
- 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
- 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
- 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
- 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
- 0xf9, 0xfa }
-};
-
-
-/*
- These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1.
-*/
-static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
-{
- 16, 11, 10, 16, 24, 40, 51, 61,
- 12, 12, 14, 19, 26, 58, 60, 55,
- 14, 13, 16, 24, 40, 57, 69, 56,
- 14, 17, 22, 29, 51, 87, 80, 62,
- 18, 22, 37, 56, 68, 109, 103, 77,
- 24, 35, 55, 64, 81, 104, 113, 92,
- 49, 64, 78, 87, 103, 121, 120, 101,
- 72, 92, 95, 98, 112, 100, 103, 99
-};
-static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
-{
- 17, 18, 24, 47, 99, 99, 99, 99,
- 18, 21, 26, 66, 99, 99, 99, 99,
- 24, 26, 56, 99, 99, 99, 99, 99,
- 47, 66, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99
-};
-
-static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
-{
- 0, 1, 8, 16, 9, 2, 3, 10,
- 17, 24, 32, 25, 18, 11, 4, 5,
- 12, 19, 26, 33, 40, 48, 41, 34,
- 27, 20, 13, 6, 7, 14, 21, 28,
- 35, 42, 49, 56, 57, 50, 43, 36,
- 29, 22, 15, 23, 30, 37, 44, 51,
- 58, 59, 52, 45, 38, 31, 39, 46,
- 53, 60, 61, 54, 47, 55, 62, 63
-};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup JPEG_Private_Functions_Prototypes
- * @{
- */
-
-static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);
-static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
-static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
-static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress);
-static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress);
-static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
-static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
-static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress);
-static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);
-static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);
-static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);
-
-static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);
-static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);
-static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);
-static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);
-static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);
-
-static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
-static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
-static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
-static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
-static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma);
-static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma);
-static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma);
-static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma);
-/**
- * @}
- */
-
-/** @defgroup JPEG_Exported_Functions JPEG Exported Functions
- * @{
- */
-
-/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the JPEG peripheral and creates the associated handle
- (+) DeInitialize the JPEG peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the JPEG according to the specified
- * parameters in the JPEG_InitTypeDef and creates the associated handle.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
-{
- /*Note : these intermediate variables are used to avoid MISRA warning
- regarding rule 11.5 */
- uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable);
- uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable);
- uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable);
- uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable);
-
- /* Check the JPEG handle allocation */
- if(hjpeg == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hjpeg->State == HAL_JPEG_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hjpeg->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_JPEG_MspInit(hjpeg);
- }
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- /* Start the JPEG Core*/
- __HAL_JPEG_ENABLE(hjpeg);
-
- /* Stop the JPEG encoding/decoding process*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- /* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- /* Flush input and output FIFOs*/
- hjpeg->Instance->CR |= JPEG_CR_IFF;
- hjpeg->Instance->CR |= JPEG_CR_OFF;
-
- /* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
-
- /* init default quantization tables*/
- hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable);
- hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable);
- hjpeg->QuantTable2 = NULL;
- hjpeg->QuantTable3 = NULL;
-
- /* init the default Huffman tables*/
- if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK)
- {
- hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;
-
- return HAL_ERROR;
- }
-
- /* Enable header processing*/
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
-
- /* Reset JpegInCount and JpegOutCount */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /* Reset the JPEG ErrorCode */
- hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
-
- /*Clear the context filelds*/
- hjpeg->Context = 0;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the JPEG peripheral.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)
-{
- /* Check the JPEG handle allocation */
- if(hjpeg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_JPEG_MspDeInit(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- /* Reset the JPEG ErrorCode */
- hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
-
- /* Reset JpegInCount and JpegOutCount */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_RESET;
-
- /*Clear the context fields*/
- hjpeg->Context = 0;
-
- /* Release Lock */
- __HAL_UNLOCK(hjpeg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the JPEG MSP.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes JPEG MSP.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions
- * @brief JPEG Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Configuration functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
- (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding
- (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding
- (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
- (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the JPEG encoding configuration.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains
- * the encoding configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
-{
- uint32_t error = HAL_OK;
- uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU;
-
- /* Check the JPEG handle allocation */
- if( (hjpeg == NULL) || (pConf == NULL) )
- {
- return HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));
- assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));
- assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- hjpeg->Conf.ColorSpace = pConf->ColorSpace;
- hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling;
- hjpeg->Conf.ImageHeight = pConf->ImageHeight;
- hjpeg->Conf.ImageWidth = pConf->ImageWidth;
- hjpeg->Conf.ImageQuality = pConf->ImageQuality;
-
- /* Reset the Color Space : by default only one quantization table is used*/
- hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;
-
- /* Set Number of color components*/
- if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
- {
- /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/
- hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;
-
- JPEG_SetColorGrayScale(hjpeg);
- /* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
- }
- else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
- {
- /*
- Set the Color Space for YCbCr : 2 quantization tables are used
- one for Luminance(Y) and one for both Chrominances (Cb & Cr)
- */
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;
-
- JPEG_SetColorYCBCR(hjpeg);
-
- /* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
- /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
-
- if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
- {
- /* use 3 quantization tables , one for each component*/
- hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;
-
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
-
- /*Use Quantization 1 table for component 1*/
- hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
- hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0;
-
- /*Use Quantization 2 table for component 2*/
- hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);
- hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1;
- }
- }
- else /* ColorSpace == JPEG_CMYK_COLORSPACE */
- {
- JPEG_SetColorCMYK(hjpeg);
-
- /* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
- /*By default quantization table 0 for All components*/
-
- if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
- {
- /* use 4 quantization tables , one for each component*/
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;
-
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3));
-
- /*Use Quantization 1 table for component 1*/
- hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0;
-
- /*Use Quantization 2 table for component 2*/
- hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1;
-
- /*Use Quantization 3 table for component 3*/
- hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT;
- }
- }
-
- if(error != HAL_OK)
- {
- hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Set the JPEG State to ready */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- return HAL_ERROR;
- }
- /* Set the image size*/
- MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16)); /* set the number of lines*/
- MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16)); /* set the number of pixels per line*/
-
-
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
- {
- hfactor = 16;
- vfactor = 16;
- }
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
- {
- hfactor = 16;
- vfactor = 8;
- }
- else /* Default is 8x8 MCU, 4:4:4*/
- {
- hfactor = 8;
- vfactor = 8;
- }
-
- hMCU = (hjpeg->Conf.ImageWidth / hfactor);
- if((hjpeg->Conf.ImageWidth % hfactor) != 0)
- {
- hMCU++; /*+1 for horizontal incomplete MCU */
- }
-
- vMCU = (hjpeg->Conf.ImageHeight / vfactor);
- if((hjpeg->Conf.ImageHeight % vfactor) != 0)
- {
- vMCU++; /*+1 for vertical incomplete MCU */
- }
-
- numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
- /* Set the number of MCU*/
- hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);
-
- hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Set the JPEG State to ready */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Return function status */
- return HAL_BUSY;
- }
- }
-}
-
-/**
- * @brief Extract the image configuration from the JPEG header during the decoding
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains
- * The JPEG decoded header informations
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
-{
- uint32_t yblockNb, cBblockNb, cRblockNb;
-
- /* Check the JPEG handle allocation */
- if((hjpeg == NULL) || (pInfo == NULL))
- {
- return HAL_ERROR;
- }
-
- /*Read the conf parameters */
- if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
- {
- pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;
- }
- else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0)
- {
- pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;
- }
- else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
- {
- pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;
- }
-
- pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16;
- pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16;
-
- if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
- {
- yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;
- cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;
- cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;
-
- if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0))
- {
- pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/
- }
- else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0))
- {
- pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
- }
- else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0))
- {
- pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;
- }
- else /*Default is 4:4:4*/
- {
- pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
- }
- }
- else
- {
- pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
- }
-
- pInfo->ImageQuality = JPEG_GetQuality(hjpeg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enable JPEG Header parsing for decoding
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for the JPEG.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
-{
- /* Process locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- /* Enable header processing*/
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable JPEG Header parsing for decoding
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for the JPEG.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
-{
- /* Process locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- /* Disable header processing*/
- hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Modify the default Quantization tables used for JPEG encoding.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1.
- * If NULL assume no need to update the table and no error return
- * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2.
- * If NULL assume no need to update the table and no error return.
- * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3,
- * If NULL assume no need to update the table and no error return.
- * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4.
- * If NULL assume no need to update the table and no error return.
- *
- * @retval HAL status
- */
-
-
-HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
-{
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /* Change the DMA state */
- hjpeg->State = HAL_JPEG_STATE_BUSY;
-
- hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;
-
- hjpeg->QuantTable0 = QTable0;
- hjpeg->QuantTable1 = QTable1;
- hjpeg->QuantTable2 = QTable2;
- hjpeg->QuantTable3 = QTable3;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the DMA state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### JPEG processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) HAL_JPEG_Encode() : JPEG encoding with polling process
- (+) HAL_JPEG_Decode() : JPEG decoding with polling process
- (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process
- (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process
- (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
- (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
- (+) HAL_JPEG_Pause() : Pause the Input/Output processing
- (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing
- (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer
- (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
- (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts JPEG encoding with polling processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataInMCU: Pointer to the Input buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOut: Pointer to the jpeg output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
- {
- return HAL_ERROR;
- }
- /* Process locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State != HAL_JPEG_STATE_READY)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
-
- /*Set the Context to Encode with Polling*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);
-
- /* Get tick */
- tickstart = HAL_GetTick();
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataInMCU;
- hjpeg->pJpegOutBuffPtr = pDataOut;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- /*JPEG data processing : In/Out FIFO transfer*/
- while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
-
- /* Update error code */
- hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
-
- }else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_ERROR;
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts JPEG decoding with polling processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataIn: Pointer to the input data buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOutMCU: Pointer to the Output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
-
- /*Set the Context to Decode with Polling*/
- /*Set the Context to Encode with Polling*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);
-
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataIn;
- hjpeg->pJpegOutBuffPtr = pDataOutMCU;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- /*JPEG data processing : In/Out FIFO transfer*/
- while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
-
- /* Update error code */
- hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
-
- }else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts JPEG encoding with interrupt processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataInMCU: Pointer to the Input buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOut: Pointer to the jpeg output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
-{
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State != HAL_JPEG_STATE_READY)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
- else
- {
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
-
- /*Set the Context to Encode with IT*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);
-
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataInMCU;
- hjpeg->pJpegOutBuffPtr = pDataOut;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_ERROR;
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts JPEG decoding with interrupt processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataIn: Pointer to the input data buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOutMCU: Pointer to the Output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
-{
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
-
- /*Set the Context to Decode with IT*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);
-
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataIn;
- hjpeg->pJpegOutBuffPtr = pDataOutMCU;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts JPEG encoding with DMA processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataInMCU: Pointer to the Input buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOut: Pointer to the jpeg output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
-{
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State != HAL_JPEG_STATE_READY)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
- else
- {
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
-
- /*Set the Context to Encode with DMA*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataInMCU;
- hjpeg->pJpegOutBuffPtr = pDataOut;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- /* JPEG encoding process using DMA */
- JPEG_DMA_StartProcess(hjpeg);
-
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_ERROR;
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts JPEG decoding with DMA processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataIn: Pointer to the input data buffer
- * @param InDataLength: size in bytes Input buffer
- * @param pDataOutMCU: Pointer to the Output data buffer
- * @param OutDataLength: size in bytes of the Output buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
-{
- /* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
-
- /* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hjpeg);
-
- if(hjpeg->State == HAL_JPEG_STATE_READY)
- {
- /*Change JPEG state*/
- hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
-
- /*Set the Context to Decode with DMA*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
- hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA);
-
- /*Store In/out buffers pointers and size*/
- hjpeg->pJpegInBuffPtr = pDataIn;
- hjpeg->pJpegOutBuffPtr = pDataOutMCU;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
-
- /*Reset In/out data counter */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Init decoding process*/
- JPEG_Init_Process(hjpeg);
-
- /* JPEG decoding process using DMA */
- JPEG_DMA_StartProcess(hjpeg);
-
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_BUSY;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Pause the JPEG Input/Output processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param XferSelection: This parameter can be one of the following values :
- * JPEG_PAUSE_RESUME_INPUT : Pause Input processing
- * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing
- * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
-{
- uint32_t mask = 0;
-
- assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
-
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
- {
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
- {
- hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
- }
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
- {
- hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
- }
- }
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
- {
-
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
- {
- hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
- mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
- }
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
- {
- hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
- mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
- }
- __HAL_JPEG_DISABLE_IT(hjpeg,mask);
-
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Resume the JPEG Input/Output processing
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param XferSelection: This parameter can be one of the following values :
- * JPEG_PAUSE_RESUME_INPUT : Resume Input processing
- * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing
- * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
-{
- uint32_t mask = 0;
- uint32_t xfrSize = 0;
-
- assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
-
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
- {
-
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
- {
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
-
- /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
- then MDMA In buffer size is 32 bytes
-
- else (MDMA In is triggred with JPEG In FIFO not full flag)
- then MDMA In buffer size is 4 bytes
- */
- xfrSize = hjpeg->hdmain->Init.BufferTransferLength;
-
- /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % xfrSize);
-
- if(hjpeg->InDataLength > 0)
- {
- /* Start DMA FIFO In transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
- }
- }
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
- {
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
-
- if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
- {
- JPEG_DMA_PollResidualData(hjpeg);
- }
- else
- {
- /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
- then MDMA out buffer size is 32 bytes
- else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
- then MDMA buffer size is 4 bytes
- */
- xfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
-
- /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
- hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % xfrSize);
-
- /* Start DMA FIFO Out transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
- }
- }
- }
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
- {
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
- {
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
- mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
- }
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
- {
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
- mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
- }
- __HAL_JPEG_ENABLE_IT(hjpeg,mask);
-
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Config Encoding/Decoding Input Buffer.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module.
- * @param pNewInputBuffer: Pointer to the new input data buffer
- * @param InDataLength: Size in bytes of the new Input data buffer
- * @retval HAL status
- */
-void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
-{
- hjpeg->pJpegInBuffPtr = pNewInputBuffer;
- hjpeg->InDataLength = InDataLength;
-}
-
-/**
- * @brief Config Encoding/Decoding Output Buffer.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module.
- * @param pNewOutputBuffer: Pointer to the new output data buffer
- * @param OutDataLength: Size in bytes of the new Output data buffer
- * @retval HAL status
- */
-void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
-{
- hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;
- hjpeg->OutDataLength = OutDataLength;
-}
-
-/**
- * @brief Aborts the JPEG Encoding/Decoding.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t tickstart, tmpContext;
-
- tmpContext = hjpeg->Context;
-
- /*Reset the Context operation and method*/
- hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);
-
- if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
- {
- /* Stop the DMA In/out Xfer*/
- HAL_MDMA_Abort(hjpeg->hdmaout);
- HAL_MDMA_Abort(hjpeg->hdmain);
- }
-
- /* Stop the JPEG encoding/decoding process*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the JPEG Codec is effectively disabled */
- while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE)
- {
- /* Update error code */
- hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
-
- /* Change the DMA state */
- hjpeg->State = HAL_JPEG_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- /* Flush input and output FIFOs*/
- hjpeg->Instance->CR |= JPEG_CR_IFF;
- hjpeg->Instance->CR |= JPEG_CR_OFF;
-
- /* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
-
- /* Reset JpegInCount and JpegOutCount */
- hjpeg->JpegInCount = 0;
- hjpeg->JpegOutCount = 0;
-
- /*Reset the Context Pause*/
- hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);
-
- /* Change the DMA state*/
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions
- * @brief JPEG process callback functions.
- *
-@verbatim
- ==============================================================================
- ##### JPEG Decode and Encode callback functions #####
- ==============================================================================
- [..] This section provides callback functions:
- (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback
- (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
- (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
- (+) HAL_JPEG_ErrorCallback() : JPEG error callback.
- (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback.
- (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Decoding JPEG Info ready callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains
- * The JPEG decoded header informations
- * @retval None
- */
-__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
- UNUSED(pInfo);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Encoding complete callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Decoding complete callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief JPEG error callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
- __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Get New Data chunk callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param NbDecodedData: Number of consummed data in the previous chunk in bytes
- * @retval None
- */
- __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
- UNUSED(NbDecodedData);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_GetDataCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Decoded/Encoded Data ready callback.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param pDataOut: pointer to the output data buffer
- * @param OutDataLength: number in bytes of data available in the specified output buffer
- * @retval None
- */
-__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hjpeg);
- UNUSED(pDataOut);
- UNUSED(OutDataLength);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_JPEG_DataReadyCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management
- * @brief JPEG IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### JPEG IRQ handler management #####
- ==============================================================================
- [..] This section provides JPEG IRQ handler function.
- (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles JPEG interrupt request.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
-{
- switch(hjpeg->State)
- {
- case HAL_JPEG_STATE_BUSY_ENCODING:
- case HAL_JPEG_STATE_BUSY_DECODING:
- /* continue JPEG data encoding/Decoding*/
- /* JPEG data processing : In/Out FIFO transfer*/
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
- {
- JPEG_Process(hjpeg);
- }
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
- {
- JPEG_DMA_ContinueProcess(hjpeg);
-
- }
-
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..] This section provides JPEG State and Errors function.
- (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state.
- (+) HAL_JPEG_GetError() : Returns the JPEG error code if any.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the JPEG state.
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG state
- */
-HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)
-{
- return hjpeg->State;
-}
-
-/**
-* @brief Return the JPEG error code
-* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for the specified JPEG.
-* @retval JPEG Error Code
-*/
-uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
-{
- return hjpeg->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup JPEG_Private_Functions
- * @{
- */
-
-/**
- * @brief Generates Huffman sizes/Codes Table from Bits/vals Table
- * @param Bits: pointer to bits table
- * @param Huffsize: pointer to sizes table
- * @param Huffcode: pointer to codes table
- * @param LastK: pointer to last Coeff (table dimmension)
- * @retval HAL status
- */
-static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
-{
- uint32_t i, p, l, code, si;
-
- /* Figure C.1: Generation of table of Huffman code sizes */
- p = 0;
- for (l = 0; l < 16; l++)
- {
- i = (uint32_t)Bits[l];
- if ( (p + i) > 256)
- { /* check for table overflow */
- return HAL_ERROR;
- }
- while (i != 0)
- {
- Huffsize[p++] = (uint8_t) l+1;
- i--;
- }
- }
- Huffsize[p] = 0;
- *LastK = p;
-
- /* Figure C.2: Generation of table of Huffman codes */
- code = 0;
- si = Huffsize[0];
- p = 0;
- while (Huffsize[p] != 0)
- {
- while (((uint32_t) Huffsize[p]) == si)
- {
- Huffcode[p++] = code;
- code++;
- }
- /* code must fit in "size" bits (si), no code is allowed to be all ones*/
- if (((uint32_t) code) >= (((uint32_t) 1) << si))
- {
- return HAL_ERROR;
- }
- code <<= 1;
- si++;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table
- * that can programmed to the JPEG encoder registers
- * @param AC_BitsValsTable: pointer to AC huffman bits/vals table
- * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table
- * @retval HAL status
- */
-static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
-{
- HAL_StatusTypeDef error;
- uint8_t huffsize[257];
- uint32_t huffcode[257];
- uint32_t k;
- uint32_t l,lsb, msb;
- uint32_t lastK;
-
- error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
- if(error != HAL_OK)
- {
- return error;
- }
-
- /* Figure C.3: Ordering procedure for encoding procedure code tables */
- k=0;
-
- while(k < lastK)
- {
- l = AC_BitsValsTable->HuffVal[k];
- if(l == 0)
- {
- l = 160; /*l = 0x00 EOB code*/
- }
- else if(l == 0xF0)/* l = 0xF0 ZRL code*/
- {
- l = 161;
- }
- else
- {
- msb = (l & 0xF0) >> 4;
- lsb = (l & 0x0F);
- l = (msb * 10) + lsb - 1;
- }
- if(l >= JPEG_AC_HUFF_TABLE_SIZE)
- {
- return HAL_ERROR; /* Huffman Table overflow error*/
- }
- else
- {
- AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
- AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
- k++;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table
- * that can programmed to the JPEG encoder registers
- * @param DC_BitsValsTable: pointer to DC huffman bits/vals table
- * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table
- * @retval HAL status
- */
-static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
-{
- HAL_StatusTypeDef error;
-
- uint32_t k;
- uint32_t l;
- uint32_t lastK;
- uint8_t huffsize[257];
- uint32_t huffcode[257];
- error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
- if(error != HAL_OK)
- {
- return error;
- }
- /* Figure C.3: ordering procedure for encoding procedure code tables */
- k=0;
-
- while(k < lastK)
- {
- l = DC_BitsValsTable->HuffVal[k];
- if(l >= JPEG_DC_HUFF_TABLE_SIZE)
- {
- return HAL_ERROR; /* Huffman Table overflow error*/
- }
- else
- {
- DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
- DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
- k++;
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the JPEG register with an DC huffman table at the given DC table address
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param HuffTableDC: pointer to DC huffman table
- * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
- * @retval HAL status
- */
-static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, __IO uint32_t *DCTableAddress)
-{
- HAL_StatusTypeDef error = HAL_OK;
- JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
- uint32_t i, lsb, msb;
- __IO uint32_t *address, *addressDef;
-
- if(DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
- {
- address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2));
- }
- else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1))
- {
- address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2));
- }
- else
- {
- return HAL_ERROR;
- }
-
- if(HuffTableDC != NULL)
- {
- error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);
- if(error != HAL_OK)
- {
- return error;
- }
- addressDef = address;
- *addressDef = 0x0FFF0FFF;
- addressDef++;
- *addressDef = 0x0FFF0FFF;
-
- i = JPEG_DC_HUFF_TABLE_SIZE;
- while(i>0)
- {
- i--;
- address --;
- msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
- i--;
- lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
-
- *address = lsb | (msb << 16);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the JPEG register with an AC huffman table at the given AC table address
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param HuffTableAC: pointer to AC huffman table
- * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
- * @retval HAL status
- */
-static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, __IO uint32_t *ACTableAddress)
-{
- HAL_StatusTypeDef error = HAL_OK;
- JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;
- uint32_t i, lsb, msb;
- __IO uint32_t *address, *addressDef;
-
- if(ACTableAddress == (hjpeg->Instance->HUFFENC_AC0))
- {
- address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2));
- }
- else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1))
- {
- address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2));
- }
- else
- {
- return HAL_ERROR;
- }
-
- if(HuffTableAC != NULL)
- {
- error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);
- if(error != HAL_OK)
- {
- return error;
- }
- /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */
- /* Locations 162:175 of each AC table contain information used internally by the core */
-
- addressDef = address;
- for(i=0; i<3; i++)
- {
- *addressDef = 0x0FFF0FFF;
- addressDef++;
- }
- *addressDef = 0x0FD10FD0;
- addressDef++;
- *addressDef = 0x0FD30FD2;
- addressDef++;
- *addressDef = 0x0FD50FD4;
- addressDef++;
- *addressDef = 0x0FD70FD6;
- /* end of Locations 162:175 */
-
-
- i = JPEG_AC_HUFF_TABLE_SIZE;
- while (i > 0)
- {
- i--;
- address--;
- msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
- i--;
- lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
-
- *address = lsb | (msb << 16);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the JPEG encoder register huffman tables to used during
- * the encdoing operation
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param HuffTableAC0: AC0 huffman table
- * @param HuffTableDC0: DC0 huffman table
- * @param HuffTableAC1: AC1 huffman table
- * @param HuffTableDC1: DC1 huffman table
- * @retval None
- */
-static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
-{
- HAL_StatusTypeDef error = HAL_OK;
-
- JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1);
-
- if(HuffTableAC0 != NULL)
- {
- error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (hjpeg->Instance->HUFFENC_AC0));
- if(error != HAL_OK)
- {
- return error;
- }
- }
-
- if(HuffTableAC1 != NULL)
- {
- error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (hjpeg->Instance->HUFFENC_AC1));
- if(error != HAL_OK)
- {
- return error;
- }
- }
-
- if(HuffTableDC0 != NULL)
- {
- error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, hjpeg->Instance->HUFFENC_DC0);
- if(error != HAL_OK)
- {
- return error;
- }
- }
-
- if(HuffTableDC1 != NULL)
- {
- error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, hjpeg->Instance->HUFFENC_DC1);
- if(error != HAL_OK)
- {
- return error;
- }
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the JPEG register huffman tables to be included in the JPEG
- * file header (used for encoding only)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param HuffTableAC0: AC0 huffman table
- * @param HuffTableDC0: DC0 huffman table
- * @param HuffTableAC1: AC1 huffman table
- * @param HuffTableDC1: DC1 huffman table
- * @retval None
- */
-static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
-{
- uint32_t value, index;
- __IO uint32_t *address;
- if(HuffTableDC0 != NULL)
- {
- /* DC0 Huffman Table : BITS*/
- /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
- address = (hjpeg->Instance->DHTMEM + 3);
- index = 16;
- while(index > 0)
- {
-
- *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF);
- address--;
- index -=4;
-
- }
- /* DC0 Huffman Table : Val*/
- /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
- address = (hjpeg->Instance->DHTMEM + 6);
- index = 12;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF);
- address--;
- index -=4;
- }
- }
-
- if(HuffTableAC0 != NULL)
- {
- /* AC0 Huffman Table : BITS*/
- /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
- address = (hjpeg->Instance->DHTMEM + 10);
- index = 16;
- while(index > 0)
- {
-
- *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF);
- address--;
- index -=4;
-
- }
- /* AC0 Huffman Table : Val*/
- /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
- address = (hjpeg->Instance->DHTMEM + 51);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF);
- *address = value;
-
- /*continue setting 160 AC0 huffman values */
- address--; /* address = hjpeg->Instance->DHTMEM + 50*/
- index = 160;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF);
- address--;
- index -=4;
- }
- }
-
- if(HuffTableDC1 != NULL)
- {
- /* DC1 Huffman Table : BITS*/
- /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 51);
- value = *address & 0x0000FFFFU;
- value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16);
- *address = value;
-
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 55);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF);
- *address = value;
-
- /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
- address--;
- index = 12;
- while(index > 0)
- {
-
- *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF);
- address--;
- index -=4;
-
- }
- /* DC1 Huffman Table : Val*/
- /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
- address = (hjpeg->Instance->DHTMEM + 55);
- value = *address & 0x0000FFFF;
- value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16);
- *address = value;
-
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
- address = (hjpeg->Instance->DHTMEM + 58);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF);
- *address = value;
-
- /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
- address--;
- index = 8;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF);
- address--;
- index -=4;
- }
- }
-
- if(HuffTableAC1 != NULL)
- {
- /* AC1 Huffman Table : BITS*/
- /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 58);
- value = *address & 0x0000FFFFU;
- value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16);
- *address = value;
-
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
- address = (hjpeg->Instance->DHTMEM + 62);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF);
- *address = value;
-
- /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
- address--;
- index = 12;
- while(index > 0)
- {
-
- *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF);
- address--;
- index -=4;
-
- }
- /* AC1 Huffman Table : Val*/
- /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
- address = (hjpeg->Instance->DHTMEM + 62);
- value = *address & 0x0000FFFF;
- value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16);
- *address = value;
-
- /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
- address = (hjpeg->Instance->DHTMEM + 102);
- index = 160;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF);
- address--;
- index -=4;
- }
- }
-}
-
-/**
- * @brief Configure the JPEG registers with a given quantization table
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param QTable: pointer to an array of 64 bytes giving the quantization table
- * @param QTableAddress: destination quantization address in the JPEG peripheral
- * it could be QMEM0, QMEM1, QMEM2 or QMEM3
- * @retval None
- */
-static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress)
-{
- uint32_t i, j, quantRow, quantVal, ScaleFactor;
- __IO uint32_t *tableAddress;
-
- if((QTableAddress == ((hjpeg->Instance->QMEM0))) ||
- (QTableAddress == ((hjpeg->Instance->QMEM1))) ||
- (QTableAddress == ((hjpeg->Instance->QMEM2))) ||
- (QTableAddress == ((hjpeg->Instance->QMEM3))))
- {
- tableAddress = QTableAddress;
- }
- else
- {
- return HAL_ERROR;
- }
-
- if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100))
- {
- ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2);
- }
- else if (hjpeg->Conf.ImageQuality > 0)
- {
- ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);
- }
- else
- {
- return HAL_ERROR;
- }
-
- /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/
- i = 0;
- while( i < JPEG_QUANT_TABLE_SIZE)
- {
- quantRow = 0;
- for(j=0; j<4; j++)
- {
- /* Note that the quantization coefficients must be specified in the table in zigzag order */
- quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100;
-
- if(quantVal == 0)
- {
- quantVal = 1;
- }
- else if (quantVal > 255)
- {
- quantVal = 255;
- }
-
- quantRow |= ((quantVal & 0xFF) << (8 * j));
- }
-
- i += 4;
- *tableAddress = quantRow;
- tableAddress ++;
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the JPEG registers for YCbCr color space
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t ySamplingH;
- uint32_t ySamplingV;
- uint32_t yblockNb;
-
- /*Set Number of color components to 3*/
- hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF;
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1;
-
- /* compute MCU block size and Y, Cb ,Cr sampling factors*/
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
- {
- ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
- ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/
-
- yblockNb = 0x30; /* 4 blocks of 8x8*/
- }
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
- {
- ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
- ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
-
- yblockNb = 0x10; /* 2 blocks of 8x8*/
- }
- else /*JPEG_444_SUBSAMPLING and default*/
- {
- ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/
- ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
-
- yblockNb = 0; /* 1 block of 8x8*/
- }
-
- hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
- hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
-
- /*Reset CONFR4 register*/
- hjpeg->Instance->CONFR4 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
- hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
-
- /*Reset CONFR5 register*/
- hjpeg->Instance->CONFR5 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
- hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);
-
- /*Reset CONFR6 register*/
- hjpeg->Instance->CONFR6 = 0;
- /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/
- /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */
- /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */
- hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);
-
-}
-
-/**
- * @brief Configure the JPEG registers for GrayScale color space
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)
-{
- /*Set Number of color components to 1*/
- hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
-
- /*in GrayScale use 1 single Quantization table (Table 0)*/
- /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/
-
- /*Reset CONFR4 register*/
- hjpeg->Instance->CONFR4 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
- hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;
-}
-
-/**
- * @brief Configure the JPEG registers for CMYK color space
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t ySamplingH;
- uint32_t ySamplingV;
- uint32_t yblockNb;
-
- /*Set Number of color components to 4*/
- hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);
-
- /* compute MCU block size and Y, Cb ,Cr sampling factors*/
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
- {
- ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
- ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/
-
- yblockNb = 0x30; /* 4 blocks of 8x8*/
- }
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
- {
- ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
- ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
-
- yblockNb = 0x10; /* 2 blocks of 8x8*/
- }
- else /*JPEG_444_SUBSAMPLING and default*/
- {
- ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/
- ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
-
- yblockNb = 0; /* 1 block of 8x8*/
- }
-
- /*Reset CONFR4 register*/
- hjpeg->Instance->CONFR4 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
- hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
-
- /*Reset CONFR5 register*/
- hjpeg->Instance->CONFR5 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
- hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
-
- /*Reset CONFR6 register*/
- hjpeg->Instance->CONFR6 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/
- hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
-
- /*Reset CONFR7 register*/
- hjpeg->Instance->CONFR7 = 0;
- /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/
- hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
-}
-
-/**
- * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None
- */
-static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
-{
- /*Reset pause*/
- hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));
-
- if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
- {
- /*Set JPEG Codec to Decoding mode */
- hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;
- }
- else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
- {
- /*Set JPEG Codec to Encoding mode */
- hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;
- }
-
- /*Stop JPEG processing */
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- /* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- /* Flush input and output FIFOs*/
- hjpeg->Instance->CR |= JPEG_CR_IFF;
- hjpeg->Instance->CR |= JPEG_CR_OFF;
-
- /* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
-
- /*Start Encoding/Decoding*/
- hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START;
-
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
- {
- /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/
- __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD);
- }
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
- {
- /*Enable End Of Conversation, and End Of Header parsing interruptions*/
- __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD);
-
- }
-}
-
-/**
- * @brief JPEG encoding/decoding process in case of Polling or Interrupt
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING
- */
-static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t tmpContext;
-
- /*End of header processing flag rised*/
- if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
- {
- /*Call Header parsing complet callback */
- HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
- /* Reset the ImageQuality */
- hjpeg->Conf.ImageQuality = 0;
- /* Note : the image quality is only available at the end of the decoding operation */
- /* at the current stage the calculated image quality is not correct so reset it */
-
- /*Call Info Ready callback */
- HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
-
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
-
- /* Clear header processing done flag */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
- }
-
- /*Input FIFO status handling*/
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0)
- {
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET)
- {
- /*Input FIFO threshold flag rised*/
- /*4 words (16 bytes) can be written in */
- JPEG_ReadInputData(hjpeg,JPEG_FIFO_TH_SIZE);
- }
- else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET)
- {
- /*Input FIFO Not Full flag rised*/
- /*32-bit value can be written in */
- JPEG_ReadInputData(hjpeg,1);
- }
- }
-
-
- /*Output FIFO flag handling*/
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
- {
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET)
- {
- /*Output FIFO threshold flag rised*/
- /*4 words (16 bytes) can be read out */
- JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
- }
- else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET)
- {
- /*Output FIFO Not Empty flag rised*/
- /*32-bit value can be read out */
- JPEG_StoreOutputData(hjpeg, 1);
- }
- }
-
- /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)
- {
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
- {
- /* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
- }
-
- /* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
-
- /*Call End of conversion callback */
- if(hjpeg->JpegOutCount > 0)
- {
- /*Output Buffer is not empty, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
-
- /*Reset Context Operation*/
- tmpContext = hjpeg->Context;
- /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
- hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
- {
- HAL_JPEG_DecodeCpltCallback(hjpeg);
- }
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
- {
- HAL_JPEG_EncodeCpltCallback(hjpeg);
- }
-
- return JPEG_PROCESS_DONE;
- }
-
-
- return JPEG_PROCESS_ONGOING;
-}
-
-/**
- * @brief Store some output data from the JPEG peripheral to the output buffer.
- * This function is used when the JPEG peripheral has new data to output
- * in case of Polling or Interrupt process
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral
- * @retval None
- */
-static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
-{
- uint32_t index, nBwords, nbBytes , dataword;
-
- if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4)))
- {
- for(index = 0; index < nbOutputWords; index++)
- {
- /*Transfer 32 bits from the JPEG output FIFO*/
- dataword = hjpeg->Instance->DOR;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataword & 0x000000FF;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataword & 0x0000FF00) >> 8;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataword & 0x00FF0000) >> 16;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataword & 0xFF000000) >> 24;
- hjpeg->JpegOutCount += 4;
- }
- if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
- {
- /*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
- }
- else if(hjpeg->OutDataLength > hjpeg->JpegOutCount)
- {
- nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4;
- for(index = 0; index < nBwords; index++)
- {
- /*Transfer 32 bits from the JPEG output FIFO*/
- dataword = hjpeg->Instance->DOR;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataword & 0x000000FF;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataword & 0x0000FF00) >> 8;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataword & 0x00FF0000) >> 16;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataword & 0xFF000000) >> 24;
- hjpeg->JpegOutCount += 4;
- }
- if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
- {
- /*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
- else
- {
- nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
- dataword = hjpeg->Instance->DOR;
- for(index = 0; index < nbBytes; index++)
- {
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
- hjpeg->JpegOutCount++;
- }
- /*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
-
- nbBytes = 4 - nbBytes;
- for(index = nbBytes; index < 4; index++)
- {
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
- hjpeg->JpegOutCount++;
- }
- }
- }
-}
-
-/**
- * @brief Read some input Data from the input buffer.
- * This function is used when the JPEG peripheral needs new data
- * in case of Polling or Interrupt process
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request
- * @retval None
- */
-static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
-{
- uint32_t nbBytes = 0, nBwords = 0, index = 0, Dataword = 0, inputCount = 0;
-
- if((hjpeg->InDataLength == 0) || (nbRequestWords == 0))
- {
- /* No more Input data : nothing to do*/
- HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
- }
- else if(hjpeg->InDataLength > hjpeg->JpegInCount)
- {
- nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
- }
- else if(hjpeg->InDataLength == hjpeg->JpegInCount)
- {
- /*Call HAL_JPEG_GetDataCallback to get new data */
- HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
- if(hjpeg->InDataLength > 4)
- {
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
- }
- hjpeg->JpegInCount = 0;
- nbBytes = hjpeg->InDataLength;
- }
- if((nbBytes > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0))
- {
- nBwords = nbBytes / 4;
- if(nBwords >= nbRequestWords)
- {
- for(index = 0; index < nbRequestWords; index++)
- {
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1])) << 8) |\
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2])) << 16) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3])) << 24));
-
- hjpeg->JpegInCount += 4;
- }
- }
- else /*nBwords < nbRequestWords*/
- {
- if(nBwords > 0)
- {
- for(index = 0; index < nBwords; index++)
- {
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1])) << 8) |\
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2])) << 16) | (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3])) << 24));
-
- hjpeg->JpegInCount += 4;
- }
- }
- else
- {
- /* end of file*/
- Dataword = 0;
- for(index=0; index< nbBytes; index++)
- {
- Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index);
- hjpeg->JpegInCount++;
- }
- hjpeg->Instance->DIR = Dataword;
- }
- }
- }
-}
-
-/**
- * @brief Start the JPEG DMA process (encoding/decoding)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
- */
-static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t inXfrSize, outXfrSize;
-
- /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
- then MDMA In buffer size is 32 bytes
- else (MDMA In is triggred with JPEG In FIFO not full flag)
- then MDMA In buffer size is 4 bytes
- */
- inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
-
- /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag
- then MDMA out buffer size is 32 bytes
- else (MDMA Out is triggred with JPEG Out FIFO not empty flag)
- then MDMA buffer size is 4 bytes
- */
- outXfrSize = hjpeg->hdmaout->Init.BufferTransferLength;
-
- if((hjpeg->InDataLength < inXfrSize) || (hjpeg->OutDataLength < outXfrSize))
- {
- return HAL_ERROR;
- }
- /* Set the JPEG MDMA In transfer complete callback */
- hjpeg->hdmain->XferCpltCallback = JPEG_MDMAInCpltCallback;
- /* Set the MDMA In error callback */
- hjpeg->hdmain->XferErrorCallback = JPEG_MDMAErrorCallback;
-
- /* Set the JPEG MDMA Out transfer complete callback */
- hjpeg->hdmaout->XferCpltCallback = JPEG_MDMAOutCpltCallback;
- /* Set the MDMA In error callback */
- hjpeg->hdmaout->XferErrorCallback = JPEG_MDMAErrorCallback;
- /* Set the MDMA Out Abort callback */
- hjpeg->hdmaout->XferAbortCallback = JPEG_MDMAOutAbortCallback;
-
- /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
-
- /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/
- hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % outXfrSize);
-
-
- /* Start MDMA FIFO Out transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
-
- /* Start DMA FIFO In transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
-
- return HAL_OK;
-}
-
-/**
- * @brief Continue the current JPEG DMA process (encoding/decoding)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
- */
-static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
-{
- /*End of header processing flag rises*/
- if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
- {
- /*Call Header parsing complete callback */
- HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
-
- /* Reset the ImageQuality */
- hjpeg->Conf.ImageQuality = 0;
- /* Note : the image quality is only available at the end of the decoding operation */
- /* at the current stage the calculated image quality is not correct so reset it */
-
- /*Call Info Ready callback */
- HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
-
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
-
- /* Clear header processing done flag */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
- }
-
- /*End of Conversion handling*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET)
- {
- hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;
-
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- /* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
-
-
- if(hjpeg->hdmain->State == HAL_MDMA_STATE_BUSY)
- {
- /* Stop the MDMA In Xfer*/
- HAL_MDMA_Abort_IT(hjpeg->hdmain);
- }
-
- if(hjpeg->hdmaout->State == HAL_MDMA_STATE_BUSY)
- {
- /* Stop the MDMA out Xfer*/
- HAL_MDMA_Abort_IT(hjpeg->hdmaout);
- }
- else
- {
- return JPEG_DMA_EndProcess(hjpeg);
- }
- }
-
- return JPEG_PROCESS_ONGOING;
-}
-
-/**
- * @brief Finalize the current JPEG DMA process (encoding/decoding)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG_PROCESS_DONE
- */
-static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t tmpContext;
- hjpeg->JpegOutCount = hjpeg->OutDataLength - (hjpeg->hdmaout->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
-
- /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
- {
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
-
- /*Check if remaining data in the output FIFO*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0)
- {
- if(hjpeg->JpegOutCount > 0)
- {
- /*Output Buffer is not empty, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
-
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- tmpContext = hjpeg->Context;
- /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
- hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
- {
- HAL_JPEG_DecodeCpltCallback(hjpeg);
- }
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
- {
- HAL_JPEG_EncodeCpltCallback(hjpeg);
- }
- }
- else if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
- {
- JPEG_DMA_PollResidualData(hjpeg);
-
- return JPEG_PROCESS_DONE;
- }
-
- return JPEG_PROCESS_ONGOING;
-}
-
-/**
- * @brief Poll residual output data when DMA process (encoding/decoding)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval None.
- */
-static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t tmpContext, count = JPEG_FIFO_SIZE, dataOut;
-
- while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0))
- {
- count--;
-
- dataOut = hjpeg->Instance->DOR;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = dataOut & 0x000000FF;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1] = (dataOut & 0x0000FF00) >> 8;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2] = (dataOut & 0x00FF0000) >> 16;
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3] = (dataOut & 0xFF000000) >> 24;
- hjpeg->JpegOutCount += 4;
-
- if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
- {
- /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
- }
-
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
- {
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- if(hjpeg->JpegOutCount > 0)
- {
- /*Output Buffer is not empty, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
-
- tmpContext = hjpeg->Context;
- /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
- hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
- {
- HAL_JPEG_DecodeCpltCallback(hjpeg);
- }
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
- {
- HAL_JPEG_EncodeCpltCallback(hjpeg);
- }
- }
-}
-
-/**
- * @brief DMA input transfer complete callback
- * @param hmdma: pointer to a DMA_HandleTypeDef structure.
- * @retval None
- */
-static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma)
-{
- uint32_t inXfrSize;
-
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
-
- /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
- {
-
- /*if the MDMA In is triggred with JPEG In FIFO Threshold flag
- then MDMA In buffer size is 32 bytes
- else (MDMA In is triggred with JPEG In FIFO not full flag)
- then MDMA In buffer size is 4 bytes
- */
- inXfrSize = hjpeg->hdmain->Init.BufferTransferLength;
-
- hjpeg->JpegInCount = hjpeg->InDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
-
- /*Call HAL_JPEG_GetDataCallback to get new data */
- HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
-
-
- if(hjpeg->InDataLength >= inXfrSize)
- {
- /*JPEG Input DMA transfer data number must be multiple of MDMA buffer size
- as the destination is a 32 bits register */
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize);
-
- }
- else if(hjpeg->InDataLength > 0)
- {
- /* Transfer the remaining Data, must be multiple of source data size (byte) and destination data size (word) */
- if((hjpeg->InDataLength % 4) != 0)
- {
- hjpeg->InDataLength = ((hjpeg->InDataLength / 4) + 1) * 4;
- }
- }
-
- if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0))
- {
- /* Start MDMA FIFO In transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength, 1);
- }
-
- /* JPEG Conversion still on going : Enable the JPEG IT */
- __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
- }
-}
-
-/**
- * @brief DMA output transfer complete callback
- * @param hmdma: pointer to a DMA_HandleTypeDef structure.
- * @retval None
- */
-static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma)
-{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
-
-
- /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
- {
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0)
- {
- hjpeg->JpegOutCount = hjpeg->OutDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT);
-
- /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
-
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
- {
- /* Start MDMA FIFO Out transfer */
- HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength, 1);
- }
- }
-
- /* JPEG Conversion still on going : Enable the JPEG IT */
- __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
- }
-}
-
-/**
- * @brief DMA Transfer error callback
- * @param hmdma: pointer to a DMA_HandleTypeDef structure.
- * @retval None
- */
-static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma)
-{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
-
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
-
- /* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
-
- hjpeg->State= HAL_JPEG_STATE_READY;
- hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
- HAL_JPEG_ErrorCallback(hjpeg);
-}
-
-/**
- * @brief DMA output Abort callback
- * @param hmdma: pointer to a DMA_HandleTypeDef structure.
- * @retval None
- */
-static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma)
-{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
-
- if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
- {
- JPEG_DMA_EndProcess(hjpeg);
- }
-}
-
-/**
- * @brief Calculate the decoded image quality (from 1 to 100)
- * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
- * the configuration information for JPEG module
- * @retval JPEG image quality from 1 to 100.
- */
-static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
-{
- uint32_t quality = 0;
- uint32_t quantRow, quantVal,scale, i, j;
- __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0;
-
- i = 0;
- while( i < JPEG_QUANT_TABLE_SIZE)
- {
- quantRow = *tableAddress;
- for(j=0; j<4; j++)
- {
- quantVal = (quantRow >> (8 * j)) & 0xFF;
- if(quantVal == 1)
- {
- /* if Quantization value = 1 then quality is 100%*/
- quality += 100;
- }
- else
- {
- /* Note that the quantization coefficients must be specified in the table in zigzag order */
- scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]);
-
- if(scale <= 100)
- {
- quality += (200 - scale)/2;
- }
- else
- {
- quality += 5000/scale;
- }
- }
- }
-
- i += 4;
- tableAddress ++;
- }
-
- return (quality/((uint32_t)64));
-}
-/**
- * @}
- */
-
-#endif /* HAL_JPEG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
deleted file mode 100644
index f581503..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
+++ /dev/null
@@ -1,1673 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_lptim.c
- * @author MCD Application Team
- * @brief LPTIM HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Low Power Timer (LPTIM) peripheral:
- * + Initialization and de-initialization functions.
- * + Start/Stop operation functions in polling mode.
- * + Start/Stop operation functions in interrupt mode.
- * + Reading operation functions.
- * + Peripheral State functions.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LPTIM HAL driver can be used as follows:
-
- (#)Initialize the LPTIM low level resources by implementing the
- HAL_LPTIM_MspInit():
- (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
- (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
- (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
- (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
- (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
-
- (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
- configures mainly:
- (++) The instance: LPTIM1 or LPTIM2.
- (++) Clock: the counter clock.
- (+++) Source : it can be either the ULPTIM input (IN1) or one of
- the internal clock; (APB, LSE, LSI or MSI).
- (+++) Prescaler: select the clock divider.
- (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
- as counter clock source.
- (+++) Polarity: polarity of the active edge for the counter unit
- if the ULPTIM input is selected.
- (+++) SampleTime: clock sampling time to configure the clock glitch
- filter.
- (++) Trigger: How the counter start.
- (+++) Source: trigger can be software or one of the hardware triggers.
- (+++) ActiveEdge : only for hardware trigger.
- (+++) SampleTime : trigger sampling time to configure the trigger
- glitch filter.
- (++) OutputPolarity : 2 opposite polarities are possibles.
- (++) UpdateMode: specifies whether the update of the autoreload and
- the compare values is done immediately or after the end of current
- period.
- (++) Input1Source: Source selected for input1 (GPIO or comparator output).
- (++) Input2Source: Source selected for input2 (GPIO or comparator output).
- Input2 is used only for encoder feature so is used only for LPTIM1 instance.
-
- (#)Six modes are available:
-
- (++) PWM Mode: To generate a PWM signal with specified period and pulse,
- call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
- mode.
-
- (++) One Pulse Mode: To generate pulse with specified width in response
- to a stimulus, call HAL_LPTIM_OnePulse_Start() or
- HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
-
- (++) Set once Mode: In this mode, the output changes the level (from
- low level to high level if the output polarity is configured high, else
- the opposite) when a compare match occurs. To start this mode, call
- HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
- interruption mode.
-
- (++) Encoder Mode: To use the encoder interface call
- HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
- interruption mode. Only available for LPTIM1 instance.
-
- (++) Time out Mode: an active edge on one selected trigger input rests
- the counter. The first trigger event will start the timer, any
- successive trigger event will reset the counter and the timer will
- restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
- HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
-
- (++) Counter Mode: counter can be used to count external events on
- the LPTIM Input1 or it can be used to count internal clock cycles.
- To start this mode, call HAL_LPTIM_Counter_Start() or
- HAL_LPTIM_Counter_Start_IT() for interruption mode.
-
-
- (#) User can stop any process by calling the corresponding API:
- HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
- already started in interruption mode.
-
- (#)De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup LPTIM LPTIM
- * @brief LPTIM HAL module driver.
- * @{
- */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
- * @{
- */
-
-/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the LPTIM according to the specified parameters in the
- LPTIM_InitTypeDef and initialize the associated handle.
- (+) DeInitialize the LPTIM peripheral.
- (+) Initialize the LPTIM MSP.
- (+) DeInitialize the LPTIM MSP.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the LPTIM according to the specified parameters in the
- * LPTIM_InitTypeDef and creates the associated handle.
- * @param hlptim: LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
-{
- uint32_t tmpcfgr = 0;
-
- /* Check the LPTIM handle allocation */
- if(hlptim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
- {
- assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
- }
- assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
- }
- assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
- assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
- assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
-
- if(hlptim->State == HAL_LPTIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hlptim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_LPTIM_MspInit(hlptim);
- }
-
- /* Change the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_BUSY;
-
- /* Get the LPTIMx CFGR value */
- tmpcfgr = hlptim->Instance->CFGR;
-
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
- {
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
- }
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
- }
-
- /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
- LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
-
- /* Set initialization parameters */
- tmpcfgr |= (hlptim->Init.Clock.Source |
- hlptim->Init.Clock.Prescaler |
- hlptim->Init.OutputPolarity |
- hlptim->Init.UpdateMode |
- hlptim->Init.CounterSource);
-
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
- {
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
- hlptim->Init.UltraLowPowerClock.SampleTime);
- }
-
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
- }
-
- /* Write to LPTIMx CFGR */
- hlptim->Instance->CFGR = tmpcfgr;
-
- /* Configure LPTIM input sources */
- if((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
- {
- /* Check LPTIM1/2 Input1 and Input2 sources */
- assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
- assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source));
-
- /* Configure LPTIM1/2 Input1 and Input2 sources */
- hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
- }
- else
- {
- if(hlptim->Instance == LPTIM3)
- {
- /* Check LPTIM2 Input1 source */
- assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
-
- /* Configure LPTIM2 Input1 source */
- hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
- }
- }
- /* Change the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the LPTIM peripheral.
- * @param hlptim: LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the LPTIM handle allocation */
- if(hlptim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Change the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_BUSY;
-
- /* Disable the LPTIM Peripheral Clock */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_LPTIM_MspDeInit(hlptim);
-
- /* Change the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hlptim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the LPTIM MSP.
- * @param hlptim: LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize LPTIM MSP.
- * @param hlptim: LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
- * @brief Start-Stop operation functions.
- *
-@verbatim
- ==============================================================================
- ##### LPTIM Start Stop operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start the PWM mode.
- (+) Stop the PWM mode.
- (+) Start the One pulse mode.
- (+) Stop the One pulse mode.
- (+) Start the Set once mode.
- (+) Stop the Set once mode.
- (+) Start the Encoder mode.
- (+) Stop the Encoder mode.
- (+) Start the Timeout mode.
- (+) Stop the Timeout mode.
- (+) Start the Counter mode.
- (+) Stop the Counter mode.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Reset WAVE bit to set PWM mode */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Reset WAVE bit to set PWM mode */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
- /* Enable Autoreload write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Enable Compare write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Enable Autoreload match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Enable Compare match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Enable external trigger interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Disable Autoreload write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Disable Compare write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Disable Autoreload match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Disable Compare match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Disable external trigger interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Reset WAVE bit to set one pulse mode */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_SINGLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Reset WAVE bit to set one pulse mode */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
-
- /* Enable Autoreload write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Enable Compare write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Enable Autoreload match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Enable Compare match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Enable external trigger interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_SINGLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Disable Autoreload write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Disable Compare write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Disable Autoreload match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Disable Compare match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Disable external trigger interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the LPTIM in Set once mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Set WAVE bit to enable the set once mode */
- hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_SINGLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM Set once mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Pulse));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Set WAVE bit to enable the set once mode */
- hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
-
- /* Enable Autoreload write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Enable Compare write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Enable Autoreload match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Enable Compare match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Enable external trigger interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_SINGLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Disable Autoreload write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Disable Compare write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
-
- /* Disable Autoreload match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Disable Compare match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
- {
- /* Disable external trigger interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
- }
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the Encoder interface.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpcfgr;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
- assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
- assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
-
- /* Encoder feature is only available for LPTIM1 instance */
- if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
- {
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Get the LPTIMx CFGR value */
- tmpcfgr = hlptim->Instance->CFGR;
-
- /* Clear CKPOL bits */
- tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
-
- /* Set Input polarity */
- tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
-
- /* Write to LPTIMx CFGR */
- hlptim->Instance->CFGR = tmpcfgr;
-
- /* Set ENC bit to enable the encoder interface */
- hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stop the Encoder interface.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Reset ENC bit to disable the encoder interface */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the Encoder interface in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmpcfgr;
-
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
- assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
- assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
-
- /* Encoder feature is only available for LPTIM1 instance */
- if (hlptim->Instance == LPTIM1)
- {
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Configure edge sensitivity for encoder mode */
- /* Get the LPTIMx CFGR value */
- tmpcfgr = hlptim->Instance->CFGR;
-
- /* Clear CKPOL bits */
- tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
-
- /* Set Input polarity */
- tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
-
- /* Write to LPTIMx CFGR */
- hlptim->Instance->CFGR = tmpcfgr;
-
- /* Set ENC bit to enable the encoder interface */
- hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
-
- /* Enable "switch to down direction" interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
-
- /* Enable "switch to up direction" interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Stop the Encoder interface in nterrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Reset ENC bit to disable the encoder interface */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
-
- /* Disable "switch to down direction" interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
-
- /* Disable "switch to up direction" interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the Timeout function.
- * @note The first trigger event will start the timer, any successive
- * trigger event will reset the counter and the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Timeout));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Set TIMOUT bit to enable the timeout function */
- hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the Timeout value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the Timeout function.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Reset TIMOUT bit to enable the timeout function */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the Timeout function in interrupt mode.
- * @note The first trigger event will start the timer, any successive
- * trigger event will reset the counter and the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
- assert_param(IS_LPTIM_PULSE(Timeout));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Set TIMOUT bit to enable the timeout function */
- hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
-
- /* Enable Compare match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the Timeout value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the Timeout function in interrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Reset TIMOUT bit to enable the timeout function */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
-
- /* Disable Compare match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the Counter mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
- {
- /* Check if clock is prescaled */
- assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
- /* Set clock prescaler to 0 */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
- }
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the Counter mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- assert_param(IS_LPTIM_PERIOD(Period));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
- {
- /* Check if clock is prescaled */
- assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
- /* Set clock prescaler to 0 */
- hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
- }
-
- /* Enable Autoreload write complete interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Enable Autoreload match interrupt */
- __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Enable the Peripheral */
- __HAL_LPTIM_ENABLE(hlptim);
-
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Start timer in continuous mode */
- __HAL_LPTIM_START_CONTINUOUS(hlptim);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- /* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_LPTIM_DISABLE(hlptim);
-
- /* Disable Autoreload write complete interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
-
- /* Disable Autoreload match interrupt */
- __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
- /* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
- * @brief Read operation functions.
- *
-@verbatim
- ==============================================================================
- ##### LPTIM Read operation functions #####
- ==============================================================================
-[..] This section provides LPTIM Reading functions.
- (+) Read the counter value.
- (+) Read the period (Auto-reload) value.
- (+) Read the pulse (Compare)value.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the current counter value.
- * @param hlptim: LPTIM handle
- * @retval Counter value.
- */
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- return (hlptim->Instance->CNT);
-}
-
-/**
- * @brief Return the current Autoreload (Period) value.
- * @param hlptim: LPTIM handle
- * @retval Autoreload value.
- */
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- return (hlptim->Instance->ARR);
-}
-
-/**
- * @brief Return the current Compare (Pulse) value.
- * @param hlptim: LPTIM handle
- * @retval Compare value.
- */
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
-{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
-
- return (hlptim->Instance->CMP);
-}
-
-/**
- * @}
- */
-
-
-
-/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
- * @brief LPTIM IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### LPTIM IRQ handler and callbacks #####
- ==============================================================================
-[..] This section provides LPTIM IRQ handler and callback functions called within
- the IRQ handler.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle LPTIM interrupt request.
- * @param hlptim: LPTIM handle
- * @retval None
- */
-void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
-{
- /* Compare match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
- {
- /* Clear Compare match flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
-
- /* Compare match Callback */
- HAL_LPTIM_CompareMatchCallback(hlptim);
- }
- }
-
- /* Autoreload match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
- {
- /* Clear Autoreload match flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
-
- /* Autoreload match Callback */
- HAL_LPTIM_AutoReloadMatchCallback(hlptim);
- }
- }
-
- /* Trigger detected interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
- {
- /* Clear Trigger detected flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
-
- /* Trigger detected callback */
- HAL_LPTIM_TriggerCallback(hlptim);
- }
- }
-
- /* Compare write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
- {
- /* Clear Compare write flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
-
- /* Compare write Callback */
- HAL_LPTIM_CompareWriteCallback(hlptim);
- }
- }
-
- /* Autoreload write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
- {
- /* Clear Autoreload write flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
-
- /* Autoreload write Callback */
- HAL_LPTIM_AutoReloadWriteCallback(hlptim);
- }
- }
-
- /* Direction counter changed from Down to Up interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
- {
- /* Clear Direction counter changed from Down to Up flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
-
- /* Direction counter changed from Down to Up Callback */
- HAL_LPTIM_DirectionUpCallback(hlptim);
- }
- }
-
- /* Direction counter changed from Up to Down interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
- {
- /* Clear Direction counter changed from Up to Down flag */
- __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
-
- /* Direction counter changed from Up to Down Callback */
- HAL_LPTIM_DirectionDownCallback(hlptim);
- }
- }
-}
-
-/**
- * @brief Compare match callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Autoreload match callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Trigger detected callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Compare write callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Autoreload write callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Direction counter changed from Down to Up callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Direction counter changed from Up to Down callback in non-blocking mode
- * @param hlptim : LPTIM handle
- * @retval None
- */
-__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hlptim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the LPTIM state.
- * @param hlptim: LPTIM handle
- * @retval HAL state
- */
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
-{
- /* Return LPTIM handle state */
- return hlptim->State;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
deleted file mode 100644
index 75f1fab..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
+++ /dev/null
@@ -1,1893 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_ltdc.c
- * @author MCD Application Team
- * @brief LTDC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the LTDC peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Program the required configuration through the following parameters:
- the LTDC timing, the horizontal and vertical polarity,
- the pixel clock polarity, Data Enable polarity and the LTDC background color value
- using HAL_LTDC_Init() function
-
- (#) Program the required configuration through the following parameters:
- the pixel format, the blending factors, input alpha value, the window size
- and the image size using HAL_LTDC_ConfigLayer() function for foreground
- or/and background layer.
-
- (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
- HAL_LTDC_EnableCLUT functions.
-
- (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
-
- (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
- and HAL_LTDC_EnableColorKeying functions.
-
- (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
- function
-
- (#) If needed, reconfigure and change the pixel format value, the alpha value
- value, the window size, the window position and the layer start address
- for foreground or/and background layer using respectively the following
- functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
- HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
-
- (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.
- This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
- then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload
-
- After calling the _NoReload functions to set different color/format/layer settings,
- the program can call the function HAL_LTDC_Reload To apply(Reload) these settings.
- Function HAL_LTDC_Reload can be called with the parameter ReloadType
- set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
- Function HAL_LTDC_Reload can be called with the parameter ReloadType
- set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
- this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
-
-
- (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
-
- *** LTDC HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in LTDC HAL driver.
-
- (+) __HAL_LTDC_ENABLE: Enable the LTDC.
- (+) __HAL_LTDC_DISABLE: Disable the LTDC.
- (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
- (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
- (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration.
- (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
- (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
- (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
- (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
- (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
-
- [..]
- (@) You can refer to the LTDC HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-/** @defgroup LTDC LTDC
- * @brief LTDC HAL module driver
- * @{
- */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
- * @{
- */
-
-/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the LTDC
- (+) De-initialize the LTDC
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
-{
- uint32_t tmp = 0, tmp1 = 0;
-
- /* Check the LTDC peripheral state */
- if(hltdc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check function parameters */
- assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
- assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
- assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
- assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
- assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
- assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
- assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
- assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
- assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
- assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
- assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
- assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
- assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
-
- if(hltdc->State == HAL_LTDC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hltdc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_LTDC_MspInit(hltdc);
- }
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Configure the HS, VS, DE and PC polarity */
- hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
- hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
- hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
-
- /* Set Synchronization size */
- hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
- tmp = (hltdc->Init.HorizontalSync << 16);
- hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
-
- /* Set Accumulated Back porch */
- hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
- tmp = (hltdc->Init.AccumulatedHBP << 16);
- hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
-
- /* Set Accumulated Active Width */
- hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
- tmp = (hltdc->Init.AccumulatedActiveW << 16);
- hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
-
- /* Set Total Width */
- hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
- tmp = (hltdc->Init.TotalWidth << 16);
- hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
-
- /* Set the background color value */
- tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);
- tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
- hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
- hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
-
- /* Enable the Transfer Error and FIFO underrun interrupts */
- __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
-
- /* Enable LTDC by setting LTDCEN bit */
- __HAL_LTDC_ENABLE(hltdc);
-
- /* Initialize the error code */
- hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
-
- /* Initialize the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-initialize the LTDC peripheral.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-
-HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
-{
- /* DeInit the low level hardware */
- HAL_LTDC_MspDeInit(hltdc);
-
- /* Initialize the error code */
- hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
-
- /* Initialize the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the LTDC MSP.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hltdc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_LTDC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief De-initialize the LTDC MSP.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hltdc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_LTDC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides function allowing to:
- (+) Handle LTDC interrupt request
-
-@endverbatim
- * @{
- */
-/**
- * @brief Handle LTDC interrupt request.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval HAL status
- */
-void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
-{
- /* Transfer Error Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
- {
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
- {
- /* Disable the transfer Error interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
-
- /* Clear the transfer error flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
-
- /* Update error code */
- hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Transfer error Callback */
- HAL_LTDC_ErrorCallback(hltdc);
- }
- }
- /* FIFO underrun Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
- {
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
- {
- /* Disable the FIFO underrun interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
-
- /* Clear the FIFO underrun flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
-
- /* Update error code */
- hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Transfer error Callback */
- HAL_LTDC_ErrorCallback(hltdc);
- }
- }
- /* Line Interrupt management ************************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
- {
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
- {
- /* Disable the Line interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
-
- /* Clear the Line interrupt flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Line interrupt Callback */
- HAL_LTDC_LineEventCallback(hltdc);
- }
- }
- /* Register reload Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)
- {
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)
- {
- /* Disable the register reload interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
-
- /* Clear the register reload flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Register reload interrupt Callback */
- HAL_LTDC_ReloadEventCallback(hltdc);
- }
- }
-}
-
-/**
- * @brief Error LTDC callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hltdc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_LTDC_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Line Event callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hltdc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_LTDC_LineEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Reload Event callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval None
- */
-__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hltdc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the LTDC foreground or/and background parameters.
- (+) Set the active layer.
- (+) Configure the color keying.
- (+) Configure the C-LUT.
- (+) Enable / Disable the color keying.
- (+) Enable / Disable the C-LUT.
- (+) Update the layer position.
- (+) Update the layer size.
- (+) Update pixel format on the fly.
- (+) Update transparency on the fly.
- (+) Update address on the fly.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the LTDC Layer according to the specified
- * parameters in the LTDC_InitTypeDef and create the associated handle.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
- * the configuration information for the Layer.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
- assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
- assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
- assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
- assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
- assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
- assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
- assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Copy new layer configuration into handle structure */
- hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
-
- /* Configure the LTDC Layer */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Initialize the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param RGBValue the color key value
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Configure the default color values */
- LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
- LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Load the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param pCLUT pointer to the color lookup table address.
- * @param CLUTSize the color lookup table size.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
-{
- uint32_t tmp = 0;
- uint32_t counter = 0;
- uint32_t pcounter = 0;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- for(counter = 0; (counter < CLUTSize); counter++)
- {
- if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
- {
- tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
- }
- else
- {
- tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
- }
- pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
- pCLUT = (uint32_t *)pcounter;
-
- /* Specifies the C-LUT address and RGB value */
- LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
- }
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Enable LTDC color keying by setting COLKEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable LTDC color keying by setting COLKEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Enable LTDC color lookup table by setting CLUTEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable LTDC color lookup table by setting CLUTEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable Dither.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
-{
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Enable Dither by setting DTEN bit */
- LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable Dither.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
-{
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable Dither by setting DTEN bit */
- LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the LTDC window size.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param XSize LTDC Pixel per line
- * @param YSize LTDC Line number
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters (Layers parameters)*/
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_CFBLL(XSize));
- assert_param(IS_LTDC_CFBLNBR(YSize));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* update horizontal stop */
- pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
-
- /* update vertical stop */
- pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
-
- /* Reconfigures the color frame buffer pitch in byte */
- pLayerCfg->ImageWidth = XSize;
-
- /* Reconfigures the frame buffer line number */
- pLayerCfg->ImageHeight = YSize;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the LTDC window position.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param X0 LTDC window X offset
- * @param Y0 LTDC window Y offset
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_CFBLL(X0));
- assert_param(IS_LTDC_CFBLNBR(Y0));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* update horizontal start/stop */
- pLayerCfg->WindowX0 = X0;
- pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
-
- /* update vertical start/stop */
- pLayerCfg->WindowY0 = Y0;
- pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reconfigure the pixel format.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Pixelformat new pixel format value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the pixel format */
- pLayerCfg->PixelFormat = Pixelformat;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reconfigure the layer alpha value.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Alpha new alpha value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_ALPHA(Alpha));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the Alpha value */
- pLayerCfg->Alpha = Alpha;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-/**
- * @brief Reconfigure the frame buffer Address.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Address new address value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the Address */
- pLayerCfg->FBStartAdress = Address;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Set the Immediate Reload type */
- hltdc->Instance->SRCR = LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
- * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
- * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
- * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
-{
- uint32_t tmp = 0;
- uint32_t pitchUpdate = 0;
- uint32_t pixelFormat = 0;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* get LayerIdx used pixel format */
- pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
-
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
- {
- tmp = 4;
- }
- else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
- {
- tmp = 3;
- }
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
- {
- tmp = 2;
- }
- else
- {
- tmp = 1;
- }
-
- pitchUpdate = ((LinePitchInPixels * tmp) << 16);
-
- /* Clear previously set standard pitch */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
-
- /* Set the Reload type as immediate update of LTDC pitch configured above */
- LTDC->SRCR |= LTDC_SRCR_IMR;
-
- /* Set new line pitch value */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
-
- /* Set the Reload type as immediate update of LTDC pitch configured above */
- LTDC->SRCR |= LTDC_SRCR_IMR;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Define the position of the line interrupt.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Line Line Interrupt Position.
- * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LIPOS(Line));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable the Line interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
-
- /* Set the Line Interrupt position */
- LTDC->LIPCR = (uint32_t)Line;
-
- /* Enable the Line interrupt */
- __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reload LTDC Layers configuration.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param ReloadType This parameter can be one of the following values :
- * LTDC_RELOAD_IMMEDIATE : Immediate Reload
- * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
- * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_RELOAD(ReloadType));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Enable the Reload interrupt */
- __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
-
- /* Apply Reload type */
- hltdc->Instance->SRCR = ReloadType;
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the LTDC Layer according to the specified without reloading
- * parameters in the LTDC_InitTypeDef and create the associated handle.
- * Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
- * the configuration information for the Layer.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
- assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
- assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
- assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
- assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
- assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
- assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
- assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Copy new layer configuration into handle structure */
- hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
-
- /* Configure the LTDC Layer */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Initialize the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the LTDC window size without reloading.
- * Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param XSize LTDC Pixel per line
- * @param YSize LTDC Line number
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters (Layers parameters)*/
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_CFBLL(XSize));
- assert_param(IS_LTDC_CFBLNBR(YSize));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* update horizontal stop */
- pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
-
- /* update vertical stop */
- pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
-
- /* Reconfigures the color frame buffer pitch in byte */
- pLayerCfg->ImageWidth = XSize;
-
- /* Reconfigures the frame buffer line number */
- pLayerCfg->ImageHeight = YSize;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the LTDC window position without reloading.
- * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param X0 LTDC window X offset
- * @param Y0 LTDC window Y offset
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_CFBLL(X0));
- assert_param(IS_LTDC_CFBLNBR(Y0));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* update horizontal start/stop */
- pLayerCfg->WindowX0 = X0;
- pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
-
- /* update vertical start/stop */
- pLayerCfg->WindowY0 = Y0;
- pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reconfigure the pixel format without reloading.
- * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
- * the configuration information for the LTDC.
- * @param Pixelformat new pixel format value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the pixel format */
- pLayerCfg->PixelFormat = Pixelformat;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reconfigure the layer alpha value without reloading.
- * Variant of the function HAL_LTDC_SetAlpha without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Alpha new alpha value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_ALPHA(Alpha));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the Alpha value */
- pLayerCfg->Alpha = Alpha;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reconfigure the frame buffer Address without reloading.
- * Variant of the function HAL_LTDC_SetAddress without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Address new address value.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
-{
- LTDC_LayerCfgTypeDef *pLayerCfg;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Get layer configuration from handle structure */
- pLayerCfg = &hltdc->LayerCfg[LayerIdx];
-
- /* Reconfigure the Address */
- pLayerCfg->FBStartAdress = Address;
-
- /* Set LTDC parameters */
- LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
- * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
- * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
- * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
- * Variant of the function HAL_LTDC_SetPitch without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
-{
- uint32_t tmp = 0;
- uint32_t pitchUpdate = 0;
- uint32_t pixelFormat = 0;
-
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* get LayerIdx used pixel format */
- pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
-
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
- {
- tmp = 4;
- }
- else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
- {
- tmp = 3;
- }
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
- {
- tmp = 2;
- }
- else
- {
- tmp = 1;
- }
-
- pitchUpdate = ((LinePitchInPixels * tmp) << 16);
-
- /* Clear previously set standard pitch */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
-
- /* Set new line pitch value */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Configure the color keying without reloading.
- * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param RGBValue the color key value
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Configure the default color values */
- LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
- LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the color keying without reloading.
- * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Enable LTDC color keying by setting COLKEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the color keying without reloading.
- * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable LTDC color keying by setting COLKEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the color lookup table without reloading.
- * Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable LTDC color lookup table by setting CLUTEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the color lookup table without reloading.
- * Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values:
- * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
-{
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
- /* Disable LTDC color lookup table by setting CLUTEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
-
- /* Do not set the Immediate Reload */
-
- /* Change the LTDC state*/
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the LTDC handle state.
- (+) Get the LTDC handle error code.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the LTDC handle state.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @retval HAL state
- */
-HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
-{
- return hltdc->State;
-}
-
-/**
- * @brief Return the LTDC handle error code.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
-* @retval LTDC Error Code
-*/
-uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
-{
- return hltdc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Configures the LTDC peripheral
- * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param pLayerCfg Pointer LTDC Layer Configuration structure
- * @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
- * @retval None
- */
-static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
-{
- uint32_t tmp = 0;
- uint32_t tmp1 = 0;
- uint32_t tmp2 = 0;
-
- /* Configure the horizontal start and stop position */
- tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
- LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
-
- /* Configure the vertical start and stop position */
- tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
- LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
- LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
-
- /* Specifies the pixel format */
- LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
- LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
-
- /* Configure the default color values */
- tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
- tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
- tmp2 = (pLayerCfg->Alpha0 << 24);
- LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
- LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
-
- /* Specifies the constant alpha value */
- LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
- LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
-
- /* Specifies the blending factors */
- LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
- LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
-
- /* Configure the color frame buffer start address */
- LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
- LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
-
- if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
- {
- tmp = 4;
- }
- else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
- {
- tmp = 3;
- }
- else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
- {
- tmp = 2;
- }
- else
- {
- tmp = 1;
- }
-
- /* Configure the color frame buffer pitch in byte */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 7));
-
- /* Configure the frame buffer line number */
- LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
- LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
-
- /* Enable LTDC_Layer by setting LEN bit */
- LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c
deleted file mode 100644
index 74f16e7..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c
+++ /dev/null
@@ -1,623 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mdios.c
- * @author MCD Application Team
- * @brief MDIOS HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the MDIOS Peripheral.
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The MDIOS HAL driver can be used as follow:
-
- (#) Declare a MDIOS_HandleTypeDef handle structure.
-
- (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
- (##) Enable the MDIOS interface clock.
- (##) MDIOS pins configuration:
- (+++) Enable clocks for the MDIOS GPIOs.
- (+++) Configure the MDIOS pins as alternate function.
- (##) NVIC configuration if you need to use interrupt process:
- (+++) Configure the MDIOS interrupt priority.
- (+++) Enable the NVIC MDIOS IRQ handle.
-
- (#) Program the Port Address and the Preamble Check in the Init structure.
-
- (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
-
- (#) Perform direct slave read/write operations using the following APIs:
- (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
- (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
-
- (#) Get the Master read/write operations flags using the following APIs:
- (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
- (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
-
- (#) Clear the read/write flags using the following APIs:
- (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
- (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
-
- (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
- the MDIOS will generate an interrupt in the following cases:
- (##) a DINn register written by the Master
- (##) a DOUTn register read by the Master
- (##) an error occur
-
- (@) A callback is executed for each genereted interrupt, so the driver provide the following
- HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
- (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
- and execute the previous callbacks
-
- (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
- (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
- (GPIO, Clocks, NVIC configuration ...)
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-/** @defgroup MDIOS MDIOS
- * @brief HAL MDIOS module driver
- * @{
- */
-#ifdef HAL_MDIOS_MODULE_ENABLED
-
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
-#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
-#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
-
-#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
-#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
- * @{
- */
-
-/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the MDIOS
- (+) The following parameters can be configured:
- (++) Port Address
- (++) Preamble Check
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the MDIOS according to the specified parameters in
- * the MDIOS_InitTypeDef and creates the associated handle .
- * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
- * the configuration information for MDIOS module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
-{
- uint32_t tmpcr = 0;
-
- /* Check the MDIOS handle allocation */
- if(hmdios == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
- assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
- assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
-
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- if(hmdios->State == HAL_MDIOS_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_MDIOS_MspInit(hmdios);
- }
-
- /* Change the MDIOS state */
- hmdios->State = HAL_MDIOS_STATE_BUSY;
-
- /* Get the MDIOS CR value */
- tmpcr = hmdios->Instance->CR;
-
- /* Clear PORT_ADDRESS, DPC and EN bits */
- tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
-
- /* Set MDIOS control parametrs and enable the peripheral */
- tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\
- (hmdios->Init.PreambleCheck) | \
- (MDIOS_CR_EN));
-
- /* Write the MDIOS CR */
- hmdios->Instance->CR = tmpcr;
-
- /* Change the MDIOS state */
- hmdios->State = HAL_MDIOS_STATE_READY;
-
- /* Release Lock */
- __HAL_UNLOCK(hmdios);
-
- /* Return function status */
- return HAL_OK;
-
-}
-
-/**
- * @brief DeInitializes the MDIOS peripheral.
- * @param hmdios: MDIOS handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
-{
- /* Check the MDIOS handle allocation */
- if(hmdios == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
-
- /* Change the MDIOS state */
- hmdios->State = HAL_MDIOS_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_MDIOS_DISABLE(hmdios);
-
- /* DeInit the low level hardware */
- HAL_MDIOS_MspDeInit(hmdios);
-
- /* Change the MDIOS state */
- hmdios->State = HAL_MDIOS_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hmdios);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief MDIOS MSP Init
- * @param hmdios: mdios handle
- * @retval None
- */
- __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MDIOS_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief MDIOS MSP DeInit
- * @param hmdios: mdios handle
- * @retval None
- */
- __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MDIOS_MspDeInit can be implemented in the user file
- */
-}
-
-/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
- * @brief MDIOS Read/Write functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the MDIOS
- read and write operations.
-
- (#) APIs that allow to the MDIOS to read/write from/to the
- values of one of the DINn/DOUTn registers:
- (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
- (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
-
- (#) APIs that provide if there are some Slave registres have been
- read or written by the Master:
- (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
- (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
-
- (#) APIs that Clear the read/write flags:
- (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
- (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
-
- (#) A set of Callbacks are provided:
- (+) HAL_MDIOS_WriteCpltCallback()
- (+) HAL_MDIOS_ReadCpltCallback()
- (+) HAL_MDIOS_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes to an MDIOS output register
- * @param hmdios: mdios handle
- * @param RegNum: MDIOS output register address
- * @param Data: Data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
-{
- uint32_t tmpreg;
-
- /* Check the parameters */
- assert_param(IS_MDIOS_REGISTER(RegNum));
-
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- /* Get the addr of output register to be written by the MDIOS */
- tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);
-
- /* Write to DOUTn register */
- *((uint32_t *)tmpreg) = Data;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdios);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads an MDIOS input register
- * @param hmdios: mdios handle
- * @param RegNum: MDIOS input register address
- * @param pData: pointer to Data
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
-{
- uint32_t tmpreg;
-
- /* Check the parameters */
- assert_param(IS_MDIOS_REGISTER(RegNum));
-
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- /* Get the addr of input register to be read by the MDIOS */
- tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);
-
- /* Read DINn register */
- *pData = (uint16_t)(*((uint32_t *)tmpreg));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdios);
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets Written registers by MDIO master
- * @param hmdios: mdios handle
- * @retval bit map of written registers addresses
- */
-uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
-{
- return hmdios->Instance->WRFR;
-}
-
-/**
- * @brief Gets Read registers by MDIO master
- * @param hmdios: mdios handle
- * @retval bit map of read registers addresses
- */
-uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
-{
- return hmdios->Instance->RDFR;
-}
-
-/**
- * @brief Clears Write registers flag
- * @param hmdios: mdios handle
- * @param RegNum: registers addresses to be cleared
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
-{
- /* Check the parameters */
- assert_param(IS_MDIOS_REGISTER(RegNum));
-
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- /* Clear write registers flags */
- hmdios->Instance->CWRFR |= (RegNum);
-
- /* Release Lock */
- __HAL_UNLOCK(hmdios);
-
- return HAL_OK;
-}
-
-/**
- * @brief Clears Read register flag
- * @param hmdios: mdios handle
- * @param RegNum: registers addresses to be cleared
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
-{
- /* Check the parameters */
- assert_param(IS_MDIOS_REGISTER(RegNum));
-
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- /* Clear read registers flags */
- hmdios->Instance->CRDFR |= (RegNum);
-
- /* Release Lock */
- __HAL_UNLOCK(hmdios);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables Events for MDIOS peripheral
- * @param hmdios: mdios handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
-{
- /* Process Locked */
- __HAL_LOCK(hmdios);
-
- /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
- __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdios);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles MDIOS interrupt request.
- * @param hmdios: MDIOS handle
- * @retval None
- */
-void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
-{
- /* Write Register Interrupt enabled ? */
- if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)
- {
- /* Write register flag */
- if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)
- {
- /* Write callback function */
- HAL_MDIOS_WriteCpltCallback(hmdios);
-
- /* Clear write register flag */
- HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
- }
- }
-
- /* Read Register Interrupt enabled ? */
- if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)
- {
- /* Read register flag */
- if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)
- {
- /* Read callback function */
- HAL_MDIOS_ReadCpltCallback(hmdios);
-
- /* Clear read register flag */
- HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
- }
- }
-
- /* Error Interrupt enabled ? */
- if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)
- {
- /* All Errors Flag */
- if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)
- {
- /* Error Callback */
- HAL_MDIOS_ErrorCallback(hmdios);
-
- /* Clear errors flag */
- __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
- }
- }
- /* check MDIOS WAKEUP exti flag */
- if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
- {
- /* Clear MDIOS WAKEUP Exti pending bit */
- __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
- /* MDIOS WAKEUP interrupt user callback */
- HAL_MDIOS_WakeUpCallback(hmdios);
- }
-}
-
-/**
- * @brief Write Complete Callback
- * @param hmdios: mdios handle
- * @retval None
- */
- __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Read Complete Callback
- * @param hmdios: mdios handle
- * @retval None
- */
- __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Error Callback
- * @param hmdios: mdios handle
- * @retval None
- */
- __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MDIOS_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief MDIOS WAKEUP interrupt callback
- * @param hmdios: mdios handle
- * @retval None
- */
-__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdios);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MDIOS_WakeUpCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
- * @brief MDIOS control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the MDIOS.
- (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
- (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Gets MDIOS error flags
- * @param hmdios: mdios handle
- * @retval bit map of occured errors
- */
-uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
-{
- /* return errors flags on status register */
- return hmdios->Instance->SR;
-}
-
-/**
- * @brief Return the MDIOS HAL state
- * @param hmdios: mdios handle
- * @retval HAL state
- */
-HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
-{
- /* Return MDIOS state */
- return hmdios->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-/**
- * @}
- */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
deleted file mode 100644
index 34f883f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
+++ /dev/null
@@ -1,1906 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mdma.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Master Direct Memory Access (MDMA) peripheral:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral State and errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the MDMA Channel
- (except for internal SRAM/FLASH memories: no initialization is
- necessary) please refer to Reference manual for connection between peripherals
- and MDMA requests.
-
- (#)
- For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
- transfer request , channel priority, data endianness, Source increment, destination increment ,
- source data size, destination data size, data alignment, source Burst, destination Burst ,
- buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
- or full transfer) source and destination block address offset, mask address and data.
-
- If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
- Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
- Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
- User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
- last node of the list to the first one in order to make the list circular.
- In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
-
- -@- The initial transfer itself (node 0 corresponding to the Init).
- User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
- the connection between last node and first one.
-
- Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
- When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops),
- the linked list remains circular and node 2 becomes the first one.
- Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
-
- [..]
- (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
- transfer upon a request :
- (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
- with BufferTransferLength defined within the HAL_MDMA_Init.
- (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
- with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
- or within the current linked list node parameters.
- (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
- with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
- or within the current linked list node parameters.
- (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
- all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred.
- (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
- In this case a fixed Timeout can be configured by User depending from his application.
- (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
- when the abort ends or timeout (should not be called from an interrupt service routine).
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred. In this
- case the MDMA interrupt is configured.
- (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of MDMA handle structure).
-
- (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API returns immediately
- then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel hase effectively aborted.
- (could be called from an interrupt service routine).
-
- (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
- from the following list :
- (++) XferCpltCallback : transfer complete callback.
- (++) XferBufferCpltCallback : buffer transfer complete callback.
- (++) XferBlockCpltCallback : block transfer complete callback.
- (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
- (++) XferErrorCallback : transfer error callback.
- (++) XferAbortCallback : transfer abort complete callback.
-
- [..]
- (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
- trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
- (++) This function returns an error if used while the Transfer hase ends or not started.
- (++) If used while the current request hase not been served yet (current request transfer on going)
- this function returns an error and the new request is ignored.
-
- Generally this function should be used in conjunctions with the MDMA callbacks:
- (++) example 1:
- (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
- (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
- (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
- (+++) When the buffer transfer complete callback is asserted first buffer hase been transferred and user can ask for a new buffer transfer
- request using HAL_MDMA_GenerateSWRequest.
-
- (++) example 2:
- (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
- (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
- (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
- (+++) When the block transfer complete callback is asserted the fisrt block hase been transferred and user can ask
- for a new block transfer request using HAL_MDMA_GenerateSWRequest.
-
- [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
-
- *** MDMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in MDMA HAL driver.
-
- (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Stream.
- (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Stream.
- (+) __HAL_MDMA_GET_FLAG: Get the MDMA Stream pending flags.
- (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Stream pending flags.
- (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Stream interrupts.
- (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Stream interrupts.
- (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Stream interrupt has occurred or not.
-
- [..]
- (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
-
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup MDMA MDMA
- * @brief MDMA HAL module driver
- * @{
- */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup MDMA_Private_Constants
- * @{
- */
-#define HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */
-#define HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup MDMA_Private_Functions_Prototypes
- * @{
- */
-static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
-static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
-
-/**
- * @}
- */
-
-/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
- * @{
- */
-
-/** @addtogroup MDMA_Exported_Functions_Group1
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to :
- Initialize and de-initialize the MDMA channel.
- Register and Unregister MDMA callbacks
- [..]
- The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
- reference manual.
- The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
- HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows
- respectevely to register/unregister an MDMA callback function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the MDMA according to the specified
- * parameters in the MDMA_InitTypeDef and create the associated handle.
- * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
- assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
- assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
- assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
- assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
- assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
- assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
- assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
- assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
- assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
- assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
- assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
- assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
- assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
- assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
-
-
- /* Allocate lock resource */
- __HAL_UNLOCK(hmdma);
-
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* Disable the MDMA channel */
- __HAL_MDMA_DISABLE(hmdma);
-
- /* Check if the MDMA channel is effectively disabled */
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
- {
- /* Update error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
-
- /* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Init MDMA channel registers */
- MDMA_Init(hmdma);
-
- /* Reset the MDMA first/last linkedlist node addresses and node counter */
- hmdma->FirstLinkedListNodeAddress = 0;
- hmdma->LastLinkedListNodeAddress = 0;
- hmdma->LinkedListNodeCounter = 0;
-
- /* Initialise the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
- /* Initialize the MDMA state */
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the MDMA peripheral
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
-{
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the MDMA peripheral state */
- if(hmdma->State == HAL_MDMA_STATE_BUSY)
- {
- hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
- return HAL_ERROR;
- }
-
- /* Disable the selected MDMA Channelx */
- __HAL_MDMA_DISABLE(hmdma);
-
- /* Reset MDMA Channel control register */
- hmdma->Instance->CCR = 0;
- hmdma->Instance->CTCR = 0;
- hmdma->Instance->CBNDTR = 0;
- hmdma->Instance->CSAR = 0;
- hmdma->Instance->CDAR = 0;
- hmdma->Instance->CBRUR = 0;
- hmdma->Instance->CLAR = 0;
- hmdma->Instance->CTBR = 0;
- hmdma->Instance->CMAR = 0;
- hmdma->Instance->CMDR = 0;
-
- /* Clear all flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
-
- /* Reset the MDMA first/last linkedlist node addresses and node counter */
- hmdma->FirstLinkedListNodeAddress = 0;
- hmdma->LastLinkedListNodeAddress = 0;
- hmdma->LinkedListNodeCounter = 0;
-
- /* Initialise the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
- /* Initialize the MDMA state */
- hmdma->State = HAL_MDMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hmdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Config the Post request Mask address and Mask data
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
- * @param MaskData: specifies the value to be written to MaskAddress after a request is served.
- * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* if HW request set Post Request MaskAddress and MaskData, */
- if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0)
- {
- /* Set the HW request clear Mask and Data */
- hmdma->Instance->CMAR = MaskAddress;
- hmdma->Instance->CMDR = MaskData;
-
- /*
- -If the request is done by SW : BWM could be set to 1 or 0.
- -If the request is done by a peripheral :
- If mask address not set (0) => BWM must be set to 0
- If mask address set (different than 0) => BWM could be set to 1 or 0
- */
- if(MaskAddress == 0)
- {
- hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM;
- }
- else
- {
- hmdma->Instance->CTCR |= MDMA_CTCR_BWM;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- /* Release Lock */
- __HAL_UNLOCK(hmdma);
-
- return status;
-}
-
-/**
- * @brief Register callbacks
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param CallbackID: User Callback identifier
- * @param pCallback: pointer to callbacsk function.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- switch (CallbackID)
- {
- case HAL_MDMA_XFER_CPLT_CB_ID:
- hmdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
- hmdma->XferBufferCpltCallback = pCallback;
- break;
-
- case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
- hmdma->XferBlockCpltCallback = pCallback;
- break;
-
- case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
- hmdma->XferRepeatBlockCpltCallback = pCallback;
- break;
-
- case HAL_MDMA_XFER_ERROR_CB_ID:
- hmdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_MDMA_XFER_ABORT_CB_ID:
- hmdma->XferAbortCallback = pCallback;
- break;
-
- default:
- break;
- }
- }
- else
- {
- /* Return error status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hmdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param CallbackID: User Callback identifier
- * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- switch (CallbackID)
- {
- case HAL_MDMA_XFER_CPLT_CB_ID:
- hmdma->XferCpltCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
- hmdma->XferBufferCpltCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
- hmdma->XferBlockCpltCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
- hmdma->XferRepeatBlockCpltCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_ERROR_CB_ID:
- hmdma->XferErrorCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_ABORT_CB_ID:
- hmdma->XferAbortCallback = NULL;
- break;
-
- case HAL_MDMA_XFER_ALL_CB_ID:
- hmdma->XferCpltCallback = NULL;
- hmdma->XferBufferCpltCallback = NULL;
- hmdma->XferBlockCpltCallback = NULL;
- hmdma->XferRepeatBlockCpltCallback = NULL;
- hmdma->XferErrorCallback = NULL;
- hmdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hmdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup MDMA_Exported_Functions_Group2
- *
-@verbatim
- ===============================================================================
- ##### Linked list operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Create a linked list node
- (+) Add a node to the MDMA linked list
- (+) Remove a node from the MDMA linked list
- (+) Enable/Disable linked list circular mode
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes an MDMA Link Node according to the specified
- * parameters in the pMDMA_LinkedListNodeConfig .
- * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
- * registers configurations.
- * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
- * the configuration information for the specified MDMA Linked List Node.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
-{
- uint32_t addressMask = 0;
- uint32_t blockoffset = 0;
-
- /* Check the MDMA peripheral state */
- if((pNode == NULL) || (pNodeConfig == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
- assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
- assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
- assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
- assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
- assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
- assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
- assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
- assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
- assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
- assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
- assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
- assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
- assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
-
- assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
-
-
- /*configure next Link node Address Register to zero */
- pNode->CLAR = 0;
-
- /*Configure the Link Node registers*/
- pNode->CTBR = 0;
- pNode->CMAR = 0;
- pNode->CMDR = 0;
- pNode->Reserved = 0;
-
- /* write new CTCR Register value */
- pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
- pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \
- pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \
- pNodeConfig->Init.DestBurst | \
- ((pNodeConfig->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
- pNodeConfig->Init.TransferTriggerMode;
-
- /* If SW request set the CTCR register to SW Request Mode*/
- if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
- {
- pNode->CTCR |= MDMA_CTCR_SWRM;
- }
-
- /*
- -If the request is done by SW : BWM could be set to 1 or 0.
- -If the request is done by a peripheral :
- If mask address not set (0) => BWM must be set to 0
- If mask address set (different than 0) => BWM could be set to 1 or 0
- */
- if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0))
- {
- pNode->CTCR |= MDMA_CTCR_BWM;
- }
-
- /* Set the new CBNDTR Register value */
- pNode->CBNDTR = ((pNodeConfig->BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC;
-
- /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
- if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
- {
- pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
- /*write new CBRUR Register value : source repeat block offset */
- blockoffset = (-1 * pNodeConfig->Init.SourceBlockAddressOffset);
- pNode->CBRUR = blockoffset & 0x0000FFFFU;
- }
- else
- {
- /*write new CBRUR Register value : source repeat block offset */
- pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
- }
-
- /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
- if(pNodeConfig->Init.DestBlockAddressOffset < 0)
- {
- pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
- /*write new CBRUR Register value : destination repeat block offset */
- blockoffset = (-1 * pNodeConfig->Init.DestBlockAddressOffset);
- pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV));
- }
- else
- {
- /*write new CBRUR Register value : destination repeat block offset */
- pNode->CBRUR |= (((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
- }
-
- /* Configure MDMA Link Node data length */
- pNode->CBNDTR |= pNodeConfig->BlockDataLength;
-
- /* Configure MDMA Link Node destination address */
- pNode->CDAR = pNodeConfig->DstAddress;
-
- /* Configure MDMA Link Node Source address */
- pNode->CSAR = pNodeConfig->SrcAddress;
-
- /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
- if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
- {
- /* Set the HW request in CTBR register */
- pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
- /* Set the HW request clear Mask and Data */
- pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
- pNode->CMDR = pNodeConfig->PostRequestMaskData;
- }
-
- addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
- if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
- {
- /*The AHBSbus is used as source (read operation) on channel x */
- pNode->CTBR |= MDMA_CTBR_SBUS;
- }
-
- addressMask = pNodeConfig->DstAddress & 0xFF000000U;
- if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
- {
- /*The AHB bus is used as destination (write operation) on channel x */
- pNode->CTBR |= MDMA_CTBR_DBUS;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Connect a node to the linked list.
- * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
- * to be add to the list.
- * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
- * at the end of the list
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
-{
- MDMA_LinkNodeTypeDef *pNode = 0;
- uint32_t counter = 0, nodeInserted = 0;
- HAL_StatusTypeDef hal_status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if((hmdma == NULL) || (pNewNode == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* Check if this is the first node (after the Inititlization node) */
- if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0)
- {
- if(pPrevNode == NULL)
- {
- /* if this is the first node after the initialization
- connect this node to the node 0 by updating
- the MDMA channel CLAR register to this node address */
- hmdma->Instance->CLAR = (uint32_t)pNewNode;
- /* Set the MDMA handle First linked List node*/
- hmdma->FirstLinkedListNodeAddress = pNewNode;
-
- /*reset New node link */
- pNewNode->CLAR = 0;
-
- /* Update the Handle last node address */
- hmdma->LastLinkedListNodeAddress = pNewNode;
-
- hmdma->LinkedListNodeCounter = 1;
- }
- else
- {
- hal_status = HAL_ERROR;
- }
- }
- else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
- {
- /* Check if the node to insert already exists*/
- pNode = hmdma->FirstLinkedListNodeAddress;
- while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
- {
- if(pNode->CLAR == (uint32_t)pNewNode)
- {
- hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
- }
- pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
- counter++;
- }
-
- if(hal_status == HAL_OK)
- {
- /* Check if the previous node is the last one in the current list or zero */
- if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == 0))
- {
- /* insert the new node at the end of the list. */
- pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
- hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
- /* Update the Handle last node address */
- hmdma->LastLinkedListNodeAddress = pNewNode;
- /* Increment the linked list node counter */
- hmdma->LinkedListNodeCounter++;
- }
- else
- {
- /*insert the new node after the pPreviousNode node */
- pNode = hmdma->FirstLinkedListNodeAddress;
- counter = 0;
- while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
- {
- counter++;
- if(pNode == pPrevNode)
- {
- /*Insert the new node after the previous one */
- pNewNode->CLAR = pNode->CLAR;
- pNode->CLAR = (uint32_t)pNewNode;
- /* Increment the linked list node counter */
- hmdma->LinkedListNodeCounter++;
- nodeInserted = 1;
- }
- else
- {
- pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
- }
- }
-
- if(nodeInserted == 0)
- {
- hal_status = HAL_ERROR;
- }
- }
- }
- }
- else
- {
- hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Return error status */
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disconnect/Remove a node from the transfer linked list.
- * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
- * to be removed from the list.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
-{
- MDMA_LinkNodeTypeDef *ptmpNode = 0;
- uint32_t counter = 0, nodeDeleted = 0;
- HAL_StatusTypeDef hal_status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if((hmdma == NULL) || (pNode == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* If first and last node are null (no nodes in the list) : return error*/
- if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
- {
- hal_status = HAL_ERROR;
- }
- else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
- {
- /* Delete 1st node */
- if(hmdma->LastLinkedListNodeAddress == pNode)
- {
- /*if the last node is at the same time the first one (1 single node after the init node 0)
- then update the last node too */
-
- hmdma->FirstLinkedListNodeAddress = 0;
- hmdma->LastLinkedListNodeAddress = 0;
- hmdma->LinkedListNodeCounter = 0;
-
- hmdma->Instance->CLAR = 0;
- }
- else
- {
- if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
- {
- /* if last node is looping to first (circular list) one update the last node connection */
- hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
- }
-
- /* if deleting the first node after the initialization
- connect the next node to the node 0 by updating
- the MDMA channel CLAR register to this node address */
- hmdma->Instance->CLAR = pNode->CLAR;
- hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
- /* Update the Handle node counter */
- hmdma->LinkedListNodeCounter--;
- }
- }
- else /* Deleting any other node */
- {
- /*Deleted node is not the first one : find it */
- ptmpNode = hmdma->FirstLinkedListNodeAddress;
- while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0))
- {
- counter++;
- if(ptmpNode->CLAR == ((uint32_t)pNode))
- {
- /* if deleting the last node */
- if(pNode == hmdma->LastLinkedListNodeAddress)
- {
- /*Update the linked list last node address in the handle*/
- hmdma->LastLinkedListNodeAddress = ptmpNode;
- }
- /* update the next node link after deleting pMDMA_LinkedListNode */
- ptmpNode->CLAR = pNode->CLAR;
- nodeDeleted = 1;
- /* Update the Handle node counter */
- hmdma->LinkedListNodeCounter--;
- }
- else
- {
- ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
- }
- }
-
- if(nodeDeleted == 0)
- {
- /* last node reashed without finding the node to delete : return error */
- hal_status = HAL_ERROR;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Return error status */
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Make the linked list circular by connecting the last node to the first.
- * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
-{
- HAL_StatusTypeDef hal_status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* If first and last node are null (no nodes in the list) : return error*/
- if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
- {
- hal_status = HAL_ERROR;
- }
- else
- {
- /* to enable circular mode Last Node should be connected to first node */
- hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
- }
-
- }
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
-}
-
-/**
- * @brief Disable the linked list circular mode by setting the last node connection to null
- * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
-{
- HAL_StatusTypeDef hal_status = HAL_OK;
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* If first and last node are null (no nodes in the list) : return error*/
- if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
- {
- hal_status = HAL_ERROR;
- }
- else
- {
- /* to disable circular mode Last Node should be connected to NULL */
- hmdma->LastLinkedListNodeAddress->CLAR = 0;
- }
-
- }
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- hmdma->State = HAL_MDMA_STATE_READY;
-
- return hal_status;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup MDMA_Exported_Functions_Group3
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start MDMA transfer
- (+) Configure the source, destination address and data length and
- Start MDMA transfer with interrupt
- (+) Abort MDMA transfer
- (+) Poll for transfer complete
- (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
- (+) Handle MDMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the MDMA Transfer.
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @param SrcAddress : The source memory Buffer address
- * @param DstAddress : The destination memory Buffer address
- * @param BlockDataLength : The length of a block transfer in bytes
- * @param BlockCount : The number of a blocks to be transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
-{
- /* Check the parameters */
- assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* Initialize the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_MDMA_DISABLE(hmdma);
-
- /* Configure the source, destination address and the data length */
- MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
-
-
- /* Enable the Peripheral */
- __HAL_MDMA_ENABLE(hmdma);
-
-
- if(hmdma->Init.Request == MDMA_REQUEST_SW)
- {
- /* activate If SW request mode*/
- hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Return error status */
- return HAL_BUSY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the MDMA Transfer with interrupts enabled.
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @param SrcAddress : The source memory Buffer address
- * @param DstAddress : The destination memory Buffer address
- * @param BlockDataLength : The length of a block transfer in bytes
- * @param BlockCount : The number of a blocks to be transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
-{
- /* Check the parameters */
- assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
- assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmdma);
-
- if(HAL_MDMA_STATE_READY == hmdma->State)
- {
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_BUSY;
-
- /* Initialize the error code */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_MDMA_DISABLE(hmdma);
-
- /* Configure the source, destination address and the data length */
- MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
-
- /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
-
- if(hmdma->XferBlockCpltCallback != NULL)
- {
- /* if Block transfer complete Callback is set enable the corresponding IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
- }
-
- if(hmdma->XferRepeatBlockCpltCallback != NULL)
- {
- /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
- }
-
- if(hmdma->XferBufferCpltCallback != NULL)
- {
- /* if buffer transfer complete Callback is set enable the corresponding IT*/
- __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
- }
-
- /* Enable the Peripheral */
- __HAL_MDMA_ENABLE(hmdma);
-
- if(hmdma->Init.Request == MDMA_REQUEST_SW)
- {
- /* activate If SW request mode*/
- hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Return error status */
- return HAL_BUSY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Aborts the MDMA Transfer.
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- *
- * @note After disabling a MDMA Stream, a check for wait until the MDMA Channel is
- * effectively disabled is added. If a Stream is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Stream will be effectively disabled only after the transfer of
- * this single data is finished.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if(HAL_MDMA_STATE_BUSY != hmdma->State)
- {
- hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- return HAL_ERROR;
- }
- else
- {
- /* Disable all the transfer interrupts */
- __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
-
- /* Disable the channel */
- __HAL_MDMA_DISABLE(hmdma);
-
- /* Check if the MDMA Channel is effectively disabled */
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0)
- {
- /* Check for the Timeout */
- if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
- {
- /* Update error code */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change the MDMA state */
- hmdma->State = HAL_MDMA_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- /* Clear all interrupt flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change the MDMA state*/
- hmdma->State = HAL_MDMA_STATE_READY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Aborts the MDMA Transfer in Interrupt mode.
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
-{
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if(HAL_MDMA_STATE_BUSY != hmdma->State)
- {
- hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
- return HAL_ERROR;
- }
- else
- {
- /* Set Abort State */
- hmdma->State = HAL_MDMA_STATE_ABORT;
-
- /* Disable the stream */
- __HAL_MDMA_DISABLE(hmdma);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Channel.
- * @param CompleteLevel: Specifies the MDMA level complete.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
- uint32_t levelFlag = 0, errorFlag = 0;
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
-
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if(HAL_MDMA_STATE_BUSY != hmdma->State)
- {
- /* No transfer ongoing */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
-
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC :\
- (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC :\
- (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT :\
- MDMA_FLAG_BRT);
-
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == RESET)
- {
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
- {
- /* Get the transfer error source flag */
- errorFlag = hmdma->Instance->CESR;
-
- if((errorFlag & MDMA_CESR_TED) == 0)
- {
- /* Update error code : Read Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
- }
- else
- {
- /* Update error code : Write Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
- }
-
- if((errorFlag & MDMA_CESR_TEMD) != 0)
- {
- /* Update error code : Error Mask Data */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
- }
-
- if((errorFlag & MDMA_CESR_TELD) != 0)
- {
- /* Update error code : Error Linked list */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
- }
-
- if((errorFlag & MDMA_CESR_ASE) != 0)
- {
- /* Update error code : Address/Size alignment error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
- }
-
- if((errorFlag & MDMA_CESR_BSE) != 0)
- {
- /* Update error code : Block Size error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
- }
-
- HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
-
- /*
- Note that the Abort function will
- - Clear the transfer error flags
- - Unlock
- - Set the State
- */
-
- return HAL_ERROR;
-
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update error code */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
-
- HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
-
- /*
- Note that the Abort function will
- - Clear the transfer error flags
- - Unlock
- - Set the State
- */
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Clear the transfer level flag */
- if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
- {
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
-
- }
- else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
- {
- __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
-
- }
- else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
- {
- __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
- }
- else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
- {
- __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
-
- /* Process unlocked */
- __HAL_UNLOCK(hmdma);
-
- hmdma->State = HAL_MDMA_STATE_READY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Generate an MDMA SW request trigger to activate the request on the given Channel.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
-{
- /* Check the MDMA peripheral handle */
- if(hmdma == NULL)
- {
- return HAL_ERROR;
- }
-
- if((hmdma->Instance->CCR & MDMA_CCR_EN) == RESET)
- {
- /* if no Transfer on going (MDMA enable bit not set) retrun error */
- hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
- return HAL_ERROR;
- }
- else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != RESET) || ((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == RESET))
- {
- /* if an MDMA ongoing request hase not yet ends or if request mode is not SW request retrun error */
- hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
- return HAL_ERROR;
- }
- else
- {
- /* Set the SW request bit to activate the request on the Channel */
- hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Handles MDMA interrupt request.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval None
- */
-void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
-{
- __IO uint32_t count = 0;
- uint32_t timeout = SystemCoreClock / 9600;
-
- uint32_t generalIntFlag, errorFlag;
-
- /* General Interrupt Flag management ****************************************/
- generalIntFlag = 1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
- if((MDMA->GISR0 & generalIntFlag) == RESET)
- {
- return; /* the General interrupt flag for the current channel is down , nothing to do */
- }
-
- /* Transfer Error Interrupt management ***************************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
- {
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != RESET)
- {
- /* Disable the transfer error interrupt */
- __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
-
- /* Get the transfer error source flag */
- errorFlag = hmdma->Instance->CESR;
-
- if((errorFlag & MDMA_CESR_TED) == 0)
- {
- /* Update error code : Read Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
- }
- else
- {
- /* Update error code : Write Transfer error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
- }
-
- if((errorFlag & MDMA_CESR_TEMD) != 0)
- {
- /* Update error code : Error Mask Data */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
- }
-
- if((errorFlag & MDMA_CESR_TELD) != 0)
- {
- /* Update error code : Error Linked list */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
- }
-
- if((errorFlag & MDMA_CESR_ASE) != 0)
- {
- /* Update error code : Address/Size alignment error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
- }
-
- if((errorFlag & MDMA_CESR_BSE) != 0)
- {
- /* Update error code : Block Size error error */
- hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
- }
-
- /* Clear the transfer error flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
- }
- }
-
- /* Buffer Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != RESET))
- {
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != RESET)
- {
- /* Clear the buffer transfer complete flag */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
-
- if(hmdma->XferBufferCpltCallback != NULL)
- {
- /* Buffer transfer callback */
- hmdma->XferBufferCpltCallback(hmdma);
- }
- }
- }
-
- /* Block Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != RESET))
- {
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != RESET)
- {
- /* Clear the block transfer complete flag */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
-
- if(hmdma->XferBlockCpltCallback != NULL)
- {
- /* Block transfer callback */
- hmdma->XferBlockCpltCallback(hmdma);
- }
- }
- }
-
- /* Repeated Block Transfer Complete Interrupt management ******************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != RESET))
- {
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != RESET)
- {
- /* Clear the repeat block transfer complete flag */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
-
- if(hmdma->XferRepeatBlockCpltCallback != NULL)
- {
- /* Repeated Block transfer callback */
- hmdma->XferRepeatBlockCpltCallback(hmdma);
- }
- }
- }
-
- /* Channel Transfer Complete Interrupt management ***********************************/
- if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != RESET))
- {
- if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != RESET)
- {
- /* Disable all the transfer interrupts */
- __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
-
- if(HAL_MDMA_STATE_ABORT == hmdma->State)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change the DMA state */
- hmdma->State = HAL_MDMA_STATE_READY;
-
- if(hmdma->XferAbortCallback != NULL)
- {
- hmdma->XferAbortCallback(hmdma);
- }
- return;
-
- }
- /* Clear the Channel Transfer Complete flag */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- /* Change MDMA peripheral state */
- hmdma->State = HAL_MDMA_STATE_READY;
-
- if(hmdma->XferCpltCallback != NULL)
- {
- /* Channel Transfer Complete callback */
- hmdma->XferCpltCallback(hmdma);
- }
- }
- }
-
- /* manage error case */
- if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
- {
- hmdma->State = HAL_MDMA_STATE_ABORT;
-
- /* Disable the channel */
- __HAL_MDMA_DISABLE(hmdma);
-
- do
- {
- if (++count > timeout)
- {
- break;
- }
- }
- while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hmdma);
-
- if((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
- {
- /* Change the MDMA state to error if MDMA disable fails */
- hmdma->State = HAL_MDMA_STATE_ERROR;
- }
- else
- {
- /* Change the MDMA state to Ready if MDMA disable success */
- hmdma->State = HAL_MDMA_STATE_READY;
- }
-
-
- if (hmdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hmdma->XferErrorCallback(hmdma);
- }
- }
-
-}
-
-/**
- * @}
- */
-
-/** @addtogroup MDMA_Exported_Functions_Group4
- *
-@verbatim
- ===============================================================================
- ##### State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the MDMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the MDMA state.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval HAL state
- */
-HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
-{
- return hmdma->State;
-}
-
-/**
- * @brief Return the MDMA error code
- * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @retval MDMA Error Code
- */
-uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
-{
- return hmdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup JPEG_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the MDMA Transfer parameter.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified MDMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param BlockDataLength : The length of a block transfer in bytes
- * @param BlockCount: The number of a blocks to be transfer
- * @retval HAL status
- */
-static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
-{
- uint32_t addressMask;
- /* Configure MDMA Channel data length */
- MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
-
- /*Configure the MDMA block repeat count*/
- MODIFY_REG( hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC);
-
- /* Clear all interrupt flags */
- __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
-
- /* Configure MDMA Channel destination address */
- hmdma->Instance->CDAR = DstAddress;
-
- /* Configure MDMA Channel Source address */
- hmdma->Instance->CSAR = SrcAddress;
-
- addressMask = SrcAddress & 0xFF000000U;
- if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
- {
- /*The AHBSbus is used as source (read operation) on channel x */
- hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
- }
- else
- {
- /*The AXI bus is used as source (read operation) on channel x */
- hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
- }
-
- addressMask = DstAddress & 0xFF000000U;
- if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
- {
- /*The AHB bus is used as destination (write operation) on channel x */
- hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
- }
- else
- {
- /*The AXI bus is used as destination (write operation) on channel x */
- hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
- }
-
- /* Set the linked list rgeitser to the first node of the list */
- hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
-}
-
-static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
-{
- uint32_t blockoffset = 0;
-
- /* Prepare the MDMA Channel configuration */
- hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness;
-
- /* write new CTCR Register value */
- hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \
- hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \
- hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \
- hmdma->Init.DestBurst | \
- ((hmdma->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
- hmdma->Init.TransferTriggerMode;
-
- /* If SW request set the CTCR register to SW Request Mode*/
- if(hmdma->Init.Request == MDMA_REQUEST_SW)
- {
- /*
- -If the request is done by SW : BWM could be set to 1 or 0.
- -If the request is done by a peripheral :
- If mask address not set (0) => BWM must be set to 0
- If mask address set (different than 0) => BWM could be set to 1 or 0
- */
- hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
- }
-
- /* Reset CBNDTR Register */
- hmdma->Instance->CBNDTR = 0;
-
- /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
- if(hmdma->Init.SourceBlockAddressOffset < 0)
- {
- hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
- /*write new CBRUR Register value : source repeat block offset */
- blockoffset = (-1 * hmdma->Init.SourceBlockAddressOffset);
- hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
- }
- else
- {
- /*write new CBRUR Register value : source repeat block offset */
- hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
- }
-
- /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
- if(hmdma->Init.DestBlockAddressOffset < 0)
- {
- hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
- /*write new CBRUR Register value : destination repeat block offset */
- blockoffset = (-1 * hmdma->Init.DestBlockAddressOffset);
- hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV));
- }
- else
- {
- /*write new CBRUR Register value : destination repeat block offset */
- hmdma->Instance->CBRUR |= (((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
- }
-
- /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
- if(hmdma->Init.Request != MDMA_REQUEST_SW)
- {
- /* Set the HW request in CTRB register */
- hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
- }
- else /* SW request : reset the CTBR register */
- {
- hmdma->Instance->CTBR = 0;
- }
-
- /*Write Link Address Register*/
- hmdma->Instance->CLAR = 0;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_MDMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
deleted file mode 100644
index 24e5f04..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
+++ /dev/null
@@ -1,2753 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mmc.c
- * @author MCD Application Team
- * @brief MMC card HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (MMC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + MMC card Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_MMC_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
- examples.
- You can easily tailor this configuration according to hardware resources.
-
- [..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with MMC and eMMC cards devices.
- It is used as follows:
-
- (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
- (##) SDMMC pins configuration for MMC card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
- and according to your pin assignment;
- (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
- (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
- and __HAL_MMC_DISABLE_IT() inside the communication process.
- (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
- and __HAL_MMC_CLEAR_IT()
- (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.
-
- (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
-
-
- *** MMC Card Initialization and configuration ***
- ================================================
- [..]
- To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
- SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
- This function provide the following operations:
-
- (#) Initialize the SDMMC peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
- The MMC Card frequency (SDMMC_CK) is computed as follows:
-
- SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
-
- In initialization mode and according to the MMC Card standard,
- make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-
- This phase of initialization is done through SDMMC_Init() and
- SDMMC_PowerState_ON() SDMMC low level APIs.
-
- (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
- This phase allows the card initialization and identification
- and check the MMC Card type (Standard Capacity or High Capacity)
- The initialization flow is compatible with MMC standard.
-
- This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
- of plug-off plug-in.
-
- (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
- frequency by adjusting the "ClockDiv" field.
- In transfer mode and according to the MMC Card standard, make sure that the
- SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
-
- (#) Select the corresponding MMC Card according to the address read with the step 2.
-
- (#) Configure the MMC Card in wide bus mode: 4-bits data.
-
- *** MMC Card Read operation ***
- ==============================
- [..]
- (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
-
- (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- *** MMC Card Write operation ***
- ===============================
- [..]
- (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 byte).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- *** MMC card CID register ***
- ============================
- [..]
- (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
- Some of the CID parameters are useful for card initialization and identification.
-
- *** MMC HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in MMC HAL driver.
-
- (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
- (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
- (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
- (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
-
- [..]
- (@) You can refer to the MMC HAL driver header file for more useful macros
-
- *** Callback registration ***
- =============================================
- [..]
- The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
-
- Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
- it allows to register following callbacks:
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
- (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
- (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
- (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
- (+) MspInitCallback : MMC MspInit.
- (+) MspDeInitCallback : MMC MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
- (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
- (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
- (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
- (+) MspInitCallback : MMC MspInit.
- (+) MspDeInitCallback : MMC MspDeInit.
- This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
- By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
- and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in READY state only.
- Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
- or @ref HAL_MMC_Init function.
-
- When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup MMC MMC
- * @brief MMC HAL module driver
- * @{
- */
-
-#ifdef HAL_MMC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup MMC_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
-static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
-static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
-static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
-static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
-static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout);
-
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup MMC_Exported_Functions
- * @{
- */
-
-/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize the MMC
- card device to be ready for use.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the MMC according to the specified parameters in the
- MMC_HandleTypeDef and create the associated handle.
- * @param hmmc: Pointer to the MMC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
-{
- /* Check the MMC handle allocation */
- if(hmmc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
- assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
- assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
- assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
- assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
- assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
-
- if(hmmc->State == HAL_MMC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hmmc->Lock = HAL_UNLOCKED;
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
- hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
- hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
- hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
- hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
- hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback;
- hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback;
- hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback;
- hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback;
-
- if(hmmc->MspInitCallback == NULL)
- {
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- }
-
- /* Init the low level hardware */
- hmmc->MspInitCallback(hmmc);
-#else
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_MMC_MspInit(hmmc);
-#endif
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize the Card parameters */
- if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* Initialize the error code */
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the MMC operation */
- hmmc->Context = MMC_CONTEXT_NONE;
-
- /* Initialize the MMC state */
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the MMC Card.
- * @param hmmc: Pointer to MMC handle
- * @note This function initializes the MMC card. It could be used when a card
- re-initialization is needed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
-{
- uint32_t errorstate;
- MMC_InitTypeDef Init;
- HAL_StatusTypeDef status;
-
- /* Default SDMMC peripheral configuration for MMC card initialization */
- Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
- Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDMMC_BUS_WIDE_1B;
- Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
-
- /* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hmmc->Instance, Init);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* Set Power State to ON */
- status = SDMMC_PowerState_ON(hmmc->Instance);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* Identify card operating voltage */
- errorstate = MMC_PowerON(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- /* Card initialization */
- errorstate = MMC_InitCard(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the MMC card.
- * @param hmmc: Pointer to MMC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
-{
- /* Check the MMC handle allocation */
- if(hmmc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Set MMC power state to off */
- MMC_PowerOFF(hmmc);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- if(hmmc->MspDeInitCallback == NULL)
- {
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- }
-
- /* DeInit the low level hardware */
- hmmc->MspDeInitCallback(hmmc);
-#else
- /* De-Initialize the MSP layer */
- HAL_MMC_MspDeInit(hmmc);
-#endif
-
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_RESET;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the MMC MSP.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MMC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize MMC MSP.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MMC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the data
- transfer from/to MMC card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of MMC blocks to read
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count, data;
- uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Poll on SDMMC flags */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
- {
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = SDMMC_ReadFIFO(hmmc->Instance);
- *tempbuff = (uint8_t)(data & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
- tempbuff++;
- }
- }
-
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock read */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of MMC blocks to write
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count, data;
- uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Write block(s) in polling mode */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE))
- {
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = (uint32_t)(*tempbuff);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 8U);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 16U);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 24U);
- tempbuff++;
- (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
- }
- }
-
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock write */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Rx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pRxBuffPtr = pData;
- hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
- }
-
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
-
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pTxBuffPtr = pData;
- hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- /* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Rx
- * interrupt event.
- * @param hmmc: Pointer MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pRxBuffPtr = pData;
- hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode = errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
-
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
- hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
- hmmc->ErrorCode = errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pTxBuffPtr = pData;
- hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
-
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
- hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Erases the specified memory area of the given MMC card.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
-{
- uint32_t errorstate;
- uint32_t start_add = BlockStartAdd;
- uint32_t end_add = BlockEndAdd;
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(end_add < start_add)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(end_add > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- start_add *= 512U;
- end_add *= 512U;
- }
-
-
- /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles MMC card interrupt request.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
-{
- uint32_t errorstate;
- uint32_t context = hmmc->Context;
-
- /* Check for SDMMC interrupt flags */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
-
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
-
- if((context & MMC_CONTEXT_DMA) != 0U)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
-
- hmmc->Instance->DLEN = 0;
- hmmc->Instance->DCTRL = 0;
- hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
-
- /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode = errorstate;
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
- }
-
- if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->TxCpltCallback(hmmc);
-#else
- HAL_MMC_TxCpltCallback(hmmc);
-#endif
- }
-
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->RxCpltCallback(hmmc);
-#else
- HAL_MMC_RxCpltCallback(hmmc);
-#endif
- }
-
- hmmc->State = HAL_MMC_STATE_READY;
- }
-
- if((context & MMC_CONTEXT_IT) != 0U)
- {
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->RxCpltCallback(hmmc);
-#else
- HAL_MMC_RxCpltCallback(hmmc);
-#endif
- }
- else
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->TxCpltCallback(hmmc);
-#else
- HAL_MMC_TxCpltCallback(hmmc);
-#endif
- }
- }
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE);
-
- MMC_Write_IT(hmmc);
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF);
-
- MMC_Read_IT(hmmc);
- }
-
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL);
-
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
-
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT);
-
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DTIMEOUT);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
-
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXOVERR);
-
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_RXOVERR);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
-
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXUNDERR);
-
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_TXUNDERR);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMABTC) != RESET)
- {
- if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
- {
- /* Current buffer is buffer0, Transfer complete for buffer1 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->Write_DMADblBuf1CpltCallback(hmmc);
-#else
- HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(hmmc);
-#endif
- }
- else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->Read_DMADblBuf1CpltCallback(hmmc);
-#else
- HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(hmmc);
-#endif
- }
- }
- else /* MMC_DMA_BUFFER1 */
- {
- /* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->Write_DMADblBuf0CpltCallback(hmmc);
-#else
- HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(hmmc);
-#endif
- }
- else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->Read_DMADblBuf0CpltCallback(hmmc);
-#else
- HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(hmmc);
-#endif
- }
- }
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
- }
-
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief return the MMC state
- * @param hmmc: Pointer to mmc handle
- * @retval HAL state
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
-{
- return hmmc->State;
-}
-
-/**
-* @brief Return the MMC error code
-* @param hmmc : pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
-* @retval MMC Error Code
-*/
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
-{
- return hmmc->ErrorCode;
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief MMC error callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief MMC Abort callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
-}
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/**
- * @brief Register a User MMC Callback
- * To be used instead of the weak (surcharged) predefined callback
- * @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be registered
- * This parameter can be one of the following values:
- * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
- * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
- * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
- * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID
- * @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID
- * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
- * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
- * @param pCallback : pointer to the Callback function
- * @retval status
- */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(pCallback == NULL)
- {
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hmmc);
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- switch (CallbackId)
- {
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = pCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = pCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = pCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hmmc->State == HAL_MMC_STATE_RESET)
- {
- switch (CallbackId)
- {
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hmmc);
- return status;
-}
-
-/**
- * @brief Unregister a User MMC Callback
- * MMC Callback is redirected to the weak (surcharged) predefined callback
- * @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be unregistered
- * This parameter can be one of the following values:
- * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
- * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
- * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
- * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID
- * @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID
- * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID
- * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
- * @retval status
- */
-HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hmmc);
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- switch (CallbackId)
- {
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else if (hmmc->State == HAL_MMC_STATE_RESET)
- {
- switch (CallbackId)
- {
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hmmc);
- return status;
-}
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the MMC card
- operations and get the related information
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CID register.
- * @param hmmc: Pointer to MMC handle
- * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
- * contains all CID register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
-{
- pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
-
- pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
-
- pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
-
- pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
-
- pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
-
- pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
-
- pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
-
- pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
-
- pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
-
- pCID->Reserved2 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CSD register.
- * @param hmmc: Pointer to MMC handle
- * @param pCSD: Pointer to a HAL_MMC_CardInfoTypedef structure that
- * contains all CSD register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
-{
- uint32_t block_nbr = 0;
-
- pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
-
- pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
-
- pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
-
- pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
-
- pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
-
- pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
-
- pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
-
- pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
-
- pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
-
- pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
-
- pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
-
- pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
-
- pCSD->Reserved2 = 0U; /*!< Reserved */
-
- if(MMC_ReadExtCSD(hmmc, &block_nbr, 0x0FFFFFFFU) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
- {
- pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
-
- pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
-
- pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
-
- pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
-
- pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
-
- pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
-
- hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
- hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
-
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
- hmmc->MmcCard.LogBlockSize = 512U;
- }
- else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
- {
- hmmc->MmcCard.BlockNbr = block_nbr;
- hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
- hmmc->MmcCard.BlockSize = 512U;
- hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
- }
- else
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
-
- pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
-
- pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
-
- pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
-
- pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
-
- pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
-
- pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
-
- pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
-
- pCSD->Reserved3 = 0;
-
- pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
-
- pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
-
- pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
-
- pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
-
- pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
-
- pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
-
- pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
-
- pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
-
- pCSD->Reserved4 = 1;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the MMC card info.
- * @param hmmc: Pointer to MMC handle
- * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
- * will contain the MMC card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
-{
- pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
- pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
- pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
- pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
- pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
- pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
- pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables wide bus operation for the requested card if supported by
- * card.
- * @param hmmc: Pointer to MMC handle
- * @param WideMode: Specifies the MMC card wide bus mode
- * This parameter can be one of the following values:
- * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
- * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
- * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
-{
- __IO uint32_t count = 0;
- SDMMC_InitTypeDef Init;
- uint32_t errorstate;
- uint32_t response = 0, busy = 0;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_BUS_WIDE(WideMode));
-
- /* Chnage Satte */
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- if(WideMode == SDMMC_BUS_WIDE_8B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else if(WideMode == SDMMC_BUS_WIDE_4B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else if(WideMode == SDMMC_BUS_WIDE_1B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, SDMMC_BUS_WIDE_1B /*0x03B70000*/);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else
- {
- /* WideMode is not a valid argument*/
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- }
-/* Check for switch error and violation of the trial number of sending CMD 13 */
- while(busy == 0U)
- {
- if(count == SDMMC_MAX_TRIAL)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
- }
- count++;
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- busy = (((response >> 7U) == 1U) ? 0U : 1U);
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_DATATIMEOUT;
- while((response & 0x00000100U) == 0U)
- {
- if(count == 0U)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
- }
- count--;
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- }
-
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
- }
-
- /* Change State */
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the current mmc card data state.
- * @param hmmc: pointer to MMC handle
- * @retval Card state
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
-{
- uint32_t cardstate;
- uint32_t errorstate;
- uint32_t resp1 = 0;
-
- errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- cardstate = ((resp1 >> 9U) & 0x0FU);
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(hmmc->Instance, SDMMC_STATIC_FLAGS);
- return (HAL_MMC_CardStateTypeDef)cardstate;
-}
-
-/**
- * @brief Abort the current transfer and disable the MMC.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information for MMC module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- /* If IDMA Context, disable Internal DMA */
- hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
- hmmc->State = HAL_MMC_STATE_READY;
- CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
- }
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information for MMC module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- CardState = HAL_MMC_GetCardState(hmmc);
- hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
- }
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
- {
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- hmmc->AbortCpltCallback(hmmc);
-#else
- HAL_MMC_AbortCallback(hmmc);
-#endif
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup MMC_Private_Functions
- * @{
- */
-
-
-/**
- * @brief Initializes the mmc card.
- * @param hmmc: Pointer to MMC handle
- * @retval MMC Card error state
- */
-static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardCSDTypeDef CSD;
- uint32_t errorstate;
- uint16_t mmc_rca = 1;
- MMC_InitTypeDef Init;
-
- /* Check the power State */
- if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
- {
- /* Power off */
- return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- /* Send CMD2 ALL_SEND_CID */
- errorstate = SDMMC_CmdSendCID(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card identification number data */
- hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
- hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
- hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
- }
-
- /* Send CMD3 SET_REL_ADDR with argument 0 */
- /* MMC Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get the MMC card RCA */
- hmmc->MmcCard.RelCardAdd = mmc_rca;
-
- /* Send CMD9 SEND_CSD with argument as card's RCA */
- errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card Specific Data */
- hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
- hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
- hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
- }
-
- /* Get the Card Class */
- hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20);
-
- /* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get CSD parameters */
- if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
- {
- return hmmc->ErrorCode;
- }
-
- //////////////////////////////////////////////
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = SDMMC_BUS_WIDE_1B;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
- /////////////////////////////////////
-
- /* Configure SDMMC peripheral interface */
- //SDMMC_Init(hmmc->Instance, hmmc->Init);
-
- /* All cards are initialized */
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Enquires cards about their operating voltage and configures clock
- * controls and stores MMC information that will be needed in future
- * in the MMC handle.
- * @param hmmc: Pointer to MMC handle
- * @retval error state
- */
-static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
-{
- __IO uint32_t count = 0;
- uint32_t response = 0, validvoltage = 0;
- uint32_t errorstate;
-
- /* CMD0: GO_IDLE_STATE */
- errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- while(validvoltage == 0U)
- {
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_MMC_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
- errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
- }
-
- /* When power routine is finished and command returns valid voltage */
- if (((response & (0xFF000000U)) >> 24) == 0xC0U)
- {
- hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
- }
- else
- {
- hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
- }
-
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Turns the SDMMC output signals off.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
-{
- /* Set Power State to OFF */
- (void)SDMMC_PowerState_OFF(hmmc->Instance);
-}
-
-
-/**
- * @brief Returns the current card's status.
- * @param hmmc: pointer to MMC handle
- * @param pCardStatus: pointer to the buffer that will contain the MMC card
- * status (Card Status register)
- * @retval error state
- */
-static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
-{
- uint32_t errorstate;
-
- if(pCardStatus == NULL)
- {
- return HAL_MMC_ERROR_PARAM;
- }
-
- /* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get MMC card status */
- *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Reads extended CSD register to get the sectors number of the device
- * @param hmmc: Pointer to MMC handle
- * @param pBlockNbr: Pointer to the read buffer
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count;
- uint32_t i = 0;
- uint32_t tmp_data;
-
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 0;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 512;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Poll on SDMMC flags */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
- {
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
- if ((i == 48U) && (count == 5U))
- {
- *pBlockNbr = tmp_data;
- }
- }
- i += 8U;
- }
-
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Wrap up reading in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
- * @retval None
- */
-static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
-{
- uint32_t count, data;
- uint8_t* tmp;
-
- tmp = hmmc->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = SDMMC_ReadFIFO(hmmc->Instance);
- *tmp = (uint8_t)(data & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 8U) & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 16U) & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 24U) & 0xFFU);
- tmp++;
- }
-
- hmmc->pRxBuffPtr = tmp;
-}
-
-/**
- * @brief Wrap up writing in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
- * @retval None
- */
-static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
-{
- uint32_t count, data;
- uint8_t* tmp;
-
- tmp = hmmc->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = (uint32_t)(*tmp);
- tmp++;
- data |= ((uint32_t)(*tmp) << 8U);
- tmp++;
- data |= ((uint32_t)(*tmp) << 16U);
- tmp++;
- data |= ((uint32_t)(*tmp) << 24U);
- tmp++;
- (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
- }
-
- hmmc->pTxBuffPtr = tmp;
-}
-
-/**
- * @brief Read DMA Buffer 0 Transfer completed callbacks
- * @param hmmc: MMC handle
- * @retval None
- */
-__weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Read DMA Buffer 1 Transfer completed callbacks
- * @param hmmc: MMC handle
- * @retval None
- */
-__weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Write DMA Buffer 0 Transfer completed callbacks
- * @param hmmc: MMC handle
- * @retval None
- */
-__weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Write DMA Buffer 1 Transfer completed callbacks
- * @param hmmc: MMC handle
- * @retval None
- */
-__weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c
deleted file mode 100644
index fea2174..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_mmc_ex.c
- * @author MCD Application Team
- * @brief MMC card Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (MMC) peripheral:
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The MMC Extension HAL driver can be used as follows:
- (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
-
- (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup MMCEx MMCEx
- * @brief MMC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_MMC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup MMCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup MMCEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
-@verbatim
- ==============================================================================
- ##### Multibuffer functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to configure the multibuffer mode and start read and write
- multibuffer mode for MMC HAL driver.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
- * @param hmmc: MMC handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
- * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
-{
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
- hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
- hmmc->Instance->IDMABSIZE= (uint32_t) BufferSize;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
- * @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Total number of blocks to read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t DmaBase0_reg, DmaBase1_reg;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- DmaBase0_reg = hmmc->Instance->IDMABASE0;
- DmaBase1_reg = hmmc->Instance->IDMABASE1;
- if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
- {
- hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
-
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
-
- /* Read Blocks in DMA mode */
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
- * @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Total number of blocks to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
- uint32_t add = BlockAdd;
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- DmaBase0_reg = hmmc->Instance->IDMABASE0;
- DmaBase1_reg = hmmc->Instance->IDMABASE1;
- if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
- {
- hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0;
-
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
- {
- add *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
-
- /* Write Blocks in DMA mode */
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Change the DMA Buffer0 or Buffer1 address on the fly.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure.
- * @param Buffer: the buffer to be changed, This parameter can be one of
- * the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
- * @param pDataBuffer: The new address
- * @note The BUFFER0 address can be changed only when the current transfer use
- * BUFFER1 and the BUFFER1 address can be changed only when the current
- * transfer use BUFFER0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
-{
- if(Buffer == MMC_DMA_BUFFER0)
- {
- /* change the buffer0 address */
- hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
- }
- else
- {
- /* change the memory1 address */
- hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c
deleted file mode 100644
index 28c6408..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c
+++ /dev/null
@@ -1,1860 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_nand.c
- * @author MCD Application Team
- * @brief NAND HAL module driver.
- * This file provides a generic firmware to drive NAND memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NAND flash memories. It uses the FMC/FSMC layer functions to interface
- with NAND devices. This driver is used as follows:
-
- (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
- with control and timing parameters for both common and attribute spaces.
-
- (+) Read NAND flash memory maker and device IDs using the function
- HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NAND flash memory by read/write operations using the functions
- HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
- HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
- HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
- HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
- to read/write page(s)/spare area(s). These functions use specific device
- information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
- structure. The read/write address information is contained by the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
-
- (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
- The erase block address information is contained in the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
-
- (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
- HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
- feature or the function HAL_NAND_GetECC() to get the ECC correction code.
-
- (+) You can monitor the NAND device HAL state by calling the function
- HAL_NAND_GetState()
-
- [..]
- (@) This driver is a set of generic APIs which handle standard NAND flash operations.
- If a NAND flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-
-#ifdef HAL_NAND_MODULE_ENABLED
-
-/** @defgroup NAND NAND
- * @brief NAND HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private Constants ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NAND memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ComSpace_Timing: pointer to Common space timing structure
- * @param AttSpace_Timing: pointer to Attribute space timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
-{
- /* Check the NAND handle state */
- if(hnand == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnand->State == HAL_NAND_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnand->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspInit(hnand);
- }
-
- /* Initialize NAND control Interface */
- FMC_NAND_Init(hnand->Instance, &(hnand->Init));
-
- /* Initialize NAND common space timing Interface */
- FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
-
- /* Initialize NAND attribute space timing Interface */
- FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
-
- /* Enable the NAND device */
- __FMC_NAND_ENABLE(hnand->Instance);
-
- /* Enable FMC IP */
- __FMC_ENABLE();
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
-{
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspDeInit(hnand);
-
- /* Configure the NAND registers with their reset values */
- FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
-
- /* Reset the NAND controller state */
- hnand->State = HAL_NAND_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND MSP Init
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NAND MSP DeInit
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
-*/
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
-{
- /* Check NAND interrupt Rising edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Rising edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
- }
-
- /* Check NAND interrupt Level flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Level pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
- }
-
- /* Check NAND interrupt Falling edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Falling edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
- }
-
- /* Check NAND interrupt FIFO empty flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt FIFO empty pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
- }
-
-}
-
-/**
- * @brief NAND interrupt feature callback
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_ITCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NAND
- memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the NAND memory electronic signature
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pNAND_ID: NAND ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
-{
- __IO uint32_t data = 0;
- __IO uint32_t data1 = 0;
- uint32_t deviceAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
-
- /* Read the electronic signature from NAND flash */
- if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
- {
- data = *(__IO uint32_t *)deviceAddress;
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
- }
- else
- {
- data = *(__IO uint32_t *)deviceAddress;
- data1 = *((__IO uint32_t *)deviceAddress + 4);
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
- pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory reset
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
-{
- uint32_t deviceAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Configure the device: Enter the physical parameters of the device
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
-{
- hnand->Config.PageSize = pDeviceConfig->PageSize;
- hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
- hnand->Config.BlockSize = pDeviceConfig->BlockSize;
- hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
- hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
- hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
- hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Read Page(s) from NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer
- * @param NumPageToRead : number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0U;
- uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
- __DSB();
-
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
- __DSB();
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Read Page(s) from NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
- * @param NumPageToRead : number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
- __DSB();
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
- __DSB();
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
- __DSB();
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- __DSB();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
- __DSB();
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- __DSB();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaToRead: Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0U;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
- __DSB();
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
- __DSB();
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaToRead: Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0U;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
- __DSB();
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
- __DSB();
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress =0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Page address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
- __DSB();
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- __DSB();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- deviceAddress = NAND_DEVICE;
-
- /* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
- __DSB();
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
- __DSB();
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- __DSB();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory Block erase
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t DeviceAddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- DeviceAddress = NAND_DEVICE;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- __DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- __DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- __DSB();
-
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
- __DSB();
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Increment the NAND memory address
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @retval The new status of the increment address operation. It can be:
- * - NAND_VALID_ADDRESS: When the new address is valid address
- * - NAND_INVALID_ADDRESS: When the new address is invalid address
- */
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t status = NAND_VALID_ADDRESS;
-
- /* Increment page address */
- pAddress->Page++;
-
- /* Check NAND address is valid */
- if(pAddress->Page == hnand->Config.BlockSize)
- {
- pAddress->Page = 0;
- pAddress->Block++;
-
- if(pAddress->Block == hnand->Config.PlaneSize)
- {
- pAddress->Block = 0;
- pAddress->Plane++;
-
- if(pAddress->Plane == (hnand->Config.PlaneSize/ hnand->Config.BlockNbr))
- {
- status = NAND_INVALID_ADDRESS;
- }
- }
- }
-
- return (status);
-}
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NAND interface.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Enable ECC feature */
- FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Disable ECC feature */
- FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ECCval: pointer to ECC value
- * @param Timeout: maximum timeout to wait
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Get NAND ECC value */
- status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return status;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NAND State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NAND controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NAND state
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL state
- */
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
-{
- return hnand->State;
-}
-
-/**
- * @brief NAND memory read status
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval NAND status
- */
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
-{
- uint32_t data = 0;
- uint32_t DeviceAddress = 0;
-
- /* Identify the device address */
- DeviceAddress = NAND_DEVICE;
-
- /* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
-
- /* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
-
- /* Return the status */
- if((data & NAND_ERROR) == NAND_ERROR)
- {
- return NAND_ERROR;
- }
- else if((data & NAND_READY) == NAND_READY)
- {
- return NAND_READY;
- }
-
- return NAND_BUSY;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c
deleted file mode 100644
index 4a80fe2..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c
+++ /dev/null
@@ -1,1045 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_nor.c
- * @author MCD Application Team
- * @brief NOR HAL module driver.
- * This file provides a generic firmware to drive NOR memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NOR flash memories. It uses the FMC layer functions to interface
- with NOR devices. This driver is used as follows:
-
- (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
- with control and timing parameters for both normal and extended mode.
-
- (+) Read NOR flash memory manufacturer code and device IDs using the function
- HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NOR flash memory by read/write data unit operations using the functions
- HAL_NOR_Read(), HAL_NOR_Program().
-
- (+) Perform NOR flash erase block/chip operations using the functions
- HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-
- (+) Read the NOR flash CFI (common flash interface) IDs using the function
- HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
- structure declared by the function caller.
-
- (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
- HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
-
- (+) You can monitor the NOR device HAL state by calling the function
- HAL_NOR_GetState()
- [..]
- (@) This driver is a set of generic APIs which handle standard NOR flash operations.
- If a NOR flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- *** NOR HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in NOR HAL driver.
-
- (+) NOR_WRITE : NOR memory write data to specified address
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup NOR NOR
- * @brief NOR driver modules
- * @{
- */
-#ifdef HAL_NOR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Defines NOR Private Defines
- * @{
- */
-
-/* Constants to define address to set to write a command */
-#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
-#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
-
-/* Constants to define data to program a command */
-#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
-#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
-#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
-#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
-#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
-#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
-#define NOR_CMD_DATA_CFI (uint16_t)0x0098
-
-#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
-#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
-#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
-
-/* Mask on NOR STATUS REGISTER */
-#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
-#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup NOR_Private_Variables NOR Private Variables
- * @{
- */
-
-static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timing: pointer to NOR control timing structure
- * @param ExtTiming: pointer to NOR extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the NOR handle parameter */
- if(hnor == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnor->State == HAL_NOR_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnor->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_NOR_MspInit(hnor);
- }
-
- /* Initialize NOR control Interface */
- FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
-
- /* Initialize NOR timing Interface */
- FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
-
- /* Initialize NOR extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
-
- /* Initialize NOR Memory Data Width*/
- if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
- {
- uwNORMemoryDataWidth = NOR_MEMORY_8B;
- }
- else
- {
- uwNORMemoryDataWidth = NOR_MEMORY_16B;
- }
-
- /* Enable FMC IP */
- __FMC_ENABLE();
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_NOR_MspDeInit(hnor);
-
- /* Configure the NOR registers with their reset values */
- FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief NOR MSP Init
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP DeInit
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP Wait for Ready/Busy signal
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timeout: Maximum timeout value
- * @retval None
- */
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
- UNUSED(Timeout);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspWait could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read NOR flash IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_ID : pointer to NOR ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read data from NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress: pointer to Device address
- * @param pData : pointer to read data
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-
- /* Read the data */
- *pData = *(__IO uint32_t *)(uint32_t)pAddress;
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Program data to NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress: Device address
- * @param pData : pointer to the data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a half-word buffer from the NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal address to read from.
- * @param pData: pointer to the buffer that receives the data read from the
- * NOR memory.
- * @param uwBufferSize : number of Half word to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while( uwBufferSize > 0)
- {
- *pData++ = *(__IO uint16_t *)uwAddress;
- uwAddress += 2;
- uwBufferSize--;
- }
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a half-word buffer to the NOR memory. This function must be used
- only with S29GL128P NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal start write address
- * @param pData: pointer to source data buffer.
- * @param uwBufferSize: Size of the buffer to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint16_t * p_currentaddress = (uint16_t *)NULL;
- uint16_t * p_endaddress = (uint16_t *)NULL;
- uint32_t lastloadedaddress = 0, deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Initialize variables */
- p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
- p_endaddress = p_currentaddress + (uwBufferSize-1);
- lastloadedaddress = (uint32_t)(uwAddress);
-
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1));
-
- /* Load Data into NOR Buffer */
- while(p_currentaddress <= p_endaddress)
- {
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
-
- NOR_WRITE(p_currentaddress, *pData++);
-
- p_currentaddress ++;
- }
-
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param BlockAddress : Block to erase address
- * @param Address: Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the entire NOR chip.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address : Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read NOR flash CFI IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_CFI : pointer to NOR CFI IDs structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
-{
- uint32_t deviceaddress = 0;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
- /* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NOR Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NOR interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Update the SRAM controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NOR State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NOR controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NOR controller state
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval NOR controller state
- */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
-{
- return hnor->State;
-}
-
-/**
- * @brief Returns the NOR operation status.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address: Device address
- * @param Timeout: NOR programming Timeout
- * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
- * or HAL_NOR_STATUS_TIMEOUT
- */
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{
- HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmpSR1 = 0, tmpSR2 = 0;
- uint32_t tickstart = 0;
-
- /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
- HAL_NOR_MspWait(hnor, Timeout);
-
- /* Get the NOR memory operation status -------------------------------------*/
-
- /* Get tick */
- tickstart = HAL_GetTick();
- while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- status = HAL_NOR_STATUS_TIMEOUT;
- }
- }
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS ;
- }
-
- if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
-
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS;
- }
- if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- return HAL_NOR_STATUS_ERROR;
- }
- }
-
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_NOR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c
deleted file mode 100644
index c9f8261..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c
+++ /dev/null
@@ -1,990 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_opamp.c
- * @author MCD Application Team
- * @brief OPAMP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the operational amplifier(s) peripheral:
- * + OPAMP configuration
- * + OPAMP calibration
- * Thanks to
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
-================================================================================
- ##### OPAMP Peripheral Features #####
-================================================================================
-
- [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2
-
- (#) The OPAMP(s) provides several exclusive running modes.
- (++) Standalone mode
- (++) Programmable Gain Amplifier (PGA) modes
- (++) Follower mode
-
- (#) Each OPAMP(s) can be configured in normal and high speed mode.
-
- (#) The OPAMP(s) provide(s) calibration capabilities.
- (++) Calibration aims at correcting some offset for running mode.
- (++) The OPAMP uses either factory calibration settings OR user defined
- calibration (trimming) settings (i.e. trimming mode).
- (++) The user defined settings can be figured out using self calibration
- handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
- (++) HAL_OPAMP_SelfCalibrate:
- (+++) Runs automatically the calibration in 2 steps.
- (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
- (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
- appropriate and enough in most cases).
- (+++) Runs automatically the calibration.
- (+++) Enables the user trimming mode
- (+++) Updates the init structure with trimming values with fresh calibration
- results.
- The user may store the calibration results for larger
- (ex monitoring the trimming as a function of temperature
- for instance)
- (+++) HAL_OPAMPEx_SelfCalibrateAll
- runs calibration of all OPAMPs in parallel to save search time.
-
- (#) Running mode: Standalone mode
- (++) Gain is set externally (gain depends on external loads).
- (++) Follower mode also possible externally by connecting the inverting input to
- the output.
-
- (#) Running mode: Follower mode
- (++) No Inverting Input is connected.
-
- (#) Running mode: Programmable Gain Amplifier (PGA) mode
- (Resistor feedback output)
- (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
- output.
- (#) OPAMP gain can be selected as :
-
- (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
- (+++) VREF- referenced.
- (+++) Filtering on VINM0, VREF- referenced.
- (+++) VINM0 node for bias voltage and VINP0 for input signal.
- (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.
-
- (##) Gain of x-1, x-3, x-7 or x-15 for inverting mode with:
- (+++) VINM0 node for input signal and VINP0 for bias.
- (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.
-
- (#) The OPAMPs inverting input can be selected according to the Reference Manual
- "OPAMP functional description" chapter.
-
- (#) The OPAMPs non inverting input can be selected according to the Reference Manual
- "OPAMP functional description" chapter.
-
-
- ##### How to use this driver #####
-================================================================================
- [..]
-
- *** High speed / normal power mode ***
- ============================================
- [..] To run in high speed mode:
-
- (#) Configure the OPAMP using HAL_OPAMP_Init() function:
- (++) Select OPAMP_POWERMODE_HIGHSPEED
- (++) Otherwise select OPAMP_POWERMODE_NORMAL
-
- *** Calibration ***
- ============================================
- [..] To run the OPAMP calibration self calibration:
-
- (#) Start calibration using HAL_OPAMP_SelfCalibrate.
- Store the calibration results.
-
- *** Running mode ***
- ============================================
-
- [..] To use the OPAMP, perform the following steps:
-
- (#) Fill in the HAL_OPAMP_MspInit() to
- (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
- (++) Configure the OPAMP input AND output in analog mode using
- HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
-
- (#) Configure the OPAMP using HAL_OPAMP_Init() function:
- (++) Select the mode
- (++) Select the inverting input
- (++) Select the non-inverting input
- (++) If PGA mode is enabled, Select if inverting input is connected.
- (++) Select either factory or user defined trimming mode.
- (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
- (typically values set by HAL_OPAMP_SelfCalibrate function).
-
- (#) Enable the OPAMP using HAL_OPAMP_Start() function.
-
- (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
-
- (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
- Caution: On STM32H7, HAL OPAMP lock is software lock only (not
- hardware lock as on some other STM32 devices)
-
- (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
-
- *** Running mode: change of configuration while OPAMP ON ***
- ============================================
- [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
- (#) If needed, fill in the HAL_OPAMP_MspInit()
- (++) This is the case for instance if you wish to use new OPAMP I/O
-
- (#) Configure the OPAMP using HAL_OPAMP_Init() function:
- (++) As in configure case, select first the parameters you wish to modify.
-
- (#) Change from high speed mode to normal power mode (& vice versa) requires
- first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
- In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
- alone.
-
- @endverbatim
- ******************************************************************************
- Table 1. OPAMPs inverting/non-inverting inputs for the STM32H7 devices:
-
- +------------------------------------------------------------------------|
- | | | OPAMP1 | OPAMP2 |
- |-----------------|---------|----------------------|---------------------|
- | Inverting Input | VM_SEL | VINM0-> PC5 | VINM0-> PE8 |
- | | | VINM1-> PA7 | VINM1-> PG1 |
- | | | Internal: | Internal: |
- | | | ADC1_IN9 | OPAMP2_OUT |
- | | | ADC2_IN9 | PGA mode |
- | | | OPAMP1_OUT | |
- | | | PGA mode | |
- |-----------------|---------|----------------------|---------------------|
- | Non Inverting | VP_SEL | | |
- | | | VP0 -> PB0 (GPIO) | VP0 -> PE9 (GPIO) |
- | | | Internal: | Internal: |
- | Input | | DAC1_int | DAC2_int |
- | | | ADC1_IN8 | COMP2_INP |
- | | | ADC2_IN8 | |
- | | | COMP1_INP | |
- +------------------------------------------------------------------------|
-
-
- [..] Table 2. OPAMPs outputs for the STM32H7 devices:
-
- +-------------------------------------------------------------------------
- | | | OPAMP1 | OPAMP2 |
- |-----------------|--------|-----------------------|---------------------|
- | Output | VOUT | PC4 | PE7 |
- | | | & ADC1_IN4| | & COMP2_INN7 if |
- | | | ADC2_IN4 |connected internally |
- | | | COMP1_INN7 if | |
- | | | connected internally | |
- |-----------------|--------|-----------------------|---------------------|
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup OPAMP OPAMP
- * @brief OPAMP module driver
- * @{
- */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup OPAMP_Private_Constants
- * @{
- */
-
-/* CSR register reset value */
-#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
-
-
-#define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL \
- | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
- | OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM)
-/* CSR Init masks */
-
-#define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_PGGAIN | OPAMP_CSR_PGGAIN \
- | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)
-
-
-#define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
- | OPAMP_CSR_USERTRIM)
-
-
-#define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
- | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
- * @{
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the OPAMP according to the specified
- * parameters in the OPAMP_InitTypeDef and initialize the associated handle.
- * @note If the selected opamp is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t updateotrlpotr = 0;
-
- /* Check the OPAMP handle allocation and lock status */
- /* Init not allowed if calibration is ongoing */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Set OPAMP parameters */
- assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
- assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
- assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
-
- if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
- {
- assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
- }
-
- if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
- {
- assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
- assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
- }
-
-
- assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
-
- if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
- {
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
- {
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
- }
- else
- {
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePHighSpeed));
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNHighSpeed));
- }
- }
-
- if(hopamp->State == HAL_OPAMP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hopamp->Lock = HAL_UNLOCKED;
- }
-
- /* Call MSP init function */
- HAL_OPAMP_MspInit(hopamp);
-
- /* Set operating mode */
- CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
- /* In PGA mode InvertingInput is Not Applicable */
- if (hopamp->Init.Mode == OPAMP_PGA_MODE)
- {
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
- hopamp->Init.PowerMode | \
- hopamp->Init.Mode | \
- hopamp->Init.PgaGain | \
- hopamp->Init.PgaConnect | \
- hopamp->Init.NonInvertingInput | \
- hopamp->Init.UserTrimming);
- }
-
- if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
- {
- /* In Follower mode InvertingInput is Not Applicable */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
- hopamp->Init.PowerMode | \
- hopamp->Init.Mode | \
- hopamp->Init.NonInvertingInput | \
- hopamp->Init.UserTrimming);
- }
-
- if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
- {
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
- hopamp->Init.PowerMode | \
- hopamp->Init.Mode | \
- hopamp->Init.InvertingInput | \
- hopamp->Init.NonInvertingInput | \
- hopamp->Init.UserTrimming);
- }
-
- if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
- {
- /* Set power mode and associated calibration parameters */
- if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
- {
- /* OPAMP_POWERMODE_NORMAL */
- /* Set calibration mode (factory or user) and values for */
- /* transistors differential pair high (PMOS) and low (NMOS) for */
- /* normal mode. */
- updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
- | (hopamp->Init.TrimmingValueN));
- MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
- }
- else
- {
- /* OPAMP_POWERMODE_HIGHSPEED*/
- /* transistors differential pair high (PMOS) and low (NMOS) for */
- /* high speed mode. */
- updateotrlpotr = (((hopamp->Init.TrimmingValuePHighSpeed) << (OPAMP_INPUT_NONINVERTING)) \
- | (hopamp->Init.TrimmingValueNHighSpeed));
- MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
- }
- }
-
- /* Update the OPAMP state*/
- if (hopamp->State == HAL_OPAMP_STATE_RESET)
- {
- /* From RESET state to READY State */
- hopamp->State = HAL_OPAMP_STATE_READY;
- }
- /* else: remain in READY or BUSY state (no update) */
- return status;
- }
-}
-
-/**
- * @brief DeInitialize the OPAMP peripheral
- * @note Deinitialization can be performed if the OPAMP configuration is locked.
- * (the lock is SW in H7)
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* DeInit not allowed if calibration is on going */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Set OPAMP_CSR register to reset value */
- /* OPAMP shall be disabled first separately */
-
- CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
-
- /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
- HAL_OPAMP_MspDeInit(hopamp);
-
- /* Update the OPAMP state*/
- hopamp->State = HAL_OPAMP_STATE_RESET;
- /* Process unlocked */
- __HAL_UNLOCK(hopamp);
-
- }
-
- return status;
-}
-
-
-/**
- * @brief Initialize the OPAMP MSP.
- * @param hopamp: OPAMP handle
- * @retval None
- */
-__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hopamp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitialize OPAMP MSP.
- * @param hopamp: OPAMP handle
- * @retval None
- */
-__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hopamp);
- /* NOTE : This function should not be modified, when the callback is needed,
- the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the OPAMP
- start, stop and calibration actions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the OPAMP.
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- if(hopamp->State == HAL_OPAMP_STATE_READY)
- {
- /* Enable the selected opamp */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Update the OPAMP state*/
- /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
- hopamp->State = HAL_OPAMP_STATE_BUSY;
- }
- else
- {
- status = HAL_ERROR;
- }
-
- }
- return status;
-}
-
-/**
- * @brief Stop the OPAMP.
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- /* Check if OPAMP calibration ongoing */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- if(hopamp->State == HAL_OPAMP_STATE_BUSY)
- {
- /* Disable the selected opamp */
- CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Update the OPAMP state*/
- /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
- hopamp->State = HAL_OPAMP_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
- return status;
-}
-
-/**
- * @brief Run the self calibration of one OPAMP.
- * @note Calibration is performed in the mode specified in OPAMP init
- * structure (mode normal or high-speed). To perform calibration for
- * both modes, repeat this function twice after OPAMP init structure
- * accordingly updated.
- * @param hopamp handle
- * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
-{
-
- HAL_StatusTypeDef status = HAL_OK;
-
- uint32_t trimmingvaluen = 0;
- uint32_t trimmingvaluep = 0;
- uint32_t delta;
- uint32_t opampmode;
-
- __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or HSOTR */
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
- {
- status = HAL_ERROR;
- }
- else
- {
-
- /* Check if OPAMP in calibration mode and calibration not yet enable */
- if(hopamp->State == HAL_OPAMP_STATE_READY)
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
- assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-
- opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_VMSEL);
-
- /* Use of standalone mode */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
- /* user trimming values are used for offset calibration */
- SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
-
- /* Select trimming settings depending on power mode */
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
- {
- tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
-
- }
- else
- {
- /* high speed Mode */
- tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
- }
-
-
- /* Enable calibration */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
-
- /* Force internal reference on VP */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
-
- /* 1st calibration - N */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
-
- /* Enable the selected opamp */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvaluen = 16;
- delta = 8;
-
- while (delta != 0)
- {
- /* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
- /* Offset trim time: during calibration, minimum time needed between */
- /* two steps to have 1 mV accuracy */
- HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
- {
- /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
- trimmingvaluen += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is LOW try lower trimming */
- trimmingvaluen -= delta;
- }
- /* Divide range by 2 to continue dichotomy sweep */
- delta >>= 1;
- }
-
- /* Still need to check if right calibration is current value or one step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
-
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
- /* Offset trim time: during calibration, minimum time needed between */
- /* two steps to have 1 mV accuracy */
- HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
- {
- /* Trimming value is actually one value more */
- trimmingvaluen++;
- /* Set right trimming */
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
- }
-
- /* 2nd calibration - P */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvaluep = 16;
- delta = 8;
-
- while (delta != 0)
- {
- /* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
- trimmingvaluep += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is LOW try lower trimming */
- trimmingvaluep -= delta;
- }
-
- /* Divide range by 2 to continue dichotomy sweep */
- delta >>= 1;
- }
-
- /* Still need to check if right calibration is current value or one step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
- /* Set candidate trimming */
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
- {
- /* Trimming value is actually one value more */
- trimmingvaluep++;
- MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALON);
-
- /* Disable the OPAMP */
- CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Set operating mode back */
- CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
-
- /* Self calibration is successful */
- /* Store calibration(user trimming) results in init structure. */
-
- /* Set user trimming mode */
- hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
-
- /* Affect calibration parameters depending on mode normal/high speed */
- if (hopamp->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
- {
- /* Write calibration result N */
- hopamp->Init.TrimmingValueN = trimmingvaluen;
- /* Write calibration result P */
- hopamp->Init.TrimmingValueP = trimmingvaluep;
- }
- else
- {
- /* Write calibration result N */
- hopamp->Init.TrimmingValueNHighSpeed = trimmingvaluen;
- /* Write calibration result P */
- hopamp->Init.TrimmingValuePHighSpeed = trimmingvaluep;
- }
- /* Restore OPAMP mode after calibration */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, opampmode);
- }
-
- else
- {
- /* OPAMP can not be calibrated from this mode */
- status = HAL_ERROR;
- }
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the OPAMP data
- transfers.
-
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected OPAMP configuration.
- * @note On STM32H7, HAL OPAMP lock is software lock only (in
- * contrast of hardware lock available on some other STM32
- * devices)
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- /* OPAMP can be locked when enabled and running in normal mode */
- /* It is meaningless otherwise */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
- || (hopamp->State == HAL_OPAMP_STATE_READY) \
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
- || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-
- {
- status = HAL_ERROR;
- }
-
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* OPAMP state changed to locked */
- hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
- }
- return status;
-}
-
-/**
- * @brief Return the OPAMP factory trimming value.
- * @note On STM32H7 OPAMP, user can retrieve factory trimming if
- * OPAMP has never been set to user trimming before.
- * Therefore, this function must be called when OPAMP init
- * parameter "UserTrimming" is set to trimming factory,
- * and before OPAMP calibration (function
- * "HAL_OPAMP_SelfCalibrate()").
- * Otherwise, factory trimming value cannot be retrieved and
- * error status is returned.
- * @param hopamp : OPAMP handle
- * @param trimmingoffset : Trimming offset (P or N)
- * This parameter must be a value of @ref OPAMP_FactoryTrimming
- * @note Calibration parameter retrieved is corresponding to the mode
- * specified in OPAMP init structure (mode normal or high-speed).
- * To retrieve calibration parameters for both modes, repeat this
- * function after OPAMP init structure accordingly updated.
- * @retval Trimming value (P or N): range: 0->31
- * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
- *
- */
-
-HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
-{
- HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
- __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-
- /* Check the OPAMP handle allocation */
- /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
- || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
- || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
- {
- return OPAMP_FACTORYTRIMMING_DUMMY;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
- assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
- assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-
- /* Check the trimming mode */
- if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= RESET)
- {
- /* This function must called when OPAMP init parameter "UserTrimming" */
- /* is set to trimming factory, and before OPAMP calibration (function */
- /* "HAL_OPAMP_SelfCalibrate()"). */
- /* Otherwise, factory trimming value cannot be retrieved and error */
- /* status is returned. */
- trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
- }
- else
- {
- /* Select trimming settings depending on power mode */
- if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
- {
- tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
- }
- else
- {
- tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
- }
-
- /* Get factory trimming */
- if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
- {
- /* OPAMP_FACTORYTRIMMING_P */
- trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
- }
- else
- {
- /* OPAMP_FACTORYTRIMMING_N */
- trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
- }
- }
- }
- return trimmingvalue;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the OPAMP handle state.
- * @param hopamp : OPAMP handle
- * @retval HAL state
- */
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
-{
- /* Check the OPAMP handle allocation */
- if(hopamp == NULL)
- {
- return HAL_OPAMP_STATE_RESET;
- }
-
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Return OPAMP handle state */
- return hopamp->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c
deleted file mode 100644
index c41bfb1..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_opamp_ex.c
- * @author MCD Application Team
- * @brief Extended OPAMP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
- * peripheral:
- * + Extended Initialization and de-initialization functions
- * + Extended Peripheral Control functions
- *
- @verbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup OPAMPEx OPAMPEx
- * @brief OPAMP Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
- * @{
- */
-
-/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
- * @brief Extended operation functions
- *
-@verbatim
- ===============================================================================
- ##### Extended IO operation functions #####
- ===============================================================================
- [..]
- (+) OPAMP Self calibration.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Run the self calibration of 2 OPAMPs in parallel.
- * @note Trimming values (PMOS & NMOS) are updated and user trimming is
- * enabled is calibration is successful.
- * @note Calibration is performed in the mode specified in OPAMP init
- * structure (mode normal or low power). To perform calibration for
- * both modes, repeat this function twice after OPAMP init structure
- * accordingly updated.
- * @param hopamp1 handle
- * @param hopamp2 handle
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- uint32_t trimmingvaluen1 = 0;
- uint32_t trimmingvaluep1 = 0;
- uint32_t trimmingvaluen2 = 0;
- uint32_t trimmingvaluep2 = 0;
-
-/* Selection of register of trimming depending on power mode: OTR or HSOTR */
- __IO uint32_t* tmp_opamp1_reg_trimming;
- __IO uint32_t* tmp_opamp2_reg_trimming;
-
- uint32_t delta;
- uint32_t opampmode1;
- uint32_t opampmode2;
-
- if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
- (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check if OPAMP in calibration mode and calibration not yet enable */
- if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY))
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
-
- assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
- assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
-
- /* Set Calibration mode */
- /* Non-inverting input connected to calibration reference voltage. */
- SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
- SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
-
- /* Save OPAMP mode */
- opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_VMSEL);
- opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_VMSEL);
-
- /* Use of standalone mode */
- MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
- MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
-
- /* user trimming values are used for offset calibration */
- SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
- SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
-
- /* Select trimming settings depending on power mode */
- if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
- {
- tmp_opamp1_reg_trimming = &OPAMP1->OTR;
- }
- else
- {
- tmp_opamp1_reg_trimming = &OPAMP1->HSOTR;
- }
-
- if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
- {
- tmp_opamp2_reg_trimming = &OPAMP2->OTR;
- }
- else
- {
- tmp_opamp2_reg_trimming = &OPAMP2->HSOTR;
- }
-
- /* Enable calibration */
- SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
- SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
-
- /* 1st calibration - N */
- /* Select 90U% VREF */
- MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
- MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
-
- /* Enable the selected opamp */
- SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
- SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvaluen1 = 16;
- trimmingvaluen2 = 16;
- delta = 8;
-
- while (delta != 0)
- {
- /* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
- MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
- /* Offset trim time: during calibration, minimum time needed between */
- /* two steps to have 1 mV accuracy */
- HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* OPAMP_CSR_CALOUT is Low try higher trimming */
- trimmingvaluen1 += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is High try lower trimming */
- trimmingvaluen1 -= delta;
- }
-
- if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* OPAMP_CSR_CALOUT is Low try higher trimming */
- trimmingvaluen2 += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is High try lower trimming */
- trimmingvaluen2 -= delta;
- }
- /* Divide range by 2 to continue dichotomy sweep */
- delta >>= 1;
- }
-
- /* Still need to check if right calibration is current value or one step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
- /* Set candidate trimming */
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
- MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
- /* Offset trim time: during calibration, minimum time needed between */
- /* two steps to have 1 mV accuracy */
- HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
- {
- /* Trimming value is actually one value more */
- trimmingvaluen1++;
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
- }
-
- if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) != 0)
- {
- /* Trimming value is actually one value more */
- trimmingvaluen2++;
- MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
- }
-
- /* 2nd calibration - P */
- /* Select 10U% VREF */
- MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
- MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvaluep1 = 16;
- trimmingvaluep2 = 16;
- delta = 8;
-
- while (delta != 0)
- {
- /* Set candidate trimming */
- /* OPAMP_POWERMODE_NORMAL */
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* OPAMP_CSR_CALOUT is Low try higher trimming */
- trimmingvaluep1 += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
- trimmingvaluep1 -= delta;
- }
-
- if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* OPAMP_CSR_CALOUT is Low try higher trimming */
- trimmingvaluep2 += delta;
- }
- else
- {
- /* OPAMP_CSR_CALOUT is High try lower trimming */
- trimmingvaluep2 -= delta;
- }
- /* Divide range by 2 to continue dichotomy sweep */
- delta >>= 1;
- }
-
- /* Still need to check if right calibration is current value or one step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
- /* Set candidate trimming */
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* Trimming value is actually one value more */
- trimmingvaluep1++;
- MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT)!= RESET)
- {
- /* Trimming value is actually one value more */
- trimmingvaluep2++;
- MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<Instance->CSR, OPAMP_CSR_CALON);
- CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
-
- /* Disable the OPAMPs */
- CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
- CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Self calibration is successful */
- /* Store calibration (user trimming) results in init structure. */
-
- /* Set user trimming mode */
- hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
- hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
-
- /* Affect calibration parameters depending on mode normal/high speed */
- if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
- {
- /* Write calibration result N */
- hopamp1->Init.TrimmingValueN = trimmingvaluen1;
- /* Write calibration result P */
- hopamp1->Init.TrimmingValueP = trimmingvaluep1;
- }
- else
- {
- /* Write calibration result N */
- hopamp1->Init.TrimmingValueNHighSpeed = trimmingvaluen1;
- /* Write calibration result P */
- hopamp1->Init.TrimmingValuePHighSpeed = trimmingvaluep1;
- }
-
- if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
- {
- /* Write calibration result N */
- hopamp2->Init.TrimmingValueN = trimmingvaluen2;
- /* Write calibration result P */
- hopamp2->Init.TrimmingValueP = trimmingvaluep2;
- }
- else
- {
- /* Write calibration result N */
- hopamp2->Init.TrimmingValueNHighSpeed = trimmingvaluen2;
- /* Write calibration result P */
- hopamp2->Init.TrimmingValuePHighSpeed = trimmingvaluep2;
-
- }
- /* Update OPAMP state */
- hopamp1->State = HAL_OPAMP_STATE_READY;
- hopamp2->State = HAL_OPAMP_STATE_READY;
-
- /* Restore OPAMP mode after calibration */
- MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, opampmode1);
- MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, opampmode2);
- }
- else
- {
- /* At least one OPAMP can not be calibrated */
- status = HAL_ERROR;
- }
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- (+) OPAMP unlock.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the selected OPAMP configuration.
- * @note This function must be called only when OPAMP is in state "locked".
- * @param hopamp: OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
- || (hopamp->State == HAL_OPAMP_STATE_READY)
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
- || (hopamp->State == HAL_OPAMP_STATE_BUSY))
-
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* OPAMP state changed to locked */
- hopamp->State = HAL_OPAMP_STATE_BUSY;
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
deleted file mode 100644
index 51e9d02..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
+++ /dev/null
@@ -1,1348 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pcd.c
- * @author MCD Application Team
- * @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The PCD HAL driver can be used as follows:
-
- (#) Declare a PCD_HandleTypeDef handle structure, for example:
- PCD_HandleTypeDef hpcd;
-
- (#) Fill parameters of Init structure in PCD handle
-
- (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
-
- (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
- (##) Enable the PCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
-
- (##) Initialize the related GPIO clocks
- (##) Configure PCD pin-out
- (##) Configure PCD NVIC interrupt
-
- (#)Associate the Upper USB device stack to the HAL PCD Driver:
- (##) hpcd.pData = pdev;
-
- (#)Enable PCD transmission and reception:
- (##) HAL_PCD_Start();
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCD PCD
- * @brief PCD HAL module driver
- * @{
- */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/**
- * USB_OTG_CORE VERSION ID
- */
-#define USB_OTG_CORE_ID_310A 0x4F54310A
-#define USB_OTG_CORE_ID_320A 0x4F54320A
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
- uint32_t i = 0;
-
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
-
- /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
-
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
-
- /* Init endpoints structures */
- for (i = 0; i < 15 ; i++)
- {
- /* Init ep structure */
- hpcd->IN_ep[i].is_in = 1;
- hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is activated */
- hpcd->IN_ep[i].type = EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0;
- hpcd->IN_ep[i].xfer_buff = 0;
- hpcd->IN_ep[i].xfer_len = 0;
- }
-
- for (i = 0; i < 15 ; i++)
- {
- hpcd->OUT_ep[i].is_in = 0;
- hpcd->OUT_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is activated */
- hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0;
- hpcd->OUT_ep[i].xfer_buff = 0;
- hpcd->OUT_ep[i].xfer_len = 0;
-
- hpcd->Instance->DIEPTXF[i] = 0;
- }
-
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
-
- hpcd->State= HAL_PCD_STATE_READY;
-
- /* Activate LPM */
- if (hpcd->Init.lpm_enable == 1)
- {
- HAL_PCDEx_ActivateLPM(hpcd);
- }
-
-#if defined (USB_OTG_GCCFG_BCDEN)
- /* Activate Battery charging */
- if (hpcd->Init.battery_charging_enable ==1)
- {
- HAL_PCDEx_ActivateBCD(hpcd);
- }
-#endif /* USB_OTG_GCCFG_BCDEN */
-
- USB_DevDisconnect (hpcd->Instance);
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the PCD peripheral.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Stop Device */
- HAL_PCD_Stop(hpcd);
-
- /* DeInit the low level hardware */
- HAL_PCD_MspDeInit(hpcd);
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the PCD MSP.
- * @param hpcd: PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes PCD MSP.
- * @param hpcd: PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start The USB OTG Device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
-
- USB_DevConnect (hpcd->Instance);
- __HAL_PCD_ENABLE(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop The USB OTG Device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- __HAL_PCD_DISABLE(hpcd);
- USB_StopDevice(hpcd->Instance);
- USB_DevDisconnect (hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Handle PCD interrupt request.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
- uint32_t fifoemptymsk = 0, temp = 0;
- USB_OTG_EPTypeDef *ep = NULL;
- uint32_t hclk = 400000000;
-
- /* ensure that we are in device mode */
- if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
- {
- /* avoid spurious interrupt */
- if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
- {
- return;
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
- {
- epnum = 0;
-
- /* Read in the device interrupt bits */
- ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-
- while ( ep_intr )
- {
- if (ep_intr & 0x1)
- {
- epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-
- if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
- /* setup/out transaction management for Core ID >= 310A */
- if (USBx->GSNPSID >= USB_OTG_CORE_ID_310A)
- {
- if(hpcd->Init.dma_enable == 1)
- {
- if(USBx_OUTEP(0)->DOEPINT & (1 << 15))
- {
- CLEAR_OUT_EP_INTR(epnum, (1 << 15));
- }
- }
- }
-
- if(hpcd->Init.dma_enable == 1)
- {
- hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
- hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
- }
-
- HAL_PCD_DataOutStageCallback(hpcd, epnum);
- if(hpcd->Init.dma_enable == 1)
- {
- if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
- {
- /* this is ZLP, so prepare EP0 for next setup */
- USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
- }
- }
- }
-
- if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
- {
- /* setup/out transaction management for Core ID >= 310A */
- if (USBx->GSNPSID >= USB_OTG_CORE_ID_310A)
- {
- if(hpcd->Init.dma_enable == 1)
- {
- if(USBx_OUTEP(0)->DOEPINT & (1 <<15 ))
- {
- CLEAR_OUT_EP_INTR(epnum, (1 << 15));
- }
- }
- }
-
- /* Inform the upper layer that a setup packet is available */
- HAL_PCD_SetupStageCallback(hpcd);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
- }
-
- if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
- }
- /* Clear Status Phase Received interrupt */
- if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
- }
- }
- epnum++;
- ep_intr >>= 1;
- }
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
- {
- /* Read in the device interrupt bits */
- ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-
- epnum = 0;
-
- while ( ep_intr )
- {
- if (ep_intr & 0x1) /* In ITR */
- {
- epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-
- if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
- {
- fifoemptymsk = 0x1 << epnum;
- USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-
- if (hpcd->Init.dma_enable == 1)
- {
- hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
- }
-
- HAL_PCD_DataInStageCallback(hpcd, epnum);
-
- if (hpcd->Init.dma_enable == 1)
- {
- /* this is ZLP, so prepare EP0 for next setup */
- if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
- {
- /* prepare to rx more setup packets */
- USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
- }
- }
- }
- if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
- }
- if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
- }
- if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
- }
- if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
- }
- if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
- {
- PCD_WriteEmptyTxFifo(hpcd , epnum);
- }
- }
- epnum++;
- ep_intr >>= 1;
- }
- }
-
- /* Handle Resume Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
- {
- /* Clear the Remote Wake-up Signaling */
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
- if(hpcd->LPM_State == LPM_L1)
- {
- hpcd->LPM_State = LPM_L0;
- HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
- }
- else
- {
- HAL_PCD_ResumeCallback(hpcd);
- }
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
- }
-
- /* Handle Suspend Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
- {
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
-
- HAL_PCD_SuspendCallback(hpcd);
- }
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
- }
-
- /* Handle LPM Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
- if( hpcd->LPM_State == LPM_L0)
- {
- hpcd->LPM_State = LPM_L1;
- hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
- HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
- }
- else
- {
- HAL_PCD_SuspendCallback(hpcd);
- }
- }
-
- /* Handle Reset Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
- {
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
- USB_FlushTxFifo(hpcd->Instance, 0x10);
-
- for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
- {
- USBx_INEP(i)->DIEPINT = 0xFF;
- USBx_OUTEP(i)->DOEPINT = 0xFF;
- }
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
- USBx_DEVICE->DAINTMSK |= 0x10001;
-
- if(hpcd->Init.use_dedicated_ep1)
- {
- USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
- }
- else
- {
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
- }
-
- /* Set Default Address to 0 */
- USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-
- /* setup EP0 to receive SETUP packets */
- USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
- }
-
- /* Handle Enumeration done Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
- {
- USB_ActivateSetup(hpcd->Instance);
- hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
- if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
- {
- hpcd->Init.speed = USB_OTG_SPEED_HIGH;
- hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
- }
- else
- {
- hpcd->Init.speed = USB_OTG_SPEED_FULL;
- hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
-
- /* The USBTRD is configured according to the tables below, depending on AHB frequency
- used by application. In the low AHB frequency range it is used to stretch enough the USB response
- time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
- latency to the Data FIFO */
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- if((hclk >= 14200000)&&(hclk < 15000000))
- {
- /* hclk Clock Range between 14.2-15 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 15000000)&&(hclk < 16000000))
- {
- /* hclk Clock Range between 15-16 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 16000000)&&(hclk < 17200000))
- {
- /* hclk Clock Range between 16-17.2 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 17200000)&&(hclk < 18500000))
- {
- /* hclk Clock Range between 17.2-18.5 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 18500000)&&(hclk < 20000000))
- {
- /* hclk Clock Range between 18.5-20 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 20000000)&&(hclk < 21800000))
- {
- /* hclk Clock Range between 20-21.8 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 21800000)&&(hclk < 24000000))
- {
- /* hclk Clock Range between 21.8-24 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 24000000)&&(hclk < 27700000))
- {
- /* hclk Clock Range between 24-27.7 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 27700000)&&(hclk < 32000000))
- {
- /* hclk Clock Range between 27.7-32 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else /* if(hclk >= 32000000) */
- {
- /* hclk Clock Range between 32-400 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
- }
- }
-
- HAL_PCD_ResetCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
- }
-
- /* Handle RxQLevel Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- temp = USBx->GRXSTSP;
- ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
- if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
- {
- if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
- {
- USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- }
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
- {
- USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
-
- /* Handle SOF Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
- {
- HAL_PCD_SOFCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
- }
-
- /* Handle Incomplete ISO IN Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
- {
- HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
- }
-
- /* Handle Incomplete ISO OUT Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
- {
- HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
- }
-
- /* Handle Connection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
- {
- HAL_PCD_ConnectCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
- }
-
- /* Handle Disconnection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
- {
- temp = hpcd->Instance->GOTGINT;
-
- if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
- {
- HAL_PCD_DisconnectCallback(hpcd);
- }
- hpcd->Instance->GOTGINT |= temp;
- }
- }
-}
-
-/**
- * @brief Data out stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Data IN stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataInStageCallback could be implemented in the user file
- */
-}
-/**
- * @brief Setup stage callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Start Of Frame callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_SOFCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Reset callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_ResetCallback could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Suspend event callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_SuspendCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Resume event callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_ResumeCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO OUT callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO IN callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Connection event callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_ConnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disconnection event callback.
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Connect the USB device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- USB_DevConnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Disconnect the USB device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- USB_DevDisconnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Set the USB Device address.
- * @param hpcd: PCD handle
- * @param address: new device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
- __HAL_LOCK(hpcd);
- USB_SetDevAddress(hpcd->Instance, address);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Open and configure an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint type
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
- HAL_StatusTypeDef ret = HAL_OK;
- USB_OTG_EPTypeDef *ep = NULL;
-
- if ((ep_addr & 0x80) == 0x80)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
- }
- ep->num = ep_addr & 0x7F;
-
- ep->is_in = (0x80 & ep_addr) != 0;
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
- if (ep->is_in)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
- /* Set initial data PID. */
- if (ep_type == EP_TYPE_BULK )
- {
- ep->data_pid_start = 0;
- }
-
- __HAL_LOCK(hpcd);
- USB_ActivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
- return ret;
-}
-
-
-/**
- * @brief Deactivate an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- USB_OTG_EPTypeDef *ep = NULL;
-
- if ((ep_addr & 0x80) == 0x80)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
- }
- ep->num = ep_addr & 0x7F;
-
- ep->is_in = (0x80 & ep_addr) != 0;
-
- __HAL_LOCK(hpcd);
- USB_DeactivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the reception buffer
- * @param len: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
- USB_OTG_EPTypeDef *ep = NULL;
-
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 0;
- ep->num = ep_addr & 0x7F;
-
- if (hpcd->Init.dma_enable == 1)
- {
- ep->dma_addr = (uint32_t)pBuf;
- }
-
- if ((ep_addr & 0x7F) == 0 )
- {
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
- }
- else
- {
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Get Received Data Size.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval Data Size
- */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
-}
-
-/**
- * @brief Send an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the transmission buffer
- * @param len: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
- USB_OTG_EPTypeDef *ep = NULL;
-
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 1;
- ep->num = ep_addr & 0x7F;
-
- if (hpcd->Init.dma_enable == 1)
- {
- ep->dma_addr = (uint32_t)pBuf;
- }
-
- if ((ep_addr & 0x7F) == 0 )
- {
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
- }
- else
- {
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set a STALL condition over an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- USB_OTG_EPTypeDef *ep = NULL;
-
- if ((0x80 & ep_addr) == 0x80)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 1;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
-
-
- __HAL_LOCK(hpcd);
- USB_EPSetStall(hpcd->Instance , ep);
- if((ep_addr & 0x7F) == 0)
- {
- USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
- }
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear a STALL condition over in an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- USB_OTG_EPTypeDef *ep = NULL;
-
- if ((0x80 & ep_addr) == 0x80)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 0;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
-
- __HAL_LOCK(hpcd);
- USB_EPClearStall(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Flush an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- __HAL_LOCK(hpcd);
-
- if ((ep_addr & 0x80) == 0x80)
- {
- USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
- }
- else
- {
- USB_FlushRxFifo(hpcd->Instance);
- }
-
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Activate remote wake-up signalling.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
- /* Activate Remote wake-up signaling */
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
- }
- return HAL_OK;
-}
-
-/**
- * @brief De-activate remote wake-up signalling.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- /* De-activate Remote wake-up signaling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the PCD handle state.
- * @param hpcd: PCD handle
- * @retval HAL state
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
- return hpcd->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
- * @{
- */
-
-/**
- * @brief Check FIFO for the next packet to be loaded.
- * @param hpcd: PCD handle
- * @param epnum : endpoint number
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- USB_OTG_EPTypeDef *ep = NULL;
- int32_t len = 0U;
- uint32_t len32b = 0U;
- uint32_t fifoemptymsk = 0U;
-
- ep = &hpcd->IN_ep[epnum];
- len = ep->xfer_len - ep->xfer_count;
-
- if (len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
-
-
- len32b = (len + 3) / 4;
-
- while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
- ep->xfer_count < ep->xfer_len &&
- ep->xfer_len != 0)
- {
- /* Write the FIFO */
- len = ep->xfer_len - ep->xfer_count;
-
- if (len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
- len32b = (len + 3) / 4;
-
- USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
-
- ep->xfer_buff += len;
- ep->xfer_count += len;
- }
-
- if(len <= 0)
- {
- fifoemptymsk = 0x1 << epnum;
- USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
deleted file mode 100644
index 04c3eb8..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pcd_ex.c
- * @author MCD Application Team
- * @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Extended features functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCDEx PCDEx
- * @brief PCD Extended HAL module driver
- * @{
- */
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief PCDEx control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Update FIFO configuration
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set Tx FIFO.
- * @param hpcd: PCD handle
- * @param fifo: The number of Tx fifo
- * @param size: Fifo size
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
- uint8_t i = 0;
- uint32_t Tx_Offset = 0;
-
- /* TXn min size = 16 words. (n : Transmit FIFO index)
- When a TxFIFO is not used, the Configuration should be as follows:
- case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
- --> Txm can use the space allocated for Txn.
- case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
- --> Txn should be configured with the minimum space of 16 words
- The FIFO is used optimally when used TxFIFOs are allocated in the top
- of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
- When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-
- Tx_Offset = hpcd->Instance->GRXFSIZ;
-
- if(fifo == 0)
- {
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
- }
- else
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
- for (i = 0; i < (fifo - 1); i++)
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
- }
-
- /* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Rx FIFO.
- * @param hpcd: PCD handle
- * @param size: Size of Rx fifo
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
- hpcd->Instance->GRXFSIZ = size;
-
- return HAL_OK;
-}
-
-/**
- * @brief Activate LPM Feature.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- hpcd->lpm_active = ENABLE;
- hpcd->LPM_State = LPM_L0;
- USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
- USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-
- return HAL_OK;
-}
-
-/**
- * @brief De-activate LPM feature.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- hpcd->lpm_active = DISABLE;
- USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
- USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
-
- return HAL_OK;
-}
-
-#if defined (USB_OTG_GCCFG_BCDEN)
-/**
- * @brief Handle Battery Charging Process.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- uint32_t tickstart = HAL_GetTick();
-
- /* Start BCD When device is connected */
- if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
- {
- /* Enable DCD : Data Contact Detect */
- USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
-
- /* Wait Detect flag or a timeout is happen*/
- while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > 1000)
- {
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
- return;
- }
- }
-
- /* Right response got */
- HAL_Delay(100);
-
- /* Check Detect flag*/
- if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
- {
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
- }
-
- /*Primary detection: checks if connected to Standard Downstream Port
- (without charging capability) */
- USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
- USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
- HAL_Delay(100);
-
- if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
- {
- /* Case of Standard Downstream Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
- }
- else
- {
- /* start secondary detection to check connection to Charging Downstream
- Port or Dedicated Charging Port */
- USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
- USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
- HAL_Delay(100);
-
- if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
- {
- /* case Dedicated Charging Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
- }
- else
- {
- /* case Charging Downstream Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
- }
- }
- /* Battery Charging capability discovery finished */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
- }
-}
-
-/**
- * @brief Activate BatteryCharging feature.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- hpcd->battery_charging_active = ENABLE;
- USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
-
- /* Enable DCD : Data Contact Detect */
- USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate BatteryCharging feature.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- hpcd->battery_charging_active = DISABLE;
- USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
- return HAL_OK;
-}
-
-/**
- * @brief Send BatteryCharging message to user layer callback.
- * @param hpcd: PCD handle
- * @param msg: LPM message
- * @retval HAL status
- */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(msg);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCDEx_BCD_Callback could be implemented in the user file
- */
-}
-#endif /* USB_OTG_GCCFG_BCDEN */
-
-/**
- * @brief Send LPM message to user layer callback.
- * @param hpcd: PCD handle
- * @param msg: LPM message
- * @retval HAL status
- */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(msg);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCDEx_LPM_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
deleted file mode 100644
index 535df1d..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pwr.c
- * @author MCD Application Team
- * @brief PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWR_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
- * @{
- */
-#define PVD_MODE_IT ((uint32_t)0x00010000U)
-#define PVD_MODE_EVT ((uint32_t)0x00020000U)
-#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
-#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
-#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
- * @brief Initialization and De-Initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and De-Initialization functions #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() macro.
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
- * @note This functionality is not available in this product.
- * The prototype is kept just to maintain compatibility with other products.
- * @retval None
- */
-void HAL_PWR_DeInit(void)
-{
-}
-
-/**
- * @brief Enable access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void)
-{
- /* Enable access to RTC and backup registers */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void)
-{
- /* Disable access to RTC and backup registers */
- CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- *** PVD configuration ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).
- (+) A PVDO flag is available to indicate if VDD is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line 16 to generate an interrupt if enabled.
- It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
- (+) The PVD is stopped in Standby mode.
-
- *** Wake-up pin configuration ***
- ================================
- [..]
- (+) Wake-up pin is used to wake up the system from Standby mode.
- The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.
- The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.
- (+) There are up to six Wake-up pin in the STM32H7 devices family.
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The device present 3 principles low-power modes features:
- (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.
- (+) STOP mode: all clocks are stoppedand the regulator running in main or low power mode.
- (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply
- regulator is powered off.
-
- *** SLEEP mode ***
- ==================
- [..]
- (+) Entry:
- The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
- function.
-
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- -@@- The Regulator parameter is not used for the STM32H7 family
- and is kept as parameter just to maintain compatibility with the
- lower power families (STM32L).
- (+) Exit:
- Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** STOP mode ***
- =================
- [..]
- In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
- To minimize the consumption In Stop mode, FLASH can be powered off before
- entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
- It can be switched on again by software after exiting the Stop mode using
- the HAL_PWREx_DisableFlashPowerDown() function.
-
- (+) Entry:
- The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
- function with:
- (++) Regulator:
- (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
- (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
- (++) STOPEntry:
- (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
- (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
- (+) Exit:
- Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- *** STANDBY mode ***
- ====================
- [..]
- (+)
- The system Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
- The system is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
- [..]
- The voltage regulator is OFF.
- (++) Entry:
- (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
- (++) Exit:
- (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
- wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event or a time-stamp event, without depending on
- an external interrupt (Auto-wakeup mode).
- (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to configure the RTC to detect the tamper or time stamp event using the
- HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
- configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
- * information for the PVD.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS[7:5] bits according to PVDLevel value */
- MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-}
-
-/**
- * @brief Enable the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void)
-{
- /* Enable the power voltage detector */
- SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
-}
-
-/**
- * @brief Disable the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void)
-{
- /* Disable the power voltage detector */
- CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
-}
-
-/**
- * @brief Enable the WakeUp PINx functionality.
- * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
- * This parameter can be one of the following legacy values, which sets the default:
- * polarity detection on high level (rising edge):
- * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4,
- * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where
- * the user can explicitly states the enabled pin and the chosen polarity.
- * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
- * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
- * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
- * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
- * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
- * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
- * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
-{
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
-
- /* Enable and Specify the Wake-Up pin polarity and the pull configuration
- for the event detection (rising or falling edge) */
- MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1
- * @arg PWR_WAKEUP_PIN2
- * @arg PWR_WAKEUP_PIN3
- * @arg PWR_WAKEUP_PIN4
- * @arg PWR_WAKEUP_PIN5
- * @arg PWR_WAKEUP_PIN6
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
- CLEAR_BIT(PWR->WKUPEPR, WakeUpPinx);
-}
-
-/**
- * @brief Enter CM7 core to Sleep mode.
- * @param Regulator: Specifies the regulator state in SLEEP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
- * @note This parameter is not used for the STM32H7 family and is kept as parameter
- * just to maintain compatibility with the lower power families.
- * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select SLEEP mode entry */
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-}
-
-/**
- * @brief Enter the system to STOP mode.
- * @note In System Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting System Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as default system wakeup clock.
- * @note In System STOP mode, when the voltage regulator operates in low power mode,
- * an additional startup delay is incurred when the system is waking up.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
- * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Select the regulator state in Stop mode */
- tmpreg = PWR->CR1;
- /* Clear PDDS and LPDS bits */
- tmpreg &= (uint32_t)~(PWR_CR1_LPDS);
-
- /* Set LPDS bit according to Regulator value */
- tmpreg |= Regulator;
-
- /* Store the new value */
- PWR->CR1 = tmpreg;
-
- /* Keep DSTOP mode when D1 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
-
- /* Keep DSTOP mode when D2 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
-
- /* Keep DSTOP mode when D3 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Ensure that all instructions done before entering STOP mode */
- __DSB();
- __ISB();
-
- /* Select Stop mode entry */
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enter the system to STANDBY mode.
- * @note The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
- * @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @retval None.
- */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
- /* Keep DSTANDBY mode when D1 domain enters Deepsleep */
- SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
-
- /* Keep DSTANDBY mode when D2 domain enters Deepsleep */
- SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
-
- /* Keep DSTANDBY mode when D3 domain enters Deepsleep */
- SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * Setting this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
- * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enable CORTEX SEVONPEND bit.
- * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void)
-{
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Disable CORTEX SEVONPEND bit.
- * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void)
-{
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief This function handles the PWR PVD interrupt request.
- * @note This API should be called under the PVD_IRQHandler().
- * @retval None
- */
-void HAL_PWR_PVD_IRQHandler(void)
-{
- /* PVD EXTI line interrupt detected */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PWR EXTI pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
-}
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_PVDCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
deleted file mode 100644
index 7bf6be6..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,1291 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_pwr_ex.c
- * @author MCD Application Team
- * @brief Extended PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of PWR extension peripheral:
- * + Peripheral Extended features functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWREx PWREx
- * @brief PWR Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Constants
- * @{
- */
-
-/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
- * @{
- */
-#define AVD_MODE_IT ((uint32_t)0x00010000U)
-#define AVD_MODE_EVT ((uint32_t)0x00020000U)
-#define AVD_RISING_EDGE ((uint32_t)0x00000001U)
-#define AVD_FALLING_EDGE ((uint32_t)0x00000002U)
-#define AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
-/**
- * @}
- */
-
-/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
- * @{
- */
-#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
- * @{
- */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Power supply control functions
- * @brief Power supply control functions
- *
-@verbatim
-
- ===============================================================================
- ##### Power supply control functions #####
- ===============================================================================
-
- *** Power supply configuration ***
- ==================================
- [..]
- When the system is powered on, the POR monitors VDD supply. Once VDD is above the
- POR threshold level, the voltage regulator is enabled in the default supply
- configuration:
- (+) The Voltage converter output level is set at 1.0 V in accordance with the VOS3
- level configured in PWR D3 domain control register (PWR_D3CR).
- (+) The system is kept in reset mode as long as VCORE is not ok.
- (+) Once VCORE is ok, the system is taken out of reset and the HSI oscillator is enabled.
- (+) Once the oscillator is stable, the system is initialized: Flash memory and option
- bytes are loaded and the CPU starts in Run* mode.
- (+) The software shall then initialize the system including supply configuration
- programming using the HAL_PWREx_ConfigSupply(SupplySource) with:
- (++) SupplySource:
- (+++) PWR_LDO_SUPPLY: VCORE Power Domains are supplied from the LDO according to
- VOS. LDO power mode (Main, LP, Off) will follow system low-power
- modes.
- (+++) PWR_EXTERNAL_SOURCE_SUPPLY: VCORE supplied from external source and LDO bypassed,
- voltage monitoring still active.
- (+) Once the supply configuration has been configured, the HAL_PWREx_ConfigSupply
- function checks the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
- to guarantee a valid voltage levels:
- (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in
- limited Run* mode, write accesses to the RAMs are not permitted and VOS shall
- not be changed.
- (++) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal
- Run mode, write accesses to RAMs are allowed and VOS can be changed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure the system Power Supply.
- * @param SupplySource: Specifies the Power Supply source to set after a system startup.
- * This parameter can be one of the following values:
- * @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains.
- *
- * @arg PWR_EXTERNAL_SOURCE_SUPPLY The LDO regulator is Bypassed.
- * The Vcore Power Domains are supplied from external source.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_SUPPLY(SupplySource));
-
- /* Set the power supply configuration */
- MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till voltage level flag is set and supply configuration update flag is reset */
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY) && __HAL_PWR_GET_FLAG(PWR_FLAG_SCUEN))
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Get the power supply configuration.
- * @retval The supply configuration.
- */
-uint32_t HAL_PWREx_GetSupplyConfig(void)
-{
- return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
-}
-
-
-/**
- * @brief Configure the main internal regulator output voltage.
- * @param VoltageScaling: Specifies the regulator output voltage to achieve
- * a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode.
- * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode.
- * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode.
- * @note When moving from Range 1 to Range 2, the system frequency must be decreased
- * before calling HAL_PWREx_ControlVoltageScaling() API.
- * When moving from Range 2 to Range 1, the system frequency can be increased
- * after calling HAL_PWREx_ControlVoltageScaling() API.
- * @note When moving from a Range to an other one, the API waits for VOSRDY flag to be
- * set before returning the status. If the flag is not set within 1000 microseconds,
- * HAL_TIMEOUT status is reported.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
- uint32_t tickstart = 0;
-
- assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
-
- /* Set the voltage range */
- MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the VOSRDY flag is set */
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the main internal regulator output voltage.
- * Reflecting the last VOS value applied to the PMU.
- * @retval The actual applied VOS for VDD11 Voltage Scaling selection.
- */
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
- return (PWR->CSR1 & PWR_CSR1_ACTVOS);
-}
-
-/**
- * @brief Configure the main internal regulator output voltage in STOP mode.
- * @param VoltageScaling: Specifies the regulator output voltage when the system enters
- * STOP mode to achieve a tradeoff between performance and power consumption.
- * This parameter can be one of the following values:
- * @arg PWR_REGULATOR_SVOS_SCALE3: Regulator voltage output range 3 mode.
- * @arg PWR_REGULATOR_SVOS_SCALE4: Regulator voltage output range 4 mode.
- * @arg PWR_REGULATOR_SVOS_SCALE5: Regulator voltage output range 5 mode.
- * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator
- * in Low-power (LP) mode to further reduce power consumption.
- * When preselecting SVOS3, the use of the voltage regulator low-power mode (LP)
- * can be selected by LPDS register bit.
- * @note The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting
- * from system Stop mode.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)
-{
- assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));
-
- /* Set the stop mode voltage range */
- MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the main internal regulator output voltage in STOP mode.
- * @retval The actual applied VOS for VDD11 Voltage Scaling selection.
- */
-uint32_t HAL_PWREx_GetStopModeVoltageRange(void)
-{
- return (PWR->CR1 & PWR_CR1_SVOS);
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWREx_Exported_Functions_Group2 Low power control functions
- * @brief Low power control functions
- *
-@verbatim
-
- ===============================================================================
- ##### Low power control functions #####
- ===============================================================================
-
- *** Domains Low Power modes configuration ***
- =============================================
- [..]
- The system present 3 principles domains (D1, D2 and D3) that can be operated
- in low-power modes (DSTOP or DSTANDBY mode):
-
- (+) DSTOP mode to enters a domain to STOP mode:
- (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
- subsystem is in CSTOP mode and has allocated peripheral in the domain.
- In DSTOP mode the domain bus matrix clock is stopped.
- (++) The system enters STOP mode using one of the following scenarios:
- (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains enter DSTOP mode.
- (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains enter DSTOP mode.
- (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains enter DSTOP mode.
- (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain enters DSTOP mode.
- (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain enters DSTOP mode.
- (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain enters DSTOP mode.
- (+++) D1, D2 and D3 domains enter DSTOP mode.
- (++) When the system enters STOP mode, the clocks are stopped and the regulator is running
- in main or low power mode.
- (++) D3 domain can be kept in Run mode regardless of the CPU status when enter
- STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
-
- (+) DSTANDBY mode to enters a domain to STANDBY mode:
- (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control register
- (PWR_CPUCR) for the Dn domain selects Standby mode.
- (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter DSTANDBY mode.
- Consequently the VCORE supply regulator is powered off.
-
- *** DSTOP mode ***
- ==================
- [..]
- In DStop mode the domain bus matrix clock is stopped.
- The Flash memory can enter low-power Stop mode when it is enabled through FLPS in
- PWR_CR1 register. This allows a trade-off between domain DStop restart time and low
- power consumption.
- [..]
- In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a
- kernel clock request are still able to operate.
- [..]
- Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
- in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
-
- (+) Entry:
- The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, STOPEntry, Domain)
- function with:
- (++) Regulator:
- (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
- (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
- (++) STOPEntry:
- (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
- (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
- (++) Domain:
- (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTOP mode.
- (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTOP mode.
- (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTOP mode.
-
- (+) Exit:
- Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
- *** DSTANDBY mode ***
- ====================
- [..]
- In DStandby mode:
- (+) The domain bus matrix clock is stopped.
- (+) The domain is powered down and the domain RAM and register contents are lost.
- [..]
- Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
- in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
-
- (+) Entry:
- The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode(Domain) function with:
- (++) Domain:
- (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTANDBY mode.
- (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTANDBY mode.
- (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTANDBY mode.
-
- (+) Exit:
- WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
- wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
-
- *** Keep D3 in RUN mode ***
- ===========================
- [..]
- D3 domain can be kept in Run mode regardless of the CPU status when enter
- STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function with:
- (+) D3State:
- (++) PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
- (++) PWR_D3_DOMAIN_RUN: D3 domain remains in Run mode regardless of CPU subsystem mode.
-
- *** FLASH Power Down configuration ****
- =======================================
- [..]
- By setting the FLPS bit in the PWR_CR1 register using the HAL_PWREx_EnableFlashPowerDown()
- function, the Flash memory also enters power down mode when the device enters Stop mode.
- When the Flash memory is in power down mode, an additional startup delay is incurred when
- waking up from Stop mode.
-
- *** Wakeup Pins configuration ****
- ===================================
- [..]
- Wakeup pins allow the system to exit from Standby mode. The configuration of
- wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) function with:
- (+) sPinParams: structure to enable and configure a wakeup pin:
- (++) WakeUpPin: Wakeup pin to be enabled.
- (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
- (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
- [..]
- The wakeup pins are internally connected to the EXTI lines [55-60] to generate an interrupt
- if enabled. The EXTI lines configuration is done by the HAL_EXTI_Dx_EventInputConfig() functions
- defined in the stm32h7xxhal.c file.
- [..]
- When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is called
- and the appropriate flag is set in the PWR_WKUPFR register. Then in the HAL_PWREx_WAKEUP_PIN_IRQHandler
- function the wakeup pin flag will be cleared and the appropriate user callback will be called.
- The user can add his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enter a Domain to DSTOP mode.
- * @note In DStop mode the domain bus matrix clock is stopped.
- * @note The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,
- * the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU
- * control register (PWR_CPUCR) for any domain request Stop.
- * @note In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or
- * DStandby mode.
- * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
- * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
- * @note In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the
- * peripherals that have a kernel clock request to select HSI or CSI as source,
- * are still able to operate.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction
- * @arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction
- * @param Domain: Specifies the Domain to enter STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.
- * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.
- * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.
- * @retval None
- */
-void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
- assert_param(IS_PWR_DOMAIN(Domain));
-
- /* Select the regulator state in Stop mode */
- MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, Regulator);
-
- /* Select the domain Power Down DeepSleep */
- if (Domain == PWR_D1_DOMAIN)
- {
- /* Keep DSTOP mode when D1 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
-
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Ensure that all instructions done before entering STOP mode */
- __DSB();
- __ISB();
-
- /* Select Stop mode entry */
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
- }
- else if (Domain == PWR_D2_DOMAIN)
- {
- /* Keep DSTOP mode when D2 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
-
- }
- else
- {
- /* Keep DSTOP mode when D3 domain enters Deepsleep */
- CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
-
- }
-}
-
-/**
- * @brief Enter a Domain to DSTANDBY mode.
- * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain
- * select Standby mode. When the system enters Standby mode, the voltage regulator
- * is disabled.
- * @note When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn
- * bit to select Stop mode, the domain remains in DStandby mode. The domain will only
- * exit DStandby when the CPU allocates a peripheral in the domain.
- * @note The system D3 domain enters Standby mode only when the D1 and D2 domain are in
- * DStandby.
- * @note Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
- * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
- * @param Domain: Specifies the Domain to enter to STANDBY mode.
- * This parameter can be one of the following values:
- * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.
- * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
- * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.
- * @retval None
- */
-void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)
-{
- /* Check the parameters */
- assert_param(IS_PWR_DOMAIN(Domain));
-
- /* Select the domain Power Down DeepSleep */
- if (Domain == PWR_D1_DOMAIN)
- {
- /* Allow DSTANDBY mode when D1 domain enters to Deepsleep */
- SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
-
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
-
- /* Request Wait For Interrupt */
- __WFI();
- }
- else if (Domain == PWR_D2_DOMAIN)
- {
- /* Allow DSTANDBY mode when D2 domain enters to Deepsleep */
- SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
-
- }
- else
- {
- /* Allow DSTANDBY mode when D3 domain enters to Deepsleep */
- SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
-
- }
-}
-
-/**
- * @brief Configure the D3 Domain state when the CPU is in low power mode.
- * @param D3State: Specifies the D3 state.
- * This parameter can be one of the following values:
- * @arg PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode.
- * @arg PWR_D3_DOMAIN_RUN : D3 domain will stay in RUN mode regardless of the
- * CPU sub-system mode.
- * @retval None
- */
-void HAL_PWREx_ConfigD3Domain(uint32_t D3State)
-{
- /* Check the parameters */
- assert_param(IS_D3_STATE(D3State));
-
- /* Keep D3 in run mode */
- MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
-}
-
-
-
-
-
-/**
- * @brief Enable the Flash Power Down in Stop mode.
- * @retval None
- */
-void HAL_PWREx_EnableFlashPowerDown(void)
-{
- /* Enable the Flash Power Down */
- SET_BIT(PWR->CR1, PWR_CR1_FLPS);
-}
-
-/**
- * @brief Disable the Flash Power Down in Stop mode.
- * @retval None
- */
-void HAL_PWREx_DisableFlashPowerDown(void)
-{
- /* Disable the Flash Power Down */
- CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
-}
-
-/**
- * @brief Enable the Wake-up PINx functionality.
- * @param sPinParams: pointer to an PWREx_WakeupPinTypeDef structure that contains
- * the configuration informations for the wake-up Pin.
- * @retval None
- */
-void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams)
-{
- uint32_t pinConfig;
- uint32_t regMask;
- const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
-
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));
- assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));
- assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));
-
- pinConfig = sPinParams->WakeUpPin | \
- (sPinParams->PinPolarity << (POSITION_VAL(sPinParams->WakeUpPin) + PWR_WAKEUP_PINS_POLARITY_REGISTER_OFFSET)) | \
- (sPinParams->PinPull << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_POSITION_OFFSET) + PWR_WAKEUP_PINS_PULL_REGISTER_OFFSET));
-
- regMask = sPinParams->WakeUpPin | \
- (PWR_WKUPEPR_WKUPP_1 << POSITION_VAL(sPinParams->WakeUpPin)) | \
- (pullMask << (POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_POSITION_OFFSET));
-
- /* Enable and Specify the Wake-Up pin polarity and the pull configuration
- for the event detection (rising or falling edge) */
- MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig);
- /* Configure the Wakeup Pin EXTI Line */
- MODIFY_REG(EXTI_D1->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << PWR_EXTI_WAKEUP_PINS_PULL_POSITION_OFFSET));
-}
-
-/**
- * @brief Disable the Wake-up PINx functionality.
- * @param WakeUpPin: Specifies the Wake-Up pin to be disabled.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1: Disable PA0 wake-up PIN.
- * @arg PWR_WAKEUP_PIN2: Disable PA2 wake-up PIN..
- * @arg PWR_WAKEUP_PIN3: Disable PI8 wake-up PIN..
- * @arg PWR_WAKEUP_PIN4: Disable PC13 wake-up PIN..
- * @arg PWR_WAKEUP_PIN5: Disable PI11 wake-up PIN..
- * @arg PWR_WAKEUP_PIN6: Disable PC1 wake-up PIN..
- * @retval None
- */
-void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
-
- /* Disable the WakeUpPin */
- CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
-}
-
-/**
- * @brief Get the Wake-Up Pin flag.
- * @param WakeUpFlag: Specifies the Wake-Up PIN flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_FLAG1: A wakeup event was received from PA0.
- * @arg PWR_WAKEUP_FLAG2: A wakeup event was received from PA2.
- * @arg PWR_WAKEUP_FLAG3: A wakeup event was received from PC1.
- * @arg PWR_WAKEUP_FLAG4: A wakeup event was received from PC13.
- * @arg PWR_WAKEUP_FLAG5: A wakeup event was received from PI8.
- * @arg PWR_WAKEUP_FLAG6: A wakeup event was received from PI11.
- * @retval The Wake-Up pin flag.
- */
-uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
-
- return (PWR->WKUPFR & WakeUpFlag);
-}
-
-/**
- * @brief Clear the Wake-Up pin flag.
- * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_FLAG1: Clear the wakeup event received from PA0.
- * @arg PWR_WAKEUP_FLAG2: Clear the wakeup event received from PA2.
- * @arg PWR_WAKEUP_FLAG3: Clear the wakeup event received from PC1.
- * @arg PWR_WAKEUP_FLAG4: Clear the wakeup event received from PC13.
- * @arg PWR_WAKEUP_FLAG5: Clear the wakeup event received from PI8.
- * @arg PWR_WAKEUP_FLAG6: Clear the wakeup event received from PI11.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
-
- SET_BIT(PWR->WKUPCR, WakeUpFlag);
-
- if((PWR->WKUPFR & WakeUpFlag) != RESET)
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles the PWR WAKEUP PIN interrupt request.
- * @note This API should be called under the WAKEUP_PIN_IRQHandler().
- * @retval None
- */
-void HAL_PWREx_WAKEUP_PIN_IRQHandler(void)
-{
- /* Wakeup pin EXTI line interrupt detected */
- if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != RESET)
- {
- /* Clear PWR WKUPF1 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
-
- /* PWR WKUP1 interrupt user callback */
- HAL_PWREx_WKUP1_Callback();
- }
- else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != RESET)
- {
- /* Clear PWR WKUPF2 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
-
- /* PWR WKUP2 interrupt user callback */
- HAL_PWREx_WKUP2_Callback();
- }
- else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != RESET)
- {
- /* Clear PWR WKUPF3 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
-
- /* PWR WKUP3 interrupt user callback */
- HAL_PWREx_WKUP3_Callback();
- }
- else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != RESET)
- {
- /* Clear PWR WKUPF4 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
-
- /* PWR WKUP4 interrupt user callback */
- HAL_PWREx_WKUP4_Callback();
- }
- else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != RESET)
- {
- /* Clear PWR WKUPF5 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
-
- /* PWR WKUP5 interrupt user callback */
- HAL_PWREx_WKUP5_Callback();
- }
- else
- {
- /* Clear PWR WKUPF6 flag */
- SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
-
- /* PWR WKUP6 interrupt user callback */
- HAL_PWREx_WKUP6_Callback();
- }
-}
-
-/**
- * @brief PWR WKUP1 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP1_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP1Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWR WKUP2 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP2_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP2Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWR WKUP3 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP3_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP3Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWR WKUP4 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP4_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP4Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWR WKUP5 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP5_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP5Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWR WKUP6 interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_WKUP6_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWREx_WKUP6Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
- * @brief Peripherals control functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripherals control functions #####
- ===============================================================================
-
- *** Main and Backup Regulators configuration ***
- ================================================
- [..]
- (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
- the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
- retained even in Standby or VBAT mode when the low power backup regulator
- is enabled. It can be considered as an internal EEPROM when VBAT is
- always present. You can use the HAL_PWREx_EnableBkUpReg() function to
- enable the low power backup regulator.
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
- (+) The backup SRAM is not mass erased by a tamper event. It is read
- protected to prevent confidential data, such as cryptographic private
- key, from being accessed. The backup SRAM can be erased only through
- the Flash interface when a protection level change from level 1 to
- level 0 is requested.
- -@- Refer to the description of Read protection (RDP) in the Flash
- programming manual.
- (+) The main internal regulator can be configured to have a tradeoff between
- performance and power consumption when the device does not operate at
- the maximum frequency. This is done through HAL_PWREx_ControlVoltageScaling(VOS)
- function which configure the VOS bit in PWR_D3CR register.
- (+) The main internal regulator can be configured to operate in Low Power mode
- when the system enter STOP mode to further reduce power consumption.
- This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
- function which configure the SVOS bit in PWR_CR1 register.
- The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from
- system Stop mode.
- -@- Refer to the product datasheets for more details.
-
- *** USB Regulator configuration ***
- ===================================
- [..]
- (+) The USB transceivers are supplied from a dedicated VDD33USB supply that can be
- provided either by the integrated USB regulator, or by an external USB supply.
- (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the VDD33USB
- is then provided from the USB regulator.
- (+) When the USB regulator is enabled, the VDD33USB supply level detector shall
- be enabled through HAL_PWREx_EnableUSBVoltageDetector() function.
- (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() function and VDD33USB
- can be provided from an external supply. In this case VDD33USB and VDD50USB shall
- be connected together
-
- *** VBAT battery charging ***
- =============================
- [..]
- (+) When VDD is present, the external battery connected to VBAT can be charged through an
- internal resistance. VBAT charging can be performed either through a 5 KOhm resistor
- or through a 1.5 KOhm resistor.
- (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function
- with:
- (++) ResistorValue:
- (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
- (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
- (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the Backup Regulator.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
-{
- uint32_t tickstart = 0;
-
- /* Enable the Backup regulator */
- SET_BIT(PWR->CR2, PWR_CR2_BREN);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till Backup regulator ready flag is set */
- while(!__HAL_PWR_GET_FLAG(PWR_FLAG_BRR))
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Backup Regulator.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
-{
- uint32_t tickstart = 0;
-
- /* Disable the Backup regulator */
- CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till Backup regulator ready flag is reset */
- while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Enable the USB Regulator.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void)
-{
- uint32_t tickstart = 0;
-
- /* Enable the USB regulator */
- SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till the USB regulator ready flag is set */
- while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the USB Regulator.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void)
-{
- uint32_t tickstart = 0;
-
- /* Disable the USB regulator */
- CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait till the USB regulator ready flag is reset */
- while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
- {
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Enable the USB voltage level detector.
- * @retval None
- */
-void HAL_PWREx_EnableUSBVoltageDetector(void)
-{
- /* Enable the USB voltage detector */
- SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
-}
-
-/**
- * @brief Disable the USB voltage level detector.
- * @retval None
- */
-void HAL_PWREx_DisableUSBVoltageDetector(void)
-{
- /* Disable the USB voltage detector */
- CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
-}
-
-
-/**
- * @brief Enable the Battery charging.
- * When VDD is present, charge the external battery through an internal resistor.
- * @param ResistorValue: Specifies the charging resistor.
- * This parameter can be one of the following values:
- * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
- * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
- * @retval None
- */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
-{
- assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
-
- /* Specify the charging resistor */
- MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, ResistorValue);
-
- /* Enable the Battery charging */
- SET_BIT(PWR->CR3, PWR_CR3_VBE);
-}
-
-
-/**
- * @brief Disable the Battery charging.
- * @retval None
- */
-void HAL_PWREx_DisableBatteryCharging(void)
-{
- /* Disable the Battery charging */
- CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
- * @brief Power Monitoring functions
- *
-@verbatim
-
- ===============================================================================
- ##### Power Monitoring functions #####
- ===============================================================================
-
- *** VBAT and Temperature supervision ***
- ========================================
- [..]
- (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold
- levels: VBAThigh and VBATlow. VBATH flag and VBATL flags in the PWR control register 2
- (PWR_CR2), indicate if VBAT is higher or lower than the threshold.
- (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh
- and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2),
- indicate whether the device temperature is higher or lower than the threshold.
- (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring()
- function and disabled by HAL_PWREx_DisableMonitoring() function.
- (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be:
- PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
- PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
- (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which
- can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
- PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
-
- *** AVD configuration ***
- =========================
- [..]
- (+) The AVD is used to monitor the VDDA power supply by comparing it to a
- threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 register).
- (+) A AVDO flag is available to indicate if VDDA is higher or lower
- than the AVD threshold. This event is internally connected to the EXTI
- line 16 to generate an interrupt if enabled.
- It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
- (+) The AVD is stopped in System Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable the VBAT and temperature monitoring.
- * @retval HAL status
- */
-void HAL_PWREx_EnableMonitoring(void)
-{
- /* Enable the VBAT and Temperature monitoring */
- SET_BIT(PWR->CR2, PWR_CR2_MONEN);
-}
-
-/**
- * @brief Disable the VBAT and temperature monitoring.
- * @retval HAL status
- */
-void HAL_PWREx_DisableMonitoring(void)
-{
- /* Disable the VBAT and Temperature monitoring */
- CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
-}
-
-/**
- * @brief Indicate whether the junction temperature is between, above or below the threshold.
- * @retval Temperature level.
- */
-uint32_t HAL_PWREx_GetTemperatureLevel(void)
-{
- uint32_t tempLevel;
- uint32_t regValue;
-
- /* Read the temperature flags */
- regValue = PWR->CR2 & (PWR_CR2_TEMPH | PWR_CR2_TEMPL);
-
- /* Compare the read value to the temperature threshold */
- if(regValue == PWR_CR2_TEMPL)
- {
- tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
- }
- else if(regValue == PWR_CR2_TEMPH)
- {
- tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
- }
- else
- {
- tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
- }
-
- return tempLevel;
-}
-
-/**
- * @brief Indicate whether the Battery voltage level is between, above or below the threshold.
- * @retval VBAT level.
- */
-uint32_t HAL_PWREx_GetVBATLevel(void)
-{
- uint32_t VBATLevel;
- uint32_t regValue;
-
- /* Read the VBAT flags */
- regValue = PWR->CR2 & (PWR_CR2_VBATH | PWR_CR2_VBATL);
-
- /* Compare the read value to the VBAT threshold */
- if(regValue == PWR_CR2_VBATL)
- {
- VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
- }
- else if(regValue == PWR_CR2_VBATH)
- {
- VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
- }
- else
- {
- VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
- }
-
- return VBATLevel;
-}
-
-/**
- * @brief Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
- * @param sConfigAVD: pointer to an PWR_AVDTypeDef structure that contains the configuration
- * information for the AVD.
- * @note Refer to the electrical characteristics of your device datasheet for more details
- * about the voltage threshold corresponding to each detection level.
- * @retval None
- */
-void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel));
- assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode));
-
- /* Set the ALS[18:17] bits according to AVDLevel value */
- MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
-
- /* Clear any previous config */
- __HAL_PWR_AVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_AVD_EXTI_DISABLE_IT();
- __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();
- __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();
-
- /* Configure the interrupt mode */
- if(AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT))
- {
- __HAL_PWR_AVD_EXTI_ENABLE_IT();
- }
-
- /* Configure the event mode */
- if(AVD_MODE_EVT == (sConfigAVD->Mode & AVD_MODE_EVT))
- {
- __HAL_PWR_AVD_EXTI_ENABLE_EVENT();
- }
- /* Configure the edge */
- if(AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE))
- {
- __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if(AVD_FALLING_EDGE == (sConfigAVD->Mode & AVD_FALLING_EDGE))
- {
- __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();
- }
-}
-
-/**
- * @brief Enable the Analog Voltage Detector(AVD).
- * @retval None
- */
-void HAL_PWREx_EnableAVD(void)
-{
- /* Enable the Analog Voltage Detector */
- SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
-}
-
-/**
- * @brief Disable the Analog Voltage Detector(AVD).
- * @retval None
- */
-void HAL_PWREx_DisableAVD(void)
-{
- /* Disable the Analog Voltage Detector */
- CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
-}
-
-/**
- * @brief This function handles the PWR PVD/AVD interrupt request.
- * @note This API should be called under the PVD_AVD_IRQHandler().
- * @retval None
- */
-void HAL_PWREx_PVD_AVD_IRQHandler(void)
-{
- /* PVD EXTI line interrupt detected */
- if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != RESET)
- {
- /* Check PWR EXTI flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PWR EXTI pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
- }
-
- /* AVD EXTI line interrupt detected */
- if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != RESET)
- {
- /* Check PWR EXTI flag */
- if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR AVD interrupt user callback */
- HAL_PWREx_AVDCallback();
-
- /* Clear PWR EXTI pending bit */
- __HAL_PWR_AVD_EXTI_CLEAR_FLAG();
- }
- }
-}
-
-/**
- * @brief PWR AVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWREx_AVDCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_AVDCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
deleted file mode 100644
index 9518477..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
+++ /dev/null
@@ -1,2205 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_qspi.c
- * @author MCD Application Team
- * @brief QSPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the QuadSPI interface (QSPI).
- * + Initialization and de-initialization functions
- * + Indirect functional mode management
- * + Memory-mapped functional mode management
- * + Auto-polling functional mode management
- * + Interrupts and flags management
- * + MDMA channel configuration for indirect functional mode
- * + Errors management and abort functionality
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- *** Initialization ***
- ======================
- [..]
- (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
- (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
- (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
- (++) If interrupt mode is used, enable and configure QuadSPI global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
- with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
- link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
- MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (#) Configure the flash size, the clock prescaler, the fifo threshold, the
- clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
-
- *** Indirect functional mode ***
- ================================
- [..]
- (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
- functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used and if present the number of bytes.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (#) If no data is required for the command, it is sent directly to the memory :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
- HAL_QSPI_Transmit_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
- HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
- HAL_QSPI_Receive_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
- HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
-
- *** Auto-polling functional mode ***
- ====================================
- [..]
- (#) Configure the command sequence and the auto-polling functional mode using the
- HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
- the polling interval and the automatic stop activation.
- (#) After the configuration :
- (++) In polling mode, the output of the function is done when the status match is reached. The
- automatic stop is activated to avoid an infinite loop.
- (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
-
- *** Memory-mapped functional mode ***
- =====================================
- [..]
- (#) Configure the command sequence and the memory-mapped functional mode using the
- HAL_QSPI_MemoryMapped() functions :
- (++) Instruction phase : the mode used and if present the instruction opcode.
- (++) Address phase : the mode used and the size.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
- bytes values.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
- if activated.
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) The timeout activation and the timeout period.
- (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
- the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
-
- *** Errors management and abort functionality ***
- =================================================
- [..]
- (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
- flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
- complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bi is set.
-
- *** Control functions ***
- =========================
- [..]
- (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
- (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
- (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
- (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
-
- *** Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- (#) Workarounds Implemented inside HAL Driver
- (++) Extra data written in the FIFO at the end of a read transfer
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup QSPI QSPI
- * @brief QSPI HAL module driver
- * @{
- */
-#ifdef HAL_QSPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-
-/* Private define ------------------------------------------------------------*/
-/** @defgroup QSPI_Private_Constants QSPI Private Constants
- * @{
- */
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Instance));
- assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
- assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
- assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
- assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
- assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
- assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
- assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
-
- if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
- {
- assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
- }
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hqspi->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_QSPI_MspInit(hqspi);
-
- /* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
- }
-
- /* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if(status == HAL_OK)
- {
- /* Configure QSPI Clock Prescaler and Sample Shift */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
- ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
- hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
-
- /* Configure QSPI Flash Size, CS High Time and Clock Mode */
- MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
- ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) |
- hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
- /* Enable the QSPI peripheral */
- __HAL_QSPI_ENABLE(hqspi);
-
- /* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Initialize the QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief De-Initialize the QSPI peripheral.
- * @param hqspi: QSPI handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Check the QSPI handle allocation */
- if(hqspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- /* Disable the QSPI Peripheral Clock */
- __HAL_QSPI_DISABLE(hqspi);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_QSPI_MspDeInit(hqspi);
-
- /* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Initialize the QSPI state */
- hqspi->State = HAL_QSPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the QSPI MSP.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the QSPI MSP.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
- * @brief QSPI Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to :
- (+) Handle the interrupts.
- (+) Handle the command sequence.
- (+) Transmit data in blocking, interrupt or DMA mode.
- (+) Receive data in blocking, interrupt or DMA mode.
- (+) Manage the auto-polling functional mode.
- (+) Manage the memory-mapped functional mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle QSPI interrupt request.
- * @param hqspi: QSPI handle
- * @retval None
- */
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
-{
- __IO uint32_t *data_reg;
- uint32_t flag = READ_REG(hqspi->Instance->SR);
- uint32_t itsource = READ_REG(hqspi->Instance->CR);
-
- /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
- {
- data_reg = &hqspi->Instance->DR;
-
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
- {
- /* Transmission process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
- {
- if (hqspi->TxXferCount > 0)
- {
- /* Fill the FIFO until the threshold is reached */
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
- hqspi->TxXferCount--;
- }
- else
- {
- /* No more data available for the transfer */
- /* Disable the QSPI FIFO Threshold Interrupt */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
- break;
- }
- }
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
- {
- /* Receiving Process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
- {
- if (hqspi->RxXferCount > 0)
- {
- /* Read the FIFO until the threshold is reached */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
- hqspi->RxXferCount--;
- }
- else
- {
- /* All data have been received for the transfer */
- /* Disable the QSPI FIFO Threshold Interrupt */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
- break;
- }
- }
- }
-
- /* FIFO Threshold callback */
- HAL_QSPI_FifoThresholdCallback(hqspi);
- }
-
- /* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
-
- /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
- /* Transfer complete callback */
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
- {
- if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the MDMA channel */
- __HAL_MDMA_DISABLE(hqspi->hmdma);
- }
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* TX Complete callback */
- HAL_QSPI_TxCpltCallback(hqspi);
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
- {
- if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the MDMA channel */
- __HAL_MDMA_DISABLE(hqspi->hmdma);
- }
- else
- {
- data_reg = &hqspi->Instance->DR;
- while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
- {
- if (hqspi->RxXferCount > 0)
- {
- /* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
- hqspi->RxXferCount--;
- }
- else
- {
- /* All data have been received for the transfer */
- break;
- }
- }
- }
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* RX Complete callback */
- HAL_QSPI_RxCpltCallback(hqspi);
- }
- else if(hqspi->State == HAL_QSPI_STATE_BUSY)
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Command Complete callback */
- HAL_QSPI_CmdCpltCallback(hqspi);
- }
- else if(hqspi->State == HAL_QSPI_STATE_ABORT)
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
- {
- /* Abort called by the user */
-
- /* Abort Complete callback */
- HAL_QSPI_AbortCpltCallback(hqspi);
- }
- else
- {
- /* Abort due to an error (eg : MDMA error) */
-
- /* Error callback */
- HAL_QSPI_ErrorCallback(hqspi);
- }
- }
- }
-
- /* QSPI Status Match interrupt occurred ------------------------------------*/
- else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
-
- /* Check if the automatic poll mode stop is activated */
- if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
- {
- /* Disable the QSPI Transfer Error and Status Match Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
-
- /* Status match callback */
- HAL_QSPI_StatusMatchCallback(hqspi);
- }
-
- /* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
-
- /* Disable all the QSPI Interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
- /* Set error code */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-
- if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Disable the MDMA channel */
- hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_MDMA_Abort_IT(hqspi->hmdma);
-
- }
- else
- {
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Error callback */
- HAL_QSPI_ErrorCallback(hqspi);
- }
- }
-
- /* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
- {
- /* Clear interrupt */
- WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
-
- /* Timeout callback */
- HAL_QSPI_TimeOutCallback(hqspi);
- }
-}
-
-/**
- * @brief Set the command configuration.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Read or Write Modes
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* When there is no data phase, the transfer start as soon as the configuration is done
- so wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
-
- }
- else
- {
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Set the command configuration in interrupt mode.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @note This function is used only in Indirect Read or Write Modes
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
- }
-
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- if (cmd->DataMode == QSPI_DATA_NONE)
- {
- /* When there is no data phase, the transfer start as soon as the configuration is done
- so activate TC and TE interrupts */
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI Transfer Error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
- }
- else
- {
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Write Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
- __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- while(hqspi->TxXferCount > 0)
- {
- /* Wait until FT flag is set to send data */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
-
- if (status != HAL_OK)
- {
- break;
- }
-
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
- hqspi->TxXferCount--;
- }
-
- if (status == HAL_OK)
- {
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Clear Transfer Complete bit */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- }
- }
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- return status;
-}
-
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Timeout duration
- * @note This function is used only in Indirect Read Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
- __IO uint32_t *data_reg = &hqspi->Instance->DR;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pRxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- while(hqspi->RxXferCount > 0)
- {
- /* Wait until FT or TC flag is set to read received data */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
-
- if (status != HAL_OK)
- {
- break;
- }
-
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
- hqspi->RxXferCount--;
- }
-
- if (status == HAL_OK)
- {
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Clear Transfer Complete bit */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
- }
- }
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- return status;
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @note This function is used only in Indirect Write Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @note This function is used only in Indirect Read Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pRxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @note This function is used only in Indirect Write Mode
- * @note If MDMA peripheral access is configured as halfword, the number
- * of data and the fifo threshold should be aligned on halfword
- * @note If MDMA peripheral access is configured as word, the number
- * of data and the fifo threshold should be aligned on word
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Clear the error code */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
- /* Set the QSPI MDMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
-
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
-
- if(hqspi->hmdma->Init.DestinationInc != MDMA_DEST_INC_DISABLE)
- {
- /* Update MDMA handle with the correct DestinationInc and SourceInc field for Write operation */
- hqspi->hmdma->Init.DestinationInc = MDMA_DEST_INC_DISABLE;
- hqspi->hmdma->Init.SourceInc = MDMA_SRC_INC_BYTE;
- HAL_MDMA_Init(hqspi->hmdma);
- }
-
- /* Enable the QSPI transmit MDMA */
- tmp = (uint32_t*)&pData;
- HAL_MDMA_Start_IT(hqspi->hmdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
- else
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer.
- * @note This function is used only in Indirect Read Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Clear the error code */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- if(pData != NULL )
- {
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
- hqspi->pRxBuffPtr = pData;
-
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
-
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
-
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
-
-
- /* QSPI need to be configured to indirect mode before starting
- the MDMA to avoid primatury triggering for the MDMA transfert */
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- if(hqspi->hmdma->Init.DestinationInc != MDMA_DEST_INC_BYTE)
- {
- /* Update MDMA handle with the correct DestinationInc and SourceInc field for Read operation */
- hqspi->hmdma->Init.DestinationInc = MDMA_DEST_INC_BYTE;
- hqspi->hmdma->Init.SourceInc = MDMA_SRC_INC_DISABLE;
- HAL_MDMA_Init(hqspi->hmdma);
- }
-
- /* Enable the MDMA */
- tmp = (uint32_t*)&pData;
- HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize, 1);
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- return status;
-}
-
-/**
- * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
- * @param Timeout : Timeout duration
- * @note This function is used only in Automatic Polling Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: PSMAR register with the status match value */
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
- /* Configure QSPI: PSMKR register with the status mask value */
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
- /* Configure QSPI: PIR register with the interval value */
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop enabled
- (otherwise there will be an infinite loop in blocking mode) */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
- (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
- /* Call the configuration function */
- cmd->NbData = cfg->StatusBytesSize;
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
- /* Wait until SM flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
-
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
- * @note This function is used only in Automatic Polling Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
- assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: PSMAR register with the status match value */
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
- /* Configure QSPI: PSMKR register with the status mask value */
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
- /* Configure QSPI: PIR register with the interval value */
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop mode */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
- (cfg->MatchMode | cfg->AutomaticStop));
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
- /* Call the configuration function */
- cmd->NbData = cfg->StatusBytesSize;
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI Transfer Error and status match Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
-
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Configure the Memory Mapped mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the memory mapped configuration information.
- * @note This function is used only in Memory mapped Mode
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
- }
-
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
- }
-
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
- }
-
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
- assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-
- /* Wait till BUSY flag reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
- if (status == HAL_OK)
- {
- /* Configure QSPI: CR register with timeout counter enable */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
-
- if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
- {
- assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-
- /* Configure QSPI: LPTR register with the low-power timeout value */
- WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
-
- /* Enable the QSPI TimeOut Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
- }
-
- /* Call the configuration function */
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Transfer Error callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Abort completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Command completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_CmdCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FIFO Threshold callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Status Match callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_StatusMatchCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timeout callback.
- * @param hqspi: QSPI handle
- * @retval None
- */
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hqspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_QSPI_TimeOutCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
- * @brief QSPI control and State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control and State functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to :
- (+) Check in run-time the state of the driver.
- (+) Check the error code set during last operation.
- (+) Abort any operation.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the QSPI handle state.
- * @param hqspi: QSPI handle
- * @retval HAL state
- */
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
-{
- /* Return QSPI handle state */
- return hqspi->State;
-}
-
-/**
-* @brief Return the QSPI error code.
-* @param hqspi: QSPI handle
-* @retval QSPI Error Code
-*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
-{
- return hqspi->ErrorCode;
-}
-
-/**
-* @brief Abort the current transmission.
-* @param hqspi: QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = HAL_GetTick();
-
- /* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2) != 0)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort MDMA */
- status = HAL_MDMA_Abort(hqspi->hmdma);
- if(status != HAL_OK)
- {
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- }
- }
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
-
- if(status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Wait until BUSY flag is reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
- }
-
- if (status == HAL_OK)
- {
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_READY;
- }
- }
-
- return status;
-}
-
-/**
-* @brief Abort the current transmission (non-blocking function)
-* @param hqspi: QSPI handle
-* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2) != 0)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_ABORT;
-
- /* Disable all interrupts */
- __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
-
- if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
- {
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort MDMA channel */
- hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_MDMA_Abort_IT(hqspi->hmdma);
- }
- else
- {
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Enable the QSPI Transfer Complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
- }
- }
- return status;
-}
-
-/** @brief Set QSPI timeout.
- * @param hqspi: QSPI handle.
- * @param Timeout: Timeout for the QSPI memory access.
- * @retval None
- */
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
-{
- hqspi->Timeout = Timeout;
-}
-
-/** @brief Set QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @param Threshold: Threshold of the Fifo (value between 1 and 16).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hqspi);
-
- if(hqspi->State == HAL_QSPI_STATE_READY)
- {
- /* Synchronize init structure with new FIFO threshold value */
- hqspi->Init.FifoThreshold = Threshold;
-
- /* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
- }
- else
- {
- status = HAL_BUSY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Return function status */
- return status;
-}
-
-/** @brief Get QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @retval Fifo threshold (value between 1 and 16)
- */
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
-{
- return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
-}
-
-/**
- * @}
- */
-
-/**
- * @brief DMA QSPI receive process complete callback.
- * @param hmdma: MDMA handle
- * @retval None
- */
-static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
- hqspi->RxXferCount = 0;
-
- /* Enable the QSPI transfer complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
- * @brief DMA QSPI transmit process complete callback.
- * @param hmdma: MDMA handle
- * @retval None
- */
-static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
- hqspi->TxXferCount = 0;
-
- /* Enable the QSPI transfer complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-}
-
-/**
- * @brief DMA QSPI communication error callback.
- * @param hmdma: MDMA handle
- * @retval None
- */
-static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
-
- hqspi->RxXferCount = 0;
- hqspi->TxXferCount = 0;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
- /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort the QSPI */
- HAL_QSPI_Abort_IT(hqspi);
-}
-
-/**
- * @brief MDMA QSPI abort complete callback.
- * @param hmdma: MDMA handle
- * @retval None
- */
-static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
-{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
-
- hqspi->RxXferCount = 0;
- hqspi->TxXferCount = 0;
-
- if(hqspi->State == HAL_QSPI_STATE_ABORT)
- {
- /* MDMA Abort called by QSPI abort */
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Enable the QSPI Transfer Complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
- }
- else
- {
- /* MDMA Abort called due to a transfer error interrupt */
- /* Change state of QSPI */
- hqspi->State = HAL_QSPI_STATE_READY;
-
- /* Error callback */
- HAL_QSPI_ErrorCallback(hqspi);
- }
-}
-/**
- * @brief Wait for a flag state until timeout.
- * @param hqspi: QSPI handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param tickstart: Tick start value
- * @param Timeout: Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
- FlagStatus State, uint32_t tickstart, uint32_t Timeout)
-{
- /* Wait until flag is in expected state */
- while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hqspi->State = HAL_QSPI_STATE_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-
- return HAL_ERROR;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Configure the communication registers.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information
- * @param FunctionalMode: functional mode to configured
- * This parameter can be one of the following values:
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
- * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
- * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
- * @retval None
- */
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
-{
- assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
-
- if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
- {
- /* Configure QSPI: DLR register with the number of data to read or write */
- WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
- }
-
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
- {
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- /* Configure QSPI: ABR register with alternate bytes value */
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with instruction, address and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with instruction and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
- }
- }
- else
- {
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with instruction and address ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only instruction ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateByteMode | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
- }
- }
- }
- else
- {
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
- {
- /* Configure QSPI: ABR register with alternate bytes value */
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
-
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with address and alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only alternate bytes ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateBytesSize | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
- }
- }
- else
- {
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)
- {
- /*---- Command with only address ----*/
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateByteMode | cmd->AddressSize |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
-
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
- {
- /* Configure QSPI: AR register with address value */
- WRITE_REG(hqspi->Instance->AR, cmd->Address);
- }
- }
- else
- {
- /*---- Command with only data phase ----*/
- if (cmd->DataMode != QSPI_DATA_NONE)
- {
- /* Configure QSPI: CCR register with all communications parameters */
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
- cmd->AlternateByteMode | cmd->AddressMode |
- cmd->InstructionMode | FunctionalMode));
- }
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_QSPI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
deleted file mode 100644
index 94c7347..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
+++ /dev/null
@@ -1,1356 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rcc.c
- * @author MCD Application Team
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
- internal SRAM, Flash, JTAG and PWR
- (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
- all peripherals mapped on these buses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in analogue mode , except the JTAG pins which
- are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB buses pre-scalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock kernel source(s) for peripherals which clocks are not
- derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
- and RCC_D3CCIPR registers
-
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
- after the clock enable bit is set on the hardware register
- (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
- after the clock enable bit is set on the hardware register
-
- [..]
- Implemented Workaround:
- (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
- * @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
-
-#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
-#define MCO2_GPIO_PORT GPIOC
-#define MCO2_PIN GPIO_PIN_9
-
-/**
- * @}
- */
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
- AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
-
- [..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
- (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
- clock, or PLL input.But even with frequency calibration, is less accurate than an
- external crystal oscillator or ceramic resonator.
- (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
- featuring three different output clocks and able to work either in integer or Fractional mode.
- (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
- and to some peripherals.
- (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
-
-
- (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
- exception vector.
-
- (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
- or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
-
- (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
- LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
-
- [..] System, AHB and APB buses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System core clock through configurable
- pre-scaler and used to clock the CPU, memory and peripherals mapped
- on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers
- and used to clock the peripherals mapped on these buses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
- with dual clock domain where kernel source clock could be selected through
- RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE, PLL1, PLL2 and PLL3 OFF
- * - AHB, APB Bus pre-scaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
- */
-void HAL_RCC_DeInit(void)
-{
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION);
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
- |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
-
- /* Reset D1CFGR register */
- CLEAR_REG(RCC->D1CFGR);
-
- /* Reset D2CFGR register */
- CLEAR_REG(RCC->D2CFGR);
-
- /* Reset D3CFGR register */
- CLEAR_REG(RCC->D3CFGR);
-
- /* Reset PLLCKSELR register */
- CLEAR_REG(RCC->PLLCKSELR);
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
-
- /* Reset PLL1DIVR register */
- CLEAR_REG(RCC->PLL1DIVR);
-
- /* Reset PLL1FRACR register */
- CLEAR_REG(RCC->PLL1FRACR);
-
- /* Reset PLL2DIVR register */
- CLEAR_REG(RCC->PLL2DIVR);
-
- /* Reset PLL2FRACR register */
- CLEAR_REG(RCC->PLL2FRACR);
-
- /* Reset PLL3DIVR register */
- CLEAR_REG(RCC->PLL3DIVR);
-
- /* Reset PLL3FRACR register */
- CLEAR_REG(RCC->PLL3FRACR);
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CICR);
-}
-
-/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this function. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* When the HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
- __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
-
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
- __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- CSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
-
- /* When the CSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_CSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL1) && ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
- {
- /* When CSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
- __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
- }
- }
- else
- {
- /* Check the CSI State */
- if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (CSI). */
- __HAL_RCC_CSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till CSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
- __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (CSI). */
- __HAL_RCC_CSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till CSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /*------------------------------ HSI48 Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
- /* Check the HSI48 State */
- if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
- {
- /* Enable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_ENABLE();
-
- /* Get time-out */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_DISABLE();
-
- /* Get time-out */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI48 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ,
- RCC_OscInitStruct->PLL.PLLR);
-
- /* Configure PLL PLL1FRACN */
- __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
-
- /* Select PLL1 input reference frequency range: VCI */
- __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
-
- /* Select PLL1 output frequency range : VCO */
- __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
-
- /* Enable PLL System Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
-
- /* Enable PLL1Q Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* Enable PLL1R Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
-
- /* Enable PLL1FRACN . */
- __HAL_RCC_PLLFRACN_ENABLE();
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency, this parameter depend on device selected
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by HAL_InitTick() function called within this function
- *
- * @note The HSI is used (enabled by hardware) as system clock source after
- * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after start-up delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- * @note Depending on the device voltage range, the software has to set correctly
- * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
-
- }
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration -------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
- MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* CSI is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_CSI)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*-------------------------- D1PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
- {
- assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
- MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
- }
-
-
- /*-------------------------- D3PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
- {
- assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
- MODIFY_REG(RCC->D3CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB4CLKDivider) );
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
- * @note PA8/PC9 should be configured in alternate function mode.
- * @param RCC_MCOx: specifies the output direction for the clock source.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
- * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
- * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source
- * @param RCC_MCODiv: specifies the MCOx pre-scaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock
- * @retval None
- */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
- GPIO_InitTypeDef GPIO_InitStruct;
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- /* RCC_MCO1 */
- if(RCC_MCOx == RCC_MCO1)
- {
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* MCO1 Clock Enable */
- __MCO1_CLK_ENABLE();
-
- /* Configure the MCO1 pin in alternate function mode */
- GPIO_InitStruct.Pin = MCO1_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
- HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
- /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
- }
- else
- {
- assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-
- /* MCO2 Clock Enable */
- __MCO2_CLK_ENABLE();
-
- /* Configure the MCO2 pin in alternate function mode */
- GPIO_InitStruct.Pin = MCO2_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
- HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-
- /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7)));
- }
-}
-
-/**
- * @brief Enables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
-}
-
-/**
- * @brief Returns the SYSCLK frequency
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
- * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
- * 4 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
- * 64 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baud rate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- uint32_t pllp = 1, pllsource = 0, pllm = 1 ,pllfracen =0 , hsivalue = 0;
- float fracn1=0, pllvco = 0;
- uint32_t sysclockfreq = 0;
- /* Get SYSCLK source -------------------------------------------------------*/
-
- switch (RCC->CFGR & RCC_CFGR_SWS)
- {
- case 0x00: /* HSI used as system clock source */
-
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
- }
- else
- {
- sysclockfreq = (uint32_t) HSI_VALUE;
- }
-
- break;
-
- case 0x08: /* CSI used as system clock source */
- sysclockfreq = CSI_VALUE;
- break;
-
- case 0x10: /* HSE used as system clock source */
- sysclockfreq = HSE_VALUE;
- break;
-
- case 0x18: /* PLL1 used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
- pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
- fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
-
- switch (pllsource)
- {
- case 0x00: /* HSI used as PLL clock source */
-
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
- pllvco = ( hsivalue / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- }
- else
- {
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- }
- break;
-
- case 0x01: /* CSI used as PLL clock source */
- pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- case 0x02: /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- default:
- pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
- }
- pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
- sysclockfreq = (uint32_t)(pllvco/pllp);
- break;
-
- default:
- sysclockfreq = CSI_VALUE;
- break;
- }
-
- return sysclockfreq;
-}
-
-
-/**
- * @brief Returns the HCLK frequency
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
- * and updated within this function
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> POSITION_VAL(RCC_D1CFGR_HPRE_0)]);
- return SystemD2Clock;
-}
-
-
-/**
- * @brief Returns the PCLK1 frequency
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> POSITION_VAL(RCC_D2CFGR_D2PPRE1_0)]);
-}
-
-
-/**
- * @brief Returns the PCLK2 frequency
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> POSITION_VAL(RCC_D2CFGR_D2PPRE2_0)]);
-}
-
-/**
- * @brief Configures the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
-
- /* Get the HSE configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
-
- /* Get the CSI configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
- {
- RCC_OscInitStruct->CSIState = RCC_CSI_ON;
- }
- else
- {
- RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
- }
-
- RCC_OscInitStruct->CSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_CSITRIM) >> POSITION_VAL(RCC_ICSCR_CSITRIM));
-
- /* Get the HSI configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
-
- /* Get the LSE configuration -----------------------------------------------*/
- if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
- /* Get the HSI48 configuration ---------------------------------------------*/
- if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
- }
- else
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
- }
-
- /* Get the PLL configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> POSITION_VAL(RCC_PLLCKSELR_DIVM1));
- RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> POSITION_VAL(RCC_PLL1DIVR_N1))+ 1;
- RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> POSITION_VAL(RCC_PLL1DIVR_R1))+ 1;
- RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> POSITION_VAL(RCC_PLL1DIVR_P1))+ 1;
- RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> POSITION_VAL(RCC_PLL1DIVR_Q1))+ 1;
- RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL1RGE_1));
- RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL1VCOSEL));
-}
-
-/**
- * @brief Configures the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
- * will be configured.
- * @param pFLatency: Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
- RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the SYSCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
-
- /* Get the D1HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
-
- /* Get the APB3 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
-
- /* Get the APB4 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
-
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-}
-
-/**
- * @brief This function handles the RCC CSS interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void)
-{
- /* Check RCC CSSF flag */
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))
- {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CCSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback
- * @retval none
- */
-__weak void HAL_RCC_CCSCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CCSCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
deleted file mode 100644
index 045d6a4..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,2652 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extension peripheral:
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RCCEx_Private_defines Private Defines
- * @{
- */
-#define PLL2_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define PLL3_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-
-#define DIVIDER_P_UPDATE 0U
-#define DIVIDER_Q_UPDATE 1U
-#define DIVIDER_R_UPDATE 2U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
-static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
- the backup registers) and RCC_BDCR register are set to their reset values.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the RCC extended peripherals clocks according to the specified
- * parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains the configuration information for the Extended Peripherals
- * clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
- * USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
- * SAI4A,SAI4B,SPI6,RTC).
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t tmpreg;
- uint32_t tickstart;
- HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
- HAL_StatusTypeDef status = HAL_OK; /* Final status */
-
- /*---------------------------- SPDIFRX configuration -------------------------------*/
-
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- {
-
- switch(PeriphClkInit->SpdifrxClockSelection)
- {
- case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
- /* Enable SAI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPDIFRXCLKSOURCE_HSI:
- /* Internal OSC clock is used as source of SPDIFRX clock*/
- /* SPDIFRX clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SPDIFRX clock*/
- __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SAI1 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
- {
- switch(PeriphClkInit->Sai1ClockSelection)
- {
- case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
- /* Enable SAI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI1CLKSOURCE_PIN:
- /* External clock is used as source of SAI1 clock*/
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI1CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI1 clock*/
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SAI2/3 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
- {
- switch(PeriphClkInit->Sai23ClockSelection)
- {
- case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */
- /* Enable SAI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SAI2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* SAI2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
-
- /* SAI2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI23CLKSOURCE_PIN:
- /* External clock is used as source of SAI2/3 clock*/
- /* SAI2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI23CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
- /* SAI2/3 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI2/3 clock*/
- __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SAI4A configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
- {
- switch(PeriphClkInit->Sai4AClockSelection)
- {
- case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
- /* Enable SAI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* SAI2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4ACLKSOURCE_PIN:
- /* External clock is used as source of SAI2 clock*/
- /* SAI2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4ACLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI2 clock*/
- __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
- /*---------------------------- SAI4B configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
- {
- switch(PeriphClkInit->Sai4BClockSelection)
- {
- case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
- /* Enable SAI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* SAI2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
-
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4BCLKSOURCE_PIN:
- /* External clock is used as source of SAI2 clock*/
- /* SAI2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SAI4BCLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
- /* SAI1 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SAI2 clock*/
- __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
- /*---------------------------- QSPI configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
- {
- switch(PeriphClkInit->QspiClockSelection)
- {
- case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/
- /* Enable QSPI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* QSPI clock source configuration done later after clock selection check */
- break;
-
- case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
-
- /* QSPI clock source configuration done later after clock selection check */
- break;
-
-
- case RCC_QSPICLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
- /* QSPI clock source configuration done later after clock selection check */
- break;
-
- case RCC_QSPICLKSOURCE_D1HCLK:
- /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of QSPI clock*/
- __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SPI1/2/3 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
- {
- switch(PeriphClkInit->Spi123ClockSelection)
- {
- case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
- /* Enable SPI Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SPI1/2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* SPI1/2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
-
- /* SPI1/2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI123CLKSOURCE_PIN:
- /* External clock is used as source of SPI1/2/3 clock*/
- /* SPI1/2/3 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI123CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
- /* SPI1/2/3 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SPI1/2/3 clock*/
- __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SPI4/5 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
- {
- switch(PeriphClkInit->Spi45ClockSelection)
- {
- case RCC_SPI45CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for SPI4/5 */
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
- case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI45CLKSOURCE_HSI:
- /* HSI oscillator clock is used as source of SPI4/5 clock*/
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI45CLKSOURCE_CSI:
- /* CSI oscillator clock is used as source of SPI4/5 clock */
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI45CLKSOURCE_HSE:
- /* HSE, oscillator is used as source of SPI4/5 clock */
- /* SPI4/5 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SPI4/5 clock*/
- __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- SPI6 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
- {
- switch(PeriphClkInit->Spi6ClockSelection)
- {
- case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for SPI6*/
- /* SPI6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-
- /* SPI6 clock source configuration done later after clock selection check */
- break;
- case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
- /* SPI6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI6CLKSOURCE_HSI:
- /* HSI oscillator clock is used as source of SPI6 clock*/
- /* SPI6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI6CLKSOURCE_CSI:
- /* CSI oscillator clock is used as source of SPI6 clock */
- /* SPI6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_SPI6CLKSOURCE_HSE:
- /* HSE, oscillator is used as source of SPI6 clock */
- /* SPI6 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SPI6 clock*/
- __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
-
-#if defined(FDCAN1) || defined(FDCAN2)
- /*---------------------------- FDCAN configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
- {
- switch(PeriphClkInit->FdcanClockSelection)
- {
- case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
- /* Enable FDCAN Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* FDCAN clock source configuration done later after clock selection check */
- break;
-
- case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-
- /* FDCAN clock source configuration done later after clock selection check */
- break;
-
- case RCC_FDCANCLKSOURCE_HSE:
- /* HSE is used as clock source for FDCAN*/
- /* FDCAN clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of FDCAN clock*/
- __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
-#endif /*FDCAN1 || FDCAN2*/
- /*---------------------------- FMC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
- {
- switch(PeriphClkInit->FmcClockSelection)
- {
- case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
- /* Enable FMC Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* FMC clock source configuration done later after clock selection check */
- break;
-
- case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
-
- /* FMC clock source configuration done later after clock selection check */
- break;
-
-
- case RCC_FMCCLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
- /* FMC clock source configuration done later after clock selection check */
- break;
-
- case RCC_FMCCLKSOURCE_D1HCLK:
- /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of FMC clock*/
- __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- RTC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
- {
- /* check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR1, PWR_CR1_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- ret = HAL_TIMEOUT;
- break;
- }
- }
-
- if(ret == HAL_OK)
- {
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- ret = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- if(ret == HAL_OK)
- {
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
-
- /*-------------------------- USART1/6 configuration --------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
- {
- switch(PeriphClkInit->Usart16ClockSelection)
- {
- case RCC_USART16CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART1/6 */
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART16CLKSOURCE_HSI:
- /* HSI oscillator clock is used as source of USART1/6 clock */
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART16CLKSOURCE_CSI:
- /* CSI oscillator clock is used as source of USART1/6 clock */
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART16CLKSOURCE_LSE:
- /* LSE, oscillator is used as source of USART1/6 clock */
- /* USART1/6 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of USART1/6 clock */
- __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
- {
- switch(PeriphClkInit->Usart234578ClockSelection)
- {
- case RCC_USART234578CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART2/3/4/5/7/8 */
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART234578CLKSOURCE_HSI:
- /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART234578CLKSOURCE_CSI:
- /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- case RCC_USART234578CLKSOURCE_LSE:
- /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */
- /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of USART2/3/4/5/7/8 clock */
- __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*-------------------------- LPUART1 Configuration -------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
- {
- switch(PeriphClkInit->Lpuart1ClockSelection)
- {
- case RCC_LPUART1CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPUART1 */
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPUART1CLKSOURCE_HSI:
- /* HSI oscillator clock is used as source of LPUART1 clock */
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPUART1CLKSOURCE_CSI:
- /* CSI oscillator clock is used as source of LPUART1 clock */
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPUART1CLKSOURCE_LSE:
- /* LSE, oscillator is used as source of LPUART1 clock */
- /* LPUART1 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of LPUART1 clock */
- __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- LPTIM1 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- {
- switch(PeriphClkInit->Lptim1ClockSelection)
- {
- case RCC_LPTIM1CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for LPTIM1*/
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
-
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM1CLKSOURCE_LSE:
- /* External low speed OSC clock is used as source of LPTIM1 clock*/
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM1CLKSOURCE_LSI:
- /* Internal low speed OSC clock is used as source of LPTIM1 clock*/
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
- case RCC_LPTIM1CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
- /* LPTIM1 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of LPTIM1 clock*/
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- LPTIM2 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
- {
- switch(PeriphClkInit->Lptim2ClockSelection)
- {
- case RCC_LPTIM2CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM2*/
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
-
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM2CLKSOURCE_LSE:
- /* External low speed OSC clock is used as source of LPTIM2 clock*/
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM2CLKSOURCE_LSI:
- /* Internal low speed OSC clock is used as source of LPTIM2 clock*/
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
- case RCC_LPTIM2CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
- /* LPTIM2 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of LPTIM2 clock*/
- __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*---------------------------- LPTIM345 configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
- {
- switch(PeriphClkInit->Lptim345ClockSelection)
- {
-
- case RCC_LPTIM345CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM3/4/5 */
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
-
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM345CLKSOURCE_LSE:
- /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
-
- case RCC_LPTIM345CLKSOURCE_LSI:
- /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
- case RCC_LPTIM345CLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
- /* LPTIM3/4/5 clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of LPTIM3/4/5 clock */
- __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*------------------------------ I2C1/2/3 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
-
- if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
- {
- status |= RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
- }
-
- else
- {
- __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
- }
-
- }
-
- /*------------------------------ I2C4 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
- {
- status |= RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
- }
-
- else
- {
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- }
- }
-
- /*---------------------------- ADC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- {
- switch(PeriphClkInit->AdcClockSelection)
- {
-
- case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
-
- /* ADC clock source configuration done later after clock selection check */
- break;
-
- case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
-
- /* ADC clock source configuration done later after clock selection check */
- break;
-
- case RCC_ADCCLKSOURCE_CLKP:
- /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
- /* ADC clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of ADC clock*/
- __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*------------------------------ USB Configuration -------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
- {
-
- switch(PeriphClkInit->UsbClockSelection)
- {
- case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/
- /* Enable USB Clock output generated form System USB . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* USB clock source configuration done later after clock selection check */
- break;
-
- case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
-
- ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-
- /* USB clock source configuration done later after clock selection check */
- break;
-
- case RCC_USBCLKSOURCE_HSI48:
- /* HSI48 oscillator is used as source of USB clock */
- /* USB clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of USB clock*/
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
-
- }
-
- /*------------------------------------- SDMMC Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
-
- switch(PeriphClkInit->SdmmcClockSelection)
- {
- case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/
- /* Enable SDMMC Clock output generated form System PLL . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* SDMMC clock source configuration done later after clock selection check */
- break;
-
- case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
-
- ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
-
- /* SDMMC clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of SDMMC clock*/
- __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- {
- status |= RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
- }
-
- /*------------------------------ RNG Configuration -------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
- {
-
- switch(PeriphClkInit->RngClockSelection)
- {
- case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/
- /* Enable RNG Clock output generated form System RNG . */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
-
- /* RNG clock source configuration done later after clock selection check */
- break;
-
- case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
-
- /* RNG clock source configuration done later after clock selection check */
- break;
-
- case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
-
- /* RNG clock source configuration done later after clock selection check */
- break;
- case RCC_RNGCLKSOURCE_HSI48:
- /* HSI48 oscillator is used as source of RNG clock */
- /* RNG clock source configuration done later after clock selection check */
- break;
-
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if(ret == HAL_OK)
- {
- /* Set the source of RNG clock*/
- __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
- }
- else
- {
- /* set overall return value */
- status |= ret;
- }
-
- }
-
- /*------------------------------ SWPMI1 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
-
- /* Configure the SWPMI1 interface clock source */
- __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
- }
-
- /*------------------------------ HRTIM1 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
-
- /* Configure the HRTIM1 clock source */
- __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
- }
-
- /*------------------------------ DFSDM1 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- }
-
- /*------------------------------------ CKPER configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
-
- /* Configure the CKPER clock source */
- __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
- }
-
- if (status == HAL_OK)
- {
- return HAL_OK;
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-* returns the configuration information for the Extended Peripherals clocks :
- * (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
- * USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
-* SAI4A,SAI4B,SPI6,RTC,TIM).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- /* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection =
- RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C123 |
- RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 |
- RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI23 | RCC_PERIPHCLK_SAI4A | RCC_PERIPHCLK_SAI4B |
- RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_FDCAN |
- RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC |
- RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CEC |
- RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_SPDIFRX |
- RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER;
-
- /* Get the PLL3 Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> POSITION_VAL(RCC_PLLCKSELR_DIVM3));
- PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> POSITION_VAL(RCC_PLL3DIVR_N3))+ 1;
- PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> POSITION_VAL(RCC_PLL3DIVR_R3))+ 1;
- PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> POSITION_VAL(RCC_PLL3DIVR_P3))+ 1;
- PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> POSITION_VAL(RCC_PLL3DIVR_Q3))+ 1;
- PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL3RGE_1));
- PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL3VCOSEL));
-
- /* Get the PLL2 Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> POSITION_VAL(RCC_PLLCKSELR_DIVM2));
- PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> POSITION_VAL(RCC_PLL2DIVR_N2))+ 1;
- PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> POSITION_VAL(RCC_PLL2DIVR_R2))+ 1;
- PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> POSITION_VAL(RCC_PLL2DIVR_P2))+ 1;
- PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> POSITION_VAL(RCC_PLL2DIVR_Q2))+ 1;
- PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> POSITION_VAL(RCC_PLLCFGR_PLL2RGE_1));
- PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> POSITION_VAL(RCC_PLLCFGR_PLL2VCOSEL));
-
- /* Get the USART1 configuration --------------------------------------------*/
- PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE();
- /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
- PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
- /* Get the LPUART1 clock source --------------------------------------------*/
- PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
- /* Get the I2C1/2/3 clock source -------------------------------------------*/
- PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
- /* Get the LPTIM1 clock source ---------------------------------------------*/
- PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
- /* Get the LPTIM2 clock source ---------------------------------------------*/
- PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
- /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
- PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE();
- /* Get the SAI1 clock source -----------------------------------------------*/
- PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
- /* Get the SAI2/3 clock source ---------------------------------------------*/
- PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();
- /* Get the SAI4A clock source ----------------------------------------------*/
- PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();
- /* Get the SAI4B clock source ----------------------------------------------*/
- PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();
- /* Get the RTC clock source ------------------------------------------------*/
- PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
- /* Get the USB clock source ------------------------------------------------*/
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
- /* Get the SDMMC clock source ----------------------------------------------*/
- PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
- /* Get the RNG clock source ------------------------------------------------*/
- PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
- /* Get the HRTIM1 clock source ---------------------------------------------*/
- PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
- /* Get the ADC clock source ------------------------------------------------*/
- PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
- /* Get the SWPMI1 clock source ---------------------------------------------*/
- PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
- /* Get the DFSDM1 clock source ---------------------------------------------*/
- PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
- /* Get the SPDIFRX clock source --------------------------------------------*/
- PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
- /* Get the SPI1/2/3 clock source -------------------------------------------*/
- PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE();
- /* Get the SPI4/5 clock source ---------------------------------------------*/
- PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
- /* Get the SPI6 clock source -----------------------------------------------*/
- PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
- /* Get the FDCAN clock source ----------------------------------------------*/
- PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
- /* Get the CEC clock source ------------------------------------------------*/
- PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
- /* Get the FMC clock source ------------------------------------------------*/
- PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
- /* Get the QSPI clock source -----------------------------------------------*/
- PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
-
-
- /* Get the CKPER clock source ----------------------------------------------*/
- PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
-
- /* Get the TIM Prescaler configuration -------------------------------------*/
- if ((RCC->CFGR & RCC_CFGR_TIMPRE) == RESET)
- {
- PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
- }
- else
- {
- PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
- }
-}
-
-/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
- * @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
- * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock
- * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock
- * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock
- * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
- * @retval Frequency in KHz
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
- PLL1_ClocksTypeDef pll1_clocks;
- PLL2_ClocksTypeDef pll2_clocks;
- PLL3_ClocksTypeDef pll3_clocks;
-
- /* This variable is used to store the SAI clock frequency (value in Hz) */
- uint32_t frequency = 0;
- /* This variable is used to store the SAI and CKP clock source */
- uint32_t saiclocksource = 0;
- uint32_t ckpclocksource = 0;
- uint32_t srcclk = 0U;
- switch (PeriphClk)
- {
- case RCC_PERIPHCLK_SAI1:
- {
-
- saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
-
- switch (saiclocksource)
- {
- case 0: /* PLL1 is the clock source for SAI1 */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_D2CCIP1R_SAI1SEL_0: /* PLLI2 is the clock source for SAI1 */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SAI1SEL_1: /* PLLI3 is the clock source for SAI1 */
- {
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SAI1SEL_2: /* CKPER is the clock source for SAI1*/
- {
-
- ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
- if(ckpclocksource== 0)
- {
- /* In Case the main PLL Source is HSI */
- frequency = HSI_VALUE;
- }
-
- else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
- {
- /* In Case the main PLL Source is CSI */
- frequency = CSI_VALUE;
- }
-
- else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
- {
- /* In Case the main PLL Source is HSE */
- frequency = HSE_VALUE;
- }
-
- break;
- }
-
- case (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1 ): /* External clock is the clock source for SAI1 */
- {
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
- }
- default :
- {
- break;
- }
- }
- break;
- }
-
- case RCC_PERIPHCLK_SAI23:
- {
-
- saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
-
- switch (saiclocksource)
- {
- case 0: /* PLL1 is the clock source for SAI2/3 */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI2/3 */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI2/3 */
- {
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI2/3 */
- {
-
- ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
- if(ckpclocksource== 0)
- {
- /* In Case the main PLL Source is HSI */
- frequency = HSI_VALUE;
- }
-
- else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
- {
- /* In Case the main PLL Source is CSI */
- frequency = CSI_VALUE;
- }
-
- else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
- {
- /* In Case the main PLL Source is HSE */
- frequency = HSE_VALUE;
- }
-
- break;
- }
-
- case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI2/3 */
- {
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
- }
- default :
- {
- break;
- }
- }
- break;
- }
-
- case RCC_PERIPHCLK_SAI4A:
- {
-
- saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
-
- switch (saiclocksource)
- {
- case 0: /* PLL1 is the clock source for SAI4A */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
- }
-
- case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
- {
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
- }
-
- case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
- {
-
- ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
- if(ckpclocksource== 0)
- {
- /* In Case the main PLL Source is HSI */
- frequency = HSI_VALUE;
- }
-
- else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
- {
- /* In Case the main PLL Source is CSI */
- frequency = CSI_VALUE;
- }
-
- else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
- {
- /* In Case the main PLL Source is HSE */
- frequency = HSE_VALUE;
- }
-
- break;
- }
-
- case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
- {
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
- }
-
- default :
- {
- break;
- }
- }
- break;
- }
-
- case RCC_PERIPHCLK_SAI4B:
- {
-
- saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
-
- switch (saiclocksource)
- {
- case 0: /* PLL1 is the clock source for SAI4B */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
- }
-
- case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
- {
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
- }
-
- case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
- {
-
- ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
- if(ckpclocksource== 0)
- {
- /* In Case the main PLL Source is HSI */
- frequency = HSI_VALUE;
- }
-
- else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
- {
- /* In Case the main PLL Source is CSI */
- frequency = CSI_VALUE;
- }
-
- else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
- {
- /* In Case the main PLL Source is HSE */
- frequency = HSE_VALUE;
- }
-
- break;
- }
-
- case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
- {
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
- }
-
- default :
- {
- break;
- }
- }
- break;
- }
- case RCC_PERIPHCLK_SPI123:
- {
- /* Get SPI1/2/3 clock source */
- srcclk= __HAL_RCC_GET_SPI123_SOURCE();
-
- switch (srcclk)
- {
- case 0: /* PLL1 is the clock source for I2S */
- {
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
- break;
- }
- case RCC_D2CCIP1R_SPI123SEL_0: /* PLL2 is the clock source for I2S */
- {
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- frequency = pll2_clocks.PLL2_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SPI123SEL_1: /* PLL3 is the clock source for I2S */
- {
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- frequency = pll3_clocks.PLL3_P_Frequency;
- break;
- }
-
- case RCC_D2CCIP1R_SPI123SEL_2: /* CKPER is the clock source for I2S */
- {
-
- ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
- {
- /* In Case the main PLL Source is HSI */
- frequency = HSI_VALUE;
- }
-
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
- {
- /* In Case the main PLL Source is CSI */
- frequency = CSI_VALUE;
- }
-
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
- {
- /* In Case the main PLL Source is HSE */
- frequency = HSE_VALUE;
- }
-
- break;
- }
-
- case (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1): /* External clock is the clock source for I2S */
- {
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
- }
- default :
- {
- break;
- }
- }
- break;
- }
-
- }
- return frequency;
-}
-
-
-/**
- * @brief Returns the D1PCLK1 frequency
- * @note Each time D1PCLK1 changes, this function must be called to update the
- * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval D1PCLK1 frequency
- */
-uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
-{
- /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> POSITION_VAL(RCC_D1CFGR_D1PPRE_0)]);
-}
-
-/**
- * @brief Returns the D3PCLK1 frequency
- * @note Each time D3PCLK1 changes, this function must be called to update the
- * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval D3PCLK1 frequency
- */
-uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
-{
- /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> POSITION_VAL(RCC_D3CFGR_D3PPRE_0)]);
-}
-/**
-* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
- * @note The PLL2 clock frequencies computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time PLL2CLK changes, this function must be called to update the
- * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
- * @param PLL2_Clocks structure.
- * @retval None
- */
-void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
-{
- uint32_t pllsource = 0, pll2m = 1 , pll2fracen = 0, hsivalue = 0;
- float fracn2 =0 ,pll2vco = 0;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
- PLL2xCLK = PLL2_VCO / PLL2x
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12) ;
- pll2fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN;
- fracn2 =(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
-
- switch (pllsource)
- {
-
- case 0x00: /* HSI used as PLL clock source */
-
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
- pll2vco = ( hsivalue / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x2000) +1 );
- }
- else
- {
- pll2vco = (HSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x2000) +1 );
- }
- break;
-
- case 0x01: /* HSI used as PLL clock source */
- pll2vco = (CSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x2000) +1 );
- break;
-
- case 0x02: /* HSE used as PLL clock source */
- pll2vco = (HSE_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x2000) +1 );
- break;
-
- default:
- pll2vco = (CSI_VALUE / pll2m) * ((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/0x2000) +1 );
- break;
- }
- PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + 1 )) ;
- PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + 1 )) ;
- PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(pll2vco/(((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + 1 )) ;
-
-
-}
-
-/**
-* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
- * @note The PLL3 clock frequencies computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time PLL3CLK changes, this function must be called to update the
- * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
- * @param PLL3_Clocks structure.
- * @retval None
- */
-void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
-{
- uint32_t pllsource = 0, pll3m = 1, pll3fracen = 0 , hsivalue =0;
- float fracn3 =0 , pll3vco = 0;
- /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
- PLL3xCLK = PLL3_VCO / PLLxR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ;
- pll3fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN;
- fracn3 = (pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
- switch (pllsource)
- {
- case 0x00: /* HSI used as PLL clock source */
-
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
- pll3vco = (hsivalue / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x2000) +1 );
- }
- else
- {
- pll3vco = (HSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x2000) +1 );
- }
- break;
- case 0x01: /* HSI used as PLL clock source */
- pll3vco = (CSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x2000) +1 );
- break;
-
- case 0x02: /* HSE used as PLL clock source */
- pll3vco = (HSE_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x2000) +1 );
- break;
-
- default:
- pll3vco = (CSI_VALUE / pll3m) * ((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/0x2000) +1 );
- break;
- }
- PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + 1 )) ;
- PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + 1 )) ;
- PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(pll3vco/(((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + 1 )) ;
-
-}
-
-/**
-* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
- * @note The PLL1 clock frequencies computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time PLL1CLK changes, this function must be called to update the
- * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
- * @param PLL1_Clocks structure.
- * @retval None
- */
-void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
-{
- uint32_t pllsource = 0, pll1m = 1, pll1fracen = 0, hsivalue=0;
- float fracn1, pll1vco =0;
-
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
- pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
- fracn1 = (pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
- switch (pllsource)
- {
-
- case 0x00: /* HSI used as PLL clock source */
-
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
- pll1vco = (hsivalue / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- }
- else
- {
- pll1vco = (HSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- }
- break;
- case 0x01: /* CSI used as PLL clock source */
- pll1vco = (CSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- case 0x02: /* HSE used as PLL clock source */
- pll1vco = (HSE_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
-
- default:
- pll1vco = (CSI_VALUE / pll1m) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
- break;
- }
-
- PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 )) ;
- PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + 1 )) ;
- PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(pll1vco/(((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + 1 )) ;
-
-}
-
-/**
- * @brief Returns the main Core frequency
- * @note Each time core clock changes, this function must be called to update the
- * right system core clock value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated within this function
- * @retval HCLK frequency
- */
-uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
-{
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
- return SystemCoreClock;
-}
-
-/**
- * @brief Enables the LSE Clock Security System.
- * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
- * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
- * clock with HAL_RCCEx_PeriphCLKConfig().
- * @retval None
- */
-void HAL_RCCEx_EnableLSECSS(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
-}
-
-/**
- * @brief Disables the LSE Clock Security System.
- * @note LSE Clock Security System can only be disabled after a LSE failure detection.
- * @retval None
- */
-void HAL_RCCEx_DisableLSECSS(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
- /* Disable LSE CSS IT if any */
- __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
- * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
- * @param WakeUpClk: Wakeup clock
- * This parameter can be one of the following values:
- * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
- * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
- * @note This function shall not be called after the Clock Security System on HSE has been
- * enabled.
- * @retval None
- */
-void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
-{
- assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
-
- __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
-}
-
-/**
- * @brief Configure the oscillator Kernel clock source for wakeup from Stop
- * @param WakeUpClk: Kernel Wakeup clock
- * This parameter can be one of the following values:
- * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
- * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
- * @retval None
- */
-void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
-{
- assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
-
- __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
-}
-
-
-
-/**
- * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
- * @param RCC_WWDGx: WWDGx to be configured
- * This parameter can be one of the following values:
- * @arg RCC_WWDG1: WWDG1 generates system reset
- * @note This bit can be set by software but is cleared by hardware during a system reset
- *
- * @retval None
- */
-void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
-{
- assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
- SET_BIT(RCC->GCR, RCC_WWDGx) ;
-}
-
-
-
-/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
- * @brief Extended Clock Recovery System Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Clock Recovery System Control functions #####
- ===============================================================================
- [..]
- For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
-
- (#) In System clock config, HSI48 needs to be enabled
-
- (#) Enable CRS clock in IP MSP init which will use CRS functions
-
- (#) Call CRS functions as follows:
- (##) Prepare synchronization configuration necessary for HSI48 calibration
- (+++) Default values can be set for frequency Error Measurement (reload and error limit)
- and also HSI48 oscillator smooth trimming.
- (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
- directly reload value with target and synchronization frequencies values
- (##) Call function HAL_RCCEx_CRSConfig which
- (+++) Resets CRS registers to their default values.
- (+++) Configures CRS registers with synchronization configuration
- (+++) Enables automatic calibration and frequency error counter feature
- Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
- periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
- provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
- precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
- should be used as SYNC signal.
-
- (##) A polling function is provided to wait for complete synchronization
- (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
- (+++) According to CRS status, user can decide to adjust again the calibration or continue
- application if synchronization is OK
-
- (#) User can retrieve information related to synchronization in calling function
- HAL_RCCEx_CRSGetSynchronizationInfo()
-
- (#) Regarding synchronization status and synchronization information, user can try a new calibration
- in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
- Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
- it means that the actual frequency is lower than the target (and so, that the TRIM value should be
- incremented), while when it is detected during the up-counting phase it means that the actual frequency
- is higher (and that the TRIM value should be decremented).
-
- (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
- through CRS Handler (CRS_IRQn/CRS_IRQHandler)
- (++) Call function HAL_RCCEx_CRSConfig()
- (++) Enable CRS_IRQn (thanks to NVIC functions)
- (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
- (++) Implement CRS status management in the following user callbacks called from
- HAL_RCCEx_CRS_IRQHandler():
- (+++) HAL_RCCEx_CRS_SyncOkCallback()
- (+++) HAL_RCCEx_CRS_SyncWarnCallback()
- (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
- (+++) HAL_RCCEx_CRS_ErrorCallback()
-
- (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
- This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start automatic synchronization for polling mode
- * @param pInit Pointer on RCC_CRSInitTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
-{
- uint32_t value = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
- assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
- assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
- assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
- assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
- assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
-
- /* CONFIGURATION */
-
- /* Before configuration, reset CRS registers to their default values*/
- __HAL_RCC_CRS_FORCE_RESET();
- __HAL_RCC_CRS_RELEASE_RESET();
-
- /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
- /* Set the SYNCSRC[1:0] bits according to Source value */
- /* Set the SYNCSPOL bit according to Polarity value */
- value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
- /* Set the RELOAD[15:0] bits according to ReloadValue value */
- value |= pInit->ReloadValue;
- /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
- value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
- WRITE_REG(CRS->CFGR, value);
-
- /* Adjust HSI48 oscillator smooth trimming */
- /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
- MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
-
- /* START AUTOMATIC SYNCHRONIZATION*/
-
- /* Enable Automatic trimming & Frequency error counter */
- SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
-}
-
-/**
- * @brief Generate the software synchronization event
- * @retval None
- */
-void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
-{
- SET_BIT(CRS->CR, CRS_CR_SWSYNC);
-}
-
-/**
- * @brief Return synchronization info
- * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
- * @retval None
- */
-void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
-{
- /* Check the parameter */
- assert_param(pSynchroInfo != NULL);
-
- /* Get the reload value */
- pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
-
- /* Get HSI48 oscillator smooth trimming */
- pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
-
- /* Get Frequency error capture */
- pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
-
- /* Get Frequency error direction */
- pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
-}
-
-/**
-* @brief Wait for CRS Synchronization status.
-* @param Timeout Duration of the time-out
-* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
-* frequency.
-* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
-* @retval Combination of Synchronization status
-* This parameter can be a combination of the following values:
-* @arg @ref RCC_CRS_TIMEOUT
-* @arg @ref RCC_CRS_SYNCOK
-* @arg @ref RCC_CRS_SYNCWARN
-* @arg @ref RCC_CRS_SYNCERR
-* @arg @ref RCC_CRS_SYNCMISS
-* @arg @ref RCC_CRS_TRIMOVF
-*/
-uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
-{
- uint32_t crsstatus = RCC_CRS_NONE;
- uint32_t tickstart = 0U;
-
- /* Get time-out */
- tickstart = HAL_GetTick();
-
- /* Wait for CRS flag or time-out detection */
- do
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- crsstatus = RCC_CRS_TIMEOUT;
- }
- }
- /* Check CRS SYNCOK flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
- {
- /* CRS SYNC event OK */
- crsstatus |= RCC_CRS_SYNCOK;
-
- /* Clear CRS SYNC event OK bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
- }
-
- /* Check CRS SYNCWARN flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
- {
- /* CRS SYNC warning */
- crsstatus |= RCC_CRS_SYNCWARN;
-
- /* Clear CRS SYNCWARN bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
- }
-
- /* Check CRS TRIM overflow flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
- {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_TRIMOVF;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
- }
-
- /* Check CRS Error flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
- {
- /* CRS SYNC Error */
- crsstatus |= RCC_CRS_SYNCERR;
-
- /* Clear CRS Error bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
- }
-
- /* Check CRS SYNC Missed flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
- {
- /* CRS SYNC Missed */
- crsstatus |= RCC_CRS_SYNCMISS;
-
- /* Clear CRS SYNC Missed bit */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
- }
-
- /* Check CRS Expected SYNC flag */
- if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
- {
- /* frequency error counter reached a zero value */
- __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
- }
- } while(RCC_CRS_NONE == crsstatus);
-
- return crsstatus;
-}
-
-/**
- * @brief Handle the Clock Recovery System interrupt request.
- * @retval None
- */
-void HAL_RCCEx_CRS_IRQHandler(void)
-{
- uint32_t crserror = RCC_CRS_NONE;
- /* Get current IT flags and IT sources values */
- uint32_t itflags = READ_REG(CRS->ISR);
- uint32_t itsources = READ_REG(CRS->CR);
-
- /* Check CRS SYNCOK flag */
- if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
- {
- /* Clear CRS SYNC event OK flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncOkCallback();
- }
- /* Check CRS SYNCWARN flag */
- else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
- {
- /* Clear CRS SYNCWARN flag */
- WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
-
- /* user callback */
- HAL_RCCEx_CRS_SyncWarnCallback();
- }
- /* Check CRS Expected SYNC flag */
- else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
- {
- /* frequency error counter reached a zero value */
- WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
-
- /* user callback */
- HAL_RCCEx_CRS_ExpectedSyncCallback();
- }
- /* Check CRS Error flags */
- else
- {
- if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
- {
- if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
- {
- crserror |= RCC_CRS_SYNCERR;
- }
- if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
- {
- crserror |= RCC_CRS_SYNCMISS;
- }
- if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
- {
- crserror |= RCC_CRS_TRIMOVF;
- }
-
- /* Clear CRS Error flags */
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
-
- /* user error callback */
- HAL_RCCEx_CRS_ErrorCallback(crserror);
- }
- }
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief RCCEx Clock Recovery System Error interrupt callback.
- * @param Error Combination of Error status.
- * This parameter can be a combination of the following values:
- * @arg @ref RCC_CRS_SYNCERR
- * @arg @ref RCC_CRS_SYNCMISS
- * @arg @ref RCC_CRS_TRIMOVF
- * @retval none
- */
-__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Error);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Private_functions Private Functions
- * @{
- */
-
-
-
-/**
- * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
- * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
- * contains the configuration parameters as well as VCI, VCO clock ranges.
- * @param Divider divider parameter to be updated
- * @note PLL2 is temporary disable to apply new parameters
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
-{
-
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
- assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
- assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
- assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
- assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
- assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
-
- /* Check that PLL2 OSC clock source is already set */
- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
- {
- return HAL_ERROR;
- }
-
-
- else
- {
- /* Disable PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure PLL2 multiplication and division factors. */
- __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
- pll2->PLL2N,
- pll2->PLL2P,
- pll2->PLL2Q,
- pll2->PLL2R);
-
- /* Select PLL2 input reference frequency range: VCI */
- __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
-
- /* Select PLL2 output frequency range : VCO */
- __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
-
- /* Enable the PLL2 clock output */
- if(Divider == DIVIDER_P_UPDATE)
- {
- __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
- }
- else if(Divider == DIVIDER_Q_UPDATE)
- {
- __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
- }
- else
- {
- __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
- }
-
- /* Enable PLL2. */
- __HAL_RCC_PLL2_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- }
-
-
- return status;
-}
-
-/**
- * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
- * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
- * contains the configuration parameters as well as VCI, VCO clock ranges.
- * @param Divider divider parameter to be updated
- * @note PLL3 is temporary disable to apply new parameters
- *
- * @retval HAL status
- */
-static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
-{
- uint32_t tickstart;
- HAL_StatusTypeDef status = HAL_OK;
- assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
- assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
- assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
- assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
- assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
-
- /* Check that PLL3 OSC clock source is already set */
- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
- {
- return HAL_ERROR;
- }
-
-
- else
- {
- /* Disable PLL3. */
- __HAL_RCC_PLL3_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- /* Wait till PLL3 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the PLL3 multiplication and division factors. */
- __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
- pll3->PLL3N,
- pll3->PLL3P,
- pll3->PLL3Q,
- pll3->PLL3R);
-
- /* Select PLL3 input reference frequency range: VCI */
- __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
-
- /* Select PLL3 output frequency range : VCO */
- __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
-
- /* Enable the PLL3 clock output */
- if(Divider == DIVIDER_P_UPDATE)
- {
- __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
- }
- else if(Divider == DIVIDER_Q_UPDATE)
- {
- __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
- }
- else
- {
- __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
- }
-
- /* Enable PLL3. */
- __HAL_RCC_PLL3_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL3 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
- {
- if((int32_t) (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- }
-
-
- return status;
-}
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
deleted file mode 100644
index fd643af..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rng.c
- * @author MCD Application Team
- * @brief RNG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The RNG HAL driver can be used as follows:
-
- (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
- in HAL_RNG_MspInit().
- (#) Activate the RNG peripheral using HAL_RNG_Init() function.
- (#) Wait until the 32 bit Random Number Generator contains a valid
- random data using (polling/interrupt) mode.
- (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RNG
- * @{
- */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
- * @{
- */
-#define RNG_TIMEOUT_VALUE 2U
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RNG_Exported_Functions
- * @{
- */
-
-/** @addtogroup RNG_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the RNG according to the specified parameters
- in the RNG_InitTypeDef and create the associated handle
- (+) DeInitialize the RNG peripheral
- (+) Initialize the RNG MSP
- (+) DeInitialize RNG MSP
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the RNG peripheral and creates the associated handle.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{
- /* Check the RNG handle allocation */
- if(hrng == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the parameters */
- assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
- assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
-
- if(hrng->State == HAL_RNG_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hrng->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_RNG_MspInit(hrng);
- }
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* CED Configuration */
- MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
-
- /* Enable the RNG Peripheral */
- __HAL_RNG_ENABLE(hrng);
-
- /* Initialize the RNG state */
- hrng->State = HAL_RNG_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the RNG peripheral.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{
- /* Check the RNG handle allocation */
- if(hrng == NULL)
- {
- return HAL_ERROR;
- }
- /* Disable the RNG Peripheral */
- CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN |RNG_CR_CED);
-
- /* Clear RNG interrupt status flags */
- CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-
- /* DeInit the low level hardware */
- HAL_RNG_MspDeInit(hrng);
-
- /* Update the RNG state */
- hrng->State = HAL_RNG_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hrng);
-
- /* Return the function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval None
- */
-__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrng);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_RNG_MspInit must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval None
- */
-__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrng);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_RNG_MspDeInit must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RNG_Exported_Functions_Group2
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Get the 32 bit Random number
- (+) Get the 32 bit Random number with interrupt enabled
- (+) Handle RNG interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Generates a 32-bit random number.
- * @note Each time the random number data is read the RNG_FLAG_DRDY flag
- * is automatically cleared.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @param random32bit: pointer to generated random number variable if successful.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hrng);
-
- /* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
- {
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if data register contains valid random data */
- while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
- {
- hrng->State = HAL_RNG_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Get a 32bit Random number */
- hrng->RandomNumber = hrng->Instance->DR;
- *random32bit = hrng->RandomNumber;
-
- hrng->State = HAL_RNG_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
- return status;
-}
-
-/**
- * @brief Generates a 32-bit random number in interrupt mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hrng);
-
- /* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
- {
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
- /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
- __HAL_RNG_ENABLE_IT(hrng);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
- status = HAL_ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Handles RNG interrupt request.
- * @note In the case of a clock error, the RNG is no more able to generate
- * random numbers because the PLL48CLK clock is not correct. User has
- * to check that the clock controller is correctly configured to provide
- * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
- * The clock error has no impact on the previously generated
- * random numbers, and the RNG_DR register contents can be used.
- * @note In the case of a seed error, the generation of random numbers is
- * interrupted as long as the SECS bit is '1'. If a number is
- * available in the RNG_DR register, it must not be used because it may
- * not have enough entropy. In this case, it is recommended to clear the
- * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
- * the RNG peripheral to reinitialize and restart the RNG.
- * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
- * or CEIS are set.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval None
-
- */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
- /* RNG clock error interrupt occurred */
- if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
- {
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_ERROR;
-
- HAL_RNG_ErrorCallback(hrng);
-
- /* Clear the clock error flag */
- __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-
- }
-
- /* Check RNG data ready interrupt occurred */
- if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
- {
- /* Generate random number once, so disable the IT */
- __HAL_RNG_DISABLE_IT(hrng);
-
- /* Get the 32bit Random number (DRDY flag automatically cleared) */
- hrng->RandomNumber = hrng->Instance->DR;
-
- if(hrng->State != HAL_RNG_STATE_ERROR)
- {
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_READY;
-
- /* Data Ready callback */
- HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
- }
- }
-}
-
-/**
- * @brief Read latest generated random number.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval random value
- */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
-{
- return(hrng->RandomNumber);
-}
-
-/**
- * @brief Data Ready callback in non-blocking mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @param random32bit: generated random number.
- * @retval None
- */
-__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrng);
- UNUSED(random32bit);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_RNG_ReadyDataCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief RNG error callbacks.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval None
- */
-__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrng);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_RNG_ErrorCallback must be implemented in the user file.
- */
-}
-/**
- * @}
- */
-
-
-/** @addtogroup RNG_Exported_Functions_Group3
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the RNG state.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval HAL state
- */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
-{
- return hrng->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c
deleted file mode 100644
index 549a792..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c
+++ /dev/null
@@ -1,1529 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rtc.c
- * @author MCD Application Team
- * @brief RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + RTC Tamper and TimeStamp Pins Selection
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### RTC Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
- to their reset values.
- A backup domain reset is generated when one of the following events occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
- (#) Tamper detection event resets all data backup registers.
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
-
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
- PeriphClockSelection and select RTCClockSelection (LSE, LSI or any HSE divider)
- (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
-
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (#) Enable the RTC domain access (see description in the section above).
- (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
- HAL_RTC_SetAlarm_IT() function.
- (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
- ##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and Standby low power
- modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RTC RTC
- * @brief RTC HAL module driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provide functions allowing to initialize and configure the
- RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
- RTC registers Write protection, enter and exit the RTC initialization mode,
- RTC registers synchronization check and reference clock detection enable.
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
- It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize power consumption.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To configure the RTC Calendar, user application should enter
- initialization mode. In this mode, the calendar counter is stopped
- and its value can be updated. When the initialization sequence is
- complete, the calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
- implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the RTC according to the specified parameters
- * in the RTC_InitTypeDef structure and initialize the associated handle.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
- /* Check the RTC peripheral state */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
- assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
- assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
- assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
- assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
- assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
- if(hrtc->State == HAL_RTC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hrtc->Lock = HAL_UNLOCKED;
- /* Initialize RTC MSP */
- HAL_RTC_MspInit(hrtc);
- }
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
- hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief DeInitialize the RTC peripheral.
- * @param hrtc: RTC handle
- * @note This function doesn't reset the RTC Backup Data registers.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- hrtc->Instance->TR = (uint32_t)0x00000000;
- hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
- /* Reset All CR bits except CR[2:0] */
- hrtc->Instance->CR &= RTC_CR_WUCKSEL;
-
- tickstart = HAL_GetTick();
-
- /* Wait till WUTWF flag is set and if Time out is reached exit */
- while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset all RTC CR register bits */
- hrtc->Instance->CR &= (uint32_t)0x00000000;
- hrtc->Instance->WUTR = RTC_WUTR_WUT;
- hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
- hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
- hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
- hrtc->Instance->CALR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper configuration register */
- hrtc->Instance->TAMPCR = 0x00000000;
-
- /* Reset Option register */
- hrtc->Instance->OR = 0x00000000;
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* De-Initialize RTC MSP */
- HAL_RTC_MspDeInit(hrtc);
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the RTC MSP.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the RTC MSP.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
- * @brief RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set RTC current time.
- * @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sTime->Hours));
- assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
- else
- {
- sTime->TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(sTime->Hours));
- }
- assert_param(IS_RTC_MINUTES(sTime->Minutes));
- assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sTime->Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
- else
- {
- sTime->TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
- ((uint32_t)(sTime->Minutes) << 8) | \
- ((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Clear the bits to be configured */
- hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Get RTC current time.
- * @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
- * with input format (BIN or BCD), also SubSeconds field returning the
- * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
- * factor to be used for second fraction ratio computation.
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
- * value in second fraction ratio with time unit following generic formula:
- * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
- * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read
- * to ensure consistency between the time and date values.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get subseconds structure field from the corresponding register*/
- sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-
- /* Get SecondFraction structure field from the corresponding register field*/
- sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
- /* Get the TR register */
- tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the time structure parameters to Binary format */
- sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
- sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
- sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set RTC current date.
- * @param hrtc: RTC handle
- * @param sDate: Pointer to date structure
- * @param Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- uint32_t datetmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
- {
- sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
- }
-
- assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_YEAR(sDate->Year));
- assert_param(IS_RTC_MONTH(sDate->Month));
- assert_param(IS_RTC_DATE(sDate->Date));
-
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- datetmpreg = RTC_Bcd2ToByte(sDate->Month);
- assert_param(IS_RTC_MONTH(datetmpreg));
- datetmpreg = RTC_Bcd2ToByte(sDate->Date);
- assert_param(IS_RTC_DATE(datetmpreg));
-
- datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
- (((uint32_t)sDate->Month) << 8) | \
- ((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13));
- }
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Get RTC current date.
- * @param hrtc: RTC handle
- * @param sDate: Pointer to Date structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- uint32_t datetmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get the DR register */
- datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the date structure parameters to Binary format */
- sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
- sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
- sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
- * @brief RTC Alarm functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
- * @{
- */
-/**
- * @brief Set the specified RTC Alarm.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0;
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
-
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
-
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
-
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if(sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified RTC Alarm with Interrupt.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the HAL_RTC_DeactivateAlarm()).
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0;
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if(sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* Clear flag alarm B */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
- }
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the specified RTC Alarm.
- * @param hrtc: RTC handle
- * @param Alarm: Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @arg RTC_ALARM_B: AlarmB
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- if(Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* AlarmB */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @arg RTC_ALARM_B: AlarmB
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(Alarm));
-
- if(Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- sAlarm->Alarm = RTC_ALARM_A;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
- }
- else
- {
- sAlarm->Alarm = RTC_ALARM_B;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- /* Fill the structure with the read parameters */
- /* ALRMAR/ALRMBR registers have same mapping) */
- sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
- sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
- sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
- sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
- if(Format == RTC_FORMAT_BIN)
- {
- sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
- sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
- sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Alarm interrupt request.
- * @param hrtc: RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
-
- /* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
- /* Get the AlarmA interrupt source enable status */
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
- {
- /* Get the pending status of the AlarmA Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
- {
-
- /* Clear the AlarmA interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* AlarmA callback */
- HAL_RTC_AlarmAEventCallback(hrtc);
- }
- }
-
- /* Get the AlarmB interrupt source enable status */
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
- {
- /* Get the pending status of the AlarmB Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
- {
-
- /* Clear the AlarmB interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- /* AlarmB callback */
- HAL_RTCEx_AlarmBEventCallback(hrtc);
- }
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Alarm A callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_AlarmAEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle AlarmA Polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0;
-
- /* Clear RSF flag */
- hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- tickstart = HAL_GetTick();
-
- /* Wait the registers to be synchronised */
- while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Get RTC state
-
-@endverbatim
- * @{
- */
-/**
- * @brief Return the RTC handle state.
- * @param hrtc: RTC handle
- * @retval HAL state
- */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
- /* Return RTC handle state */
- return hrtc->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Functions RTC Private functions
- * @{
- */
-/**
- * @brief Enter the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0;
-
- /* Check if the Initialization mode is set */
- if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
- tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Convert a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted
- * @retval Converted byte
- */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint32_t bcdhigh = 0;
-
- while(Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted
- * @retval Converted word
- */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint32_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c
deleted file mode 100644
index 8c360b7..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1828 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_rtc_ex.c
- * @author MCD Application Team
- * @brief Extended RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extended peripheral:
- * + RTC Time Stamp functions
- * + RTC Tamper functions
- * + RTC Wake-up functions
- * + Extended Control functions
- * + Extended RTC features functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) Enable the RTC domain access.
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals.
- To output the selected RTC signal, use the HAL_RTC_Init() function.
- (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
- To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
- (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
- the RTC_OR register.
- (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
- automatically configured in output alternate function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
- You can also configure the RTC TimeStamp with interrupt mode using the
- HAL_RTCEx_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
- function.
-
- *** Internal TimeStamp configuration ***
- ===============================
- [..]
- (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
- User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
- function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
- Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
- with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
- (+) The default configuration of the Tamper erases the backup registers. To avoid
- erase, enable the NoErase field on the RTC_TAMPCR register.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
- function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RTCEx RTCEx
- * @brief RTC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
- * @{
- */
-
-
-/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
- * @brief RTC TimeStamp and Tamper functions
- *
-@verbatim
- ===============================================================================
- ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure TimeStamp feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set TimeStamp.
- * @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: RTC handle
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
- * The RTC TimeStamp Pin is per default PC13, but for reasons of
- * compatibility, this parameter is required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- tmpreg|= TimeStampEdge;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set TimeStamp with Interrupt.
- * @param hrtc: RTC handle
- * @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
- * The RTC TimeStamp Pin is per default PC13, but for reasons of
- * compatibility, this parameter is required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- tmpreg |= TimeStampEdge;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
- /* Enable IT timestamp */
- __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-
- /* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate TimeStamp.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tmpreg = 0;
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Internal TimeStamp.
- * @note This API must be called before enabling the internal TimeStamp feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the internal Time Stamp Enable bits */
- __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Deactivate Internal TimeStamp.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-
- /* Configure the internal Time Stamp Enable bits */
- __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC TimeStamp value.
- * @param hrtc: RTC handle
- * @param sTimeStamp: Pointer to Time structure
- * @param sTimeStampDate: Pointer to Date structure
- * @param Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
- sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-
- /* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the TimeStamp structure parameters to Binary format */
- sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
- sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
- sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
- /* Convert the DateTimeStamp structure parameters to Binary format */
- sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
- sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
- sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
- }
-
- /* Clear the TIMESTAMP Flags */
- __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Tamper.
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
- * @param sTamper: Pointer to Tamper Structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
- assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
- assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Configure the tamper trigger */
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
- {
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
- }
-
- if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
- {
- sTamper->NoErase = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
- }
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
- }
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
- }
- }
-
- if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
- {
- sTamper->MaskFlag = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
- }
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
- }
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
- }
- }
-
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\
- (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
- (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
- hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
- (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
- (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
- (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
-
- hrtc->Instance->TAMPCR |= tmpreg;
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Tamper with interrupt.
- * @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
- * @param sTamper: Pointer to RTC Tamper.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
- assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
- assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Configure the tamper trigger */
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
- {
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
- }
-
- if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
- {
- sTamper->NoErase = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
- }
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
- }
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
- {
- sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
- }
- }
-
- if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
- {
- sTamper->MaskFlag = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
- }
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
- }
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
- {
- sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
- }
- }
-
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\
- (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
- (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
- hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\
- (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\
- (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
- (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
-
- hrtc->Instance->TAMPCR |= tmpreg;
-
- /* RTC Tamper Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate Tamper.
- * @param hrtc: RTC handle
- * @param Tamper: Selected tamper pin.
- * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
- assert_param(IS_RTC_TAMPER(Tamper));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the selected Tamper pin */
- hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
-
- if ((Tamper & RTC_TAMPER_1) != 0)
- {
- /* Disable the Tamper1 interrupt */
- hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
- }
- if ((Tamper & RTC_TAMPER_2) != 0)
- {
- /* Disable the Tamper2 interrupt */
- hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
- }
- if ((Tamper & RTC_TAMPER_3) != 0)
- {
- /* Disable the Tamper3 interrupt */
- hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
- }
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle TimeStamp interrupt request.
- * @param hrtc: RTC handle
- * @retval None
- */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
- /* Get the TimeStamp interrupt source enable status */
- if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
- {
- /* Get the pending status of the TIMESTAMP Interrupt */
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
- {
-
- /* TIMESTAMP callback */
- HAL_RTCEx_TimeStampEventCallback(hrtc);
-
- /* Clear the TIMESTAMP interrupt pending bit */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
- }
- }
-
- /* Get the Tamper1 interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET)
- {
- /* Get the pending status of the Tamper1 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
- {
- /* Tamper1 callback */
- HAL_RTCEx_Tamper1EventCallback(hrtc);
-
- /* Clear the Tamper1 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
- }
- }
-
- /* Get the Tamper2 interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET)
- {
- /* Get the pending status of the Tamper2 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
- {
- /* Tamper2 callback */
- HAL_RTCEx_Tamper2EventCallback(hrtc);
-
- /* Clear the Tamper2 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
- }
- }
-
- /* Get the Tamper3 interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET)
- {
- /* Get the pending status of the Tamper3 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
- {
- /* Tamper3 callback */
- HAL_RTCEx_Tamper3EventCallback(hrtc);
-
- /* Clear the Tamper3 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
- }
- }
-
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief TimeStamp callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tamper 1 callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tamper 2 callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tamper 3 callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle TimeStamp polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
- {
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
- {
- /* Clear the TIMESTAMP OverRun Flag */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
- /* Change TIMESTAMP state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Tamper1 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Tamper2 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Tamper3 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
- * @brief RTC Wake-up functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Wake-up functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure Wake-up feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set wake up timer.
- * @param hrtc: RTC handle
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
- {
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
- /* Enable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set wake up timer with interrupt.
- * @param hrtc: RTC handle
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
- {
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Disable the Wake-Up timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* Clear flag Wake-Up */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
- /* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
- /* Enable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate wake up timer counter.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Disable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get wake up timer counter.
- * @param hrtc: RTC handle
- * @retval Counter value
- */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
- /* Get the counter value */
- return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Handle Wake Up Timer interrupt request.
- * @param hrtc: RTC handle
- * @retval None
- */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
- /* Get the pending status of the WAKEUPTIMER Interrupt */
- if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
- {
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- /* WAKEUPTIMER callback */
- HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Wake Up Timer callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle Wake Up Timer Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the WAKEUPTIMER Flag */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Write a data in a specified RTC Backup data register
- (+) Read a data in a specified RTC Backup data register
- (+) Set the Coarse calibration parameters.
- (+) Deactivate the Coarse calibration parameters
- (+) Set the Smooth calibration parameters.
- (+) Configure the Synchronization Shift Control Settings.
- (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enable the RTC reference clock detection.
- (+) Disable the RTC reference clock detection.
- (+) Enable the Bypass Shadow feature.
- (+) Disable the Bypass Shadow feature.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Write a data in a specified RTC Backup data register.
- * @param hrtc: RTC handle
- * @param BackupRegister: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Read data from the specified RTC Backup data Register.
- * @param hrtc: RTC handle
- * @param BackupRegister: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval Read value
- */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @brief Set the Smooth calibration parameters.
- * @param hrtc: RTC handle
- * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values :
- * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
- * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
- * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
- * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
- * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmoothCalibMinusPulsesValue must be equal to 0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* check if a calibration is pending*/
- if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
- {
- tickstart = HAL_GetTick();
-
- /* check if a calibration is pending*/
- while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: RTC handle
- * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
- * This parameter can be one of the following values :
- * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
- * @arg RTC_SHIFTADD1S_RESET: No effect.
- * @param ShiftSubFS: Select the number of Second Fractions to substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- tickstart = HAL_GetTick();
-
- /* Wait until the shift is completed*/
- while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the reference clock detection is disabled */
- if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- }
- else
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
- * @param CalibOutput : Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
- * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Clear flags before config */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
- /* Configure the RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)CalibOutput;
-
- __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the RTC reference clock detection.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the RTC reference clock detection.
- * @param hrtc: RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the Bypass Shadow feature.
- * @param hrtc: RTC handle
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set the BYPSHAD bit */
- hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Bypass Shadow feature.
- * @param hrtc: RTC handle
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Reset the BYPSHAD bit */
- hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) RTC Alarm B callback
- (+) RTC Poll for Alarm B request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Alarm B callback.
- * @param hrtc: RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle Alarm B Polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm Flag */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c
deleted file mode 100644
index e0d95f6..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c
+++ /dev/null
@@ -1,2330 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sai.c
- * @author MCD Application Team
- * @brief SAI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Audio Interface (SAI) peripheral:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- The SAI HAL driver can be used as follows:
-
- (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
- (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
- (##) Enable the SAI interface clock.
- (##) SAI pins configuration:
- (+++) Enable the clock for the SAI GPIOs.
- (+++) Configure these SAI pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
- and HAL_SAI_Receive_IT() APIs):
- (+++) Configure the SAI interrupt priority.
- (+++) Enable the NVIC SAI IRQ handle.
-
- (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
- and HAL_SAI_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Stream.
-
- (#) The initialization can be done by two ways
- (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
- (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
-
- [..]
- (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
- will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
- inside the transmit and receive process.
- [..]
- (@) Make sure that either:
- (+@) PLLSAI1CLK output is configured or
- (+@) PLLSAI2CLK output is configured or
- (+@) PLLSAI3CLK output is configured or
- (+@) PLLSAI4ACLK output is configured or
- (+@) PLLSAI4BCLK output is configured or
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
-
- [..]
- (@) In master Tx mode: enabling the audio block immediately generates the bit clock
- for the external slaves even if there is no data in the FIFO, However FS signal
- generation is conditioned by the presence of data in the FIFO.
-
- [..]
- (@) In master Rx mode: enabling the audio block immediately generates the bit clock
- and FS signal for the external slaves.
-
- [..]
- (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
- (+@) First bit Offset <= (SLOT size - Data size)
- (+@) Data size <= SLOT size
- (+@) Number of SLOT x SLOT size = Frame length
- (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
-
- [..]
- (@) PDM interface can be activated through HAL_SAI_Init function.
- Please note that PDM interface is only available for SAIx sub-block A.
- PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
-
- [..]
- Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
- (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
- (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
- (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SAI_ErrorCallback()
-
- *** DMA mode IO operation ***
- =============================
- [..]
- (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
- (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
- (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
- (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SAI_ErrorCallback()
- (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
- (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
- (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
-
- *** SAI HAL driver additional function list ***
- ===============================================
- [..]
- Below the list the others API available SAI HAL driver :
-
- (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
- (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
- (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
- (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
- (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
- (+) HAL_SAI_Abort(): Abort the current transfer
-
- *** SAI HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in SAI HAL driver :
-
- (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
- (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
- (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
- (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
- (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
- enabled or disabled
- (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SAI SAI
- * @brief SAI HAL module driver
- * @{
- */
-
-#ifdef HAL_SAI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-
-/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
- * @{
- */
-typedef enum {
- SAI_MODE_DMA,
- SAI_MODE_IT
-}SAI_ModeTypedef;
-/**
- * @}
- */
-
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup SAI_Private_Constants SAI Private Constants
- * @{
- */
-#define SAI_FIFO_SIZE 8U
-#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */
-#define SAI_LONG_TIMEOUT 1000U
-#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
-#define SAI_PDMCR_MICNBR_OFFSET POSITION_VAL(SAI_PDMCR_MICNBR)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup SAI_Private_Functions SAI Private Functions
- * @{
- */
-static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
-static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
-static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
-static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
-
-static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
-static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
-static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
-static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
-static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
-static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
-static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
-
-static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SAI_DMAError(DMA_HandleTypeDef *hdma);
-static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SAI_Exported_Functions SAI Exported Functions
- * @{
- */
-
-/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SAIx peripheral:
-
- (+) User must implement HAL_SAI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SAI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode (Master/slave TX/RX)
- (++) Protocol
- (++) Data Size
- (++) MCLK Output
- (++) Audio frequency
- (++) FIFO Threshold
- (++) Frame Config
- (++) Slot Config
- (++) PDM Config
-
- (+) Call the function HAL_SAI_DeInit() to restore the default configuration
- of the selected SAI peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the structure FrameInit, SlotInit and the low part of
- * Init according to the specified parameters and call the function
- * HAL_SAI_Init to initialize the SAI block.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param protocol one of the supported protocol @ref SAI_Protocol
- * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
- * the configuration information for SAI module.
- * @param nbslot Number of slot.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
- assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
-
- switch(protocol)
- {
- case SAI_I2S_STANDARD :
- case SAI_I2S_MSBJUSTIFIED :
- case SAI_I2S_LSBJUSTIFIED :
- status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
- break;
- case SAI_PCM_LONG :
- case SAI_PCM_SHORT :
- status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
- break;
- default :
- status = HAL_ERROR;
- break;
- }
-
- if(status == HAL_OK)
- {
- status = HAL_SAI_Init(hsai);
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the SAI according to the specified parameters.
- * in the SAI_InitTypeDef structure and initialize the associated handle.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
-{
- uint32_t tmpregisterGCR = 0;
- uint32_t ckstr_bits = 0;
- uint32_t syncen_bits = 0;
- SAI_TypeDef *SaiBaseAddress;
-
- /* Check the SAI handle allocation */
- if(hsai == NULL)
- {
- return HAL_ERROR;
- }
-
- /* check the instance */
- assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
-
- /* Check the SAI Block parameters */
- assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
- assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
- assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
- assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
- assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
- assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
- assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
- assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
- assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
- assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
- assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
- assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
- assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
- assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
- assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
-
- /* Check the SAI Block Frame parameters */
- assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
- assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
- assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
- assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
- assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
-
- /* Check the SAI Block Slot parameters */
- assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
- assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
- assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
- assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
-
- /* Check the SAI PDM parameters */
- assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
-
- if(hsai->Init.PdmInit.Activation == ENABLE)
- {
- /* Check the SAI PDM Microphone pairs number parameter */
- assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
-
- /* Check the SAI PDM clock enable paramater */
- assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
-
- /* The PDM function is intended to be used in conjunction with SAI_A sub-block
- configured in TDM MASTER mode. It cannot be used with SAI_B sub-block.
- Make sure that the SAI is already operating in TDM master mode before
- enabling the PDM interface */
- if(((hsai->Instance != SAI1_Block_A) && (hsai->Instance != SAI2_Block_A) && \
- (hsai->Instance != SAI3_Block_A) && (hsai->Instance != SAI4_Block_A)) || \
- (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || \
- (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
- {
- return HAL_ERROR;
- }
- }
-
- /* Get the SAI base address according to the SAI handle */
- if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
- {
- SaiBaseAddress = SAI1;
- }
- else if((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
- {
- SaiBaseAddress = SAI2;
- }
- else if((hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI3_Block_B))
- {
- SaiBaseAddress = SAI3;
- }
- else
- {
- SaiBaseAddress = SAI4;
- }
-
- if(hsai->State == HAL_SAI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsai->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_SAI_MspInit(hsai);
- }
-
- hsai->State = HAL_SAI_STATE_BUSY;
-
- /* Disable the selected SAI peripheral */
- SAI_Disable(hsai);
-
- /* SAI PDM Configuration -----------------------------------------*/
- /* Disable PDM interface */
- CLEAR_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
-
- if(hsai->Init.PdmInit.Activation == ENABLE)
- {
- /* Configure and enable the PDM interface */
- SaiBaseAddress->PDMCR = (hsai->Init.PdmInit.ClockEnable |
- ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_OFFSET));
- SET_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
- }
-
- /* SAI Block Synchro Configuration -----------------------------------------*/
- /* This setting must be done with both audio block (A & B) disabled */
- switch(hsai->Init.SynchroExt)
- {
- case SAI_SYNCEXT_DISABLE :
- tmpregisterGCR = 0;
- break;
- case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
- tmpregisterGCR = SAI_GCR_SYNCOUT_0;
- break;
- case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
- tmpregisterGCR = SAI_GCR_SYNCOUT_1;
- break;
- default:
- break;
- }
-
- switch(hsai->Init.Synchro)
- {
- case SAI_ASYNCHRONOUS :
- {
- syncen_bits = 0;
- }
- break;
- case SAI_SYNCHRONOUS :
- {
- syncen_bits = SAI_xCR1_SYNCEN_0;
- }
- break;
- case SAI_SYNCHRONOUS_EXT_SAI1 :
- {
- syncen_bits = SAI_xCR1_SYNCEN_1;
- }
- break;
- case SAI_SYNCHRONOUS_EXT_SAI2 :
- {
- syncen_bits = SAI_xCR1_SYNCEN_1;
- tmpregisterGCR |= SAI_GCR_SYNCIN_0;
- }
- break;
- default:
- break;
- }
-
- /* Set the SAI Block Synchro Configuration */
- SaiBaseAddress->GCR = tmpregisterGCR;
-
- if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
- {
- uint32_t freq = 0;
- uint32_t tmpval;
-
- if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))
- {
- freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
- }
- if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))
- {
- freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
- }
- if((hsai->Instance == SAI3_Block_A ) || (hsai->Instance == SAI3_Block_B ))
- {
- freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI3);
- }
- if(hsai->Instance == SAI4_Block_A)
- {
- freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4A);
- }
- if(hsai->Instance == SAI4_Block_B)
- {
- freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI4B);
- }
-
- /* Configure Master Clock using the following formula :
- If NOMCK = 1
- MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
- If NOMCK = 0
- MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
- if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
- {
- /* (freq x 10) to keep Significant digits */
- tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
- }
- else
- {
- /* NOMCK = 0 */
- uint32_t tmposr;
-
- tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE)? 2 : 1;
-
- /* (freq x 10) to keep Significant digits */
- tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256);
- }
-
- hsai->Init.Mckdiv = tmpval / 10;
-
- /* Round result to the nearest integer */
- if((tmpval % 10) > 8)
- {
- hsai->Init.Mckdiv += 1;
- }
- }
-
- /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
- if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
- { /* Transmit */
- ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;
- }
- else
- { /* Receive */
- ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;
- }
-
- /* SAI Block Configuration -------------------------------------------------*/
- /* SAI CR1 Configuration */
- hsai->Instance->CR1 &=~ (SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
- SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
- SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
- SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV);
-
- hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
- hsai->Init.DataSize | hsai->Init.FirstBit | \
- ckstr_bits | syncen_bits | \
- hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
- hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \
- hsai->Init.MckOverSampling);
-
- /* SAI CR2 Configuration */
- hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
- hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
-
- /* SAI Frame Configuration -----------------------------------------*/
- hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
- SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
- hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1) | \
- hsai->FrameInit.FSOffset | \
- hsai->FrameInit.FSDefinition | \
- hsai->FrameInit.FSPolarity | \
- ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
-
- /* SAI Block_x SLOT Configuration ------------------------------------------*/
- /* This register has no meaning in AC 97 and SPDIF audio protocol */
- hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
- SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
-
- hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
- (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8);
-
- /* Initialize the error code */
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
- /* Initialize the SAI state */
- hsai->State= HAL_SAI_STATE_READY;
-
- /* Release Lock */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the SAI peripheral.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
-{
- SAI_TypeDef *SaiBaseAddress;
-
- /* Check the SAI handle allocation */
- if(hsai == NULL)
- {
- return HAL_ERROR;
- }
-
- hsai->State = HAL_SAI_STATE_BUSY;
-
- /* Disabled All interrupt and clear all the flag */
- hsai->Instance->IMR = 0;
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
-
- /* Disable the SAI PDM interface */
- if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI2_Block_A) || \
- (hsai->Instance == SAI3_Block_A) || (hsai->Instance == SAI4_Block_A))
- {
- /* Get the SAI base address according to the SAI handle */
- SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : \
- ((hsai->Instance == SAI2_Block_A) ? SAI2 : \
- ((hsai->Instance == SAI3_Block_A) ? SAI3 : SAI4));
-
- /* Disable PDM interface */
- CLEAR_BIT(SaiBaseAddress->PDMCR, SAI_PDMCR_PDMEN);
- }
-
- /* Disable the SAI */
- SAI_Disable(hsai);
-
- /* Flush the fifo */
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_SAI_MspDeInit(hsai);
-
- /* Initialize the error code */
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
- /* Initialize the SAI state */
- hsai->State = HAL_SAI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SAI MSP.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SAI MSP.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SAI data
- transfers.
-
- (+) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (+) Blocking mode functions are :
- (++) HAL_SAI_Transmit()
- (++) HAL_SAI_Receive()
-
- (+) Non Blocking mode functions with Interrupt are :
- (++) HAL_SAI_Transmit_IT()
- (++) HAL_SAI_Receive_IT()
-
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SAI_Transmit_DMA()
- (++) HAL_SAI_Receive_DMA()
-
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SAI_TxCpltCallback()
- (++) HAL_SAI_RxCpltCallback()
- (++) HAL_SAI_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- if((pData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->pBuffPtr = pData;
- hsai->State = HAL_SAI_STATE_BUSY_TX;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* fill the fifo with data before to enabled the SAI */
- SAI_FillFifo(hsai);
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- while(hsai->XferCount > 0)
- {
- /* Write data if the FIFO is not full */
- if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
- {
- if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
- {
- hsai->Instance->DR = (*hsai->pBuffPtr++);
- }
- else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
- {
- hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
- hsai->pBuffPtr+= 2;
- }
- else
- {
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr+= 4;
- }
- hsai->XferCount--;
- }
- else
- {
- /* Check for the Timeout */
- if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
- {
- /* Update error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-
- /* Clear all the flags */
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
-
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Flush the fifo */
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
-
- /* Change the SAI state */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_ERROR;
- }
- }
- }
-
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- if((pData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->pBuffPtr = pData;
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->State = HAL_SAI_STATE_BUSY_RX;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- /* Receive data */
- while(hsai->XferCount > 0)
- {
- if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
- {
- if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
- {
- (*hsai->pBuffPtr++) = hsai->Instance->DR;
- }
- else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
- {
- *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
- hsai->pBuffPtr+= 2;
- }
- else
- {
- *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
- hsai->pBuffPtr+= 4;
- }
- hsai->XferCount--;
- }
- else
- {
- /* Check for the Timeout */
- if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
- {
- /* Update error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-
- /* Clear all the flags */
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
-
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Flush the fifo */
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
-
- /* Change the SAI state */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_ERROR;
- }
- }
- }
-
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
-{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->pBuffPtr = pData;
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
- hsai->State = HAL_SAI_STATE_BUSY_TX;
-
- if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
- {
- hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
- }
- else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
- {
- hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
- }
- else
- {
- hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
- }
-
- /* Fill the fifo before starting the communication */
- SAI_FillFifo(hsai);
-
- /* Enable FRQ and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
-{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->pBuffPtr = pData;
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
- hsai->State = HAL_SAI_STATE_BUSY_RX;
-
- if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
- {
- hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
- }
- else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
- {
- hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
- }
- else
- {
- hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
- }
-
- /* Enable TXE and OVRUDR interrupts */
- __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the audio stream playing from the Media.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
-{
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Pause the audio file playing by disabling the SAI DMA requests */
- hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the audio stream playing from the Media.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
-{
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Enable the SAI DMA requests */
- hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
- /* If the SAI peripheral is still not enabled, enable it */
- if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the audio stream playing from the Media.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Disable the SAI DMA request */
- hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Abort the SAI Tx DMA Stream */
- if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
- {
- if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
- {
- /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
- if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
- {
- status = HAL_ERROR;
- }
- }
- }
-
- /* Abort the SAI Rx DMA Stream */
- if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
- {
- if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
- {
- /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
- if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
- {
- status = HAL_ERROR;
- }
- }
- }
-
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Set hsai state to ready */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return status;
-}
-
-/**
- * @brief Abort the current transfer and disable the SAI.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
-{
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- /* Check SAI DMA is enabled or not */
- if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
- {
- /* Disable the SAI DMA request */
- hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
- {
- if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
-
- if(hsai->hdmarx != NULL)
- {
- if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
- }
-
- /* Disabled All interrupt and clear all the flag */
- hsai->Instance->IMR = 0;
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
-
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Flush the fifo */
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
-
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = HAL_GetTick();
-
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->pBuffPtr = pData;
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
- hsai->State = HAL_SAI_STATE_BUSY_TX;
-
- /* Set the SAI Tx DMA Half transfer complete callback */
- hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
-
- /* Set the SAI TxDMA transfer complete callback */
- hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
-
- /* Set the DMA error callback */
- hsai->hdmatx->XferErrorCallback = SAI_DMAError;
-
- /* Set the DMA Tx abort callback */
- hsai->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream */
- if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
- {
- __HAL_UNLOCK(hsai);
- return HAL_ERROR;
- }
-
- /* Enable the interrupts for error handling */
- __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
-
- /* Enable SAI Tx DMA Request */
- hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
- /* Wait untill FIFO is not empty */
- while((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
- {
- /* Update error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
-{
-
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- if(hsai->State == HAL_SAI_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsai);
-
- hsai->pBuffPtr = pData;
- hsai->XferSize = Size;
- hsai->XferCount = Size;
- hsai->ErrorCode = HAL_SAI_ERROR_NONE;
- hsai->State = HAL_SAI_STATE_BUSY_RX;
-
- /* Set the SAI Rx DMA Half transfer complete callback */
- hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
-
- /* Set the SAI Rx DMA transfer complete callback */
- hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
-
- /* Set the DMA error callback */
- hsai->hdmarx->XferErrorCallback = SAI_DMAError;
-
- /* Set the DMA Rx abort callback */
- hsai->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream */
- if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
- {
- __HAL_UNLOCK(hsai);
- return HAL_ERROR;
- }
-
- /* Check if the SAI is already enabled */
- if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
- {
- /* Enable SAI peripheral */
- __HAL_SAI_ENABLE(hsai);
- }
-
- /* Enable the interrupts for error handling */
- __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
-
- /* Enable SAI Rx DMA Request */
- hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsai);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the Tx mute mode.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param val value sent during the mute @ref SAI_Block_Mute_Value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
-{
- assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
-
- if(hsai->State != HAL_SAI_STATE_RESET)
- {
- CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
- return HAL_OK;
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Disable the Tx mute mode.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
-{
- if(hsai->State != HAL_SAI_STATE_RESET)
- {
- CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
- return HAL_OK;
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Enable the Rx mute detection.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param callback function called when the mute is detected.
- * @param counter number a data before mute detection max 63.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
-{
- assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
-
- if(hsai->State != HAL_SAI_STATE_RESET)
- {
- /* set the mute counter */
- CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
- SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
- hsai->mutecallback = callback;
- /* enable the IT interrupt */
- __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
- return HAL_OK;
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Disable the Rx mute detection.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
-{
- if(hsai->State != HAL_SAI_STATE_RESET)
- {
- /* set the mutecallback to NULL */
- hsai->mutecallback = (SAIcallback)NULL;
- /* enable the IT interrupt */
- __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
- return HAL_OK;
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Handle SAI interrupt request.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
-{
- if(hsai->State != HAL_SAI_STATE_RESET)
- {
- uint32_t itflags = hsai->Instance->SR;
- uint32_t itsources = hsai->Instance->IMR;
- uint32_t cr1config = hsai->Instance->CR1;
- uint32_t tmperror;
-
- /* SAI Fifo request interrupt occured ------------------------------------*/
- if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
- {
- hsai->InterruptServiceRoutine(hsai);
- }
- /* SAI Overrun error interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
- {
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
- /* Get the SAI error code */
- tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
- /* Change the SAI error code */
- hsai->ErrorCode |= tmperror;
- /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
- HAL_SAI_ErrorCallback(hsai);
- }
- /* SAI mutedet interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
- {
- /* Clear the SAI mutedet flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
- /* call the call back function */
- if(hsai->mutecallback != (SAIcallback)NULL)
- {
- /* inform the user that an RX mute event has been detected */
- hsai->mutecallback();
- }
- }
- /* SAI AFSDET interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
- {
- /* Change the SAI error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
-
- /* Check SAI DMA is enabled or not */
- if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
- {
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
- }
- else if(hsai->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
- }
- }
- else
- {
- /* Abort SAI */
- HAL_SAI_Abort(hsai);
-
- /* Set error callback */
- HAL_SAI_ErrorCallback(hsai);
- }
- }
- /* SAI LFSDET interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
- {
- /* Change the SAI error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
-
- /* Check SAI DMA is enabled or not */
- if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
- {
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
- }
- else if(hsai->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
- }
- }
- else
- {
- /* Abort SAI */
- HAL_SAI_Abort(hsai);
-
- /* Set error callback */
- HAL_SAI_ErrorCallback(hsai);
- }
- }
- /* SAI WCKCFG interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
- {
- /* Change the SAI error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
-
- /* Check SAI DMA is enabled or not */
- if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
- {
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmatx);
- }
- else if(hsai->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
-
- /* Abort DMA in IT mode */
- HAL_DMA_Abort_IT(hsai->hdmarx);
- }
- }
- else
- {
- /* If WCKCFG occurs, SAI audio block is automatically disabled */
- /* Disable all interrupts and clear all flags */
- hsai->Instance->IMR = 0U;
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
- /* Set the SAI state to ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Initialize XferCount */
- hsai->XferCount = 0U;
-
- /* SAI error Callback */
- HAL_SAI_ErrorCallback(hsai);
- }
- }
- /* SAI CNRDY interrupt occurred ----------------------------------*/
- else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
- {
- /* Clear the SAI CNRDY flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
- /* Change the SAI error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
- /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
- HAL_SAI_ErrorCallback(hsai);
- }
- else
- {
- /* Nothing to do */
- }
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer Half completed callback.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer half completed callback.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SAI error callback.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsai);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SAI_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SAI handle state.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval HAL state
- */
-HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
-{
- return hsai->State;
-}
-
-/**
-* @brief Return the SAI error code.
-* @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for the specified SAI Block.
-* @retval SAI Error Code
-*/
-uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
-{
- return hsai->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SAI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief Initialize the SAI I2S protocol according to the specified parameters
- * in the SAI_InitTypeDef and create the associated handle.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param protocol one of the supported protocol.
- * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize.
- * @param nbslot number of slot minimum value is 2 and max is 16.
- * the value must be a multiple of 2.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
-{
- hsai->Init.Protocol = SAI_FREE_PROTOCOL;
- hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
- /* Compute ClockStrobing according AudioMode */
- if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
- { /* Transmit */
- hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
- }
- else
- { /* Receive */
- hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
- }
- hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
- hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
- hsai->SlotInit.FirstBitOffset = 0;
- hsai->SlotInit.SlotNumber = nbslot;
-
- /* in IS2 the number of slot must be even */
- if((nbslot & 0x1) != 0 )
- {
- return HAL_ERROR;
- }
-
- switch(protocol)
- {
- case SAI_I2S_STANDARD :
- hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
- hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
- break;
- case SAI_I2S_MSBJUSTIFIED :
- case SAI_I2S_LSBJUSTIFIED :
- hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
- hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
- break;
- default :
- return HAL_ERROR;
- }
-
- /* Frame definition */
- switch(datasize)
- {
- case SAI_PROTOCOL_DATASIZE_16BIT:
- hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 32*(nbslot/2);
- hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
- break;
- case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
- hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 64*(nbslot/2);
- hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- case SAI_PROTOCOL_DATASIZE_24BIT:
- hsai->Init.DataSize = SAI_DATASIZE_24;
- hsai->FrameInit.FrameLength = 64*(nbslot/2);
- hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- case SAI_PROTOCOL_DATASIZE_32BIT:
- hsai->Init.DataSize = SAI_DATASIZE_32;
- hsai->FrameInit.FrameLength = 64*(nbslot/2);
- hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- default :
- return HAL_ERROR;
- }
- if(protocol == SAI_I2S_LSBJUSTIFIED)
- {
- if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
- {
- hsai->SlotInit.FirstBitOffset = 16;
- }
- if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
- {
- hsai->SlotInit.FirstBitOffset = 8;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SAI PCM protocol according to the specified parameters
- * in the SAI_InitTypeDef and create the associated handle.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param protocol one of the supported protocol
- * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
- * @param nbslot number of slot minimum value is 1 and the max is 16.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
-{
- hsai->Init.Protocol = SAI_FREE_PROTOCOL;
- hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;
- /* Compute ClockStrobing according AudioMode */
- if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
- { /* Transmit */
- hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE;
- }
- else
- { /* Receive */
- hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
- }
- hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;
- hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
- hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
- hsai->SlotInit.FirstBitOffset = 0;
- hsai->SlotInit.SlotNumber = nbslot;
- hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
-
- switch(protocol)
- {
- case SAI_PCM_SHORT :
- hsai->FrameInit.ActiveFrameLength = 1;
- break;
- case SAI_PCM_LONG :
- hsai->FrameInit.ActiveFrameLength = 13;
- break;
- default :
- return HAL_ERROR;
- }
-
- switch(datasize)
- {
- case SAI_PROTOCOL_DATASIZE_16BIT:
- hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 16 * nbslot;
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
- break;
- case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
- hsai->Init.DataSize = SAI_DATASIZE_16;
- hsai->FrameInit.FrameLength = 32 * nbslot;
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- case SAI_PROTOCOL_DATASIZE_24BIT :
- hsai->Init.DataSize = SAI_DATASIZE_24;
- hsai->FrameInit.FrameLength = 32 * nbslot;
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- case SAI_PROTOCOL_DATASIZE_32BIT:
- hsai->Init.DataSize = SAI_DATASIZE_32;
- hsai->FrameInit.FrameLength = 32 * nbslot;
- hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
- break;
- default :
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Fill the fifo.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
-{
- /* fill the fifo with data before to enabled the SAI */
- while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
- {
- if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
- {
- hsai->Instance->DR = (*hsai->pBuffPtr++);
- }
- else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
- {
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr+= 2;
- }
- else
- {
- hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
- hsai->pBuffPtr+= 4;
- }
- hsai->XferCount--;
- }
-}
-
-/**
- * @brief Return the interrupt flag to set according the SAI setup.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @param mode SAI_MODE_DMA or SAI_MODE_IT
- * @retval the list of the IT flag to enable
- */
-static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
-{
- uint32_t tmpIT = SAI_IT_OVRUDR;
-
- if(mode == SAI_MODE_IT)
- {
- tmpIT|= SAI_IT_FREQ;
- }
-
- if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
- ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
- {
- tmpIT|= SAI_IT_CNRDY;
- }
-
- if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
- {
- tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
- }
- else
- {
- /* hsai has been configured in master mode */
- tmpIT|= SAI_IT_WCKCFG;
- }
- return tmpIT;
-}
-
-/**
- * @brief Disable the SAI and wait for the disabling.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
-{
- register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000);
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Disable the SAI instance */
- __HAL_SAI_DISABLE(hsai);
-
- do
- {
- /* Check for the Timeout */
- if (count-- == 0)
- {
- /* Update error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
- status = HAL_TIMEOUT;
- break;
- }
- } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
-
- return status;
-}
-
-/**
- * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
-{
- if(hsai->XferCount == 0)
- {
- /* Handle the end of the transmission */
- /* Disable FREQ and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_TxCpltCallback(hsai);
- }
- else
- {
- /* Write data on DR register */
- hsai->Instance->DR = (*hsai->pBuffPtr++);
- hsai->XferCount--;
- }
-}
-
-/**
- * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
-{
- if(hsai->XferCount == 0)
- {
- /* Handle the end of the transmission */
- /* Disable FREQ and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_TxCpltCallback(hsai);
- }
- else
- {
- /* Write data on DR register */
- hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
- hsai->pBuffPtr+=2;
- hsai->XferCount--;
- }
-}
-
-/**
- * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
-{
- if(hsai->XferCount == 0)
- {
- /* Handle the end of the transmission */
- /* Disable FREQ and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_TxCpltCallback(hsai);
- }
- else
- {
- /* Write data on DR register */
- hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
- hsai->pBuffPtr+=4;
- hsai->XferCount--;
- }
-}
-
-/**
- * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
-{
- /* Receive data */
- (*hsai->pBuffPtr++) = hsai->Instance->DR;
- hsai->XferCount--;
-
- /* Check end of the transfer */
- if(hsai->XferCount == 0)
- {
- /* Disable TXE and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
-
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
-
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_RxCpltCallback(hsai);
- }
-}
-
-/**
- * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
-{
- /* Receive data */
- *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
- hsai->pBuffPtr+=2;
- hsai->XferCount--;
-
- /* Check end of the transfer */
- if(hsai->XferCount == 0)
- {
- /* Disable TXE and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
-
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
-
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_RxCpltCallback(hsai);
- }
-}
-/**
- * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
- * @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for SAI module.
- * @retval None
- */
-static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
-{
- /* Receive data */
- *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
- hsai->pBuffPtr+=4;
- hsai->XferCount--;
-
- /* Check end of the transfer */
- if(hsai->XferCount == 0)
- {
- /* Disable TXE and OVRUDR interrupts */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
-
- /* Clear the SAI Overrun flag */
- __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
-
- hsai->State = HAL_SAI_STATE_READY;
- HAL_SAI_RxCpltCallback(hsai);
- }
-}
-
-/**
- * @brief DMA SAI transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(hdma->Init.Mode != DMA_CIRCULAR)
- {
- hsai->XferCount = 0;
-
- /* Disable SAI Tx DMA Request */
- hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
-
- /* Stop the interrupts error handling */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
-
- hsai->State= HAL_SAI_STATE_READY;
- }
- HAL_SAI_TxCpltCallback(hsai);
-}
-
-/**
- * @brief DMA SAI transmit process half complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SAI_TxHalfCpltCallback(hsai);
-}
-
-/**
- * @brief DMA SAI receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(hdma->Init.Mode != DMA_CIRCULAR)
- {
- /* Disable Rx DMA Request */
- hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
- hsai->XferCount = 0;
-
- /* Stop the interrupts error handling */
- __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
-
- hsai->State = HAL_SAI_STATE_READY;
- }
- HAL_SAI_RxCpltCallback(hsai);
-}
-
-/**
- * @brief DMA SAI receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SAI_RxHalfCpltCallback(hsai);
-}
-/**
- * @brief DMA SAI communication error callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))
- {
- /* Disable the SAI DMA request */
- hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Set the SAI state ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Initialize XferCount */
- hsai->XferCount = 0U;
- }
-
- /* Ignore DMA FIFO error */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
- {
- /* Set SAI error code */
- hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
-
- /* SAI error Callback */
- HAL_SAI_ErrorCallback(hsai);
- }
-}
-
-/**
- * @brief DMA SAI Abort callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
-{
- SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable DMA request */
- hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Disable all interrupts and clear all flags */
- hsai->Instance->IMR = 0U;
- hsai->Instance->CLRFR = 0xFFFFFFFFU;
-
- if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
- {
- /* Disable SAI peripheral */
- SAI_Disable(hsai);
-
- /* Flush the fifo */
- SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
- }
- /* Set the SAI state to ready to be able to start again the process */
- hsai->State = HAL_SAI_STATE_READY;
-
- /* Initialize XferCount */
- hsai->XferCount = 0U;
-
- /* SAI error Callback */
- HAL_SAI_ErrorCallback(hsai);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SAI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c
deleted file mode 100644
index a0c06da..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sai_ex.c
- * @author MCD Application Team
- * @brief SAI Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionality of the SAI Peripheral Controller:
- * + Modify PDM microphone delays.
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#ifdef HAL_SAI_MODULE_ENABLED
-
-/** @defgroup SAIEx SAIEx
- * @brief SAI Extended HAL module driver
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-#define SAI_PDM_DELAY_MASK 0x77U
-#define SAI_PDM_DELAY_OFFSET 8U
-#define SAI_PDM_RIGHT_DELAY_OFFSET 4U
-
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
- * @{
- */
-
-/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief SAIEx control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Modify PDM microphone delays
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure PDM microphone delays.
- * @param hsai SAI handle.
- * @param pdmMicDelay Microphone delays configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
-{
- HAL_StatusTypeDef status = HAL_OK;
- SAI_TypeDef *SaiBaseAddress = NULL;
-
- /* Get the SAI base address according to the SAI handle */
- SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : \
- ((hsai->Instance == SAI2_Block_A) ? SAI2 : \
- ((hsai->Instance == SAI3_Block_A) ? SAI3 : \
- ((hsai->Instance == SAI4_Block_A) ? SAI4 : \
- NULL)));
- if((SaiBaseAddress != NULL) && (hsai->State != HAL_SAI_STATE_RESET))
- {
- /* Check microphone delay parameters */
- assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
- assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
- assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
-
- /* Reset current delays for specified microphone */
- SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
-
- /* Apply new microphone delays */
- SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \
- (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
- }
- else
- {
- status = HAL_ERROR;
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SAI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
deleted file mode 100644
index 41d0b32..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
+++ /dev/null
@@ -1,3081 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sd.c
- * @author MCD Application Team
- * @brief SD card HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (SD) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_SD_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
- examples.
- You can easily tailor this configuration according to hardware resources.
-
- [..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with SD and uSD cards devices.
- It is used as follows:
-
- (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
- (##) SDMMC pins configuration for SD card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
- and according to your pin assignment;
- (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority();
- (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
- and __HAL_SD_DISABLE_IT() inside the communication process.
- (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
- and __HAL_SD_CLEAR_IT()
- (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC IP are used.
-
- (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
-
- *** SD Card Initialization and configuration ***
- ================================================
- [..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- the SD Card and put it into StandBy State (Ready for data transfer).
- This function provide the following operations:
-
- (#) Apply the SD Card initialization process at 400KHz and check the SD Card
- type (Standard Capacity or High Capacity). You can change or adapt this
- frequency by adjusting the "ClockDiv" field.
- The SD Card frequency (SDMMC_CK) is computed as follows:
-
- SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
-
- In initialization mode and according to the SD Card standard,
- make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-
- (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
- structure. This structure provide also ready computed SD Card capacity
- and Block size.
-
- -@- These information are stored in SD handle structure in case of future use.
-
- (#) Configure the SD Card Data transfer frequency. You can change or adapt this
- frequency by adjusting the "ClockDiv" field.
- In transfer mode and according to the SD Card standard, make sure that the
- SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
-
- (#) Select the corresponding SD Card according to the address read with the step 2.
-
- (#) Configure the SD Card in wide bus mode: 4-bits data.
-
- *** SD Card Read operation ***
- ==============================
- [..]
- (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- *** SD Card Write operation ***
- ===============================
- [..]
- (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 byte).
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
-
- *** SD card status ***
- ======================
- [..]
- (+) At any time, you can check the SD Card status and get the SD card state
- by using the HAL_SD_GetStatusInfo() function. This function checks first if the
- SD card is still connected and then get the internal SD Card transfer state.
-
- *** SD HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in SD HAL driver.
-
- (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
- (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
- (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
- (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
-
- (@) You can refer to the SD HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SD
- * @{
- */
-
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
- * @{
- */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_PowerOFF(SD_HandleTypeDef *hsd);
-static void SD_Write_IT(SD_HandleTypeDef *hsd);
-static void SD_Read_IT(SD_HandleTypeDef *hsd);
-static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
-#if (USE_SD_TRANSCEIVER != 0U)
-static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
-#endif /* USE_SD_TRANSCEIVER */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
- * @{
- */
-
-/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize the SD
- card device to be ready for use.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SD according to the specified parameters in the
- SD_HandleTypeDef and create the associated handle.
- * @param hsd: Pointer to the SD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStatusTypedef CardStatus;
- uint32_t speedgrade, unitsize;
- uint32_t tickstart;
-
- /* Check the SD handle allocation */
- if(hsd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
- assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
- assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
- assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
- assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
- assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
-
- if(hsd->State == HAL_SD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsd->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_SD_MspInit(hsd);
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize the Card parameters */
- if (HAL_SD_InitCard(hsd) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
- {
- return HAL_ERROR;
- }
- /* Get Initial Card Speed from Card Status*/
- speedgrade = CardStatus.UhsSpeedGrade;
- unitsize = CardStatus.UhsAllocationUnitSize;
- if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
- {
- hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
- }
- else
- {
- if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
- {
- hsd->SdCard.CardSpeed = CARD_HIGH_SPEED;
- }
- else
- {
- hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED;
- }
-
- }
- /* Configure the bus wide */
- if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
- {
- return HAL_ERROR;
- }
-#if (USE_SD_TRANSCEIVER != 0U)
- if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
- {
- hsd->Instance->CLKCR |= 0x00100000U;
- /* Enable High Speed */
- if(SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- }
- else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
- {
- /* Enable High Speed */
- if(SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Normal Speed mode, Nothing todo */
- }
-#else
- if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
- (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
- {
- /* Enable High Speed */
- if(SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- }
-#endif /* USE_SD_TRANSCEIVER */
-
-
- /* Verify that SD card is ready to use after Initialization */
- tickstart = HAL_GetTick();
- while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
- {
- if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT)
- {
- hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the error code */
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- /* Initialize the SD operation */
- hsd->Context = SD_CONTEXT_NONE;
-
- /* Initialize the SD state */
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the SD Card.
- * @param hsd: Pointer to SD handle
- * @note This function initializes the SD card. It could be used when a card
- re-initialization is needed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate;
- HAL_StatusTypeDef status;
- SD_InitTypeDef Init;
-
- /* Default SDMMC peripheral configuration for SD card initialization */
- Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
- Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDMMC_BUS_WIDE_1B;
- Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
-
-#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
- /* Set Transceiver polarity */
- hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
-#endif /* USE_SD_TRANSCEIVER */
-
- /* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Set Power State to ON */
- status = SDMMC_PowerState_ON(hsd->Instance);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Identify card operating voltage */
- errorstate = SD_PowerON(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- /* Card initialization */
- errorstate = SD_InitCard(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the SD card.
- * @param hsd: Pointer to SD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
- /* Check the SD handle allocation */
- if(hsd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
-
- hsd->State = HAL_SD_STATE_BUSY;
-
-#if (USE_SD_TRANSCEIVER != 0U)
- /* Desactivate the 1.8V Mode */
- HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
-#endif /* USE_SD_TRANSCEIVER */
-
- /* Set SD power state to off */
- SD_PowerOFF(hsd);
-
- /* De-Initialize the MSP layer */
- HAL_SD_MspDeInit(hsd);
-
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_RESET;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the SD MSP.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize SD MSP.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the data
- transfer from/to SD card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of SD blocks to read
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count, data;
- uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Poll on SDMMC flags */
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
- {
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = SDMMC_ReadFIFO(hsd->Instance);
- *tempbuff = (uint8_t)(data & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
- tempbuff++;
- *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
- tempbuff++;
- }
- }
-
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
-
- /* Send stop transmission command in case of multiblock read */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of SD blocks to write
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count, data;
- uint32_t add = BlockAdd;
- uint8_t *tempbuff = pData;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write block(s) in polling mode */
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
- {
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = (uint32_t)(*tempbuff);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 8U);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 16U);
- tempbuff++;
- data |= ((uint32_t)(*tempbuff) << 24U);
- tempbuff++;
- (void)SDMMC_WriteFIFO(hsd->Instance, &data);
- }
- }
-
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
-
- /* Send stop transmission command in case of multiblock write */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Rx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pRxBuffPtr = pData;
- hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- /* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Tx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pTxBuffPtr = pData;
- hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- /* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Rx
- * interrupt event.
- * @param hsd: Pointer SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pRxBuffPtr = pData;
- hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
-
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
- hsd->Instance->IDMABASE0 = (uint32_t) pData ;
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Tx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t add = BlockAdd;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pTxBuffPtr = pData;
- hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
-
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
- hsd->Instance->IDMABASE0 = (uint32_t) pData ;
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Erases the specified memory area of the given SD card.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
-{
- uint32_t errorstate;
- uint32_t start_add = BlockStartAdd;
- uint32_t end_add = BlockEndAdd;
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- if(end_add < start_add)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(end_add > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Check if the card command class supports erase command */
- if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Get start and end block for high capacity cards */
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- start_add *= 512U;
- end_add *= 512U;
- }
-
- /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles SD card interrupt request.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate;
- uint32_t context = hsd->Context;
-
- /* Check for SDMMC interrupt flags */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
-
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
-
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
-
- if((context & SD_CONTEXT_IT) != 0U)
- {
- if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
- {
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- HAL_SD_ErrorCallback(hsd);
- }
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
- {
- HAL_SD_RxCpltCallback(hsd);
- }
- else
- {
- HAL_SD_TxCpltCallback(hsd);
- }
- }
- else if((context & SD_CONTEXT_DMA) != 0U)
- {
- hsd->Instance->DLEN = 0;
- hsd->Instance->DCTRL = 0;
- hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
- /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */
- if((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U)
- {
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- HAL_SD_ErrorCallback(hsd);
- }
- }
-
- hsd->State = HAL_SD_STATE_READY;
- if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
- {
- HAL_SD_TxCpltCallback(hsd);
- }
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
- {
- HAL_SD_RxCpltCallback(hsd);
- }
- }
- else
- {
- /* Nothing to do */
- }
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)
- {
- SD_Write_IT(hsd);
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)
- {
- SD_Read_IT(hsd);
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- }
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- /* Disable all interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
- hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
- hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
- hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
-
- if((context & SD_CONTEXT_IT) != 0U)
- {
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
- HAL_SD_ErrorCallback(hsd);
- }
- else if((context & SD_CONTEXT_DMA) != 0U)
- {
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- /* Disable Internal DMA */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
- hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
- HAL_SD_ErrorCallback(hsd);
- }
- }
- else
- {
- /* Nothing to do */
- }
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET)
- {
- if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
- {
- /* Current buffer is buffer0, Transfer complete for buffer1 */
- if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
- {
- HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd);
- }
- else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
- {
- HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd);
- }
- }
- else /* SD_DMA_BUFFER1 */
- {
- /* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
- {
- HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd);
- }
- else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
- {
- HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd);
- }
- }
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
- }
- else
- {
- /* Nothing to do */
- }
-}
-
-/**
- * @brief return the SD state
- * @param hsd: Pointer to sd handle
- * @retval HAL state
- */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
-{
- return hsd->State;
-}
-
-/**
-* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
-* @retval SD Error Code
-*/
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
-{
- return hsd->ErrorCode;
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief SD error callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief SD Abort callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_AbortCallback can be implemented in the user file
- */
-}
-
-#if (USE_SD_TRANSCEIVER != 0U)
-/**
- * @brief Enable/Disable the SD Transceiver 1.8V Mode Callback.
- * @param status: Voltage Switch State
- * @retval None
- */
-__weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
-{
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_EnableTransceiver could be implemented in the user file
- */
-}
-#endif /* USE_SD_TRANSCEIVER */
-
-
-/**
- * @}
- */
-
-/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SD card
- operations and get the related information
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CID register.
- * @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CIDTypedef structure that
- * contains all CID register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID)
-{
- pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
-
- pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
-
- pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
-
- pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
-
- pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
-
- pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
-
- pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
-
- pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
-
- pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
-
- pCID->Reserved2 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CSD register.
- * @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that
- * contains all CSD register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD)
-{
- pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
-
- pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
-
- pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
-
- pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
-
- pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
-
- pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
-
- pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
-
- pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
-
- pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
-
- pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
-
- pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
-
- pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
-
- pCSD->Reserved2 = 0U; /*!< Reserved */
-
- if(hsd->SdCard.CardType == CARD_SDSC)
- {
- pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
-
- pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
-
- pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
-
- pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
-
- pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
-
- pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
-
- hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
- hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
-
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
- hsd->SdCard.LogBlockSize = 512U;
- }
- else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
- {
- /* Byte 7 */
- pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
-
- hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
- hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
- hsd->SdCard.BlockSize = 512U;
- hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
- }
- else
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
-
- pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
-
- pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
-
- pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
-
- pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
-
- pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
-
- pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
-
- pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
-
- pCSD->Reserved3 = 0;
-
- pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
-
- pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
-
- pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
-
- pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
-
- pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
-
- pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
-
- pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
-
- pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
-
- pCSD->Reserved4 = 1;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the SD status info.
- * @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
- * will contain the SD card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus)
-{
- uint32_t sd_status[16];
- uint32_t errorstate;
-
- errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
-
- pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
-
- pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
-
- pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
- ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
-
- pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
-
- pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
-
- pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
-
- pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
-
- pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
-
- pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
-
- pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
- pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
- pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the SD card info.
- * @param hsd: Pointer to SD handle
- * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
- * will contain the SD card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
-{
- pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
- pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
- pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
- pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
- pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
- pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
- pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
- pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables wide bus operation for the requested card if supported by
- * card.
- * @param hsd: Pointer to SD handle
- * @param WideMode: Specifies the SD card wide bus mode
- * This parameter can be one of the following values:
- * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
- * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
- * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
- SDMMC_InitTypeDef Init;
- uint32_t errorstate;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_BUS_WIDE(WideMode));
-
- /* Change State */
- hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- if(WideMode == SDMMC_BUS_WIDE_8B)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
- else if(WideMode == SDMMC_BUS_WIDE_4B)
- {
- errorstate = SD_WideBus_Enable(hsd);
-
- hsd->ErrorCode |= errorstate;
- }
- else if(WideMode == SDMMC_BUS_WIDE_1B)
- {
- errorstate = SD_WideBus_Disable(hsd);
-
- hsd->ErrorCode |= errorstate;
- }
- else
- {
- /* WideMode is not a valid argument*/
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- }
- }
- else
- {
- /* MMC Card does not support this feature */
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hsd->Init.ClockEdge;
- Init.ClockPowerSave = hsd->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-
- /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
- if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
- {
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
- {
- /* UltraHigh speed SD card,user Clock div */
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
- {
- /* High speed SD card, Max Frequency = 50Mhz */
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
- }
- else
- {
- /* No High speed SD card, Max Frequency = 25Mhz */
- Init.ClockDiv = SDMMC_NSpeed_CLK_DIV;
- }
-
- (void)SDMMC_Init(hsd->Instance, Init);
- }
-
- /* Change State */
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the current sd card data state.
- * @param hsd: pointer to SD handle
- * @retval Card state
- */
-HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
-{
- uint32_t cardstate;
- uint32_t errorstate;
- uint32_t resp1 = 0;
-
- errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- }
-
- cardstate = ((resp1 >> 9U) & 0x0FU);
-
- return (HAL_SD_CardStateTypedef)cardstate;
-}
-
-/**
- * @brief Abort the current transfer and disable the SD.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information for SD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStateTypedef CardState;
-
- /* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- /* If IDMA Context, disable Internal DMA */
- hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
- hsd->State = HAL_SD_STATE_READY;
-
- /* Initialize the SD operation */
- hsd->Context = SD_CONTEXT_NONE;
-
- CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
- }
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information for SD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStateTypedef CardState;
-
- /* Disable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
-
- /* If IDMA Context, disable Internal DMA */
- hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- CardState = HAL_SD_GetCardState(hsd);
- hsd->State = HAL_SD_STATE_READY;
-
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
- }
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
- {
- HAL_SD_AbortCallback(hsd);
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
- * @{
- */
-
-
-/**
- * @brief Initializes the sd card.
- * @param hsd: Pointer to SD handle
- * @retval SD Card error state
- */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardCSDTypedef CSD;
- uint32_t errorstate;
- uint16_t sd_rca = 1;
-
- /* Check the power State */
- if(SDMMC_GetPowerState(hsd->Instance) == 0U)
- {
- /* Power off */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD2 ALL_SEND_CID */
- errorstate = SDMMC_CmdSendCID(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card identification number data */
- hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
- hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
- hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
- hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
- }
- }
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD3 SET_REL_ADDR with argument 0 */
- /* SD Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- }
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Get the SD card RCA */
- hsd->SdCard.RelCardAdd = sd_rca;
-
- /* Send CMD9 SEND_CSD with argument as card's RCA */
- errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card Specific Data */
- hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
- hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
- hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
- hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
- }
- }
-
- /* Get the Card Class */
- hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);
-
- /* Get CSD parameters */
- if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* All cards are initialized */
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Enquires cards about their operating voltage and configures clock
- * controls and stores SD information that will be needed in future
- * in the SD handle.
- * @param hsd: Pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
-{
- __IO uint32_t count = 0;
- uint32_t response = 0, validvoltage = 0;
- uint32_t errorstate;
-#if (USE_SD_TRANSCEIVER != 0U)
- uint32_t tickstart = HAL_GetTick();
-#endif /* USE_SD_TRANSCEIVER */
-
- /* CMD0: GO_IDLE_STATE */
- errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
- errorstate = SDMMC_CmdOperCond(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->SdCard.CardVersion = CARD_V1_X;
- }
- else
- {
- hsd->SdCard.CardVersion = CARD_V2_X;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
- else
- {
- /* SD CARD */
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
- {
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
-
- count++;
- }
-
- if(count >= SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
- {
- hsd->SdCard.CardType = CARD_SDHC_SDXC;
-#if (USE_SD_TRANSCEIVER != 0U)
- if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
- {
- hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
-
- /* Start switching procedue */
- hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
-
- /* Send CMD11 to switch 1.8V mode */
- errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Check to CKSTOP */
- while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
- {
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- /* Clear CKSTOP Flag */
- hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
-
- /* Check to BusyD0 */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
- {
- /* Error when activate Voltage Switch in SDMMC IP */
- return SDMMC_ERROR_UNSUPPORTED_FEATURE;
- }
- else
- {
- /* Enable Transceiver Switch PIN */
- HAL_SD_DriveTransceiver_1_8V_Callback(SET);
-
- /* Switch ready */
- hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
-
- /* Check VSWEND Flag */
- while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
- {
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- /* Clear VSWEND Flag */
- hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
-
- /* Check BusyD0 status */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
- {
- /* Error when enabling 1.8V mode */
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
- /* Switch to 1.8V OK */
-
- /* Disable VSWITCH FLAG from SDMMC IP */
- hsd->Instance->POWER = 0x13U;
-
- /* Clean Status flags */
- hsd->Instance->ICR = 0xFFFFFFFFU;
- }
-
- hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
- }
-#endif /* USE_SD_TRANSCEIVER */
- }
- }
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Turns the SDMMC output signals off.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-static void SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
- /* Set Power State to OFF */
- (void)SDMMC_PowerState_OFF(hsd->Instance);
-}
-
-/**
- * @brief Send Status info command.
- * @param hsd: pointer to SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
- * SD Status register)
- * @retval error state
- */
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count;
- uint32_t *pData = pSDstatus;
-
- /* Check SD response */
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Set block size for card if it is not equal to current block size for card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Send CMD55 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 64;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
- errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Get status data */
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
- {
- for(count = 0U; count < 8U; count++)
- {
- *pData = SDMMC_ReadFIFO(hsd->Instance);
- pData++;
- }
- }
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- return HAL_SD_ERROR_DATA_TIMEOUT;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- return HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
- {
- return HAL_SD_ERROR_RX_OVERRUN;
- }
- else
- {
- /* Nothing to do */
- }
-
- while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
- {
- *pData = SDMMC_ReadFIFO(hsd->Instance);
- pData++;
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- /* Clear all the static status flags*/
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Returns the current card's status.
- * @param hsd: Pointer to SD handle
- * @param pCardStatus: pointer to the buffer that will contain the SD card
- * status (Card Status register)
- * @retval error state
- */
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
- uint32_t errorstate;
-
- if(pCardStatus == NULL)
- {
- return HAL_SD_ERROR_PARAM;
- }
-
- /* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get SD card status */
- *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Enables the SDMMC wide bus mode.
- * @param hsd: pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
- uint32_t scr[2] = {0, 0};
- uint32_t errorstate;
-
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Get SCR Register */
- errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* If requested card supports wide bus operation */
- if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
- {
- /* Send CMD55 APP_CMD with argument as card's RCA.*/
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- return HAL_SD_ERROR_NONE;
- }
- else
- {
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-}
-
-/**
- * @brief Disables the SDMMC wide bus mode.
- * @param hsd: Pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
- uint32_t scr[2] = {0, 0};
- uint32_t errorstate;
-
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Get SCR Register */
- errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* If requested card supports 1 bit mode operation */
- if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
- {
- /* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- return HAL_SD_ERROR_NONE;
- }
- else
- {
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-}
-
-
-/**
- * @brief Finds the SD card SCR register value.
- * @param hsd: Pointer to SD handle
- * @param pSCR: pointer to the buffer that will contain the SCR value
- * @retval error state
- */
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t tickstart = HAL_GetTick();
- uint32_t index = 0;
- uint32_t tempscr[2] = {0, 0};
- uint32_t *scr = pSCR;
-
- /* Set Block Size To 8 Bytes */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 8;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_ENABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
- errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
- {
- if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
- {
- tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
- tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
- index++;
- }
-
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
- return HAL_SD_ERROR_DATA_TIMEOUT;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
- return HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
- return HAL_SD_ERROR_RX_OVERRUN;
- }
- else
- {
- /* No error flag set */
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
- ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
- scr++;
- *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
- ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
-
- }
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Wrap up reading in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
- * @retval None
- */
-static void SD_Read_IT(SD_HandleTypeDef *hsd)
-{
- uint32_t count, data;
- uint8_t* tmp;
-
- tmp = hsd->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = SDMMC_ReadFIFO(hsd->Instance);
- *tmp = (uint8_t)(data & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 8U) & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 16U) & 0xFFU);
- tmp++;
- *tmp = (uint8_t)((data >> 24U) & 0xFFU);
- tmp++;
- }
-
- hsd->pRxBuffPtr = tmp;
-}
-
-/**
- * @brief Wrap up writing in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
- * @retval None
- */
-static void SD_Write_IT(SD_HandleTypeDef *hsd)
-{
- uint32_t count, data;
- uint8_t* tmp;
-
- tmp = hsd->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- data = (uint32_t)(*tmp);
- tmp++;
- data |= ((uint32_t)(*tmp) << 8U);
- tmp++;
- data |= ((uint32_t)(*tmp) << 16U);
- tmp++;
- data |= ((uint32_t)(*tmp) << 24U);
- tmp++;
- (void)SDMMC_WriteFIFO(hsd->Instance, &data);
- }
-
- hsd->pTxBuffPtr = tmp;
-}
-
-uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- SDMMC_DataInitTypeDef sdmmc_datainitstructure;
- uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
- uint32_t Timeout = HAL_GetTick();
-
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
- {
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
- {
- /* Initialize the Data control register */
- hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
-
- if (errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
- sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
- sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
-
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
-
-
- errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
- {
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
- {
- for (count = 0U; count < 8U; count++)
- {
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
- }
- loop ++;
- }
-
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
- {
- hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
- errorstate = 0;
-
- return errorstate;
- }
- else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
- errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
-
- return errorstate;
- }
- else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
- errorstate = SDMMC_ERROR_RX_OVERRUN;
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- /* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
- {
- errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
- }
-
- }
-
- return errorstate;
-}
-
-#if (USE_SD_TRANSCEIVER != 0U)
-/**
- * @brief Switches the SD card to High Speed mode.
- * This API must be used after "Transfer State"
- * @note This operation should be followed by the configuration
- * of PLL to have SDMMCCK clock between 50 and 120 MHz
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- SDMMC_DataInitTypeDef sdmmc_datainitstructure;
- uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
- uint32_t Timeout = HAL_GetTick();
-
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
- {
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
- {
- /* Initialize the Data control register */
- hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
-
- if (errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
- sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
- sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
-
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
-
- errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
- {
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
- {
- for (count = 0U; count < 8U; count++)
- {
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
- }
- loop ++;
- }
-
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
- {
- hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
-
- errorstate = 0;
-
- return errorstate;
- }
- else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
-
- errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
-
- return errorstate;
- }
- else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
-
- errorstate = SDMMC_ERROR_RX_OVERRUN;
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
- /* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
- {
- errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
- }
- else
- {
- HAL_SD_DriveTransceiver_1_8V_Callback(SET);
-#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
- /* Enable DelayBlock IP */
- /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
- MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
- if (DelayBlock_Enable(DLYB_SDMMC1) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
-#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
- }
- }
-
- return errorstate;
-}
-#endif /* USE_SD_TRANSCEIVER */
-
-/**
- * @brief Read DMA Buffer 0 Transfer completed callbacks
- * @param hsd: SD handle
- * @retval None
- */
-__weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Read DMA Buffer 1 Transfer completed callbacks
- * @param hsd: SD handle
- * @retval None
- */
-__weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Write DMA Buffer 0 Transfer completed callbacks
- * @param hsd: SD handle
- * @retval None
- */
-__weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Write DMA Buffer 1 Transfer completed callbacks
- * @param hsd: SD handle
- * @retval None
- */
-__weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
deleted file mode 100644
index a82e8fc..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sd_ex.c
- * @author MCD Application Team
- * @brief SD card Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (SD) peripheral:
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SD Extension HAL driver can be used as follows:
- (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
-
- (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SDEx SDEx
- * @brief SD Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup SDEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
-@verbatim
- ==============================================================================
- ##### Multibuffer functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to configure the multibuffer mode and start read and write
- multibuffer mode for SD HAL driver.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
- * @param hsd: SD handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
- * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
-{
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
- hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
- hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
- * @param hsd: SD handle
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Total number of blocks to read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
- uint32_t add = BlockAdd;
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- DmaBase0_reg = hsd->Instance->IDMABASE0;
- DmaBase1_reg = hsd->Instance->IDMABASE1;
- if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
- {
- hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
- /* Clear old Flags*/
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
-
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
-
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
-
- /* Read Blocks in DMA mode */
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
- * @param hsd: SD handle
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Total number of blocks to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDMMC_DataInitTypeDef config;
- uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
- uint32_t add = BlockAdd;
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- DmaBase0_reg = hsd->Instance->IDMABASE0;
- DmaBase1_reg = hsd->Instance->IDMABASE1;
- if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
- {
- hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- add *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hsd->Instance, &config);
-
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
-
- hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
-
- /* Write Blocks in DMA mode */
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Change the DMA Buffer0 or Buffer1 address on the fly.
- * @param hsd: pointer to a SD_HandleTypeDef structure.
- * @param Buffer: the buffer to be changed, This parameter can be one of
- * the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
- * @param pDataBuffer: The new address
- * @note The BUFFER0 address can be changed only when the current transfer use
- * BUFFER1 and the BUFFER1 address can be changed only when the current
- * transfer use BUFFER0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
-{
- if(Buffer == SD_DMA_BUFFER0)
- {
- /* change the buffer0 address */
- hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
- }
- else
- {
- /* change the memory1 address */
- hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c
deleted file mode 100644
index d43356c..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c
+++ /dev/null
@@ -1,860 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sdram.c
- * @author MCD Application Team
- * @brief SDRAM HAL module driver.
- * This file provides a generic firmware to drive SDRAM memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control SDRAM memories. It uses the FMC layer functions to interface
- with SDRAM devices.
- The following sequence should be followed to configure the FMC to interface
- with SDRAM memories:
-
- (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
- SDRAM_HandleTypeDef hdsram
-
- (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
- values of the structure member.
-
- (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
- base register instance for NOR or SDRAM device
-
- (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
- FMC_SDRAM_TimingTypeDef Timing;
- and fill its fields with the allowed values of the structure member.
-
- (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
- performs the following sequence:
-
- (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
- (##) Control register configuration using the FMC SDRAM interface function
- FMC_SDRAM_Init()
- (##) Timing register configuration using the FMC SDRAM interface function
- FMC_SDRAM_Timing_Init()
- (##) Program the SDRAM external device by applying its initialization sequence
- according to the device plugged in your hardware. This step is mandatory
- for accessing the SDRAM device.
-
- (#) At this stage you can perform read/write accesses from/to the memory connected
- to the SDRAM Bank. You can perform either polling or DMA transfer using the
- following APIs:
- (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
- (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
-
- (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
- HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
- the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
- device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
- structure.
-
- (#) You can continuously monitor the SDRAM device HAL state by calling the function
- HAL_SDRAM_GetState()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SDRAM SDRAM
- * @brief SDRAM driver modules
- * @{
- */
-#ifdef HAL_SDRAM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
- * @{
- */
-
-/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### SDRAM Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the SDRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Performs the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param Timing: Pointer to SDRAM control timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
-{
- /* Check the SDRAM handle parameter */
- if(hsdram == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hsdram->State == HAL_SDRAM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsdram->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_SDRAM_MspInit(hsdram);
- }
-
- /* Initialize the SDRAM controller state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Initialize SDRAM control Interface */
- FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
-
- /* Initialize SDRAM timing Interface */
- FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
-
- /* Enable FMC IP */
- __FMC_ENABLE();
-
- /* Update the SDRAM controller state */
- hsdram->State = HAL_SDRAM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
-{
- /* Initialize the low level hardware (MSP) */
- HAL_SDRAM_MspDeInit(hsdram);
-
- /* Configure the SDRAM registers with their reset values */
- FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
-
- /* Reset the SDRAM controller state */
- hsdram->State = HAL_SDRAM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief SDRAM MSP Init.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval None
- */
-__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdram);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_SDRAM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SDRAM MSP DeInit.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval None
- */
-__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdram);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_SDRAM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function handles SDRAM refresh error interrupt request.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval HAL status
-*/
-void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
-{
- /* Check SDRAM interrupt Rising edge flag */
- if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
- {
- /* SDRAM refresh error interrupt callback */
- HAL_SDRAM_RefreshErrorCallback(hsdram);
-
- /* Clear SDRAM refresh error interrupt pending bit */
- __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
- }
-}
-
-/**
- * @brief SDRAM Refresh error callback.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval None
- */
-__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdram);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-__weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdma);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete error callback.
- * @param hmdma: DMA handle
- * @retval None
- */
-__weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdma);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### SDRAM Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the SDRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads 8-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
- {
- return HAL_ERROR;
- }
-
- /* Read data from source */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
- pDstBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Writes 8-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
- uint32_t tmp = 0;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- tmp = hsdram->State;
-
- if(tmp == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
- {
- return HAL_ERROR;
- }
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
- pSrcBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Reads 16-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
- {
- return HAL_ERROR;
- }
-
- /* Read data from source */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
- pDstBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 16-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
- uint32_t tmp = 0;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- tmp = hsdram->State;
-
- if(tmp == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
- {
- return HAL_ERROR;
- }
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
- pSrcBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 32-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
- {
- return HAL_ERROR;
- }
-
- /* Read data from source */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
- pDstBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 32-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
- uint32_t tmp = 0;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- tmp = hsdram->State;
-
- if(tmp == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
- {
- return HAL_ERROR;
- }
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
- pSrcBuffer++;
- pSdramAddress++;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a Words data from the SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- uint32_t tmp = 0;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- tmp = hsdram->State;
-
- if(tmp == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
- {
- return HAL_ERROR;
- }
-
- /* Configure DMA user callbacks */
- hsdram->hmdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
- hsdram->hmdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Stream */
- HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4), 1);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- uint32_t tmp = 0;
-
- /* Process Locked */
- __HAL_LOCK(hsdram);
-
- /* Check the SDRAM controller state */
- tmp = hsdram->State;
-
- if(tmp == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
- {
- return HAL_ERROR;
- }
-
- /* Configure DMA user callbacks */
- hsdram->hmdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
- hsdram->hmdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Stream */
- HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4), 1);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsdram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### SDRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the SDRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
-{
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Enable write protection */
- FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
-{
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Disable write protection */
- FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Sends Command to the SDRAM bank.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param Command: SDRAM command structure
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
-{
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Send SDRAM command */
- FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
-
- /* Update the SDRAM controller state state */
- if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
- {
- hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
- }
- else
- {
- hsdram->State = HAL_SDRAM_STATE_READY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Programs the SDRAM Memory Refresh rate.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param RefreshRate: The SDRAM refresh rate value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
-{
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Program the refresh rate */
- FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @param AutoRefreshNumber: The SDRAM auto Refresh number
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
-{
- /* Check the SDRAM controller state */
- if(hsdram->State == HAL_SDRAM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_BUSY;
-
- /* Set the Auto-Refresh number */
- FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
-
- /* Update the SDRAM state */
- hsdram->State = HAL_SDRAM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the SDRAM memory current mode.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval The SDRAM memory mode.
- */
-uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
-{
- /* Return the SDRAM memory current mode */
- return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDRAM_Exported_Functions_Group4 State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### SDRAM State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the SDRAM controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the SDRAM state.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
- * the configuration information for SDRAM module.
- * @retval HAL state
- */
-HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
-{
- return hsdram->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c
deleted file mode 100644
index 43a1bb1..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c
+++ /dev/null
@@ -1,2341 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smartcard.c
- * @author MCD Application Team
- * @brief SMARTCARD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the SMARTCARD peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SMARTCARD HAL driver can be used as follows:
-
- (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
- (#) Associate a USART to the SMARTCARD handle hsmartcard.
- (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
- (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
- and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
- and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
- the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
- error enabling or disabling in the hsmartcard handle Init structure.
-
- (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
- in the hsmartcard handle AdvancedInit structure.
-
- (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMARTCARD_MspInit() API.
- [..]
- (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
- [..]
- [..] Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
- *** SMARTCARD HAL driver macros list ***
- ========================================
- [..]
- Below the list of most used macros in SMARTCARD HAL driver.
-
- (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
-
- [..]
- (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMARTCARD SMARTCARD
- * @brief HAL SMARTCARD module driver
- * @{
- */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
- USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT|\
- USART_CR3_TXFTCFG|USART_CR3_RXFTCFG)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
- * @{
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx
- associated to the SmartCard.
- (+) These parameters can be configured:
- (++) Baud Rate
- (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
- (++) Receiver/transmitter modes
- (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
- (++) Prescaler value
- (++) Guard bit time
- (++) NACK enabling or disabling on transmission error
-
- (+) The following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) Time out enabling (and if activated, timeout value)
- (++) Block length
- (++) Auto-retry counter
- [..]
- The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
- (details for the procedures are available in reference manual).
-
-@endverbatim
-
- The USART frame format is given in the following table:
-
- Table 1. USART frame format.
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 01 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
-
-
- * @{
- */
-
-/**
- * @brief Initialize the SMARTCARD mode according to the specified
- * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART associated to the SMARTCARD handle */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsmartcard->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_SMARTCARD_MspInit(hsmartcard);
- }
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Disable the Peripheral to set smartcard mode */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* In SmartCard mode, the following bits must be kept cleared:
- - LINEN in the USART_CR2 register,
- - HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* set the USART in SMARTCARD mode */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
-
- /* Set the SMARTCARD Communication parameters */
- if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* Set the SMARTCARD transmission completion indication */
- SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
-
- if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
- {
- SMARTCARD_AdvFeatureConfig(hsmartcard);
- }
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
- return (SMARTCARD_CheckIdleState(hsmartcard));
-}
-
-/**
- * @brief DeInitialize the SMARTCARD peripheral.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the SMARTCARD handle */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Disable the Peripheral */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- WRITE_REG(hsmartcard->Instance->CR1, 0x0);
- WRITE_REG(hsmartcard->Instance->CR2, 0x0);
- WRITE_REG(hsmartcard->Instance->CR3, 0x0);
- WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
- WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
-
- /* DeInit the low level hardware */
- HAL_SMARTCARD_MspDeInit(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SMARTCARD MSP.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SMARTCARD MSP.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
- [..]
- Smartcard is a single wire half duplex communication protocol.
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard. The USART should be configured as:
- (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
- [..]
- (+) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
- or DMA, the relevant API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
- error is detected.
-
- (+) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
-
- (+) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
-
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
-
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_SMARTCARD_Abort()
- (+) HAL_SMARTCARD_AbortTransmit()
- (+) HAL_SMARTCARD_AbortReceive()
- (+) HAL_SMARTCARD_Abort_IT()
- (+) HAL_SMARTCARD_AbortTransmit_IT()
- (+) HAL_SMARTCARD_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_SMARTCARD_AbortCpltCallback()
- (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- while(hsmartcard->TxXferCount > 0)
- {
- hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
- }
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- {
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- }
-
- /* At end of Tx process, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(hsmartcard->RxXferCount > 0)
- {
- hsmartcard->RxXferCount--;
-
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
- }
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
- */
- if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the SMARTCARD Parity Error interupt and RX FIFO Threshold interrupt
- (if FIFO mode is enabled) or Data Register Not Empty interrupt
- (if FIFO mode is disabled).
- */
- if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
- /* Set the SMARTCARD error callback */
- hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the SMARTCARD transmit DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the UART Error Interrupt: (Frame error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
- * the received data contain the parity bit (MSB position).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
- /* Set the SMARTCARD DMA error callback */
- hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmatx);
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE, TXFTIE and TCIE interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t abortcplt = 1;
-
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
- }
- else
- {
- hsmartcard->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
- }
- else
- {
- hsmartcard->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* SMARTCARD Tx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- hsmartcard->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0;
- }
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* SMARTCARD Rx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- hsmartcard->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1;
- }
- else
- {
- abortcplt = 0;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1)
- {
- /* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE, TXFTIE and TCIE interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
- hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
-
- /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
- hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMARTCARD interrupt requests.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
- uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
- if (errorflags == RESET)
- {
- /* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsmartcard);
- /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(hsmartcard->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
- {
- /* SMARTCARD parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- }
-
- /* SMARTCARD frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
- }
-
- /* SMARTCARD noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
- }
-
- /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
- }
-
- /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
- }
-
- /* Call SMARTCARD Error Call back function if need be --------------------------*/
- if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
- {
- /* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsmartcard);
- }
-
- /* If Error is to be considered as blocking :
- - Receiver Timeout error in Reception
- - Overrun error in Reception
- - any error occurs in DMA mode reception
- */
- if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
- || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- SMARTCARD_EndRxTransfer(hsmartcard);
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
- hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- /* other error type to be considered as blocking :
- - Frame error in Transmission
- */
- else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
- {
- /* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
- SMARTCARD_EndTxTransfer(hsmartcard);
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
- hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
- if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
- {
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- __HAL_UNLOCK(hsmartcard);
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
- /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
- * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
- return;
- }
-
- /* SMARTCARD in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- SMARTCARD_Transmit_IT(hsmartcard);
- return;
- }
-
- /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
- {
- SMARTCARD_EndTransmit_IT(hsmartcard);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD error callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Receive Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of SmartCard
- handle and also return Peripheral Errors occurred during communication process
- (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
- of the SMARTCARD peripheral.
- (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
- communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SMARTCARD handle state.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval SMARTCARD handle state
- */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Return SMARTCARD handle state */
- uint32_t temp1= 0x00, temp2 = 0x00;
- temp1 = hsmartcard->gState;
- temp2 = hsmartcard->RxState;
-
- return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the SMARTCARD handle error code.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval SMARTCARD handle Error Code
-*/
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- return hsmartcard->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @{
- */
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t tmpreg = 0x0U;
- SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
- PLL2_ClocksTypeDef pll2_clocks;
- PLL3_ClocksTypeDef pll3_clocks;
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
- assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
- assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
- assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
- assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
- assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
- assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
- assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
- assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
- assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
- assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
- assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
- assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
- assert_param(IS_SMARTCARD_FIFO_MODE_STATE(hsmartcard->Init.FIFOMode));
- if (hsmartcard->Init.FIFOMode == UART_FIFOMODE_ENABLE)
- {
- assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(hsmartcard->Init.TXFIFOThreshold));
- assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(hsmartcard->Init.RXFIFOThreshold));
- }
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
- * Oversampling is forced to 16 (OVER8 = 0).
- * Configure the Parity and Mode:
- * set PS bit according to hsmartcard->Init.Parity value
- * set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
- tmpreg |= (uint32_t) hsmartcard->Init.FIFOMode;
- MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = hsmartcard->Init.StopBits;
- /* Synchronous mode is activated by default */
- tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
- tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - one-bit sampling method versus three samples' majority rule
- * according to hsmartcard->Init.OneBitSampling
- * - NACK transmission in case of parity error according
- * to hsmartcard->Init.NACKEnable
- * - autoretry counter according to hsmartcard->Init.AutoRetryCount
- * - set TXFTCFG bit according to hsmartcard->Init.TXFIFOThreshold value
- * - set RXFTCFG bit according to hsmartcard->Init.RXFIFOThreshold value */
- tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
- tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
- tmpreg |= ((uint32_t)hsmartcard->Init.TXFIFOThreshold | (uint32_t)hsmartcard->Init.RXFIFOThreshold );
- MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
-
- /*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
- if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
- {
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
- }
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
- switch (clocksource)
- {
- case SMARTCARD_CLOCKSOURCE_D2PCLK1:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_D2PCLK2:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_PLL2Q:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- hsmartcard->Instance->BRR = (uint16_t)((pll2_clocks.PLL2_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_PLL3Q:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- hsmartcard->Instance->BRR = (uint16_t)((pll3_clocks.PLL3_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- hsmartcard->Instance->BRR = (uint16_t)(((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)) + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- }
- else
- {
- hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- }
- break;
- case SMARTCARD_CLOCKSOURCE_CSI:
- hsmartcard->Instance->BRR = (uint16_t)((CSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- return ret;
-}
-
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral advanced features.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
- MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
- }
-
-}
-
-/**
- * @brief Check the SMARTCARD Idle State.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t tickstart = 0;
-
- /* Initialize the SMARTCARD ErrorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the SMARTCARD states */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMARTCARD Communication Timeout.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param Flag Specifies the SMARTCARD flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Tx process, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
- * @brief DMA SMARTCARD transmit process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-}
-
-/**
- * @brief DMA SMARTCARD receive process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD communication error callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
-
- /* Stop SMARTCARD DMA Tx request if ongoing */
- if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
- {
- hsmartcard->TxXferCount = 0;
- SMARTCARD_EndTxTransfer(hsmartcard);
- }
-
- /* Stop SMARTCARD DMA Rx request if ongoing */
- if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
- {
- hsmartcard->RxXferCount = 0;
- SMARTCARD_EndRxTransfer(hsmartcard);
- }
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0;
- hsmartcard->TxXferCount = 0;
-
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmarx != NULL)
- {
- if(hsmartcard->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-}
-
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmatx != NULL)
- {
- if(hsmartcard->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-}
-
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
-
- hsmartcard->TxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->RxXferCount = 0;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Tx process is ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- if(hsmartcard->TxXferCount == 0)
- {
- /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-
- return HAL_OK;
- }
- else
- {
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
- hsmartcard->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- {
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- }
-
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Rx process is ongoing */
- if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
-
- if(--hsmartcard->RxXferCount == 0)
- {
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Check if a transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c
deleted file mode 100644
index b5ec810..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smartcard_ex.c
- * @author MCD Application Team
- * @brief SMARTCARD HAL module driver.
- * This file provides extended firmware functions to manage the following
- * functionalities of the SmartCard.
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- =============================================================================
- ##### SMARTCARD peripheral extended features #####
- =============================================================================
- [..]
- The Extended SMARTCARD HAL driver can be used as follows:
-
- (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
- then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
- auto-retry counter,...) in the hsmartcard AdvancedInit structure.
-
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMARTCARDEx SMARTCARDEx
- * @brief SMARTCARD Extended HAL module driver
- * @{
- */
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
- * @{
- */
-
-/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the SMARTCARD.
- (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
- (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
- (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
- (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Update on the fly the SMARTCARD block length in RTOR register.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param BlockLength: SMARTCARD block length (8-bit long at most)
- * @retval None
- */
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
-{
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
-}
-
-/**
- * @brief Update on the fly the receiver timeout value in RTOR register.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
- * value must be less or equal to 0x00FFFFFF.
- * @retval None
- */
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
-{
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
-}
-
-/**
- * @brief Enable the SMARTCARD receiver timeout feature.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Set the USART RTOEN bit */
- SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the SMARTCARD receiver timeout feature.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Clear the USART RTOEN bit */
- CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c
deleted file mode 100644
index dadb37f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c
+++ /dev/null
@@ -1,2037 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_smbus.c
- * @author MCD Application Team
- * @brief SMBUS HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the System Management Bus (SMBus) peripheral,
- * based on I2C principles of operation :
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SMBUS HAL driver can be used as follows:
-
- (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
- SMBUS_HandleTypeDef hsmbus;
-
- (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
- (++) Enable the SMBUSx interface clock
- (++) SMBUS pins configuration
- (+++) Enable the clock for the SMBUS GPIOs
- (+++) Configure SMBUS pins as alternate function open-drain
- (++) NVIC configuration if you need to use interrupt process
- (+++) Configure the SMBUSx interrupt priority
- (+++) Enable the NVIC SMBUS IRQ Channel
-
- (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
- Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
- Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
-
- (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
-
- (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
-
- (#) For SMBUS IO operations, only one mode of operations is available within this driver
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
- (++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
- (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
- (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Error Code using function HAL_SMBUS_GetError()
-
- *** SMBUS HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in SMBUS HAL driver.
-
- (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
- (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
- (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
- (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
-
- [..]
- (@) You can refer to the SMBUS HAL driver header file for more useful macros
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMBUS SMBUS
- * @brief SMBUS HAL module driver
- * @{
- */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Define SMBUS Private Constants
- * @{
- */
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance));
- assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
- assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
- assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
- assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
- assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
- assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
- assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
- assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
- assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
- assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
-
- if(hsmbus->State == HAL_SMBUS_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsmbus->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_SMBUS_MspInit(hsmbus);
- }
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
- /* Configure SMBUSx: Frequency range */
- hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
- /* Configure SMBUSx: Bus Timeout */
- hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
- hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
- hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
-
- /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
- /* Configure SMBUSx: Own Address1 and ack own address1 mode */
- hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- if(hsmbus->Init.OwnAddress1 != 0U)
- {
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
- }
- else /* SMBUS_ADDRESSINGMODE_10BIT */
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
- }
- }
-
- /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
- /* Configure SMBUSx: Addressing Master mode */
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
- {
- hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
- }
- /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
- /* AUTOEND and NACK bit will be manage during Transfer process */
- hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
- /* Configure SMBUSx: Dual mode and Own Address2 */
- hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
-
- /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
- /* Configure SMBUSx: Generalcall and NoStretch mode */
- hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
-
- /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
- {
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
- }
-
- /* Enable the selected SMBUS peripheral */
- __HAL_SMBUS_ENABLE(hsmbus);
-
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the SMBUS peripheral.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Check the SMBUS handle allocation */
- if(hsmbus == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the SMBUS Peripheral Clock */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_SMBUS_MspDeInit(hsmbus);
-
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
- hsmbus->State = HAL_SMBUS_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SMBUS MSP.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SMBUS MSP.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMBUS data
- transfers.
-
- (#) Blocking mode function to check if device is ready for usage is :
- (++) HAL_SMBUS_IsDeviceReady()
-
- (#) There is only one mode of transfer:
- (++) Non-Blocking mode : The communication is performed using Interrupts.
- These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated SMBUS IRQ when using Interrupt mode.
-
- (#) Non-Blocking mode functions with Interrupt are :
- (++) HAL_SMBUS_Master_Transmit_IT()
- (++) HAL_SMBUS_Master_Receive_IT()
- (++) HAL_SMBUS_Slave_Transmit_IT()
- (++) HAL_SMBUS_Slave_Receive_IT()
- (++) HAL_SMBUS_EnableListen_IT()
- (++) HAL_SMBUS_DisableListen_IT()
- (++) HAL_SMBUS_EnableAlert_IT()
- (++) HAL_SMBUS_DisableAlert_IT()
-
- (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (++) HAL_SMBUS_MasterTxCpltCallback()
- (++) HAL_SMBUS_MasterRxCpltCallback()
- (++) HAL_SMBUS_SlaveTxCpltCallback()
- (++) HAL_SMBUS_SlaveRxCpltCallback()
- (++) HAL_SMBUS_AddrCallback()
- (++) HAL_SMBUS_ListenCpltCallback()
- (++) HAL_SMBUS_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* In case of Quick command, remove autoend mode */
- /* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
- {
- hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
- }
-
- if(Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
- {
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
- }
- else
- {
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
- {
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- /* Else transfer direction change, so generate Restart with new transfer direction */
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
- }
-
- /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress: Target device address
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* In case of Quick command, remove autoend mode */
- /* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
- {
- hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
- }
-
- if(Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
- {
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
- }
- else
- {
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
- {
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- /* Else transfer direction change, so generate Restart with new transfer direction */
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master/host SMBUS process communication with Interrupt.
- * @note This abort can be called only if state is ready
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress: Target device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
-{
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- /* Keep the same state as previous */
- /* to perform as well the call of the corresponding end of transfer callback */
- if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
- }
- else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
- /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
- }
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set SBC bit to manage Acknowledge at each bit */
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
- /* Enable Address Acknowledge */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- if(Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
- {
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
- }
- else
- {
- /* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
-
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set SBC bit to manage Acknowledge at each bit */
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
- /* Enable Address Acknowledge */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferSize = Size;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Set NBYTE to receive */
- /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
- /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
- /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
- /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
- {
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- else
- {
- SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
- }
-
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-
- /* Enable the Address Match interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Disable Address listen mode only if a transfer is not ongoing */
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Disable the Address Match interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the SMBUS alert mode with Interrupt.
- * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUSx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Enable SMBus alert */
- hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
-
- /* Enable Alert Interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
- return HAL_OK;
-}
-/**
- * @brief Disable the SMBUS alert mode with Interrupt.
- * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUSx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Enable SMBus alert */
- hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
-
- /* Disable Alert Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
- return HAL_OK;
-}
-
-/**
- * @brief Check if target device is ready for communication.
- * @note This function is used with Memory devices
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress: Target device address
- * @param Trials: Number of trials
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- __IO uint32_t SMBUS_Trials = 0U;
-
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- do
- {
- /* Generate Start */
- hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set or a NACK flag is set*/
- tickstart = HAL_GetTick();
- while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Device is ready */
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check if the NACKF flag has not been set */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
- {
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Device is ready */
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
- }
- else
- {
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Clear STOP Flag, auto generated with autoend*/
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- }
-
- /* Check if the maximum allowed number of trials has been reached */
- if (SMBUS_Trials++ == Trials)
- {
- /* Generate Stop */
- hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- }
- }while(SMBUS_Trials < Trials);
-
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief Handle SMBUS event interrupt request.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
- uint32_t tmpisrvalue = 0U;
-
- /* Use a local variable to store the current ISR flags */
- /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
- tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
-
- /* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
- {
- /* Slave mode selected */
- if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- /* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- SMBUS_Master_ISR(hsmbus);
- }
- }
-
- /* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
- {
- /* Slave mode selected */
- if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- /* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Master_ISR(hsmbus);
- }
- }
-
- /* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
- {
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- }
-}
-
-/**
- * @brief Handle SMBUS error interrupt request.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
- /* SMBUS Bus error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
- }
-
- /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
- }
-
- /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
- }
-
- /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
- /* Clear TIMEOUT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
- }
-
- /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
- }
-
- /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
- /* Clear PEC error flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
- }
-
- /* Call the Error Callback in case of Error detected */
- if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
- {
- /* Do not Reset the HAL state in case of ALERT error */
- if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
- {
- if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
- {
- /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
- /* keep HAL_SMBUS_STATE_LISTEN if set */
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
- }
- }
-
- /* Call the Error callback to prevent upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param TransferDirection: Master request Transfer Direction (Write/Read)
- * @param AddrMatchCode: Address Match Code
- * @retval None
- */
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_AddrCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief SMBUS error callback.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_ErrorCallback() could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SMBUS handle state.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL state
- */
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Return SMBUS handle state */
- return hsmbus->State;
-}
-
-/**
-* @brief Return the SMBUS error code.
-* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
-* @retval SMBUS Error Code
-*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
-{
- return hsmbus->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
- * @{
- */
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
-{
- uint16_t DevAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
- {
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Set corresponding Error Code */
- /* No need to generate STOP, it is automatically done */
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to prevent upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* REenable the selected SMBUS peripheral */
- __HAL_SMBUS_ENABLE(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- /* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
-
- if((hsmbus->XferSize > 0U))
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
- {
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
- {
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
- {
- DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
-
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
- }
- else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- }
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
- {
- if(hsmbus->XferCount == 0U)
- {
- /* Specific use case for Quick command */
- if(hsmbus->pBuffPtr == NULL)
- {
- /* Generate a Stop command */
- hsmbus->Instance->CR2 |= I2C_CR2_STOP;
- }
- /* Call TxCpltCallback() if no stop mode is set */
- else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
- {
- /* No Generate Stop, to permit restart mode */
- /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
-{
- uint8_t TransferDirection = 0U;
- uint16_t SlaveAddrCode = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
- {
- /* Check that SMBUS transfer finished */
- /* if yes, normal use case, a NACK is sent by the HOST when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if(hsmbus->XferCount == 0U)
- {
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the HOST*/
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Set HAL State to "Idle" State, mean to LISTEN state */
- /* So reset Slave Busy state */
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
- /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to prevent upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
- {
- TransferDirection = SMBUS_GET_DIR(hsmbus);
- SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
-
- /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
- /* Other ADDRInterrupt will be treat in next Listen use case */
- __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call Slave Addr callback */
- HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
- }
- else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
- {
- if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- hsmbus->XferSize--;
- hsmbus->XferCount--;
-
- if(hsmbus->XferCount == 1U)
- {
- /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
- /* or only the last Byte of Transfer */
- /* So reset the RELOAD bit mode */
- hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- else if(hsmbus->XferCount == 0U)
- {
- /* Last Byte is received, disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
- /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
- HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
- }
- else
- {
- /* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
-
- /* Ack last Byte Read */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
- }
- }
- else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- {
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
- {
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
- SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
- }
- }
- }
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- /* Check if all Data have already been sent */
- /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hsmbus->XferCount > 0U)
- {
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
- hsmbus->XferCount--;
- hsmbus->XferSize--;
- }
-
- if(hsmbus->XferCount == 0U)
- {
- /* Last Byte is Transmitted */
- /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
- HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
- }
- }
-
- /* Check if STOPF is set */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
- {
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
- {
- /* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
-
- if((hsmbus->XferSize > 0U))
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Disable RX and TX Interrupts */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
- /* Disable ADDR Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- /* Disable Address Acknowledge */
- hsmbus->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear ADDR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
-
- hsmbus->XferOptions = 0U;
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Listen Complete callback, to prevent upper layer of the end of Listen use case */
- HAL_SMBUS_ListenCpltCallback(hsmbus);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-/**
- * @brief Manage the enabling of Interrupts.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
- {
- /* Enable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
- {
- /* Enable ADDR, STOP interrupt */
- tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
- }
-
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
- {
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
- }
-
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
- {
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
- }
-
- /* Enable interrupts only at the end */
- /* to avoid the risk of SMBUS interrupt handle execution before */
- /* all interrupts requested done */
- __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
-}
-/**
- * @brief Manage the disabling of Interrupts.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
- {
- /* Disable TC, STOP, NACK, TXI interrupt */
- tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
-
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
- {
- /* Disable STOPI, NACKI */
- tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- }
- }
-
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
- {
- /* Disable TC, STOP, NACK, RXI interrupt */
- tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
-
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
- {
- /* Disable STOPI, NACKI */
- tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- }
- }
-
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
- {
- /* Enable ADDR, STOP interrupt */
- tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
-
- if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
- }
-
- /* Disable interrupts only at the end */
- /* to avoid a breaking situation like at "t" time */
- /* all disable interrupts request are not done */
- __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
-}
-/**
- * @brief Handle SMBUS Communication Timeout.
- * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param Flag: specifies the SMBUS flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param hsmbus: SMBUS handle.
- * @param DevAddress: specifies the slave address to be programmed.
- * @param Size: specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param Mode: new state of the SMBUS START condition generation.
- * This parameter can be one or a combination of the following values:
- * @arg SMBUS_NO_MODE: No specific mode enabled.
- * @arg SMBUS_RELOAD_MODE: Enable Reload mode.
- * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
- * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
- * @param Request: new state of the SMBUS START condition generation.
- * This parameter can be one of the following values:
- * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
- * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
- * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
- * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
- * @retval None
- */
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
- assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
- assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
-
- /* update CR2 register */
- MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
-}
-
-/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
- * @param hsmbus SMBUS handle.
- * @retval None
- */
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
-{
- /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
- /* it request implicitly to generate a restart condition */
- /* set XferOptions to SMBUS_FIRST_FRAME */
- if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_FRAME;
- }
- /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
- /* it request implicitly to generate a restart condition */
- /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
- else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
- }
- /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
- /* it request implicitly to generate a restart condition */
- /* then generate a stop condition at the end of transfer */
- /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
- }
- /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
- /* it request implicitly to generate a restart condition */
- /* then generate a stop condition at the end of transfer */
- /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
- }
-}
-/**
- * @}
- */
-
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c
deleted file mode 100644
index 5d933cf..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c
+++ /dev/null
@@ -1,1264 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spdifrx.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the SPDIFRX audio interface:
- * + Initialization and Configuration
- * + Data transfers functions
- * + DMA transfers management
- * + Interrupts and flags management
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The SPDIFRX HAL driver can be used as follow:
-
- (#) Declare SPDIFRX_HandleTypeDef handle structure.
- (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
- (##) Enable the SPDIFRX interface clock.
- (##) SPDIFRX pins configuration:
- (+++) Enable the clock for the SPDIFRX GPIOs.
- (+++) Configure these SPDIFRX pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
- (+++) Configure the SPDIFRX interrupt priority.
- (+++) Enable the NVIC SPDIFRX IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
- (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
- (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
- (+++) Configure the DMA Channel.
- (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA CtrlRx/DataRx channel.
-
- (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
- using HAL_SPDIFRX_Init() function.
-
- -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
- __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
- -@- Make sure that ck_spdif clock is configured.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode for reception operation (for debug purpose) ***
- ================================================================
- [..]
- (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
- (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
-
- *** Interrupt mode for reception operation ***
- =========================================
- [..]
- (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
- (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
- (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
- (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
- (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
-
- *** DMA mode for reception operation ***
- ========================================
- [..]
- (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
- (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
- (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
- (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
- (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
- (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
-
- *** SPDIFRX HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in USART HAL driver.
- (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
- (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
- (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
- (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
- (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
- (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
-
- [..]
- (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-#if defined (SPDIFRX)
-
-/** @defgroup SPDIFRX SPDIFRX
- * @brief SPDIFRX HAL module driver
- * @{
- */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPDIFRX_Private_Functions
- * @{
- */
-static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
-static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
-static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
-static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
-/**
- * @}
- */
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
- * @{
- */
-
-/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPDIFRX peripheral:
-
- (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
- the selected configuration:
- (++) Input Selection (IN0, IN1,...)
- (++) Maximum allowed re-tries during synchronization phase
- (++) Wait for activity on SPDIF selected input
- (++) Channel status selection (from channel A or B)
- (++) Data format (LSB, MSB, ...)
- (++) Stereo mode
- (++) User bits masking (PT,C,U,V,...)
-
- (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
- of the selected SPDIFRXx peripheral.
- @endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SPDIFRX according to the specified parameters
- * in the SPDIFRX_InitTypeDef and create the associated handle.
- * @param hspdif: SPDIFRX handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
-{
- uint32_t tmpreg = 0;
-
- /* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the SPDIFRX parameters */
- assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
- assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
- assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
- assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
- assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
- assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
- assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
- assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
- assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
- assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
- assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.SymbolClockGen));
- assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen));
-
- if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hspdif->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_SPDIFRX_MspInit(hspdif);
- }
-
- /* SPDIFRX peripheral state is BUSY*/
- hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-
- /* Disable SPDIFRX interface (IDLE State) */
- __HAL_SPDIFRX_IDLE(hspdif);
-
- /* Reset the old SPDIFRX CR configuration */
- tmpreg = hspdif->Instance->CR;
-
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
- SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
- SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
- SPDIFRX_CR_CKSEN | SPDIFRX_CR_CKSBKPEN |
- SPDIFRX_CR_INSEL);
-
- /* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
- hspdif->Init.InputSelection |
- hspdif->Init.Retries |
- hspdif->Init.WaitForActivity |
- hspdif->Init.ChannelSelection |
- hspdif->Init.DataFormat |
- hspdif->Init.PreambleTypeMask |
- hspdif->Init.ChannelStatusMask |
- hspdif->Init.ValidityBitMask |
- hspdif->Init.SymbolClockGen |
- hspdif->Init.BackupSymbolClockGen |
- hspdif->Init.ParityErrorMask
- );
-
- hspdif->Instance->CR = tmpreg;
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-
- /* SPDIFRX peripheral state is READY*/
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the SPDIFRX peripheral
- * @param hspdif: SPDIFRX handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
-
- hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-
- /* Disable SPDIFRX interface (IDLE state) */
- __HAL_SPDIFRX_IDLE(hspdif);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPDIFRX_MspDeInit(hspdif);
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-
- /* SPDIFRX peripheral state is RESET*/
- hspdif->State = HAL_SPDIFRX_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
-}
-
-/**
- * @brief SPDIFRX MSP Init
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SPDIFRX MSP DeInit
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Sets the SPDIFRX dtat format according to the specified parameters
- * in the SPDIFRX_InitTypeDef.
- * @param hspdif: SPDIFRX handle
- * @param sDataFormat: SPDIFRX data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
-{
- uint32_t tmpreg = 0;
-
- /* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the SPDIFRX parameters */
- assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
- assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
- assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
- assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
- assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
- assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
-
- /* Reset the old SPDIFRX CR configuration */
- tmpreg = hspdif->Instance->CR;
-
- if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
- (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
- ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
- {
- return HAL_ERROR;
- }
-
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
- SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
-
- /* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) sDataFormat.StereoMode |
- sDataFormat.DataFormat |
- sDataFormat.PreambleTypeMask |
- sDataFormat.ChannelStatusMask |
- sDataFormat.ValidityBitMask |
- sDataFormat.ParityErrorMask);
-
- hspdif->Instance->CR = tmpreg;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
-===============================================================================
- ##### IO operation functions #####
-===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPDIFRX data
- transfers.
-
- (#) There is two mode of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer start-up.
- The end of the data processing will be indicated through the
- dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_SPDIFRX_ReceiveDataFlow()
- (++) HAL_SPDIFRX_ReceiveControlFlow()
- (+@) Do not use blocking mode to receive both control and data flow at the same time.
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
- (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
- (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (++) HAL_SPDIFRX_RxCpltCallback()
- (++) HAL_SPDIFRX_ErrorCallback()
-
-@endverbatim
-* @{
-*/
-
-
-/**
- * @brief Receives an amount of data (Data Flow) in blocking mode.
- * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
- * the configuration information for SPDIFRX module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hspdif->State == HAL_SPDIFRX_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-
- /* Start synchronisation */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
-
- /* Receive data flow */
- while(Size > 0U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until RXNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*pData++) = hspdif->Instance->DR;
- Size--;
- }
-
- /* SPDIFRX ready */
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data (Control Flow) in blocking mode.
- * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
- * the configuration information for SPDIFRX module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hspdif->State == HAL_SPDIFRX_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->State = HAL_SPDIFRX_STATE_BUSY;
-
- /* Start synchronization */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
-
- /* Receive control flow */
- while(Size > 0U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until CSRNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*pData++) = hspdif->Instance->CSR;
- Size--;
- }
-
- /* SPDIFRX ready */
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
- * @param hspdif: SPDIFRX handle
- * @param pData: a 32-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be received .
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
-
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->pRxBuffPtr = pData;
- hspdif->RxXferSize = Size;
- hspdif->RxXferCount = Size;
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-
- /* Check if a receive process is ongoing or not */
- hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
-
-
- /* Enable the SPDIFRX PE Error Interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
-
- /* Enable the SPDIFRX OVR Error Interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- /* Enable the SPDIFRX RXNE interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
-
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
- {
- /* Start synchronization */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data (Control Flow) with Interrupt
- * @param hspdif: SPDIFRX handle
- * @param pData: a 32-bit pointer to the Receive data buffer.
- * @param Size: number of data sample (Control Flow) to be received :
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
-
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->pCsBuffPtr = pData;
- hspdif->CsXferSize = Size;
- hspdif->CsXferCount = Size;
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
-
- /* Check if a receive process is ongoing or not */
- hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
-
-
- /* Enable the SPDIFRX PE Error Interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
-
- /* Enable the SPDIFRX OVR Error Interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- /* Enable the SPDIFRX CSRNE interrupt */
- __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
-
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
- {
- /* Start synchronization */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data (Data Flow) mode with DMA
- * @param hspdif: SPDIFRX handle
- * @param pData: a 32-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be received :
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
- {
- hspdif->pRxBuffPtr = pData;
- hspdif->RxXferSize = Size;
- hspdif->RxXferCount = Size;
-
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
- hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
-
- /* Set the SPDIFRX Rx DMA Half transfer complete callback */
- hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
-
- /* Set the SPDIFRX Rx DMA transfer complete callback */
- hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
-
- /* Set the DMA error callback */
- hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
-
- /* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
-
- /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
- hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
-
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
- {
- /* Start synchronization */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data (Control Flow) with DMA
- * @param hspdif: SPDIFRX handle
- * @param pData: a 32-bit pointer to the Receive data buffer.
- * @param Size: number of data (Control Flow) sample to be received :
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
- {
- hspdif->pCsBuffPtr = pData;
- hspdif->CsXferSize = Size;
- hspdif->CsXferCount = Size;
-
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
- hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
-
- /* Set the SPDIFRX Rx DMA Half transfer complete callback */
- hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
-
- /* Set the SPDIFRX Rx DMA transfer complete callback */
- hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
-
- /* Set the DMA error callback */
- hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
-
- /* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
-
- /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
- hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
-
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
- {
- /* Start synchronization */
- __HAL_SPDIFRX_SYNC(hspdif);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Start reception */
- __HAL_SPDIFRX_RCV(hspdif);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief stop the audio stream receive from the Media.
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
- /* Disable the SPDIFRX DMA requests */
- hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
- hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
-
- /* Disable the SPDIFRX DMA channel */
- __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
- __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
-
- /* Disable SPDIFRX peripheral */
- __HAL_SPDIFRX_IDLE(hspdif);
-
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles SPDIFRX interrupt request.
- * @param hspdif: SPDIFRX handle
- * @retval HAL status
- */
-void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
- {
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
- SPDIFRX_ReceiveDataFlow_IT(hspdif);
- }
-
- /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
- {
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
- SPDIFRX_ReceiveControlFlow_IT(hspdif);
- }
-
- /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
- {
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
-
- /* Change the SPDIFRX error code */
- hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
-
- /* the transfer is not stopped */
- HAL_SPDIFRX_ErrorCallback(hspdif);
- }
-
- /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
- {
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
-
- /* Change the SPDIFRX error code */
- hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
-
- /* the transfer is not stopped */
- HAL_SPDIFRX_ErrorCallback(hspdif);
- }
-}
-
-/**
- * @brief Rx Transfer (Data flow) half completed callbacks
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer (Data flow) completed callbacks
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx (Control flow) Transfer half completed callbacks
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer (Control flow) completed callbacks
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SPDIFRX error callbacks
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspdif);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
-@verbatim
-===============================================================================
-##### Peripheral State and Errors functions #####
-===============================================================================
-[..]
-This subsection permit to get in run-time the status of the peripheral
-and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPDIFRX state
- * @param hspdif : SPDIFRX handle
- * @retval HAL state
- */
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
-{
- return hspdif->State;
-}
-
-/**
- * @brief Return the SPDIFRX error code
- * @param hspdif : SPDIFRX handle
- * @retval SPDIFRX Error Code
- */
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
-{
- return hspdif->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief DMA SPDIFRX receive process (Data flow) complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Rx DMA Request */
- if(hdma->Init.Mode != DMA_CIRCULAR)
- {
- hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
- hspdif->RxXferCount = 0;
- hspdif->State = HAL_SPDIFRX_STATE_READY;
- }
- HAL_SPDIFRX_RxCpltCallback(hspdif);
-}
-
-/**
- * @brief DMA SPDIFRX receive process (Data flow) half complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
-}
-
-
-/**
- * @brief DMA SPDIFRX receive process (Control flow) complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
-{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Cb DMA Request */
- hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
- hspdif->CsXferCount = 0;
-
- hspdif->State = HAL_SPDIFRX_STATE_READY;
- HAL_SPDIFRX_CxCpltCallback(hspdif);
-}
-
-/**
- * @brief DMA SPDIFRX receive process (Control flow) half complete callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
-}
-
-/**
- * @brief DMA SPDIFRX communication error callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Rx and Cb DMA Request */
- hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
- hspdif->RxXferCount = 0;
-
- hspdif->State= HAL_SPDIFRX_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
- HAL_SPDIFRX_ErrorCallback(hspdif);
-}
-
-/**
- * @brief Receive an amount of data (Data Flow) with Interrupt
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Receive data */
- (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
- hspdif->RxXferCount--;
-
- if(hspdif->RxXferCount == 0)
- {
- /* Disable RXNE/PE and OVR interrupts */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
-
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- HAL_SPDIFRX_RxCpltCallback(hspdif);
- }
-}
-
-/**
- * @brief Receive an amount of data (Control Flow) with Interrupt
- * @param hspdif: SPDIFRX handle
- * @retval None
- */
-static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
-{
- /* Receive data */
- (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
- hspdif->CsXferCount--;
-
- if(hspdif->CsXferCount == 0)
- {
- /* Disable CSRNE interrupt */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
-
- hspdif->State = HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- HAL_SPDIFRX_CxCpltCallback(hspdif);
- }
-}
-
-/**
- * @brief This function handles SPDIFRX Communication Timeout.
- * @param hspdif: SPDIFRX handle
- * @param Flag: Flag checked
- * @param Status: Value of the flag expected
- * @param Timeout: Duration of the timeout
- * @param tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
-{
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
-
- hspdif->State= HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
-
- hspdif->State= HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* SPDIFRX */
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
deleted file mode 100644
index 4d9f0de..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
+++ /dev/null
@@ -1,3137 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spi.c
- * @author MCD Application Team
- * @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Peripheral Interface (SPI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
- (+++) Enable the DMAx clock
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SPI_MspInit() API.
-
- [..]
- Circular mode restriction:
- (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
- (++) Master 2Lines RxOnly
- (++) Master 1Line Rx
- (+) The CRC feature is not managed when the DMA circular mode is enabled
- (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
- HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
- Those functions are maintained for backward compatibility reasons.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPI SPI
- * @brief SPI HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
- uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_32BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_32BIT(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPIx peripheral:
-
- (+) User must implement HAL_SPI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Direction
- (++) Data Size
- (++) Clock Polarity and Phase
- (++) NSS Management
- (++) BaudRate Prescaler
- (++) FirstBit
- (++) TIMode
- (++) CRC Calculation
- (++) CRC Polynomial if CRC enabled
- (++) CRC Length, used only with Data8 and Data16
- (++) FIFO reception threshold
- (++) FIFO transmission threshold
-
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SPI according to the specified parameters
- * in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
- uint32_t crc_length = 0;
- uint32_t packet_length = 0;
-
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
- if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
- {
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
- }
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
- assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
- assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- /* Verify that the SPI instance supports Data Size higher than 16bits */
- if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
- {
- return HAL_ERROR;
- }
-
- /* Verify that the SPI instance supports requested data packing */
- packet_length = SPI_GetPacketSize(hspi);
- if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE )) ||
- (( IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)) )
- {
- return HAL_ERROR;
- }
-
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Verify that the SPI instance supports CRC Length higher than 16bits */
- if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
- {
- return HAL_ERROR;
- }
-
- /* Align the CRC Length on the data size */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
- {
- crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
- }
- else
- {
- crc_length = hspi->Init.CRCLength;
- }
-
- /* Verify that the CRC Length is higher than DataSize */
- if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
- {
- return HAL_ERROR;
- }
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->State == HAL_SPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hspi->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit, CRC calculation state, CRC Length */
-
- if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
- }
-
- /* SPIx CFG1 Configuration */
- WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
- hspi->Init.FifoThreshold | hspi->Init.DataSize));
-
- /* SPIx CFG2 Configuration */
- WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | hspi->Init.NSSPolarity |
- hspi->Init.NSS | hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
- hspi->Init.FirstBit | hspi->Init.Mode | hspi->Init.MasterInterDataIdleness |
- hspi->Init.Direction | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
-
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Initialize TXCRC Pattern Initial Value */
- if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
- SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
- else
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
-
- /* Initialize RXCRC Pattern Initial Value */
- if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
- SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
- else
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
-
- /* Enable 33/17 bits CRC computation */
- if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
- ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)) )
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
- else
- CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
-
- /* Write CRC polynomial in SPI Register */
- WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
- }
-#endif /* USE_SPI_CRC */
-
- /* Insure that Underrun configuration is managed only by Salve */
- if (hspi->Init.Mode == SPI_MODE_SLAVE)
- {
- /* Set Default Underrun configuration */
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
-#endif
- {
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
- }
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
- }
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
- /* Insure that AFCNTR is managed only by Master */
- if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
- {
- /* Alternate function GPIOs control */
- MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
- }
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initialize the SPI peripheral.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check SPI Instance parameter */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the SPI Peripheral Clock */
- __HAL_SPI_DISABLE(hspi);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPI_MspDeInit(hspi);
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPI
- data transfers.
-
- [..] The SPI supports master and slave mode :
-
- (#) There are two modes of transfer:
- (##) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (##) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
- exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Transmit data in 32 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- /* Transmit data in 32 Bit mode */
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
- /* Transmit data in 16 Bit mode */
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- if ( (hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount-=2;
- }
- else
- {
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
- /* Transmit data in 8 Bit mode */
- else
- {
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- if ((hspi->TxXferCount > 3U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount-=4;
- }
- else if ((hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount-=2;
- }
- else
- {
- *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
-
- /* Wait for Tx (and CRC) data to be sent */
- if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
- /* Configure communication direction: 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Receive data in 32 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXWNE/EOT flag */
- if (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_EOT))
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
- /* Receive data in 16 Bit mode */
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXWNE/FRLVL flag */
- if (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_FRLVL))
- {
- if (hspi->Instance->SR & SPI_FLAG_RXWNE)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount-=2;
- }
- else
- {
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
- /* Receive data in 8 Bit mode */
- else
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXWNE/FRLVL flag */
- if (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_FRLVL))
- {
- if (hspi->Instance->SR & SPI_FLAG_RXWNE)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount-=4;
- }
- else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
- {
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount-=2;
- }
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait for crc data to be received */
- if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (!((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferCount = Size;
- hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Transmit and Receive data in 32 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount --;
- }
-
- /* Check RXWNE/EOT flag */
- if ((hspi->RxXferCount > 0U) && (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_EOT)))
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount --;
- }
-
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- /* Transmit and Receive data in 16 Bit mode */
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- if ( (hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount-=2;
- }
- else
- {
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- }
-
- /* Check RXWNE/FRLVL flag */
- if ((hspi->RxXferCount > 0U) && (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_FRLVL)))
- {
- if (hspi->Instance->SR & SPI_FLAG_RXWNE)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount-=2;
- }
- else
- {
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
- }
-
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
- /* Transmit and Receive data in 8 Bit mode */
- else
- {
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* check TXE flag */
- if ((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- if ((hspi->TxXferCount > 3U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount-=4;
- }
- else if ((hspi->TxXferCount > 1U) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount-=2;
- }
- else
- {
- *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- }
-
- /* Wait until RXWNE/FRLVL flag is reset */
- if ((hspi->RxXferCount > 0U) && (hspi->Instance->SR & (SPI_FLAG_RXWNE|SPI_FLAG_FRLVL)))
- {
- if (hspi->Instance->SR & SPI_FLAG_RXWNE)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount-=4;
- }
- else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_FRLVL_QUARTER_FULL)
- {
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount-=2;
- }
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
- }
-
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Wait for Tx/Rx (and CRC) data to be sent/received */
- if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- hspi->TxISR = SPI_TxISR_32BIT;
- }
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- /* Enable EOT, TXE and UDR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXE | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->TxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- hspi->RxISR = SPI_RxISR_32BIT;
- }
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->RxISR = SPI_RxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_RxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- /* Enable EOT, RXNE and OVR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXNE | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (!((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- hspi->RxISR = SPI_2linesRxISR_32BIT;
- hspi->TxISR = SPI_2linesTxISR_32BIT;
- }
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
- /* Set the number if data at current transfer */
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- /* Enable EOT, TXE, RXNE, UDR and OVR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = NULL;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
- /* Packing mode management is enabled by the DMA settings */
- if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
- ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
- (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Adjust XferCount according to DMA alignement / Data size */
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
- {
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 1U) >> 1U;
- }
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 3U) >> 2U;
- }
- }
- else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
- {
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 1U) >> 1U;
- }
- }
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Clear TXDMAEN bit*/
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount);
-
- /* Set the number if data at current transfer */
- if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0);
- }
- else
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
- }
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
- /* Packing mode management is enabled by the DMA settings */
- if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
- ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
- (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Clear RXDMAEN bit */
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Adjust XferCount according to DMA alignement / Data size */
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
- {
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 1U) >> 1U;
- }
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 3U) >> 2U;
- }
- }
- else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
- {
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 1U) >> 1U;
- }
- }
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Set the number if data at current transfer */
- if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0);
- }
- else
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
- }
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- if (!((hspi->State == HAL_SPI_STATE_READY) ||
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
- /* Reset the Tx/Rx DMA bits */
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
-
- /* Packing mode management is enabled by the DMA settings */
- if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
- ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
- (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Adjust XferCount according to DMA alignement / Data size */
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
- {
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 1U) >> 1U;
- }
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 3U) >> 2U;
- }
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 1U) >> 1U;
- }
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 3U) >> 2U;
- }
- }
- else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
- {
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->TxXferCount = (hspi->TxXferCount + 1U) >> 1U;
- }
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
- {
- hspi->RxXferCount = (hspi->RxXferCount + 1U) >> 1U;
- }
- }
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- }
- else
- {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
- hspi->hdmatx->XferErrorCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount);
-
- if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0);
- }
- else
- {
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
- }
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
-
- if (hspi->Init.Mode == SPI_MODE_MASTER)
- {
- /* Master transfer start */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * @note This procedure performs following operations :
- * + Disable SPI Interrupts (depending of transfer direction)
- * + Disable the DMA transfer in the peripheral register (if enabled)
- * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * + Set handle State to READY.
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- __IO uint32_t count;
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- /* Set hspi->state to aborting to avoid any interaction */
- hspi->State = HAL_SPI_STATE_ABORT;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* If master communication on going, make sure current frame is done before closing the connection */
- if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
- {
- if (hspi->hdmatx != NULL)
- {
- /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
- {
- if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- }
- }
- }
-
- /* Disable the SPI DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
- {
- if (hspi->hdmarx != NULL)
- {
- /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
- {
- if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- }
- }
- }
-
- /* Proceed with abort procedure */
- SPI_AbortTransfer(hspi);
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * @note This procedure performs following operations :
- * + Disable SPI Interrupts (depending of transfer direction)
- * + Disable the DMA transfer in the peripheral register (if enabled)
- * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * + Set handle State to READY
- * + At abort completion, call user abort complete callback.
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- __IO uint32_t count;
- uint32_t dma_tx_abort_done = 1, dma_rx_abort_done = 1;
-
- /* Set hspi->state to aborting to avoid any interaction */
- hspi->State = HAL_SPI_STATE_ABORT;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* If master communication on going, make sure current frame is done before closing the connection */
- if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
- }
-
- /* Reset Callbacks */
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
-
- if ((hspi->hdmatx != NULL) && HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled */
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
- }
-
- if ((hspi->hdmarx != NULL) && HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled */
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
- }
-
- /* Disable the SPI DMA Tx request if enabled */
- if ((hspi->hdmatx != NULL) && HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
- {
- dma_tx_abort_done = 0;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
- {
- dma_tx_abort_done = 1;
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- }
- }
-
- /* Disable the SPI DMA Rx request if enabled */
- if ((hspi->hdmarx != NULL) && HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
- {
- dma_rx_abort_done = 0;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
- {
- dma_rx_abort_done = 1;
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- }
- }
-
- /* If no running DMA transfer, finish cleanup and call callbacks */
- if ((dma_tx_abort_done == 1) && (dma_rx_abort_done == 1))
- {
- /* Proceed with abort procedure */
- SPI_AbortTransfer(hspi);
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
- }
-
- return errorcode;
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * This API is supported, it is maintained for backward compatibility.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL_ERROR
- */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
- /* Set error code to not supported */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
-
- return HAL_ERROR;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * This API is supported, it is maintained for backward compatibility.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL_ERROR
- */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
- /* Set error code to not supported */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
-
- return HAL_ERROR;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * This API is supported, it is maintained for backward compatibility.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL_ERROR
- */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
- /* Set error code to not supported */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
-
- return HAL_ERROR;
-}
-
-/**
- * @brief Handle SPI interrupt request.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None
- */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
- uint32_t itsource = hspi->Instance->IER;
- uint32_t itflag = hspi->Instance->SR;
- uint32_t trigger = itsource & itflag;
- uint32_t cfg1 = hspi->Instance->CFG1;
- uint32_t handled = 0;
-
- HAL_SPI_StateTypeDef State = hspi->State;
-
- /* SPI in mode Receiver ----------------------------------------------------*/
- if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXNE))
- {
- hspi->RxISR(hspi);
- handled = 1;
- }
-
- /* SPI in mode Transmitter -------------------------------------------------*/
- if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXE))
- {
- hspi->TxISR(hspi);
- handled = 1;
- }
-
- if (handled != 0)
- return;
-
- /* SPI End Of Transfer: DMA or IT based transfer */
- if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
- {
- /* Clear EOT/TXTF/SUSP flag */
- __HAL_SPI_CLEAR_EOTFLAG(hspi);
- __HAL_SPI_CLEAR_TXTFFLAG(hspi);
- __HAL_SPI_CLEAR_SUSPFLAG(hspi);
-
- /* Disable EOT interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
-
- /* DMA Normal Mode */
- if( HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN|SPI_CFG1_RXDMAEN) || // IT based transfer is done
- ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
- ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL)) ) // DMA is used in normal mode
- {
- /* For the IT based receive extra polling maybe required for last packet */
- if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN|SPI_CFG1_RXDMAEN))
- {
- /* Pooling remaining data */
- while (hspi->RxXferCount != 0)
- {
- /* Receive data in 32 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- }
- /* Receive data in 16 Bit mode */
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- }
- /* Receive data in 8 Bit mode */
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- }
- hspi->RxXferCount--;
- }
- }
-
- /* Call SPI Standard close procedure */
- SPI_CloseTransfer(hspi);
-
- hspi->State = HAL_SPI_STATE_READY;
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
-
- /* Call appropriate user callback */
- if (State == HAL_SPI_STATE_BUSY_TX_RX)
- {
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- else if (State == HAL_SPI_STATE_BUSY_RX)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else if (State == HAL_SPI_STATE_BUSY_TX)
- {
- HAL_SPI_TxCpltCallback(hspi);
- }
- return;
- }
-
- if (HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT) && HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP ))
- {
- /* Abort on going, clear SUSP flag to avoid infinit looping */
- __HAL_SPI_CLEAR_SUSPFLAG(hspi);
-
- return;
- }
-
- /* SPI in Error Treatment --------------------------------------------------*/
- if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != RESET)
- {
- /* SPI Overrun error interrupt occurred ----------------------------------*/
- if ((trigger & SPI_FLAG_OVR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if ((trigger & SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Frame error interrupt occurred ------------------------------------*/
- if ((trigger & SPI_FLAG_FRE) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
- }
-
- /* SPI Underrun error interrupt occurred ------------------------------------*/
- if ((trigger & SPI_FLAG_UDR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
- __HAL_SPI_CLEAR_UDRFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
-
- /* Disable the SPI DMA requests if enabled */
- if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN|SPI_CFG1_RXDMAEN))
- {
- /* Disable the SPI DMA requests */
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
-
- /* Abort the SPI DMA Rx channel */
- if (hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
- }
- /* Abort the SPI DMA Tx channel */
- if (hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
- }
- }
- else
- {
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user error callback */
- HAL_SPI_ErrorCallback(hspi);
- }
- }
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Half Transfer callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief SPI error callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred
- */
-}
-
-/**
- * @brief SPI Abort Complete callback.
- * @param hspi SPI handle.
- * @retval None
- */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
- (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPI handle state.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI state
- */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI handle state */
- return hspi->State;
-}
-
-/**
- * @brief Return the SPI error code.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI error code in bitmap format
- */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI ErrorCode */
- return hspi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief DMA SPI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hspi->State != HAL_SPI_STATE_ABORT)
- {
- if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
- {
- HAL_SPI_TxCpltCallback(hspi);
- }
- else
- {
- /* Enable EOT interrupt */
- __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
- }
- }
-}
-
-/**
- * @brief DMA SPI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hspi->State != HAL_SPI_STATE_ABORT)
- {
- if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- /* Enable EOT interrupt */
- __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
- }
- }
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- if (hspi->State != HAL_SPI_STATE_ABORT)
- {
- if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
- {
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- else
- {
- /* Enable EOT interrupt */
- __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
- }
- }
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* if DMA error is FIFO error ignore it */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
- {
- /* Call SPI standard close procedure */
- SPI_CloseTransfer(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
- }
-}
-
-/**
- * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmarx != NULL)
- {
- if (hspi->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* Call the Abort procedure */
- SPI_AbortTransfer(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmatx != NULL)
- {
- if (hspi->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* Call the Abort procedure */
- SPI_AbortTransfer(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BIT(SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 8 Bit mode */
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BIT(SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Rx 32-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_32BIT(SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 32 Bit mode */
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_8BIT(SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 8 Bit mode */
- *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_16BIT(SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-
-/**
- * @brief Tx 32-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_32BIT(SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 32 Bit mode */
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-
-/**
- * @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
-{
- *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
-{
- *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Manage the 32-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
-{
- *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->RxXferCount == 0U)
- {
- /* Disable RXNE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- }
-}
-
-
-/**
- * @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-/**
- * @brief Handle the data 32-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount--;
-
- /* Disable IT if no more data excepted */
- if (hspi->TxXferCount == 0U)
- {
- /* Disable TXE interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- }
-}
-
-/**
- * @brief Abort Transfer and clear flags.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
-{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable ITs */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
-
- /* Clear the Status flags in the SR register */
- __HAL_SPI_CLEAR_EOTFLAG(hspi);
- __HAL_SPI_CLEAR_TXTFFLAG(hspi);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN|SPI_CFG1_RXDMAEN);
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_UDRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- __HAL_SPI_CLEAR_SUSPFLAG(hspi);
-
-#if (USE_SPI_CRC != 0U)
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-#endif /* USE_SPI_CRC */
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
-}
-
-
-/**
- * @brief Close Transfer and clear flags.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL_ERROR: if any error detected
-* HAL_OK: if nothing detected
- */
-static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
-{
- uint32_t itflag = hspi->Instance->SR;
-
- __HAL_SPI_CLEAR_EOTFLAG(hspi);
- __HAL_SPI_CLEAR_TXTFFLAG(hspi);
-
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable ITs */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN|SPI_CFG1_RXDMAEN);
-
- /* Report UnderRun error for non RX Only communication */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- if ((itflag & SPI_FLAG_UDR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
- __HAL_SPI_CLEAR_UDRFLAG(hspi);
- }
- }
-
- /* Report OverRun error for non TX Only communication */
- if (hspi->State != HAL_SPI_STATE_BUSY_TX)
- {
- if ((itflag & SPI_FLAG_OVR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- if ((itflag & SPI_FLAG_CRCERR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if ((itflag & SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Frame error interrupt occurred ------------------------------------*/
- if ((itflag & SPI_FLAG_FRE) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
- }
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
-}
-
-/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param Status: flag state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
- uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Compute configurated packet size from fifo prespective.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval Packet size occuppied in the fifo
- */
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
-{
- uint32_t fifo_threashold = (hspi->Init.FifoThreshold>>SPI_CFG1_FTHLV_Pos) + 1;
- uint32_t data_size = (hspi->Init.DataSize >>SPI_CFG1_DSIZE_Pos) + 1;
-
- /* Convert data size to Byte */
- data_size = (data_size+7)/8;
-
- return data_size * fifo_threashold;
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c
deleted file mode 100644
index d23559e..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_spi_ex.c
- * @author MCD Application Team
- * @brief Extended SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * SPI peripheral extended functionalities :
- * + IO operation functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPIEx SPIEx
- * @brief SPI Extended HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
- * @{
- */
-
-/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of extended functions to manage the SPI
- data transfers.
-
- (#) SPIEx function:
- (++) HAL_SPIEx_FlushRxFifo()
- (++) HAL_SPIEx_FlushRxFifo()
- (++) HAL_SPIEx_EnableLockConfiguration()
- (++) HAL_SPIEx_ConfigureUnderrun()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Flush the RX fifo.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t tmpreg;
- uint8_t count = 0;
- while ( ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) || ((hspi->Instance->SR & SPI_FLAG_RXWNE) == SPI_FLAG_RXWNE))
- {
- count+=4;
- tmpreg = hspi->Instance->RXDR;
- UNUSED(tmpreg); /* To avoid GCC warning */
-
- if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
- {
- if(count > SPI_HIGHEND_FIFO_SIZE)
- {
- return HAL_TIMEOUT;
- }
- }
- else
- {
- if(count > SPI_LOWEND_FIFO_SIZE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief Enable the Lock for the AF configuration of associated IOs
- * and write protect the Content of Configuartion register 2
- * when SPI is enabled
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Check if the SPI is disabled to edit IOLOCK bit */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- SET_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- SET_BIT(hspi->Instance->CR1 , SPI_CR1_IOLOCK);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Configure the UNDERRUN condition and behavior of slave transmitter.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param UnderrunDetection : Detection of underrun condition at slave transmitter
- * This parameter can be a value of @ref SPI_Underrun_Detection.
- * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
- * This parameter can be a value of @ref SPI_Underrun_Behaviour.
- * @retval None
- */
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Check State and Insure that Underrun configuration is managed only by Salve */
- if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
- {
- errorcode = HAL_BUSY;
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
- assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
-
- /* Check if the SPI is disabled to edit CFG1 register */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Configure Underrun fields */
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
- }
- else
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Configure Underrun fields */
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
- MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
-
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c
deleted file mode 100644
index 5eae651..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_sram.c
- * @author MCD Application Team
- * @brief SRAM HAL module driver.
- * This file provides a generic firmware to drive SRAM memories
- * mounted as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control SRAM memories. It uses the FMC layer functions to interface
- with SRAM devices.
- The following sequence should be followed to configure the FMC to interface
- with SRAM/PSRAM memories:
-
- (#) Declare a SRAM_HandleTypeDef handle structure, for example:
- SRAM_HandleTypeDef hsram; and:
-
- (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
- values of the structure member.
-
- (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
- base register instance for NOR or SRAM device
-
- (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
- base register instance for NOR or SRAM extended mode
-
- (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
- mode timings; for example:
- FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
- and fill its fields with the allowed values of the structure member.
-
- (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
- performs the following sequence:
-
- (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
- (##) Control register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Init()
- (##) Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Timing_Init()
- (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Extended_Timing_Init()
- (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
-
- (#) At this stage you can perform read/write accesses from/to the memory connected
- to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
- following APIs:
- (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
- (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-
- (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
- HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
-
- (#) You can continuously monitor the SRAM device HAL state by calling the function
- HAL_SRAM_GetState()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SRAM SRAM
- * @brief SRAM driver modules
- * @{
- */
-#ifdef HAL_SRAM_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
- @verbatim
- ==============================================================================
- ##### SRAM Initialization and de_initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to initialize/de-initialize
- the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param Timing: Pointer to SRAM control timing structure
- * @param ExtTiming: Pointer to SRAM extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the SRAM handle parameter */
- if(hsram == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hsram->State == HAL_SRAM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsram->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_SRAM_MspInit(hsram);
- }
-
- /* Initialize SRAM control Interface */
- FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
-
- /* Initialize SRAM timing Interface */
- FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
-
- /* Initialize SRAM extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
-
- /* Enable FMC IP */
- __FMC_ENABLE();
-
- return HAL_OK;
-}
-
-/**
- * @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_SRAM_MspDeInit(hsram);
-
- /* Configure the SRAM registers with their reset values */
- FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
-
- hsram->State = HAL_SRAM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief SRAM MSP Init.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SRAM MSP DeInit.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hmdma: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdma);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete error callback.
- * @param hmdma: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmdma);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### SRAM Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint8_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint8_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint16_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint16_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *pDstBuffer = *(__IO uint32_t *)pAddress;
- pDstBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
- {
- *(__IO uint32_t *)pAddress = *pSrcBuffer;
- pSrcBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hmdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hmdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Stream */
- HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4), 1);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hmdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hmdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Stream */
- HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4), 1);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the SRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the SRAM controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the SRAM controller state
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL state
- */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
-{
- return hsram->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_SRAM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c
deleted file mode 100644
index 919afae..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c
+++ /dev/null
@@ -1,1532 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_swpmi.c
- * @author MCD Application Team
- * @brief SWPMI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Single Wire Protocol Master Interface (SWPMI).
- * + Initialization and Configuration
- * + Data transfers functions
- * + DMA transfers management
- * + Interrupts and flags management
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The SWPMI HAL driver can be used as follows:
-
- (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).
-
- (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
- (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
- (##) SWPMI IO configuration:
- (+++) Enable the clock for the SWPMI GPIO.
- (+++) Configure these SWPMI pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
- and HAL_SWPMI_Receive_IT() APIs):
- (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
- (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().
-
- (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
- and HAL_SWPMI_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channels.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required
- Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channels and requests.
- (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Tx/Rx channels.
-
- (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.
-
- (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SWPMI SWPMI
- * @brief HAL SWPMI module driver
- * @{
- */
-#ifdef HAL_SWPMI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup SWPMI_Private_Constants SWPMI Private Constants
- * @{
- */
-#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000U)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
-static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
-static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
-static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
-static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
-static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
-static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
- * @{
- */
-
-/** @defgroup SWPMI_Exported_Group1 Initialization/de-initialization methods
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the SWPMI peripheral.
- (+) De-initialize the SWPMI peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
-{
- uint32_t tickstart = HAL_GetTick();
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
- assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
- assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
- assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
-
- if(hswpmi->State == HAL_SWPMI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hswpmi->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_SWPMI_MspInit(hswpmi);
- }
-
- hswpmi->State = HAL_SWPMI_STATE_BUSY;
-
- /* Disable SWPMI interface */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
-
- /* Apply Voltage class selection */
- MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
-
- /* Configure the BRR register (Bitrate) */
- WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
-
- /* Apply SWPMI CR configuration */
- MODIFY_REG(hswpmi->Instance->CR, \
- SWPMI_CR_RXDMA | SWPMI_CR_TXDMA | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
- hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
-
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
- hswpmi->State = HAL_SWPMI_STATE_READY;
- /*Enable the SWPMI transceiver.*/
- __HAL_SWPMI_TRANSCEIVER_ENABLE(hswpmi);
- /* Wait on TXBEF flag to be able to start a second transfer */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
- {
- status = HAL_TIMEOUT;
- }
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
-
- return status;
-}
-
-/**
- * @brief De-initialize the SWPMI peripheral.
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
-
- hswpmi->State = HAL_SWPMI_STATE_BUSY;
-
- /* Disable SWPMI interface */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
-
- /* Disable SWPMI transceiver */
- __HAL_SWPMI_TRANSCEIVER_DISABLE(hswpmi);
-
- /* DeInit the low level hardware */
- HAL_SWPMI_MspDeInit(hswpmi);
-
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
-
- hswpmi->State = HAL_SWPMI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hswpmi);
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the SWPMI MSP.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SWPMI_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SWPMI MSP.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SWPMI_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Exported_Group2 IO operation methods
- * @brief SWPMI Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation methods #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SWPMI
- data transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
- or DMA. The end of the data processing will be indicated through the
- dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
- the selected DMA channel interrupt handler when using DMA mode.
- The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or receive process.
- The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.
-
- (#) Blocking mode API's are:
- (++) HAL_SWPMI_Transmit()
- (++) HAL_SWPMI_Receive()
-
- (#) Non-Blocking mode API's with Interrupt are:
- (++) HAL_SWPMI_Transmit_IT()
- (++) HAL_SWPMI_Receive_IT()
- (++) HAL_SWPMI_IRQHandler()
-
- (#) Non-Blocking mode API's with DMA are:
- (++) HAL_SWPMI_Transmit_DMA()
- (++) HAL_SWPMI_Receive_DMA()
- (++) HAL_SWPMI_DMAPause()
- (++) HAL_SWPMI_DMAResume()
- (++) HAL_SWPMI_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
- (++) HAL_SWPMI_TxHalfCpltCallback()
- (++) HAL_SWPMI_TxCpltCallback()
- (++) HAL_SWPMI_RxHalfCpltCallback()
- (++) HAL_SWPMI_RxCpltCallback()
- (++) HAL_SWPMI_ErrorCallback()
-
- (#) The capability to launch the above IO operations in loopback mode for
- user application verification:
- (++) HAL_SWPMI_EnableLoopback()
- (++) HAL_SWPMI_DisableLoopback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
- * the configuration information for SWPMI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
- {
- /* Check if a non-blocking receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
-
- /* Disable any transmitter interrupts */
- __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
-
- /* Disable any transmitter flags */
- __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- do
- {
- /* Wait the TXE to write data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
- {
- hswpmi->Instance->TDR = (*pData++);
- Size--;
- }
- else
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
- }
- } while(Size != 0);
-
- /* Wait on TXBEF flag to be able to start a second transfer */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
- {
- status = HAL_TIMEOUT;
- }
-
- if(status == HAL_OK)
- {
- /* Check if a non-blocking receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
- }
-
- if((status != HAL_OK) && (status != HAL_BUSY))
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
- * the configuration information for SWPMI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
- {
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
-
- /* Disable any receiver interrupts */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- do
- {
- /* Wait the RXNE to read data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
- {
- (*pData++) = hswpmi->Instance->RDR;
- Size--;
- }
- else
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
- }
- } while(Size != 0);
-
- if(status == HAL_OK)
- {
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
- {
- /* Clear RXBFF at end of reception */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
- }
-
- /* Check if a non-blocking transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
- }
- }
- else
- {
- status = HAL_BUSY;
- }
- }
-
- if((status != HAL_OK) && (status != HAL_BUSY))
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- return status;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with interrupt.
- * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
- * the configuration information for SWPMI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
- {
- /* Update handle */
- hswpmi->pTxBuffPtr = pData;
- hswpmi->TxXferSize = Size;
- hswpmi->TxXferCount = Size;
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
-
- /* Check if a receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- /* Enable the SWPMI transmit underrun error */
- __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- /* Enable the SWPMI interrupts: */
- /* - Transmit data register empty */
- /* - Transmit buffer empty */
- /* - Transmit/Reception completion */
- __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hswpmi: SWPMI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
- {
- /* Update handle */
- hswpmi->pRxBuffPtr = pData;
- hswpmi->RxXferSize = Size;
- hswpmi->RxXferCount = Size;
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
-
- /* Check if a transmit process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- /* Enable the SWPMI slave resume */
- /* Enable the SWPMI Data Register not empty Interrupt, receive CRC Error, receive overrun and RxBuf Interrupt */
- /* Enable the SWPMI Transmit/Reception completion */
- __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA interrupt.
- * @param hswpmi: SWPMI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
- {
- /* Update handle */
- hswpmi->pTxBuffPtr = pData;
- hswpmi->TxXferSize = Size;
- hswpmi->TxXferCount = Size;
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
-
- /* Check if a receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- /* Set the SWPMI DMA transfer complete callback */
- hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
-
- /* Set the SWPMI DMA Half transfer complete callback */
- hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
-
- /* Enable the SWPMI transmit DMA Stream */
- HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- /* Enable the SWPMI transmit underrun error */
- __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
-
- /* Enable the DMA transfer for transmit request by setting the TXDMA bit
- in the SWPMI CR register */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA interrupt.
- * @param hswpmi: SWPMI handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if((pData == NULL ) || (Size == 0))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
- {
- /* Update handle */
- hswpmi->pRxBuffPtr = pData;
- hswpmi->RxXferSize = Size;
- hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
-
- /* Check if a transmit process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
-
- /* Enable SWPMI peripheral if not */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
- }
-
- /* Set the SWPMI DMA transfer complete callback */
- hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
-
- /* Set the SWPMI DMA Half transfer complete callback */
- hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
-
- /* Enable the DMA request */
- HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- /* Enable the SWPMI receive CRC Error and receive overrun interrupts */
- __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE);
-
- /* Enable the DMA transfer for the receiver request by setting the RXDMA bit
- in the SWPMI CR register */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
- }
- else
- {
- status = HAL_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Stop all DMA transfers.
- * @param hswpmi: SWPMI handle
- * @retval HAL_OK
- */
-HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- /* Disable the SWPMI Tx/Rx DMA requests */
- CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
-
- /* Abort the SWPMI DMA tx channel */
- if(hswpmi->hdmatx != NULL)
- {
- HAL_DMA_Abort(hswpmi->hdmatx);
- }
- /* Abort the SWPMI DMA rx channel */
- if(hswpmi->hdmarx != NULL)
- {
- HAL_DMA_Abort(hswpmi->hdmarx);
- }
-
- /* Disable SWPMI interface */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
-
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Enable the Loopback mode.
- * @param hswpmi: SWPMI handle
- * @note Loopback mode is to be used only for test purposes
- * @retval HAL_OK / HAL_BUSY
- */
-HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- /* Check SWPMI not enabled */
- if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
- {
- status = HAL_BUSY;
- }
- else
- {
- /* Set Loopback */
- SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- return status;
-}
-
-/**
- * @brief Disable the Loopback mode.
- * @param hswpmi: SWPMI handle
- * @note Loopback mode is to be used only for test purposes
- * @retval HAL_OK / HAL_BUSY
- */
-HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(hswpmi);
-
- /* Check SWPMI not enabled */
- if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
- {
- status = HAL_BUSY;
- }
- else
- {
- /* Reset Loopback */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hswpmi);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks
- * @brief SWPMI IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### SWPMI IRQ handler and callbacks #####
- ==============================================================================
-[..] This section provides SWPMI IRQ handler and callback functions called within
- the IRQ handler.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Handle SWPMI interrupt request.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
-{
-
- uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
- uint32_t regier = READ_REG(hswpmi->Instance->IER);
- uint32_t errcode = HAL_SWPMI_ERROR_NONE;
-
- /* SWPMI CRC error interrupt occurred --------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET))
- {
- /* Disable Receive CRC interrupt */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
- /* Clear Receive CRC and Receive buffer full flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
-
- errcode |= HAL_SWPMI_ERROR_CRC;
- }
-
- /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET))
- {
- /* Disable Receive overrun interrupt */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
- /* Clear Receive overrun flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
-
- errcode |= HAL_SWPMI_ERROR_OVR;
- }
-
- /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET))
- {
- /* Disable Transmit under run interrupt */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
- /* Clear Transmit under run flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
-
- errcode |= HAL_SWPMI_ERROR_UDR;
- }
-
- /* Call SWPMI Error Call back function if needed --------------------------*/
- if(errcode != HAL_SWPMI_ERROR_NONE)
- {
- hswpmi->ErrorCode |= errcode;
-
- if((errcode & HAL_SWPMI_ERROR_UDR) != RESET)
- {
- /* Check TXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
- {
- /* Disable DMA TX at SWPMI level */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
-
- /* Abort the USART DMA Tx channel */
- if(hswpmi->hdmatx != NULL)
- {
- /* Set the SWPMI Tx DMA Abort callback :
- will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
- hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
- {
- /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
- hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
- }
- }
- else
- {
- /* Set the SWPMI state ready to be able to start again the process */
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
- }
- }
- else
- {
- /* Set the SWPMI state ready to be able to start again the process */
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
- }
- }
- else
- {
- /* Check RXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
- {
- /* Disable DMA RX at SWPMI level */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
-
- /* Abort the USART DMA Rx channel */
- if(hswpmi->hdmarx != NULL)
- {
- /* Set the SWPMI Rx DMA Abort callback :
- will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
- hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
- {
- /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
- hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
- }
- }
- else
- {
- /* Set the SWPMI state ready to be able to start again the process */
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
- }
- }
- else
- {
- /* Set the SWPMI state ready to be able to start again the process */
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
- }
- }
- }
-
- /* SWPMI in mode Receiver ---------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE) != RESET))
- {
- SWPMI_Receive_IT(hswpmi);
- }
-
- /* SWPMI in mode Transmitter ------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET))
- {
- SWPMI_Transmit_IT(hswpmi);
- }
-
- /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
- if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET))
- {
- SWPMI_EndTransmit_IT(hswpmi);
- }
-
- /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
- if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET))
- {
- SWPMI_EndReceive_IT(hswpmi);
- }
-
- /* Both Transmission and reception complete ---------------------------------*/
- if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET))
- {
- SWPMI_EndTransmitReceive_IT(hswpmi);
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SWPMI_TxCpltCallback is to be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SWPMI_TxHalfCpltCallback is to be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SWPMI_RxCpltCallback is to be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SWPMI_RxHalfCpltCallback is to be implemented in the user file
- */
-}
-
-/**
- * @brief SWPMI error callback.
- * @param hswpmi: SWPMI handle
- * @retval None
- */
-__weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hswpmi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SWPMI_ErrorCallback is to be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SWPMI_Exported_Group4 Peripheral Control methods
- * @brief SWPMI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control methods #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SWPMI.
- (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
- (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SWPMI handle state.
- * @param hswpmi: SWPMI handle
- * @retval HAL state
- */
-HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Return SWPMI handle state */
- return hswpmi->State;
-}
-
-/**
-* @brief Return the SWPMI error code.
-* @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains
- * the configuration information for the specified SWPMI.
-* @retval SWPMI Error Code
-*/
-uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
-{
- return hswpmi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SWPMI_Private_Functions SWPMI Private Functions
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in interrupt mode.
- * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
- {
- if(hswpmi->TxXferCount == 0)
- {
- /* Disable the SWPMI TXE and Underrun Interrupts */
- CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
- }
- else
- {
- hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++);
- hswpmi->TxXferCount--;
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- return status;
-}
-
-/**
- * @brief Wraps up transmission in non-blocking mode.
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Clear the SWPMI Transmit buffer empty Flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
- /* Disable the all SWPMI Transmit Interrupts */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
-
- /* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
-
- HAL_SWPMI_TxCpltCallback(hswpmi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
- {
- *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR);
-
- if(--hswpmi->RxXferCount == 0)
- {
- /* Wait for RXBFF flag to update state */
- HAL_SWPMI_RxCpltCallback(hswpmi);
- }
- }
- else
- {
- status = HAL_BUSY;
- }
-
- return status;
-}
-
-/**
- * @brief Wraps up reception in non-blocking mode.
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Clear the SWPMI Receive buffer full Flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
- /* Disable the all SWPMI Receive Interrupts */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
-
- /* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Wraps up transmission and reception in non-blocking mode.
- * @param hswpmi: SWPMI handle
- * @retval HAL status
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
-{
- /* Clear the SWPMI Transmission Complete Flag */
- WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
- /* Disable the SWPMI Transmission Complete Interrupt */
- CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
-
- /* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
- }
- else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief DMA SWPMI transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t tickstart = 0;
-
- /* DMA Normal mode*/
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) != SET)
- {
- hswpmi->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by setting the TXDMA bit
- in the SWPMI CR register */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Wait the TXBEF */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- HAL_SWPMI_ErrorCallback(hswpmi);
- }
- else
- {
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
-
- HAL_SWPMI_TxCpltCallback(hswpmi);
- }
- }
- /* DMA Circular mode */
- else
- {
- HAL_SWPMI_TxCpltCallback(hswpmi);
- }
-}
-
-/**
- * @brief DMA SWPMI transmit process half complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SWPMI_TxHalfCpltCallback(hswpmi);
-}
-
-
-/**
- * @brief DMA SWPMI receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode*/
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == RESET)
- {
- hswpmi->RxXferCount = 0;
-
- /* Disable the DMA transfer for the receiver request by setting the RXDMA bit
- in the SWPMI CR register */
- CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
-
- /* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
- {
- hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
- }
- else
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
- }
- }
- HAL_SWPMI_RxCpltCallback(hswpmi);
-}
-
-/**
- * @brief DMA SWPMI receive process half complete callback.
- * @param hdma : DMA handle
- * @retval None
- */
-static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_SWPMI_RxHalfCpltCallback(hswpmi);
-}
-
-/**
- * @brief DMA SWPMI communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update handle */
- hswpmi->RxXferCount = 0;
- hswpmi->TxXferCount = 0;
- hswpmi->State= HAL_SWPMI_STATE_READY;
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
-}
-/**
- * @brief DMA SWPMI communication abort callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update handle */
- hswpmi->RxXferCount = 0;
- hswpmi->TxXferCount = 0;
- hswpmi->State= HAL_SWPMI_STATE_READY;
-
- HAL_SWPMI_ErrorCallback(hswpmi);
-}
-
-/**
- * @brief Handle SWPMI Communication Timeout.
- * @param hswpmi: SWPMI handle
- * @param Flag: specifies the SWPMI flag to check.
- * @param Tickstart Tick start value
- * @param Timeout timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Wait until flag is set */
- while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- hswpmi->State = HAL_SWPMI_STATE_READY;
-
- status = HAL_TIMEOUT;
- break;
- }
- }
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
deleted file mode 100644
index 9d1e013..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
+++ /dev/null
@@ -1,5704 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_tim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
- @verbatim
- ==============================================================================
- ##### TIM Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit (32-bit for TIM2/TIM5) up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending on the selected feature:
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base.
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT().
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT().
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT().
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT().
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT().
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
- (#) The DMA Burst is managed with the two following functions:
- (++)HAL_TIM_DMABurst_WriteStart().
- (++)HAL_TIM_DMABurst_ReadStart().
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief TIM Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Time base.
- (+) De-initialize the TIM Time base.
- (+) Start the TIM Time Base.
- (+) Stop the TIM Time Base.
- (+) Start the TIM Time Base and enable interrupt.
- (+) Stop the TIM Time Base and disable interrupt.
- (+) Start the TIM Time Base and enable DMA transfer.
- (+) Stop the TIM Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM Base peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM Time Base MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM Time Base MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Starts the TIM Time Base generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Time Base generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Time Base generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Time Base generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Time Base generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to peripheral.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- if(htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(htim->State == HAL_TIM_STATE_READY)
- {
- if((pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Time Base generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the TIM Output Compare.
- (+) Stop the TIM Output Compare.
- (+) Start the TIM Output Compare and enable interrupt.
- (+) Stop the TIM Output Compare and disable interrupt.
- (+) Start the TIM Output Compare and enable DMA transfer.
- (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM Output Compare MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM Output Compare MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if(htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
- *
-@verbatim
- ==============================================================================
- ##### TIM PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM PWM mode.
- (+) De-initialize the TIM PWM mode.
- (+) Start the TIM PWM mode.
- (+) Stop the TIM PWM mode.
- (+) Start the TIM PWM mode and enable interrupt.
- (+) Stop the TIM PWM mode and disable interrupt.
- (+) Start the TIM PWM mode and enable DMA transfer.
- (+) Stop the TIM PWM mode and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM PWM mode according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM PWM MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM PWM MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the TIM Input Capture mode.
- (+) Stop the TIM Input Capture mode.
- (+) Start the TIM Input Capture mode and enable interrupt.
- (+) Stop the TIM Input Capture mode and disable interrupt.
- (+) Start the TIM Input Capture mode and enable DMA transfer.
- (+) Stop the TIM Input Capture mode and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM Input Capture MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM Input Capture MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if((pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### TIM One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse mode.
- (+) De-initialize the TIM One Pulse mode.
- (+) Start the TIM One Pulse mode.
- (+) Stop the TIM One Pulse mode.
- (+) Start the TIM One Pulse mode and enable interrupt.
- (+) Stop the TIM One Pulse mode and disable interrupt.
- (+) Start the TIM One Pulse mode and enable DMA transfer.
- (+) Stop the TIM One Pulse mode and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM One Pulse mode according to the specified
- * parameters in the TIM_HandleTypeDef and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OnePulseMode: Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM One Pulse mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM One Pulse MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM One Pulse MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief TIM Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder mode.
- (+) Start the Time Encoder mode.
- (+) Stop the Time Encoder mode.
- (+) Start the Time Encoder mode and enable interrupt.
- (+) Stop the Time Encoder mode and disable interrupt.
- (+) Start the Time Encoder mode and enable DMA transfer.
- (+) Stop the Time Encoder mode and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initialize the TIM Encoder Interface and initialize the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sConfig: TIM Encoder Interface configuration structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
-{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
- tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitialize the TIM Encoder interface
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM Encoder Interface MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM Encoder Interface MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- }
- break;
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- }
- break;
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- }
- break;
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- }
- break;
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- }
- break;
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- }
- break;
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1: The destination Buffer address for Input Capture Channel1.
- * @param pData2: The destination Buffer address for Input Capture Channel2.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if(htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(htim->State == HAL_TIM_STATE_READY)
- {
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_ALL:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- default:
- break;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides TIM IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- /* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- HAL_TIM_PeriodElapsedCallback(htim);
- }
- }
- /* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- HAL_TIMEx_BreakCallback(htim);
- }
- }
- /* TIM Break input2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- HAL_TIMEx_BreakCallback(htim);
- }
- }
- /* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- HAL_TIM_TriggerCallback(htim);
- }
- }
- /* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- HAL_TIMEx_CommutationCallback(htim);
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input/Output channels for Output Compare, PWM, Input Capture
- or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sConfig: TIM Output Compare configuration structure.
- * @param Channel : TIM Channels to configure.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef* sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 5 in Output Compare */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 6 in Output Compare */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sConfig: TIM Input Capture configuration structure.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (Channel == TIM_CHANNEL_1)
- {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
- }
- else if (Channel == TIM_CHANNEL_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sConfig: TIM PWM configuration structure.
- * @param Channel : TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef* sConfig,
- uint32_t Channel)
-{
-
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sConfig: TIM One Pulse configuration structure.
- * @param OutputChannel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
-{
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if(OutputChannel != InputChannel)
- {
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Output compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- }
- break;
- default:
- break;
- }
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
- * This parameters can be on of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources.
- * This parameters can be on of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
- * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
- if(htim->State == HAL_TIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
- else if(htim->State == HAL_TIM_STATE_READY)
- {
- if((BurstBuffer == 0 ) && (BurstLength > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
- }
- break;
- default:
- break;
- }
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstRequestSrc: TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
- * This parameters can be on of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources.
- * This parameters can be on of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if((BurstBuffer == 0 ) && (BurstLength > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable t he DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
- }
- break;
- default:
- break;
- }
-
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstRequestSrc: TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Generate a software event
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param EventSource: specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: TIM Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: TIM Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: TIM Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: TIM Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: TIM COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: TIM Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: TIM Break event source
- * @arg TIM_EVENTSOURCE_BREAK2: TIM Break2 event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel.
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @arg TIM_Channel_5: TIM Channel 5
- * @arg TIM_Channel_6: TIM Channel 6
- * @retval None
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- uint32_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- }
- break;
-
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- case TIM_CHANNEL_5:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
- }
- }
- break;
- case TIM_CHANNEL_6:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 1 */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
- }
- }
- break;
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
- uint32_t tmpsmcr = 0;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource)
- {
- case TIM_CLOCKSOURCE_INTERNAL:
- {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE1:
- {
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE2:
- {
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- }
- break;
-
- case TIM_CLOCKSOURCE_TI1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- }
- break;
- case TIM_CLOCKSOURCE_TI2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- }
- break;
- case TIM_CLOCKSOURCE_TI1ED:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- }
- break;
- case TIM_CLOCKSOURCE_ITR0:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
- }
- break;
- case TIM_CLOCKSOURCE_ITR1:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
- case TIM_CLOCKSOURCE_ITR2:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
- }
- break;
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
- uint32_t tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim: TIM handle.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the Slave mode
- * (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel : TIM Channels to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0;
-
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) TIM Period elapsed callback
- (+) TIM Output Compare callback
- (+) TIM Input capture callback
- (+) TIM Trigger callback
- (+) TIM Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-
-}
-/**
- * @brief Output Compare callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-/**
- * @brief Input Capture callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TIM error callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base handle state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Output Compare handle state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM handle state
- * @param htim: TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture handle state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode handle state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_ErrorCallback(htim);
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_IC_CaptureCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_TriggerCallback(htim);
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx: TIM periheral
- * @param Structure: TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1 = 0;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief TIM Output Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The Output configuration structure
- * @retval None
- */
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Output Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The Output configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Output Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
- * @retval None
- */
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Output Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The Output configuration structure
- * @retval None
- */
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Output Compare 5 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The Output configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Output Compare 6 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config: The Output configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief TIM Slave mode configuration
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sSlaveConfig: The slave configuration structure
- * @retval None
- */
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
- }
- break;
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
-{
- uint32_t tmpsmcr = 0;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- uint32_t tmpsmcr = 0;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param ChannelState: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-/**
- * @}
- */
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
deleted file mode 100644
index 4afd4ea..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2088 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_tim_ex.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
- * + Time OCRef clear configuration
- * + Timer remapping capabilities configuration
- @verbatim
- ==============================================================================
- ##### TIM Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
- interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit().
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit().
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit().
- (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit().
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT().
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT().
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT().
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BDTR_BKF_SHIFT (16)
-#define BDTR_BK2F_SHIFT (20)
-#define TIMx_ETRSEL_MASK ((uint32_t)0x003C000)
-#define TIMx_TIxSEL_MASK ((uint32_t)0x000000F)
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-
-/* Private functions ---------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief TIM Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
- * @param htim: TIM Encoder Interface handle
- * @param sConfig: TIM Hall Sensor configuration structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the TIM Hall Sensor interface
- * @param htim: TIM Hall Sensor handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize TIM Hall Sensor MSP.
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM Hall Sensor handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM Hall Sensor handle.
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief TIM Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare/PWM.
- (+) Stop the Complementary Output Compare/PWM.
- (+) Start the Complementary Output Compare/PWM and enable interrupts.
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle.
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief TIM Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State) == (HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State) == (HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0 ) && (Length > 0))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief TIM Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
- * output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
- }
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure Output channels for OC and PWM mode.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
- (+) Configure timer remapping capabilities.
- (+) Enable or disable channel grouping
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source.
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source.
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation Interrupt Request */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source.
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim: TIM handle.
- * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef * sMasterConfig)
-{
- uint32_t tmpcr2;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim: TIM handle
- * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
-{
- uint32_t tmpbdtr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
-
- if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
- {
- assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
- assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
- /* Set the BREAK2 input related BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
- }
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the break input source.
- * @param htim: TIM handle.
- * @param BreakInput: Break input to configure.
- * This parameter can be one of the following values:
- * @arg TIM_BREAKINPUT_BRK: Timer break input
- * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @param sBreakInputConfig: Break input source configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
- uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
-{
- uint32_t tmporx = 0;
- uint32_t bkin_enable_mask = 0;
- uint32_t bkin_polarity_mask = 0;
- uint32_t bkin_enable_bitpos = 0;
- uint32_t bkin_polarity_bitpos = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_BREAKINPUT(BreakInput));
- assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
- assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
- }
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- switch(sBreakInputConfig->Source)
- {
- case TIM_BREAKINPUTSOURCE_BKIN:
- {
- bkin_enable_mask = TIM1_AF1_BKINE;
- bkin_enable_bitpos = 0;
- bkin_polarity_mask = TIM1_AF1_BKINP;
- bkin_polarity_bitpos = 9;
- }
- break;
- case TIM_BREAKINPUTSOURCE_COMP1:
- {
- bkin_enable_mask = TIM1_AF1_BKCMP1E;
- bkin_enable_bitpos = 1;
- bkin_polarity_mask = TIM1_AF1_BKCMP1P;
- bkin_polarity_bitpos = 10;
- }
- break;
- case TIM_BREAKINPUTSOURCE_COMP2:
- {
- bkin_enable_mask = TIM1_AF1_BKCMP2E;
- bkin_enable_bitpos = 2;
- bkin_polarity_mask = TIM1_AF1_BKCMP2P;
- bkin_polarity_bitpos = 11;
- }
- break;
- case TIM_BREAKINPUTSOURCE_DFSDM1:
- {
- bkin_enable_mask = TIM1_AF1_BKDFBK0E;
- bkin_enable_bitpos = 8;
- }
- break;
-
- default:
- break;
- }
-
- switch(BreakInput)
- {
- case TIM_BREAKINPUT_BRK:
- {
- /* Get the TIMx_OR2 register value */
- tmporx = htim->Instance->AF1;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
-
- /* Set TIMx_OR2 */
- htim->Instance->AF1 = tmporx;
- }
- break;
- case TIM_BREAKINPUT_BRK2:
- {
- /* Get the TIMx_OR3 register value */
- tmporx = htim->Instance->AF2;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- /* Set the break input polarity */
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
-
- /* Set TIMx_OR3 */
- htim->Instance->AF2 = tmporx;
- }
- break;
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIMx Remapping input capabilities.
- * @param htim: TIM handle.
- * @param Remap: specifies the TIM remapping source.
- * For TIM1, the parameter is one of the following values:
- * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO
- * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
- * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
- * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3:
- *
- * For TIM2, the parameter is one of the following values:
- * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
- * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
- * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
- * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
- * @arg TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
- * @arg TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
- *
- * For TIM3, the parameter is one of the following values:
- * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
- * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
- *
- * For TIM5, the parameter is one of the following values:
- * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO
- * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A
- * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B
- *
- * For TIM8, the parameter is one of the following values:
- * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO
- * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
- * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
- * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
- * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
- * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
- * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
- *
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
- uint32_t tmpor2 = 0;
-
- __HAL_LOCK(htim);
-
- /* Check parameters */
- assert_param(IS_TIM_ETRSEL_INSTANCE(htim->Instance));
- assert_param(IS_TIM_ETRREMAP(Remap));
-
- tmpor2 = htim->Instance->AF1;
- tmpor2 &= ~TIMx_ETRSEL_MASK;
- tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
-
- /* Set TIMx_OR2 */
- htim->Instance->AF1 = tmpor2;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIMx input Selection capabilities.
- * @param htim: TIM handle.
- * @param TISelection : parameter of the TIM_TISelectionStruct structure.
- * @param Channel: specifies the channels that will be selected for configuration:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- *
- * TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
- * For TIM1, the parameter is one of the following values:
- * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
- * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
- *
- * For TIM2, the parameter is one of the following values:
- * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
- * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
- * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
- * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
- *
- * For TIM3, the parameter is one of the following values:
- * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
- * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
- * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
- * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
- *
- * For TIM5, the parameter is one of the following values:
- * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
- * @arg TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP
- * @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP
- *
- * For TIM8, the parameter is one of the following values:
- * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
- * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
- *
- * For TIM15, the parameter is one of the following values:
- * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
- * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
- * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
- * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
- * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
- * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
- * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
- * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
- * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
- * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
- * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
- *
- * For TIM16, the parameter can have the following values:
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
- * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
- * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
- *
- * For TIM17, the parameter can have the following values:
- * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
- * @arg TIM_TIM17_TI1_SPDIFFS: TIM17 TI1 is connected to SPDIF FS
- * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
- * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel)
-{
- uint32_t tmptisel = 0;
-
- __HAL_LOCK(htim);
-
- /* Check parameters */
- assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TISEL(TISelection));
-
- tmptisel = htim->Instance->TISEL;
-
- tmptisel &= ~(TIMx_TIxSEL_MASK << (Channel << 2));
- tmptisel |= (TISelection);
-
- /* Set TIMx_TISEL */
- htim->Instance->TISEL = tmptisel;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-/**
- * @brief Group channel 5 and channel 1, 2 or 3
- * @param htim: TIM handle.
- * @param Channels: specifies the reference signal(s) the OC5REF is combined with.
- * This parameter can be any combination of the following values:
- * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
- * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
- * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
- * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
-{
- /* Check parameters */
- assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_GROUPCH5(Channels));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Clear GC5Cx bit fields */
- htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
-
- /* Set GC5Cx bit fields */
- htim->Instance->CCR5 |= Channels;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extended TIM callback functions:
- (+) TIM Commutation callback
- (+) TIM Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface state
- * @param htim: TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIMEx_CommutationCallback(htim);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
- uint32_t tmp = 0;
-
- tmp = TIM_CCER_CC1NE << Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
deleted file mode 100644
index cd2811b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
+++ /dev/null
@@ -1,2914 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_uart.c
- * @author MCD Application Team
- * @brief UART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
- (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) UART pins configuration:
- (+++) Enable the clock for the UART GPIOs.
- (+++) Configure these UART pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
- and HAL_UART_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) UART interrupts handling:
- -@@- The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) are managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
- (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
- and HAL_UART_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
-
- (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
- in the huart handle AdvancedInit structure.
-
- (#) For the UART asynchronous mode, initialize the UART registers by calling
- the HAL_UART_Init() API.
-
- (#) For the UART Half duplex mode, initialize the UART registers by calling
- the HAL_HalfDuplex_Init() API.
-
- (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
- by calling the HAL_LIN_Init() API.
-
- (#) For the UART Multiprocessor mode, initialize the UART registers
- by calling the HAL_MultiProcessor_Init() API.
-
- (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
- [..]
- (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
- also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
- calling the customized HAL_UART_MspInit() API.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UART UART
- * @brief HAL UART module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
- * @{
- */
-#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
-
-#define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */
-#define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
- * @{
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
- follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
- and UART multiprocessor mode configuration procedures (details for the procedures
- are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible UART formats are listed in the
- following table.
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the UART mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- /* Check the parameters */
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- }
- else
- {
- /* Check the parameters */
- assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
- }
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Initialize the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check UART instance */
- assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In half-duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief Initialize the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: UART handle.
- * @param BreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
- * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the LIN UART instance */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Check the Break detection length parameter */
- assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
- /* LIN mode limited to 16-bit oversampling only */
- if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- return HAL_ERROR;
- }
- /* LIN mode limited to 8-bit data length */
- if(huart->Init.WordLength != UART_WORDLENGTH_8B)
- {
- return HAL_ERROR;
- }
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In LIN mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
- /* Set the USART LIN Break detection length. */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief Initialize the multiprocessor mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart: UART handle.
- * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod: specifies the UART wakeup method.
- * This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
- * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
- * @note If the user resorts to idle line detection wake up, the Address parameter
- * is useless and ignored by the initialization function.
- * @note If the user resorts to address mark wake up, the address length detection
- * is configured by default to 4 bits only. For the UART to be able to
- * manage 6-, 7- or 8-bit long addresses detection, the API
- * HAL_MultiProcessorEx_AddressLength_Set() must be called after
- * HAL_MultiProcessor_Init().
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the wake up method parameter */
- assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In multiprocessor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
- {
- /* If address mark wake up method is chosen, set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
- }
-
- /* Set the wake up method by setting the WAKE bit in the CR1 register */
- MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief DeInitialize the UART peripheral.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- huart->Instance->CR1 = 0x0U;
- huart->Instance->CR2 = 0x0U;
- huart->Instance->CR3 = 0x0U;
-
- /* DeInit the low level hardware */
- HAL_UART_MspDeInit(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the UART MSP.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the UART MSP.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the UART asynchronous
- and Half duplex data transfers.
-
- (#) There are two mode of transfer:
- (+) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (+) Non-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) Blocking mode API's are :
- (+) HAL_UART_Transmit()
- (+) HAL_UART_Receive()
-
- (#) Non-Blocking mode API's with Interrupt are :
- (+) HAL_UART_Transmit_IT()
- (+) HAL_UART_Receive_IT()
- (+) HAL_UART_IRQHandler()
-
- (#) Non-Blocking mode API's with DMA are :
- (+) HAL_UART_Transmit_DMA()
- (+) HAL_UART_Receive_DMA()
- (+) HAL_UART_DMAPause()
- (+) HAL_UART_DMAResume()
- (+) HAL_UART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (+) HAL_UART_TxHalfCpltCallback()
- (+) HAL_UART_TxCpltCallback()
- (+) HAL_UART_RxHalfCpltCallback()
- (+) HAL_UART_RxCpltCallback()
- (+) HAL_UART_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_UART_Abort()
- (+) HAL_UART_AbortTransmit()
- (+) HAL_UART_AbortReceive()
- (+) HAL_UART_Abort_IT()
- (+) HAL_UART_AbortTransmit_IT()
- (+) HAL_UART_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_UART_AbortCpltCallback()
- (+) HAL_UART_AbortTransmitCpltCallback()
- (+) HAL_UART_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-
- -@- In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param huart: UART handle.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
- while(huart->TxXferCount > 0U)
- {
- huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2U;
- }
- else
- {
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
- }
- }
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0;
-
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- uhMask = huart->Mask;
-
- /* as long as data have to be received */
- while(huart->RxXferCount > 0U)
- {
- huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2U;
- }
- else
- {
- *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
- */
- if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART Parity Error interupt and RX FIFO Threshold interrupt
- (if FIFO mode is enabled) or Data Register Not Empty interrupt
- (if FIFO mode is disabled).
- */
- if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the UART transmit DMA channel */
- HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the UART DMA Tx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- /* Enable the UART DMA Tx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART DMA Rx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
- HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
-
- /* Stop UART DMA Tx request if ongoing */
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
- {
- HAL_DMA_Abort(huart->hdmatx);
- }
-
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- HAL_DMA_Abort(huart->hdmarx);
- }
-
- UART_EndRxTransfer(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
- /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
- /* Disable TCIE, TXEIE and TXFTIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE | USART_CR1_TXEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
- /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(huart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
- }
- else
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(huart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
- }
- else
- {
- huart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
- {
- /* UART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
- {
- /* UART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- huart->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE | USART_CR1_TXEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
- huart->hdmatx->XferAbortCallback(huart->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
- /* Disable ERR (Frame error, noise error, overrun error) interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle UART interrupt request.
- * @param huart: UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET)
- && ( ((cr1its & USART_CR1_RXNEIE) != RESET)
- || ((cr3its & USART_CR3_RXFTIE) != RESET)) )
- {
- UART_Receive_IT(huart);
- return;
- }
- }
-
- /* If some errors occur */
- if( (errorflags != RESET)
- && ( ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if( ((isrflags & USART_ISR_ORE) != RESET)
- &&( ((cr1its & USART_CR1_RXNEIE) != RESET) ||
- ((cr3its & USART_CR3_RXFTIE) != RESET) ||
- ((cr3its & USART_CR3_EIE) != RESET)) )
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET)
- && ( ((cr1its & USART_CR1_RXNEIE) != RESET)
- || ((cr3its & USART_CR3_RXFTIE) != RESET)) )
- {
- UART_Receive_IT(huart);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_UART_ErrorCallback(huart);
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
- if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
- /* Set the UART state ready to be able to start again the process */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- HAL_UARTEx_WakeupCallback(huart);
- return;
- }
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET)
- && ( ((cr1its & USART_CR1_TXEIE) != RESET)
- || ((cr3its & USART_CR3_TXFTIE) != RESET)) )
- {
- UART_Transmit_IT(huart);
- return;
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- UART_EndTransmit_IT(huart);
- return;
- }
-
- /* UART TX FIFO Empty -----------------------------------------------------*/
- if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET))
- {
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXFEIE);
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART error callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Receive Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the UART.
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
- (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
- (+) UART_SetConfig() API configures the UART peripheral
- (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
- (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
- (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
- (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
- (+) HAL_LIN_SendBreak() API transmits the break characters
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable UART in mute mode (does not mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Enable USART mute mode by setting the MME bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
- * as it may not have been in mute mode at this very moment).
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable USART mute mode by clearing the MME bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Enter UART mute mode (means UART actually enters mute mode).
- * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
- * @param huart: UART handle.
- * @retval None
- */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
- __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-/**
- * @brief Enable the UART transmitter and disable the UART receiver.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the UART receiver and disable the UART transmitter.
- * @param huart: UART handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
- huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Transmit break characters.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Send break characters */
- SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief UART Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Return the UART handle state.
- (+) Return the UART handle error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the UART handle state.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval HAL state
- */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = huart->gState;
- temp2 = huart->RxState;
-
- return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the UART handle error code.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval UART Error Code
-*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
- return huart->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-/**
- * @brief Configure the UART peripheral.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- uint32_t tmpreg = 0x00000000U;
- UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
- HAL_StatusTypeDef ret = HAL_OK;
- PLL2_ClocksTypeDef pll2_clocks;
- PLL3_ClocksTypeDef pll3_clocks;
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- if(UART_INSTANCE_LOWPOWER(huart))
- {
- assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
- }
- else
- {
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
- }
-
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
- assert_param(IS_UART_PRESCALER(huart->Init.Prescaler));
- assert_param(IS_UART_FIFO_MODE_STATE(huart->Init.FIFOMode));
- if (huart->Init.FIFOMode == UART_FIFOMODE_ENABLE)
- {
- assert_param(IS_UART_TXFIFO_THRESHOLD(huart->Init.TXFIFOThreshold));
- assert_param(IS_UART_RXFIFO_THRESHOLD(huart->Init.RXFIFOThreshold));
- }
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- tmpreg |= (uint32_t)huart->Init.FIFOMode;
- MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART)
- * - set TXFTCFG bit according to husart->Init.TXFIFOThreshold value
- * - set RXFTCFG bit according to husart->Init.RXFIFOThreshold value */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
-
- if (!(UART_INSTANCE_LOWPOWER(huart)))
- {
- tmpreg |= huart->Init.OneBitSampling;
- }
-
- if (huart->Init.FIFOMode == UART_FIFOMODE_ENABLE)
- {
- tmpreg |= ((uint32_t)huart->Init.TXFIFOThreshold | (uint32_t)huart->Init.RXFIFOThreshold);
- }
-
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
-
-/*-------------------------- USART PRESC Configuration -----------------------*/
- /* Configure
- * - UART Clock Prescaler : set PRESCALER according to huart->Init.Prescaler value */
- MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.Prescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check LPUART instance */
- if(UART_INSTANCE_LOWPOWER(huart))
- {
- /* Retrieve frequency clock */
- tmpreg = 0U;
-
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_D3PCLK1:
- tmpreg = HAL_RCCEx_GetD3PCLK1Freq();
- break;
- case UART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- tmpreg = pll2_clocks.PLL2_Q_Frequency;
- break;
- case UART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- tmpreg = pll3_clocks.PLL3_Q_Frequency;
- break;
- case UART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- tmpreg = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
- }
- else
- {
- tmpreg = (uint32_t) HSI_VALUE;
- }
- break;
- case UART_CLOCKSOURCE_CSI:
- tmpreg =(uint32_t) CSI_VALUE;
- break;
- case UART_CLOCKSOURCE_LSE:
- tmpreg = (uint32_t) LSE_VALUE;
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- /* if proper clock source reported */
- if (tmpreg != 0U)
- {
- /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
- if ( (tmpreg < (3 * huart->Init.BaudRate) ) ||
- (tmpreg > (4096 * huart->Init.BaudRate) ))
- {
- ret = HAL_ERROR;
- }
- else
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_D3PCLK1:
- tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCCEx_GetD3PCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- tmpreg = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- tmpreg = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- tmpreg = (uint32_t)(UART_DIV_LPUART((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
- }
- else
- {
- tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- }
- break;
- case UART_CLOCKSOURCE_CSI:
- tmpreg = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_LSE:
- tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX))
- {
- huart->Instance->BRR = tmpreg;
- }
- else
- {
- ret = HAL_ERROR;
- }
- } /* if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */
- } /* if (tmpreg != 0) */
- }
- /* Check UART Over Sampling to set Baud Rate Register */
- else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_D2PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_D2PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
- }
- else
- {
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- }
- break;
- case UART_CLOCKSOURCE_CSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- }
- else
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_D2PCLK1:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_D2PCLK2:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), huart->Init.BaudRate, huart->Init.Prescaler));
- }
- else
- {
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- }
- break;
- case UART_CLOCKSOURCE_CSI:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.Prescaler));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
- }
-
- return ret;
-}
-
-/**
- * @brief Configure the UART peripheral advanced features.
- * @param huart: UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- /* set auto Baudrate detection parameters if detection is enabled */
- if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- }
- }
-
- /* if required, configure MSB first on communication line */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- }
-}
-
-/**
- * @brief Check the UART Idle State.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle UART Communication Timeout.
- * @param huart: UART handle.
- * @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
- * @param huart: UART handle.
- * @retval None
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart: UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-}
-
-
-/**
- * @brief DMA UART transmit process complete callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- huart->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else
- {
- HAL_UART_TxCpltCallback(huart);
- }
-
-}
-
-/**
- * @brief DMA UART transmit process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process complete callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- huart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- }
-
- HAL_UART_RxCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- HAL_UART_RxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART communication error callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* if DMA error is FIFO error ignore it */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
- {
- /* Stop UART DMA Tx request if ongoing */
- if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
- {
- huart->TxXferCount = 0U;
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
- {
- huart->RxXferCount = 0U;
- UART_EndRxTransfer(huart);
- }
-
- huart->ErrorCode |= HAL_UART_ERROR_DMA;
- HAL_UART_ErrorCallback(huart);
- }
-}
-
-/**
- * @brief DMA UART communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
-
- HAL_UART_ErrorCallback(huart);
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmarx != NULL)
- {
- if(huart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmatx != NULL)
- {
- if(huart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart: UART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- if(huart->TxXferCount == 0U)
- {
- /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
- */
- if (READ_BIT(huart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
- }
-
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- huart->pTxBuffPtr += 2U;
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
- huart->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart: UART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(uhdata & uhMask);
- huart->pRxBuffPtr +=2;
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
- }
-
- if(--huart->RxXferCount == 0U)
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- HAL_UART_RxCpltCallback(huart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
deleted file mode 100644
index 6e9efff..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_uart_ex.c
- * @author MCD Application Team
- * @brief Extended UART HAL module driver.
- * This file provides firmware functions to manage the following extended
- * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- ==============================================================================
- ##### UART peripheral extended features #####
- ==============================================================================
-
- (#) Declare a UART_HandleTypeDef handle structure.
-
- (#) For the UART RS485 Driver Enable mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UARTEx UARTEx
- * @brief UART Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
- * @{
- */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
- * @{
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Extended Initialization and Configuration Functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
- procedures (details for the procedures are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible UART formats are listed in the
- following table.
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the RS485 Driver enable feature according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle.
- * @param Polarity: select the driver enable polarity.
- * This parameter can be one of the following values:
- * @arg UART_DE_POLARITY_HIGH: DE signal is active high
- * @arg UART_DE_POLARITY_LOW: DE signal is active low
- * @param AssertionTime: Driver Enable assertion time:
- * 5-bit value defining the time between the activation of the DE (Driver Enable)
- * signal and the beginning of the start bit. It is expressed in sample time
- * units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime: Driver Enable deassertion time:
- * 5-bit value defining the time between the end of the last stop bit, in a
- * transmitted message, and the de-activation of the DE (Driver Enable) signal.
- * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
- * oversampling rate).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
-{
- uint32_t temp = 0x0U;
-
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the Driver Enable UART instance */
- assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
- /* Check the Driver Enable polarity */
- assert_param(IS_UART_DE_POLARITY(Polarity));
-
- /* Check the Driver Enable assertion time */
- assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
- /* Check the Driver Enable deassertion time */
- assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
- /* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
- /* Set the Driver Enable assertion and deassertion times */
- temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides the following functions:
- (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
- (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
- (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
- detection length to more than 4 bits for multiprocessor address mark wake up.
- (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
- trigger: address match, Start Bit detection or RXNE bit status.
- (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
- (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
- (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
-
-
-@endverbatim
- * @{
- */
-
-
-
-
-/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection;
- * this API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long).
- * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
- * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
- * @param huart: UART handle.
- * @param AddressLength: this parameter can be one of the following values:
- * @arg UART_ADDRESS_DETECT_4B: 4-bit long address
- * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the address length parameter */
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief Set Wakeup from Stop mode interrupt flag selection.
- * @param huart: UART handle.
- * @param WakeUpSelection: address match, Start Bit detection, RXNE bit status
- * or RX/TX FIFO related event.
- * This parameter can be one of the following values:
- * @arg @ref UART_WAKEUP_ON_ADDRESS
- * @arg @ref UART_WAKEUP_ON_STARTBIT
- * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
- * @arg @ref UART_WAKEUP_ON_RXFIFO_THRESHOLD
- * @arg @ref UART_WAKEUP_ON_RXFIFO_FULL
- * @arg @ref UART_WAKEUP_ON_TXFIFO_THRESHOLD
- * @arg @ref UART_WAKEUP_ON_TXFIFO_EMPTY
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = 0U;
-
- /* check the wake-up from stop mode UART instance */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
- /* check the wake-up selection parameter */
- assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- switch (WakeUpSelection.WakeUpEvent)
- {
- case UART_WAKEUP_ON_ADDRESS:
- case UART_WAKEUP_ON_STARTBIT:
- case UART_WAKEUP_ON_READDATA_NONEMPTY:
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the wake-up selection scheme */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
-
- if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
- {
- UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
- }
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- }
- break;
-
- case UART_WAKEUP_ON_RXFIFO_THRESHOLD:
- /* Enable RXFT interrupt */
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- huart->gState = HAL_UART_STATE_READY;
- break;
-
- case UART_WAKEUP_ON_RXFIFO_FULL:
- /* Enable RXFF interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXFFIE);
- huart->gState = HAL_UART_STATE_READY;
- break;
-
- case UART_WAKEUP_ON_TXFIFO_THRESHOLD:
- /* Enable TXFT interrupt */
- SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- huart->gState = HAL_UART_STATE_READY;
- break;
-
- case UART_WAKEUP_ON_TXFIFO_EMPTY:
- /* Enable TXFE interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXFEIE);
- huart->gState = HAL_UART_STATE_READY;
- break;
-
- default:
- break;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-
-/**
- * @brief Enable UART Stop Mode.
- * @note The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Set UESM bit */
- SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable UART Stop Mode.
- * @param huart: UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear UESM bit */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief UART wakeup from Stop mode callback.
- * @param huart: UART handle.
- * @retval None
- */
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_WakeupCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart: UART handle.
- * @param WakeUpSelection: UART wake up from stop mode parameters.
- * @retval None
- */
-static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
- /* Set the USART address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
-
- /* Set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
deleted file mode 100644
index f8b0b4f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
+++ /dev/null
@@ -1,2430 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_usart.c
- * @author MCD Application Team
- * @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
- * Peripheral (USART).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The USART HAL driver can be used as follows:
-
- (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure these USART pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) USART interrupts handling:
- -@@- The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
- (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
-
- (#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_USART_MspInit(&husart) API.
-
- [..]
- (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
- HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
- HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
- * @{
- */
-
-#ifdef HAL_USART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
- * @{
- */
-#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
-#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8|\
- USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL |USART_CR2_DIS_NSS|\
- USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP|\
- USART_CR2_SLVEN)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by USART_SetConfig API */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions
- * @{
- */
-static void USART_EndTransfer(USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
-
- [..]
- The HAL_USART_Init() function follows the USART synchronous configuration
- procedure (details for the procedure are available in reference manual).
-
-@endverbatim
-
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible USART formats are listed in the
- following table.
-
- Table 1. USART frame format.
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | USART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
- * @{
- */
-
-/**
- * @brief Initialize the USART mode according to the specified
- * parameters in the USART_InitTypeDef and initialize the associated handle.
- * @param husart: USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- if(husart->State == HAL_USART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- husart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_USART_MspInit(husart);
- }
-
- husart->State = HAL_USART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_USART_DISABLE(husart);
-
- /* Set the Usart Communication parameters */
- if (USART_SetConfig(husart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* In Synchronous Slave mode, the following bits must be kept cleared:
- - CLKEN bits in the USART_CR2 register, */
- if (husart->Init.SlaveMode)
- {
- CLEAR_BIT(husart->Instance->CR2, USART_CR2_CLKEN);
- }
-
- /* Enable the Peripheral */
- __HAL_USART_ENABLE(husart);
-
- /* TEACK and/or REACK to check before moving husart->State to Ready */
- return (USART_CheckIdleState(husart));
-}
-
-/**
- * @brief DeInitialize the USART peripheral.
- * @param husart: USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- husart->State = HAL_USART_STATE_BUSY;
-
- husart->Instance->CR1 = 0x0U;
- husart->Instance->CR2 = 0x0U;
- husart->Instance->CR3 = 0x0U;
-
- /* DeInit the low level hardware */
- HAL_USART_MspDeInit(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the USART MSP.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the USART MSP.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
- data transfers.
-
- [..] The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) Blocking mode API's are :
- (++) HAL_USART_Transmit()in simplex mode
- (++) HAL_USART_Receive() in full duplex receive only
- (++) HAL_USART_TransmitReceive() in full duplex mode
-
- (#) Non-Blocking mode API's with Interrupt are :
- (++) HAL_USART_Transmit_IT()in simplex mode
- (++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
- (++) HAL_USART_IRQHandler()
-
- (#) No-Blocking mode API's with DMA are :
- (++) HAL_USART_Transmit_DMA()in simplex mode
- (++) HAL_USART_Receive_DMA() in full duplex receive only
- (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
- (++) HAL_USART_DMAPause()
- (++) HAL_USART_DMAResume()
- (++) HAL_USART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (++) HAL_USART_TxCpltCallback()
- (++) HAL_USART_RxCpltCallback()
- (++) HAL_USART_TxHalfCpltCallback()
- (++) HAL_USART_RxHalfCpltCallback()
- (++) HAL_USART_ErrorCallback()
- (++) HAL_USART_TxRxCpltCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_USART_Abort()
- (+) HAL_USART_Abort_IT()
-
- (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
- (+) HAL_USART_AbortCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Simplex send an amount of data in blocking mode.
- * @param husart: USART handle.
- * @param pTxData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- /* Check the remaining data to be sent */
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
- }
- }
-
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart: USART handle.
- * @param pRxData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
- uhMask = husart->Mask;
-
- /* as long as data have to be received */
- while(husart->RxXferCount > 0U)
- {
- husart->RxXferCount--;
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
- {
- /* Wait until TC flag is set to send dummy byte in order to generate the
- * clock for the slave to send data.
- * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
- * can be written for all the cases. */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
- }
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
- }
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be sent (same amount to be received).
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
- husart->RxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
- uhMask = husart->Mask;
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_ENABLE)
- {
- husart->TxXferCount--;
-
- /* Wait until TXE flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
- }
- }
-
- /* Check the remain data to be sent */
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- husart->RxXferCount--;
-
- /* Wait until TXE flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
- }
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
- }
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_ENABLE)
- {
- husart->RxXferCount--;
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
- }
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of TxRx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* The USART Error Interrupts: (Frame error, noise error, overrun error)
- are not managed by the USART Transmit Process to avoid the overrun interrupt
- when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
- to benefit for the frame error and noise interrupts the usart mode should be
- configured only for transmit "USART_MODE_TX" */
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
- */
- if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart: USART handle.
- * @param pRxData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
-
- USART_MASK_COMPUTATION(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the USART Parity Error interupt and RX FIFO Threshold interrupt
- (if FIFO mode is enabled) or Data Register Not Empty interrupt
- (if FIFO mode is disabled).
- */
- if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- }
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
- {
- /* Send dummy byte in order to generate the clock for the Slave to send the next data */
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
- }
- else
- {
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
- }
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be sent (same amount to be received).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the USART Parity Error interupt and RX/TX FIFO Threshold interrupts
- (if FIFO mode is enabled) or Receive Data Register Not Empty and Transmit
- Data Register Empty Interrupts (if FIFO mode is disabled).
- */
- if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE | USART_CR3_TXFTIE);
- }
- else
- {
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE | USART_CR1_TXEIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Set the USART DMA transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param husart: USART handle.
- * @param pRxData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @note When the USART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pRxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
- {
- /* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
- this mode isn't a simplex receive mode but a full-duplex receive mode */
- /* Set the USART DMA Tx Complete and Error callback to Null */
- husart->hdmatx->XferErrorCallback = NULL;
- husart->hdmatx->XferHalfCpltCallback = NULL;
- husart->hdmatx->XferCpltCallback = NULL;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
- {
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be received/sent.
- * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Tx transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the USART DMA Tx transfer error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param husart: USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
- {
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the USART DMA Rx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param husart: USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Enable the USART DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the USART DMA Rx request before the DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the USART DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param husart: USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
- HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
-
- /* Disable the USART Tx/Rx DMA requests */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA tx channel */
- if(husart->hdmatx != NULL)
- {
- HAL_DMA_Abort(husart->hdmatx);
- }
- /* Abort the USART DMA rx channel */
- if(husart->hdmarx != NULL)
- {
- HAL_DMA_Abort(husart->hdmarx);
- }
-
- USART_EndTransfer(husart);
- husart->State = HAL_USART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable USART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
-{
- /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
- /* Disable the USART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmatx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmatx);
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable USART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(husart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
- }
- else
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(husart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
- }
- else
- {
- husart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at USART level */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmatx != NULL)
- {
- /* USART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmarx != NULL)
- {
- /* USART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- husart->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle USART interrupt request.
- * @param husart USART handle.
- * @retval None
- */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
- uint32_t isrflags = READ_REG(husart->Instance->ISR);
- uint32_t cr1its = READ_REG(husart->Instance->CR1);
- uint32_t cr3its = READ_REG(husart->Instance->CR3);
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
- if (errorflags == RESET)
- {
- /* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET)
- && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_RXFTIE) != RESET)))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
- }
-
- /* If some errors occur */
- if((errorflags != RESET)
- && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* USART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_PE;
- }
-
- /* USART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_FE;
- }
-
- /* USART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_NE;
- }
-
- /* USART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET)
- && (((cr1its & USART_CR1_RXNEIE) != RESET)
- || ((cr3its & USART_CR3_RXFTIE) != RESET)
- || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
-
- husart->ErrorCode |= HAL_USART_ERROR_ORE;
- }
-
- /* USART Under-Run interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_UDRCF);
- husart->ErrorCode |= HAL_USART_ERROR_UDR;
- }
-
- /* Call USART Error Call back function if need be --------------------------*/
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
- {
- /* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET)
- && (((cr1its & USART_CR1_RXNEIE) != RESET)
- || ((cr3its & USART_CR3_RXFTIE) != RESET)))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the USART state ready to be able to start again the process,
- Disable Interrupts, and disable DMA requests, if ongoing */
- USART_EndTransfer(husart);
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
-
- /* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
- {
- /* Set the USART Tx DMA Abort callback to NULL : no callback
- executed at end of DMA abort procedure */
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA TX */
- HAL_DMA_Abort_IT(husart->hdmatx);
- }
-
- /* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART Rx DMA Abort callback :
- will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
- husart->hdmarx->XferAbortCallback(husart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_USART_ErrorCallback(husart);
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
-
- /* USART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET)
- && (((cr1its & USART_CR1_TXEIE) != RESET)
- || ((cr3its & USART_CR3_TXFTIE) != RESET)))
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- USART_Transmit_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
-
- /* USART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- USART_EndTransmit_IT(husart);
- return;
- }
-
- /* USART TX FIFO Empty -----------------------------------------------------*/
- if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET))
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXFEIE);
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_RxHalfCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxRxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief USART error callback.
- * @param husart: USART handle.
- * @retval None
- */
-__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief USART Abort Complete callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief USART Peripheral State and Error functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Return the USART handle state
- (+) Return the USART handle error code
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Return the USART handle state.
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART handle state
- */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
- return husart->State;
-}
-
-/**
- * @brief Return the USART error code.
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART handle Error Code
- */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
- return husart->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
-
-/**
- * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
- * @param husart USART handle.
- * @retval None
- */
-static void USART_EndTransfer(USART_HandleTypeDef *husart)
-{
- /* Disable RXNE, PE, TXE, TC, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
- /* At end of process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-}
-
-/**
- * @brief DMA USART transmit process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- husart->TxXferCount = 0U;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the USART Transmit Complete Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
- }
- }
- /* DMA Circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- HAL_USART_TxCpltCallback(husart);
- }
- }
-}
-
-/**
- * @brief DMA USART transmit process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- HAL_USART_TxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART receive process complete callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if (hdma->Init.Mode != DMA_CIRCULAR)
- {
- husart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
- in USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* similarly, disable the DMA TX transfer that was started to provide the
- clock to the slave device */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- husart->State= HAL_USART_STATE_READY;
- }
- /* DMA circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- }
-
-}
-
-/**
- * @brief DMA USART receive process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- HAL_USART_RxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART communication error callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- husart->RxXferCount = 0U;
- husart->TxXferCount = 0U;
- USART_EndTransfer(husart);
-
- husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief DMA USART communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
- husart->RxXferCount = 0U;
- husart->TxXferCount = 0U;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief DMA USART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmarx != NULL)
- {
- if(husart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-
-/**
- * @brief DMA USART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
- husart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmatx != NULL)
- {
- if(husart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-
-/**
- * @brief Handle USART Communication Timeout.
- * @param husart: USART handle.
- * @param Flag: specifies the USART flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Tickstart: tick start value.
- * @param Timeout: timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the USART peripheral.
- * @param husart: USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
-{
- uint32_t tmpreg = 0x0U;
- USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
- PLL2_ClocksTypeDef pll2_clocks;
- PLL3_ClocksTypeDef pll3_clocks;
-
- /* Check the parameters */
- assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
- assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
- assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
- assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
- assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
- assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
- assert_param(IS_USART_PARITY(husart->Init.Parity));
- assert_param(IS_USART_MODE(husart->Init.Mode));
- assert_param(IS_USART_PRESCALER(husart->Init.Prescaler));
- assert_param(IS_USART_NSS(husart->Init.NSS));
- assert_param(IS_USART_SLAVEMODE(husart->Init.SlaveMode));
- assert_param(IS_USART_FIFO_MODE_STATE(husart->Init.FIFOMode));
- if (husart->Init.FIFOMode == USART_FIFOMODE_ENABLE)
- {
- assert_param(IS_USART_TXFIFO_THRESHOLD(husart->Init.TXFIFOThreshold));
- assert_param(IS_USART_RXFIFO_THRESHOLD(husart->Init.RXFIFOThreshold));
- }
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity and Mode:
- * set the M bits according to husart->Init.WordLength value
- * set PCE and PS bits according to husart->Init.Parity value
- * set TE and RE bits according to husart->Init.Mode value
- * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
- tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
- tmpreg |= (uint32_t)husart->Init.FIFOMode;
- MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*---------------------------- USART CR2 Configuration ---------------------*/
- /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
- * set CPOL bit according to husart->Init.CLKPolarity value
- * set CPHA bit according to husart->Init.CLKPhase value
- * set DIS_NSS bit according to husart->Init.NSS value
- * set LBCL bit according to husart->Init.CLKLastBit value
- * set STOP[13:12] bits according to husart->Init.StopBits value
- * set SlaveMode bit according to husart->Init.SlaveMode value */
- tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
- tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase | (uint32_t)husart->Init.NSS);
- tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits | (uint32_t)husart->Init.SlaveMode);
- MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Clear and configure the TXFTCFG & RXFTCFG bits:
- * set TXFTCFG bit according to husart->Init.TXFIFOThreshold value
- * set RXFTCFG bit according to husart->Init.RXFIFOThreshold value */
- if (husart->Init.FIFOMode == USART_FIFOMODE_ENABLE)
- {
- tmpreg = ((uint32_t)husart->Init.TXFIFOThreshold | (uint32_t)husart->Init.RXFIFOThreshold );
- MODIFY_REG(husart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- }
-
- /*-------------------------- USART PRESC Configuration -----------------------*/
- /* Configure
- * - USART Clock Prescaler : set PRESCALER according to husart->Init.Prescaler value */
- MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.Prescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
- USART_GETCLOCKSOURCE(husart, clocksource);
- switch (clocksource)
- {
- case USART_CLOCKSOURCE_D2PCLK1:
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_D2PCLK2:
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)), husart->Init.BaudRate, husart->Init.Prescaler));
- }
- else
- {
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
- }
- break;
- case USART_CLOCKSOURCE_CSI:
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.Prescaler));
- break;
- case USART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- husart->Instance->BRR = brrtemp;
-
- return ret;
-}
-
-/**
- * @brief Check the USART Idle State.
- * @param husart: USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the USART ErrorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the USART state*/
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Simplex send an amount of data in non-blocking mode.
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Transmit_IT().
- * @note The USART errors are not managed to avoid the overrun error.
- * @param husart: USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
-
- if(husart->TxXferCount == 0U)
- {
- /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
- */
- if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
- }
-
- /* Enable the USART Transmit Complete Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
-
- husart->TxXferCount--;
-
- return HAL_OK;
- }
-}
-
-
-/**
- * @brief Wraps up transmission in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
- /* Disable the USART Transmit Complete Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Tx process is ended, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Simplex receive an amount of data in non-blocking mode.
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Receive_IT().
- * @param husart: USART handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
- uint16_t uhMask = husart->Mask;
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
-
- if (husart->Init.SlaveMode == USART_SLAVEMODE_DISABLE)
- {
- /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
- }
-
- if(--husart->RxXferCount == 0U)
- {
- /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_RxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
- * @param husart: USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
- uint16_t uhMask = husart->Mask;
-
- if(husart->TxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
- }
- husart->TxXferCount--;
-
- /* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
- {
- /* Disable the TX FIFO threshold interrupt (if FIFO mode is enabled) or
- Transmit Data Register Empty interrupt (if FIFO mode is Disabled) */
- if (READ_BIT(husart->Instance->CR1, USART_CR1_FIFOEN) != RESET)
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
- }
- else
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
- }
- }
- }
- }
-
- if(husart->RxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- husart->RxXferCount--;
- }
- }
-
- /* Check the latest data received */
- if(husart->RxXferCount == 0U)
- {
- /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxRxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c
deleted file mode 100644
index 5d6b303..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_wwdg.c
- * @author MCD Application Team
- * @brief WWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and Configuration function
- * + IO operation functions
- @verbatim
- ==============================================================================
- ##### WWDG specific features #####
- ==============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (T[6;0] downcounter)
- before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
-
- (+) An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- (+) Once enabled the WWDG cannot be disabled except by a system reset.
-
- (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
- occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
-
- (+) The WWDG downcounter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
-
- (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
- where T[5;0] are the lowest 6 bits of downcounter.
-
- (+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
- (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
-
- (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
- HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
-
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
-
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-/** @defgroup WWDG WWDG
- * @brief WWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and start the WWDG according to the specified parameters
- in the WWDG_InitTypeDef of associated handle.
- (+) Initialize the WWDG MSP.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the WWDG according to the specified.
- * parameters in the WWDG_InitTypeDef of associated handle.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check the WWDG handle allocation */
- if(hwwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
- assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
- assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
- assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
- assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
-
- /* Init the low level hardware */
- HAL_WWDG_MspInit(hwwdg);
-
- /* Set WWDG Counter */
- WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
-
- /* Set WWDG Prescaler and Window */
- WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the WWDG MSP.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @note When rewriting this function in user file, mechanism may be added
- * to avoid multiple initialize when HAL_WWDG_Init function is called
- * again to change parameters.
- * @retval None
- */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Refresh the WWDG.
- (+) Handle WWDG interrupt request and associated function callback.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Refresh the WWDG.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
-{
- /* Write to WWDG CR the WWDG Counter value to refresh with */
- WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handle WWDG interrupt request.
- * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
- * or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
- * EWIMode set to WWDG_EWI_ENABLE.
- * When the downcounter reaches the value 0x40, and EWI interrupt is
- * generated and the corresponding Interrupt Service Routine (ISR) can
- * be used to trigger specific actions (such as communications or data
- * logging), before resetting the device.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
- {
- /* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
- {
- /* Clear the WWDG Early Wakeup flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Early Wakeup callback */
- HAL_WWDG_EarlyWakeupCallback(hwwdg);
- }
- }
-}
-
-
-/**
- * @brief WWDG Early Wakeup callback.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c
deleted file mode 100644
index fd0fb9b..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_delayblock.c
- * @author MCD Application Team
- * @brief DelayBlock Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Delay Block peripheral:
- * + input clock frequency range 25MHz to 208MHz
- * + up to 12 oversampling phases
- *
- @verbatim
- ==============================================================================
- ##### DelayBlock peripheral features #####
- ==============================================================================
- [..] The Delay block is used to generate an Output clock which is de-phased from the Input
- clock. The phase of the Output clock is programmed by FW. The Output clock is then used
- to clock the receive data in i.e. a SDMMC or QSPI interface.
- The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
- and recenter the Output clock phase to the receive data.
-
- [..] The Delay Block features include the following:
- (+) Input clock frequency range 25MHz to 208MHz.
- (+) Up to 12 oversampling phases.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a considered as a driver of service for external devices drivers
- that interfaces with the DELAY peripheral.
- The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
- and configure the Output clock phase.
- The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DELAYBLOCK_LL DELAYBLOCK_LL
- * @brief Low layer module for Delay Block
- * @{
- */
-
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DelayBlock_LL_Exported_Functions Delay Block Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enable the Delay Block instance.
- * @param DLYBx: Pointer to DLYB instance.
- * @retval HAL status
- */
-HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx)
-{
- uint32_t i=0,N=0, lng=0, tuningOn = 1;
-
- assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
-
- DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN;
-
- while((tuningOn != 0) && (i < DLYB_MAX_UNIT))
- {
-
- DLYBx->CFGR = 12 | (i << 8);
- HAL_Delay(1);
- if(((DLYBx->CFGR & DLYB_CFGR_LNGF) != 0)
- && ((DLYBx->CFGR & DLYB_CFGR_LNG) != 0)
- && ((DLYBx->CFGR & DLYB_CFGR_LNG) != (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)))
- {
- tuningOn = 0;
- }
- i++;
-
- }
-
- if(DLYB_MAX_UNIT != i)
- {
-
- lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16;
- N = 10;
- while((N>0) && ((lng >> N) == 0))
- {
- N--;
- }
- if(0 != N)
- {
- MODIFY_REG(DLYBx->CFGR, DLYB_CFGR_SEL, ((N/2)+1));
-
- /* Disable Selection phase */
- DLYBx->CR = DLYB_CR_DEN;
- return HAL_OK;
- }
- }
-
- /* Disable DLYB */
- DelayBlock_Disable(DLYBx);
- return HAL_ERROR;
-
-}
-
-/**
- * @brief Disable the Delay Block instance.
- * @param DLYBx: Pointer to DLYB instance.
- * @retval HAL status
- */
-HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx)
-{
- /* Disable DLYB */
- DLYBx->CR = 0;
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* (HAL_SD_MODULE_ENABLED) & (HAL_QSPI_MODULE_ENABLED)*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
deleted file mode 100644
index 709b092..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
+++ /dev/null
@@ -1,1097 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_fmc.c
- * @author MCD Application Team
- * @brief FMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### FMC peripheral features #####
- ==============================================================================
- [..] The Flexible memory controller (FMC) includes three memory controllers:
- (+) The NOR/PSRAM memory controller
- (+) The NAND memory controller
- (+) The Synchronous DRAM (SDRAM) controller
-
- [..] The FMC functional block makes the interface with synchronous and asynchronous static
- memories and SDRAM memories. Its main purposes are:
- (+) to translate AHB transactions into the appropriate external device protocol
- (+) to meet the access time requirements of the external memory devices
-
- [..] All external memories share the addresses, data and control signals with the controller.
- Each external device is accessed by means of a unique Chip Select. The FMC performs
- only one access at a time to an external device.
- The main features of the FMC controller are the following:
- (+) Interface with static-memory mapped devices including:
- (++) Static random access memory (SRAM)
- (++) Read-only memory (ROM)
- (++) NOR Flash memory/OneNAND Flash memory
- (++) PSRAM (4 memory banks)
- (++) NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
- (+) Interface with synchronous DRAM (SDRAM) memories
- (+) Independent Chip Select control for each memory bank
- (+) Independent configuration for each memory bank
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup FMC_LL FMC Low Layer
- * @brief FMC driver modules
- * @{
- */
-
-#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
- * @brief NORSRAM Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NORSRAM device driver #####
- ==============================================================================
-
- [..]
- This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
- to run the NORSRAM external devices.
-
- (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
- (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
- (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
- (+) FMC NORSRAM bank extended timing configuration using the function
- FMC_NORSRAM_Extended_Timing_Init()
- (+) FMC NORSRAM bank enable/disable write operation using the functions
- FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
-
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC NORSRAM interface
- (+) De-initialize the FMC NORSRAM interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the FMC_NORSRAM device according to the specified
- * control parameters in the FMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
- assert_param(IS_FMC_MUX(Init->DataAddressMux));
- assert_param(IS_FMC_MEMORY(Init->MemoryType));
- assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
- assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
- assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
- assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
- assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
- assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
- assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
- assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
- assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
- assert_param(IS_FMC_PAGESIZE(Init->PageSize));
-
- /* Get the BTCR register value */
- tmpr = Device->BTCR[Init->NSBank];
-
- /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
- WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
- tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
- FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
- FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \
- FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
- FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
-
- /* Set NORSRAM device control parameters */
- tmpr |= (uint32_t)(Init->DataAddressMux |\
- Init->MemoryType |\
- Init->MemoryDataWidth |\
- Init->BurstAccessMode |\
- Init->WaitSignalPolarity |\
- Init->WaitSignalActive |\
- Init->WriteOperation |\
- Init->WaitSignal |\
- Init->ExtendedMode |\
- Init->AsynchronousWait |\
- Init->WriteBurst |\
- Init->ContinuousClock |\
- Init->PageSize |\
- Init->WriteFifo);
-
- if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
- {
- tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
- }
-
- Device->BTCR[Init->NSBank] = tmpr;
-
- /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
- if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
- {
- Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
- }
- if(Init->NSBank != FMC_NORSRAM_BANK1)
- {
- Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitialize the FMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Disable the FMC_NORSRAM device */
- __FMC_NORSRAM_DISABLE(Device, Bank);
-
- /* De-initialize the FMC_NORSRAM device */
- /* FMC_NORSRAM_BANK1 */
- if(Bank == FMC_NORSRAM_BANK1)
- {
- Device->BTCR[Bank] = 0x000030DB;
- }
- /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
- else
- {
- Device->BTCR[Bank] = 0x000030D2;
- }
-
- Device->BTCR[Bank + 1] = 0x0FFFFFFF;
- ExDevice->BWTR[Bank] = 0x0FFFFFFF;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the FMC_NORSRAM Timing according to the specified
- * parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Get the BTCR register value */
- tmpr = Device->BTCR[Bank + 1];
-
- /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
- tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
- FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
- FMC_BTR1_ACCMOD));
-
- /* Set FMC_NORSRAM device timing parameters */
- tmpr |= (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode)
- );
-
- Device->BTCR[Bank + 1] = tmpr;
-
- /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
- if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
- {
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
- tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
- Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
- * parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
-
- /* Set NORSRAM device timing register for write configuration, if extended mode is used */
- if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
- {
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Get the BWTR register value */
- tmpr = Device->BWTR[Bank];
-
- /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
- tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
- FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
-
- tmpr |= (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (Timing->AccessMode));
-
- Device->BWTR[Bank] = tmpr;
- }
- else
- {
- Device->BWTR[Bank] = 0x0FFFFFFF;
- }
-
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FMC_NORSRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FMC NORSRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Enable write operation */
- Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Disable write operation */
- Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
- * @brief NAND Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NAND device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FMC NAND banks in order
- to run the NAND external devices.
-
- (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
- (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
- (+) FMC NAND bank common space timing configuration using the function
- FMC_NAND_CommonSpace_Timing_Init()
- (+) FMC NAND bank attribute space timing configuration using the function
- FMC_NAND_AttributeSpace_Timing_Init()
- (+) FMC NAND bank enable/disable ECC correction feature using the functions
- FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
- (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC NAND interface
- (+) De-initialize the FMC NAND interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FMC_NAND device according to the specified
- * control parameters in the FMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Init->NandBank));
- assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
- assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
- assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
- assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
-
- /* Get the NAND bank 3 register value */
- tmpr = Device->PCR;
-
- /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
- tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
- FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
- FMC_PCR_TAR | FMC_PCR_ECCPS));
-
- /* Set NAND device control parameters */
- tmpr |= (uint32_t)(Init->Waitfeature |\
- Init->MemoryDataWidth |\
- Init->EccComputation |\
- Init->ECCPageSize |\
- ((Init->TCLRSetupTime) << 9) |\
- ((Init->TARSetupTime) << 13));
-
- /* NAND bank 3 registers configuration */
- Device->PCR = tmpr;
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Initializes the FMC_NAND Common space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Get the NAND bank 3 register value */
- tmpr = Device->PMEM;
-
- /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
- tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
- FMC_PMEM_MEMHIZ3));
- /* Set FMC_NAND device timing parameters */
- tmpr |= (uint32_t)(Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- ((Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
- /* NAND bank 3 registers configuration */
- Device->PMEM = tmpr;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Get the NAND bank 3 register value */
- tmpr = Device->PATT;
-
- /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
- tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
- FMC_PATT_ATTHIZ3));
- /* Set FMC_NAND device timing parameters */
- tmpr |= (uint32_t)(Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- ((Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24));
-
- /* NAND bank 3 registers configuration */
- Device->PATT = tmpr;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the FMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Disable the NAND Bank */
- __FMC_NAND_DISABLE(Device);
-
- /* Set the FMC_NAND_BANK3 registers to their reset values */
- Device->PCR = 0x00000018U;
- Device->SR = 0x00000040U;
- Device->PMEM = 0xFCFCFCFCU;
- Device->PATT = 0xFCFCFCFCU;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FMC_NAND_Group3 Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FMC_NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FMC NAND interface.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Enable ECC feature */
- Device->PCR |= FMC_PCR_ECCEN;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Disable ECC feature */
- Device->PCR &= ~FMC_PCR_ECCEN;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FIFO is empty */
- while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Get the ECCR register value */
- *ECCval = (uint32_t)Device->ECCR;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LL_SDRAM
- * @brief SDRAM Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use SDRAM device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FMC SDRAM banks in order
- to run the SDRAM external devices.
-
- (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
- (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
- (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
- (+) FMC SDRAM bank enable/disable write operation using the functions
- FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
- (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
-
-@endverbatim
- * @{
- */
-
-/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC SDRAM interface
- (+) De-initialize the FMC SDRAM interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FMC_SDRAM device according to the specified
- * control parameters in the FMC_SDRAM_InitTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Init: Pointer to SDRAM Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
-{
- uint32_t tmpr1 = 0;
- uint32_t tmpr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
- assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
- assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
- assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
- assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
- assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
- assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
- assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
- assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
-
- /* Set SDRAM bank configuration parameters */
- if (Init->SDBank != FMC_SDRAM_BANK2)
- {
- tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-
- /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
- tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
- FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
- FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
- tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
- Init->RowBitsNumber |\
- Init->MemoryDataWidth |\
- Init->InternalBankNumber |\
- Init->CASLatency |\
- Init->WriteProtection |\
- Init->SDClockPeriod |\
- Init->ReadBurst |\
- Init->ReadPipeDelay
- );
- Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
- }
- else /* FMC_Bank2_SDRAM */
- {
- tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-
- /* Clear SDCLK, RBURST, and RPIPE bits */
- tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
- tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
- Init->ReadBurst |\
- Init->ReadPipeDelay);
-
- tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
-
- /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
- tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
- FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
- FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
- tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
- Init->RowBitsNumber |\
- Init->MemoryDataWidth |\
- Init->InternalBankNumber |\
- Init->CASLatency |\
- Init->WriteProtection);
-
- Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
- Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FMC_SDRAM device timing according to the specified
- * parameters in the FMC_SDRAM_TimingTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Bank: SDRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmpr1 = 0;
- uint32_t tmpr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
- assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
- assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
- assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
- assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
- assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
- assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
- assert_param(IS_FMC_SDRAM_BANK(Bank));
-
- /* Set SDRAM device timing parameters */
- if (Bank != FMC_SDRAM_BANK2)
- {
- tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
-
- /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
- tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
- FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
- FMC_SDTR1_TRCD));
-
- tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
- (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
- (((Timing->SelfRefreshTime)-1) << 8) |\
- (((Timing->RowCycleDelay)-1) << 12) |\
- (((Timing->WriteRecoveryTime)-1) <<16) |\
- (((Timing->RPDelay)-1) << 20) |\
- (((Timing->RCDDelay)-1) << 24));
- Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
- }
- else /* FMC_Bank2_SDRAM */
- {
- tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
-
- /* Clear TRC and TRP bits */
- tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
-
- tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
- (((Timing->RPDelay)-1) << 20));
-
- tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
-
- /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
- tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
- FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
- FMC_SDTR1_TRCD));
-
- tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
- (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
- (((Timing->SelfRefreshTime)-1) << 8) |\
- (((Timing->WriteRecoveryTime)-1) <<16) |\
- (((Timing->RCDDelay)-1) << 24));
-
- Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
- Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the FMC_SDRAM peripheral
- * @param Device: Pointer to SDRAM device instance
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_SDRAM_BANK(Bank));
-
- /* De-initialize the SDRAM device */
- Device->SDCR[Bank] = 0x000002D0;
- Device->SDTR[Bank] = 0x0FFFFFFF;
- Device->SDCMR = 0x00000000;
- Device->SDRTR = 0x00000000;
- Device->SDSR = 0x00000000;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FMC_SDRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FMC SDRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically FMC_SDRAM write protection.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: SDRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_SDRAM_BANK(Bank));
-
- /* Enable write protection */
- Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_SDRAM write protection.
- * @param hsdram: FMC_SDRAM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_SDRAM_BANK(Bank));
-
- /* Disable write protection */
- Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Send Command to the FMC SDRAM bank
- * @param Device: Pointer to SDRAM device instance
- * @param Command: Pointer to SDRAM command structure
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Timeout: Timeout wait value
- * @retval HAL state
- */
-HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
-{
- __IO uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
- assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
- assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
-
- /* Set command register */
- tmpr = (uint32_t)((Command->CommandMode) |\
- (Command->CommandTarget) |\
- (((Command->AutoRefreshNumber)-1) << 5) |\
- ((Command->ModeRegisterDefinition) << 9)
- );
-
- Device->SDCMR = tmpr;
-
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Program the SDRAM Memory Refresh rate.
- * @param Device: Pointer to SDRAM device instance
- * @param RefreshRate: The SDRAM refresh rate value.
- * @retval HAL state
- */
-HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
-{
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
-
- /* Set the refresh rate in command register */
- Device->SDRTR |= (RefreshRate<<1);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param Device: Pointer to SDRAM device instance
- * @param AutoRefreshNumber: Specifies the auto Refresh number.
- * @retval HAL state
- */
-HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
-{
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
-
- /* Set the Auto-refresh number in command register */
- Device->SDCMR |= (AutoRefreshNumber << 5);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the indicated FMC SDRAM bank mode status.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: Defines the FMC SDRAM bank. This parameter can be
- * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
- * @retval The FMC SDRAM bank mode status, could be on of the following values:
- * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
- * FMC_SDRAM_POWER_DOWN_MODE.
- */
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_SDRAM_DEVICE(Device));
- assert_param(IS_FMC_SDRAM_BANK(Bank));
-
- /* Get the corresponding bank mode */
- if(Bank == FMC_SDRAM_BANK1)
- {
- tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
- }
- else
- {
- tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
- }
-
- /* Return the mode status */
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
deleted file mode 100644
index aaa783a..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
+++ /dev/null
@@ -1,1586 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_sdmmc.c
- * @author MCD Application Team
- * @brief SDMMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the SDMMC peripheral:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### SDMMC peripheral features #####
- ==============================================================================
- [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
- peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
- devices.
-
- [..] The SDMMC features include the following:
- (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support
- for three different databus modes: 1-bit (default), 4-bit and 8-bit.
- (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility).
- (+) Full compliance with SD memory card specifications version 4.1.
- (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
- UHS-II mode not supported).
- (+) Full compliance with SDIO card specification version 4.0. Card support
- for two different databus modes: 1-bit (default) and 4-bit.
- (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
- UHS-II mode not supported).
- (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed).
- (+) Data and command output enable signals to control external bidirectional drivers
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a considered as a driver of service for external devices drivers
- that interfaces with the SDMMC peripheral.
- According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
- is used in the device's driver to perform SDMMC operations and functionalities.
-
- This driver is almost transparent for the final user, it is only used to implement other
- functionalities of the external device.
-
- [..]
- (+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R.
- Before start working with SDMMC peripheral make sure that the PLL is well configured.
- The SDMMC peripheral uses two clock signals:
- (++) PLL1_Q bus clock (default after reset)
- (++) PLL2_R bus clock
-
- (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
- peripheral.
-
- (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
- function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
-
- (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
- and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
-
- (+) When using the DMA mode
- (++) Configure the IDMA mode (Single buffer or double)
- (++) Configure the buffer address
- (++) Configure Data Path State Machine
-
- (+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the SDMMC_SendCommand(SDMMCx),
- SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
- to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
- to the selected command to be sent.
- The parameters that should be filled are:
- (++) Command Argument
- (++) Command Index
- (++) Command Response type
- (++) Command Wait
- (++) CPSM Status (Enable or Disable).
-
- -@@- To check if the command is well received, read the SDMMC_CMDRESP
- register using the SDMMC_GetCommandResponse().
- The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
- SDMMC_GetResponse() function.
-
- (+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
- SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
-
- *** Read Operations ***
- =======================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDMMC_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be from card (To SDMMC)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDMMC resources to receive the data from the card
- according to selected transfer mode (Refer to Step 8, 9 and 10).
-
- (#) Send the selected Read command (refer to step 11).
-
- (#) Use the SDMMC flags/interrupts to check the transfer status.
-
- *** Write Operations ***
- ========================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDMMC_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be to card (To CARD)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDMMC resources to send the data to the card according to
- selected transfer mode.
-
- (#) Send the selected Write command.
-
- (#) Use the SDMMC flags/interrupts to check the transfer status.
-
- *** Command management operations ***
- =====================================
- [..]
- (#) The commands used for Read/Write/Erase operations are managed in
- separate functions.
- Each function allows to send the needed command with the related argument,
- then check the response.
- By the same approach, you could implement a command and check the response.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
- * @brief Low layer module for SD
- * @{
- */
-
-#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization/de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDMMC according to the specified
- * parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Init: SDMMC initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
- assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
- assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
- assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
- assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
- assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
-
- /* Set SDMMC configuration parameters */
- tmpreg |= (Init.ClockEdge |\
- Init.ClockPowerSave |\
- Init.BusWide |\
- Init.HardwareFlowControl |\
- Init.ClockDiv
- );
-
- /* Write to SDMMC CLKCR */
- MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### I/O operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SDMMC data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
-{
- /* Read data from Rx FIFO */
- return (SDMMCx->FIFO);
-}
-
-/**
- * @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDMMCx: Pointer to SDMMC register base
- * @param pWriteData: pointer to data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
-{
- /* Write data to FIFO */
- SDMMCx->FIFO = *pWriteData;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SDMMC data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set SDMMC Power state to ON.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
-{
- /* Set power state to ON */
- SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
-
- /* 1ms: required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(2);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set SDMMC Power state to Power-Cycle.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
-{
- /* Set power state to Power Cycle*/
- SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
-
- return HAL_OK;
-}
-
-/**
- * @brief Set SDMMC Power state to OFF.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
-{
- /* Set power state to OFF */
- SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get SDMMC Power state.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
-{
- return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
-}
-
-/**
- * @brief Configure the SDMMC command path according to the specified parameters in
- * SDMMC_CmdInitTypeDef structure and send the command
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
- * the configuration information for the SDMMC command
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
- assert_param(IS_SDMMC_RESPONSE(Command->Response));
- assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
- assert_param(IS_SDMMC_CPSM(Command->CPSM));
-
- /* Set the SDMMC Argument value */
- SDMMCx->ARG = Command->Argument;
-
- /* Set SDMMC command parameters */
- tmpreg |= (uint32_t)(Command->CmdIndex |\
- Command->Response |\
- Command->WaitForInterrupt |\
- Command->CPSM);
-
- /* Write to SDMMC CMD register */
- MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-}
-
-/**
- * @brief Return the command index of last command for which response received
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval Command index of the last command response received
- */
-uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
-{
- return (uint8_t)(SDMMCx->RESPCMD);
-}
-
-
-/**
- * @brief Return the response received from the card for the last command
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Response: Specifies the SDMMC response register.
- * This parameter can be one of the following values:
- * @arg SDMMC_RESP1: Response Register 1
- * @arg SDMMC_RESP2: Response Register 2
- * @arg SDMMC_RESP3: Response Register 3
- * @arg SDMMC_RESP4: Response Register 4
- * @retval The Corresponding response register value
- */
-uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
-{
- uint32_t tmp;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_RESP(Response));
-
- /* Get the response */
- tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @brief Configure the SDMMC data path according to the specified
- * parameters in the SDMMC_DataInitTypeDef.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Data : pointer to a SDMMC_DataInitTypeDef structure
- * that contains the configuration information for the SDMMC data.
- * @retval HAL status
- */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
- assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
- assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
- assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
- assert_param(IS_SDMMC_DPSM(Data->DPSM));
-
- /* Set the SDMMC Data TimeOut value */
- SDMMCx->DTIMER = Data->DataTimeOut;
-
- /* Set the SDMMC DataLength value */
- SDMMCx->DLEN = Data->DataLength;
-
- /* Set the SDMMC data configuration parameters */
- tmpreg |= (uint32_t)(Data->DataBlockSize |\
- Data->TransferDir |\
- Data->TransferMode |\
- Data->DPSM);
-
- /* Write to SDMMC DCTRL */
- MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
-{
- return (SDMMCx->DCOUNT);
-}
-
-/**
- * @brief Get the FIFO data
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval Data received
- */
-uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
-{
- return (SDMMCx->FIFO);
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
- * This parameter can be:
- * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
- * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
- * @retval None
- */
-HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
-
- /* Set SDMMC read wait mode */
- MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Commands management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the needed commands.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send the Data Block Lenght command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Read Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Read Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Write Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Write Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Start Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the End Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Start Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the End Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Stop Transfer command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD12 STOP_TRANSMISSION */
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
-
- __SDMMC_CMDSTOP_ENABLE(SDMMCx);
- __SDMMC_CMDTRANS_DISABLE(SDMMCx);
-
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
-
- __SDMMC_CMDSTOP_DISABLE(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Select Deselect command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param addr: Address of the card to be selected
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD7 SDMMC_SEL_DESEL_CARD */
- sdmmc_cmdinit.Argument = (uint32_t)Addr;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Go Idle State command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdError(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Operating Condition command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD8 to verify SD card interface operating condition */
- /* Argument: - [31:12]: Reserved (shall be set to '0')
- - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
- - [7:0]: Check Pattern (recommended 0xAA) */
- /* CMD Response: R7 */
- sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp7(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Application command to verify that that the next command
- * is an application specific com-mand rather than a standard command
- * and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
- * @retval HAL status
- */
-uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- /* If there is a HAL_ERROR, it is a MMC card, else
- it is a SD card: SD card 2.0 (voltage range mismatch)
- or SD card 1.x */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the command asking the accessed card to send its operating
- * condition register (OCR)
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
- * @retval HAL status
- */
-uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp3(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Bus Width command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param BusWidth: BusWidth
- * @retval HAL status
- */
-uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send SCR command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD51 SD_APP_SEND_SCR */
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CID command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD2 ALL_SEND_CID */
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp2(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD9 SEND_CSD */
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp2(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param pRCA: Card RCA
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD3 SD_CMD_SET_REL_ADDR */
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Status command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Status register command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = 0;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Sends host capacity support information and activates the card's
- * initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
- * @retval HAL status
- */
-uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp3(SDMMCx);
-
- return errorstate;
-}
-
-/**
- * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
- /* CMD Response: R1 */
- sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the command asking the accessed card to send its operating
- * condition register (OCR)
- * @param None
- * @retval HAL status
- */
-uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- sdmmc_cmdinit.Argument = 0x00000000;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send EXT_CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Argument: Command Argument
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
-{
- SDMMC_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate;
-
- /* Send CMD9 SEND_CSD */
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
- sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
- (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
-
- return errorstate;
-}
-
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
- * @{
- */
-
-/**
- * @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R1 response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
-{
- uint32_t response_r1;
-
- /* 8 is the number of required instructions cycles for the below loop statement.
- The Timeout is expressed in ms */
- register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END));
-
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
- /* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
- {
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* We have received response, retrieve it for analysis */
- response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
-
- if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
- {
- return SDMMC_ERROR_NONE;
- }
- else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
- {
- return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
- }
- else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
- {
- return SDMMC_ERROR_ADDR_MISALIGNED;
- }
- else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
- {
- return SDMMC_ERROR_BLOCK_LEN_ERR;
- }
- else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
- {
- return SDMMC_ERROR_ERASE_SEQ_ERR;
- }
- else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
- {
- return SDMMC_ERROR_BAD_ERASE_PARAM;
- }
- else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
- {
- return SDMMC_ERROR_WRITE_PROT_VIOLATION;
- }
- else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
- {
- return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
- {
- return SDMMC_ERROR_COM_CRC_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
- {
- return SDMMC_ERROR_ILLEGAL_CMD;
- }
- else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
- {
- return SDMMC_ERROR_CARD_ECC_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
- {
- return SDMMC_ERROR_CC_ERR;
- }
- else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
- {
- return SDMMC_ERROR_STREAM_READ_UNDERRUN;
- }
- else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
- {
- return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
- }
- else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
- {
- return SDMMC_ERROR_CID_CSD_OVERWRITE;
- }
- else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
- {
- return SDMMC_ERROR_WP_ERASE_SKIP;
- }
- else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
- {
- return SDMMC_ERROR_CARD_ECC_DISABLED;
- }
- else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
- {
- return SDMMC_ERROR_ERASE_RESET;
- }
- else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
- {
- return SDMMC_ERROR_AKE_SEQ_ERR;
- }
- else
- {
- return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
-}
-
-/**
- * @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
- if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
- else
- {
- /* No error flag set */
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
- }
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else
- {
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
- }
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
- * address RCA
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
-{
- uint32_t response_r1;
-
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
- {
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
- else
- {
- /* Nothing to do */
- }
-
- /* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
- {
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
- /* We have received response, retrieve it. */
- response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
-
- if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
- {
- *pRCA = (uint16_t) (response_r1 >> 16);
-
- return SDMMC_ERROR_NONE;
- }
- else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
- {
- return SDMMC_ERROR_ILLEGAL_CMD;
- }
- else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
- {
- return SDMMC_ERROR_COM_CRC_FAILED;
- }
- else
- {
- return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
-}
-
-/**
- * @brief Checks for error conditions for R7 response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));
-
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
- {
- /* Card is SD V2.0 compliant */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
-
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
- {
- /* Card is SD V2.0 compliant */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
- else
- {
- /* Nothing to do */
- }
-
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
- {
- /* Card is SD V2.0 compliant */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
- }
-
- return SDMMC_ERROR_NONE;
-
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
deleted file mode 100644
index e1d573f..0000000
--- a/KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
+++ /dev/null
@@ -1,1697 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_ll_usb.c
- * @author MCD Application Team
- * @brief USB Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
- (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
- (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/** @addtogroup STM32H7xx_LL_USB_DRIVER
- * @{
- */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization/de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- if (cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
-
- USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
-
- /* Init The ULPI Interface */
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
- /* Select vbus source */
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
- if(cfg.use_external_vbus == 1)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
- }
- /* Reset after a PHY select */
- USB_CoreReset(USBx);
- }
- else /* FS interface (embedded Phy) */
- {
-
- /* Select FS Embedded PHY */
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-
- /* Reset after a PHY select and set Host mode */
- USB_CoreReset(USBx);
-
- /* Deactivate the power down*/
- USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
- }
-
- if(cfg.dma_enable == ENABLE)
- {
- USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
- USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EnableGlobalInt
- * Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
- USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
- return HAL_OK;
-}
-
-
-/**
- * @brief USB_DisableGlobalInt
- * Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
- USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
- * This parameter can be one of these values:
- * @arg USB_OTG_DEVICE_MODE: Peripheral mode
- * @arg USB_OTG_HOST_MODE: Host mode
- * @arg USB_OTG_DRD_MODE: Dual Role Device mode
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
-{
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
-
- if ( mode == USB_OTG_HOST_MODE)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
- }
- else if ( mode == USB_OTG_DEVICE_MODE)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
- }
- HAL_Delay(50);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevInit : Initializes the USB_OTG controller registers
- * for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- uint32_t i = 0;
-
- /*Activate VBUS Sensing B */
- USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
- if (cfg.vbus_sensing_enable == 0)
- {
- /*Deactivate VBUS Sensing B */
- USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
-
- /* B-peripheral session valid override enable*/
- USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
- USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
- }
-
- /* Restart the Phy Clock */
- USBx_PCGCCTL = 0;
-
- /* Device mode configuration */
- USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-
- if(cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- if(cfg.speed == USB_OTG_SPEED_HIGH)
- {
- /* Set High speed phy */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
- }
- else
- {
- /* set High speed phy in Full speed mode */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
- }
- }
- else
- {
- /* Set Full speed phy */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
- }
-
- /* Flush the FIFOs */
- USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
-
- /* Clear all pending Device Interrupts */
- USBx_DEVICE->DIEPMSK = 0;
- USBx_DEVICE->DOEPMSK = 0;
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
- USBx_DEVICE->DAINTMSK = 0;
-
- for (i = 0; i < cfg.dev_endpoints; i++)
- {
- if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
- {
- USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
- }
- else
- {
- USBx_INEP(i)->DIEPCTL = 0;
- }
-
- USBx_INEP(i)->DIEPTSIZ = 0;
- USBx_INEP(i)->DIEPINT = 0xFF;
- }
-
- for (i = 0; i < cfg.dev_endpoints; i++)
- {
- if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
- {
- USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
- }
- else
- {
- USBx_OUTEP(i)->DOEPCTL = 0;
- }
-
- USBx_OUTEP(i)->DOEPTSIZ = 0;
- USBx_OUTEP(i)->DOEPINT = 0xFF;
- }
-
- USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-
- if (cfg.dma_enable == 1)
- {
- /*Set threshold parameters */
- USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_8 | USB_OTG_DTHRCTL_RXTHRLEN_8);
- USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN | 0x08000000);
-
- i= USBx_DEVICE->DTHRCTL;
- }
-
- /* Disable all interrupts. */
- USBx->GINTMSK = 0;
-
- /* Clear any pending interrupts */
- USBx->GINTSTS = 0xBFFFFFFF;
-
- /* Enable the common interrupts */
- if (cfg.dma_enable == DISABLE)
- {
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
- }
-
- /* Enable interrupts matching to the Device mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
- USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
- USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
- USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
- if(cfg.Sof_enable)
- {
- USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
- }
-
- if (cfg.vbus_sensing_enable == ENABLE)
- {
- USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
- * This parameter can be a value from 1 to 15
- 15 means Flush all Tx FIFOs
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
-{
- uint32_t count = 0;
-
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t count = 0;
-
- USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
- * depending the PHY type and the enumeration speed of the device.
- * @param USBx : Selected device
- * @param speed : device speed
- * This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- * @retval Hal status
- */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
-{
- USBx_DEVICE->DCFG |= speed;
- return HAL_OK;
-}
-
-/**
- * @brief USB_GetDevSpeed :Return the Dev Speed
- * @param USBx : Selected device
- * @retval speed : device speed
- * This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
-{
- uint8_t speed = 0;
-
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
- {
- speed = USB_OTG_SPEED_HIGH;
- }
- else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
- ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
- {
- speed = USB_OTG_SPEED_FULL;
- }
- else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- speed = USB_OTG_SPEED_LOW;
- }
-
- return speed;
-}
-
-/**
- * @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- if (ep->is_in == 1)
- {
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
- }
-
- }
- else
- {
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
- }
- }
- return HAL_OK;
-}
-/**
- * @brief Activate and configure a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- static __IO uint32_t debug = 0;
-
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
- }
-
-
- debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
- }
- else
- {
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-
- debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
- debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
- debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
- }
-
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
- }
-
- return HAL_OK;
-}
-/**
- * @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
- }
- else
- {
-
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
- }
- return HAL_OK;
-}
-
-/**
- * @brief De-activate and de-initialize a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- }
- else
- {
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
- uint16_t pktcnt = 0;
-
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
- }
- }
-
- if (dma == 1)
- {
- USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
- }
- else
- {
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
- }
- }
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
- }
- else
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
- }
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
- }
- }
- else /* OUT endpoint */
- {
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
- if (ep->xfer_len == 0)
- {
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
- }
- else
- {
- pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
- }
-
- if (dma == 1)
- {
- USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
- }
- else
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
- }
- }
- /* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
-{
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-
- if(ep->xfer_len > ep->maxpacket)
- {
- ep->xfer_len = ep->maxpacket;
- }
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
- }
-
- if (dma == 1)
- {
- USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
- }
- else
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0U)
- {
- USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
- }
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
- }
- else /* OUT endpoint */
- {
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
- if (ep->xfer_len > 0U)
- {
- ep->xfer_len = ep->maxpacket;
- }
-
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
-
- if (dma == 1)
- {
- USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
- }
-
- /* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
-{
- uint32_t count32b= 0 , i= 0;
-
- if (dma == 0)
- {
- count32b = (len + 3) / 4;
- for (i = 0; i < count32b; i++)
- {
- USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
- src += 4;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : source pointer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to read
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @retval pointer to destination buffer
- */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
-{
- uint32_t i=0;
- uint32_t count32b = (len + 3) / 4;
-
- for ( i = 0; i < count32b; i++)
- {
- *(__packed uint32_t *)dest = USBx_DFIFO(0);
- dest += 4;
-
- }
- return ((void *)dest);
-}
-
-/**
- * @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
- if (ep->is_in == 1)
- {
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
- }
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
- }
- else
- {
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
- }
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- if (ep->is_in == 1)
- {
- USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
- }
- else
- {
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t i;
-
- /* Clear Pending interrupt */
- for (i = 0; i < 15 ; i++)
- {
- USBx_INEP(i)->DIEPINT = 0xFF;
- USBx_OUTEP(i)->DOEPINT = 0xFF;
- }
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
-
- /* Clear interrupt masks */
- USBx_DEVICE->DIEPMSK = 0;
- USBx_DEVICE->DOEPMSK = 0;
- USBx_DEVICE->DAINTMSK = 0;
-
- /* Flush the FIFO */
- USB_FlushRxFifo(USBx);
- USB_FlushTxFifo(USBx , 0x10 );
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
- * This parameter can be a value from 0 to 255
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
-{
- USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
- USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
-{
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
- HAL_Delay(3);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
-{
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
- HAL_Delay(3);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t v = 0;
-
- v = USBx->GINTSTS;
- v &= USBx->GINTMSK;
- return v;
-}
-
-/**
- * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t v;
- v = USBx_DEVICE->DAINT;
- v &= USBx_DEVICE->DAINTMSK;
- return ((v & 0xffff0000) >> 16);
-}
-
-/**
- * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t v;
- v = USBx_DEVICE->DAINT;
- v &= USBx_DEVICE->DAINTMSK;
- return ((v & 0xFFFF));
-}
-
-/**
- * @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device OUT EP Interrupt register
- */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
- uint32_t v;
- v = USBx_OUTEP(epnum)->DOEPINT;
- v &= USBx_DEVICE->DOEPMSK;
- return v;
-}
-
-/**
- * @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device IN EP Interrupt register
- */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
- uint32_t v, msk, emp;
-
- msk = USBx_DEVICE->DIEPMSK;
- emp = USBx_DEVICE->DIEPEMPMSK;
- msk |= ((emp >> epnum) & 0x1) << 7;
- v = USBx_INEP(epnum)->DIEPINT & msk;
- return v;
-}
-
-/**
- * @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx : Selected device
- * @param interrupt : interrupt flag
- * @retval None
- */
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
-{
- USBx->GINTSTS |= interrupt;
-}
-
-/**
- * @brief Returns USB core mode
- * @param USBx : Selected device
- * @retval return core mode : Host or Device
- * This parameter can be one of these values:
- * 0 : Host
- * 1 : Device
- */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
-{
- return ((USBx->GINTSTS ) & 0x1);
-}
-
-
-/**
- * @brief Activate EP0 for Setup transactions
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Set the MPS of the IN EP based on the enumeration speed */
- USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- USBx_INEP(0)->DIEPCTL |= 3;
- }
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Prepare the EP0 to start the first control setup
- * @param USBx : Selected device
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @param psetup : pointer to setup packet
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
-{
- USBx_OUTEP(0)->DOEPTSIZ = 0;
- USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
- USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
-
- if (dma == 1)
- {
- USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
- /* EP enable */
- USBx_OUTEP(0)->DOEPCTL = 0x80008000;
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Reset the USB Core (needed after USB clock settings change)
- * @param USBx : Selected device
- * @retval HAL status
- */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t count = 0;
-
- /* Wait for AHB master IDLE state. */
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-
- /* Core Soft Reset */
- count = 0;
- USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief USB_HostInit : Initializes the USB OTG controller registers
- * for Host mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- uint32_t i;
-
- /* Restart the Phy Clock */
- USBx_PCGCCTL = 0;
-
- /*Activate VBUS Sensing B */
- USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
- /* Disable the FS/LS support mode only */
- if((cfg.speed == USB_OTG_SPEED_FULL)&&
- (USBx != USB2_OTG_FS))
- {
- USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
- }
- else
- {
- USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
- }
-
- /* Make sure the FIFOs are flushed. */
- USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
-
- /* Clear all pending HC Interrupts */
- for (i = 0; i < cfg.Host_channels; i++)
- {
- USBx_HC(i)->HCINT = 0xFFFFFFFF;
- USBx_HC(i)->HCINTMSK = 0;
- }
-
- /* Enable VBUS driving */
- USB_DriveVbus(USBx, 1);
-
- HAL_Delay(200);
-
- /* Disable all interrupts. */
- USBx->GINTMSK = 0;
-
- /* Clear any pending interrupts */
- USBx->GINTSTS = 0xFFFFFFFF;
-
- if(USBx == USB2_OTG_FS)
- {
- /* set Rx FIFO size */
- USBx->GRXFSIZ = (uint32_t )0x80;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
- USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
- }
- else
- {
- /* set Rx FIFO size */
- USBx->GRXFSIZ = (uint32_t )0x200;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
- USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
- }
-
- /* Enable the common interrupts */
- if (cfg.dma_enable == DISABLE)
- {
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
- }
-
- /* Enable interrupts matching to the Host mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
- USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
- USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
- * HCFG register on the PHY type and set the right frame interval
- * @param USBx : Selected device
- * @param freq : clock frequency
- * This parameter can be one of these values:
- * HCFG_48_MHZ : Full Speed 48 MHz Clock
- * HCFG_6_MHZ : Low Speed 6 MHz Clock
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
-{
- USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
- USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-
- if (freq == HCFG_48_MHZ)
- {
- USBx_HOST->HFIR = (uint32_t)48000;
- }
- else if (freq == HCFG_6_MHZ)
- {
- USBx_HOST->HFIR = (uint32_t)6000;
- }
- return HAL_OK;
-}
-
-/**
-* @brief USB_OTG_ResetPort : Reset Host Port
- * @param USBx : Selected device
- * @retval HAL status
- * @note : (1)The application must wait at least 10 ms
- * before clearing the reset bit.
- */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
-{
- __IO uint32_t hprt0;
-
- hprt0 = USBx_HPRT0;
-
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
- HAL_Delay (100); /* See Note #1 */
- USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
- return HAL_OK;
-}
-
-/**
- * @brief USB_DriveVbus : activate or de-activate vbus
- * @param state : VBUS state
- * This parameter can be one of these values:
- * 0 : VBUS Active
- * 1 : VBUS Inactive
- * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
-{
- __IO uint32_t hprt0;
-
- hprt0 = USBx_HPRT0;
-
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
- {
- USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
- }
- if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
- {
- USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
- }
- return HAL_OK;
-}
-
-/**
- * @brief Return Host Core speed
- * @param USBx : Selected device
- * @retval speed : Host speed
- * This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
-{
- __IO uint32_t hprt0;
-
- hprt0 = USBx_HPRT0;
- return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
-}
-
-/**
- * @brief Return Host Current Frame number
- * @param USBx : Selected device
- * @retval current frame number
-*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
-{
- return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
-}
-
-/**
- * @brief Initialize a host channel
- * @param USBx : Selected device
- * @param ch_num : Channel number
- * This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
- * This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
- * This parameter can be a value from 0 to 255
- * @param speed : Current device speed
- * This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
- * This parameter can be one of these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochronous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
- * This parameter can be a value from 0 to32K
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
-
- /* Clear old interrupt conditions for this host channel. */
- USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-
- /* Enable channel interrupts required for this transfer. */
- switch (ep_type)
- {
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
-
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_NAKM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- else
- {
- if(USBx != USB2_OTG_FS)
- {
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
- }
- }
- break;
-
- case EP_TYPE_INTR:
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_NAKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
-
- break;
- case EP_TYPE_ISOC:
-
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_ACKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
- }
- break;
- }
-
- /* Enable the top level host channel interrupt. */
- USBx_HOST->HAINTMSK |= (1 << ch_num);
-
- /* Make sure host channel interrupts are enabled. */
- USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-
- /* Program the HCCHAR register */
- USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
- (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
- ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
- (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
- ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
- (mps & USB_OTG_HCCHAR_MPSIZ));
-
- if (ep_type == EP_TYPE_INTR)
- {
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Start a transfer over a host channel
- * @param USBx : Selected device
- * @param hc : pointer to host channel structure
- * @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @retval HAL state
- */
-#if defined (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
-{
- uint8_t is_oddframe = 0;
- uint16_t len_words = 0;
- uint16_t num_packets = 0;
- uint16_t max_hc_pkt_count = 256;
- uint32_t tmpreg = 0;
-
- if((USBx != USB2_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
- {
- if((dma == 0) && (hc->do_ping == 1))
- {
- USB_DoPing(USBx, hc->ch_num);
- return HAL_OK;
- }
- else if(dma == 1)
- {
- USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
- hc->do_ping = 0;
- }
- }
-
- /* Compute the expected number of packets associated to the transfer */
- if (hc->xfer_len > 0)
- {
- num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-
- if (num_packets > max_hc_pkt_count)
- {
- num_packets = max_hc_pkt_count;
- hc->xfer_len = num_packets * hc->max_packet;
- }
- }
- else
- {
- num_packets = 1;
- }
- if (hc->ep_is_in)
- {
- hc->xfer_len = num_packets * hc->max_packet;
- }
-
- /* Initialize the HCTSIZn register */
- USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
- ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
- (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-
- if (dma)
- {
- /* xfer_buff MUST be 32-bits aligned */
- USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
- }
-
- is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
- USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-
- /* Set host channel enable */
- tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-
- if (dma == 0) /* Slave mode */
- {
- if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
- {
- switch(hc->ep_type)
- {
- /* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
-
- len_words = (hc->xfer_len + 3) / 4;
-
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx->HNPTXSTS & 0xFFFF))
- {
- /* need to process data in nptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
- }
- break;
- /* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- len_words = (hc->xfer_len + 3) / 4;
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
- }
- break;
-
- default:
- break;
- }
-
- /* Write packet into the Tx FIFO. */
- USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Read all host channel interrupts status
- * @param USBx : Selected device
- * @retval HAL state
- */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- return ((USBx_HOST->HAINT) & 0xFFFF);
-}
-
-/**
- * @brief Halt a host channel
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
- * This parameter can be a value from 1 to 15
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
-{
- uint32_t count = 0;
-
- /* Check for space in the request queue to issue the halt. */
- if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
- if ((USBx->HNPTXSTS & 0xFFFF) == 0)
- {
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- }
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
- if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
- {
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initiate Do Ping protocol
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
- * This parameter can be a value from 1 to 15
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
-{
- uint8_t num_packets = 1;
- uint32_t tmpreg = 0;
-
- USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
- USB_OTG_HCTSIZ_DOPING;
-
- /* Set host channel enable */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop Host Core
- * @param USBx : Selected device
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
-{
- uint8_t i;
- uint32_t count = 0;
- uint32_t value;
-
- USB_DisableGlobalInt(USBx);
-
- /* Flush FIFO */
- USB_FlushTxFifo(USBx, 0x10);
- USB_FlushRxFifo(USBx);
-
- /* Flush out any leftover queued requests. */
- for (i = 0; i <= 15; i++)
- {
-
- value = USBx_HC(i)->HCCHAR ;
- value |= USB_OTG_HCCHAR_CHDIS;
- value &= ~USB_OTG_HCCHAR_CHENA;
- value &= ~USB_OTG_HCCHAR_EPDIR;
- USBx_HC(i)->HCCHAR = value;
- }
-
- /* Halt all channels to put them into a known state. */
- for (i = 0; i <= 15; i++)
- {
- value = USBx_HC(i)->HCCHAR ;
-
- value |= USB_OTG_HCCHAR_CHDIS;
- value |= USB_OTG_HCCHAR_CHENA;
- value &= ~USB_OTG_HCCHAR_EPDIR;
-
- USBx_HC(i)->HCCHAR = value;
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
-
- /* Clear any pending Host interrupts */
- USBx_HOST->HAINT = 0xFFFFFFFF;
- USBx->GINTSTS = 0xFFFFFFFF;
- USB_EnableGlobalInt(USBx);
- return HAL_OK;
-}
-/**
- * @}
- */
-
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
-
-
-
diff --git a/KugleFirmware/Inc/FreeRTOSConfig.h b/KugleFirmware/Inc/FreeRTOSConfig.h
deleted file mode 100644
index 2e1b6b3..0000000
--- a/KugleFirmware/Inc/FreeRTOSConfig.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* USER CODE BEGIN Header */
-/*
- FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
- All rights reserved
-
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License (version 2) as published by the
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
- ***************************************************************************
- >>! NOTE: The modification to the GPL is included to allow you to !<<
- >>! distribute a combined work that includes FreeRTOS without being !<<
- >>! obliged to provide the source code for proprietary components !<<
- >>! outside of the FreeRTOS kernel. !<<
- ***************************************************************************
-
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
- FOR A PARTICULAR PURPOSE. Full license text is available on the following
- link: http://www.freertos.org/a00114.html
-
- ***************************************************************************
- * *
- * FreeRTOS provides completely free yet professionally developed, *
- * robust, strictly quality controlled, supported, and cross *
- * platform software that is more than just the market leader, it *
- * is the industry's de facto standard. *
- * *
- * Help yourself get started quickly while simultaneously helping *
- * to support the FreeRTOS project by purchasing a FreeRTOS *
- * tutorial book, reference manual, or both: *
- * http://www.FreeRTOS.org/Documentation *
- * *
- ***************************************************************************
-
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
- the FAQ page "My application does not run, what could be wrong?". Have you
- defined configASSERT()?
-
- http://www.FreeRTOS.org/support - In return for receiving this top quality
- embedded software for free we request you assist our global community by
- participating in the support forum.
-
- http://www.FreeRTOS.org/training - Investing in training allows your team to
- be as productive as possible as early as possible. Now you can receive
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
- Ltd, and the world's leading authority on the world's leading RTOS.
-
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS
- compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
- licenses offer ticketed support, indemnification and commercial middleware.
-
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety
- engineered and independently SIL3 certified version for use in safety and
- mission critical applications that require provable dependability.
-
- 1 tab == 4 spaces!
-*/
-/* USER CODE END Header */
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-/* USER CODE BEGIN Includes */
-/* Section where include file can be added */
-/* USER CODE END Includes */
-
-/* Ensure stdint is only used by the compiler, and not the assembler. */
-#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
- #include
- extern uint32_t SystemCoreClock;
-/* USER CODE BEGIN 0 */
- extern void configureTimerForRunTimeStats(void);
- extern unsigned long getRunTimeCounterValue(void);
- extern uint32_t millis();
-/* USER CODE END 0 */
-#endif
-
-#define configUSE_PREEMPTION 1
-#define configSUPPORT_STATIC_ALLOCATION 0
-#define configSUPPORT_DYNAMIC_ALLOCATION 1
-#define configUSE_IDLE_HOOK 0
-#define configUSE_TICK_HOOK 0
-#define configCPU_CLOCK_HZ ( SystemCoreClock )
-#define configTICK_RATE_HZ ((TickType_t)1000)
-#define configMAX_PRIORITIES ( 20 )
-#define configMINIMAL_STACK_SIZE ((uint16_t)256)
-#define configTOTAL_HEAP_SIZE ((size_t)262144)//((size_t)65535)//
-#define configMAX_TASK_NAME_LEN ( 20 )
-#define configGENERATE_RUN_TIME_STATS 1
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_TRACE_FACILITY 1
-#define configUSE_STATS_FORMATTING_FUNCTIONS 1
-#define configUSE_16_BIT_TICKS 0
-#define configUSE_MUTEXES 1
-#define configUSE_COUNTING_SEMAPHORES 1
-#define configQUEUE_REGISTRY_SIZE 20
-#define configCHECK_FOR_STACK_OVERFLOW 2
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#define configUSE_MALLOC_FAILED_HOOK 1
-
-#define configRECORD_STACK_HIGH_ADDRESS 1 /* 1: record stack high address for the debugger, 0: do not record stack high address */
-#define configTASK_RETURN_ADDRESS 0
-#define configUSE_HEAP_SCHEME 4 /* either 1 (only alloc), 2 (alloc/free), 3 (malloc), 4 (coalesc blocks), 5 (multiple blocks) */
-#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 0
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
-#define INCLUDE_xTaskGetSchedulerState 1
-
-/* Cortex-M specific definitions. */
-#ifdef __NVIC_PRIO_BITS
- /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
- #define configPRIO_BITS __NVIC_PRIO_BITS
-#else
- #define configPRIO_BITS 4
-#endif
-
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 3
-
-/* Interrupt priorities used by the kernel port layer itself. These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* Normal assert() semantics without relying on the provision of an assert.h
-header file. */
-/* USER CODE BEGIN 1 */
-#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
-/* USER CODE END 1 */
-
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
-standard names. */
-#define vPortSVCHandler SVC_Handler
-#define xPortPendSVHandler PendSV_Handler
-#define xPortSysTickHandler SysTick_Handler
-
-/* USER CODE BEGIN 2 */
-/* Definitions needed when configGENERATE_RUN_TIME_STATS is on */
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS configureTimerForRunTimeStats
-#define portGET_RUN_TIME_COUNTER_VALUE getRunTimeCounterValue
-/* USER CODE END 2 */
-
-/* USER CODE BEGIN Defines */
-/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
-/* USER CODE END Defines */
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/KugleFirmware/Inc/MainTask.h b/KugleFirmware/Inc/MainTask.h
deleted file mode 100644
index 60f2203..0000000
--- a/KugleFirmware/Inc/MainTask.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef MAIN_TASK_H
-#define MAIN_TASK_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void MainTask(void * pvParameters);
-
-#ifdef __cplusplus
-}
-
-#include "LSPC.hpp"
-void Reboot_Callback(void * param, const std::vector& payload);
-void EnterBootloader_Callback(void * param, const std::vector& payload);
-
-#endif
-
-#endif
diff --git a/KugleFirmware/Inc/MemoryManagement.h b/KugleFirmware/Inc/MemoryManagement.h
deleted file mode 100644
index 507eeee..0000000
--- a/KugleFirmware/Inc/MemoryManagement.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef MEMORY_MANAGEMENT_H
-#define MEMORY_MANAGEMENT_H
-
-void ZeroInitFreeRTOSheap(void);
-
-#endif
diff --git a/KugleFirmware/Inc/Priorities.h b/KugleFirmware/Inc/Priorities.h
deleted file mode 100644
index b703955..0000000
--- a/KugleFirmware/Inc/Priorities.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef PRIORITIES_H
-#define PRIORITIES_H
-
-/* Define hardware interrupt priorities (HAL_NVIC_SetPriority)
- * Lower value means higher priority
- * Interrupt priority has to be between 0 and 15
- * Remember to respect the "configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY" in FreeRTOSConfig.h, hence no hardware interrupt calling FreeRTOS functions must have a priority value lower than configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
- */
-#define HIGH_RES_TIMER_TICK_PRIORITY 0 // This timer is also used to generate ticks for any ST HAL library (eg. HAL_Delay)
-#define ENCODER_TIMER_OVERFLOW_PRIORITY 1
-#define ADC_DMA_INTERRUPT_PRIORITY 15
-
-// Below are periphiral priorities which uses FreeRTOS functions
-#define USB_INTERRUPT_PRIORITY 5
-#define UART_INTERRUPT_PRIORITY 6
-#define SPI_INTERRUPT_PRIORITY 7
-#define I2C_INTERRUPT_PRIORITY 8
-#define TIMER_INTERRUPT_PRIORITY 9
-#define IO_INTERRUPT_PRIORITY 10
-#define SMBUS_INTERRUPT_PRIORITY 11
-
-
-
-/* Define task priorities in FreeRTOS format
- * Higher values means higher priority
- * Hence low values denote low priority tasks. The idle task has priority 0 (tskIDLE_PRIORITY)
- * Task priority has to be between 0 and (configMAX_PRIORITIES-1)
- */
-#define MAIN_TASK_PRIORITY 0
-#define APPLICATION_TEMPLATE_PRIORITY 0
-#define POWER_MANAGEMENT_PRIORITY 1
-#define FRONT_PANEL_PRIORITY 2
-#define TEST_BENCH_PRIORITY 3
-#define DEBUG_MESSAGE_PRIORITY 4
-#define BALANCE_CONTROLLER_PRIORITY 6
-#define UART_RECEIVER_PRIORITY 10
-#define LSPC_RECEIVER_PRIORITY 11
-#define USBCDC_TRANSMITTER_PRIORITY 12
-#define LSPC_TRANSMITTER_PRIORITY 13 // important that this has the highest priority
-
-
-
-#endif
diff --git a/KugleFirmware/Inc/ProcessorInit.h b/KugleFirmware/Inc/ProcessorInit.h
deleted file mode 100644
index 00a36ad..0000000
--- a/KugleFirmware/Inc/ProcessorInit.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef PROCESSOR_INIT_H
-#define PROCESSOR_INIT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "stm32h7xx_hal.h"
-
-#define BOOTLOADER_MAGIC_ADDR ((uint32_t*) ((uint32_t) 0x2001FFF0))
-#define BOOTLOADER_MAGIC_TOKEN 0xDEADBEEF
-
-//Value taken from CD00167594.pdf page 35, system memory start.
-#define BOOTLOADER_START_ADDR 0x1fffc400 //for ST32F042
-
-#define A_VALUE 0x12345678
-
-void SystemClock_Config(void);
-void Enter_DFU_Bootloader(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/KugleFirmware/Inc/main.h b/KugleFirmware/Inc/main.h
deleted file mode 100644
index 193c735..0000000
--- a/KugleFirmware/Inc/main.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-/* Private includes ----------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions prototypes ---------------------------------------------*/
-void TestBench_Init(void);
-void CPU_CACHE_Enable(void);
-void MPU_Config(void);
-
-/* Private defines -----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MAIN_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Inc/stm32h7xx_hal_conf.h b/KugleFirmware/Inc/stm32h7xx_hal_conf.h
deleted file mode 100644
index 44d3398..0000000
--- a/KugleFirmware/Inc/stm32h7xx_hal_conf.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32h7xx_hal_conf_template.h
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32h7xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CONF_H
-#define __STM32H7xx_HAL_CONF_H
-
-#include "Priorities.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-
-#define HAL_ADC_MODULE_ENABLED
-/* #define HAL_FDCAN_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DCMI_MODULE_ENABLED */
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_HSEM_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-#define HAL_SMBUS_MODULE_ENABLED
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_MMC_MODULE_ENABLED */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_SWPMI_MODULE_ENABLED */
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-/* #define HAL_EXTI_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_MDMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_HSEM_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal oscillator (CSI) default value.
- * This value is the default CSI value after Reset.
- */
-#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief External Low Speed oscillator (LSE) value.
- * This value is used by the UART, RTC HAL module to compute the system frequency
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)HIGH_RES_TIMER_TICK_PRIORITY) /*!< tick interrupt priority */
-#define USE_RTOS 0U
-#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1U */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC 0U
-
-/* ################## ETH peripheral configuration ########################## */
-
-#define ETH_TX_DESC_CNT ((uint32_t)4U) /* Tx Descriptor Length */
-#define ETH_RX_DESC_CNT ((uint32_t)4U) /* Rx Descriptor Length */
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32h7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32h7xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32h7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32h7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32h7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32h7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
- #include "stm32h7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32h7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
- #include "stm32h7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32h7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32h7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
- #include "stm32h7xx_hal_fdcan.h"
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32h7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32h7xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32h7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32h7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32h7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32h7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
- #include "stm32h7xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
- #include "stm32h7xx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32h7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32h7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32h7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32h7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32h7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32h7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
- #include "stm32h7xx_hal_mdma.h"
-#endif /* HAL_MDMA_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32h7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-#include "stm32h7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32h7xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32h7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32h7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32h7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32h7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32h7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32h7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32h7xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32h7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32h7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32h7xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32h7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32h7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32h7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32h7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32h7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32h7xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32h7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32h7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#include "stm32h7xx_hal_timebase_tim.h"
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/Inc/stm32h7xx_hal_timebase_tim.h b/KugleFirmware/Inc/stm32h7xx_hal_timebase_tim.h
deleted file mode 100644
index 20cd960..0000000
--- a/KugleFirmware/Inc/stm32h7xx_hal_timebase_tim.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __STM32H7xx_HAL_TIMEBASE_TIM_H
-#define __STM32H7xx_HAL_TIMEBASE_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal.h"
-
-uint32_t HAL_GetTickTimerValue(void);
-uint32_t HAL_GetHighResTick(void);
-void HAL_DelayHighRes(uint32_t Delay);
-
-uint32_t HAL_tic();
-float HAL_toc(uint32_t timerPrev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_TIMEBASE_TIM_H */
diff --git a/KugleFirmware/Inc/stm32h7xx_it.h b/KugleFirmware/Inc/stm32h7xx_it.h
deleted file mode 100644
index 16254c0..0000000
--- a/KugleFirmware/Inc/stm32h7xx_it.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file stm32h7xx_it.h
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- *
- * COPYRIGHT(c) 2018 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_IT_H
-#define __STM32H7xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-#include "cmsis_os.h"
-/* USER CODE END Includes */
-
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void DebugMon_Handler(void);
-void EXTI1_IRQHandler(void);
-void EXTI2_IRQHandler(void);
-void EXTI9_5_IRQHandler(void);
-void TIM2_IRQHandler(void);
-void TIM3_IRQHandler(void);
-void TIM4_IRQHandler(void);
-void USART3_IRQHandler(void);
-void EXTI15_10_IRQHandler(void);
-void SPI3_IRQHandler(void);
-void UART4_IRQHandler(void);
-void UART7_IRQHandler(void);
-void SPI6_IRQHandler(void);
-void OTG_FS_IRQHandler(void);
-void TIM16_IRQHandler(void);
-/* USER CODE BEGIN EFP */
-void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName );
-void vApplicationMallocFailedHook( void );
-void DisableHardware(void);
-/* USER CODE END EFP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/KugleFirmware/KugleFirmware Debug.cfg b/KugleFirmware/KugleFirmware Debug.cfg
deleted file mode 100644
index 2ca9335..0000000
--- a/KugleFirmware/KugleFirmware Debug.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-# This is an KugleFirmware board with a single STM32H743ZITx chip
-#
-# Generated by System Workbench for STM32
-# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
-
-source [find interface/stlink.cfg]
-
-set WORKAREASIZE 0x8000
-
-transport select "hla_swd"
-
-set CHIPNAME STM32H743ZITx
-set BOARDNAME KugleFirmware
-
-# Enable debug when in low power modes
-set ENABLE_LOW_POWER 1
-
-# Stop Watchdog counters when halt
-set STOP_WATCHDOG 1
-
-# STlink Debug clock frequency
-set CLOCK_FREQ 4000
-
-# use hardware reset, connect under reset
-# connect_assert_srst needed if low power mode application running (WFI...)
-reset_config srst_only srst_nogate connect_assert_srst
-set CONNECT_UNDER_RESET 1
-
-source [find target/stm32h7x.cfg]
diff --git a/KugleFirmware/KugleFirmware.ioc b/KugleFirmware/KugleFirmware.ioc
deleted file mode 100644
index 0bbd56c..0000000
--- a/KugleFirmware/KugleFirmware.ioc
+++ /dev/null
@@ -1,662 +0,0 @@
-#MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_8
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master
-ADC1.NbrOfConversionFlag=1
-ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC1.Rank-0\#ChannelRegularConversion=1
-ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-ADC1.master=1
-ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_11
-ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag
-ADC2.NbrOfConversionFlag=1
-ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC2.Rank-0\#ChannelRegularConversion=1
-ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
-ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag
-ADC3.NbrOfConversionFlag=1
-ADC3.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC3.Rank-0\#ChannelRegularConversion=1
-ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-FREERTOS.INCLUDE_vTaskDelayUntil=1
-FREERTOS.IPParameters=Tasks01,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configTOTAL_HEAP_SIZE,configGENERATE_RUN_TIME_STATS,configUSE_STATS_FORMATTING_FUNCTIONS,INCLUDE_vTaskDelayUntil,configUSE_TRACE_FACILITY
-FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default,NULL
-FREERTOS.configGENERATE_RUN_TIME_STATS=1
-FREERTOS.configMAX_PRIORITIES=20
-FREERTOS.configMINIMAL_STACK_SIZE=256
-FREERTOS.configTOTAL_HEAP_SIZE=262144
-FREERTOS.configUSE_STATS_FORMATTING_FUNCTIONS=1
-FREERTOS.configUSE_TRACE_FACILITY=1
-File.Version=6
-I2C1.IPParameters=Timing
-I2C1.Timing=0x10C0ECFF
-I2C2.IPParameters=Timing,Timeout,SMBusPeripheralMode,SMBusOwnAddress
-I2C2.SMBusOwnAddress=0x13
-I2C2.SMBusPeripheralMode=SMBUS_PERIPHERAL_MODE_SMBUS_HOST
-I2C2.Timeout=0x000084C4
-I2C2.Timing=0x10C0ECFF
-I2C3.IPParameters=Timing
-I2C3.Timing=0x10C0ECFF
-I2C4.IPParameters=Timing,Timeout,SMBusPeripheralMode,SMBusOwnAddress
-I2C4.SMBusOwnAddress=0x13
-I2C4.SMBusPeripheralMode=SMBUS_PERIPHERAL_MODE_SMBUS_HOST
-I2C4.Timeout=0x000084C4
-I2C4.Timing=0x10C0ECFF
-KeepUserPlacement=false
-Mcu.Family=STM32H7
-Mcu.IP0=ADC1
-Mcu.IP1=ADC2
-Mcu.IP10=RCC
-Mcu.IP11=SPI3
-Mcu.IP12=SPI6
-Mcu.IP13=SYS
-Mcu.IP14=TIM1
-Mcu.IP15=TIM2
-Mcu.IP16=TIM3
-Mcu.IP17=TIM4
-Mcu.IP18=TIM8
-Mcu.IP19=TIM15
-Mcu.IP2=ADC3
-Mcu.IP20=TIM17
-Mcu.IP21=UART4
-Mcu.IP22=UART7
-Mcu.IP23=USART3
-Mcu.IP24=USB_DEVICE
-Mcu.IP25=USB_OTG_FS
-Mcu.IP3=CORTEX_M7
-Mcu.IP4=FREERTOS
-Mcu.IP5=I2C1
-Mcu.IP6=I2C2
-Mcu.IP7=I2C3
-Mcu.IP8=I2C4
-Mcu.IP9=NVIC
-Mcu.IPNb=26
-Mcu.Name=STM32H743ZITx
-Mcu.Package=LQFP144
-Mcu.Pin0=PE3
-Mcu.Pin1=PE4
-Mcu.Pin10=PF5
-Mcu.Pin11=PF6
-Mcu.Pin12=PF10
-Mcu.Pin13=PH0-OSC_IN (PH0)
-Mcu.Pin14=PH1-OSC_OUT (PH1)
-Mcu.Pin15=PC0
-Mcu.Pin16=PC1
-Mcu.Pin17=PC2_C
-Mcu.Pin18=PC3_C
-Mcu.Pin19=PA0
-Mcu.Pin2=PE5
-Mcu.Pin20=PA1
-Mcu.Pin21=PA2
-Mcu.Pin22=PA3
-Mcu.Pin23=PA4
-Mcu.Pin24=PA5
-Mcu.Pin25=PA6
-Mcu.Pin26=PA7
-Mcu.Pin27=PC5
-Mcu.Pin28=PB1
-Mcu.Pin29=PB2
-Mcu.Pin3=PE6
-Mcu.Pin30=PF11
-Mcu.Pin31=PF14
-Mcu.Pin32=PF15
-Mcu.Pin33=PE7
-Mcu.Pin34=PE8
-Mcu.Pin35=PE9
-Mcu.Pin36=PE11
-Mcu.Pin37=PE13
-Mcu.Pin38=PE14
-Mcu.Pin39=PB10
-Mcu.Pin4=PC13
-Mcu.Pin40=PB11
-Mcu.Pin41=PB14
-Mcu.Pin42=PB15
-Mcu.Pin43=PD8
-Mcu.Pin44=PD9
-Mcu.Pin45=PD10
-Mcu.Pin46=PD11
-Mcu.Pin47=PD12
-Mcu.Pin48=PD13
-Mcu.Pin49=PD14
-Mcu.Pin5=PF0
-Mcu.Pin50=PD15
-Mcu.Pin51=PG8
-Mcu.Pin52=PC6
-Mcu.Pin53=PC7
-Mcu.Pin54=PC8
-Mcu.Pin55=PC9
-Mcu.Pin56=PA8
-Mcu.Pin57=PA9
-Mcu.Pin58=PA11
-Mcu.Pin59=PA12
-Mcu.Pin6=PF1
-Mcu.Pin60=PA13 (JTMS/SWDIO)
-Mcu.Pin61=PA14 (JTCK/SWCLK)
-Mcu.Pin62=PA15 (JTDI)
-Mcu.Pin63=PC10
-Mcu.Pin64=PC11
-Mcu.Pin65=PC12
-Mcu.Pin66=PD0
-Mcu.Pin67=PD1
-Mcu.Pin68=PD2
-Mcu.Pin69=PD3
-Mcu.Pin7=PF2
-Mcu.Pin70=PD5
-Mcu.Pin71=PD6
-Mcu.Pin72=PD7
-Mcu.Pin73=PG12
-Mcu.Pin74=PG13
-Mcu.Pin75=PG14
-Mcu.Pin76=PB4 (NJTRST)
-Mcu.Pin77=PB5
-Mcu.Pin78=PB6
-Mcu.Pin79=PB7
-Mcu.Pin8=PF3
-Mcu.Pin80=PB8
-Mcu.Pin81=PB9
-Mcu.Pin82=PE0
-Mcu.Pin83=PE1
-Mcu.Pin84=VP_FREERTOS_VS_ENABLE
-Mcu.Pin85=VP_SYS_VS_tim16
-Mcu.Pin86=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin87=VP_TIM8_VS_ClockSourceINT
-Mcu.Pin88=VP_TIM15_VS_ClockSourceINT
-Mcu.Pin89=VP_TIM17_VS_ClockSourceINT
-Mcu.Pin9=PF4
-Mcu.Pin90=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
-Mcu.PinsNb=91
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=
-Mcu.UserName=STM32H743ZITx
-MxCube.Version=5.0.0
-MxDb.Version=DB.5.0.0
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.EXTI15_10_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.EXTI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.EXTI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false
-NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SPI3_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.SPI6_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false
-NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false
-NVIC.TIM16_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.TIM2_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.TIM3_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.TIM4_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.TimeBase=TIM16_IRQn
-NVIC.TimeBaseIP=TIM16
-NVIC.UART4_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.UART7_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.USART3_IRQn=true\:5\:0\:false\:false\:true\:true\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA0.Locked=true
-PA0.Signal=S_TIM2_CH1
-PA1.Locked=true
-PA1.Signal=S_TIM2_CH2
-PA11.Mode=Device_Only
-PA11.Signal=USB_OTG_FS_DM
-PA12.Mode=Device_Only
-PA12.Signal=USB_OTG_FS_DP
-PA13\ (JTMS/SWDIO).Mode=Serial_Wire
-PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO
-PA14\ (JTCK/SWCLK).Mode=Serial_Wire
-PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK
-PA15\ (JTDI).Locked=true
-PA15\ (JTDI).Signal=GPIO_Output
-PA2.Locked=true
-PA2.Signal=GPIO_Input
-PA3.Locked=true
-PA3.Signal=GPIO_Input
-PA4.Locked=true
-PA4.Signal=GPIO_Output
-PA5.Locked=true
-PA5.Signal=GPIO_Output
-PA6.Locked=true
-PA6.Signal=GPIO_Output
-PA7.Locked=true
-PA7.Signal=GPIO_Input
-PA8.Locked=true
-PA8.Mode=I2C
-PA8.Signal=I2C3_SCL
-PA9.Locked=true
-PA9.Mode=Activate_VBUS
-PA9.Signal=USB_OTG_FS_VBUS
-PB1.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PB1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
-PB1.GPIO_PuPd=GPIO_PULLUP
-PB1.Locked=true
-PB1.Signal=GPXTI1
-PB10.Locked=true
-PB10.Mode=Asynchronous
-PB10.Signal=USART3_TX
-PB11.Locked=true
-PB11.Mode=Asynchronous
-PB11.Signal=USART3_RX
-PB14.Locked=true
-PB14.Signal=GPIO_Input
-PB15.Locked=true
-PB15.Signal=GPIO_Input
-PB2.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PB2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
-PB2.GPIO_PuPd=GPIO_PULLUP
-PB2.Locked=true
-PB2.Signal=GPXTI2
-PB4\ (NJTRST).Locked=true
-PB4\ (NJTRST).Signal=S_TIM3_CH1
-PB5.Locked=true
-PB5.Signal=S_TIM3_CH2
-PB6.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PB6.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
-PB6.GPIO_PuPd=GPIO_PULLUP
-PB6.Locked=true
-PB6.Signal=GPXTI6
-PB7.Locked=true
-PB7.Mode=PWM Generation1 CH1N
-PB7.Signal=TIM17_CH1N
-PB8.Locked=true
-PB8.Mode=I2C
-PB8.Signal=I2C1_SCL
-PB9.Locked=true
-PB9.Mode=I2C
-PB9.Signal=I2C1_SDA
-PC0.Locked=true
-PC0.Signal=ADCx_INP10
-PC1.Locked=true
-PC1.Signal=ADCx_INP11
-PC10.Locked=true
-PC10.Mode=Full_Duplex_Master
-PC10.Signal=SPI3_SCK
-PC11.Locked=true
-PC11.Mode=Full_Duplex_Master
-PC11.Signal=SPI3_MISO
-PC12.Locked=true
-PC12.Mode=Full_Duplex_Master
-PC12.Signal=SPI3_MOSI
-PC13.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
-PC13.GPIO_PuPd=GPIO_PULLUP
-PC13.Locked=true
-PC13.Signal=GPXTI13
-PC2_C.Locked=true
-PC2_C.Mode=IN0-Single-Ended
-PC2_C.Signal=ADC3_INP0
-PC3_C.Locked=true
-PC3_C.Signal=GPIO_Output
-PC5.Locked=true
-PC5.Signal=ADCx_INP8
-PC6.Locked=true
-PC6.Signal=S_TIM8_CH1
-PC7.Locked=true
-PC7.Signal=S_TIM8_CH2
-PC8.Locked=true
-PC8.Signal=S_TIM8_CH3
-PC9.Locked=true
-PC9.Mode=I2C
-PC9.Signal=I2C3_SDA
-PCC.Checker=false
-PCC.Line=STM32H743/753
-PCC.MCU=STM32H743ZITx
-PCC.PartNumber=STM32H743ZITx
-PCC.Seq0=0
-PCC.Series=STM32H7
-PCC.Temperature=25
-PCC.Vdd=3.0
-PD0.Locked=true
-PD0.Mode=Asynchronous
-PD0.Signal=UART4_RX
-PD1.Locked=true
-PD1.Mode=Asynchronous
-PD1.Signal=UART4_TX
-PD10.Locked=true
-PD10.Signal=GPIO_Input
-PD11.Locked=true
-PD11.Signal=GPIO_Input
-PD12.Locked=true
-PD12.Signal=S_TIM4_CH1
-PD13.Locked=true
-PD13.Signal=S_TIM4_CH2
-PD14.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PD14.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
-PD14.GPIO_PuPd=GPIO_PULLUP
-PD14.Locked=true
-PD14.Signal=GPXTI14
-PD15.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PD15.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
-PD15.GPIO_PuPd=GPIO_PULLUP
-PD15.Locked=true
-PD15.Signal=GPXTI15
-PD2.Locked=true
-PD2.Signal=GPIO_Input
-PD3.Locked=true
-PD3.Signal=GPIO_Input
-PD5.Locked=true
-PD5.Signal=GPIO_Input
-PD6.Locked=true
-PD6.Signal=GPIO_Input
-PD7.Locked=true
-PD7.Signal=GPIO_Input
-PD8.Locked=true
-PD8.Signal=GPIO_Input
-PD9.Locked=true
-PD9.Signal=GPIO_Input
-PE0.Locked=true
-PE0.Signal=GPIO_Output
-PE1.Locked=true
-PE1.Signal=GPIO_Input
-PE11.Locked=true
-PE11.Signal=S_TIM1_CH2
-PE13.Locked=true
-PE13.Signal=S_TIM1_CH3
-PE14.Locked=true
-PE14.Signal=GPIO_Output
-PE3.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultEXTI
-PE3.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING
-PE3.GPIO_PuPd=GPIO_PULLDOWN
-PE3.Locked=true
-PE3.Signal=GPXTI3
-PE4.Locked=true
-PE4.Signal=GPIO_Output
-PE5.Locked=true
-PE5.Signal=S_TIM15_CH1
-PE6.Locked=true
-PE6.Signal=GPIO_Output
-PE7.Locked=true
-PE7.Mode=Asynchronous
-PE7.Signal=UART7_RX
-PE8.Locked=true
-PE8.Mode=Asynchronous
-PE8.Signal=UART7_TX
-PE9.Locked=true
-PE9.Signal=S_TIM1_CH1
-PF0.Locked=true
-PF0.Mode=SMBus-two-wire-Interface
-PF0.Signal=I2C2_SDA
-PF1.Locked=true
-PF1.Mode=SMBus-two-wire-Interface
-PF1.Signal=I2C2_SCL
-PF10.Locked=true
-PF10.Mode=IN6-Single-Ended
-PF10.Signal=ADC3_INP6
-PF11.Locked=true
-PF11.Mode=IN2-Single-Ended
-PF11.Signal=ADC1_INP2
-PF14.Locked=true
-PF14.Mode=SMBus-two-wire-Interface
-PF14.Signal=I2C4_SCL
-PF15.Locked=true
-PF15.Mode=SMBus-two-wire-Interface
-PF15.Signal=I2C4_SDA
-PF2.Locked=true
-PF2.Signal=GPIO_Output
-PF3.Locked=true
-PF3.Mode=IN5-Single-Ended
-PF3.Signal=ADC3_INP5
-PF4.Locked=true
-PF4.Mode=IN9-Single-Ended
-PF4.Signal=ADC3_INP9
-PF5.Locked=true
-PF5.Mode=IN4-Single-Ended
-PF5.Signal=ADC3_INP4
-PF6.Locked=true
-PF6.Signal=GPIO_Input
-PG12.Locked=true
-PG12.Mode=Full_Duplex_Master
-PG12.Signal=SPI6_MISO
-PG13.Locked=true
-PG13.Mode=Full_Duplex_Master
-PG13.Signal=SPI6_SCK
-PG14.Locked=true
-PG14.Mode=Full_Duplex_Master
-PG14.Signal=SPI6_MOSI
-PG8.Locked=true
-PG8.Mode=NSS_Signal_Hard_Output
-PG8.Signal=SPI6_NSS
-PH0-OSC_IN\ (PH0).Locked=true
-PH0-OSC_IN\ (PH0).Mode=HSE-External-Clock-Source
-PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
-PH1-OSC_OUT\ (PH1).Mode=HSE-External-Clock-Source
-PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=false
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32H743ZITx
-ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.3.0
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=0
-ProjectManager.MainLocation=Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=SW4STM32
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=KugleFirmware.ioc
-ProjectManager.ProjectName=KugleFirmware
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=SW4STM32
-ProjectManager.ToolChainLocation=
-ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_ADC3_Init-ADC3-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_TIM1_Init-TIM1-false-HAL-true,8-MX_TIM8_Init-TIM8-false-HAL-true,9-MX_TIM2_Init-TIM2-false-HAL-true,10-MX_TIM3_Init-TIM3-false-HAL-true,11-MX_TIM4_Init-TIM4-false-HAL-true,12-MX_TIM15_Init-TIM15-false-HAL-true,13-MX_TIM17_Init-TIM17-false-HAL-true,14-MX_SPI3_Init-SPI3-false-HAL-true,15-MX_SPI6_Init-SPI6-false-HAL-true,16-MX_USART3_UART_Init-USART3-false-HAL-true,17-MX_UART7_Init-UART7-false-HAL-true,18-MX_UART4_Init-UART4-false-HAL-true,19-MX_I2C2_SMBUS_Init-I2C2-false-HAL-true,20-MX_I2C4_SMBUS_Init-I2C4-false-HAL-true,21-MX_I2C3_Init-I2C3-false-HAL-true,22-MX_I2C1_Init-I2C1-false-HAL-true,23-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true
-RCC.ADCFreq_Value=80000000
-RCC.AHB12Freq_Value=200000000
-RCC.AHB4Freq_Value=200000000
-RCC.APB1Freq_Value=100000000
-RCC.APB2Freq_Value=100000000
-RCC.APB3Freq_Value=100000000
-RCC.APB4Freq_Value=100000000
-RCC.AXIClockFreq_Value=200000000
-RCC.CECFreq_Value=32000
-RCC.CKPERFreq_Value=8000000
-RCC.CKPERSourceSelection=RCC_CLKPSOURCE_HSE
-RCC.CPU2Freq_Value=200000000
-RCC.CPU2SystikFreq_Value=200000000
-RCC.CortexFreq_Value=400000000
-RCC.CpuClockFreq_Value=400000000
-RCC.D1CPREFreq_Value=400000000
-RCC.D1PPRE=RCC_APB3_DIV2
-RCC.D2PPRE1=RCC_APB1_DIV2
-RCC.D2PPRE2=RCC_APB2_DIV2
-RCC.D3PPRE=RCC_APB4_DIV2
-RCC.DFSDMACLkFreq_Value=200000000
-RCC.DFSDMFreq_Value=100000000
-RCC.DIVM1=1
-RCC.DIVM2=1
-RCC.DIVM3=1
-RCC.DIVN1=100
-RCC.DIVN2=50
-RCC.DIVN3=42
-RCC.DIVP1Freq_Value=400000000
-RCC.DIVP2=5
-RCC.DIVP2Freq_Value=80000000
-RCC.DIVP3Freq_Value=168000000
-RCC.DIVQ1=4
-RCC.DIVQ1Freq_Value=200000000
-RCC.DIVQ2=5
-RCC.DIVQ2Freq_Value=80000000
-RCC.DIVQ3=7
-RCC.DIVQ3Freq_Value=48000000
-RCC.DIVR1Freq_Value=400000000
-RCC.DIVR2Freq_Value=200000000
-RCC.DIVR3Freq_Value=168000000
-RCC.FDCANFreq_Value=200000000
-RCC.FMCFreq_Value=200000000
-RCC.FamilyName=M
-RCC.HCLK3ClockFreq_Value=200000000
-RCC.HCLKFreq_Value=200000000
-RCC.HPRE=RCC_HCLK_DIV2
-RCC.HRTIMFreq_Value=200000000
-RCC.HSE_VALUE=8000000
-RCC.I2C123Freq_Value=100000000
-RCC.I2C4Freq_Value=100000000
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CKPERSourceSelection,CPU2Freq_Value,CPU2SystikFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
-RCC.LPTIM1Freq_Value=100000000
-RCC.LPTIM2Freq_Value=100000000
-RCC.LPTIM345Freq_Value=100000000
-RCC.LPUART1Freq_Value=100000000
-RCC.LTDCFreq_Value=168000000
-RCC.MCO1PinFreq_Value=64000000
-RCC.MCO2PinFreq_Value=400000000
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.QSPIFreq_Value=200000000
-RCC.RNGFreq_Value=48000000
-RCC.RTCFreq_Value=32000
-RCC.SAI1Freq_Value=200000000
-RCC.SAI23Freq_Value=200000000
-RCC.SAI4AFreq_Value=200000000
-RCC.SAI4BFreq_Value=200000000
-RCC.SDMMCFreq_Value=200000000
-RCC.SPDIFRXFreq_Value=200000000
-RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL2
-RCC.SPI123Freq_Value=80000000
-RCC.SPI45Freq_Value=100000000
-RCC.SPI6CLockSelection=RCC_SPI6CLKSOURCE_PLL2
-RCC.SPI6Freq_Value=80000000
-RCC.SWPMI1Freq_Value=100000000
-RCC.SYSCLKFreq_VALUE=400000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.Tim1OutputFreq_Value=200000000
-RCC.Tim2OutputFreq_Value=200000000
-RCC.TraceFreq_Value=400000000
-RCC.USART16Freq_Value=100000000
-RCC.USART234578Freq_Value=100000000
-RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
-RCC.USBFreq_Value=48000000
-RCC.VCO1OutputFreq_Value=800000000
-RCC.VCO2OutputFreq_Value=400000000
-RCC.VCO3OutputFreq_Value=336000000
-RCC.VCOInput1Freq_Value=8000000
-RCC.VCOInput2Freq_Value=8000000
-RCC.VCOInput3Freq_Value=8000000
-SH.ADCx_INP10.0=ADC2_INP10,IN10-Single-Ended
-SH.ADCx_INP10.ConfNb=1
-SH.ADCx_INP11.0=ADC2_INP11,IN11-Single-Ended
-SH.ADCx_INP11.ConfNb=1
-SH.ADCx_INP8.0=ADC1_INP8,IN8-Single-Ended
-SH.ADCx_INP8.ConfNb=1
-SH.GPXTI1.0=GPIO_EXTI1
-SH.GPXTI1.ConfNb=1
-SH.GPXTI13.0=GPIO_EXTI13
-SH.GPXTI13.ConfNb=1
-SH.GPXTI14.0=GPIO_EXTI14
-SH.GPXTI14.ConfNb=1
-SH.GPXTI15.0=GPIO_EXTI15
-SH.GPXTI15.ConfNb=1
-SH.GPXTI2.0=GPIO_EXTI2
-SH.GPXTI2.ConfNb=1
-SH.GPXTI3.0=GPIO_EXTI3
-SH.GPXTI3.ConfNb=1
-SH.GPXTI6.0=GPIO_EXTI6
-SH.GPXTI6.ConfNb=1
-SH.S_TIM15_CH1.0=TIM15_CH1,PWM Generation1 CH1
-SH.S_TIM15_CH1.ConfNb=1
-SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
-SH.S_TIM1_CH1.ConfNb=1
-SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2
-SH.S_TIM1_CH2.ConfNb=1
-SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3
-SH.S_TIM1_CH3.ConfNb=1
-SH.S_TIM2_CH1.0=TIM2_CH1,Encoder_Interface
-SH.S_TIM2_CH1.ConfNb=1
-SH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface
-SH.S_TIM2_CH2.ConfNb=1
-SH.S_TIM3_CH1.0=TIM3_CH1,Encoder_Interface
-SH.S_TIM3_CH1.ConfNb=1
-SH.S_TIM3_CH2.0=TIM3_CH2,Encoder_Interface
-SH.S_TIM3_CH2.ConfNb=1
-SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface
-SH.S_TIM4_CH1.ConfNb=1
-SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface
-SH.S_TIM4_CH2.ConfNb=1
-SH.S_TIM8_CH1.0=TIM8_CH1,PWM Generation1 CH1
-SH.S_TIM8_CH1.ConfNb=1
-SH.S_TIM8_CH2.0=TIM8_CH2,PWM Generation2 CH2
-SH.S_TIM8_CH2.ConfNb=1
-SH.S_TIM8_CH3.0=TIM8_CH3,PWM Generation3 CH3
-SH.S_TIM8_CH3.ConfNb=1
-SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
-SPI3.CLKPhase=SPI_PHASE_2EDGE
-SPI3.CLKPolarity=SPI_POLARITY_HIGH
-SPI3.CalculateBaudRate=20.0 MBits/s
-SPI3.DataSize=SPI_DATASIZE_8BIT
-SPI3.Direction=SPI_DIRECTION_2LINES
-SPI3.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate,TIMode,DataSize,CLKPolarity,CLKPhase
-SPI3.Mode=SPI_MODE_MASTER
-SPI3.TIMode=SPI_TIMODE_DISABLE
-SPI3.VirtualType=VM_MASTER
-SPI6.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
-SPI6.CLKPhase=SPI_PHASE_2EDGE
-SPI6.CLKPolarity=SPI_POLARITY_HIGH
-SPI6.CalculateBaudRate=20.0 MBits/s
-SPI6.DataSize=SPI_DATASIZE_8BIT
-SPI6.Direction=SPI_DIRECTION_2LINES
-SPI6.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,DataSize,CLKPolarity,CLKPhase,BaudRatePrescaler
-SPI6.Mode=SPI_MODE_MASTER
-SPI6.VirtualNSS=VM_NSSHARD
-SPI6.VirtualType=VM_MASTER
-TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
-TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
-TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
-TIM1.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Prescaler,Period
-TIM1.Period=999
-TIM1.Prescaler=49
-TIM15.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
-TIM15.IPParameters=Channel-PWM Generation1 CH1,Period,Prescaler
-TIM15.Period=999
-TIM15.Prescaler=1999
-TIM17.Channel=TIM_CHANNEL_1
-TIM17.IPParameters=Channel,Period,Prescaler,OCNPolarity_1
-TIM17.OCNPolarity_1=TIM_OCNPOLARITY_LOW
-TIM17.Period=999
-TIM17.Prescaler=1999
-TIM2.EncoderMode=TIM_ENCODERMODE_TI12
-TIM2.IPParameters=EncoderMode,Period
-TIM2.Period=65535
-TIM3.EncoderMode=TIM_ENCODERMODE_TI12
-TIM3.IPParameters=Period,EncoderMode
-TIM3.Period=65535
-TIM4.EncoderMode=TIM_ENCODERMODE_TI12
-TIM4.IPParameters=Period,EncoderMode
-TIM4.Period=65535
-TIM8.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
-TIM8.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
-TIM8.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
-TIM8.IPParameters=Prescaler,Period,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3
-TIM8.Period=999
-TIM8.Prescaler=49
-USART3.IPParameters=VirtualMode-Asynchronous
-USART3.VirtualMode-Asynchronous=VM_ASYNC
-USB_DEVICE.CLASS_NAME_FS=CDC
-USB_DEVICE.IPParameters=VirtualMode-CDC_FS,VirtualModeFS,CLASS_NAME_FS
-USB_DEVICE.VirtualMode-CDC_FS=Cdc
-USB_DEVICE.VirtualModeFS=Cdc_FS
-USB_OTG_FS.IPParameters=VirtualMode
-USB_OTG_FS.VirtualMode=Device_Only
-VP_FREERTOS_VS_ENABLE.Mode=Enabled
-VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE
-VP_SYS_VS_tim16.Mode=TIM16
-VP_SYS_VS_tim16.Signal=SYS_VS_tim16
-VP_TIM15_VS_ClockSourceINT.Mode=Internal
-VP_TIM15_VS_ClockSourceINT.Signal=TIM15_VS_ClockSourceINT
-VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer
-VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT
-VP_TIM1_VS_ClockSourceINT.Mode=Internal
-VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
-VP_TIM8_VS_ClockSourceINT.Mode=Internal
-VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
-VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
-VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
-board=custom
diff --git a/KugleFirmware/KugleFirmware.xml b/KugleFirmware/KugleFirmware.xml
deleted file mode 100644
index 931b7ee..0000000
--- a/KugleFirmware/KugleFirmware.xml
+++ /dev/null
@@ -1,9 +0,0 @@
-
-
-
- KugleFirmware
- STM32H743ZITx
- SWD
- ST-LinkV2-1
-
-
diff --git a/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.cpp b/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.cpp
deleted file mode 100644
index 1b1914a..0000000
--- a/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.cpp
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "ApplicationTemplate.h"
-#include "cmsis_os.h"
-
-ApplicationTemplate::ApplicationTemplate() : _TaskHandle(0), _isRunning(false), _shouldStop(false)
-{
- _params = new Parameters;
-
- Start();
-}
-
-ApplicationTemplate::~ApplicationTemplate()
-{
- _shouldStop = true;
- while (_isRunning) osDelay(10);
-}
-
-int ApplicationTemplate::Start()
-{
- if (_isRunning) return 0; // task already running
- _shouldStop = false;
- return xTaskCreate( ApplicationTemplate::Thread, (char *)"Application Template", THREAD_STACK_SIZE, (void*) this, THREAD_PRIORITY, &_TaskHandle);
-}
-
-int ApplicationTemplate::Stop(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
-
- _shouldStop = true;
-
- uint32_t timeout_millis = timeout;
- while (_isRunning && timeout_millis > 0) {
- osDelay(1);
- timeout_millis--;
- }
- if (_isRunning) return -1; // timeout trying to stop task
-
- return 1;
-}
-
-int ApplicationTemplate::Restart(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
- int errCode = Stop(timeout);
- if (errCode != 1) return errCode;
- return Start();
-}
-
-void ApplicationTemplate::Thread(void * pvParameters)
-{
- ApplicationTemplate * task = (ApplicationTemplate *)pvParameters;
- task->_isRunning = true;
-
- while (!task->_shouldStop) {
- /* THIS IS THE MAIN LOOP */
- osDelay(1000);
- }
-
- task->_isRunning = false;
- task->_TaskHandle = 0;
- vTaskDelete(NULL); // delete/stop this current task
-}
diff --git a/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.h b/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.h
deleted file mode 100644
index 132915e..0000000
--- a/KugleFirmware/Libraries/Applications/ApplicationTemplate/ApplicationTemplate.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef APPLICATION_TEMPLATE_H
-#define APPLICATION_TEMPLATE_H
-
-#include "cmsis_os.h"
-#include "Priorities.h"
-#include "Parameters.h"
-
-class ApplicationTemplate
-{
- private:
- const int THREAD_STACK_SIZE = 256; // depending on the resource usage in the main loop (Thread function) you might want to increase this STACK_SIZE value
- const uint32_t THREAD_PRIORITY = APPLICATION_TEMPLATE_PRIORITY; // modify the task priorities in "Priorities.h"
-
- public:
- ApplicationTemplate();
- ~ApplicationTemplate();
-
- int Start();
- int Stop(uint32_t timeout = 1000);
- int Restart(uint32_t timeout = 1000);
-
- private:
- static void Thread(void * pvParameters);
-
- private:
- TaskHandle_t _TaskHandle;
- bool _isRunning;
- bool _shouldStop;
-
- Parameters * _params;
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.cpp b/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.cpp
deleted file mode 100644
index a3d1ae6..0000000
--- a/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.cpp
+++ /dev/null
@@ -1,1451 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "BalanceController.h"
-#include "cmsis_os.h"
-
-#include "Parameters.h"
-#include "Debug.h"
-#include "LQR.h"
-#include "SlidingMode.h"
-#include "QuaternionVelocityControl.h"
-#include "VelocityLQR.h"
-#include "IIR.hpp"
-#include "QEKF.h"
-#include "MadgwickAHRS.h"
-#include "COMEKF.h"
-#include "VelocityEKF.h"
-#include "Kinematics.h"
-#include "WheelSlipDetector.h"
-#include "Quaternion.h"
-
-#include // for memcpy
-#include // for fminf, fmaxf
-
-BalanceController::BalanceController(IMU& imu_, ESCON& motor1_, ESCON& motor2_, ESCON& motor3_, LSPC& com_, Timer& microsTimer_, MTI200 * mti_) : TaskHandle_(0), isRunning_(false), shouldStop_(false), imu(imu_), motor1(motor1_), motor2(motor2_), motor3(motor3_), com(com_), microsTimer(microsTimer_), mti(mti_)
-{
- /* Create setpoint semaphores */
- BalanceReference.semaphore = xSemaphoreCreateBinary();
- if (BalanceReference.semaphore == NULL) {
- ERROR("Could not create Quaternion reference semaphore");
- return;
- }
- vQueueAddToRegistry(BalanceReference.semaphore, "Quaternion reference");
- xSemaphoreGive( BalanceReference.semaphore ); // give the semaphore the first time
-
- VelocityReference.semaphore = xSemaphoreCreateBinary();
- if (VelocityReference.semaphore == NULL) {
- ERROR("Could not create Velocity reference semaphore");
- return;
- }
- vQueueAddToRegistry(VelocityReference.semaphore, "Velocity reference");
- xSemaphoreGive( VelocityReference.semaphore ); // give the semaphore the first time
-
- /* Register message type callbacks */
- com.registerCallback(lspc::MessageTypesFromPC::CalibrateIMU, &CalibrateIMUCallback, (void *)this);
- com.registerCallback(lspc::MessageTypesFromPC::RestartController, &RestartControllerCallback, (void *)this);
- com.registerCallback(lspc::MessageTypesFromPC::QuaternionReference, &QuaternionReference_Callback, (void *)this);
- com.registerCallback(lspc::MessageTypesFromPC::AngularVelocityReference, &AngularVelocityReference_Callback, (void *)this);
- com.registerCallback(lspc::MessageTypesFromPC::BalanceControllerReference, &BalanceControllerReference_Callback, (void *)this);
- com.registerCallback(lspc::MessageTypesFromPC::VelocityReference, &VelocityReference_Callback, (void *)this);
-
- Start();
-}
-
-BalanceController::~BalanceController()
-{
- shouldStop_ = true;
- while (isRunning_) osDelay(10);
-
- /* Unregister message callbacks */
- com.unregisterCallback(lspc::MessageTypesFromPC::CalibrateIMU);
- com.unregisterCallback(lspc::MessageTypesFromPC::RestartController);
- com.unregisterCallback(lspc::MessageTypesFromPC::QuaternionReference);
- com.unregisterCallback(lspc::MessageTypesFromPC::AngularVelocityReference);
- com.unregisterCallback(lspc::MessageTypesFromPC::BalanceControllerReference);
- com.unregisterCallback(lspc::MessageTypesFromPC::VelocityReference);
-
- /* Delete semaphores */
- if (BalanceReference.semaphore) {
- vQueueUnregisterQueue(BalanceReference.semaphore);
- vSemaphoreDelete(BalanceReference.semaphore);
- }
-
- if (VelocityReference.semaphore) {
- vQueueUnregisterQueue(VelocityReference.semaphore);
- vSemaphoreDelete(VelocityReference.semaphore);
- }
-}
-
-int BalanceController::Start()
-{
- if (isRunning_) return 0; // task already running
- shouldStop_ = false;
- return xTaskCreate( BalanceController::Thread, (char *)"Balance Controller", THREAD_STACK_SIZE, (void*) this, THREAD_PRIORITY, &TaskHandle_);
-}
-
-int BalanceController::Stop(uint32_t timeout)
-{
- if (!isRunning_) return 0; // task not running
-
- shouldStop_ = true;
-
- uint32_t timeout_millis = timeout;
- while (isRunning_ && timeout_millis > 0) {
- osDelay(1);
- timeout_millis--;
- }
- if (isRunning_) return -1; // timeout trying to stop task
-
- return 1;
-}
-
-int BalanceController::Restart(uint32_t timeout)
-{
- if (!isRunning_) return 0; // task not running
- int errCode = Stop(timeout);
- if (errCode != 1) return errCode;
- return Start();
-}
-
-void BalanceController::Thread(void * pvParameters)
-{
- BalanceController * balanceController = (BalanceController *)pvParameters;
- TickType_t xLastWakeTime;
- uint32_t prevTimerValue; // used for measuring dt
- float timestamp, dt_compute, dt_compute2;
- balanceController->isRunning_ = true;
-
- /* Load initialized objects */
- IMU& imu = balanceController->imu;
- ESCON& motor1 = balanceController->motor1;
- ESCON& motor2 = balanceController->motor2;
- ESCON& motor3 = balanceController->motor3;
- LSPC& com = balanceController->com;
- Timer& microsTimer = balanceController->microsTimer;
-
- /* Create and load parameters */
- Parameters& params = *(new Parameters);
-
- /* Controller loop time / sample rate */
- TickType_t loopWaitTicks = configTICK_RATE_HZ / params.controller.SampleRate;
-
- /* Create and initialize controller and estimator objects */
- LQR& lqr = *(new LQR(params));
- SlidingMode& sm = *(new SlidingMode(params));
- QuaternionVelocityControl& velocityController = *(new QuaternionVelocityControl(params, &balanceController->microsTimer, 1.0f / params.controller.SampleRate));
- VelocityLQR& velocityLQR = *(new VelocityLQR(params, &balanceController->microsTimer, 1.0f / params.controller.SampleRate));
- QEKF& qEKF = *(new QEKF(params, &balanceController->microsTimer));
- Madgwick& madgwick = *(new Madgwick(params.controller.SampleRate, params.estimator.MadgwickBeta));
- VelocityEKF& velocityEKF = *(new VelocityEKF(params, &balanceController->microsTimer));
- COMEKF& comEKF = *(new COMEKF(params, &balanceController->microsTimer));
- Kinematics& kinematics = *(new Kinematics(params, &balanceController->microsTimer));
- WheelSlipDetector& wheelSlipDetector = *(new WheelSlipDetector(params, &balanceController->microsTimer));
- IIR accel_x_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
- IIR accel_y_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
- IIR accel_z_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
- IIR gyro_x_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
- IIR gyro_y_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
- IIR gyro_z_filt(params.estimator.SoftwareLPFcoeffs_a, params.estimator.SoftwareLPFcoeffs_b);
-
- IIR dx_filt(params.estimator.VelocityLPFcoeffs_a, params.estimator.VelocityLPFcoeffs_b);
- IIR dy_filt(params.estimator.VelocityLPFcoeffs_a, params.estimator.VelocityLPFcoeffs_b);
-
- /* Measurement variables */
- IMU::Measurement_t imuRaw;
- IMU::Measurement_t imuCorrected;
- IMU::Measurement_t imuFiltered;
- IMU::Estimates_t imuEstimates;
- MTI200::LastMeasurement_t MTImeas; // for logging
- IMU::Estimates_t MTIest;
- int32_t EncoderTicks[3];
- float EncoderAngle[3];
-
- /* Estimate covariance variables */
- float Cov_q[4*4];
- float Cov_dq[4*4];
- float Cov_bias[3*3];
- float Cov_dxy[2*2];
- float Cov_COM[2*2];
-
- /* Temporary variables */
- float dxy_kinematics_old[2];
- float q_tilt_integral[4]; // for logging of velocity controller
-
- /* Control output variables */
- float Torque[3];
- float TorqueDelivered[3];
- float WheelSlipRampGain = 1.0; // used for disabling during wheel slip
- float EquivalentControlPct = 1.0;
- int MotorDriverFailureCounts[3];
- float S[3]; // Sliding surface values
- float TorqueRampUpGain = 0;
- bool TorqueRampUpFinished = false;
-
- /* Control output filtering objects */
- FirstOrderLPF& Motor1_LPF = *(new FirstOrderLPF(1.0f/params.controller.SampleRate, params.controller.TorqueLPFtau));
- FirstOrderLPF& Motor2_LPF = *(new FirstOrderLPF(1.0f/params.controller.SampleRate, params.controller.TorqueLPFtau));
- FirstOrderLPF& Motor3_LPF = *(new FirstOrderLPF(1.0f/params.controller.SampleRate, params.controller.TorqueLPFtau));
-
-#if 0 // UNIT TESTS DISABLED
- if (!lqr.UnitTest()) {
- ERROR("LQR Unit test failed!");
- }
-
- if (!sm.UnitTest()) {
- ERROR("Sliding Mode Unit test failed!");
- }
-
- if (!qEKF.UnitTest()) {
- ERROR("qEKF Unit test failed!");
- }
-#endif
-
- /* Reset estimators */
- imu.Get(imuCorrected);
- imu.CorrectMeasurement(imuCorrected, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU); // do not correct gyroscope bias if Xsens IMU is used (since this is corrected internally by the Xsens Kalman filter)
- EncoderTicks[0] = motor1.GetEncoderRaw();
- EncoderTicks[1] = motor2.GetEncoderRaw();
- EncoderTicks[2] = motor3.GetEncoderRaw();
- EncoderAngle[0] = motor1.GetAngle();
- EncoderAngle[1] = motor2.GetAngle();
- EncoderAngle[2] = motor3.GetAngle();
- qEKF.Reset(imuCorrected.Accelerometer); // reset attitude estimator to current attitude, based on IMU
- madgwick.Reset(imuCorrected.Accelerometer[0], imuCorrected.Accelerometer[1], imuCorrected.Accelerometer[2]);
- velocityEKF.Reset(EncoderTicks);
- comEKF.Reset();
- kinematics.Reset(EncoderAngle);
-
- balanceController->StabilizeFilters(params, imu, qEKF, madgwick, velocityEKF, loopWaitTicks, 1.0f); // stabilize estimators for 1 second
-
- /* Reset COM estimate */
- balanceController->COM[0] = params.model.COM_X;
- balanceController->COM[1] = params.model.COM_Y;
- balanceController->COM[2] = params.model.COM_Z;
-
- /* Reset position estimate */
- balanceController->xy[0] = 0;
- balanceController->xy[1] = 0;
-
- /* Reset reference variables */
- HeadingQuaternion(balanceController->q, balanceController->q_ref); // attitude reference = upright with current heading
- balanceController->q_ref_setpoint[0] = balanceController->q_ref[0];
- balanceController->q_ref_setpoint[1] = balanceController->q_ref[1];
- balanceController->q_ref_setpoint[2] = balanceController->q_ref[2];
- balanceController->q_ref_setpoint[3] = balanceController->q_ref[3];
- balanceController->omega_ref_inertial[0] = 0; // zero angular velocity reference
- balanceController->omega_ref_inertial[1] = 0;
- balanceController->omega_ref_inertial[2] = 0;
- balanceController->omega_ref_body[0] = 0; // zero angular velocity reference
- balanceController->omega_ref_body[1] = 0;
- balanceController->omega_ref_body[2] = 0;
- balanceController->omega_ref_setpoint_frame = lspc::ParameterTypes::UNKNOWN_FRAME;
- balanceController->omega_ref_setpoint[0] = 0;
- balanceController->omega_ref_setpoint[1] = 0;
- balanceController->omega_ref_setpoint[2] = 0;
- balanceController->integrate_omega_ref_into_q_ref = false;
- balanceController->headingReference = HeadingFromQuaternion(balanceController->q);
- balanceController->headingVelocityReference = 0;
- balanceController->velocityReferenceFrame = lspc::ParameterTypes::UNKNOWN_FRAME;
- balanceController->velocityReference[0] = 0;
- balanceController->velocityReference[1] = 0;
- balanceController->velocityReference_inertial[0] = 0;
- balanceController->velocityReference_inertial[1] = 0;
- balanceController->ReferenceGenerationStep = 0; // only used if test reference generation is enabled
-
- /* Reset quaternion reference input */
- xSemaphoreTake( balanceController->BalanceReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
- balanceController->BalanceReference.frame = lspc::ParameterTypes::BODY_FRAME;
- balanceController->BalanceReference.time = 0;
- HeadingQuaternion(balanceController->q, balanceController->BalanceReference.q); // attitude reference = upright with current heading
- balanceController->BalanceReference.omega[0] = 0;
- balanceController->BalanceReference.omega[1] = 0;
- balanceController->BalanceReference.omega[2] = 0;
- balanceController->BalanceReference.angularVelocityOnly = false;
- xSemaphoreGive( balanceController->BalanceReference.semaphore ); // give semaphore back
-
- /* Reset velocity reference input */
- xSemaphoreTake( balanceController->VelocityReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
- balanceController->VelocityReference.frame = lspc::ParameterTypes::BODY_FRAME;
- balanceController->VelocityReference.time = 0;
- balanceController->VelocityReference.dx = 0;
- balanceController->VelocityReference.dy = 0;
- balanceController->VelocityReference.dyaw = 0;
- xSemaphoreGive( balanceController->VelocityReference.semaphore ); // give semaphore back
-
- /* Reset temporary variables */
- dxy_kinematics_old[0] = 0;
- dxy_kinematics_old[1] = 0;
- q_tilt_integral[0] = 1;
- q_tilt_integral[1] = 0;
- q_tilt_integral[2] = 0;
- q_tilt_integral[3] = 0;
- S[0] = 0;
- S[1] = 0;
- S[2] = 0;
-
- /* Disable motor outputs and set 0 torque - motors will be enabled when the controller is running (defined by the controller mode and type) */
- motor1.SetTorque(0);
- motor2.SetTorque(0);
- motor3.SetTorque(0);
- motor1.Disable();
- motor2.Disable();
- motor3.Disable();
- MotorDriverFailureCounts[0] = 0;
- MotorDriverFailureCounts[1] = 0;
- MotorDriverFailureCounts[2] = 0;
- EquivalentControlPct = 1.0;
- WheelSlipRampGain = 1.0;
-
- /* Main control loop */
- xLastWakeTime = xTaskGetTickCount();
- prevTimerValue = microsTimer.Get();
- while (!balanceController->shouldStop_) {
- /* Wait until time has been reached to make control loop periodic */
- vTaskDelayUntil(&xLastWakeTime, loopWaitTicks);
- params.Refresh(); // load current parameters from global parameter object
-
- uint32_t timerPrev = HAL_tic();
- float dt = microsTimer.GetDeltaTime(prevTimerValue);
- prevTimerValue = microsTimer.Get();
- timestamp = microsTimer.GetTime();
-
- /* Get measurements (sample) */
- imu.Get(imuRaw);
- /* Adjust the measurements according to the calibration */
- imuCorrected = imuRaw;
- imu.CorrectMeasurement(imuCorrected, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU); // do not correct gyroscope bias if Xsens IMU is used (since this is corrected internally by the Xsens Kalman filter)
-
- imuFiltered = imuCorrected;
- if (params.estimator.EnableSoftwareLPFfilters && !params.estimator.UseXsensIMU) {
- imuFiltered.Accelerometer[0] = accel_x_filt.Filter(imuCorrected.Accelerometer[0]);
- imuFiltered.Accelerometer[1] = accel_y_filt.Filter(imuCorrected.Accelerometer[1]);
- imuFiltered.Accelerometer[2] = accel_z_filt.Filter(imuCorrected.Accelerometer[2]);
- imuFiltered.Gyroscope[0] = gyro_x_filt.Filter(imuCorrected.Gyroscope[0]);
- imuFiltered.Gyroscope[1] = gyro_y_filt.Filter(imuCorrected.Gyroscope[1]);
- imuFiltered.Gyroscope[2] = gyro_z_filt.Filter(imuCorrected.Gyroscope[2]);
- }
-
- EncoderTicks[0] = motor1.GetEncoderRaw();
- EncoderTicks[1] = motor2.GetEncoderRaw();
- EncoderTicks[2] = motor3.GetEncoderRaw();
- EncoderAngle[0] = motor1.GetAngle();
- EncoderAngle[1] = motor2.GetAngle();
- EncoderAngle[2] = motor3.GetAngle();
-
- if (params.debug.EnableRawSensorOutput) {
- if (params.debug.UseFilteredIMUinRawSensorOutput)
- balanceController->SendRawSensors(params, imuFiltered, EncoderAngle);
- else
- balanceController->SendRawSensors(params, imuCorrected, EncoderAngle);
- }
-
- /* Attitude estimation */
- if (params.estimator.UseMadgwick) {
- madgwick.updateIMU(imuFiltered.Gyroscope[0], imuFiltered.Gyroscope[1], imuFiltered.Gyroscope[2], imuFiltered.Accelerometer[0], imuFiltered.Accelerometer[1], imuFiltered.Accelerometer[2]);
- madgwick.getQuaternion(balanceController->q);
- madgwick.getQuaternionDerivative(balanceController->dq);
- // Hack for Madgwick quaternion estimate covariance
- for (int m = 0; m < 4; m++) {
- for (int n = 0; n < 4; n++) {
- Cov_q[4*m + n] = 0;
- }
- }
- for (int d = 0; d < 4; d++) {
- Cov_q[4*d + d] = 3*1E-7; // set q covariance when MADGWICK is used
- }
- } else { // use QEKF
- if (params.estimator.UseHeadingEstimateFromXsensIMU && balanceController->mti) {
- balanceController->mti->GetEstimates(imuEstimates);
- float Xsens_Heading = HeadingFromQuaternion(imuEstimates.q);
- qEKF.Step(imuFiltered.Accelerometer, imuFiltered.Gyroscope, Xsens_Heading, params.estimator.EstimateBias);
- } else {
- qEKF.Step(imuFiltered.Accelerometer, imuFiltered.Gyroscope, params.estimator.EstimateBias);
- }
- qEKF.GetQuaternion(balanceController->q);
- qEKF.GetQuaternionDerivative(balanceController->dq);
- qEKF.GetGyroBias(balanceController->GyroBias);
- qEKF.GetQuaternionCovariance(Cov_q);
- qEKF.GetQuaternionDerivativeCovariance(Cov_dq);
- qEKF.GetBiasCovariance(Cov_bias);
- }
-
- /* Replace estimates with Xsens estimates */
- if (params.estimator.UseXsensIMU && params.estimator.UseXsensQuaternionEstimate) {
- imu.GetEstimates(imuEstimates);
- /* Extract estimated angular velocity before replacing quaternion with Xsens estimate */
- Quaternion_GetAngularVelocity_Body(balanceController->q, balanceController->dq, balanceController->omega_body);
-
- /* Replace quaternion estimate with Xsens estimate */
- balanceController->q[0] = imuEstimates.q[0];
- balanceController->q[1] = imuEstimates.q[1];
- balanceController->q[2] = imuEstimates.q[2];
- balanceController->q[3] = imuEstimates.q[3];
-
- /* Recompute quaternion derivative based on angular velocity estimate and newly updated quaternion estimate */
- Quaternion_GetDQ_FromBody(balanceController->q, balanceController->omega_body, balanceController->dq);
- }
-
- Quaternion_GetAngularVelocity_Body(balanceController->q, balanceController->dq, balanceController->omega_body);
-
- /* Independent heading requires dq to be decoupled around the yaw/heading axis */
- if (params.behavioural.IndependentHeading && !params.behavioural.YawVelocityBraking && !params.controller.DisableQdot) {
- float dq_tmp[4];
- dq_tmp[0] = balanceController->dq[0];
- dq_tmp[1] = balanceController->dq[1];
- dq_tmp[2] = balanceController->dq[2];
- dq_tmp[3] = balanceController->dq[3];
- HeadingIndependentQdot(dq_tmp, balanceController->q, balanceController->dq);
- }
-
- if (params.controller.DisableQdot) {
- balanceController->dq[0] = 0;
- balanceController->dq[1] = 0;
- balanceController->dq[2] = 0;
- balanceController->dq[3] = 0;
- }
-
- /* Compute kinematics-based velocity and update position estimate by trapezoidal integration */
- float dxy_kinematics[2];
- // compute velocity from encoder-based motor velocities and forward kinematics
- kinematics.EstimateMotorVelocity(EncoderAngle);
- kinematics.ForwardKinematics(balanceController->q, balanceController->dq, dxy_kinematics);
- if (params.estimator.PositionEstimateDefinedInCoR) {
- kinematics.ConvertBallToCoRvelocity(dxy_kinematics, balanceController->q, balanceController->dq, dxy_kinematics);
- }
- // Update position estimate by trapezoidal integration of kinematics-based velocity estimate
- balanceController->xy[0] += (dxy_kinematics_old[0] + dxy_kinematics[0]) / (2.0f * params.controller.SampleRate);
- balanceController->xy[1] += (dxy_kinematics_old[1] + dxy_kinematics[1]) / (2.0f * params.controller.SampleRate);
- // Save previous velocity estimate for usage in trapezoidal integration for position estimation
- dxy_kinematics_old[0] = dxy_kinematics[0];
- dxy_kinematics_old[1] = dxy_kinematics[1];
-
- /* If enabled, re-use the kinematics-based estimate as the velocity estimate for the controller */
- if (!params.estimator.UseVelocityEstimator) {
- if (params.estimator.UseCoRvelocity && !params.estimator.PositionEstimateDefinedInCoR) {
- kinematics.ConvertBallToCoRvelocity(dxy_kinematics, balanceController->q, balanceController->dq, balanceController->dxy); // put CoR velocity into dxy
- } else {
- // put ball velocity into dxy
- balanceController->dxy[0] = dxy_kinematics[0];
- balanceController->dxy[1] = dxy_kinematics[1];
- }
-
- if (params.estimator.EnableVelocityLPF) {
- balanceController->dxy[0] = dx_filt.Filter(balanceController->dxy[0]);
- balanceController->dxy[1] = dy_filt.Filter(balanceController->dxy[1]);
- }
- }
-
- /* Velocity estimation using velocity EKF */
- if (params.estimator.UseVelocityEstimator) {
- velocityEKF.Step(EncoderTicks, imuFiltered.Accelerometer, balanceController->q, Cov_q, balanceController->dq); // velocity estimator estimates the velocity of the center of the ball
- velocityEKF.GetVelocity(balanceController->dxy);
- velocityEKF.GetVelocityCovariance(Cov_dxy);
- }
-
- /* Center of Mass estimation */
- if (params.estimator.EstimateCOM && params.estimator.UseVelocityEstimator) { // can only estimate COM if velocity is also estimated (due to need of velocity estimate covariance)
- comEKF.Step(balanceController->dxy, Cov_dxy, balanceController->q, Cov_q, balanceController->dq);
- comEKF.GetCOM(balanceController->COM);
- comEKF.GetCOMCovariance(Cov_COM);
- }
-
- /* Send State Estimates message */
- balanceController->SendEstimates();
-
- /*Debug::printf("qEKF = [%.3f, %.3f, %.3f, %.3f]\n", balanceController->q[0], balanceController->q[1], balanceController->q[2], balanceController->q[3]);
- float YPR[3];
- Quaternion_quat2eul_zyx(balanceController->q, YPR);
- Debug::printf("Roll: %.2f, Pitch: %.2f, Yaw: %.2f\n", rad2deg(YPR[2]), rad2deg(YPR[1]), rad2deg(YPR[0]));
- //Debug::printf("%.3f\t%.3f\t%.3f\t%.3f\t%.3f\t%.3f\t%.3f\n", microsTimer.GetTime(), imuMeas.Accelerometer[0], imuMeas.Accelerometer[1], imuMeas.Accelerometer[2], imuMeas.Gyroscope[0], imuMeas.Gyroscope[1], imuMeas.Gyroscope[2]);*/
-
- /* Reference generation - get references */
- balanceController->ReferenceGeneration(params); // this function updates q_ref and omega_ref
-
- /* Compute internal q_ref, omega_ref_body and omega_ref_inertial based on mode and setpoints */
- /* Quaternion control enabled */
- if (params.controller.mode == lspc::ParameterTypes::QUATERNION_CONTROL) {
- // Get quaternion references
- if (xSemaphoreTake( balanceController->BalanceReference.semaphore, ( TickType_t ) 1) == pdTRUE) { // lock for reading
- if ((microsTimer.GetTime() - balanceController->BalanceReference.time) < params.controller.ReferenceTimeout) {
- balanceController->omega_ref_setpoint_frame = balanceController->BalanceReference.frame;
- balanceController->omega_ref_setpoint[0] = balanceController->BalanceReference.omega[0];
- balanceController->omega_ref_setpoint[1] = balanceController->BalanceReference.omega[1];
- balanceController->omega_ref_setpoint[2] = balanceController->BalanceReference.omega[2];
-
- if (balanceController->BalanceReference.angularVelocityOnly == false) {
- balanceController->integrate_omega_ref_into_q_ref = false;
- balanceController->q_ref_setpoint[0] = balanceController->BalanceReference.q[0];
- balanceController->q_ref_setpoint[1] = balanceController->BalanceReference.q[1];
- balanceController->q_ref_setpoint[2] = balanceController->BalanceReference.q[2];
- balanceController->q_ref_setpoint[3] = balanceController->BalanceReference.q[3];
- } else {
- balanceController->integrate_omega_ref_into_q_ref = true;
- }
- }
- else {
- // Reference too old - setting default upright reference
- HeadingQuaternion(balanceController->q_ref_setpoint, balanceController->q_ref_setpoint); // set q_ref_setpoint to the previously set heading and upright
- balanceController->omega_ref_setpoint_frame = lspc::ParameterTypes::INERTIAL_FRAME;
- balanceController->omega_ref_setpoint[0] = 0;
- balanceController->omega_ref_setpoint[1] = 0;
- balanceController->omega_ref_setpoint[2] = 0;
- balanceController->integrate_omega_ref_into_q_ref = false;
- }
- xSemaphoreGive( balanceController->BalanceReference.semaphore ); // give semaphore back
- }
-
- if (balanceController->omega_ref_setpoint_frame == lspc::ParameterTypes::BODY_FRAME) {
- balanceController->omega_ref_body[0] = balanceController->omega_ref_setpoint[0];
- balanceController->omega_ref_body[1] = balanceController->omega_ref_setpoint[1];
- balanceController->omega_ref_body[2] = balanceController->omega_ref_setpoint[2];
- Quaternion_RotateVector_Body2Inertial(balanceController->q, balanceController->omega_ref_body, balanceController->omega_ref_inertial);
- }
- else if (balanceController->BalanceReference.frame == lspc::ParameterTypes::INERTIAL_FRAME) {
- balanceController->omega_ref_inertial[0] = balanceController->omega_ref_setpoint[0];
- balanceController->omega_ref_inertial[1] = balanceController->omega_ref_setpoint[1];
- balanceController->omega_ref_inertial[2] = balanceController->omega_ref_setpoint[2];
- Quaternion_RotateVector_Inertial2Body(balanceController->q, balanceController->omega_ref_inertial, balanceController->omega_ref_body);
- }
- else { // unknown frame for quaternion control mode
- balanceController->omega_ref_body[0] = balanceController->omega_ref_setpoint[0];
- balanceController->omega_ref_body[1] = balanceController->omega_ref_setpoint[1];
- balanceController->omega_ref_body[2] = balanceController->omega_ref_setpoint[2];
- balanceController->omega_ref_inertial[0] = 0;
- balanceController->omega_ref_inertial[1] = 0;
- balanceController->omega_ref_inertial[2] = 0;
- }
-
- if (balanceController->integrate_omega_ref_into_q_ref) {
- // integrate omega_ref to update q_ref_setpoint
- if (balanceController->omega_ref_setpoint_frame == lspc::ParameterTypes::BODY_FRAME)
- Quaternion_Integration_Body(balanceController->q_ref, balanceController->omega_ref_body, dt, balanceController->q_ref_setpoint);
- else if (balanceController->BalanceReference.frame == lspc::ParameterTypes::INERTIAL_FRAME)
- Quaternion_Integration_Inertial(balanceController->q_ref, balanceController->omega_ref_inertial, dt, balanceController->q_ref_setpoint);
- }
-
- if (params.behavioural.IndependentHeading || (params.estimator.EnableIndependentHeadingAtWheelSlip && wheelSlipDetector.SlipDetected())) {
- HeadingIndependentReferenceManual(balanceController->q_ref_setpoint, balanceController->q, balanceController->q_ref);
- } else {
- balanceController->q_ref[0] = balanceController->q_ref_setpoint[0];
- balanceController->q_ref[1] = balanceController->q_ref_setpoint[1];
- balanceController->q_ref[2] = balanceController->q_ref_setpoint[2];
- balanceController->q_ref[3] = balanceController->q_ref_setpoint[3];
- }
- }
- else {
- // We are not in QUATERNION_CONTROL mode - se reset references related to the QUATERNION_CONTROL mode
- HeadingQuaternion(balanceController->q, balanceController->q_ref_setpoint); // set q_ref_setpoint to the current heading and upright
- balanceController->omega_ref_setpoint_frame = lspc::ParameterTypes::INERTIAL_FRAME;
- balanceController->omega_ref_setpoint[0] = 0;
- balanceController->omega_ref_setpoint[1] = 0;
- balanceController->omega_ref_setpoint[2] = 0;
- balanceController->integrate_omega_ref_into_q_ref = false;
- }
-
- /* Velocity control enabled */
- if (params.controller.mode == lspc::ParameterTypes::VELOCITY_CONTROL) {
- // Get velocity reference
- if (xSemaphoreTake( balanceController->VelocityReference.semaphore, ( TickType_t ) 1) == pdTRUE) { // lock for reading
- if ((microsTimer.GetTime() - balanceController->VelocityReference.time) < params.controller.ReferenceTimeout) {
- balanceController->velocityReferenceFrame = balanceController->VelocityReference.frame;
- balanceController->velocityReference[0] = balanceController->VelocityReference.dx;
- balanceController->velocityReference[1] = balanceController->VelocityReference.dy;
- balanceController->headingVelocityReference = balanceController->VelocityReference.dyaw;
- }
- else {
- // Reference too old - setting default upright reference
- balanceController->velocityReferenceFrame = lspc::ParameterTypes::INERTIAL_FRAME;
- balanceController->velocityReference[0] = 0;
- balanceController->velocityReference[1] = 0;
- balanceController->headingVelocityReference = 0;
- }
- xSemaphoreGive( balanceController->VelocityReference.semaphore ); // give semaphore back
- }
-
- balanceController->headingReference += balanceController->headingVelocityReference * dt;
- balanceController->omega_ref_inertial[0] = 0;
- balanceController->omega_ref_inertial[1] = 0;
- balanceController->omega_ref_inertial[2] = balanceController->headingVelocityReference;
- Quaternion_RotateVector_Inertial2Body(balanceController->q, balanceController->omega_ref_inertial, balanceController->omega_ref_body);
-
- if (params.behavioural.IndependentHeading || (params.estimator.EnableIndependentHeadingAtWheelSlip && wheelSlipDetector.SlipDetected())) {
- balanceController->headingReference = HeadingFromQuaternion(balanceController->q);
- }
-
- //velocityController.Step(balanceController->q, balanceController->dq, balanceController->dxy, balanceController->velocityReference, (balanceController->velocityReferenceFrame == lspc::ParameterTypes::HEADING_FRAME), balanceController->headingReference, balanceController->q_ref);
- /*velocityController.StepWithOmega(balanceController->q, balanceController->dq, balanceController->dxy, balanceController->velocityReference, (balanceController->velocityReferenceFrame == lspc::ParameterTypes::HEADING_FRAME), balanceController->headingReference, balanceController->q_ref, balanceController->omega_ref_body);
- velocityController.GetIntegral(q_tilt_integral);
- velocityController.GetFilteredVelocityReference_Inertial(balanceController->velocityReference_inertial); // store velocity reference with the filtered one used by the velocity controller (for logging purposes)
- */
- velocityLQR.Step(balanceController->xy, balanceController->q, balanceController->dxy, balanceController->dq, balanceController->velocityReference, (balanceController->velocityReferenceFrame == lspc::ParameterTypes::HEADING_FRAME), balanceController->headingReference, balanceController->headingVelocityReference, balanceController->q_ref, balanceController->omega_ref_body);
- velocityLQR.GetFilteredVelocityReference_Inertial(balanceController->velocityReference_inertial);
- }
- else {
- // We are not in VELOCITY_CONTROL mode - se reset references related to the VELOCITY_CONTROL mode
- balanceController->velocityReferenceFrame = lspc::ParameterTypes::INERTIAL_FRAME;
- balanceController->velocityReference[0] = 0;
- balanceController->velocityReference[1] = 0;
- balanceController->headingVelocityReference = 0;
- balanceController->headingReference = HeadingFromQuaternion(balanceController->q);
- }
-
- /* Wheel slip detector and equivalent control + q_dot ramp (to reduce the robot jumping on the ball during wheel slip) */
- if (params.estimator.EnableWheelSlipDetector) {
- wheelSlipDetector.Step(EncoderAngle);
- if (wheelSlipDetector.SlipDetected()) {
- WheelSlipRampGain = 0;
- }
- else if (WheelSlipRampGain < 1) {
- WheelSlipRampGain += dt / params.estimator.WheelSlipIncreaseTime;
- if (WheelSlipRampGain > 1)
- WheelSlipRampGain = 1;
-
- if (params.estimator.ReduceTorqueAtWheelSlip)
- TorqueRampUpGain = WheelSlipRampGain;
- }
-
- if (params.estimator.ReduceEquivalentControlAtWheelSlip)
- EquivalentControlPct = WheelSlipRampGain;
- else
- EquivalentControlPct = 1.0;
-
- if (params.estimator.ReduceQdotAtWheelSlip) {
- balanceController->dq[0] *= WheelSlipRampGain;
- balanceController->dq[1] *= WheelSlipRampGain;
- balanceController->dq[2] *= WheelSlipRampGain;
- balanceController->dq[3] *= WheelSlipRampGain;
- }
- }
-
- /* Compute control output based on references */
- if (params.controller.type == lspc::ParameterTypes::LQR_CONTROLLER && params.controller.mode != lspc::ParameterTypes::OFF) {
- lqr.Step(balanceController->q, balanceController->dq, balanceController->xy, balanceController->dxy, balanceController->COM, balanceController->q_ref, balanceController->omega_ref_body, Torque);
- } else if (params.controller.type == lspc::ParameterTypes::SLIDING_MODE_CONTROLLER && params.controller.mode != lspc::ParameterTypes::OFF) {
- // OBS. When running the Sliding Mode controller, inertial angular velocity reference is needed
- sm.Step(balanceController->q, balanceController->dq, balanceController->xy, balanceController->dxy, balanceController->COM, balanceController->q_ref, balanceController->omega_ref_body, EquivalentControlPct, Torque, S);
- } else {
- // Undefined controller mode, eg. OFF - set torque output to 0
- Torque[0] = 0;
- Torque[1] = 0;
- Torque[2] = 0;
- }
-
- /* Check if any of the torque outputs is NaN - if so, turn off the outputs */
- if (isnan(Torque[0]) || isnan(Torque[1]) || isnan(Torque[2])) {
- Torque[0] = 0;
- Torque[1] = 0;
- Torque[2] = 0;
- }
-
- /* Clamp the torque between configurable limits less than or equal to max output torque */
- float saturationTorque = params.model.SaturationTorqueOfMaxOutputTorque * params.model.MaxOutputTorque;
- Torque[0] = fmaxf(fminf(Torque[0], saturationTorque), -saturationTorque);
- Torque[1] = fmaxf(fminf(Torque[1], saturationTorque), -saturationTorque);
- Torque[2] = fmaxf(fminf(Torque[2], saturationTorque), -saturationTorque);
-
- /* Initial Torque ramp up */
- if (params.controller.TorqueRampUp) {
- if (params.controller.mode == lspc::ParameterTypes::OFF) {
- TorqueRampUpGain = 0;
- TorqueRampUpFinished = false;
- }
- else if (!TorqueRampUpFinished) { // if controller is running and ramp up is not finished
- Torque[0] *= TorqueRampUpGain;
- Torque[1] *= TorqueRampUpGain;
- Torque[2] *= TorqueRampUpGain;
-
- TorqueRampUpGain += 1.0f / (params.controller.TorqueRampUpTime * params.controller.SampleRate); // ramp up rate
- if (TorqueRampUpGain >= 1.0) {
- TorqueRampUpFinished = true;
- }
- }
- }
-
- /* Torque output LPF filtering */
- if (params.controller.EnableTorqueLPF && params.controller.mode != lspc::ParameterTypes::OFF) {
- Torque[0] = Motor1_LPF.Filter(Torque[0]);
- Torque[1] = Motor2_LPF.Filter(Torque[1]);
- Torque[2] = Motor3_LPF.Filter(Torque[2]);
- } else {
- Motor1_LPF.Reset();
- Motor2_LPF.Reset();
- Motor3_LPF.Reset();
- }
-
- if (params.controller.mode != lspc::ParameterTypes::OFF) {
- /* Set control output */
- motor1.SetOutputTorque(Torque[0]);
- motor2.SetOutputTorque(Torque[1]);
- motor3.SetOutputTorque(Torque[2]);
-
- /* Measure delivered torque feedback from ESCON drivers */
- TorqueDelivered[0] = motor1.GetAppliedOutputTorque();
- TorqueDelivered[1] = motor2.GetAppliedOutputTorque();
- TorqueDelivered[2] = motor3.GetAppliedOutputTorque();
-
- /* Detect motor driver failure mode - and if so, reset motor driver */
- if (params.controller.MotorFailureDetection && !params.debug.DisableMotorOutput) { // only run motor failure detection is output is actually enabled
- for (int i = 0; i < 3; i++) {
- //if (fabsf(Torque[i]) > 0.1 && fabsf((Torque[i] / TorqueDelivered[i]) - 1.0) > params.controller.MotorFailureThreshold) {
- if (fabsf(Torque[i]) > params.controller.MotorFailureThreshold && fabsf(Torque[i] - TorqueDelivered[i]) > params.controller.MotorFailureThreshold) {
- MotorDriverFailureCounts[i]++;
- } else {
- MotorDriverFailureCounts[i] = 0;
- }
- if (MotorDriverFailureCounts[i] > (params.controller.SampleRate * params.controller.MotorFailureDetectionTime)) {
- // Motor/motor driver failure detected
- MotorDriverFailureCounts[i] = 0;
- if (params.controller.StopAtMotorFailure) {
- // Disable motors
- motor1.Disable();
- motor2.Disable();
- motor3.Disable();
-
- // Change controller mode to OFF
- params.LockForChange();
- params.controller.mode = lspc::ParameterTypes::OFF;
- params.UnlockAfterChange();
- } else { // failing motor driver should be reset
- if (i == 0) {
- motor1.Disable();
- Motor1_LPF.Reset();
- }
- else if (i == 1) {
- motor2.Disable();
- Motor2_LPF.Reset();
- }
- else if (i == 2) {
- motor3.Disable();
- Motor3_LPF.Reset();
- }
- }
- }
- }
- }
- }
- if (params.controller.mode == lspc::ParameterTypes::OFF) {
- /* Delivered torque can not be measured when the motors are disabled */
- TorqueDelivered[0] = 0;
- TorqueDelivered[1] = 0;
- TorqueDelivered[2] = 0;
-
- /* Reset failure counts */
- MotorDriverFailureCounts[0] = 0;
- MotorDriverFailureCounts[1] = 0;
- MotorDriverFailureCounts[2] = 0;
-
- /* Reset wheel slip detector */
- wheelSlipDetector.Reset();
- WheelSlipRampGain = 1.0;
- EquivalentControlPct = 1.0;
-
- /* Reset reference variables */
- HeadingQuaternion(balanceController->q, balanceController->q_ref); // reset attitude reference to upright with current heading
- balanceController->q_ref_setpoint[0] = balanceController->q_ref[0];
- balanceController->q_ref_setpoint[1] = balanceController->q_ref[1];
- balanceController->q_ref_setpoint[2] = balanceController->q_ref[2];
- balanceController->q_ref_setpoint[3] = balanceController->q_ref[3];
- balanceController->omega_ref_inertial[0] = 0; // zero angular velocity reference
- balanceController->omega_ref_inertial[1] = 0;
- balanceController->omega_ref_inertial[2] = 0;
- balanceController->omega_ref_body[0] = 0; // zero angular velocity reference
- balanceController->omega_ref_body[1] = 0;
- balanceController->omega_ref_body[2] = 0;
- balanceController->omega_ref_setpoint_frame = lspc::ParameterTypes::UNKNOWN_FRAME;
- balanceController->omega_ref_setpoint[0] = 0;
- balanceController->omega_ref_setpoint[1] = 0;
- balanceController->omega_ref_setpoint[2] = 0;
- balanceController->integrate_omega_ref_into_q_ref = false;
- balanceController->headingReference = HeadingFromQuaternion(balanceController->q);
- balanceController->headingVelocityReference = 0;
- balanceController->velocityReferenceFrame = lspc::ParameterTypes::UNKNOWN_FRAME;
- balanceController->velocityReference[0] = 0;
- balanceController->velocityReference[1] = 0;
- balanceController->velocityReference_inertial[0] = 0;
- balanceController->velocityReference_inertial[1] = 0;
- balanceController->ReferenceGenerationStep = 0; // only used if test reference generation is enabled
-
- /* Reset controllers with internal states */
- velocityController.Reset();
- velocityLQR.Reset();
- }
-
- if (params.controller.mode != lspc::ParameterTypes::OFF && !params.debug.DisableMotorOutput) {
- /* Ensure that motor drivers are enabled */
- motor1.Enable();
- motor2.Enable();
- motor3.Enable();
- } else {
- /* Controller is disabled or DisableMotorOutput is enabled, so disable motor drivers */
- motor1.Disable();
- motor2.Disable();
- motor3.Disable();
- }
-
- /* Measure compute time */
- dt_compute = microsTimer.GetDeltaTime(prevTimerValue);
- dt_compute2 = HAL_toc(timerPrev);
-
- /* Send controller info package */
- balanceController->SendControllerInfo(params.controller.type, params.controller.mode, Torque, dt_compute, TorqueDelivered);
- balanceController->SendControllerDebug(q_tilt_integral, dxy_kinematics, Torque, S);
- //Debug::printf("Balance controller compute time: %9.7f s\n", dt_compute);
- //Debug::printf("Applied torque: %4.2f\t%4.2f\t%4.2f\n", TorqueApplied[0], TorqueApplied[1], TorqueApplied[2]);
-
- /* Get values from Xsens IMU (if available) for logging */
- if (balanceController->mti) {
- MTImeas = balanceController->mti->GetLastMeasurement();
- balanceController->mti->GetEstimates(MTIest);
- }
-
- if (params.debug.EnableDumpMessages) {
- /* Send mixed data for logging through MathDump channel */
- float mathDumpArray[] = {timestamp,
- imuFiltered.Accelerometer[0],
- imuFiltered.Accelerometer[1],
- imuFiltered.Accelerometer[2],
- imuFiltered.Gyroscope[0],
- imuFiltered.Gyroscope[1],
- imuFiltered.Gyroscope[2],
- imuFiltered.Magnetometer[0],
- imuFiltered.Magnetometer[1],
- imuFiltered.Magnetometer[2],
- balanceController->xy[0],
- balanceController->xy[1],
- balanceController->q[0],
- balanceController->q[1],
- balanceController->q[2],
- balanceController->q[3],
- balanceController->dxy[0],
- balanceController->dxy[1],
- balanceController->dq[0],
- balanceController->dq[1],
- balanceController->dq[2],
- balanceController->dq[3],
- balanceController->GyroBias[0],
- balanceController->GyroBias[1],
- balanceController->GyroBias[2],
- balanceController->COM[0],
- balanceController->COM[1],
- balanceController->COM[2],
- 1.0f*wheelSlipDetector.SlipDetected(0) + 10.0f*wheelSlipDetector.SlipDetected(1) + 100.0f*wheelSlipDetector.SlipDetected(2),
- balanceController->q_ref[0],
- balanceController->q_ref[1],
- balanceController->q_ref[2],
- balanceController->q_ref[3],
- balanceController->omega_ref_body[0],
- balanceController->omega_ref_body[1],
- balanceController->omega_ref_body[2],
- balanceController->velocityReference_inertial[0],
- balanceController->velocityReference_inertial[1],
- q_tilt_integral[0],
- q_tilt_integral[1],
- q_tilt_integral[2],
- q_tilt_integral[3],
- WheelSlipRampGain,
- S[0],
- S[1],
- S[2],
- dt_compute,
- Torque[0],
- Torque[1],
- Torque[2]
- };
- com.TransmitAsync(lspc::MessageTypesToPC::MathDump, (uint8_t *)&mathDumpArray, sizeof(mathDumpArray));
-
- /* Sensor dump */
- float sensorDumpArray[] = { timestamp,
- imuRaw.Accelerometer[0],
- imuRaw.Accelerometer[1],
- imuRaw.Accelerometer[2],
- imuRaw.Gyroscope[0],
- imuRaw.Gyroscope[1],
- imuRaw.Gyroscope[2],
- imuRaw.Magnetometer[0],
- imuRaw.Magnetometer[1],
- imuRaw.Magnetometer[2],
- EncoderAngle[0],
- EncoderAngle[1],
- EncoderAngle[2],
- TorqueDelivered[0],
- TorqueDelivered[1],
- TorqueDelivered[2],
- MTIest.q[0],
- MTIest.q[1],
- MTIest.q[2],
- MTIest.q[3],
- MTIest.dq[0],
- MTIest.dq[1],
- MTIest.dq[2],
- MTIest.dq[3],
- MTImeas.Accelerometer[0],
- MTImeas.Accelerometer[1],
- MTImeas.Accelerometer[2],
- MTImeas.Gyroscope[0],
- MTImeas.Gyroscope[1],
- MTImeas.Gyroscope[2],
- MTImeas.Magnetometer[0],
- MTImeas.Magnetometer[1],
- MTImeas.Magnetometer[2]
- };
- com.TransmitAsync(lspc::MessageTypesToPC::SensorDump, (uint8_t *)&sensorDumpArray, sizeof(sensorDumpArray));
-
- /* Covariance dump */
- float covarianceDumpArray[1 +
- sizeof(Cov_q)/sizeof(float) +
- sizeof(Cov_dq)/sizeof(float) +
- sizeof(Cov_bias)/sizeof(float) +
- sizeof(Cov_dxy)/sizeof(float) +
- sizeof(Cov_COM)/sizeof(float)];
- covarianceDumpArray[0] = timestamp;
- uint8_t * writePtr = (uint8_t *)&covarianceDumpArray[1];
- memcpy(writePtr, Cov_q, sizeof(Cov_q)); writePtr += sizeof(Cov_q);
- memcpy(writePtr, Cov_dq, sizeof(Cov_dq)); writePtr += sizeof(Cov_dq);
- memcpy(writePtr, Cov_bias, sizeof(Cov_bias)); writePtr += sizeof(Cov_bias);
- memcpy(writePtr, Cov_dxy, sizeof(Cov_dxy)); writePtr += sizeof(Cov_dxy);
- memcpy(writePtr, Cov_COM, sizeof(Cov_COM)); writePtr += sizeof(Cov_COM);
- com.TransmitAsync(lspc::MessageTypesToPC::CovarianceDump, (uint8_t *)&covarianceDumpArray, sizeof(covarianceDumpArray));
- }
- }
- /* End of control loop */
-
- /* Disable motor outputs */
- motor1.Disable();
- motor2.Disable();
- motor3.Disable();
-
- /* Clear controller and estimator objects */
- delete(¶ms);
- delete(&lqr);
- delete(&sm);
- delete(&velocityController);
- delete(&velocityLQR);
- delete(&qEKF);
- delete(&madgwick);
- delete(&velocityEKF);
- delete(&comEKF);
- delete(&kinematics);
- delete(&wheelSlipDetector);
- delete(&Motor1_LPF);
- delete(&Motor2_LPF);
- delete(&Motor3_LPF);
-
- /* Stop and delete task */
- balanceController->isRunning_ = false;
- balanceController->TaskHandle_ = 0;
- vTaskDelete(NULL); // delete/stop this current task
-}
-
-/* Initialize/stabilize estimators for certain stabilization time */
-void BalanceController::StabilizeFilters(Parameters& params, IMU& imu, QEKF& qEKF, Madgwick& madgwick, VelocityEKF& velocityEKF, TickType_t loopWaitTicks, float stabilizationTime)
-{
- TickType_t xLastWakeTime = xTaskGetTickCount();
- TickType_t finishTick = xLastWakeTime + configTICK_RATE_HZ * stabilizationTime;
-
- IMU::Measurement_t imuMeas;
- int32_t EncoderTicks[3];
- float Cov_q[4*4]; // set diagonal to something small (if Madgwick is used)
- Cov_q[4*0 + 0] = 3*1E-7;
- Cov_q[4*1 + 1] = 3*1E-7;
- Cov_q[4*2 + 2] = 3*1E-7;
- Cov_q[4*3 + 3] = 3*1E-7;
-
- while (xLastWakeTime < finishTick) {
- // Wait until time has been reached to make control loop periodic
- vTaskDelayUntil(&xLastWakeTime, loopWaitTicks);
-
- /* Get measurements (sample) */
- imu.Get(imuMeas);
- /* Adjust the measurements according to the calibration */
- imu.CorrectMeasurement(imuMeas, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU, !params.estimator.UseXsensIMU); // do not correct gyroscope bias if Xsens IMU is used (since this is corrected internally by the Xsens Kalman filter)
-
- /* Compute quaternion estimate */
- if (params.estimator.UseMadgwick) {
- madgwick.updateIMU(imuMeas.Gyroscope[0], imuMeas.Gyroscope[1], imuMeas.Gyroscope[2], imuMeas.Accelerometer[0], imuMeas.Accelerometer[1], imuMeas.Accelerometer[2], 0.1); // use larger beta to make filter converge to current angle by trusting the accelerometer more
- } else {
- qEKF.Step(imuMeas.Accelerometer, imuMeas.Gyroscope, false); // do not estimate bias while stabilizing the filter
- qEKF.GetQuaternionCovariance(Cov_q);
- }
-
- /* Compute velocity estimate */
- if (params.estimator.UseVelocityEstimator) {
- EncoderTicks[0] = motor1.GetEncoderRaw();
- EncoderTicks[1] = motor2.GetEncoderRaw();
- EncoderTicks[2] = motor3.GetEncoderRaw();
- velocityEKF.Step(EncoderTicks, imuMeas.Accelerometer, q, Cov_q, dq); // velocity estimator can estimate either CoR velocity or ball velocity
- }
- }
-}
-
-/* Reference generation based on selected test */
-void BalanceController::ReferenceGeneration(Parameters& params)
-{
- if (params.behavioural.StepTestEnabled) {
- float quaternion_reference[4];
- ReferenceGenerationStep++;
- if (ReferenceGenerationStep >= 20*params.controller.SampleRate) // reset after 20 seconds
- ReferenceGenerationStep = 0;
-
- if (ReferenceGenerationStep < 2*params.controller.SampleRate) { // from 0-2 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,0
- }
- else if (ReferenceGenerationStep < 4*params.controller.SampleRate) { // from 2-4 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(5), quaternion_reference); // rpy = 3,0,0
- }
- else if (ReferenceGenerationStep < 6*params.controller.SampleRate) { // from 4-6 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,0
- }
- else if (ReferenceGenerationStep < 8*params.controller.SampleRate) { // from 6-8 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(5), deg2rad(0), quaternion_reference); // rpy = 0,3,0
- }
- else if (ReferenceGenerationStep < 10*params.controller.SampleRate) { // from 8-10 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,0
- }
- else if (ReferenceGenerationStep < 12*params.controller.SampleRate) { // from 10-12 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(5), deg2rad(-5), quaternion_reference); // rpy = -3,3,0
- }
- else if (ReferenceGenerationStep < 14*params.controller.SampleRate) { // from 12-14 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,0
- }
- else if (ReferenceGenerationStep < 18*params.controller.SampleRate) { // from 14-18 seconds
- Quaternion_eul2quat_zyx(deg2rad(45), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,45
- }
- else if (ReferenceGenerationStep < 20*params.controller.SampleRate) { // from 18-20 seconds
- Quaternion_eul2quat_zyx(deg2rad(0), deg2rad(0), deg2rad(0), quaternion_reference); // rpy = 0,0,0
- }
-
- if (xSemaphoreTake( BalanceReference.semaphore, ( TickType_t ) 1) == pdTRUE) { // lock for updating
- BalanceReference.time = microsTimer.GetTime();
- BalanceReference.omega[0] = 0;
- BalanceReference.omega[1] = 0;
- BalanceReference.omega[2] = 0;
- BalanceReference.q[0] = quaternion_reference[0];
- BalanceReference.q[1] = quaternion_reference[1];
- BalanceReference.q[2] = quaternion_reference[2];
- BalanceReference.q[3] = quaternion_reference[3];
- BalanceReference.frame = lspc::ParameterTypes::BODY_FRAME;
- BalanceReference.angularVelocityOnly = false;
- xSemaphoreGive( BalanceReference.semaphore ); // give semaphore back
- }
- }
- else if (params.behavioural.SineTestEnabled) { // sine test with increasing frequency
- float quaternion_reference[4];
- float Amplitude = deg2rad(2);
- const float BaseFrequency = 0.5; // hz
- const float freqRate = 0.02; // hz pr. second
- float t = (float)ReferenceGenerationStep / params.controller.SampleRate;
- float freq = (BaseFrequency + freqRate*t);
- float g = 2*M_PI*freq*t;
- float f = Amplitude * sin(g);
- float dgdt = 2*M_PI* (freqRate*t + freq);
- float dfdt = Amplitude * cos(g) * dgdt;
- // Roll only
- Quaternion_eul2quat_zyx(0, 0, f, quaternion_reference);
- // Combined roll (sine wave) and pitch (cosine wave)
- //Quaternion_eul2quat_zyx(0, deg2rad(1) * cosf(2*M_PI * (float)ReferenceGenerationStep * SineFrequency / params.controller.SampleRate), deg2rad(3) * sinf(2*M_PI * (float)ReferenceGenerationStep * SineFrequency / params.controller.SampleRate), quaternion_reference);
- ReferenceGenerationStep++;
-
-
- if (xSemaphoreTake( BalanceReference.semaphore, ( TickType_t ) 1) == pdTRUE) { // lock for updating
- BalanceReference.time = microsTimer.GetTime();
- BalanceReference.omega[0] = dfdt; // deg2rad(3) * 2*M_PI*SineFrequency * cosf(2*M_PI * (float)ReferenceGenerationStep * SineFrequency / params.controller.SampleRate);
- BalanceReference.omega[1] = 0; //deg2rad(0) * 2*M_PI*SineFrequency * -sinf(2*M_PI * (float)ReferenceGenerationStep * SineFrequency / params.controller.SampleRate);
- BalanceReference.omega[2] = 0;
- BalanceReference.q[0] = quaternion_reference[0];
- BalanceReference.q[1] = quaternion_reference[1];
- BalanceReference.q[2] = quaternion_reference[2];
- BalanceReference.q[3] = quaternion_reference[3];
- BalanceReference.frame = lspc::ParameterTypes::BODY_FRAME;
- BalanceReference.angularVelocityOnly = false;
- xSemaphoreGive( BalanceReference.semaphore ); // give semaphore back
- }
- }
- else if (params.behavioural.CircleTestEnabled) { // constant inclination rotating in a circle around inertial z-axis with an increasing angular velocity
- float quaternion_reference_tmp[4];
- float Amplitude = deg2rad(3);
- float rotationIncreaseRate = 2*M_PI * 0.02; // rad/s^2
- float t = (float)ReferenceGenerationStep / params.controller.SampleRate;
- float psi = 0.5 * rotationIncreaseRate * t * t;
- float psi_dot = rotationIncreaseRate * t;
- quaternion_reference_tmp[0] = cos(Amplitude/2);
- quaternion_reference_tmp[1] = sin(Amplitude/2);
- quaternion_reference_tmp[2] = 0;
- quaternion_reference_tmp[3] = 0;
-
- float quaternion_reference[4];
- quaternion_reference[0] = quaternion_reference_tmp[0];
- quaternion_reference[1] = cosf(psi)*quaternion_reference_tmp[1] - sinf(psi)*quaternion_reference_tmp[2];
- quaternion_reference[2] = sinf(psi)*quaternion_reference_tmp[1] + cosf(psi)*quaternion_reference_tmp[2];
- quaternion_reference[3] = 0;
-
- float qdot_ref[4];
- qdot_ref[0] = 0;
- qdot_ref[1] = psi_dot * (-sinf(psi)*quaternion_reference_tmp[1] - cosf(psi)*quaternion_reference_tmp[2]);
- qdot_ref[2] = psi_dot * (cosf(psi)*quaternion_reference_tmp[1] - sinf(psi)*quaternion_reference_tmp[2]);
- qdot_ref[3] = 0;
-
- float omega_ref_body[3];
- Quaternion_GetAngularVelocity_Body(quaternion_reference, qdot_ref, omega_ref_body);
-
- ReferenceGenerationStep++;
-
- if (xSemaphoreTake( BalanceReference.semaphore, ( TickType_t ) 1) == pdTRUE) { // lock for updating
- BalanceReference.time = microsTimer.GetTime();
- BalanceReference.omega[0] = omega_ref_body[0];
- BalanceReference.omega[1] = omega_ref_body[1];
- BalanceReference.omega[2] = omega_ref_body[2];
- BalanceReference.q[0] = quaternion_reference[0];
- BalanceReference.q[1] = quaternion_reference[1];
- BalanceReference.q[2] = quaternion_reference[2];
- BalanceReference.q[3] = quaternion_reference[3];
- BalanceReference.frame = lspc::ParameterTypes::BODY_FRAME;
- BalanceReference.angularVelocityOnly = false;
- xSemaphoreGive( BalanceReference.semaphore ); // give semaphore back
- }
- }
- else {
- ReferenceGenerationStep = 0; // reset reference generation step such that we are ready when enabled
- }
-}
-
-void BalanceController::SendEstimates(void)
-{
- lspc::MessageTypesToPC::StateEstimates_t msg;
-
- msg.time = microsTimer.GetTime();
- msg.q.w = q[0];
- msg.q.x = q[1];
- msg.q.y = q[2];
- msg.q.z = q[3];
- msg.dq.w = dq[0];
- msg.dq.x = dq[1];
- msg.dq.y = dq[2];
- msg.dq.z = dq[3];
- msg.pos.x = xy[0];
- msg.pos.y = xy[1];
- msg.vel.x = dxy[0];
- msg.vel.y = dxy[1];
-
- com.TransmitAsync(lspc::MessageTypesToPC::StateEstimates, (uint8_t *)&msg, sizeof(msg));
-}
-
-void BalanceController::SendRawSensors(Parameters& params, const IMU::Measurement_t& imuMeas, const float EncoderAngle[3])
-{
- lspc::MessageTypesToPC::RawSensor_IMU_MPU9250_t imu_msg;
- lspc::MessageTypesToPC::RawSensor_Encoders_t encoders_msg;
-
- imu_msg.time = microsTimer.GetTime();
- imu_msg.accelerometer.x = imuMeas.Accelerometer[0];
- imu_msg.accelerometer.y = imuMeas.Accelerometer[1];
- imu_msg.accelerometer.z = imuMeas.Accelerometer[2];
-
- if (params.estimator.UseXsensIMU) {
- memcpy(imu_msg.accelerometer.cov, params.estimator.cov_acc_mti, sizeof(params.estimator.cov_acc_mti));
- memcpy(imu_msg.gyroscope.cov, params.estimator.cov_gyro_mti, sizeof(params.estimator.cov_gyro_mti));
- } else {
- memcpy(imu_msg.accelerometer.cov, params.estimator.cov_acc_mpu, sizeof(params.estimator.cov_acc_mpu));
- memcpy(imu_msg.gyroscope.cov, params.estimator.cov_gyro_mpu, sizeof(params.estimator.cov_gyro_mpu));
- }
- imu_msg.gyroscope.x = imuMeas.Gyroscope[0];
- imu_msg.gyroscope.y = imuMeas.Gyroscope[1];
- imu_msg.gyroscope.z = imuMeas.Gyroscope[2];
-
- imu_msg.magnetometer.x = imuMeas.Magnetometer[0];
- imu_msg.magnetometer.y = imuMeas.Magnetometer[1];
- imu_msg.magnetometer.z = imuMeas.Magnetometer[2];
-
- encoders_msg.time = microsTimer.GetTime();
- encoders_msg.angle1 = EncoderAngle[0];
- encoders_msg.angle2 = EncoderAngle[1];
- encoders_msg.angle3 = EncoderAngle[2];
-
- com.TransmitAsync(lspc::MessageTypesToPC::RawSensor_IMU_MPU9250, (uint8_t *)&imu_msg, sizeof(imu_msg));
- com.TransmitAsync(lspc::MessageTypesToPC::RawSensor_Encoders, (uint8_t *)&encoders_msg, sizeof(encoders_msg));
-}
-
-void BalanceController::SendControllerInfo(const lspc::ParameterTypes::controllerType_t Type, const lspc::ParameterTypes::controllerMode_t Mode, const float Torque[3], const float ComputeTime, const float TorqueDelivered[3])
-{
- lspc::MessageTypesToPC::ControllerInfo_t msg;
-
- msg.time = microsTimer.GetTime();
- msg.type = Type;
- msg.mode = Mode;
- msg.torque1 = Torque[0];
- msg.torque2 = Torque[1];
- msg.torque3 = Torque[2];
- msg.compute_time = ComputeTime;
- msg.delivered_torque1 = TorqueDelivered[0];
- msg.delivered_torque2 = TorqueDelivered[1];
- msg.delivered_torque3 = TorqueDelivered[2];
-
- com.TransmitAsync(lspc::MessageTypesToPC::ControllerInfo, (uint8_t *)&msg, sizeof(msg));
-}
-
-void BalanceController::SendControllerDebug(const float q_integral[4], const float velocity_kinematics[2], const float Torque[3], const float S[3])
-{
- lspc::MessageTypesToPC::ControllerDebug_t msg;
- float YPR[3];
-
- msg.time = microsTimer.GetTime();
-
- Quaternion_quat2eul_zyx(q, YPR);
- msg.orient.yaw = rad2deg(YPR[0]);
- msg.orient.pitch = rad2deg(YPR[1]);
- msg.orient.roll = rad2deg(YPR[2]);
-
- Quaternion_quat2eul_zyx(q_ref, YPR);
- msg.orient_ref.yaw = rad2deg(YPR[0]);
- msg.orient_ref.pitch = rad2deg(YPR[1]);
- msg.orient_ref.roll = rad2deg(YPR[2]);
-
- Quaternion_quat2eul_zyx(q_integral, YPR);
- msg.orient_integral.yaw = rad2deg(YPR[0]);
- msg.orient_integral.pitch = rad2deg(YPR[1]);
- msg.orient_integral.roll = rad2deg(YPR[2]);
-
- msg.omega.x = omega_body[0];
- msg.omega.y = omega_body[1];
- msg.omega.z = omega_body[2];
- msg.omega_ref.x = omega_ref_body[0];
- msg.omega_ref.y = omega_ref_body[1];
- msg.omega_ref.z = omega_ref_body[2];
- msg.vel.x = dxy[0];
- msg.vel.y = dxy[1];
- msg.vel_kinematics.x = velocity_kinematics[0];
- msg.vel_kinematics.y = velocity_kinematics[1];
- msg.vel_ref.x = velocityReference[0];
- msg.vel_ref.y = velocityReference[1];
- msg.torque[0] = Torque[0];
- msg.torque[1] = Torque[1];
- msg.torque[2] = Torque[2];
- msg.S[0] = S[0];
- msg.S[1] = S[1];
- msg.S[2] = S[2];
-
- com.TransmitAsync(lspc::MessageTypesToPC::ControllerDebug, (uint8_t *)&msg, sizeof(msg));
-}
-
-
-void BalanceController::CalibrateIMU(bool calibrateAccelerometer)
-{
- bool restartAfterCalibration = false;
- if (isRunning_) {
- Stop();
- restartAfterCalibration = true;
- }
-
- if (calibrateAccelerometer)
- imu.CalibrateAccelerometer(true);
- else
- imu.Calibrate(true); // calibrate only gyro bias and alignment
-
-
- if (restartAfterCalibration) {
- /*Debug::print("Restarting controller in 5 seconds...\n");
- osDelay(5000);*/
- Start();
- }
-}
-
-void BalanceController::CalibrateIMUCallback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
-
- lspc::MessageTypesFromPC::CalibrateIMU_t msg;
- lspc::MessageTypesToPC::CalibrateIMUAck_t msgAck;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- /* Should both check whether the magic key in the payload is correct and that the system is not balancing - otherwise calibration can not be performed */
- if (msg.magic_key != 0x12345678) {
- // Send acknowledge back to PC
- msgAck.acknowledged = false;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::CalibrateIMUAck, (uint8_t *)&msgAck, sizeof(msgAck));
- return;
- }
-
- /* Check current control mode as a calibration can not be performed if the robot is balancing */
- Parameters * params = new Parameters;
- lspc::ParameterTypes::controllerMode_t mode = params->controller.mode;
- delete(params);
- if (mode != lspc::ParameterTypes::OFF) {
- // Send acknowledge back to PC
- msgAck.acknowledged = false;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::CalibrateIMUAck, (uint8_t *)&msgAck, sizeof(msgAck));
- return;
- }
-
- /* Send acknowledge message back to PC */
- msgAck.acknowledged = true;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::CalibrateIMUAck, (uint8_t *)&msgAck, sizeof(msgAck));
-
- balanceController->CalibrateIMU(msg.calibrate_accelerometer);
-}
-
-
-void BalanceController::RestartControllerCallback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
-
- lspc::MessageTypesFromPC::RestartController_t msg;
- lspc::MessageTypesToPC::RestartControllerAck_t msgAck;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- /* Should both check whether the magic key in the payload is correct and that the system is not balancing - otherwise calibration can not be performed */
- if (msg.magic_key != 0x12345678) {
- // Send acknowledge back to PC
- msgAck.acknowledged = false;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::RestartControllerAck, (uint8_t *)&msgAck, sizeof(msgAck));
- return;
- }
-
- /* Check current control mode as a calibration can not be performed if the robot is balancing */
- Parameters * params = new Parameters;
- lspc::ParameterTypes::controllerMode_t mode = params->controller.mode;
- delete(params);
- if (mode != lspc::ParameterTypes::OFF) {
- // Send acknowledge back to PC
- msgAck.acknowledged = false;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::RestartControllerAck, (uint8_t *)&msgAck, sizeof(msgAck));
- return;
- }
-
- if (balanceController->isRunning_) {
- balanceController->Stop();
-
- /* Send acknowledge message back to PC */
- msgAck.acknowledged = true;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::RestartControllerAck, (uint8_t *)&msgAck, sizeof(msgAck));
-
- Debug::print("Restarting controller...\n");
- balanceController->Start();
- }
- else { // controller not running, so send NACK
- /* Send acknowledge message back to PC */
- msgAck.acknowledged = false;
- balanceController->com.TransmitAsync(lspc::MessageTypesToPC::RestartControllerAck, (uint8_t *)&msgAck, sizeof(msgAck));
-
- }
-}
-
-void BalanceController::QuaternionReference_Callback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
- if (!balanceController->BalanceReference.semaphore) return;
-
- volatile lspc::MessageTypesFromPC::QuaternionReference_t msg;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- xSemaphoreTake( balanceController->BalanceReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
-
- /* Update references with input values from message */
- balanceController->BalanceReference.time = balanceController->microsTimer.GetTime();
- balanceController->BalanceReference.frame = lspc::ParameterTypes::BODY_FRAME;
- balanceController->BalanceReference.q[0] = msg.q.w;
- balanceController->BalanceReference.q[1] = msg.q.x;
- balanceController->BalanceReference.q[2] = msg.q.y;
- balanceController->BalanceReference.q[3] = msg.q.z;
- balanceController->BalanceReference.omega[0] = 0; // only quaternion reference is specified in this package
- balanceController->BalanceReference.omega[1] = 0;
- balanceController->BalanceReference.omega[2] = 0;
- balanceController->BalanceReference.angularVelocityOnly = false;
-
- xSemaphoreGive( balanceController->BalanceReference.semaphore ); // give semaphore back
-}
-
-void BalanceController::AngularVelocityReference_Callback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
- if (!balanceController->BalanceReference.semaphore) return;
-
- volatile lspc::MessageTypesFromPC::AngularVelocityReference_t msg;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- xSemaphoreTake( balanceController->BalanceReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
-
- /* Update references with input values from message */
- balanceController->BalanceReference.time = balanceController->microsTimer.GetTime();
- balanceController->BalanceReference.frame = msg.frame;
- balanceController->BalanceReference.q[0] = 1; // only angular velocity reference is specified in this package
- balanceController->BalanceReference.q[1] = 0;
- balanceController->BalanceReference.q[2] = 0;
- balanceController->BalanceReference.q[3] = 0;
- balanceController->BalanceReference.omega[0] = msg.omega.x;
- balanceController->BalanceReference.omega[1] = msg.omega.y;
- balanceController->BalanceReference.omega[2] = msg.omega.z;
- balanceController->BalanceReference.angularVelocityOnly = true;
-
- xSemaphoreGive( balanceController->BalanceReference.semaphore ); // give semaphore back
-}
-
-void BalanceController::BalanceControllerReference_Callback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
- if (!balanceController->BalanceReference.semaphore) return;
-
- volatile lspc::MessageTypesFromPC::BalanceControllerReference_t msg;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- xSemaphoreTake( balanceController->BalanceReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
-
- /* Update references with input values from message */
- balanceController->BalanceReference.time = balanceController->microsTimer.GetTime();
- balanceController->BalanceReference.frame = msg.frame;
- balanceController->BalanceReference.q[0] = msg.q.w;
- balanceController->BalanceReference.q[1] = msg.q.x;
- balanceController->BalanceReference.q[2] = msg.q.y;
- balanceController->BalanceReference.q[3] = msg.q.z;
- balanceController->BalanceReference.omega[0] = msg.omega.x;
- balanceController->BalanceReference.omega[1] = msg.omega.y;
- balanceController->BalanceReference.omega[2] = msg.omega.z;
- balanceController->BalanceReference.angularVelocityOnly = false;
-
- xSemaphoreGive( balanceController->BalanceReference.semaphore ); // give semaphore back
-}
-
-void BalanceController::VelocityReference_Callback(void * param, const std::vector& payload)
-{
- BalanceController * balanceController = (BalanceController *)param;
- if (!balanceController) return;
- if (!balanceController->VelocityReference.semaphore) return;
-
- volatile lspc::MessageTypesFromPC::VelocityReference_t msg;
- if (payload.size() != sizeof(msg)) return;
- memcpy((uint8_t *)&msg, payload.data(), sizeof(msg));
-
- xSemaphoreTake( balanceController->VelocityReference.semaphore, ( TickType_t ) portMAX_DELAY); // lock for updating
-
- /* Update references with input values from message */
- balanceController->VelocityReference.time = balanceController->microsTimer.GetTime();
- balanceController->VelocityReference.frame = msg.frame;
- balanceController->VelocityReference.dx = msg.vel.x;
- balanceController->VelocityReference.dy = msg.vel.y;
- balanceController->VelocityReference.dyaw = msg.vel.yaw;
-
- xSemaphoreGive( balanceController->VelocityReference.semaphore ); // give semaphore back
-}
diff --git a/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.h b/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.h
deleted file mode 100644
index 604bab4..0000000
--- a/KugleFirmware/Libraries/Applications/BalanceController/BalanceController.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef APPLICATION_BALANCECONTROLLER_H
-#define APPLICATION_BALANCECONTROLLER_H
-
-#include "cmsis_os.h"
-#include "Priorities.h"
-#include "Parameters.h"
-#include "LSPC.hpp"
-#include "ESCON.h"
-#include "IMU.h"
-#include "Timer.h"
-#include "QuaternionVelocityControl.h"
-#include "LQR.h"
-#include "SlidingMode.h"
-#include "QEKF.h"
-#include "MadgwickAHRS.h"
-#include "COMEKF.h"
-#include "VelocityEKF.h"
-#include "MTI200.h" // for logging only, if available
-
-class BalanceController
-{
- private:
- const int THREAD_STACK_SIZE = 2500; // notice that this much stack is apparently necessary to avoid issues
- const uint32_t THREAD_PRIORITY = BALANCE_CONTROLLER_PRIORITY;
-
- public:
- BalanceController(IMU& imu_, ESCON& motor1_, ESCON& motor2_, ESCON& motor3_, LSPC& com_, Timer& microsTimer_, MTI200 * mti_ = 0);
- ~BalanceController();
-
- int Start();
- int Stop(uint32_t timeout = 1000);
- int Restart(uint32_t timeout = 1000);
-
- void CalibrateIMU(bool calibrateAccelerometer = false);
-
- private:
- void ReferenceGeneration(Parameters& params);
- void StabilizeFilters(Parameters& params, IMU& imu, QEKF& qEKF, Madgwick& madgwick, VelocityEKF& velocityEKF, TickType_t loopWaitTicks, float stabilizationTime);
-
- private:
- static void Thread(void * pvParameters);
- void SendEstimates(void);
- void SendRawSensors(Parameters& params, const IMU::Measurement_t& imuMeas, const float EncoderAngle[3]);
- void SendControllerInfo(const lspc::ParameterTypes::controllerType_t Type, const lspc::ParameterTypes::controllerMode_t Mode, const float Torque[3], const float ComputeTime, const float TorqueDelivered[3]);
- void SendControllerDebug(const float q_integral[4], const float velocity_kinematics[2], const float Torque[3], const float S[3]);
- static void CalibrateIMUCallback(void * param, const std::vector& payload);
- static void RestartControllerCallback(void * param, const std::vector& payload);
- static void QuaternionReference_Callback(void * param, const std::vector& payload);
- static void AngularVelocityReference_Callback(void * param, const std::vector& payload);
- static void BalanceControllerReference_Callback(void * param, const std::vector& payload);
- static void VelocityReference_Callback(void * param, const std::vector& payload);
-
- private:
- TaskHandle_t TaskHandle_;
- bool isRunning_;
- bool shouldStop_;
-
- private:
- IMU& imu;
- ESCON& motor1;
- ESCON& motor2;
- ESCON& motor3;
- LSPC& com;
- Timer& microsTimer;
- MTI200 * mti;
-
- // State estimates
- float xy[2];
- float q[4];
- float dq[4];
- float dxy[2];
- float COM[3];
- float GyroBias[3];
-
- // Internal or converted estimates
- float omega_body[3];
-
- // Internal references
- float q_ref[4];
- float q_ref_setpoint[4]; // used in QUATERNION_CONTROL mode to read reference into
- float omega_ref_body[3];
- float omega_ref_inertial[3];
- lspc::ParameterTypes::referenceFrame_t omega_ref_setpoint_frame;
- float omega_ref_setpoint[3];
- bool integrate_omega_ref_into_q_ref;
- lspc::ParameterTypes::referenceFrame_t velocityReferenceFrame;
- float velocityReference[2];
- float velocityReference_inertial[2]; // for debugging only
- float headingVelocityReference;
- float headingReference;
- int ReferenceGenerationStep;
-
- // Setpoints (settable references)
- // Consider to combine semaphores into 1 common setpoint/mode semaphore for all
- struct BalanceReference_t {
- SemaphoreHandle_t semaphore;
- lspc::ParameterTypes::referenceFrame_t frame;
- float time;
- float q[4];
- float omega[3];
- bool angularVelocityOnly; // used to indicate whether angular velocity reference should be integrated to generate quaternion reference (hence discarding the quaternion reference in this package)
- } BalanceReference;
-
- struct VelocityReference_t {
- SemaphoreHandle_t semaphore;
- lspc::ParameterTypes::referenceFrame_t frame;
- float time;
- float dx;
- float dy;
- float dyaw;
- } VelocityReference;
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Applications/Communication/Communication.cpp b/KugleFirmware/Libraries/Applications/Communication/Communication.cpp
deleted file mode 100644
index dcf1528..0000000
--- a/KugleFirmware/Libraries/Applications/Communication/Communication.cpp
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "Communication.h"
-#include "cmsis_os.h"
-
-Communication::Communication() : _TaskHandle(0), _isRunning(false), _shouldStop(false)
-{
- Start();
-}
-
-Communication::~Communication()
-{
- _shouldStop = true;
- while (_isRunning) osDelay(10);
-}
-
-int Communication::Start()
-{
- if (_isRunning) return 0; // task already running
- _shouldStop = false;
- return xTaskCreate( Communication::Thread, (char *)"Communication", THREAD_STACK_SIZE, (void*) this, THREAD_PRIORITY, &_TaskHandle);
-}
-
-int Communication::Stop(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
-
- _shouldStop = true;
-
- uint32_t timeout_millis = timeout;
- while (_isRunning && timeout_millis > 0) {
- osDelay(1);
- timeout_millis--;
- }
- if (_isRunning) return -1; // timeout trying to stop task
-
- return 1;
-}
-
-int Communication::Restart(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
- int errCode = Stop(timeout);
- if (errCode != 1) return errCode;
- return Start();
-}
-
-void Communication::Thread(void * pvParameters)
-{
- Communication * task = (Communication *)pvParameters;
- task->_isRunning = true;
-
- while (!task->_shouldStop) {
- osDelay(1);
- }
-
- task->_isRunning = false;
- task->_TaskHandle = 0;
- vTaskDelete(NULL); // delete/stop this current task
-}
-
diff --git a/KugleFirmware/Libraries/Applications/Communication/Communication.h b/KugleFirmware/Libraries/Applications/Communication/Communication.h
deleted file mode 100644
index 2101c25..0000000
--- a/KugleFirmware/Libraries/Applications/Communication/Communication.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef APPLICATION_COMMUNICATION_H
-#define APPLICATION_COMMUNICATION_H
-
-#include "cmsis_os.h"
-
-class Communication
-{
- private:
- const int THREAD_STACK_SIZE = 256;
- const uint32_t THREAD_PRIORITY = osPriorityNormal;
-
- public:
- Communication();
- ~Communication();
-
- int Start();
- int Stop(uint32_t timeout = 1000);
- int Restart(uint32_t timeout = 1000);
-
- private:
- static void Thread(void * pvParameters);
-
- private:
- TaskHandle_t _TaskHandle;
- bool _isRunning;
- bool _shouldStop;
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.cpp b/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.cpp
deleted file mode 100644
index e15af76..0000000
--- a/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.cpp
+++ /dev/null
@@ -1,207 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "FrontPanel.h"
-#include "cmsis_os.h"
-
-FrontPanel::FrontPanel(PowerManagement& powerManagement_, BalanceController& balanceController_, IO * powerButton_, IO * resetButton_, IO * calibrateButton_) : _TaskHandle(0), _isRunning(false), _shouldStop(false), powerManagement(powerManagement_), balanceController(balanceController_)
-{
- powerButton.btn = powerButton_;
- //powerButton.btn->RegisterInterrupt(IO::TRIGGER_RISING, PowerManagement::PowerButtonInterrupt, this);
- powerButton.callback = &PowerButtonPressed;
- powerButton.callbackParams = this;
- powerButton.debounceTime = DEBOUNCE_TIME;
- powerButton.debounceEndTime = 0;
- powerButton.prevState = powerButton.btn->Read();
-
- calibrateButton.btn = calibrateButton_;
- //calibrateButton.btn->RegisterInterrupt(IO::TRIGGER_RISING, PowerManagement::PowerButtonInterrupt, this);
- calibrateButton.callback = &CalibrateButtonPressed;
- calibrateButton.callbackParams = this;
- calibrateButton.debounceTime = 1.0f; // button should be held for 1 second to initiate
- calibrateButton.debounceEndTime = 0;
- calibrateButton.prevState = calibrateButton.btn->Read();
-
- resetButton.btn = resetButton_;
- //resetButton.btn->RegisterInterrupt(IO::TRIGGER_RISING, PowerManagement::PowerButtonInterrupt, this);
- resetButton.callback = &ResetButtonPressed;
- resetButton.callbackParams = this;
- resetButton.debounceTime = DEBOUNCE_TIME;
- resetButton.debounceEndTime = 0;
- resetButton.prevState = resetButton.btn->Read();
-
- _params = new Parameters;
-
- Start();
-}
-
-FrontPanel::~FrontPanel()
-{
- _shouldStop = true;
- while (_isRunning) osDelay(10);
-
- if (_params)
- delete(_params);
-}
-
-int FrontPanel::Start()
-{
- if (_isRunning) return 0; // task already running
- _shouldStop = false;
- return xTaskCreate( FrontPanel::Thread, (char *)"Front Panel", THREAD_STACK_SIZE, (void*) this, THREAD_PRIORITY, &_TaskHandle);
-}
-
-int FrontPanel::Stop(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
-
- _shouldStop = true;
-
- uint32_t timeout_millis = timeout;
- while (_isRunning && timeout_millis > 0) {
- osDelay(1);
- timeout_millis--;
- }
- if (_isRunning) return -1; // timeout trying to stop task
-
- return 1;
-}
-
-int FrontPanel::Restart(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
- int errCode = Stop(timeout);
- if (errCode != 1) return errCode;
- return Start();
-}
-
-void FrontPanel::Thread(void * pvParameters)
-{
- FrontPanel * fp = (FrontPanel *)pvParameters;
- fp->_isRunning = true;
-
- fp->powerManagement.SetPowerMode(PowerManagement::POWERMODE_ALL_ON);
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_ON);
-
- while (!fp->_shouldStop) {
- fp->ButtonHandler(fp->powerButton);
- fp->ButtonHandler(fp->calibrateButton);
- fp->ButtonHandler(fp->resetButton);
- osDelay(10);
- }
-
- fp->_isRunning = false;
- fp->_TaskHandle = 0;
- vTaskDelete(NULL); // delete/stop this current task
-}
-
-void FrontPanel::ButtonHandler(button_t& button)
-{
- if (button.btn->Read() != button.prevState) {
- if (button.debounceEndTime == 0) {
- button.debounceEndTime = xTaskGetTickCount() + (configTICK_RATE_HZ * button.debounceTime);
- } else {
- if (xTaskGetTickCount() > button.debounceEndTime) {
- button.debounceEndTime = 0;
- button.prevState = button.btn->Read();
-
- if (button.prevState) { // button pressed
- if (button.callback)
- button.callback(button.callbackParams);
- while (button.btn->Read()) osDelay(10); // wait until button release
- }
- }
- }
- } else {
- button.debounceEndTime = 0;
- }
-}
-
-void FrontPanel::PowerButtonPressed(void * params)
-{
- FrontPanel * fp = (FrontPanel*)params;
-
- fp->_params->Refresh();
-
- if (fp->_params->behavioural.PowerButtonMode == lspc::ParameterTypes::POWER_OFF) {
- PowerManagement::PowerMode_t powerMode = fp->powerManagement.GetPowerMode();
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_PULSING);
-
- if (powerMode != PowerManagement::POWERMODE_OFF) {
- fp->balanceController.Stop(5000);
- fp->powerManagement.SetPowerMode(PowerManagement::POWERMODE_OFF);
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_OFF);
- }
- else {
- fp->balanceController.Start();
- fp->powerManagement.SetPowerMode(PowerManagement::POWERMODE_ALL_ON);
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_ON);
- }
- }
-
- else if (fp->_params->behavioural.PowerButtonMode == lspc::ParameterTypes::START_STOP_QUATERNION_CONTROL) {
- if (fp->_params->controller.mode == lspc::ParameterTypes::OFF) {
- fp->_params->LockForChange();
- fp->_params->controller.mode = lspc::ParameterTypes::QUATERNION_CONTROL;
- fp->_params->UnlockAfterChange();
- }
- else {
- fp->_params->LockForChange();
- fp->_params->controller.mode = lspc::ParameterTypes::OFF;
- fp->_params->UnlockAfterChange();
- }
- }
-
- else if (fp->_params->behavioural.PowerButtonMode == lspc::ParameterTypes::START_STOP_VELOCITY_CONTROL) {
- if (fp->_params->controller.mode == lspc::ParameterTypes::OFF) {
- fp->_params->LockForChange();
- fp->_params->controller.mode = lspc::ParameterTypes::VELOCITY_CONTROL;
- fp->_params->UnlockAfterChange();
- }
- else {
- fp->_params->LockForChange();
- fp->_params->controller.mode = lspc::ParameterTypes::OFF;
- fp->_params->UnlockAfterChange();
- }
- }
-}
-
-void FrontPanel::ResetButtonPressed(void * params)
-{
- FrontPanel * fp = (FrontPanel*)params;
- NVIC_SystemReset();
-}
-
-void FrontPanel::CalibrateButtonPressed(void * params)
-{
- FrontPanel * fp = (FrontPanel*)params;
-
- PowerManagement::PowerMode_t powerMode = fp->powerManagement.GetPowerMode();
- fp->_params->Refresh();
-
- if (fp->_params->controller.mode == lspc::ParameterTypes::OFF) {
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_BLINKING_FAST);
-
- fp->balanceController.CalibrateIMU();
-
- if (powerMode == PowerManagement::POWERMODE_OFF)
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_OFF);
- else
- fp->powerManagement.SetLEDmode(PowerManagement::LEDMODE_ON);
- }
-}
diff --git a/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.h b/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.h
deleted file mode 100644
index 6b6e868..0000000
--- a/KugleFirmware/Libraries/Applications/FrontPanel/FrontPanel.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef APPLICATION_FRONTPANEL_H
-#define APPLICATION_FRONTPANEL_H
-
-#include "cmsis_os.h"
-#include "Priorities.h"
-#include "Parameters.h"
-#include "PowerManagement.h"
-#include "BalanceController.h"
-#include "IO.h"
-
-class FrontPanel
-{
- private:
- const int THREAD_STACK_SIZE = 512;
- const uint32_t THREAD_PRIORITY = FRONT_PANEL_PRIORITY;
- const float DEBOUNCE_TIME = 0.08; // 80 ms
-
- typedef struct button_t {
- IO * btn;
- void (*callback)(void * params);
- void * callbackParams;
- bool prevState;
- float debounceTime; // can also be used as hold time
- uint32_t debounceEndTime;
- };
-
- public:
- FrontPanel(PowerManagement& pm_, BalanceController& bc_, IO * powerButton_, IO * resetButton_, IO * calibrateButton_);
- ~FrontPanel();
-
- int Start();
- int Stop(uint32_t timeout = 1000);
- int Restart(uint32_t timeout = 1000);
-
- private:
- void ButtonHandler(button_t& button);
-
- private:
- static void Thread(void * pvParameters);
- static void PowerButtonPressed(void * params);
- static void ResetButtonPressed(void * params);
- static void CalibrateButtonPressed(void * params);
-
- private:
- TaskHandle_t _TaskHandle;
- bool _isRunning;
- bool _shouldStop;
-
- Parameters * _params;
-
- PowerManagement& powerManagement;
- BalanceController& balanceController;
-
- button_t powerButton;
- button_t resetButton;
- button_t calibrateButton;
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.cpp b/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.cpp
deleted file mode 100644
index 2b8fa2b..0000000
--- a/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.cpp
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "PathFollowingController.h"
-#include "cmsis_os.h"
-
-PathFollowingController::PathFollowingController() : _TaskHandle(0), _isRunning(false), _shouldStop(false)
-{
- Start();
-}
-
-PathFollowingController::~PathFollowingController()
-{
- _shouldStop = true;
- while (_isRunning) osDelay(10);
-}
-
-int PathFollowingController::Start()
-{
- if (_isRunning) return 0; // task already running
- _shouldStop = false;
- return xTaskCreate( PathFollowingController::Thread, (char *)"Path Following Controller", THREAD_STACK_SIZE, (void*) this, THREAD_PRIORITY, &_TaskHandle);
-}
-
-int PathFollowingController::Stop(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
-
- _shouldStop = true;
-
- uint32_t timeout_millis = timeout;
- while (_isRunning && timeout_millis > 0) {
- osDelay(1);
- timeout_millis--;
- }
- if (_isRunning) return -1; // timeout trying to stop task
-
- return 1;
-}
-
-int PathFollowingController::Restart(uint32_t timeout)
-{
- if (!_isRunning) return 0; // task not running
- int errCode = Stop(timeout);
- if (errCode != 1) return errCode;
- return Start();
-}
-
-void PathFollowingController::Thread(void * pvParameters)
-{
- PathFollowingController * task = (PathFollowingController *)pvParameters;
- task->_isRunning = true;
-
- while (!task->_shouldStop) {
- osDelay(1);
- }
-
- task->_isRunning = false;
- task->_TaskHandle = 0;
- vTaskDelete(NULL); // delete/stop this current task
-}
diff --git a/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.h b/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.h
deleted file mode 100644
index 8da429e..0000000
--- a/KugleFirmware/Libraries/Applications/PathFollowingController/PathFollowingController.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef APPLICATION_PATHFOLLOWINGCONTROLLER_H
-#define APPLICATION_PATHFOLLOWINGCONTROLLER_H
-
-#include "cmsis_os.h"
-
-class PathFollowingController
-{
- private:
- const int THREAD_STACK_SIZE = 256;
- const uint32_t THREAD_PRIORITY = osPriorityNormal;
-
- public:
- PathFollowingController();
- ~PathFollowingController();
-
- int Start();
- int Stop(uint32_t timeout = 1000);
- int Restart(uint32_t timeout = 1000);
-
- private:
- static void Thread(void * pvParameters);
-
- private:
- TaskHandle_t _TaskHandle;
- bool _isRunning;
- bool _shouldStop;
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Applications/This folder contains the code for each application thread.txt b/KugleFirmware/Libraries/Applications/This folder contains the code for each application thread.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/KugleFirmware/Libraries/Devices/Battery/Battery.cpp b/KugleFirmware/Libraries/Devices/Battery/Battery.cpp
deleted file mode 100644
index c51e88b..0000000
--- a/KugleFirmware/Libraries/Devices/Battery/Battery.cpp
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "Battery.h"
-
-Battery::Battery()
-{
-
-}
-
-Battery::~Battery()
-{
-
-}
diff --git a/KugleFirmware/Libraries/Devices/Battery/Battery.h b/KugleFirmware/Libraries/Devices/Battery/Battery.h
deleted file mode 100644
index 7d15cf5..0000000
--- a/KugleFirmware/Libraries/Devices/Battery/Battery.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef DEVICES_BATTERY_H
-#define DEVICES_BATTERY_H
-
-class Battery
-{
-
-public:
- Battery();
- ~Battery();
-
-private:
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Devices/ESCON/ESCON.cpp b/KugleFirmware/Libraries/Devices/ESCON/ESCON.cpp
deleted file mode 100644
index 1facfd2..0000000
--- a/KugleFirmware/Libraries/Devices/ESCON/ESCON.cpp
+++ /dev/null
@@ -1,254 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "ESCON.h"
-#include "stm32h7xx_hal.h"
-
-#include "Debug.h"
-#include "PWM.h"
-#include "IO.h"
-#include "ADC.h"
-#include "Encoder.h"
-
-ESCON::ESCON(PWM * TorqueSetpoint, IO * EnablePin, Encoder * encoder, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed) :
- ESCON_MAX_AMP_SETPOINT(MaxCurrent),
- MOTOR_TORQUE_CONSTANT(TorqueConstant),
- ENCODER_TICKS_PR_REV(EncoderTicksPrRev),
- GEARING_RATIO(GearRatio),
- ESCON_MAX_RAD_PR_SEC(MaxMotorSpeed),
- _torqueSetpoint(TorqueSetpoint),
- _enablePin(EnablePin),
- _encoder(encoder),
- _currentFeedback(0),
- _velocityFeedback(0),
- _directionFeedbackPin(0),
- _deleteObjectsAtDestruction(false)
-{
- SetTorque(0);
- Disable();
-}
-
-ESCON::ESCON(PWM * TorqueSetpoint, IO * EnablePin, Encoder * encoder, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed, ADC * CurrentFeedback, ADC * VelocityFeedback, IO * DirectionFeedbackPin) :
- ESCON_MAX_AMP_SETPOINT(MaxCurrent),
- MOTOR_TORQUE_CONSTANT(TorqueConstant),
- ENCODER_TICKS_PR_REV(EncoderTicksPrRev),
- GEARING_RATIO(GearRatio),
- ESCON_MAX_RAD_PR_SEC(MaxMotorSpeed),
- _torqueSetpoint(TorqueSetpoint),
- _enablePin(EnablePin),
- _encoder(encoder),
- _currentFeedback(CurrentFeedback),
- _velocityFeedback(VelocityFeedback),
- _directionFeedbackPin(DirectionFeedbackPin),
- _deleteObjectsAtDestruction(false)
-{
- SetTorque(0);
- Disable();
-}
-
-ESCON::ESCON(uint8_t MotorIndex, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed) :
- ESCON_MAX_AMP_SETPOINT(MaxCurrent),
- MOTOR_TORQUE_CONSTANT(TorqueConstant),
- ENCODER_TICKS_PR_REV(EncoderTicksPrRev),
- GEARING_RATIO(GearRatio),
- ESCON_MAX_RAD_PR_SEC(MaxMotorSpeed),
- _torqueSetpoint(0),
- _enablePin(0),
- _encoder(0),
- _currentFeedback(0),
- _velocityFeedback(0),
- _directionFeedbackPin(0),
- _deleteObjectsAtDestruction(true)
-{
- // Instantiate periphiral objects according to selected motor index
- if (MotorIndex == 1)
- {
- _torqueSetpoint = new PWM(PWM::TIMER1, PWM::CH1, ESCON_PWM_FREQUENCY, ESCON_PWM_RANGE);
- _enablePin = new IO(GPIOC, GPIO_PIN_6); // configure as output
- _currentFeedback = new ADC(ADC::ADC_3, ADC_CHANNEL_5, ADC_RESOLUTION_12B);
- _velocityFeedback = new ADC(ADC::ADC_3, ADC_CHANNEL_9, ADC_RESOLUTION_12B);
- _encoder = new Encoder(Encoder::TIMER2);
- _directionFeedbackPin = new IO(GPIOD, GPIO_PIN_2, IO::PULL_UP); // configure as input
- }
- else if (MotorIndex == 2)
- {
- _torqueSetpoint = new PWM(PWM::TIMER1, PWM::CH2, ESCON_PWM_FREQUENCY, ESCON_PWM_RANGE);
- _enablePin = new IO(GPIOC, GPIO_PIN_7); // configure as output
- _currentFeedback = new ADC(ADC::ADC_3, ADC_CHANNEL_4, ADC_RESOLUTION_12B);
- _velocityFeedback = new ADC(ADC::ADC_3, ADC_CHANNEL_6, ADC_RESOLUTION_12B);
- _encoder = new Encoder(Encoder::TIMER3);
- _directionFeedbackPin = new IO(GPIOD, GPIO_PIN_8, IO::PULL_UP); // configure as input
- }
- else if (MotorIndex == 3)
- {
- _torqueSetpoint = new PWM(PWM::TIMER1, PWM::CH3, ESCON_PWM_FREQUENCY, ESCON_PWM_RANGE);
- _enablePin = new IO(GPIOC, GPIO_PIN_8); // configure as output
- _currentFeedback = new ADC(ADC::ADC_2, ADC_CHANNEL_10, ADC_RESOLUTION_12B);
- _velocityFeedback = new ADC(ADC::ADC_2, ADC_CHANNEL_11, ADC_RESOLUTION_12B);
- _encoder = new Encoder(Encoder::TIMER4);
- _directionFeedbackPin = new IO(GPIOD, GPIO_PIN_9, IO::PULL_UP); // configure as input
- }
- else
- {
- ERROR("Incorrect motor index");
- return;
- }
-
- SetTorque(0);
- Disable();
-}
-
-ESCON::~ESCON()
-{
- if (_deleteObjectsAtDestruction) {
- if (_torqueSetpoint)
- delete(_torqueSetpoint);
- if (_velocityFeedback)
- delete(_velocityFeedback);
- if (_currentFeedback)
- delete(_currentFeedback);
- if (_encoder)
- delete(_encoder);
- }
-}
-
-void ESCON::Enable()
-{
- if (!_enablePin) return;
- _enablePin->Set(true);
-}
-
-void ESCON::Disable()
-{
- if (!_enablePin) return;
- _enablePin->Set(false);
-}
-
-// Set torque in Newton meters (Nm)
-// Returns a boolean indicating whether the applied torque was saturated/clipped
-bool ESCON::SetTorque(float torqueNewtonMeter)
-{
- if (!_torqueSetpoint) return false;
- bool didClip = false;
-
- // Torque is set as a current setpoint
- // The current setpoint is calculated from the desired torque using the torque constant
- float currentSetpoint = torqueNewtonMeter / MOTOR_TORQUE_CONSTANT;
-
- // The current setpoint is normalized to a range between -1 to 1 using the maximum current defined in ESCON controller
- float normalizedCurrentSetpoint = currentSetpoint / ESCON_MAX_AMP_SETPOINT;
-
- // Saturate/clip current setpoint
- if (normalizedCurrentSetpoint > 1.0f) {
- normalizedCurrentSetpoint = 1.0f;
- didClip = true;
- }
- else if (normalizedCurrentSetpoint < -1.0f) {
- normalizedCurrentSetpoint = -1.0f;
- didClip = true;
- }
-
- // The current setpoint is set with a PWM duty cycle between 10% to 90%
- // 10% = Maximum negative current
- // 90% = Maximum positive current
- // The normalized current range from -1 to 1 (range of 2) should thus be squeezed into the PWM range of 0.1 to 0.9 (range of 0.8)
- const float squeezeFactor = 0.8f / 2.0f;
-
- // Compute the PWM value by applying the squeeze factor and off-setting by the center value of 50% = 0.5
- float PWMvalue = 0.5f + squeezeFactor * normalizedCurrentSetpoint;
-
- // Update the PWM value
- _torqueSetpoint->Set(PWMvalue);
-
- return didClip;
-}
-
-// Set output shaft (after gearing) torque in Newton meters (Nm)
-// Returns a boolean indicating whether the applied torque was saturated/clipped
-bool ESCON::SetOutputTorque(float torqueNewtonMeter)
-{
- return SetTorque(torqueNewtonMeter / GEARING_RATIO);
-}
-
-// Return actual motor current reading in Amps (A)
-float ESCON::GetCurrent()
-{
- if (!_currentFeedback) return -1.0f;
- float AnalogReading = _currentFeedback->Read();
-
- // ESCON driver outputs an analog value from 0V to 3.3V
- // This range spans the normalized value from -1 to 1
- // However from the ADC reading we will get a value from 0 to 1, which we thus scale and offset accordingly
- float NormalizedCurrent = 2 * AnalogReading - 1.0f;
-
- // The normalized current relates to the maximum current (ESCON rating)
- return ESCON_MAX_AMP_SETPOINT * NormalizedCurrent;
-}
-
-// Return applied torque (based on current reading) in Newton meters (Nm)
-float ESCON::GetAppliedTorque()
-{
- float Current = GetCurrent();
- //if (Current < 0) return -1.0f; // error
-
- // The applied motor current can be converted to torque using the torque constant (Nm/A)
- return MOTOR_TORQUE_CONSTANT * Current;
-}
-
-// Return applied torque (based on current reading) on the output shaft (after gearing) in Newton meters (Nm)
-float ESCON::GetAppliedOutputTorque()
-{
- return GEARING_RATIO * GetAppliedTorque();
-}
-
-int32_t ESCON::GetEncoderRaw()
-{
- if (!_encoder) return 0;
- return _encoder->Get();
-}
-
-// Return motor angle in radians (rad)
-float ESCON::GetAngle()
-{
- if (!_encoder) return 0;
- int32_t encoderReading = _encoder->Get();
-
- // The encoder reading is in number of quadrature ticks (counting each edge on the two signal wires, hence 4 ticks pr. repetition)
- float absoluteMotorRevolutions = (float)encoderReading / ENCODER_TICKS_PR_REV;
-
- // Since the motor is geared the absolute output shaft angle is less than the absolute motor shaft angle
- float absoluteOutputRevolutions = absoluteMotorRevolutions / GEARING_RATIO;
-
- // Convert to radians
- return 2 * M_PI * absoluteOutputRevolutions;
-}
-
-// Return motor velocity in radians pr. second (rad/s)
-float ESCON::GetVelocity()
-{
- if (!_velocityFeedback) return -1.0f;
- float AnalogReading = _velocityFeedback->Read();
-
- // ESCON driver outputs an analog value from 0V to 3.3V
- // This range spans the normalized value from -1 to 1
- // However from the ADC reading we will get a value from 0 to 1, which we thus scale and offset accordingly
- float NormalizedVelocity = 2 * AnalogReading - 1.0f;
-
- // The normalized velocity relates to the maximum angular velocity defined in the ESCON controller
- return ESCON_MAX_RAD_PR_SEC * NormalizedVelocity;
-}
diff --git a/KugleFirmware/Libraries/Devices/ESCON/ESCON.h b/KugleFirmware/Libraries/Devices/ESCON/ESCON.h
deleted file mode 100644
index 5de2a0a..0000000
--- a/KugleFirmware/Libraries/Devices/ESCON/ESCON.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef DEVICES_ESCON_H
-#define DEVICES_ESCON_H
-
-#include "stm32h7xx_hal.h"
-#include "PWM.h"
-#include "IO.h"
-#include "ADC.h"
-#include "Encoder.h"
-
-class ESCON
-{
- private:
- const double M_PI = 3.14159265358979323846264338327950288;
-
- const int ESCON_PWM_FREQUENCY = 1000; // 4 kHz
- const int ESCON_PWM_RANGE = 2000; // 0-2000, corresponding to 0.1% resolution
-
- const float ESCON_MAX_RAD_PR_SEC; // rad/s
- const float ESCON_MAX_AMP_SETPOINT; // A
- const float MOTOR_TORQUE_CONSTANT; // Nm/A
- const uint16_t ENCODER_TICKS_PR_REV; // ticks/rev on encoder side - hence one revolution on motor shaft (before gearing)
- const float GEARING_RATIO;
-
- public:
- ESCON(PWM * TorqueSetpoint, IO * EnablePin, Encoder * encoder, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed); // minimal operation general constructor
- ESCON(PWM * TorqueSetpoint, IO * EnablePin, Encoder * encoder, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed, ADC * CurrentFeedback, ADC * VelocityFeedback, IO * DirectionFeedbackPin); // extended operation general constructor
- ESCON(uint8_t MotorIndex, float MaxCurrent, float TorqueConstant, float GearRatio, uint16_t EncoderTicksPrRev, float MaxMotorSpeed); // platform specific constructor
- ~ESCON();
-
- void Enable();
- void Disable();
-
- bool SetTorque(float torqueNewtonMeter);
- bool SetOutputTorque(float torqueNewtonMeter);
- float GetAppliedTorque();
- float GetAppliedOutputTorque();
- float GetCurrent();
- float GetAngle();
- float GetVelocity();
-
- int32_t GetEncoderRaw();
-
- private:
- PWM * _torqueSetpoint; // DIG_IN_1 on ESCON
- IO * _enablePin; // DIG_IN_4 on ESCON
- Encoder * _encoder;
- ADC * _currentFeedback; // AN_OUT_1 on ESCON
- ADC * _velocityFeedback; // AN_OUT_2 on ESCON
- IO * _directionFeedbackPin; // DIG_IN_3 on ESCON
-
- // Future use objects
- // PWM * _DIG_IN_2;
- // IO * _DIG_IN_3;
- // DAC * _AN_IN_1; // for furture use when SPI DAC library has been implemented and tested
- // DAC * _AN_IN_2;
-
- bool _deleteObjectsAtDestruction;
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Devices/IMU/IMU.cpp b/KugleFirmware/Libraries/Devices/IMU/IMU.cpp
deleted file mode 100644
index 6ff50e2..0000000
--- a/KugleFirmware/Libraries/Devices/IMU/IMU.cpp
+++ /dev/null
@@ -1,431 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "IMU.h"
-#include "Debug.h"
-#include "MathLib.h"
-#include
-#include "svd.h"
-
-// Class for sensor abstraction, sampling and calibration
-// Should eg. configure MPU-9250 interrupt
-
-#if 0
-void MPU9250_Sampling(void const * argument)
-{
- SPI * spi = new SPI(SPI::PORT_SPI3, MPU9250_SPI_LOW_FREQUENCY, GPIOG, GPIO_PIN_8);
- MPU9250 * imu = new MPU9250(spi);
-
- imu->Configure(ACCEL_RANGE_2G, GYRO_RANGE_250DPS);
- imu->setFilt(DLPF_BANDWIDTH_250HZ, DLPF_BANDWIDTH_184HZ, 8);
- imu->ConfigureInterrupt(GPIOE, GPIO_PIN_3);
-
- while (1) {
- imu->WaitForNewData();
- imu->getMotion9(&ax, &ay, &az, &gx, &gy, &gz, &mx, &my, &mz);
- }
-}
-#endif
-
-void IMU::CorrectMeasurement(Measurement_t& measurement, bool correctAccelerometerBias, bool correctAccelerometerScale, bool correctGyroBias, bool correctAlignment)
-{
- if (correctAccelerometerBias && calibration_.acc_bias_valid) {
- measurement.Accelerometer[0] -= calibration_.acc_bias[0];
- measurement.Accelerometer[1] -= calibration_.acc_bias[1];
- measurement.Accelerometer[2] -= calibration_.acc_bias[2];
- }
- if (correctAccelerometerScale && calibration_.acc_scale_valid) {
- measurement.Accelerometer[0] *= calibration_.acc_scale[0];
- measurement.Accelerometer[1] *= calibration_.acc_scale[1];
- measurement.Accelerometer[2] *= calibration_.acc_scale[2];
- }
- if (correctGyroBias && calibration_.gyro_bias_valid) {
- measurement.Gyroscope[0] -= calibration_.gyro_bias[0];
- measurement.Gyroscope[1] -= calibration_.gyro_bias[1];
- measurement.Gyroscope[2] -= calibration_.gyro_bias[2];
- }
- if (correctAlignment && calibration_.imu_calibration_matrix_valid) {
- rotateImuMeasurement(measurement.Gyroscope[0],
- measurement.Gyroscope[1],
- measurement.Gyroscope[2],
- measurement.Accelerometer[0],
- measurement.Accelerometer[1],
- measurement.Accelerometer[2],
- calibration_.imu_calibration_matrix);
- }
-}
-
-void IMU::AttachEEPROM(EEPROM * eeprom)
-{
- if (!eeprom) return;
- eeprom_ = eeprom;
- //eeprom_->EnableSection(eeprom_->sections.imu_calibration, sizeof(calibration_)); // enable IMU calibration section in EEPROM --> moved to MainTask since it has to be enabled before calling eeprom->Initialize()
- LoadCalibrationFromEEPROM();
-}
-
-void IMU::LoadCalibrationFromEEPROM(void)
-{
- if (!eeprom_) return;
- eeprom_->ReadData(eeprom_->sections.imu_calibration, (uint8_t *)&calibration_, sizeof(calibration_));
- ValidateCalibration();
-}
-
-void IMU::ValidateCalibration(void)
-{
- ValidateCalibrationMatrix();
- // Validate the other parts of the calibration
-}
-
-void IMU::ValidateCalibrationMatrix(void)
-{
- const unsigned int ValidationPrecision = 2; // decimal places checked
-
- if (!calibration_.imu_calibration_matrix_valid) return; // the calibration flag is not even set, so nothing to validate
-
- calibration_.imu_calibration_matrix_valid = false; // set the flag to false until we succeed with all checks
-
- // We perform a crude validation by ensuring that the calibration matrix is orthogonal : R*R' = I and R'*R = I
- float * R = calibration_.imu_calibration_matrix; arm_matrix_instance_f32 R_; arm_mat_init_f32(&R_, 3, 3, R);
- float R_T[3*3]; arm_matrix_instance_f32 R_T_; arm_mat_init_f32(&R_T_, 3, 3, R_T);
- arm_mat_trans_f32(&R_, &R_T_); // transpose the matrix
-
- float I1[3*3]; arm_matrix_instance_f32 I1_; arm_mat_init_f32(&I1_, 3, 3, I1);
- float I2[3*3]; arm_matrix_instance_f32 I2_; arm_mat_init_f32(&I2_, 3, 3, I2);
- arm_mat_mult_f32(&R_, &R_T_, &I1_); // R*R'
- arm_mat_mult_f32(&R_T_, &R_, &I2_); // R'*R
-
- // Verify that the diagonal elements are 1 (or very close to 1) and that any off-diagonal elements are close to 0
- for (int i = 0; i < 3; i++) {
- for (int j = 0; j < 3; j++) {
- if (i == j) { // diagonal element, should be close to 1
- if (Math_Round(I1[3*i+j], ValidationPrecision) != 1.0 ||
- Math_Round(I2[3*i+j], ValidationPrecision) != 1.0)
- return;
- } else { // off-diagonal element
- if (Math_Round(I1[3*i+j], ValidationPrecision) != 0.0 ||
- Math_Round(I2[3*i+j], ValidationPrecision) != 0.0)
- return;
- }
- }
- }
-
- // Matrix has been validated as being a proper rotation matrix (at least it is orthogonal)
- calibration_.imu_calibration_matrix_valid = true;
-}
-
-bool IMU::isCalibrated()
-{
- return (isAccelerometerCalibrated() && isGyroscopeCalibrated() && isAlignmentCalibrated());
-}
-
-bool IMU::isAccelerometerCalibrated()
-{
- return (calibration_.acc_bias_valid && calibration_.acc_scale_valid);
-}
-
-bool IMU::isGyroscopeCalibrated()
-{
- return calibration_.gyro_bias_valid;
-}
-
-bool IMU::isAlignmentCalibrated()
-{
- return calibration_.imu_calibration_matrix_valid;
-}
-
-void IMU::SetCalibration(const float accelerometer_bias[3], const float accelerometer_scale[3], const float gyroscope_bias[3], const float calibration_matrix[3*3], bool storeInEEPROM)
-{
- memcpy(calibration_.acc_bias, accelerometer_bias, sizeof(calibration_.acc_bias));
- calibration_.acc_bias_valid = true;
-
- memcpy(calibration_.acc_scale, accelerometer_scale, sizeof(calibration_.acc_scale));
- calibration_.acc_scale_valid = true;
-
- memcpy(calibration_.gyro_bias, gyroscope_bias, sizeof(calibration_.gyro_bias));
- calibration_.gyro_bias_valid = true;
-
- memcpy(calibration_.imu_calibration_matrix, calibration_matrix, sizeof(calibration_.imu_calibration_matrix));
- calibration_.imu_calibration_matrix_valid = true;
-
- ValidateCalibration();
-
- if (storeInEEPROM && eeprom_) { // if EEPROM is configured, store new calibration in EEPROM
- eeprom_->WriteData(eeprom_->sections.imu_calibration, (uint8_t *)&calibration_, sizeof(calibration_));
- }
-}
-
-void IMU::Calibrate(bool storeInEEPROM)
-{
- Measurement_t meas;
- Debug::print("Calibrating IMU\n");
- osDelay(1000);
-
- float avg_acc[3] = {0.0f, 0.0f, 0.0f};
- int num_samples = 10;
- Debug::print("Getting "); Debug::printf("%d", num_samples); Debug::print(" accelerometer samples:\n");
- for (int i = 0; i < num_samples; ++i) {
- Get(meas);
- arm_add_f32(meas.Accelerometer, avg_acc, avg_acc, 3);
- Debug::printf("%f", meas.Accelerometer[0]); Debug::print("\t");
- Debug::printf("%f", meas.Accelerometer[1]); Debug::print("\t");
- Debug::printf("%f\n", meas.Accelerometer[2]);
- osDelay(100);
- }
- arm_scale_f32(avg_acc, 1.f/num_samples, avg_acc, 3);
-
- float avg_gyro[3] = {0.0f, 0.0f, 0.0f};
- num_samples = 3000;
- Debug::print("Getting "); Debug::printf("%d", num_samples); Debug::print(" gyro samples:\n");
- for (int i = 0; i < num_samples; ++i) {
- Get(meas);
- arm_add_f32(meas.Gyroscope, avg_gyro, avg_gyro, 3);
- Debug::printf("%f", meas.Gyroscope[0]); Debug::print("\t");
- Debug::printf("%f", meas.Gyroscope[1]); Debug::print("\t");
- Debug::printf("%f\n", meas.Gyroscope[2]);
- osDelay(1);
- }
- arm_scale_f32(avg_gyro, 1.f/num_samples, calibration_.gyro_bias, 3);
-
- calibrateImu(reference_acc_vector_, avg_acc, calibration_.imu_calibration_matrix);
- calibration_.imu_calibration_matrix_valid = true;
- calibration_.gyro_bias_valid = true;
-
- Debug::print("Resulting calibration matrix:\n");
- Debug::printf("%f", calibration_.imu_calibration_matrix[0]); Debug::print("\t");
- Debug::printf("%f", calibration_.imu_calibration_matrix[1]); Debug::print("\t");
- Debug::printf("%f\n", calibration_.imu_calibration_matrix[2]);
- Debug::printf("%f", calibration_.imu_calibration_matrix[3]); Debug::print("\t");
- Debug::printf("%f", calibration_.imu_calibration_matrix[4]); Debug::print("\t");
- Debug::printf("%f\n", calibration_.imu_calibration_matrix[5]);
- Debug::printf("%f", calibration_.imu_calibration_matrix[6]); Debug::print("\t");
- Debug::printf("%f", calibration_.imu_calibration_matrix[7]); Debug::print("\t");
- Debug::printf("%f\n", calibration_.imu_calibration_matrix[8]);
-
- /* We have now calibrated, but we need to verify that the calibration is valid */
- ValidateCalibration();
- if (!isCalibrated()) {
- Debug::print("Calibration failed: Could not validate calibration\n\n");
- osDelay(5000);
- return;
- }
-
- if (storeInEEPROM && eeprom_) { // if EEPROM is configured, store new calibration in EEPROM
- eeprom_->WriteData(eeprom_->sections.imu_calibration, (uint8_t *)&calibration_, sizeof(calibration_));
- }
-
- /*Debug::print("Testing:\n");
- Get(meas);
- Debug::print("Unadjusted:\n");
- Debug::print("Acc:\t"); Debug::printf("%f", meas.Accelerometer[0]); Debug::print("\t");
- Debug::printf("%f", meas.Accelerometer[1]); Debug::print("\t"); Debug::printf("%f", meas.Accelerometer[2]); Debug::print("\n");
- Debug::print("Gyro:\t"); Debug::printf("%f", meas.Gyroscope[0]); Debug::print("\t");
- Debug::printf("%f", meas.Gyroscope[1]); Debug::print("\t"); Debug::printf("%f\n", meas.Gyroscope[2]);
- adjustImuMeasurement(meas.Gyroscope[0], meas.Gyroscope[1], meas.Gyroscope[2], meas.Accelerometer[0], meas.Accelerometer[1], meas.Accelerometer[2], calibration_.imu_calibration_matrix, calibration_.gyro_bias);
- Debug::print("Adjusted:\n");
- Debug::print("Acc:\t"); Debug::printf("%f", meas.Accelerometer[0]); Debug::print("\t");
- Debug::printf("%f", meas.Accelerometer[1]); Debug::print("\t"); Debug::printf("%f", meas.Accelerometer[2]); Debug::print("\n");
- Debug::print("Gyro:\t"); Debug::printf("%f", meas.Gyroscope[0]); Debug::print("\t");
- Debug::printf("%f", meas.Gyroscope[1]); Debug::print("\t"); Debug::printf("%f\n", meas.Gyroscope[2]);
- Debug::print("\n");*/
-}
-
-void IMU::CalibrateAccelerometer(bool storeInEEPROM)
-{
- Debug::print("Calibrating Accelerometer - tilt accelerometer slowly such that measurements are taken at all sides\n");
- osDelay(1000);
-
- float acc_min[3];
- float acc_max[3];
-
- uint32_t steadyCount = 0;
- Measurement_t meas;
- TickType_t startTime = xTaskGetTickCount();
- TickType_t endTime = startTime + configTICK_RATE_HZ * ACCELEROMETER_CALIBRATION_TIME;
- while (xTaskGetTickCount() < endTime)
- {
- Get(meas);
-
- if (fabsf(vector_length(meas.Accelerometer) - ACCELEROMETER_GRAVITY_NORM) < 0.8/* && vector_length(meas.Gyroscope) < 0.5*/) {
- steadyCount++;
- if (steadyCount > ACCELEROMETER_CALIBRATION_STEADY_TIME*ACCELEROMETER_CALIBRATION_SAMPLE_RATE) {
- if (meas.Accelerometer[0] < acc_min[0])
- acc_min[0] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_min[0] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[0];
-
- if (meas.Accelerometer[1] < acc_min[1])
- acc_min[1] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_min[1] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[1];
-
- if (meas.Accelerometer[2] < acc_min[2])
- acc_min[2] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_min[2] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[2];
-
- if (meas.Accelerometer[0] > acc_max[0])
- acc_max[0] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_max[0] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[0];
-
- if (meas.Accelerometer[1] > acc_max[1])
- acc_max[1] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_max[1] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[1];
-
- if (meas.Accelerometer[2] > acc_max[2])
- acc_max[2] = ACCELEROMETER_CALIBRATION_LPF_COEFF_A * acc_max[2] + ACCELEROMETER_CALIBRATION_LPF_COEFF_B * meas.Accelerometer[2];
- }
- } else {
- steadyCount = 0;
- }
-
- /* Compute calibration values */
- for (int i = 0; i < 3; i++) {
- calibration_.acc_bias[i] = (acc_min[i] + acc_max[i]) / 2.0;
- calibration_.acc_scale[i] = 2 * ACCELEROMETER_GRAVITY_NORM / (acc_max[i] - acc_min[i]);
- }
-
- if (steadyCount == 0)
- Debug::print(" === MOVE SLOWLY ===\n");
- else
- Debug::print(" === CALIBRATING ===\n");
- Debug::printf("Accelerometer min: { %.2f, %.2f, %.2f }\n", acc_min[0], acc_min[1], acc_min[2]);
- Debug::printf("Accelerometer max: { %.2f, %.2f, %.2f }\n", acc_max[0], acc_max[1], acc_max[2]);
- Debug::printf("Accelerometer bias: { %.2f, %.2f, %.2f }\n", calibration_.acc_bias[0], calibration_.acc_bias[1], calibration_.acc_bias[2]);
- Debug::printf("Accelerometer scale: { %.2f, %.2f, %.2f }\n", calibration_.acc_scale[0], calibration_.acc_scale[1], calibration_.acc_scale[2]);
- Debug::print("\n");
-
- osDelay(1000/ACCELEROMETER_CALIBRATION_SAMPLE_RATE);
- }
-
- calibration_.acc_bias_valid = true;
- calibration_.acc_scale_valid = true;
-
- Debug::print(" === Finished accelerometer calibration ===\n");
- Debug::printf("Accelerometer bias: { %.7f, %.7f, %.7f }\n", calibration_.acc_bias[0], calibration_.acc_bias[1], calibration_.acc_bias[2]);
- Debug::printf("Accelerometer scale: { %.7f, %.7f, %.7f }\n", calibration_.acc_scale[0], calibration_.acc_scale[1], calibration_.acc_scale[2]);
-
- /* We have now calibrated, but we need to verify that the calibration is valid */
- ValidateCalibration();
- if (!isAccelerometerCalibrated()) {
- Debug::print("Calibration failed: Could not validate calibration\n\n");
- osDelay(5000);
- return;
- }
-
- if (storeInEEPROM && eeprom_) { // if EEPROM is configured, store new calibration in EEPROM
- eeprom_->WriteData(eeprom_->sections.imu_calibration, (uint8_t *)&calibration_, sizeof(calibration_));
- }
-
- osDelay(5000);
-}
-
-float IMU::vector_length(const float v[3])
-{
- return sqrt(v[0]*v[0] + v[1]*v[1] + v[2]*v[2]);
-}
-
-void IMU::calibrateImu(const float desired_acc_vector[3],
- const float actual_acc_vector[3],
- float calibration_matrix[9])
-{
- // Scale vectors to unity
- // arm_scale_f32 does not take a const vector, but it does not modify the
- // source vector (hence the const_cast)
- Debug::print("desired_acc_vector:\t"); Debug::printf("%f", desired_acc_vector[0]); Debug::print("\t");
- Debug::printf("%f", desired_acc_vector[1]); Debug::print("\t"); Debug::printf("%f", desired_acc_vector[2]); Debug::print("\n");
- float len_des = vector_length(desired_acc_vector);
- Debug::print("len_des:\t"); Debug::printf("%f\n", len_des);
- float d[3];
- arm_scale_f32(const_cast(desired_acc_vector), 1.f/len_des, d, 3);
- Debug::print("d:\t"); Debug::printf("%f", d[0]); Debug::print("\t");
- Debug::printf("%f", d[1]); Debug::print("\t"); Debug::printf("%f", d[2]); Debug::print("\n");
-
- Debug::print("actual_acc_vector:\t"); Debug::printf("%f", actual_acc_vector[0]); Debug::print("\t");
- Debug::printf("%f", actual_acc_vector[1]); Debug::print("\t"); Debug::printf("%f", actual_acc_vector[2]); Debug::print("\n");
- float len_act = vector_length(actual_acc_vector);
- Debug::print("len_act:\t"); Debug::printf("%f\n", len_act);
- float a[3];
- arm_scale_f32(const_cast(actual_acc_vector), 1.f/len_act, a, 3);
- Debug::print("a:\t"); Debug::printf("%f", a[0]); Debug::print("\t");
- Debug::printf("%f", a[1]); Debug::print("\t"); Debug::printf("%f", a[2]); Debug::print("\n");
- // Find rotation matrix R between vectors, s.t. Ra=d
- // See: https://math.stackexchange.com/a/476311
-
- // Cross product: v = a x d
- float v[3] = {a[1]*d[2]-a[2]*d[1],
- a[2]*d[0]-a[0]*d[2],
- a[0]*d[1]-a[1]*d[0]};
- Debug::print("v:\t"); Debug::printf("%f", v[0]); Debug::print("\t");
- Debug::printf("%f", v[1]); Debug::print("\t"); Debug::printf("%f", v[2]); Debug::print("\n");
- // Sine between vectors: s = ||v||
- float s = vector_length(v);
- Debug::print("s:\t"); Debug::printf("%f\n", s);
- // Cosine between vectors: c = a . b
- float c;
- arm_dot_prod_f32(a, d, 3, &c);
- Debug::print("c:\t"); Debug::printf("%f\n", c);
- // R = I + [v]_x + [v]_x^2 (1-c)/(s^2), where [v]_x is the skew-symmetric
- // cross product matrix of v
- // It is not applicable if a and b point into exactly opposite directions,
- // which is unlikely so we do not handle it.
- float R[9] = {1.f, 0.f, 0.f,
- 0.f, 1.f, 0.f,
- 0.f, 0.f, 1.f,};
- arm_matrix_instance_f32 R_;
- arm_mat_init_f32(&R_, 3, 3, R);
- float v_x_data[9] = { 0.f, -v[2], v[1],
- v[2], 0.f, -v[0],
- -v[1], v[0], 0.f};
- arm_matrix_instance_f32 temp;
- arm_mat_init_f32(&temp, 3, 3, v_x_data);
- arm_mat_add_f32(&R_, &temp, &R_);
- arm_mat_mult_f32(&temp, &temp, &temp);
- arm_mat_scale_f32(&temp, (1.f - c) / (s * s), &temp);
- arm_mat_add_f32(&R_, &temp, &R_);
-
- // Regularize rotation matrix by making an SVD decomposition and forcing singular values to be 1
- float U[3*3]; arm_matrix_instance_f32 U_; arm_mat_init_f32(&U_, 3, 3, (float32_t *)U);
- float S[3*3]; arm_matrix_instance_f32 S_; arm_mat_init_f32(&S_, 3, 3, (float32_t *)S);
- float V[3*3]; arm_matrix_instance_f32 V_; arm_mat_init_f32(&V_, 3, 3, (float32_t *)V);
-
- /*svd(R[0], R[1], R[2], R[3], R[4], R[5], R[6], R[7], R[8],
- U[0], U[1], U[2], U[3], U[4], U[5], U[6], U[7], U[8],
- S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], S[8],
- V[0], V[1], V[2], V[3], V[4], V[5], V[6], V[7], V[8]);*/
- svd(R, U, S, V);
-
- // Compute the regularized rotation matrix
- float V_T[3*3]; arm_matrix_instance_f32 V_T_; arm_mat_init_f32(&V_T_, 3, 3, (float32_t *)V_T);
- arm_mat_trans_f32(&V_, &V_T_);
- arm_mat_mult_f32(&U_, &V_T_, &R_); // R = U * V'
-
- // Return the matrix
- memcpy(calibration_matrix, R, 9*sizeof(R[0]));
-}
-
-void IMU::rotateImuMeasurement(float& gx, float& gy, float& gz,
- float& ax, float& ay, float& az,
- const float calibration_matrix[9])
-{
- arm_matrix_instance_f32 R;
- arm_mat_init_f32(&R, 3, 3, const_cast(calibration_matrix));
-
- arm_matrix_instance_f32 g;
- float g_data[3] = {gx, gy, gz};
- arm_mat_init_f32(&g, 3, 1, g_data);
- arm_mat_mult_f32(&R, &g, &g);
- gx = g_data[0]; gy = g_data[1]; gz = g_data[2];
-
- arm_matrix_instance_f32 a;
- float a_data[3] = {ax, ay, az};
- arm_mat_init_f32(&a, 3, 1, a_data);
- arm_mat_mult_f32(&R, &a, &a);
- ax = a_data[0]; ay = a_data[1]; az = a_data[2];
-}
diff --git a/KugleFirmware/Libraries/Devices/IMU/IMU.h b/KugleFirmware/Libraries/Devices/IMU/IMU.h
deleted file mode 100644
index 55b5a17..0000000
--- a/KugleFirmware/Libraries/Devices/IMU/IMU.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef DEVICES_IMU_H
-#define DEVICES_IMU_H
-
-#include "cmsis_os.h"
-#include "EEPROM.h"
-
-class IMU
-{
- private:
- const float ACCELEROMETER_CALIBRATION_TIME = 120; // seconds
- const float ACCELEROMETER_CALIBRATION_SAMPLE_RATE = 100; // Hz
- const float ACCELEROMETER_CALIBRATION_LPF_COEFF_A = 0.904837418035960; // corresponds to 0.3 seconds settling time at 100 Hz sampling
- const float ACCELEROMETER_CALIBRATION_LPF_COEFF_B = 0.095162581964040;
- const float ACCELEROMETER_CALIBRATION_STEADY_TIME = 1.0; // seconds
- const float ACCELEROMETER_GRAVITY_NORM = 9.82; // m/s^2
-
- public:
- typedef struct Measurement_t {
- float Accelerometer[3];
- float Gyroscope[3];
- float Magnetometer[3];
- } Measurement_t;
-
- typedef struct Estimates_t {
- float q[4];
- float dq[4];
- } Estimates_t;
-
- typedef struct calibration_t {
- float imu_calibration_matrix[9];
- bool imu_calibration_matrix_valid = false;
- float gyro_bias[3];
- bool gyro_bias_valid = false;
- float acc_bias[3];
- bool acc_bias_valid = false;
- float acc_scale[3];
- bool acc_scale_valid = false;
- };
-
- public:
- virtual ~IMU() {};
-
- virtual uint32_t WaitForNewData(uint32_t xTicksToWait = portMAX_DELAY) { return pdFALSE; };
- virtual void Get(Measurement_t& measurement) {};
- virtual void GetEstimates(Estimates_t& estimates) {}; // if supported, eg. by Xsens IMU
-
- void Calibrate(bool storeInEEPROM = true);
- void CalibrateAccelerometer(bool storeInEEPROM = true);
- void SetCalibration(const float accelerometer_bias[3], const float accelerometer_scale[3], const float gyroscope_bias[3], const float calibration_matrix[3*3], bool storeInEEPROM = true);
- void CorrectMeasurement(Measurement_t& measurement, bool correctAccelerometerBias = false, bool correctAccelerometerScale = false, bool correctGyroBias = true, bool correctAlignment = true);
-
- bool isCalibrated();
- bool isAccelerometerCalibrated();
- bool isGyroscopeCalibrated();
- bool isAlignmentCalibrated();
-
- void AttachEEPROM(EEPROM * eeprom);
-
- private:
- void LoadCalibrationFromEEPROM(void);
- void ValidateCalibration(void);
- void ValidateCalibrationMatrix(void);
- float vector_length(const float v[3]);
- void calibrateImu(const float desired_acc_vector[3], const float actual_acc_vector[3], float calibration_matrix[9]);
- void rotateImuMeasurement(float& gx, float& gy, float& gz, float& ax, float& ay, float& az, const float calibration_matrix[9]);
-
- private:
- EEPROM * eeprom_ = 0;
- calibration_t calibration_;
-
- const float reference_acc_vector_[3] = {0.0f, 0.0f, 9.82f};
-
-};
-
-
-#endif
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_GFX.cpp b/KugleFirmware/Libraries/Devices/LCD/Adafruit_GFX.cpp
deleted file mode 100644
index 473d5f0..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_GFX.cpp
+++ /dev/null
@@ -1,1910 +0,0 @@
-/*
-This is the core graphics library for all our displays, providing a common
-set of graphics primitives (points, lines, circles, etc.). It needs to be
-paired with a hardware-specific library for each display device we carry
-(to handle the lower-level functions).
-
-Adafruit invests time and resources providing this open source code, please
-support Adafruit & open-source hardware by purchasing products from Adafruit!
-
-Copyright (c) 2013 Adafruit Industries. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-- Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-- Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "Adafruit_GFX.h"
-#include "glcdfont.c"
-#include
-#include // std::string class
-#include // strncopy
-
-/**************************************************************************/
-/*!
- @brief Instatiate a GFX context for graphics! Can only be done by a superclass
- @param w Display width, in pixels
- @param h Display height, in pixels
-*/
-/**************************************************************************/
-Adafruit_GFX::Adafruit_GFX(int16_t w, int16_t h):
-WIDTH(w), HEIGHT(h)
-{
- _width = WIDTH;
- _height = HEIGHT;
- rotation = 0;
- cursor_y = cursor_x = 0;
- textsize = 1;
- textcolor = textbgcolor = 0xFFFF;
- wrap = true;
- _cp437 = false;
- gfxFont = NULL;
-}
-
-/**************************************************************************/
-/*!
- @brief Write a line. Bresenham's algorithm - thx wikpedia
- @param x0 Start point x coordinate
- @param y0 Start point y coordinate
- @param x1 End point x coordinate
- @param y1 End point y coordinate
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1,
- uint16_t color) {
- int16_t steep = abs(y1 - y0) > abs(x1 - x0);
- if (steep) {
- _swap_int16_t(x0, y0);
- _swap_int16_t(x1, y1);
- }
-
- if (x0 > x1) {
- _swap_int16_t(x0, x1);
- _swap_int16_t(y0, y1);
- }
-
- int16_t dx, dy;
- dx = x1 - x0;
- dy = abs(y1 - y0);
-
- int16_t err = dx / 2;
- int16_t ystep;
-
- if (y0 < y1) {
- ystep = 1;
- } else {
- ystep = -1;
- }
-
- for (; x0<=x1; x0++) {
- if (steep) {
- writePixel(y0, x0, color);
- } else {
- writePixel(x0, y0, color);
- }
- err -= dy;
- if (err < 0) {
- y0 += ystep;
- err += dx;
- }
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Start a display-writing routine, overwrite in subclasses.
-*/
-/**************************************************************************/
-void Adafruit_GFX::startWrite(){
-}
-
-/**************************************************************************/
-/*!
- @brief Write a pixel, overwrite in subclasses if startWrite is defined!
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::writePixel(int16_t x, int16_t y, uint16_t color){
- drawPixel(x, y, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly vertical line, overwrite in subclasses if startWrite is defined!
- @param x Top-most x coordinate
- @param y Top-most y coordinate
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::writeFastVLine(int16_t x, int16_t y,
- int16_t h, uint16_t color) {
- // Overwrite in subclasses if startWrite is defined!
- // Can be just writeLine(x, y, x, y+h-1, color);
- // or writeFillRect(x, y, 1, h, color);
- drawFastVLine(x, y, h, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly horizontal line, overwrite in subclasses if startWrite is defined!
- @param x Left-most x coordinate
- @param y Left-most y coordinate
- @param w Width in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::writeFastHLine(int16_t x, int16_t y,
- int16_t w, uint16_t color) {
- // Overwrite in subclasses if startWrite is defined!
- // Example: writeLine(x, y, x+w-1, y, color);
- // or writeFillRect(x, y, w, 1, color);
- drawFastHLine(x, y, w, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a rectangle completely with one color, overwrite in subclasses if startWrite is defined!
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h,
- uint16_t color) {
- // Overwrite in subclasses if desired!
- fillRect(x,y,w,h,color);
-}
-
-/**************************************************************************/
-/*!
- @brief End a display-writing routine, overwrite in subclasses if startWrite is defined!
-*/
-/**************************************************************************/
-void Adafruit_GFX::endWrite(){
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a perfectly vertical line (this is often optimized in a subclass!)
- @param x Top-most x coordinate
- @param y Top-most y coordinate
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawFastVLine(int16_t x, int16_t y,
- int16_t h, uint16_t color) {
- startWrite();
- writeLine(x, y, x, y+h-1, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a perfectly horizontal line (this is often optimized in a subclass!)
- @param x Left-most x coordinate
- @param y Left-most y coordinate
- @param w Width in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawFastHLine(int16_t x, int16_t y,
- int16_t w, uint16_t color) {
- startWrite();
- writeLine(x, y, x+w-1, y, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Fill a rectangle completely with one color. Update in subclasses if desired!
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
- uint16_t color) {
- startWrite();
- for (int16_t i=x; i y1) _swap_int16_t(y0, y1);
- drawFastVLine(x0, y0, y1 - y0 + 1, color);
- } else if(y0 == y1){
- if(x0 > x1) _swap_int16_t(x0, x1);
- drawFastHLine(x0, y0, x1 - x0 + 1, color);
- } else {
- startWrite();
- writeLine(x0, y0, x1, y1, color);
- endWrite();
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a circle outline
- @param x0 Center-point x coordinate
- @param y0 Center-point y coordinate
- @param r Radius of circle
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawCircle(int16_t x0, int16_t y0, int16_t r,
- uint16_t color) {
- int16_t f = 1 - r;
- int16_t ddF_x = 1;
- int16_t ddF_y = -2 * r;
- int16_t x = 0;
- int16_t y = r;
-
- startWrite();
- writePixel(x0 , y0+r, color);
- writePixel(x0 , y0-r, color);
- writePixel(x0+r, y0 , color);
- writePixel(x0-r, y0 , color);
-
- while (x= 0) {
- y--;
- ddF_y += 2;
- f += ddF_y;
- }
- x++;
- ddF_x += 2;
- f += ddF_x;
-
- writePixel(x0 + x, y0 + y, color);
- writePixel(x0 - x, y0 + y, color);
- writePixel(x0 + x, y0 - y, color);
- writePixel(x0 - x, y0 - y, color);
- writePixel(x0 + y, y0 + x, color);
- writePixel(x0 - y, y0 + x, color);
- writePixel(x0 + y, y0 - x, color);
- writePixel(x0 - y, y0 - x, color);
- }
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Quarter-circle drawer, used to do circles and roundrects
- @param x0 Center-point x coordinate
- @param y0 Center-point y coordinate
- @param r Radius of circle
- @param cornername Mask bit #1 or bit #2 to indicate which quarters of the circle we're doing
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawCircleHelper( int16_t x0, int16_t y0,
- int16_t r, uint8_t cornername, uint16_t color) {
- int16_t f = 1 - r;
- int16_t ddF_x = 1;
- int16_t ddF_y = -2 * r;
- int16_t x = 0;
- int16_t y = r;
-
- while (x= 0) {
- y--;
- ddF_y += 2;
- f += ddF_y;
- }
- x++;
- ddF_x += 2;
- f += ddF_x;
- if (cornername & 0x4) {
- writePixel(x0 + x, y0 + y, color);
- writePixel(x0 + y, y0 + x, color);
- }
- if (cornername & 0x2) {
- writePixel(x0 + x, y0 - y, color);
- writePixel(x0 + y, y0 - x, color);
- }
- if (cornername & 0x8) {
- writePixel(x0 - y, y0 + x, color);
- writePixel(x0 - x, y0 + y, color);
- }
- if (cornername & 0x1) {
- writePixel(x0 - y, y0 - x, color);
- writePixel(x0 - x, y0 - y, color);
- }
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a circle with filled color
- @param x0 Center-point x coordinate
- @param y0 Center-point y coordinate
- @param r Radius of circle
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::fillCircle(int16_t x0, int16_t y0, int16_t r,
- uint16_t color) {
- startWrite();
- writeFastVLine(x0, y0-r, 2*r+1, color);
- fillCircleHelper(x0, y0, r, 3, 0, color);
- endWrite();
-}
-
-
-/**************************************************************************/
-/*!
- @brief Quarter-circle drawer with fill, used for circles and roundrects
- @param x0 Center-point x coordinate
- @param y0 Center-point y coordinate
- @param r Radius of circle
- @param corners Mask bits indicating which quarters we're doing
- @param delta Offset from center-point, used for round-rects
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::fillCircleHelper(int16_t x0, int16_t y0, int16_t r,
- uint8_t corners, int16_t delta, uint16_t color) {
-
- int16_t f = 1 - r;
- int16_t ddF_x = 1;
- int16_t ddF_y = -2 * r;
- int16_t x = 0;
- int16_t y = r;
- int16_t px = x;
- int16_t py = y;
-
- delta++; // Avoid some +1's in the loop
-
- while(x < y) {
- if (f >= 0) {
- y--;
- ddF_y += 2;
- f += ddF_y;
- }
- x++;
- ddF_x += 2;
- f += ddF_x;
- // These checks avoid double-drawing certain lines, important
- // for the SSD1306 library which has an INVERT drawing mode.
- if(x < (y + 1)) {
- if(corners & 1) writeFastVLine(x0+x, y0-y, 2*y+delta, color);
- if(corners & 2) writeFastVLine(x0-x, y0-y, 2*y+delta, color);
- }
- if(y != py) {
- if(corners & 1) writeFastVLine(x0+py, y0-px, 2*px+delta, color);
- if(corners & 2) writeFastVLine(x0-py, y0-px, 2*px+delta, color);
- py = y;
- }
- px = x;
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a rectangle with no fill color
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawRect(int16_t x, int16_t y, int16_t w, int16_t h,
- uint16_t color) {
- startWrite();
- writeFastHLine(x, y, w, color);
- writeFastHLine(x, y+h-1, w, color);
- writeFastVLine(x, y, h, color);
- writeFastVLine(x+w-1, y, h, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a rounded rectangle with no fill color
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param r Radius of corner rounding
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawRoundRect(int16_t x, int16_t y, int16_t w,
- int16_t h, int16_t r, uint16_t color) {
- int16_t max_radius = ((w < h) ? w : h) / 2; // 1/2 minor axis
- if(r > max_radius) r = max_radius;
- // smarter version
- startWrite();
- writeFastHLine(x+r , y , w-2*r, color); // Top
- writeFastHLine(x+r , y+h-1, w-2*r, color); // Bottom
- writeFastVLine(x , y+r , h-2*r, color); // Left
- writeFastVLine(x+w-1, y+r , h-2*r, color); // Right
- // draw four corners
- drawCircleHelper(x+r , y+r , r, 1, color);
- drawCircleHelper(x+w-r-1, y+r , r, 2, color);
- drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color);
- drawCircleHelper(x+r , y+h-r-1, r, 8, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a rounded rectangle with fill color
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param r Radius of corner rounding
- @param color 16-bit 5-6-5 Color to draw/fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::fillRoundRect(int16_t x, int16_t y, int16_t w,
- int16_t h, int16_t r, uint16_t color) {
- int16_t max_radius = ((w < h) ? w : h) / 2; // 1/2 minor axis
- if(r > max_radius) r = max_radius;
- // smarter version
- startWrite();
- writeFillRect(x+r, y, w-2*r, h, color);
- // draw four corners
- fillCircleHelper(x+w-r-1, y+r, r, 1, h-2*r-1, color);
- fillCircleHelper(x+r , y+r, r, 2, h-2*r-1, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a triangle with no fill color
- @param x0 Vertex #0 x coordinate
- @param y0 Vertex #0 y coordinate
- @param x1 Vertex #1 x coordinate
- @param y1 Vertex #1 y coordinate
- @param x2 Vertex #2 x coordinate
- @param y2 Vertex #2 y coordinate
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawTriangle(int16_t x0, int16_t y0,
- int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color) {
- drawLine(x0, y0, x1, y1, color);
- drawLine(x1, y1, x2, y2, color);
- drawLine(x2, y2, x0, y0, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a triangle with color-fill
- @param x0 Vertex #0 x coordinate
- @param y0 Vertex #0 y coordinate
- @param x1 Vertex #1 x coordinate
- @param y1 Vertex #1 y coordinate
- @param x2 Vertex #2 x coordinate
- @param y2 Vertex #2 y coordinate
- @param color 16-bit 5-6-5 Color to fill/draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::fillTriangle(int16_t x0, int16_t y0,
- int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color) {
-
- int16_t a, b, y, last;
-
- // Sort coordinates by Y order (y2 >= y1 >= y0)
- if (y0 > y1) {
- _swap_int16_t(y0, y1); _swap_int16_t(x0, x1);
- }
- if (y1 > y2) {
- _swap_int16_t(y2, y1); _swap_int16_t(x2, x1);
- }
- if (y0 > y1) {
- _swap_int16_t(y0, y1); _swap_int16_t(x0, x1);
- }
-
- startWrite();
- if(y0 == y2) { // Handle awkward all-on-same-line case as its own thing
- a = b = x0;
- if(x1 < a) a = x1;
- else if(x1 > b) b = x1;
- if(x2 < a) a = x2;
- else if(x2 > b) b = x2;
- writeFastHLine(a, y0, b-a+1, color);
- endWrite();
- return;
- }
-
- int16_t
- dx01 = x1 - x0,
- dy01 = y1 - y0,
- dx02 = x2 - x0,
- dy02 = y2 - y0,
- dx12 = x2 - x1,
- dy12 = y2 - y1;
- int32_t
- sa = 0,
- sb = 0;
-
- // For upper part of triangle, find scanline crossings for segments
- // 0-1 and 0-2. If y1=y2 (flat-bottomed triangle), the scanline y1
- // is included here (and second loop will be skipped, avoiding a /0
- // error there), otherwise scanline y1 is skipped here and handled
- // in the second loop...which also avoids a /0 error here if y0=y1
- // (flat-topped triangle).
- if(y1 == y2) last = y1; // Include y1 scanline
- else last = y1-1; // Skip it
-
- for(y=y0; y<=last; y++) {
- a = x0 + sa / dy01;
- b = x0 + sb / dy02;
- sa += dx01;
- sb += dx02;
- /* longhand:
- a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);
- b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
- */
- if(a > b) _swap_int16_t(a,b);
- writeFastHLine(a, y, b-a+1, color);
- }
-
- // For lower part of triangle, find scanline crossings for segments
- // 0-2 and 1-2. This loop is skipped if y1=y2.
- sa = dx12 * (y - y1);
- sb = dx02 * (y - y0);
- for(; y<=y2; y++) {
- a = x1 + sa / dy12;
- b = x0 + sb / dy02;
- sa += dx12;
- sb += dx02;
- /* longhand:
- a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);
- b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
- */
- if(a > b) _swap_int16_t(a,b);
- writeFastHLine(a, y, b-a+1, color);
- }
- endWrite();
-}
-
-// BITMAP / XBITMAP / GRAYSCALE / RGB BITMAP FUNCTIONS ---------------------
-
-/**************************************************************************/
-/*!
- @brief Draw a PROGMEM-resident 1-bit image at the specified (x,y) position, using the specified foreground color (unset bits are transparent).
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param bitmap byte array with monochrome bitmap
- @param w Width of bitmap in pixels
- @param h Hieght of bitmap in pixels
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawBitmap(int16_t x, int16_t y,
- const uint8_t bitmap[], int16_t w, int16_t h, uint16_t color) {
-
- int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte
- uint8_t byte = 0;
-
- startWrite();
- for(int16_t j=0; j>= 1;
- else byte = pgm_read_byte(&bitmap[j * byteWidth + i / 8]);
- // Nearly identical to drawBitmap(), only the bit order
- // is reversed here (left-to-right = LSB to MSB):
- if(byte & 0x01) writePixel(x+i, y, color);
- }
- }
- endWrite();
-}
-
-
-/**************************************************************************/
-/*!
- @brief Draw a PROGMEM-resident 8-bit image (grayscale) at the specified (x,y) pos.
- Specifically for 8-bit display devices such as IS31FL3731; no color reduction/expansion is performed.
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param bitmap byte array with grayscale bitmap
- @param w Width of bitmap in pixels
- @param h Hieght of bitmap in pixels
-*/
-/**************************************************************************/
-void Adafruit_GFX::drawGrayscaleBitmap(int16_t x, int16_t y,
- const uint8_t bitmap[], int16_t w, int16_t h) {
- startWrite();
- for(int16_t j=0; j= _width) || // Clip right
- (y >= _height) || // Clip bottom
- ((x + 6 * size - 1) < 0) || // Clip left
- ((y + 8 * size - 1) < 0)) // Clip top
- return;
-
- if(!_cp437 && (c >= 176)) c++; // Handle 'classic' charset behavior
-
- startWrite();
- for(int8_t i=0; i<5; i++ ) { // Char bitmap = 5 columns
- uint8_t line = pgm_read_byte(&font[c * 5 + i]);
- for(int8_t j=0; j<8; j++, line >>= 1) {
- if(line & 1) {
- if(size == 1)
- writePixel(x+i, y+j, color);
- else
- writeFillRect(x+i*size, y+j*size, size, size, color);
- } else if(bg != color) {
- if(size == 1)
- writePixel(x+i, y+j, bg);
- else
- writeFillRect(x+i*size, y+j*size, size, size, bg);
- }
- }
- }
- if(bg != color) { // If opaque, draw vertical line for last column
- if(size == 1) writeFastVLine(x+5, y, 8, bg);
- else writeFillRect(x+5*size, y, size, 8*size, bg);
- }
- endWrite();
-
- } else { // Custom font
-
- // Character is assumed previously filtered by write() to eliminate
- // newlines, returns, non-printable characters, etc. Calling
- // drawChar() directly with 'bad' characters of font may cause mayhem!
-
- c -= (uint8_t)pgm_read_byte(&gfxFont->first);
- GFXglyph *glyph = &(((GFXglyph *)pgm_read_pointer(&gfxFont->glyph))[c]);
- uint8_t *bitmap = (uint8_t *)pgm_read_pointer(&gfxFont->bitmap);
-
- uint16_t bo = pgm_read_word(&glyph->bitmapOffset);
- uint8_t w = pgm_read_byte(&glyph->width),
- h = pgm_read_byte(&glyph->height);
- int8_t xo = pgm_read_byte(&glyph->xOffset),
- yo = pgm_read_byte(&glyph->yOffset);
- uint8_t xx, yy, bits = 0, bit = 0;
- int16_t xo16 = 0, yo16 = 0;
-
- if(size > 1) {
- xo16 = xo;
- yo16 = yo;
- }
-
- // Todo: Add character clipping here
-
- // NOTE: THERE IS NO 'BACKGROUND' COLOR OPTION ON CUSTOM FONTS.
- // THIS IS ON PURPOSE AND BY DESIGN. The background color feature
- // has typically been used with the 'classic' font to overwrite old
- // screen contents with new data. This ONLY works because the
- // characters are a uniform size; it's not a sensible thing to do with
- // proportionally-spaced fonts with glyphs of varying sizes (and that
- // may overlap). To replace previously-drawn text when using a custom
- // font, use the getTextBounds() function to determine the smallest
- // rectangle encompassing a string, erase the area with fillRect(),
- // then draw new text. This WILL infortunately 'blink' the text, but
- // is unavoidable. Drawing 'background' pixels will NOT fix this,
- // only creates a new set of problems. Have an idea to work around
- // this (a canvas object type for MCUs that can afford the RAM and
- // displays supporting setAddrWindow() and pushColors()), but haven't
- // implemented this yet.
-
- startWrite();
- for(yy=0; yy _width)) { // Off right?
- cursor_x = 0; // Reset x to zero,
- cursor_y += textsize * 8; // advance y one line
- }
- drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);
- cursor_x += textsize * 6; // Advance x one char
- }
-
- } else { // Custom font
-
- if(c == '\n') {
- cursor_x = 0;
- cursor_y += (int16_t)textsize *
- (uint8_t)pgm_read_byte(&gfxFont->yAdvance);
- } else if(c != '\r') {
- uint8_t first = pgm_read_byte(&gfxFont->first);
- if((c >= first) && (c <= (uint8_t)pgm_read_byte(&gfxFont->last))) {
- GFXglyph *glyph = &(((GFXglyph *)pgm_read_pointer(
- &gfxFont->glyph))[c - first]);
- uint8_t w = pgm_read_byte(&glyph->width),
- h = pgm_read_byte(&glyph->height);
- if((w > 0) && (h > 0)) { // Is there an associated bitmap?
- int16_t xo = (int8_t)pgm_read_byte(&glyph->xOffset); // sic
- if(wrap && ((cursor_x + textsize * (xo + w)) > _width)) {
- cursor_x = 0;
- cursor_y += (int16_t)textsize *
- (uint8_t)pgm_read_byte(&gfxFont->yAdvance);
- }
- drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);
- }
- cursor_x += (uint8_t)pgm_read_byte(&glyph->xAdvance) * (int16_t)textsize;
- }
- }
-
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Set text cursor location
- @param x X coordinate in pixels
- @param y Y coordinate in pixels
-*/
-/**************************************************************************/
-void Adafruit_GFX::setCursor(int16_t x, int16_t y) {
- cursor_x = x;
- cursor_y = y;
-}
-
-/**************************************************************************/
-/*!
- @brief Get text cursor X location
- @returns X coordinate in pixels
-*/
-/**************************************************************************/
-int16_t Adafruit_GFX::getCursorX(void) const {
- return cursor_x;
-}
-
-/**************************************************************************/
-/*!
- @brief Get text cursor Y location
- @returns Y coordinate in pixels
-*/
-/**************************************************************************/
-int16_t Adafruit_GFX::getCursorY(void) const {
- return cursor_y;
-}
-
-/**************************************************************************/
-/*!
- @brief Set text 'magnification' size. Each increase in s makes 1 pixel that much bigger.
- @param s Desired text size. 1 is default 6x8, 2 is 12x16, 3 is 18x24, etc
-*/
-/**************************************************************************/
-void Adafruit_GFX::setTextSize(uint8_t s) {
- textsize = (s > 0) ? s : 1;
-}
-
-/**************************************************************************/
-/*!
- @brief Set text font color with transparant background
- @param c 16-bit 5-6-5 Color to draw text with
-*/
-/**************************************************************************/
-void Adafruit_GFX::setTextColor(uint16_t c) {
- // For 'transparent' background, we'll set the bg
- // to the same as fg instead of using a flag
- textcolor = textbgcolor = c;
-}
-
-/**************************************************************************/
-/*!
- @brief Set text font color with custom background color
- @param c 16-bit 5-6-5 Color to draw text with
- @param b 16-bit 5-6-5 Color to draw background/fill with
-*/
-/**************************************************************************/
-void Adafruit_GFX::setTextColor(uint16_t c, uint16_t b) {
- textcolor = c;
- textbgcolor = b;
-}
-
-/**************************************************************************/
-/*!
- @brief Whether text that is too long should 'wrap' around to the next line.
- @param w Set true for wrapping, false for clipping
-*/
-/**************************************************************************/
-void Adafruit_GFX::setTextWrap(bool w) {
- wrap = w;
-}
-
-/**************************************************************************/
-/*!
- @brief Get rotation setting for display
- @returns 0 thru 3 corresponding to 4 cardinal rotations
-*/
-/**************************************************************************/
-uint8_t Adafruit_GFX::getRotation(void) const {
- return rotation;
-}
-
-/**************************************************************************/
-/*!
- @brief Set rotation setting for display
- @param x 0 thru 3 corresponding to 4 cardinal rotations
-*/
-/**************************************************************************/
-void Adafruit_GFX::setRotation(uint8_t x) {
- rotation = (x & 3);
- switch(rotation) {
- case 0:
- case 2:
- _width = WIDTH;
- _height = HEIGHT;
- break;
- case 1:
- case 3:
- _width = HEIGHT;
- _height = WIDTH;
- break;
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Enable (or disable) Code Page 437-compatible charset.
- There was an error in glcdfont.c for the longest time -- one character
- (#176, the 'light shade' block) was missing -- this threw off the index
- of every character that followed it. But a TON of code has been written
- with the erroneous character indices. By default, the library uses the
- original 'wrong' behavior and old sketches will still work. Pass 'true'
- to this function to use correct CP437 character values in your code.
- @param x Whether to enable (True) or not (False)
-*/
-/**************************************************************************/
-void Adafruit_GFX::cp437(bool x) {
- _cp437 = x;
-}
-
-/**************************************************************************/
-/*!
- @brief Set the font to display when print()ing, either custom or default
- @param f The GFXfont object, if NULL use built in 6x8 font
-*/
-/**************************************************************************/
-void Adafruit_GFX::setFont(const GFXfont *f) {
- if(f) { // Font struct pointer passed in?
- if(!gfxFont) { // And no current font struct?
- // Switching from classic to new font behavior.
- // Move cursor pos down 6 pixels so it's on baseline.
- cursor_y += 6;
- }
- } else if(gfxFont) { // NULL passed. Current font struct defined?
- // Switching from new to classic font behavior.
- // Move cursor pos up 6 pixels so it's at top-left of char.
- cursor_y -= 6;
- }
- gfxFont = (GFXfont *)f;
-}
-
-
-/**************************************************************************/
-/*!
- @brief Helper to determine size of a character with current font/size.
- Broke this out as it's used by both the PROGMEM- and RAM-resident getTextBounds() functions.
- @param c The ascii character in question
- @param x Pointer to x location of character
- @param y Pointer to y location of character
- @param minx Minimum clipping value for X
- @param miny Minimum clipping value for Y
- @param maxx Maximum clipping value for X
- @param maxy Maximum clipping value for Y
-*/
-/**************************************************************************/
-void Adafruit_GFX::charBounds(char c, int16_t *x, int16_t *y,
- int16_t *minx, int16_t *miny, int16_t *maxx, int16_t *maxy) {
-
- if(gfxFont) {
-
- if(c == '\n') { // Newline?
- *x = 0; // Reset x to zero, advance y by one line
- *y += textsize * (uint8_t)pgm_read_byte(&gfxFont->yAdvance);
- } else if(c != '\r') { // Not a carriage return; is normal char
- uint8_t first = pgm_read_byte(&gfxFont->first),
- last = pgm_read_byte(&gfxFont->last);
- if((c >= first) && (c <= last)) { // Char present in this font?
- GFXglyph *glyph = &(((GFXglyph *)pgm_read_pointer(
- &gfxFont->glyph))[c - first]);
- uint8_t gw = pgm_read_byte(&glyph->width),
- gh = pgm_read_byte(&glyph->height),
- xa = pgm_read_byte(&glyph->xAdvance);
- int8_t xo = pgm_read_byte(&glyph->xOffset),
- yo = pgm_read_byte(&glyph->yOffset);
- if(wrap && ((*x+(((int16_t)xo+gw)*textsize)) > _width)) {
- *x = 0; // Reset x to zero, advance y by one line
- *y += textsize * (uint8_t)pgm_read_byte(&gfxFont->yAdvance);
- }
- int16_t ts = (int16_t)textsize,
- x1 = *x + xo * ts,
- y1 = *y + yo * ts,
- x2 = x1 + gw * ts - 1,
- y2 = y1 + gh * ts - 1;
- if(x1 < *minx) *minx = x1;
- if(y1 < *miny) *miny = y1;
- if(x2 > *maxx) *maxx = x2;
- if(y2 > *maxy) *maxy = y2;
- *x += xa * ts;
- }
- }
-
- } else { // Default font
-
- if(c == '\n') { // Newline?
- *x = 0; // Reset x to zero,
- *y += textsize * 8; // advance y one line
- // min/max x/y unchaged -- that waits for next 'normal' character
- } else if(c != '\r') { // Normal char; ignore carriage returns
- if(wrap && ((*x + textsize * 6) > _width)) { // Off right?
- *x = 0; // Reset x to zero,
- *y += textsize * 8; // advance y one line
- }
- int x2 = *x + textsize * 6 - 1, // Lower-right pixel of char
- y2 = *y + textsize * 8 - 1;
- if(x2 > *maxx) *maxx = x2; // Track max x, y
- if(y2 > *maxy) *maxy = y2;
- if(*x < *minx) *minx = *x; // Track min x, y
- if(*y < *miny) *miny = *y;
- *x += textsize * 6; // Advance x one char
- }
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Helper to determine size of a string with current font/size. Pass string and a cursor position, returns UL corner and W,H.
- @param str The ascii string to measure
- @param x The current cursor X
- @param y The current cursor Y
- @param x1 The boundary X coordinate, set by function
- @param y1 The boundary Y coordinate, set by function
- @param w The boundary width, set by function
- @param h The boundary height, set by function
-*/
-/**************************************************************************/
-void Adafruit_GFX::getTextBounds(const char *str, int16_t x, int16_t y,
- int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h) {
- uint8_t c; // Current character
-
- *x1 = x;
- *y1 = y;
- *w = *h = 0;
-
- int16_t minx = _width, miny = _height, maxx = -1, maxy = -1;
-
- while((c = *str++))
- charBounds(c, &x, &y, &minx, &miny, &maxx, &maxy);
-
- if(maxx >= minx) {
- *x1 = minx;
- *w = maxx - minx + 1;
- }
- if(maxy >= miny) {
- *y1 = miny;
- *h = maxy - miny + 1;
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Helper to determine size of a string with current font/size. Pass string and a cursor position, returns UL corner and W,H.
- @param str The ascii string to measure (as an arduino String() class)
- @param x The current cursor X
- @param y The current cursor Y
- @param x1 The boundary X coordinate, set by function
- @param y1 The boundary Y coordinate, set by function
- @param w The boundary width, set by function
- @param h The boundary height, set by function
-*/
-/**************************************************************************/
-void Adafruit_GFX::getTextBounds(const std::string &str, int16_t x, int16_t y,
- int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h) {
- if (str.length() != 0) {
- getTextBounds(const_cast(str.c_str()), x, y, x1, y1, w, h);
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Get width of the display, accounting for the current rotation
- @returns Width in pixels
-*/
-/**************************************************************************/
-int16_t Adafruit_GFX::width(void) const {
- return _width;
-}
-
-/**************************************************************************/
-/*!
- @brief Get height of the display, accounting for the current rotation
- @returns Height in pixels
-*/
-/**************************************************************************/
-int16_t Adafruit_GFX::height(void) const {
- return _height;
-}
-
-/**************************************************************************/
-/*!
- @brief Invert the display (ideally using built-in hardware command)
- @param i True if you want to invert, false to make 'normal'
-*/
-/**************************************************************************/
-void Adafruit_GFX::invertDisplay(bool i) {
- // Do nothing, must be subclassed if supported by hardware
-}
-
-/***************************************************************************/
-
-/**************************************************************************/
-/*!
- @brief Create a simple drawn button UI element
-*/
-/**************************************************************************/
-Adafruit_GFX_Button::Adafruit_GFX_Button(void) {
- _gfx = 0;
-}
-
-/**************************************************************************/
-/*!
- @brief Initialize button with our desired color/size/settings
- @param gfx Pointer to our display so we can draw to it!
- @param x The X coordinate of the center of the button
- @param y The Y coordinate of the center of the button
- @param w Width of the buttton
- @param h Height of the buttton
- @param outline Color of the outline (16-bit 5-6-5 standard)
- @param fill Color of the button fill (16-bit 5-6-5 standard)
- @param textcolor Color of the button label (16-bit 5-6-5 standard)
- @param label Ascii string of the text inside the button
- @param textsize The font magnification of the label text
-*/
-/**************************************************************************/
-// Classic initButton() function: pass center & size
-void Adafruit_GFX_Button::initButton(
- Adafruit_GFX *gfx, int16_t x, int16_t y, uint16_t w, uint16_t h,
- uint16_t outline, uint16_t fill, uint16_t textcolor,
- char *label, uint8_t textsize)
-{
- // Tweak arguments and pass to the newer initButtonUL() function...
- initButtonUL(gfx, x - (w / 2), y - (h / 2), w, h, outline, fill,
- textcolor, label, textsize);
-}
-
-/**************************************************************************/
-/*!
- @brief Initialize button with our desired color/size/settings, with upper-left coordinates
- @param gfx Pointer to our display so we can draw to it!
- @param x1 The X coordinate of the Upper-Left corner of the button
- @param y1 The Y coordinate of the Upper-Left corner of the button
- @param w Width of the buttton
- @param h Height of the buttton
- @param outline Color of the outline (16-bit 5-6-5 standard)
- @param fill Color of the button fill (16-bit 5-6-5 standard)
- @param textcolor Color of the button label (16-bit 5-6-5 standard)
- @param label Ascii string of the text inside the button
- @param textsize The font magnification of the label text
-*/
-/**************************************************************************/
-void Adafruit_GFX_Button::initButtonUL(
- Adafruit_GFX *gfx, int16_t x1, int16_t y1, uint16_t w, uint16_t h,
- uint16_t outline, uint16_t fill, uint16_t textcolor,
- char *label, uint8_t textsize)
-{
- _x1 = x1;
- _y1 = y1;
- _w = w;
- _h = h;
- _outlinecolor = outline;
- _fillcolor = fill;
- _textcolor = textcolor;
- _textsize = textsize;
- _gfx = gfx;
- strncpy(_label, label, 9);
-}
-
-/**************************************************************************/
-/*!
- @brief Draw the button on the screen
- @param inverted Whether to draw with fill/text swapped to indicate 'pressed'
-*/
-/**************************************************************************/
-void Adafruit_GFX_Button::drawButton(bool inverted) {
- uint16_t fill, outline, text;
-
- if(!inverted) {
- fill = _fillcolor;
- outline = _outlinecolor;
- text = _textcolor;
- } else {
- fill = _textcolor;
- outline = _outlinecolor;
- text = _fillcolor;
- }
-
- uint8_t r = MIN(_w, _h) / 4; // Corner radius
- _gfx->fillRoundRect(_x1, _y1, _w, _h, r, fill);
- _gfx->drawRoundRect(_x1, _y1, _w, _h, r, outline);
-
- _gfx->setCursor(_x1 + (_w/2) - (strlen(_label) * 3 * _textsize),
- _y1 + (_h/2) - (4 * _textsize));
- _gfx->setTextColor(text);
- _gfx->setTextSize(_textsize);
- _gfx->print(_label);
-}
-
-/**************************************************************************/
-/*!
- @brief Helper to let us know if a coordinate is within the bounds of the button
- @param x The X coordinate to check
- @param y The Y coordinate to check
- @returns True if within button graphics outline
-*/
-/**************************************************************************/
-bool Adafruit_GFX_Button::contains(int16_t x, int16_t y) {
- return ((x >= _x1) && (x < (int16_t) (_x1 + _w)) &&
- (y >= _y1) && (y < (int16_t) (_y1 + _h)));
-}
-
-/**************************************************************************/
-/*!
- @brief Sets the state of the button, should be done by some touch function
- @param p True for pressed, false for not.
-*/
-/**************************************************************************/
-void Adafruit_GFX_Button::press(bool p) {
- laststate = currstate;
- currstate = p;
-}
-
-/**************************************************************************/
-/*!
- @brief Query whether the button is currently pressed
- @returns True if pressed
-*/
-/**************************************************************************/
-bool Adafruit_GFX_Button::isPressed() { return currstate; }
-
-/**************************************************************************/
-/*!
- @brief Query whether the button was pressed since we last checked state
- @returns True if was not-pressed before, now is.
-*/
-/**************************************************************************/
-bool Adafruit_GFX_Button::justPressed() { return (currstate && !laststate); }
-
-/**************************************************************************/
-/*!
- @brief Query whether the button was released since we last checked state
- @returns True if was pressed before, now is not.
-*/
-/**************************************************************************/
-bool Adafruit_GFX_Button::justReleased() { return (!currstate && laststate); }
-
-// -------------------------------------------------------------------------
-
-// GFXcanvas1, GFXcanvas8 and GFXcanvas16 (currently a WIP, don't get too
-// comfy with the implementation) provide 1-, 8- and 16-bit offscreen
-// canvases, the address of which can be passed to drawBitmap() or
-// pushColors() (the latter appears only in a couple of GFX-subclassed TFT
-// libraries at this time). This is here mostly to help with the recently-
-// added proportionally-spaced fonts; adds a way to refresh a section of the
-// screen without a massive flickering clear-and-redraw...but maybe you'll
-// find other uses too. VERY RAM-intensive, since the buffer is in MCU
-// memory and not the display driver...GXFcanvas1 might be minimally useful
-// on an Uno-class board, but this and the others are much more likely to
-// require at least a Mega or various recent ARM-type boards (recommended,
-// as the text+bitmap draw can be pokey). GFXcanvas1 requires 1 bit per
-// pixel (rounded up to nearest byte per scanline), GFXcanvas8 is 1 byte
-// per pixel (no scanline pad), and GFXcanvas16 uses 2 bytes per pixel (no
-// scanline pad).
-// NOT EXTENSIVELY TESTED YET. MAY CONTAIN WORST BUGS KNOWN TO HUMANKIND.
-
-/**************************************************************************/
-/*!
- @brief Instatiate a GFX 1-bit canvas context for graphics
- @param w Display width, in pixels
- @param h Display height, in pixels
-*/
-/**************************************************************************/
-GFXcanvas1::GFXcanvas1(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {
- uint16_t bytes = ((w + 7) / 8) * h;
- if((buffer = (uint8_t *)malloc(bytes))) {
- memset(buffer, 0, bytes);
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Delete the canvas, free memory
-*/
-/**************************************************************************/
-GFXcanvas1::~GFXcanvas1(void) {
- if(buffer) free(buffer);
-}
-
-/**************************************************************************/
-/*!
- @brief Get a pointer to the internal buffer memory
- @returns A pointer to the allocated buffer
-*/
-/**************************************************************************/
-uint8_t* GFXcanvas1::getBuffer(void) {
- return buffer;
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a pixel to the canvas framebuffer
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas1::drawPixel(int16_t x, int16_t y, uint16_t color) {
-#ifdef __AVR__
- // Bitmask tables of 0x80>>X and ~(0x80>>X), because X>>Y is slow on AVR
- static const uint8_t PROGMEM
- GFXsetBit[] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 },
- GFXclrBit[] = { 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0xFE };
-#endif
-
- if(buffer) {
- if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;
-
- int16_t t;
- switch(rotation) {
- case 1:
- t = x;
- x = WIDTH - 1 - y;
- y = t;
- break;
- case 2:
- x = WIDTH - 1 - x;
- y = HEIGHT - 1 - y;
- break;
- case 3:
- t = x;
- x = y;
- y = HEIGHT - 1 - t;
- break;
- }
-
- uint8_t *ptr = &buffer[(x / 8) + y * ((WIDTH + 7) / 8)];
-#ifdef __AVR__
- if(color) *ptr |= pgm_read_byte(&GFXsetBit[x & 7]);
- else *ptr &= pgm_read_byte(&GFXclrBit[x & 7]);
-#else
- if(color) *ptr |= 0x80 >> (x & 7);
- else *ptr &= ~(0x80 >> (x & 7));
-#endif
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Fill the framebuffer completely with one color
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas1::fillScreen(uint16_t color) {
- if(buffer) {
- uint16_t bytes = ((WIDTH + 7) / 8) * HEIGHT;
- memset(buffer, color ? 0xFF : 0x00, bytes);
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Instatiate a GFX 8-bit canvas context for graphics
- @param w Display width, in pixels
- @param h Display height, in pixels
-*/
-/**************************************************************************/
-GFXcanvas8::GFXcanvas8(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {
- uint32_t bytes = w * h;
- if((buffer = (uint8_t *)malloc(bytes))) {
- memset(buffer, 0, bytes);
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Delete the canvas, free memory
-*/
-/**************************************************************************/
-GFXcanvas8::~GFXcanvas8(void) {
- if(buffer) free(buffer);
-}
-
-
-/**************************************************************************/
-/*!
- @brief Get a pointer to the internal buffer memory
- @returns A pointer to the allocated buffer
-*/
-/**************************************************************************/
-uint8_t* GFXcanvas8::getBuffer(void) {
- return buffer;
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a pixel to the canvas framebuffer
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas8::drawPixel(int16_t x, int16_t y, uint16_t color) {
- if(buffer) {
- if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;
-
- int16_t t;
- switch(rotation) {
- case 1:
- t = x;
- x = WIDTH - 1 - y;
- y = t;
- break;
- case 2:
- x = WIDTH - 1 - x;
- y = HEIGHT - 1 - y;
- break;
- case 3:
- t = x;
- x = y;
- y = HEIGHT - 1 - t;
- break;
- }
-
- buffer[x + y * WIDTH] = color;
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Fill the framebuffer completely with one color
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas8::fillScreen(uint16_t color) {
- if(buffer) {
- memset(buffer, color, WIDTH * HEIGHT);
- }
-}
-
-void GFXcanvas8::writeFastHLine(int16_t x, int16_t y,
- int16_t w, uint16_t color) {
-
- if((x >= _width) || (y < 0) || (y >= _height)) return;
- int16_t x2 = x + w - 1;
- if(x2 < 0) return;
-
- // Clip left/right
- if(x < 0) {
- x = 0;
- w = x2 + 1;
- }
- if(x2 >= _width) w = _width - x;
-
- int16_t t;
- switch(rotation) {
- case 1:
- t = x;
- x = WIDTH - 1 - y;
- y = t;
- break;
- case 2:
- x = WIDTH - 1 - x;
- y = HEIGHT - 1 - y;
- break;
- case 3:
- t = x;
- x = y;
- y = HEIGHT - 1 - t;
- break;
- }
-
- memset(buffer + y * WIDTH + x, color, w);
-}
-
-/**************************************************************************/
-/*!
- @brief Instatiate a GFX 16-bit canvas context for graphics
- @param w Display width, in pixels
- @param h Display height, in pixels
-*/
-/**************************************************************************/
-GFXcanvas16::GFXcanvas16(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {
- uint32_t bytes = w * h * 2;
- if((buffer = (uint16_t *)malloc(bytes))) {
- memset(buffer, 0, bytes);
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Delete the canvas, free memory
-*/
-/**************************************************************************/
-GFXcanvas16::~GFXcanvas16(void) {
- if(buffer) free(buffer);
-}
-
-/**************************************************************************/
-/*!
- @brief Get a pointer to the internal buffer memory
- @returns A pointer to the allocated buffer
-*/
-/**************************************************************************/
-uint16_t* GFXcanvas16::getBuffer(void) {
- return buffer;
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a pixel to the canvas framebuffer
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas16::drawPixel(int16_t x, int16_t y, uint16_t color) {
- if(buffer) {
- if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;
-
- int16_t t;
- switch(rotation) {
- case 1:
- t = x;
- x = WIDTH - 1 - y;
- y = t;
- break;
- case 2:
- x = WIDTH - 1 - x;
- y = HEIGHT - 1 - y;
- break;
- case 3:
- t = x;
- x = y;
- y = HEIGHT - 1 - t;
- break;
- }
-
- buffer[x + y * WIDTH] = color;
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Fill the framebuffer completely with one color
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void GFXcanvas16::fillScreen(uint16_t color) {
- if(buffer) {
- uint8_t hi = color >> 8, lo = color & 0xFF;
- if(hi == lo) {
- memset(buffer, lo, WIDTH * HEIGHT * 2);
- } else {
- uint32_t i, pixels = WIDTH * HEIGHT;
- for(i=0; i
-
-
-// Many (but maybe not all) non-AVR board installs define macros
-// for compatibility with existing PROGMEM-reading AVR code.
-// Do our own checks and defines here for good measure...
-
-#ifndef pgm_read_byte
- #define pgm_read_byte(addr) (*(const unsigned char *)(addr))
-#endif
-#ifndef pgm_read_word
- #define pgm_read_word(addr) (*(const unsigned short *)(addr))
-#endif
-#ifndef pgm_read_dword
- #define pgm_read_dword(addr) (*(const unsigned long *)(addr))
-#endif
-
-// Pointers are a peculiar case...typically 16-bit on AVR boards,
-// 32 bits elsewhere. Try to accommodate both...
-
-#if !defined(__INT_MAX__) || (__INT_MAX__ > 0xFFFF)
- #define pgm_read_pointer(addr) ((void *)pgm_read_dword(addr))
-#else
- #define pgm_read_pointer(addr) ((void *)pgm_read_word(addr))
-#endif
-
-#ifndef MIN
-#define MIN(a,b) (((a) < (b)) ? (a) : (b))
-#endif
-
-#ifndef _swap_int16_t
-#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; }
-#endif
-
-
-/// A generic graphics superclass that can handle all sorts of drawing. At a minimum you can subclass and provide drawPixel(). At a maximum you can do a ton of overriding to optimize. Used for any/all Adafruit displays!
-class Adafruit_GFX : public Print {
-
- public:
-
- Adafruit_GFX(int16_t w, int16_t h); // Constructor
-
- // This MUST be defined by the subclass:
- virtual void drawPixel(int16_t x, int16_t y, uint16_t color) = 0; ///< Virtual drawPixel() function to draw to the screen/framebuffer/etc, must be overridden in subclass. @param x X coordinate. @param y Y coordinate. @param color 16-bit pixel color.
-
- // TRANSACTION API / CORE DRAW API
- // These MAY be overridden by the subclass to provide device-specific
- // optimized code. Otherwise 'generic' versions are used.
- virtual void startWrite(void);
- virtual void writePixel(int16_t x, int16_t y, uint16_t color);
- virtual void writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
- virtual void writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);
- virtual void writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
- virtual void writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color);
- virtual void endWrite(void);
-
- // CONTROL API
- // These MAY be overridden by the subclass to provide device-specific
- // optimized code. Otherwise 'generic' versions are used.
- virtual void setRotation(uint8_t r);
- virtual void invertDisplay(bool i);
-
- // BASIC DRAW API
- // These MAY be overridden by the subclass to provide device-specific
- // optimized code. Otherwise 'generic' versions are used.
- virtual void
- // It's good to implement those, even if using transaction API
- drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color),
- drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color),
- fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color),
- fillScreen(uint16_t color),
- // Optional and probably not necessary to change
- drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color),
- drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
-
- // These exist only with Adafruit_GFX (no subclass overrides)
- void
- drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),
- drawCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,
- uint16_t color),
- fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),
- fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,
- int16_t delta, uint16_t color),
- drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,
- int16_t x2, int16_t y2, uint16_t color),
- fillTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,
- int16_t x2, int16_t y2, uint16_t color),
- drawRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,
- int16_t radius, uint16_t color),
- fillRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,
- int16_t radius, uint16_t color),
- drawBitmap(int16_t x, int16_t y, const uint8_t bitmap[],
- int16_t w, int16_t h, uint16_t color),
- drawBitmap(int16_t x, int16_t y, const uint8_t bitmap[],
- int16_t w, int16_t h, uint16_t color, uint16_t bg),
- drawBitmap(int16_t x, int16_t y, uint8_t *bitmap,
- int16_t w, int16_t h, uint16_t color),
- drawBitmap(int16_t x, int16_t y, uint8_t *bitmap,
- int16_t w, int16_t h, uint16_t color, uint16_t bg),
- drawXBitmap(int16_t x, int16_t y, const uint8_t bitmap[],
- int16_t w, int16_t h, uint16_t color),
- drawGrayscaleBitmap(int16_t x, int16_t y, const uint8_t bitmap[],
- int16_t w, int16_t h),
- drawGrayscaleBitmap(int16_t x, int16_t y, uint8_t *bitmap,
- int16_t w, int16_t h),
- drawGrayscaleBitmap(int16_t x, int16_t y,
- const uint8_t bitmap[], const uint8_t mask[],
- int16_t w, int16_t h),
- drawGrayscaleBitmap(int16_t x, int16_t y,
- uint8_t *bitmap, uint8_t *mask, int16_t w, int16_t h),
- drawRGBBitmap(int16_t x, int16_t y, const uint16_t bitmap[],
- int16_t w, int16_t h),
- drawRGBBitmap(int16_t x, int16_t y, uint16_t *bitmap,
- int16_t w, int16_t h),
- drawRGBBitmap(int16_t x, int16_t y,
- const uint16_t bitmap[], const uint8_t mask[],
- int16_t w, int16_t h),
- drawRGBBitmap(int16_t x, int16_t y,
- uint16_t *bitmap, uint8_t *mask, int16_t w, int16_t h),
- drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color,
- uint16_t bg, uint8_t size),
- setCursor(int16_t x, int16_t y),
- setTextColor(uint16_t c),
- setTextColor(uint16_t c, uint16_t bg),
- setTextSize(uint8_t s),
- setTextWrap(bool w),
- cp437(bool x=true),
- setFont(const GFXfont *f = NULL),
- getTextBounds(const char *string, int16_t x, int16_t y,
- int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h),
- getTextBounds(const std::string &str, int16_t x, int16_t y,
- int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h);
-
- virtual void write(uint8_t);
-
- int16_t height(void) const;
- int16_t width(void) const;
-
- uint8_t getRotation(void) const;
-
- // get current cursor position (get rotation safe maximum values, using: width() for x, height() for y)
- int16_t getCursorX(void) const;
- int16_t getCursorY(void) const;
-
- protected:
- void
- charBounds(char c, int16_t *x, int16_t *y,
- int16_t *minx, int16_t *miny, int16_t *maxx, int16_t *maxy);
- const int16_t
- WIDTH, ///< This is the 'raw' display width - never changes
- HEIGHT; ///< This is the 'raw' display height - never changes
- int16_t
- _width, ///< Display width as modified by current rotation
- _height, ///< Display height as modified by current rotation
- cursor_x, ///< x location to start print()ing text
- cursor_y; ///< y location to start print()ing text
- uint16_t
- textcolor, ///< 16-bit background color for print()
- textbgcolor; ///< 16-bit text color for print()
- uint8_t
- textsize, ///< Desired magnification of text to print()
- rotation; ///< Display rotation (0 thru 3)
- bool
- wrap, ///< If set, 'wrap' text at right edge of display
- _cp437; ///< If set, use correct CP437 charset (default is off)
- GFXfont
- *gfxFont; ///< Pointer to special font
-};
-
-
-/// A simple drawn button UI element
-class Adafruit_GFX_Button {
-
- public:
- Adafruit_GFX_Button(void);
- // "Classic" initButton() uses center & size
- void initButton(Adafruit_GFX *gfx, int16_t x, int16_t y,
- uint16_t w, uint16_t h, uint16_t outline, uint16_t fill,
- uint16_t textcolor, char *label, uint8_t textsize);
- // New/alt initButton() uses upper-left corner & size
- void initButtonUL(Adafruit_GFX *gfx, int16_t x1, int16_t y1,
- uint16_t w, uint16_t h, uint16_t outline, uint16_t fill,
- uint16_t textcolor, char *label, uint8_t textsize);
- void drawButton(bool inverted = false);
- bool contains(int16_t x, int16_t y);
-
- void press(bool p);
- bool isPressed();
- bool justPressed();
- bool justReleased();
-
- private:
- Adafruit_GFX *_gfx;
- int16_t _x1, _y1; // Coordinates of top-left corner
- uint16_t _w, _h;
- uint8_t _textsize;
- uint16_t _outlinecolor, _fillcolor, _textcolor;
- char _label[10];
-
- bool currstate, laststate;
-};
-
-
-/// A GFX 1-bit canvas context for graphics
-class GFXcanvas1 : public Adafruit_GFX {
- public:
- GFXcanvas1(uint16_t w, uint16_t h);
- ~GFXcanvas1(void);
- void drawPixel(int16_t x, int16_t y, uint16_t color),
- fillScreen(uint16_t color);
- uint8_t *getBuffer(void);
- private:
- uint8_t *buffer;
-};
-
-
-/// A GFX 8-bit canvas context for graphics
-class GFXcanvas8 : public Adafruit_GFX {
- public:
- GFXcanvas8(uint16_t w, uint16_t h);
- ~GFXcanvas8(void);
- void drawPixel(int16_t x, int16_t y, uint16_t color),
- fillScreen(uint16_t color),
- writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
-
- uint8_t *getBuffer(void);
- private:
- uint8_t *buffer;
-};
-
-
-/// A GFX 16-bit canvas context for graphics
-class GFXcanvas16 : public Adafruit_GFX {
- public:
- GFXcanvas16(uint16_t w, uint16_t h);
- ~GFXcanvas16(void);
- void drawPixel(int16_t x, int16_t y, uint16_t color),
- fillScreen(uint16_t color);
- uint16_t *getBuffer(void);
- private:
- uint16_t *buffer;
-};
-
-#endif // _ADAFRUIT_GFX_H
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.cpp b/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.cpp
deleted file mode 100644
index b862d21..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.cpp
+++ /dev/null
@@ -1,348 +0,0 @@
-/*!
- * @file Adafruit_HX8357.cpp
- *
- * @mainpage Adafruit HX8357 TFT Displays
- *
- * @section intro_sec Introduction
- *
- * This is the documentation for Adafruit's ILI9341 driver for the Arduino
- * platform.
- *
- * This library works with the Adafruit 3.5" TFT 320x480 + Touchscreen Breakout
- * http://www.adafruit.com/products/2050
- *
- * Adafruit TFT FeatherWing - 3.5" 480x320 Touchscreen for Feathers
- * https://www.adafruit.com/product/3651
- *
- * These displays use SPI to communicate. This requires 4 pins (MOSI,
- * SCK, select, data/command) and optionally a reset pin. Hardware SPI
- * or 'bitbang' software SPI are both supported.
- *
- * Adafruit invests time and resources providing this open source code,
- * please support Adafruit and open-source hardware by purchasing
- * products from Adafruit!
- *
- * @section dependencies Dependencies
- *
- * This library depends on
- * Adafruit_GFX being present on your system. Please make sure you have
- * installed the latest version before using this library.
- *
- * @section author Author
- *
- * Written by Limor Fried/Ladyada for Adafruit Industries, with
- * contributions from the open source community.
- *
- * @section license License
- *
- * BSD license, all text here must be included in any redistribution.
- */
-
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "Adafruit_HX8357.h"
-#include
-#include "cmsis_os.h" // for semaphore support
-
-#define MADCTL_MY 0x80 ///< Bottom to top
-#define MADCTL_MX 0x40 ///< Right to left
-#define MADCTL_MV 0x20 ///< Reverse Mode
-#define MADCTL_ML 0x10 ///< LCD refresh Bottom to top
-#define MADCTL_RGB 0x00 ///< Red-Green-Blue pixel order
-#define MADCTL_BGR 0x08 ///< Blue-Green-Red pixel order
-#define MADCTL_MH 0x04 ///< LCD refresh right to left
-
-// THIS REALLY SHOULD GO IN SPITFT (PART OF ADAFRUIT_GFX),
-// AND CAN BE FURTHER EXPANDED (e.g. add 12 MHz for M0, 24 for M4),
-// BUT TEMPORARILY FOR NOW IT'S HERE:
-
-#if defined (ARDUINO_ARCH_ARC32)
- #define SPI_DEFAULT_FREQ 16000000
-#elif defined (__AVR__) || defined(TEENSYDUINO)
- #define SPI_DEFAULT_FREQ 8000000
-#elif defined(ESP8266) || defined (ARDUINO_MAXIM)
- #define SPI_DEFAULT_FREQ 16000000
-#elif defined(ESP32)
- #define SPI_DEFAULT_FREQ 24000000
-#elif defined(RASPI)
- #define SPI_DEFAULT_FREQ 24000000
-#else
- #define SPI_DEFAULT_FREQ 24000000
-#endif
-
-// CONSTRUCTORS, DESTRUCTOR ------------------------------------------------
-
-/*!
- @brief Constructor for Adafruit_HX8357 cisplays, using software
- (bitbang) SPI.
- @param cs
- Chip select pin (using Arduino pin numbering).
- @param dc
- Data/Command pin (using Arduino pin numbering).
- @param mosi
- SPI MOSI pin (using Arduino pin numbering).
- @param sclk
- SPI Clock pin (using Arduino pin numbering).
- @param rst
- Reset pin (Arduino pin numbering, optional, pass -1 if unused).
- @param miso
- SPI MISO pin (Arduino pin #, optional, pass -1 if unused).
- @param type
- Display type, HX8357D (default if unspecified) or HX8357B.
- @return Adafruit_HX8357 object.
- @note Call the object's begin() function before use.
-*/
-Adafruit_HX8357::Adafruit_HX8357(SPI * spi, IO * dcPin, IO * rstPin, uint8_t type) : Adafruit_SPITFT(
- HX8357_TFTWIDTH, HX8357_TFTHEIGHT, spi, dcPin, rstPin),
- displayType(type) {
-}
-
-/*!
- @brief Destructor for Adafruit_HX8357 object.
- @return None (void).
-*/
-Adafruit_HX8357::~Adafruit_HX8357(void) {
-}
-
-// INIT DISPLAY ------------------------------------------------------------
-
-static const uint8_t
- initb[] = {
- HX8357B_SETPOWER, 3,
- 0x44, 0x41, 0x06,
- HX8357B_SETVCOM, 2,
- 0x40, 0x10,
- HX8357B_SETPWRNORMAL, 2,
- 0x05, 0x12,
- HX8357B_SET_PANEL_DRIVING, 5,
- 0x14, 0x3b, 0x00, 0x02, 0x11,
- HX8357B_SETDISPLAYFRAME, 1,
- 0x0c, // 6.8mhz
- HX8357B_SETPANELRELATED, 1,
- 0x01, // BGR
- 0xEA, 3, // seq_undefined1, 3 args
- 0x03, 0x00, 0x00,
- 0xEB, 4, // undef2, 4 args
- 0x40, 0x54, 0x26, 0xdb,
- HX8357B_SETGAMMA, 12,
- 0x00, 0x15, 0x00, 0x22, 0x00, 0x08, 0x77, 0x26, 0x66, 0x22, 0x04, 0x00,
- HX8357_MADCTL, 1,
- 0xC0,
- HX8357_COLMOD, 1,
- 0x55,
- HX8357_PASET, 4,
- 0x00, 0x00, 0x01, 0xDF,
- HX8357_CASET, 4,
- 0x00, 0x00, 0x01, 0x3F,
- HX8357B_SETDISPMODE, 1,
- 0x00, // CPU (DBI) and internal oscillation ??
- HX8357_SLPOUT, 0x80 + 120/5, // Exit sleep, then delay 120 ms
- HX8357_DISPON, 0x80 + 10/5, // Main screen turn on, delay 10 ms
- 0 // END OF COMMAND LIST
- }, initd[] = {
- HX8357_SWRESET, 0x80 + 10/5, // Soft reset, then delay 10 ms
- HX8357D_SETC, 3,
- 0xFF, 0x83, 0x57,
- 0xFF, 0x80 + 300/5, // No command, just delay 300 ms
- HX8357_SETRGB, 4,
- 0x80, 0x00, 0x06, 0x06, // 0x80 enables SDO pin (0x00 disables)
- HX8357D_SETCOM, 1,
- 0x25, // -1.52V
- HX8357_SETOSC, 1,
- 0x68, // Normal mode 70Hz, Idle mode 55 Hz
- HX8357_SETPANEL, 1,
- 0x05, // BGR, Gate direction swapped
- HX8357_SETPWR1, 6,
- 0x00, // Not deep standby
- 0x15, // BT
- 0x1C, // VSPR
- 0x1C, // VSNR
- 0x83, // AP
- 0xAA, // FS
- HX8357D_SETSTBA, 6,
- 0x50, // OPON normal
- 0x50, // OPON idle
- 0x01, // STBA
- 0x3C, // STBA
- 0x1E, // STBA
- 0x08, // GEN
- HX8357D_SETCYC, 7,
- 0x02, // NW 0x02
- 0x40, // RTN
- 0x00, // DIV
- 0x2A, // DUM
- 0x2A, // DUM
- 0x0D, // GDON
- 0x78, // GDOFF
- HX8357D_SETGAMMA, 34,
- 0x02, 0x0A, 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b,
- 0x42, 0x3A, 0x27, 0x1B, 0x08, 0x09, 0x03, 0x02, 0x0A,
- 0x11, 0x1d, 0x23, 0x35, 0x41, 0x4b, 0x4b, 0x42, 0x3A,
- 0x27, 0x1B, 0x08, 0x09, 0x03, 0x00, 0x01,
- HX8357_COLMOD, 1,
- 0x55, // 16 bit
- HX8357_MADCTL, 1,
- 0xC0,
- HX8357_TEON, 1,
- 0x00, // TW off
- HX8357_TEARLINE, 2,
- 0x00, 0x02,
- HX8357_SLPOUT, 0x80 + 150/5, // Exit Sleep, then delay 150 ms
- HX8357_DISPON, 0x80 + 50/5, // Main screen turn on, delay 50 ms
- 0, // END OF COMMAND LIST
- };
-
-/*!
- @brief Initialize HX8357 chip. Connects to the HX8357 over SPI and
- sends initialization commands.
- @param freq
- SPI bitrate -- default of 0 will use a (usually) platform-
- optimized value, e.g. 8 MHz on AVR, 12 MHz on M0.
- @return None (void).
-*/
-void Adafruit_HX8357::begin(uint32_t type) {
- // Older version of this library accepted a display type as the only
- // argument (HX8357D or HX8357B), but SPITFT (part of GFX lib) REQUIRES
- // the begin() function instead accept an SPI bitrate (or 0 for default),
- // so display type was moved to the constructor. Examples will be
- // updated, but just in case there's old code around, we pull shenanigans
- // here...the values for HX8357D and HX8357B (0xD and 0xB, respectively)
- // would make for absurd SPI bitrates...so if we receive one of those
- // values, assume it's old code intending to pass the display type.
- // Override the displayType value that was set in the constructor with
- // the value passed here, and use the default SPI bitrate for platform.
- if(type == HX8357D) {
- displayType = type;
- } else if(HX8357B) {
- displayType = type;
- }
-
- reset();
-
- startWrite();
- const uint8_t *addr = (displayType == HX8357B) ? initb : initd;
- uint8_t cmd, x, numArgs;
- while((cmd = pgm_read_byte(addr++)) > 0) { // '0' command ends list
- if(cmd != 0xFF) writeCommand(cmd); // '255' is ignored
- x = pgm_read_byte(addr++);
- numArgs = x & 0x7F;
- if(x & 0x80) { // If high bit set...
- osDelay(numArgs * 5); // numArgs is actually a delay time (5ms units)
- } else { // Otherwise, issue args to command...
- while(numArgs--) spiWrite(pgm_read_byte(addr++));
- }
- }
- endWrite();
-
- _width = HX8357_TFTWIDTH; // Screen dimensions for default rotation 0
- _height = HX8357_TFTHEIGHT;
-}
-
-// GFX FUNCTIONS -----------------------------------------------------------
-
-/*!
- @brief Set origin of (0,0) and orientation of TFT display
- @param m
- The index for rotation, from 0-3 inclusive
- @return None (void).
-*/
-void Adafruit_HX8357::setRotation(uint8_t m) {
-
- rotation = m & 3; // can't be higher than 3
- switch(rotation) {
- case 0:
- m = MADCTL_MX | MADCTL_MY | MADCTL_RGB;
- _width = HX8357_TFTWIDTH;
- _height = HX8357_TFTHEIGHT;
- break;
- case 1:
- m = MADCTL_MV | MADCTL_MY | MADCTL_RGB;
- _width = HX8357_TFTHEIGHT;
- _height = HX8357_TFTWIDTH;
- break;
- case 2:
- m = MADCTL_RGB;
- _width = HX8357_TFTWIDTH;
- _height = HX8357_TFTHEIGHT;
- break;
- case 3:
- m = MADCTL_MX | MADCTL_MV | MADCTL_RGB;
- _width = HX8357_TFTHEIGHT;
- _height = HX8357_TFTWIDTH;
- break;
- }
-
- startWrite();
- writeCommand(HX8357_MADCTL);
- spiWrite(m);
- endWrite();
-}
-
-/*!
- @brief Enable/Disable display color inversion
- @param invert
- True to invert display, False for normal color.
- @return None (void).
-*/
-void Adafruit_HX8357::invertDisplay(bool invert) {
- startWrite();
- writeCommand(invert ? HX8357_INVON : HX8357_INVOFF);
- endWrite();
-}
-
-/*!
- @brief Set the "address window" - the rectangle we will write to
- graphics RAM with the next chunk of SPI data writes. The
- HX8357 will automatically wrap the data as each row is filled.
- @param x1
- Leftmost column of rectangle (screen pixel coordinates).
- @param y1
- Topmost row of rectangle (screen pixel coordinates).
- @param w
- Width of rectangle.
- @param h
- Height of rectangle.
- @return None (void).
-*/
-void Adafruit_HX8357::setAddrWindow(
- uint16_t x1, uint16_t y1, uint16_t w, uint16_t h) {
- uint16_t x2 = (x1 + w - 1),
- y2 = (y1 + h - 1);
- writeCommand(HX8357_CASET); // Column address set
- SPI_WRITE16(x1);
- SPI_WRITE16(x2);
- writeCommand(HX8357_PASET); // Row address set
- SPI_WRITE16(y1);
- SPI_WRITE16(y2);
- writeCommand(HX8357_RAMWR); // Write to RAM
-}
-
-/*!
- @brief Read 8 bits of data from HX8357 configuration memory (not RAM).
- This is highly undocumented/supported and should be avoided,
- function is only included because some of the examples use it.
- @param command
- The command register to read data from.
- @param index
- The byte index into the command to read from.
- @return Unsigned 8-bit data read from HX8357 register.
-*/
-/**************************************************************************/
-uint8_t Adafruit_HX8357::readcommand8(uint8_t command, uint8_t index) {
- uint8_t result;
- startWrite();
- SPI_DC_LOW();
- spiWrite(command);
- SPI_DC_HIGH();
- do {
- result = spiRead();
- } while(index--); // Discard bytes up to index'th
- endWrite();
- return result;
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.h b/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.h
deleted file mode 100644
index ada5415..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_HX8357.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*!
- * @file Adafruit_HX8357.h
- *
- * This is the documentation for Adafruit's ILI9341 driver for the Arduino
- * platform.
- *
- * This library works with the Adafruit 3.5" TFT 320x480 + Touchscreen Breakout
- * http://www.adafruit.com/products/2050
- *
- * Adafruit TFT FeatherWing - 3.5" 480x320 Touchscreen for Feathers
- * https://www.adafruit.com/product/3651
- *
- * These displays use SPI to communicate. This requires 4 pins (MOSI,
- * SCK, select, data/command) and optionally a reset pin. Hardware SPI
- * or 'bitbang' software SPI are both supported.
- *
- * Adafruit invests time and resources providing this open source code,
- * please support Adafruit and open-source hardware by purchasing
- * products from Adafruit!
- *
- * This library depends on
- * Adafruit_GFX being present on your system. Please make sure you have
- * installed the latest version before using this library.
- *
- * Written by Limor Fried/Ladyada for Adafruit Industries, with
- * contributions from the open source community.
- *
- * BSD license, all text here must be included in any redistribution.
- */
-
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef _ADAFRUIT_HX8357_H
-#define _ADAFRUIT_HX8357_H
-
-#include "stm32h7xx_hal.h"
-#include "Adafruit_SPITFT.h"
-
-#define HX8357D 0xD
-#define HX8357B 0xB
-
-#define HX8357_TFTWIDTH 320
-#define HX8357_TFTHEIGHT 480
-
-#define HX8357_NOP 0x00
-#define HX8357_SWRESET 0x01
-#define HX8357_RDDID 0x04
-#define HX8357_RDDST 0x09
-
-#define HX8357_RDPOWMODE 0x0A
-#define HX8357_RDMADCTL 0x0B
-#define HX8357_RDCOLMOD 0x0C
-#define HX8357_RDDIM 0x0D
-#define HX8357_RDDSDR 0x0F
-
-#define HX8357_SLPIN 0x10
-#define HX8357_SLPOUT 0x11
-#define HX8357B_PTLON 0x12
-#define HX8357B_NORON 0x13
-
-#define HX8357_INVOFF 0x20
-#define HX8357_INVON 0x21
-#define HX8357_DISPOFF 0x28
-#define HX8357_DISPON 0x29
-
-#define HX8357_CASET 0x2A
-#define HX8357_PASET 0x2B
-#define HX8357_RAMWR 0x2C
-#define HX8357_RAMRD 0x2E
-
-#define HX8357B_PTLAR 0x30
-#define HX8357_TEON 0x35
-#define HX8357_TEARLINE 0x44
-#define HX8357_MADCTL 0x36
-#define HX8357_COLMOD 0x3A
-
-#define HX8357_SETOSC 0xB0
-#define HX8357_SETPWR1 0xB1
-#define HX8357B_SETDISPLAY 0xB2
-#define HX8357_SETRGB 0xB3
-#define HX8357D_SETCOM 0xB6
-
-#define HX8357B_SETDISPMODE 0xB4
-#define HX8357D_SETCYC 0xB4
-#define HX8357B_SETOTP 0xB7
-#define HX8357D_SETC 0xB9
-
-#define HX8357B_SET_PANEL_DRIVING 0xC0
-#define HX8357D_SETSTBA 0xC0
-#define HX8357B_SETDGC 0xC1
-#define HX8357B_SETID 0xC3
-#define HX8357B_SETDDB 0xC4
-#define HX8357B_SETDISPLAYFRAME 0xC5
-#define HX8357B_GAMMASET 0xC8
-#define HX8357B_SETCABC 0xC9
-#define HX8357_SETPANEL 0xCC
-
-#define HX8357B_SETPOWER 0xD0
-#define HX8357B_SETVCOM 0xD1
-#define HX8357B_SETPWRNORMAL 0xD2
-
-#define HX8357B_RDID1 0xDA
-#define HX8357B_RDID2 0xDB
-#define HX8357B_RDID3 0xDC
-#define HX8357B_RDID4 0xDD
-
-#define HX8357D_SETGAMMA 0xE0
-
-#define HX8357B_SETGAMMA 0xC8
-#define HX8357B_SETPANELRELATED 0xE9
-
-// Plan is to move this to GFX header (with different prefix), though
-// defines will be kept here for existing code that might be referencing
-// them. Some additional ones are in the ILI9341 lib -- add all in GFX!
-// Color definitions
-#define HX8357_BLACK 0x0000 ///< BLACK color for drawing graphics
-#define HX8357_BLUE 0x001F ///< BLUE color for drawing graphics
-#define HX8357_RED 0xF800 ///< RED color for drawing graphics
-#define HX8357_GREEN 0x07E0 ///< GREEN color for drawing graphics
-#define HX8357_CYAN 0x07FF ///< CYAN color for drawing graphics
-#define HX8357_MAGENTA 0xF81F ///< MAGENTA color for drawing graphics
-#define HX8357_YELLOW 0xFFE0 ///< YELLOW color for drawing graphics
-#define HX8357_WHITE 0xFFFF ///< WHITE color for drawing graphics
-
-/*!
- @brief Class to manage hardware interface with HX8357 chipset.
-*/
-class Adafruit_HX8357 : public Adafruit_SPITFT {
- public:
- Adafruit_HX8357(SPI * spi, IO * dcPin, IO * rstPin, uint8_t type = HX8357D);
- ~Adafruit_HX8357(void);
-
- void begin(uint32_t freq = 0),
- setRotation(uint8_t r),
- invertDisplay(bool i),
- setAddrWindow(uint16_t x, uint16_t y, uint16_t w, uint16_t h);
- uint8_t readcommand8(uint8_t command, uint8_t index = 0);
- private:
- uint8_t displayType; // HX8357D vs HX8357B
-};
-
-#endif // _ADAFRUIT_HX8357_H
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.cpp b/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.cpp
deleted file mode 100644
index af4ba15..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.cpp
+++ /dev/null
@@ -1,680 +0,0 @@
-/*!
-* @file Adafruit_SPITFT.cpp
-*
-* @mainpage Adafruit SPI TFT Displays
-*
-* @section intro_sec Introduction
- This is our library for generic SPI TFT Displays with
- address windows and 16 bit color (e.g. ILI9341, HX8357D, ST7735...)
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
-* @section dependencies Dependencies
-*
-* This library depends on
-* Adafruit_GFX being present on your system. Please make sure you have
-* installed the latest version before using this library.
-*
-* @section author Author
-*
-* Written by Limor "ladyada" Fried for Adafruit Industries.
-*
-* @section license License
-*
-* BSD license, all text here must be included in any redistribution.
-*
-*/
-
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#include "stm32h7xx_hal.h"
-#include
-#include "Adafruit_SPITFT.h"
-#include "Adafruit_SPITFT_Macros.h"
-#include "SPI.h"
-#include "IO.h"
-#include "cmsis_os.h" // for delay
-
-#ifdef USE_SPI_DMA
-#include
-#include // memalign() function
-
-// DMA transfer-in-progress indicator and callback
-static volatile bool dma_busy = false;
-static void dma_callback(Adafruit_ZeroDMA *dma) {
- dma_busy = false;
-}
-
-#endif // USE_SPI_DMA
-
-/**************************************************************************/
-/*!
- @brief Pass 8-bit (each) R,G,B, get back 16-bit packed color
- This function converts 8-8-8 RGB data to 16-bit 5-6-5
- @param red Red 8 bit color
- @param green Green 8 bit color
- @param blue Blue 8 bit color
- @return Unsigned 16-bit down-sampled color in 5-6-5 format
-*/
-/**************************************************************************/
-uint16_t Adafruit_SPITFT::color565(uint8_t red, uint8_t green, uint8_t blue) {
- return ((red & 0xF8) << 8) | ((green & 0xFC) << 3) | ((blue & 0xF8) >> 3);
-}
-
-
-/**************************************************************************/
-/*!
- @brief Instantiate Adafruit SPI display driver with hardware SPI
- @param w Display width in pixels
- @param h Display height in pixels
- @param spiClass A pointer to an SPI hardware interface, e.g. &SPI1
- @param cs Chip select pin #
- @param dc Data/Command pin #
- @param rst Reset pin # (optional, pass -1 if unused)
-*/
-/**************************************************************************/
-Adafruit_SPITFT::Adafruit_SPITFT(uint16_t w, uint16_t h, SPI * spi,
- IO * dcPin, IO * rstPin)
- : Adafruit_GFX(w, h), _spi(spi), _dc(dcPin), _rst(rstPin) {
-}
-
-
-/**************************************************************************/
-/*!
- @brief Initialiaze the SPI interface (hardware or software)
- @param freq The desired maximum SPI hardware clock frequency
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::reset(void)
-{
- // toggle RST low to reset
- if (_rst) {
- _rst->High();
- osDelay(100);
- _rst->Low();
- osDelay(100);
- _rst->High();
- osDelay(200);
- }
-
-#ifdef USE_SPI_DMA
-
- // INITIALIZE DMA
-
- if(dma.allocate() == DMA_STATUS_OK) { // Allocate channel
- // The DMA library needs to allocate at least one valid descriptor,
- // so we do that here. It's not used in the usual sense though,
- // just before a transfer we copy descriptor[0] to this address.
- if(dptr = dma.addDescriptor(NULL, NULL, 42, DMA_BEAT_SIZE_BYTE,
- false, false)) {
- // Allocate 2 scanlines worth of pixels on display's major axis,
- // whichever that is, rounding each up to 2-pixel boundary.
- int major = (WIDTH > HEIGHT) ? WIDTH : HEIGHT;
- major += (major & 1); // -> next 2-pixel bound, if needed.
- maxFillLen = major * 2; // 2 scanlines
- // Note to future self: if you decide to make the pixel buffer
- // much larger, remember that DMA transfer descriptors can't
- // exceed 65,535 bytes (not 65,536), meaning 32,767 pixels tops.
- // Not that we have that kind of RAM to throw around right now.
- if((pixelBuf[0] =
- (uint16_t *)malloc(maxFillLen * sizeof(uint16_t)))) {
- // Alloc OK. Get pointer to start of second scanline.
- pixelBuf[1] = &pixelBuf[0][major];
- // Determine number of DMA descriptors needed to cover
- // entire screen when entire 2-line pixelBuf is used
- // (round up for fractional last descriptor).
- int numDescriptors = (WIDTH * HEIGHT + (maxFillLen - 1)) /
- maxFillLen;
- // DMA descriptors MUST be 128-bit (16 byte) aligned.
- // memalign() is considered 'obsolete' but it's replacements
- // (aligned_alloc() or posix_memalign()) are not currently
- // available in the version of ARM GCC in use, but this is,
- // so here we are.
- if((descriptor = (DmacDescriptor *)memalign(16,
- numDescriptors * sizeof(DmacDescriptor)))) {
- int dmac_id;
- volatile uint32_t *data_reg;
-
- // THIS IS AN AFFRONT TO NATURE, but I don't know
- // any "clean" way to get the sercom number from the
- // SPIClass pointer (e.g. &SPI or &SPI1), which is
- // all we have to work with. SPIClass does contain
- // a SERCOM pointer but it is a PRIVATE member!
- // Doing an UNSPEAKABLY HORRIBLE THING here, directly
- // accessing the first 32-bit value in the SPIClass
- // structure, knowing that's (currently) where the
- // SERCOM pointer lives, but this ENTIRELY DEPENDS
- // on that structure not changing nor the compiler
- // rearranging things. Oh the humanity!
-
- if(*(SERCOM **)_spi == &sercom0) {
- dmac_id = SERCOM0_DMAC_ID_TX;
- data_reg = &SERCOM0->SPI.DATA.reg;
-#if defined SERCOM1
- } else if(*(SERCOM **)_spi == &sercom1) {
- dmac_id = SERCOM1_DMAC_ID_TX;
- data_reg = &SERCOM1->SPI.DATA.reg;
-#endif
-#if defined SERCOM2
- } else if(*(SERCOM **)_spi == &sercom2) {
- dmac_id = SERCOM2_DMAC_ID_TX;
- data_reg = &SERCOM2->SPI.DATA.reg;
-#endif
-#if defined SERCOM3
- } else if(*(SERCOM **)_spi == &sercom3) {
- dmac_id = SERCOM3_DMAC_ID_TX;
- data_reg = &SERCOM3->SPI.DATA.reg;
-#endif
-#if defined SERCOM4
- } else if(*(SERCOM **)_spi == &sercom4) {
- dmac_id = SERCOM4_DMAC_ID_TX;
- data_reg = &SERCOM4->SPI.DATA.reg;
-#endif
-#if defined SERCOM5
- } else if(*(SERCOM **)_spi == &sercom5) {
- dmac_id = SERCOM5_DMAC_ID_TX;
- data_reg = &SERCOM5->SPI.DATA.reg;
-#endif
- }
-
- dma.setPriority(DMA_PRIORITY_3);
- dma.setTrigger(dmac_id);
- dma.setAction(DMA_TRIGGER_ACTON_BEAT);
-
- // Initialize descriptor list.
- for(int d=0; dsetDataMode(SPI_MODE0); // See note in writeColor()
-#endif
- return;
- }
-#else
- SPI_WRITE_PIXELS((uint8_t*)colors , len * 2);
-#endif
-}
-
-/**************************************************************************/
-/*!
- @brief Blit a 2-byte color many times (must have a transaction in progress)
- @param color The 16-bit 5-6-5 Color to draw
- @param len How many pixels to draw
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::writeColor(uint16_t color, uint32_t len) {
-
- if(!len) return; // Avoid 0-byte transfers
-
-#ifdef USE_SPI_DMA
-
- uint8_t hi = color >> 8, lo = color;
-
- int i, d, numDescriptors;
- if(hi == lo) { // If high & low bytes are same...
- onePixelBuf = color;
- // Can do this with a relatively short descriptor list,
- // each transferring a max of 32,767 (not 32,768) pixels.
- // This won't run off the end of the allocated descriptor list,
- // since we're using much larger chunks per descriptor here.
- numDescriptors = (len + 32766) / 32767;
- for(d=0; d lastFillLen) {
- int fillStart = lastFillLen / 2,
- fillEnd = (((len < maxFillLen) ?
- len : maxFillLen) + 1) / 2;
- for(i=fillStart; isetDataMode(SPI_MODE0);
-#endif
-
- // Unfortunately blocking is necessary. An earlier version returned
- // immediately and checked dma_busy on startWrite() instead, but it
- // turns out to be MUCH slower on many graphics operations (as when
- // drawing lines, pixel-by-pixel), perhaps because it's a volatile
- // type and doesn't cache. Working on this.
-
-#else // Non-DMA
-
- #ifdef SPI_HAS_WRITE_PIXELS
- #define TMPBUF_LONGWORDS (SPI_MAX_PIXELS_AT_ONCE + 1) / 2
- #define TMPBUF_PIXELS (TMPBUF_LONGWORDS * 2)
- static uint32_t temp[TMPBUF_LONGWORDS];
- uint32_t c32 = color * 0x00010001;
- uint16_t bufLen = (len < TMPBUF_PIXELS) ? len : TMPBUF_PIXELS,
- xferLen, fillLen;
-
- // Fill temp buffer 32 bits at a time
- fillLen = (bufLen + 1) / 2; // Round up to next 32-bit boundary
- for(uint32_t t=0; t> 8, lo = color;
-
- while(len--) {
- HSPI_WRITE(hi);
- HSPI_WRITE(lo);
- }
- #endif
-
-#endif // end non-DMA
-}
-
-/**************************************************************************/
-/*!
- @brief Write a pixel (must have a transaction in progress)
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::writePixel(int16_t x, int16_t y, uint16_t color) {
- if((x < 0) ||(x >= _width) || (y < 0) || (y >= _height)) return;
- setAddrWindow(x,y,1,1);
- writePixel(color);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a filled rectangle (must have a transaction in progress)
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color){
- if((x >= _width) || (y >= _height)) return;
- int16_t x2 = x + w - 1, y2 = y + h - 1;
- if((x2 < 0) || (y2 < 0)) return;
-
- // Clip left/top
- if(x < 0) {
- x = 0;
- w = x2 + 1;
- }
- if(y < 0) {
- y = 0;
- h = y2 + 1;
- }
-
- // Clip right/bottom
- if(x2 >= _width) w = _width - x;
- if(y2 >= _height) h = _height - y;
-
- setAddrWindow(x, y, w, h);
- writeColor(color, (int32_t)w * h);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly vertical line (must have a transaction in progress)
- @param x Top-most x coordinate
- @param y Top-most y coordinate
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void inline Adafruit_SPITFT::writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color){
- writeFillRect(x, y, 1, h, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly horizontal line (must have a transaction in progress)
- @param x Left-most x coordinate
- @param y Left-most y coordinate
- @param w Width in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void inline Adafruit_SPITFT::writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color){
- writeFillRect(x, y, w, 1, color);
-}
-
-/**************************************************************************/
-/*!
- @brief Draw a pixel - sets up transaction
- @param x x coordinate
- @param y y coordinate
- @param color 16-bit 5-6-5 Color to draw with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::drawPixel(int16_t x, int16_t y, uint16_t color){
- // Clip first...
- if((x >= 0) && (x < _width) && (y >= 0) && (y < _height)) {
- // THEN set up transaction (if needed) and draw...
- startWrite();
- setAddrWindow(x, y, 1, 1);
- writePixel(color);
- endWrite();
- }
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly vertical line - sets up transaction
- @param x Top-most x coordinate
- @param y Top-most y coordinate
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::drawFastVLine(int16_t x, int16_t y,
- int16_t h, uint16_t color) {
- startWrite();
- writeFastVLine(x, y, h, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Write a perfectly horizontal line - sets up transaction
- @param x Left-most x coordinate
- @param y Left-most y coordinate
- @param w Width in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::drawFastHLine(int16_t x, int16_t y,
- int16_t w, uint16_t color) {
- startWrite();
- writeFastHLine(x, y, w, color);
- endWrite();
-}
-
-/**************************************************************************/
-/*!
- @brief Fill a rectangle completely with one color.
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param w Width in pixels
- @param h Height in pixels
- @param color 16-bit 5-6-5 Color to fill with
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
- uint16_t color) {
- startWrite();
- writeFillRect(x,y,w,h,color);
- endWrite();
-}
-
-
-/**************************************************************************/
-/*!
- @brief Invert the display using built-in hardware command
- @param i True if you want to invert, false to make 'normal'
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::invertDisplay(bool i) {
- startWrite();
- writeCommand(i ? invertOnCommand : invertOffCommand);
- endWrite();
-}
-
-
-/**************************************************************************/
-/*!
- @brief Draw a 16-bit image (RGB 5/6/5) at the specified (x,y) position.
- For 16-bit display devices; no color reduction performed.
- Adapted from https://github.com/PaulStoffregen/ILI9341_t3
- by Marc MERLIN. See examples/pictureEmbed to use this.
- 5/6/2017: function name and arguments have changed for compatibility
- with current GFX library and to avoid naming problems in prior
- implementation. Formerly drawBitmap() with arguments in different order.
-
- @param x Top left corner x coordinate
- @param y Top left corner y coordinate
- @param pcolors 16-bit array with 16-bit color bitmap
- @param w Width of bitmap in pixels
- @param h Height of bitmap in pixels
-*/
-/**************************************************************************/
-void Adafruit_SPITFT::drawRGBBitmap(int16_t x, int16_t y,
- uint16_t *pcolors, int16_t w, int16_t h) {
-
- int16_t x2, y2; // Lower-right coord
- if(( x >= _width ) || // Off-edge right
- ( y >= _height) || // " top
- ((x2 = (x+w-1)) < 0 ) || // " left
- ((y2 = (y+h-1)) < 0) ) return; // " bottom
-
- int16_t bx1=0, by1=0, // Clipped top-left within bitmap
- saveW=w; // Save original bitmap width value
- if(x < 0) { // Clip left
- w += x;
- bx1 = -x;
- x = 0;
- }
- if(y < 0) { // Clip top
- h += y;
- by1 = -y;
- y = 0;
- }
- if(x2 >= _width ) w = _width - x; // Clip right
- if(y2 >= _height) h = _height - y; // Clip bottom
-
- pcolors += by1 * saveW + bx1; // Offset bitmap ptr to clipped top-left
- startWrite();
- setAddrWindow(x, y, w, h); // Clipped area
- while(h--) { // For each (clipped) scanline...
- writePixels(pcolors, w); // Push one (clipped) row
- pcolors += saveW; // Advance pointer by one full (unclipped) line
- }
- endWrite();
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.h b/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.h
deleted file mode 100644
index 5b8fa20..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef _ADAFRUIT_SPITFT_
-#define _ADAFRUIT_SPITFT_
-
-#include "SPI.h"
-#include "IO.h"
-#include "Adafruit_GFX.h"
-
-// Estimated RAM usage:
-// 4 bytes/pixel on display major axis + 8 bytes/pixel on minor axis,
-// e.g. 320x240 pixels = 320 * 4 + 240 * 8 = 3,200 bytes.
-typedef volatile uint32_t RwReg;
-#include "Adafruit_SPITFT_Macros.h"
-
-/// A heavily optimized SPI display subclass of GFX. Manages SPI bitbanging, transactions, DMA, etc! Despite being called SPITFT, the classic SPI data/command interface is also used by OLEDs.
-class Adafruit_SPITFT : public Adafruit_GFX {
-
- public:
- Adafruit_SPITFT(uint16_t w, uint16_t h, SPI * spi, IO * dcPin, IO * rstPin = 0);
-
- void reset(void);
-
- // Required Non-Transaction
- void drawPixel(int16_t x, int16_t y, uint16_t color);
-
- // Transaction API
- void startWrite(void);
- void endWrite(void);
-
- void writePixel(int16_t x, int16_t y, uint16_t color);
- void writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
- void writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);
- void writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
-
- // Transaction API not used by GFX
-
- /*!
- @brief SPI displays set an address window rectangle for blitting pixels
- @param x Top left corner x coordinate
- @param y Top left corner x coordinate
- @param w Width of window
- @param h Height of window
- */
- virtual void setAddrWindow(uint16_t x, uint16_t y, uint16_t w, uint16_t h) = 0;
-
- /*!
- @brief Write a 2-byte color (must have a transaction in progress)
- @param color 16-bit 5-6-5 Color to draw
- */
- void inline writePixel(uint16_t color) { SPI_WRITE16(color); }
- void writePixels(uint16_t * colors, uint32_t len);
- void writeColor(uint16_t color, uint32_t len);
- void pushColor(uint16_t color);
-
- // Recommended Non-Transaction
- void drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);
- void drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
- void fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
-
- using Adafruit_GFX::drawRGBBitmap; // Check base class first
- void drawRGBBitmap(int16_t x, int16_t y,
- uint16_t *pcolors, int16_t w, int16_t h);
- void invertDisplay(bool i);
-
- uint16_t color565(uint8_t r, uint8_t g, uint8_t b);
- void writeCommand(uint8_t cmd);
- void spiWrite(uint8_t v);
- uint8_t spiRead(void);
-
- protected:
- SPI * _spi; ///< The SPI device we want to use (set in constructor)
- IO * _dc;
- IO * _rst;
-
- uint8_t invertOnCommand = 0, ///< SPI command byte to turn on invert
- invertOffCommand = 0; ///< SPI command byte to turn off invert
- int16_t _xstart = 0; ///< Many displays don't have pixels starting at (0,0) of the internal framebuffer, this is the x offset from 0 to align
- int16_t _ystart = 0; ///< Many displays don't have pixels starting at (0,0) of the internal framebuffer, this is the y offset from 0 to align
-
-#ifdef USE_SPI_DMA
- Adafruit_ZeroDMA dma; ///< DMA instance
- DmacDescriptor *dptr = NULL; ///< 1st descriptor
- DmacDescriptor *descriptor = NULL; ///< Allocated descriptor list
- uint16_t *pixelBuf[2]; ///< Working buffers
- uint16_t maxFillLen; ///< Max pixels per DMA xfer
- uint16_t lastFillColor = 0; ///< Last color used w/fill
- uint32_t lastFillLen = 0; ///< # of pixels w/last fill
- uint8_t onePixelBuf; ///< For hi==lo fill
-#endif
-};
-
-#endif // !_ADAFRUIT_SPITFT_
diff --git a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT_Macros.h b/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT_Macros.h
deleted file mode 100644
index 003f55e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Adafruit_SPITFT_Macros.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Modified version for use in STM32H7 project by
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef _ADAFRUIT_SPITFT_MACROS
-#define _ADAFRUIT_SPITFT_MACROS
-
-/*
- * Control Pins
- * */
-#define SPI_DC_HIGH() _dc->High()
-#define SPI_DC_LOW() _dc->Low()
-
-#define SPI_CS_HIGH() // handled by BEGIN_TRANSACTION
-#define SPI_CS_LOW() // handled by BEGIN_TRANSACTION
-
-/*
- * Hardware SPI Macros
- * */
-#define SPI_HAS_WRITE_PIXELS true
-#define HSPI_SET_CLOCK()
-#define HSPI_BEGIN_TRANSACTION() _spi->BeginTransaction()
-#define HSPI_END_TRANSACTION() _spi->EndTransaction()
-
-// Optimized SPI
-#define HSPI_READ() _spi->TransactionRead()
-#define HSPI_WRITE(b) _spi->TransactionWrite8(b)
-#define HSPI_WRITE16(s) _spi->TransactionWrite16(s)
-#define HSPI_WRITE32(l) _spi->TransactionWrite32(l)
-#define SPI_MAX_PIXELS_AT_ONCE 32
-//#define HSPI_WRITE_PIXELS(c,l) for(uint32_t i=0; i<(l); i+=2){ HSPI_WRITE(((uint8_t*)(c))[i+1]); SSPI_WRITE(((uint8_t*)(c))[i]); }
-#define HSPI_WRITE_PIXELS(c,l) for(uint32_t i=0; i<(l); i+=2){ HSPI_WRITE16( *((uint16_t*)((uint8_t*)c + i)) ); } // ((uint8_t*)(c))[i]);
-
-
-#define SPI_BEGIN_TRANSACTION() HSPI_BEGIN_TRANSACTION()
-#define SPI_END_TRANSACTION() HSPI_END_TRANSACTION()
-#define SPI_WRITE16(s) HSPI_WRITE16(s)
-#define SPI_WRITE32(l) HSPI_WRITE32(l)
-#define SPI_WRITE_PIXELS(c,l) HSPI_WRITE_PIXELS(c,l)
-
-#endif // _ADAFRUIT_SPITFT_MACROS
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono12pt7b.h
deleted file mode 100644
index 94ecb88..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono12pt7b.h
+++ /dev/null
@@ -1,227 +0,0 @@
-const uint8_t FreeMono12pt7bBitmaps[] PROGMEM = {
- 0x49, 0x24, 0x92, 0x48, 0x01, 0xF8, 0xE7, 0xE7, 0x67, 0x42, 0x42, 0x42,
- 0x42, 0x09, 0x02, 0x41, 0x10, 0x44, 0x11, 0x1F, 0xF1, 0x10, 0x4C, 0x12,
- 0x3F, 0xE1, 0x20, 0x48, 0x12, 0x04, 0x81, 0x20, 0x48, 0x04, 0x07, 0xA2,
- 0x19, 0x02, 0x40, 0x10, 0x03, 0x00, 0x3C, 0x00, 0x80, 0x10, 0x06, 0x01,
- 0xE0, 0xA7, 0xC0, 0x40, 0x10, 0x04, 0x00, 0x3C, 0x19, 0x84, 0x21, 0x08,
- 0x66, 0x0F, 0x00, 0x0C, 0x1C, 0x78, 0x01, 0xE0, 0xCC, 0x21, 0x08, 0x43,
- 0x30, 0x78, 0x3E, 0x30, 0x10, 0x08, 0x02, 0x03, 0x03, 0x47, 0x14, 0x8A,
- 0x43, 0x11, 0x8F, 0x60, 0xFD, 0xA4, 0x90, 0x05, 0x25, 0x24, 0x92, 0x48,
- 0x92, 0x24, 0x11, 0x24, 0x89, 0x24, 0x92, 0x92, 0x90, 0x00, 0x04, 0x02,
- 0x11, 0x07, 0xF0, 0xC0, 0x50, 0x48, 0x42, 0x00, 0x08, 0x04, 0x02, 0x01,
- 0x00, 0x87, 0xFC, 0x20, 0x10, 0x08, 0x04, 0x02, 0x00, 0x3B, 0x9C, 0xCE,
- 0x62, 0x00, 0xFF, 0xE0, 0xFF, 0x80, 0x00, 0x80, 0xC0, 0x40, 0x20, 0x20,
- 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x01, 0x01, 0x00, 0x80,
- 0x80, 0x40, 0x00, 0x1C, 0x31, 0x90, 0x58, 0x38, 0x0C, 0x06, 0x03, 0x01,
- 0x80, 0xC0, 0x60, 0x30, 0x34, 0x13, 0x18, 0x70, 0x30, 0xE1, 0x44, 0x81,
- 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x81, 0x1F, 0xC0, 0x1E, 0x10, 0x90,
- 0x68, 0x10, 0x08, 0x0C, 0x04, 0x04, 0x04, 0x06, 0x06, 0x06, 0x06, 0x0E,
- 0x07, 0xFE, 0x3E, 0x10, 0x40, 0x08, 0x02, 0x00, 0x80, 0x40, 0xE0, 0x04,
- 0x00, 0x80, 0x10, 0x04, 0x01, 0x00, 0xD8, 0x63, 0xE0, 0x06, 0x0A, 0x0A,
- 0x12, 0x22, 0x22, 0x42, 0x42, 0x82, 0x82, 0xFF, 0x02, 0x02, 0x02, 0x0F,
- 0x7F, 0x20, 0x10, 0x08, 0x04, 0x02, 0xF1, 0x8C, 0x03, 0x00, 0x80, 0x40,
- 0x20, 0x18, 0x16, 0x18, 0xF0, 0x0F, 0x8C, 0x08, 0x08, 0x04, 0x04, 0x02,
- 0x79, 0x46, 0xC1, 0xE0, 0x60, 0x28, 0x14, 0x19, 0x08, 0x78, 0xFF, 0x81,
- 0x81, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08,
- 0x08, 0x3E, 0x31, 0xB0, 0x70, 0x18, 0x0C, 0x05, 0x8C, 0x38, 0x63, 0x40,
- 0x60, 0x30, 0x18, 0x1B, 0x18, 0xF8, 0x3C, 0x31, 0x30, 0x50, 0x28, 0x0C,
- 0x0F, 0x06, 0x85, 0x3C, 0x80, 0x40, 0x40, 0x20, 0x20, 0x63, 0xE0, 0xFF,
- 0x80, 0x07, 0xFC, 0x39, 0xCE, 0x00, 0x00, 0x06, 0x33, 0x98, 0xC4, 0x00,
- 0x00, 0xC0, 0x60, 0x18, 0x0C, 0x06, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03,
- 0x00, 0x30, 0x01, 0x00, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xFF, 0xC0, 0x06,
- 0x00, 0x30, 0x01, 0x80, 0x18, 0x01, 0x80, 0xC0, 0x30, 0x18, 0x0C, 0x02,
- 0x00, 0x00, 0x3E, 0x60, 0xA0, 0x20, 0x10, 0x08, 0x08, 0x18, 0x10, 0x08,
- 0x00, 0x00, 0x00, 0x01, 0xC0, 0xE0, 0x1C, 0x31, 0x10, 0x50, 0x28, 0x14,
- 0x3A, 0x25, 0x22, 0x91, 0x4C, 0xA3, 0xF0, 0x08, 0x02, 0x01, 0x80, 0x7C,
- 0x3F, 0x00, 0x0C, 0x00, 0x48, 0x01, 0x20, 0x04, 0x40, 0x21, 0x00, 0x84,
- 0x04, 0x08, 0x1F, 0xE0, 0x40, 0x82, 0x01, 0x08, 0x04, 0x20, 0x13, 0xE1,
- 0xF0, 0xFF, 0x08, 0x11, 0x01, 0x20, 0x24, 0x04, 0x81, 0x1F, 0xC2, 0x06,
- 0x40, 0x68, 0x05, 0x00, 0xA0, 0x14, 0x05, 0xFF, 0x00, 0x1E, 0x48, 0x74,
- 0x05, 0x01, 0x80, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x04, 0x01, 0x01,
- 0x30, 0x87, 0xC0, 0xFE, 0x10, 0x44, 0x09, 0x02, 0x40, 0x50, 0x14, 0x05,
- 0x01, 0x40, 0x50, 0x14, 0x0D, 0x02, 0x41, 0x3F, 0x80, 0xFF, 0xC8, 0x09,
- 0x01, 0x20, 0x04, 0x00, 0x88, 0x1F, 0x02, 0x20, 0x40, 0x08, 0x01, 0x00,
- 0xA0, 0x14, 0x03, 0xFF, 0xC0, 0xFF, 0xE8, 0x05, 0x00, 0xA0, 0x04, 0x00,
- 0x88, 0x1F, 0x02, 0x20, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x01, 0xF0,
- 0x00, 0x1F, 0x46, 0x19, 0x01, 0x60, 0x28, 0x01, 0x00, 0x20, 0x04, 0x00,
- 0x83, 0xF0, 0x0B, 0x01, 0x20, 0x23, 0x0C, 0x3E, 0x00, 0xE1, 0xD0, 0x24,
- 0x09, 0x02, 0x40, 0x90, 0x27, 0xF9, 0x02, 0x40, 0x90, 0x24, 0x09, 0x02,
- 0x40, 0xB8, 0x70, 0xFE, 0x20, 0x40, 0x81, 0x02, 0x04, 0x08, 0x10, 0x20,
- 0x40, 0x81, 0x1F, 0xC0, 0x0F, 0xE0, 0x10, 0x02, 0x00, 0x40, 0x08, 0x01,
- 0x00, 0x20, 0x04, 0x80, 0x90, 0x12, 0x02, 0x40, 0xC6, 0x30, 0x7C, 0x00,
- 0xF1, 0xE4, 0x0C, 0x41, 0x04, 0x20, 0x44, 0x04, 0x80, 0x5C, 0x06, 0x60,
- 0x43, 0x04, 0x10, 0x40, 0x84, 0x08, 0x40, 0xCF, 0x07, 0xF8, 0x04, 0x00,
- 0x80, 0x10, 0x02, 0x00, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x04, 0x80,
- 0x90, 0x12, 0x03, 0xFF, 0xC0, 0xE0, 0x3B, 0x01, 0x94, 0x14, 0xA0, 0xA4,
- 0x89, 0x24, 0x49, 0x14, 0x48, 0xA2, 0x45, 0x12, 0x10, 0x90, 0x04, 0x80,
- 0x24, 0x01, 0x78, 0x3C, 0xE0, 0xF6, 0x02, 0x50, 0x25, 0x02, 0x48, 0x24,
- 0xC2, 0x44, 0x24, 0x22, 0x43, 0x24, 0x12, 0x40, 0xA4, 0x0A, 0x40, 0x6F,
- 0x06, 0x0F, 0x03, 0x0C, 0x60, 0x64, 0x02, 0x80, 0x18, 0x01, 0x80, 0x18,
- 0x01, 0x80, 0x18, 0x01, 0x40, 0x26, 0x06, 0x30, 0xC0, 0xF0, 0xFF, 0x10,
- 0x64, 0x05, 0x01, 0x40, 0x50, 0x34, 0x19, 0xFC, 0x40, 0x10, 0x04, 0x01,
- 0x00, 0x40, 0x3E, 0x00, 0x0F, 0x03, 0x0C, 0x60, 0x64, 0x02, 0x80, 0x18,
- 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x01, 0x40, 0x26, 0x06, 0x30, 0xC1,
- 0xF0, 0x0C, 0x01, 0xF1, 0x30, 0xE0, 0xFF, 0x04, 0x18, 0x40, 0xC4, 0x04,
- 0x40, 0x44, 0x0C, 0x41, 0x87, 0xE0, 0x43, 0x04, 0x10, 0x40, 0x84, 0x04,
- 0x40, 0x4F, 0x03, 0x1F, 0x48, 0x34, 0x05, 0x01, 0x40, 0x08, 0x01, 0xC0,
- 0x0E, 0x00, 0x40, 0x18, 0x06, 0x01, 0xE1, 0xA7, 0xC0, 0xFF, 0xF0, 0x86,
- 0x10, 0x82, 0x00, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10,
- 0x02, 0x00, 0x40, 0x7F, 0x00, 0xF0, 0xF4, 0x02, 0x40, 0x24, 0x02, 0x40,
- 0x24, 0x02, 0x40, 0x24, 0x02, 0x40, 0x24, 0x02, 0x40, 0x22, 0x04, 0x30,
- 0xC0, 0xF0, 0xF8, 0x7C, 0x80, 0x22, 0x01, 0x04, 0x04, 0x10, 0x20, 0x40,
- 0x80, 0x82, 0x02, 0x10, 0x08, 0x40, 0x11, 0x00, 0x48, 0x01, 0xA0, 0x03,
- 0x00, 0x0C, 0x00, 0xF8, 0x7C, 0x80, 0x22, 0x00, 0x88, 0xC2, 0x23, 0x10,
- 0x8E, 0x42, 0x29, 0x09, 0x24, 0x24, 0x90, 0x91, 0x41, 0x85, 0x06, 0x14,
- 0x18, 0x70, 0x60, 0x80, 0xF0, 0xF2, 0x06, 0x30, 0x41, 0x08, 0x09, 0x80,
- 0x50, 0x06, 0x00, 0x60, 0x0D, 0x00, 0x88, 0x10, 0xC2, 0x04, 0x60, 0x2F,
- 0x0F, 0xF0, 0xF2, 0x02, 0x10, 0x41, 0x04, 0x08, 0x80, 0x50, 0x05, 0x00,
- 0x20, 0x02, 0x00, 0x20, 0x02, 0x00, 0x20, 0x02, 0x01, 0xFC, 0xFF, 0x40,
- 0xA0, 0x90, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x10, 0x50, 0x30, 0x18,
- 0x0F, 0xFC, 0xF2, 0x49, 0x24, 0x92, 0x49, 0x24, 0x9C, 0x80, 0x60, 0x10,
- 0x08, 0x02, 0x01, 0x00, 0x40, 0x20, 0x08, 0x04, 0x01, 0x00, 0x80, 0x20,
- 0x10, 0x04, 0x02, 0x00, 0x80, 0x40, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49,
- 0x3C, 0x08, 0x0C, 0x09, 0x0C, 0x4C, 0x14, 0x04, 0xFF, 0xFC, 0x84, 0x21,
- 0x3E, 0x00, 0x60, 0x08, 0x02, 0x3F, 0x98, 0x28, 0x0A, 0x02, 0xC3, 0x9F,
- 0x30, 0xE0, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00, 0x13, 0xE0, 0xA0,
- 0x86, 0x02, 0x20, 0x09, 0x00, 0x48, 0x02, 0x40, 0x13, 0x01, 0x14, 0x1B,
- 0x9F, 0x00, 0x1F, 0x4C, 0x19, 0x01, 0x40, 0x28, 0x01, 0x00, 0x20, 0x02,
- 0x00, 0x60, 0x43, 0xF0, 0x00, 0xC0, 0x08, 0x01, 0x00, 0x20, 0x04, 0x3C,
- 0x98, 0x52, 0x06, 0x80, 0x50, 0x0A, 0x01, 0x40, 0x24, 0x0C, 0xC2, 0x87,
- 0x98, 0x3F, 0x18, 0x68, 0x06, 0x01, 0xFF, 0xE0, 0x08, 0x03, 0x00, 0x60,
- 0xC7, 0xC0, 0x0F, 0x98, 0x08, 0x04, 0x02, 0x07, 0xF8, 0x80, 0x40, 0x20,
- 0x10, 0x08, 0x04, 0x02, 0x01, 0x03, 0xF8, 0x1E, 0x6C, 0x39, 0x03, 0x40,
- 0x28, 0x05, 0x00, 0xA0, 0x12, 0x06, 0x61, 0x43, 0xC8, 0x01, 0x00, 0x20,
- 0x08, 0x3E, 0x00, 0xC0, 0x10, 0x04, 0x01, 0x00, 0x40, 0x13, 0x87, 0x11,
- 0x82, 0x40, 0x90, 0x24, 0x09, 0x02, 0x40, 0x90, 0x2E, 0x1C, 0x08, 0x04,
- 0x02, 0x00, 0x00, 0x03, 0xC0, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00,
- 0x80, 0x43, 0xFE, 0x04, 0x08, 0x10, 0x00, 0x1F, 0xC0, 0x81, 0x02, 0x04,
- 0x08, 0x10, 0x20, 0x40, 0x81, 0x02, 0x0B, 0xE0, 0xE0, 0x02, 0x00, 0x20,
- 0x02, 0x00, 0x20, 0x02, 0x3C, 0x21, 0x02, 0x60, 0x2C, 0x03, 0x80, 0x24,
- 0x02, 0x20, 0x21, 0x02, 0x08, 0xE1, 0xF0, 0x78, 0x04, 0x02, 0x01, 0x00,
- 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x80, 0x43, 0xFE,
- 0xDC, 0xE3, 0x19, 0x90, 0x84, 0x84, 0x24, 0x21, 0x21, 0x09, 0x08, 0x48,
- 0x42, 0x42, 0x17, 0x18, 0xC0, 0x67, 0x83, 0x84, 0x20, 0x22, 0x02, 0x20,
- 0x22, 0x02, 0x20, 0x22, 0x02, 0x20, 0x2F, 0x07, 0x1F, 0x04, 0x11, 0x01,
- 0x40, 0x18, 0x03, 0x00, 0x60, 0x0A, 0x02, 0x20, 0x83, 0xE0, 0xCF, 0x85,
- 0x06, 0x60, 0x24, 0x01, 0x40, 0x14, 0x01, 0x40, 0x16, 0x02, 0x50, 0x44,
- 0xF8, 0x40, 0x04, 0x00, 0x40, 0x0F, 0x00, 0x1E, 0x6C, 0x3B, 0x03, 0x40,
- 0x28, 0x05, 0x00, 0xA0, 0x12, 0x06, 0x61, 0x43, 0xC8, 0x01, 0x00, 0x20,
- 0x04, 0x03, 0xC0, 0xE3, 0x8B, 0x13, 0x80, 0x80, 0x20, 0x08, 0x02, 0x00,
- 0x80, 0x20, 0x3F, 0x80, 0x1F, 0x58, 0x34, 0x05, 0x80, 0x1E, 0x00, 0x60,
- 0x06, 0x01, 0xC0, 0xAF, 0xC0, 0x20, 0x04, 0x00, 0x80, 0x10, 0x0F, 0xF0,
- 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10, 0x03, 0x04, 0x3F,
- 0x00, 0xC1, 0xC8, 0x09, 0x01, 0x20, 0x24, 0x04, 0x80, 0x90, 0x12, 0x02,
- 0x61, 0xC7, 0xCC, 0xF8, 0xF9, 0x01, 0x08, 0x10, 0x60, 0x81, 0x08, 0x08,
- 0x40, 0x22, 0x01, 0x20, 0x05, 0x00, 0x30, 0x00, 0xF0, 0x7A, 0x01, 0x10,
- 0x08, 0x8C, 0x42, 0x62, 0x12, 0x90, 0xA5, 0x05, 0x18, 0x28, 0xC0, 0x86,
- 0x00, 0x78, 0xF3, 0x04, 0x18, 0x80, 0xD0, 0x06, 0x00, 0x70, 0x09, 0x81,
- 0x0C, 0x20, 0x6F, 0x8F, 0xF0, 0xF2, 0x02, 0x20, 0x41, 0x04, 0x10, 0x80,
- 0x88, 0x09, 0x00, 0x50, 0x06, 0x00, 0x20, 0x04, 0x00, 0x40, 0x08, 0x0F,
- 0xE0, 0xFF, 0x41, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0xBF,
- 0xC0, 0x19, 0x08, 0x42, 0x10, 0x84, 0x64, 0x18, 0x42, 0x10, 0x84, 0x20,
- 0xC0, 0xFF, 0xFF, 0xC0, 0xC1, 0x08, 0x42, 0x10, 0x84, 0x10, 0x4C, 0x42,
- 0x10, 0x84, 0x26, 0x00, 0x38, 0x13, 0x38, 0x38 };
-
-const GFXglyph FreeMono12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 14, 0, 1 }, // 0x20 ' '
- { 0, 3, 15, 14, 6, -14 }, // 0x21 '!'
- { 6, 8, 7, 14, 3, -14 }, // 0x22 '"'
- { 13, 10, 16, 14, 2, -14 }, // 0x23 '#'
- { 33, 10, 17, 14, 2, -14 }, // 0x24 '$'
- { 55, 10, 15, 14, 2, -14 }, // 0x25 '%'
- { 74, 9, 12, 14, 3, -11 }, // 0x26 '&'
- { 88, 3, 7, 14, 5, -14 }, // 0x27 '''
- { 91, 3, 18, 14, 7, -14 }, // 0x28 '('
- { 98, 3, 18, 14, 4, -14 }, // 0x29 ')'
- { 105, 9, 9, 14, 3, -14 }, // 0x2A '*'
- { 116, 9, 11, 14, 3, -11 }, // 0x2B '+'
- { 129, 5, 7, 14, 3, -3 }, // 0x2C ','
- { 134, 11, 1, 14, 2, -6 }, // 0x2D '-'
- { 136, 3, 3, 14, 5, -2 }, // 0x2E '.'
- { 138, 9, 18, 14, 3, -15 }, // 0x2F '/'
- { 159, 9, 15, 14, 3, -14 }, // 0x30 '0'
- { 176, 7, 14, 14, 4, -13 }, // 0x31 '1'
- { 189, 9, 15, 14, 2, -14 }, // 0x32 '2'
- { 206, 10, 15, 14, 2, -14 }, // 0x33 '3'
- { 225, 8, 15, 14, 3, -14 }, // 0x34 '4'
- { 240, 9, 15, 14, 3, -14 }, // 0x35 '5'
- { 257, 9, 15, 14, 3, -14 }, // 0x36 '6'
- { 274, 8, 15, 14, 3, -14 }, // 0x37 '7'
- { 289, 9, 15, 14, 3, -14 }, // 0x38 '8'
- { 306, 9, 15, 14, 3, -14 }, // 0x39 '9'
- { 323, 3, 10, 14, 5, -9 }, // 0x3A ':'
- { 327, 5, 13, 14, 3, -9 }, // 0x3B ';'
- { 336, 11, 11, 14, 2, -11 }, // 0x3C '<'
- { 352, 12, 4, 14, 1, -8 }, // 0x3D '='
- { 358, 11, 11, 14, 2, -11 }, // 0x3E '>'
- { 374, 9, 14, 14, 3, -13 }, // 0x3F '?'
- { 390, 9, 16, 14, 3, -14 }, // 0x40 '@'
- { 408, 14, 14, 14, 0, -13 }, // 0x41 'A'
- { 433, 11, 14, 14, 2, -13 }, // 0x42 'B'
- { 453, 10, 14, 14, 2, -13 }, // 0x43 'C'
- { 471, 10, 14, 14, 2, -13 }, // 0x44 'D'
- { 489, 11, 14, 14, 2, -13 }, // 0x45 'E'
- { 509, 11, 14, 14, 2, -13 }, // 0x46 'F'
- { 529, 11, 14, 14, 2, -13 }, // 0x47 'G'
- { 549, 10, 14, 14, 2, -13 }, // 0x48 'H'
- { 567, 7, 14, 14, 4, -13 }, // 0x49 'I'
- { 580, 11, 14, 14, 2, -13 }, // 0x4A 'J'
- { 600, 12, 14, 14, 2, -13 }, // 0x4B 'K'
- { 621, 11, 14, 14, 2, -13 }, // 0x4C 'L'
- { 641, 13, 14, 14, 1, -13 }, // 0x4D 'M'
- { 664, 12, 14, 14, 1, -13 }, // 0x4E 'N'
- { 685, 12, 14, 14, 1, -13 }, // 0x4F 'O'
- { 706, 10, 14, 14, 2, -13 }, // 0x50 'P'
- { 724, 12, 17, 14, 1, -13 }, // 0x51 'Q'
- { 750, 12, 14, 14, 2, -13 }, // 0x52 'R'
- { 771, 10, 14, 14, 2, -13 }, // 0x53 'S'
- { 789, 11, 14, 14, 2, -13 }, // 0x54 'T'
- { 809, 12, 14, 14, 1, -13 }, // 0x55 'U'
- { 830, 14, 14, 14, 0, -13 }, // 0x56 'V'
- { 855, 14, 14, 14, 0, -13 }, // 0x57 'W'
- { 880, 12, 14, 14, 1, -13 }, // 0x58 'X'
- { 901, 12, 14, 14, 1, -13 }, // 0x59 'Y'
- { 922, 9, 14, 14, 3, -13 }, // 0x5A 'Z'
- { 938, 3, 18, 14, 7, -14 }, // 0x5B '['
- { 945, 9, 18, 14, 3, -15 }, // 0x5C '\'
- { 966, 3, 18, 14, 5, -14 }, // 0x5D ']'
- { 973, 9, 6, 14, 3, -14 }, // 0x5E '^'
- { 980, 14, 1, 14, 0, 3 }, // 0x5F '_'
- { 982, 4, 4, 14, 4, -15 }, // 0x60 '`'
- { 984, 10, 10, 14, 2, -9 }, // 0x61 'a'
- { 997, 13, 15, 14, 0, -14 }, // 0x62 'b'
- { 1022, 11, 10, 14, 2, -9 }, // 0x63 'c'
- { 1036, 11, 15, 14, 2, -14 }, // 0x64 'd'
- { 1057, 10, 10, 14, 2, -9 }, // 0x65 'e'
- { 1070, 9, 15, 14, 4, -14 }, // 0x66 'f'
- { 1087, 11, 14, 14, 2, -9 }, // 0x67 'g'
- { 1107, 10, 15, 14, 2, -14 }, // 0x68 'h'
- { 1126, 9, 15, 14, 3, -14 }, // 0x69 'i'
- { 1143, 7, 19, 14, 3, -14 }, // 0x6A 'j'
- { 1160, 12, 15, 14, 1, -14 }, // 0x6B 'k'
- { 1183, 9, 15, 14, 3, -14 }, // 0x6C 'l'
- { 1200, 13, 10, 14, 1, -9 }, // 0x6D 'm'
- { 1217, 12, 10, 14, 1, -9 }, // 0x6E 'n'
- { 1232, 11, 10, 14, 2, -9 }, // 0x6F 'o'
- { 1246, 12, 14, 14, 1, -9 }, // 0x70 'p'
- { 1267, 11, 14, 14, 2, -9 }, // 0x71 'q'
- { 1287, 10, 10, 14, 3, -9 }, // 0x72 'r'
- { 1300, 10, 10, 14, 2, -9 }, // 0x73 's'
- { 1313, 11, 14, 14, 1, -13 }, // 0x74 't'
- { 1333, 11, 10, 14, 2, -9 }, // 0x75 'u'
- { 1347, 13, 10, 14, 1, -9 }, // 0x76 'v'
- { 1364, 13, 10, 14, 1, -9 }, // 0x77 'w'
- { 1381, 12, 10, 14, 1, -9 }, // 0x78 'x'
- { 1396, 12, 14, 14, 1, -9 }, // 0x79 'y'
- { 1417, 9, 10, 14, 3, -9 }, // 0x7A 'z'
- { 1429, 5, 18, 14, 5, -14 }, // 0x7B '{'
- { 1441, 1, 18, 14, 7, -14 }, // 0x7C '|'
- { 1444, 5, 18, 14, 5, -14 }, // 0x7D '}'
- { 1456, 10, 3, 14, 2, -7 } }; // 0x7E '~'
-
-const GFXfont FreeMono12pt7b PROGMEM = {
- (uint8_t *)FreeMono12pt7bBitmaps,
- (GFXglyph *)FreeMono12pt7bGlyphs,
- 0x20, 0x7E, 24 };
-
-// Approx. 2132 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono18pt7b.h
deleted file mode 100644
index c605d29..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono18pt7b.h
+++ /dev/null
@@ -1,363 +0,0 @@
-const uint8_t FreeMono18pt7bBitmaps[] PROGMEM = {
- 0x27, 0x77, 0x77, 0x77, 0x77, 0x22, 0x22, 0x20, 0x00, 0x6F, 0xF6, 0xF1,
- 0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1E, 0xC3, 0x98, 0x33, 0x06, 0x60, 0xCC,
- 0x18, 0x04, 0x20, 0x10, 0x80, 0x42, 0x01, 0x08, 0x04, 0x20, 0x10, 0x80,
- 0x42, 0x01, 0x10, 0x04, 0x41, 0xFF, 0xF0, 0x44, 0x02, 0x10, 0x08, 0x40,
- 0x21, 0x0F, 0xFF, 0xC2, 0x10, 0x08, 0x40, 0x21, 0x00, 0x84, 0x02, 0x10,
- 0x08, 0x40, 0x23, 0x00, 0x88, 0x02, 0x20, 0x02, 0x00, 0x10, 0x00, 0x80,
- 0x1F, 0xA3, 0x07, 0x10, 0x09, 0x00, 0x48, 0x00, 0x40, 0x03, 0x00, 0x0C,
- 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x18, 0x00, 0x20, 0x01, 0x80, 0x0C, 0x00,
- 0x70, 0x05, 0xE0, 0xC9, 0xF8, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00,
- 0x10, 0x00, 0x1E, 0x00, 0x42, 0x01, 0x02, 0x02, 0x04, 0x04, 0x08, 0x08,
- 0x10, 0x08, 0x40, 0x0F, 0x00, 0x00, 0x1E, 0x01, 0xF0, 0x1F, 0x01, 0xE0,
- 0x0E, 0x00, 0x00, 0x3C, 0x00, 0x86, 0x02, 0x06, 0x04, 0x04, 0x08, 0x08,
- 0x10, 0x30, 0x10, 0xC0, 0x1E, 0x00, 0x0F, 0xC1, 0x00, 0x20, 0x02, 0x00,
- 0x20, 0x02, 0x00, 0x10, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x6C, 0x3C, 0x62,
- 0x82, 0x68, 0x34, 0x81, 0xCC, 0x08, 0x61, 0xC3, 0xE7, 0xFF, 0xFF, 0xF6,
- 0x66, 0x66, 0x08, 0xC4, 0x62, 0x31, 0x8C, 0xC6, 0x31, 0x8C, 0x63, 0x18,
- 0xC3, 0x18, 0xC2, 0x18, 0xC3, 0x18, 0x86, 0x10, 0xC2, 0x18, 0xC6, 0x10,
- 0xC6, 0x31, 0x8C, 0x63, 0x18, 0x8C, 0x62, 0x31, 0x98, 0x80, 0x02, 0x00,
- 0x10, 0x00, 0x80, 0x04, 0x0C, 0x21, 0x9D, 0x70, 0x1C, 0x00, 0xA0, 0x0D,
- 0x80, 0xC6, 0x04, 0x10, 0x40, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00,
- 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0xFF, 0xFE, 0x02,
- 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80,
- 0x01, 0x00, 0x3E, 0x78, 0xF3, 0xC7, 0x8E, 0x18, 0x70, 0xC1, 0x80, 0xFF,
- 0xFE, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x08, 0x00, 0xC0, 0x04, 0x00, 0x60,
- 0x02, 0x00, 0x30, 0x01, 0x00, 0x18, 0x00, 0x80, 0x0C, 0x00, 0x40, 0x02,
- 0x00, 0x20, 0x01, 0x00, 0x10, 0x00, 0x80, 0x08, 0x00, 0x40, 0x04, 0x00,
- 0x20, 0x02, 0x00, 0x10, 0x01, 0x00, 0x08, 0x00, 0x80, 0x04, 0x00, 0x00,
- 0x0F, 0x81, 0x82, 0x08, 0x08, 0x80, 0x24, 0x01, 0x60, 0x0E, 0x00, 0x30,
- 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x06, 0x00,
- 0x30, 0x03, 0x40, 0x12, 0x00, 0x88, 0x08, 0x60, 0xC0, 0xF8, 0x00, 0x06,
- 0x00, 0x70, 0x06, 0x80, 0x64, 0x06, 0x20, 0x31, 0x00, 0x08, 0x00, 0x40,
- 0x02, 0x00, 0x10, 0x00, 0x80, 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x00,
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- 0x40, 0x00, 0x60, 0x00, 0x30, 0x03, 0x0C, 0x0E, 0x03, 0xF0, 0x03, 0xFC,
- 0x18, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x0F, 0xFF, 0x82, 0x00,
- 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80,
- 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0xFF, 0xF0, 0x0F,
- 0xC7, 0x9C, 0x3A, 0x18, 0x07, 0x08, 0x01, 0x8C, 0x00, 0xC4, 0x00, 0x22,
- 0x00, 0x11, 0x00, 0x08, 0x80, 0x04, 0x40, 0x02, 0x10, 0x03, 0x08, 0x01,
- 0x82, 0x01, 0x40, 0xC3, 0x20, 0x3F, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00,
- 0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x7F, 0x00, 0xF0, 0x00,
- 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x47,
- 0xC0, 0x2C, 0x18, 0x1C, 0x04, 0x0C, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41,
- 0x00, 0x20, 0x80, 0x10, 0x40, 0x08, 0x20, 0x04, 0x10, 0x02, 0x08, 0x01,
- 0x04, 0x00, 0x82, 0x00, 0x47, 0xC0, 0xF8, 0x06, 0x00, 0x18, 0x00, 0x60,
- 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x02, 0x00, 0x08,
- 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02,
- 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x03, 0xFF, 0xF0, 0x03, 0x00,
- 0xC0, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x03, 0xFF, 0x00, 0x40, 0x10, 0x04,
- 0x01, 0x00, 0x40, 0x10, 0x04, 0x01, 0x00, 0x40, 0x10, 0x04, 0x01, 0x00,
- 0x40, 0x10, 0x04, 0x01, 0x00, 0x40, 0x10, 0x08, 0x06, 0xFE, 0x00, 0xF0,
- 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10,
- 0xFE, 0x10, 0x30, 0x10, 0xE0, 0x11, 0xC0, 0x13, 0x00, 0x16, 0x00, 0x1E,
- 0x00, 0x1B, 0x00, 0x11, 0x80, 0x10, 0xC0, 0x10, 0x60, 0x10, 0x30, 0x10,
- 0x18, 0x10, 0x1C, 0xF0, 0x3F, 0x7E, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80,
- 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20,
- 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x08,
- 0x00, 0x20, 0x00, 0x80, 0xFF, 0xFC, 0xEF, 0x9E, 0x07, 0x1E, 0x20, 0xC1,
- 0x82, 0x10, 0x20, 0x42, 0x04, 0x08, 0x40, 0x81, 0x08, 0x10, 0x21, 0x02,
- 0x04, 0x20, 0x40, 0x84, 0x08, 0x10, 0x81, 0x02, 0x10, 0x20, 0x42, 0x04,
- 0x08, 0x40, 0x81, 0x3E, 0x1C, 0x38, 0x71, 0xF0, 0x0B, 0x06, 0x07, 0x01,
- 0x03, 0x00, 0x41, 0x00, 0x20, 0x80, 0x10, 0x40, 0x08, 0x20, 0x04, 0x10,
- 0x02, 0x08, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00, 0x20, 0x80, 0x13,
- 0xF0, 0x3E, 0x07, 0xC0, 0x30, 0x60, 0x80, 0x22, 0x00, 0x24, 0x00, 0x50,
- 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x05, 0x00, 0x12, 0x00,
- 0x22, 0x00, 0x83, 0x06, 0x01, 0xF0, 0x00, 0xF1, 0xFC, 0x05, 0xC1, 0x81,
- 0xC0, 0x10, 0x60, 0x02, 0x18, 0x00, 0xC4, 0x00, 0x11, 0x00, 0x04, 0x40,
- 0x01, 0x10, 0x00, 0x44, 0x00, 0x11, 0x80, 0x08, 0x60, 0x02, 0x14, 0x01,
- 0x04, 0xC1, 0x81, 0x0F, 0x80, 0x40, 0x00, 0x10, 0x00, 0x04, 0x00, 0x01,
- 0x00, 0x00, 0x40, 0x00, 0x10, 0x00, 0x3F, 0xC0, 0x00, 0x0F, 0xE3, 0xC6,
- 0x0E, 0x86, 0x00, 0xE1, 0x00, 0x18, 0xC0, 0x06, 0x20, 0x00, 0x88, 0x00,
- 0x22, 0x00, 0x08, 0x80, 0x02, 0x20, 0x00, 0x84, 0x00, 0x61, 0x00, 0x18,
- 0x20, 0x0A, 0x06, 0x0C, 0x80, 0x7C, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00,
- 0x00, 0x80, 0x00, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00, 0x0F, 0xF0, 0xF8,
- 0x7C, 0x11, 0x8C, 0x2C, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x00, 0x02, 0x00,
- 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x01,
- 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xD1, 0x83, 0x98, 0x04, 0x80, 0x24, 0x00,
- 0x30, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0x30, 0x00, 0xE0, 0x03, 0x00, 0x1C,
- 0x01, 0xF0, 0x1A, 0x7F, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,
- 0x00, 0x08, 0x00, 0xFF, 0xFC, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,
- 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,
- 0x00, 0x08, 0x00, 0x08, 0x01, 0x06, 0x0F, 0x03, 0xF8, 0xF0, 0x3E, 0x08,
- 0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00, 0x20, 0x80, 0x10, 0x40, 0x08,
- 0x20, 0x04, 0x10, 0x02, 0x08, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00,
- 0xE0, 0x41, 0xD0, 0x1F, 0x8E, 0xFE, 0x0F, 0xE2, 0x00, 0x20, 0x60, 0x0C,
- 0x0C, 0x01, 0x80, 0x80, 0x20, 0x18, 0x0C, 0x01, 0x01, 0x00, 0x30, 0x60,
- 0x02, 0x08, 0x00, 0x41, 0x00, 0x0C, 0x60, 0x00, 0x88, 0x00, 0x19, 0x00,
- 0x01, 0x40, 0x00, 0x38, 0x00, 0xFC, 0x07, 0xE4, 0x00, 0x10, 0x80, 0x02,
- 0x18, 0x20, 0xC3, 0x0E, 0x18, 0x21, 0x42, 0x04, 0x28, 0x40, 0x8D, 0x88,
- 0x19, 0x93, 0x03, 0x22, 0x60, 0x2C, 0x68, 0x05, 0x85, 0x00, 0xA0, 0xA0,
- 0x1C, 0x1C, 0x01, 0x81, 0x80, 0x7C, 0x1F, 0x18, 0x03, 0x06, 0x03, 0x01,
- 0x83, 0x00, 0x63, 0x00, 0x1B, 0x00, 0x07, 0x00, 0x03, 0x80, 0x03, 0x60,
- 0x03, 0x18, 0x03, 0x06, 0x03, 0x01, 0x83, 0x00, 0x61, 0x00, 0x33, 0xF0,
- 0x7E, 0xFC, 0x1F, 0x90, 0x01, 0x8C, 0x00, 0x86, 0x00, 0xC1, 0x80, 0x40,
- 0xC0, 0x60, 0x20, 0x20, 0x18, 0x30, 0x04, 0x10, 0x03, 0x08, 0x00, 0x8C,
- 0x00, 0x64, 0x00, 0x16, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x01, 0x00, 0x01,
- 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x20, 0x07, 0xFE, 0x00,
- 0xFF, 0xF4, 0x01, 0x20, 0x09, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00,
- 0xC0, 0x04, 0x00, 0x40, 0x04, 0x00, 0x40, 0x14, 0x00, 0xA0, 0x07, 0xFF,
- 0xE0, 0x07, 0x0C, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x30, 0xC0, 0x30, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x0C, 0x07, 0xFF, 0xFF, 0xFF, 0x80, 0xE0, 0x30, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x07, 0x0C, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x30, 0xE0, 0x1C, 0x00, 0x44, 0x0D, 0x84,
- 0x36, 0x04, 0x40, 0x07, 0x00 };
-
-const GFXglyph FreeMono18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 21, 0, 1 }, // 0x20 ' '
- { 0, 4, 22, 21, 8, -21 }, // 0x21 '!'
- { 11, 11, 10, 21, 5, -20 }, // 0x22 '"'
- { 25, 14, 24, 21, 3, -21 }, // 0x23 '#'
- { 67, 13, 26, 21, 4, -22 }, // 0x24 '$'
- { 110, 15, 21, 21, 3, -20 }, // 0x25 '%'
- { 150, 12, 18, 21, 4, -17 }, // 0x26 '&'
- { 177, 4, 10, 21, 8, -20 }, // 0x27 '''
- { 182, 5, 25, 21, 10, -20 }, // 0x28 '('
- { 198, 5, 25, 21, 6, -20 }, // 0x29 ')'
- { 214, 13, 12, 21, 4, -20 }, // 0x2A '*'
- { 234, 15, 17, 21, 3, -17 }, // 0x2B '+'
- { 266, 7, 10, 21, 5, -4 }, // 0x2C ','
- { 275, 15, 1, 21, 3, -9 }, // 0x2D '-'
- { 277, 5, 5, 21, 8, -4 }, // 0x2E '.'
- { 281, 13, 26, 21, 4, -22 }, // 0x2F '/'
- { 324, 13, 21, 21, 4, -20 }, // 0x30 '0'
- { 359, 13, 21, 21, 4, -20 }, // 0x31 '1'
- { 394, 13, 21, 21, 3, -20 }, // 0x32 '2'
- { 429, 14, 21, 21, 3, -20 }, // 0x33 '3'
- { 466, 12, 21, 21, 4, -20 }, // 0x34 '4'
- { 498, 14, 21, 21, 3, -20 }, // 0x35 '5'
- { 535, 12, 21, 21, 5, -20 }, // 0x36 '6'
- { 567, 12, 21, 21, 4, -20 }, // 0x37 '7'
- { 599, 13, 21, 21, 4, -20 }, // 0x38 '8'
- { 634, 12, 21, 21, 5, -20 }, // 0x39 '9'
- { 666, 5, 15, 21, 8, -14 }, // 0x3A ':'
- { 676, 7, 20, 21, 5, -14 }, // 0x3B ';'
- { 694, 15, 16, 21, 3, -17 }, // 0x3C '<'
- { 724, 17, 6, 21, 2, -12 }, // 0x3D '='
- { 737, 15, 16, 21, 3, -17 }, // 0x3E '>'
- { 767, 12, 20, 21, 5, -19 }, // 0x3F '?'
- { 797, 13, 23, 21, 4, -20 }, // 0x40 '@'
- { 835, 21, 20, 21, 0, -19 }, // 0x41 'A'
- { 888, 18, 20, 21, 1, -19 }, // 0x42 'B'
- { 933, 17, 20, 21, 2, -19 }, // 0x43 'C'
- { 976, 16, 20, 21, 2, -19 }, // 0x44 'D'
- { 1016, 17, 20, 21, 1, -19 }, // 0x45 'E'
- { 1059, 17, 20, 21, 1, -19 }, // 0x46 'F'
- { 1102, 17, 20, 21, 2, -19 }, // 0x47 'G'
- { 1145, 16, 20, 21, 2, -19 }, // 0x48 'H'
- { 1185, 13, 20, 21, 4, -19 }, // 0x49 'I'
- { 1218, 17, 20, 21, 3, -19 }, // 0x4A 'J'
- { 1261, 18, 20, 21, 1, -19 }, // 0x4B 'K'
- { 1306, 15, 20, 21, 3, -19 }, // 0x4C 'L'
- { 1344, 19, 20, 21, 1, -19 }, // 0x4D 'M'
- { 1392, 18, 20, 21, 1, -19 }, // 0x4E 'N'
- { 1437, 17, 20, 21, 2, -19 }, // 0x4F 'O'
- { 1480, 16, 20, 21, 1, -19 }, // 0x50 'P'
- { 1520, 17, 24, 21, 2, -19 }, // 0x51 'Q'
- { 1571, 19, 20, 21, 1, -19 }, // 0x52 'R'
- { 1619, 14, 20, 21, 3, -19 }, // 0x53 'S'
- { 1654, 15, 20, 21, 3, -19 }, // 0x54 'T'
- { 1692, 17, 20, 21, 2, -19 }, // 0x55 'U'
- { 1735, 21, 20, 21, 0, -19 }, // 0x56 'V'
- { 1788, 19, 20, 21, 1, -19 }, // 0x57 'W'
- { 1836, 19, 20, 21, 1, -19 }, // 0x58 'X'
- { 1884, 17, 20, 21, 2, -19 }, // 0x59 'Y'
- { 1927, 13, 20, 21, 4, -19 }, // 0x5A 'Z'
- { 1960, 5, 25, 21, 10, -20 }, // 0x5B '['
- { 1976, 13, 26, 21, 4, -22 }, // 0x5C '\'
- { 2019, 5, 25, 21, 6, -20 }, // 0x5D ']'
- { 2035, 13, 9, 21, 4, -20 }, // 0x5E '^'
- { 2050, 21, 1, 21, 0, 4 }, // 0x5F '_'
- { 2053, 6, 5, 21, 5, -21 }, // 0x60 '`'
- { 2057, 16, 15, 21, 3, -14 }, // 0x61 'a'
- { 2087, 18, 21, 21, 1, -20 }, // 0x62 'b'
- { 2135, 15, 15, 21, 3, -14 }, // 0x63 'c'
- { 2164, 18, 21, 21, 2, -20 }, // 0x64 'd'
- { 2212, 16, 15, 21, 2, -14 }, // 0x65 'e'
- { 2242, 14, 21, 21, 4, -20 }, // 0x66 'f'
- { 2279, 17, 22, 21, 2, -14 }, // 0x67 'g'
- { 2326, 17, 21, 21, 1, -20 }, // 0x68 'h'
- { 2371, 14, 22, 21, 4, -21 }, // 0x69 'i'
- { 2410, 10, 29, 21, 5, -21 }, // 0x6A 'j'
- { 2447, 16, 21, 21, 2, -20 }, // 0x6B 'k'
- { 2489, 14, 21, 21, 4, -20 }, // 0x6C 'l'
- { 2526, 19, 15, 21, 1, -14 }, // 0x6D 'm'
- { 2562, 17, 15, 21, 1, -14 }, // 0x6E 'n'
- { 2594, 15, 15, 21, 3, -14 }, // 0x6F 'o'
- { 2623, 18, 22, 21, 1, -14 }, // 0x70 'p'
- { 2673, 18, 22, 21, 2, -14 }, // 0x71 'q'
- { 2723, 15, 15, 21, 3, -14 }, // 0x72 'r'
- { 2752, 13, 15, 21, 4, -14 }, // 0x73 's'
- { 2777, 16, 20, 21, 1, -19 }, // 0x74 't'
- { 2817, 17, 15, 21, 1, -14 }, // 0x75 'u'
- { 2849, 19, 15, 21, 1, -14 }, // 0x76 'v'
- { 2885, 19, 15, 21, 1, -14 }, // 0x77 'w'
- { 2921, 17, 15, 21, 2, -14 }, // 0x78 'x'
- { 2953, 17, 22, 21, 2, -14 }, // 0x79 'y'
- { 3000, 13, 15, 21, 4, -14 }, // 0x7A 'z'
- { 3025, 8, 25, 21, 6, -20 }, // 0x7B '{'
- { 3050, 1, 25, 21, 10, -20 }, // 0x7C '|'
- { 3054, 8, 25, 21, 7, -20 }, // 0x7D '}'
- { 3079, 15, 5, 21, 3, -11 } }; // 0x7E '~'
-
-const GFXfont FreeMono18pt7b PROGMEM = {
- (uint8_t *)FreeMono18pt7bBitmaps,
- (GFXglyph *)FreeMono18pt7bGlyphs,
- 0x20, 0x7E, 35 };
-
-// Approx. 3761 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono24pt7b.h
deleted file mode 100644
index 4c8bd15..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono24pt7b.h
+++ /dev/null
@@ -1,577 +0,0 @@
-const uint8_t FreeMono24pt7bBitmaps[] PROGMEM = {
- 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x10, 0x84, 0x21, 0x08,
- 0x00, 0x00, 0x00, 0x03, 0xBF, 0xFF, 0xB8, 0xFE, 0x7F, 0x7C, 0x3E, 0x7C,
- 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x3C,
- 0x3E, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x01,
- 0x86, 0x00, 0x30, 0xC0, 0x06, 0x18, 0x00, 0xC3, 0x00, 0x18, 0x60, 0x03,
- 0x0C, 0x00, 0x61, 0x80, 0x0C, 0x70, 0x01, 0x8C, 0x00, 0x61, 0x80, 0x0C,
- 0x30, 0x3F, 0xFF, 0xF7, 0xFF, 0xFE, 0x06, 0x18, 0x00, 0xC3, 0x00, 0x18,
- 0x60, 0x03, 0x0C, 0x00, 0x61, 0x80, 0x0C, 0x30, 0x7F, 0xFF, 0xEF, 0xFF,
- 0xFC, 0x06, 0x18, 0x00, 0xC7, 0x00, 0x38, 0xC0, 0x06, 0x18, 0x00, 0xC3,
- 0x00, 0x18, 0x60, 0x03, 0x0C, 0x00, 0x61, 0x80, 0x0C, 0x30, 0x01, 0x86,
- 0x00, 0x30, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0F, 0xC0,
- 0x0F, 0xFD, 0x87, 0x03, 0xE3, 0x80, 0x39, 0xC0, 0x06, 0x60, 0x01, 0x98,
- 0x00, 0x06, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07, 0xC0, 0x00, 0x7F,
- 0x80, 0x03, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0x60, 0x00, 0x1C, 0x00, 0x03,
- 0x80, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x1F, 0x80, 0x0E, 0xFC, 0x0F, 0x37,
- 0xFF, 0x80, 0x7F, 0x80, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C,
- 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x07, 0x80, 0x01, 0xFE, 0x00, 0x38,
- 0x70, 0x03, 0x03, 0x00, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x18, 0x06,
- 0x01, 0x80, 0x30, 0x30, 0x03, 0x87, 0x00, 0x1F, 0xE0, 0x30, 0x78, 0x1F,
- 0x00, 0x1F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x00, 0xF8, 0x00,
- 0x0C, 0x01, 0xE0, 0x00, 0x7F, 0x80, 0x0E, 0x1C, 0x00, 0xC0, 0xC0, 0x18,
- 0x06, 0x01, 0x80, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x0C, 0x0E, 0x00,
- 0xE1, 0xC0, 0x07, 0xF8, 0x00, 0x1E, 0x00, 0x03, 0xEC, 0x01, 0xFF, 0x00,
- 0xE1, 0x00, 0x70, 0x00, 0x18, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0x30,
- 0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x7C, 0x00, 0x3B, 0x83,
- 0xD8, 0x60, 0xFE, 0x0C, 0x33, 0x03, 0x98, 0xC0, 0x66, 0x30, 0x0D, 0x8C,
- 0x03, 0xC3, 0x00, 0x70, 0x60, 0x1C, 0x1C, 0x0F, 0x03, 0x87, 0x7C, 0x7F,
- 0x9F, 0x07, 0x80, 0x00, 0xFE, 0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x3E, 0x3C,
- 0x70, 0xE1, 0xC3, 0x87, 0x00, 0x06, 0x1C, 0x30, 0xE1, 0x87, 0x0E, 0x18,
- 0x70, 0xE1, 0xC3, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC3, 0x87, 0x0E, 0x0C,
- 0x1C, 0x38, 0x70, 0x60, 0xE1, 0xC1, 0x83, 0x83, 0x06, 0x06, 0x04, 0xC1,
- 0xC1, 0x83, 0x83, 0x07, 0x0E, 0x0C, 0x1C, 0x38, 0x70, 0xE0, 0xE1, 0xC3,
- 0x87, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0x87, 0x0E, 0x1C, 0x30, 0x61, 0xC3,
- 0x0E, 0x18, 0x70, 0xC1, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00,
- 0x03, 0x00, 0x00, 0xC0, 0x10, 0x30, 0x3F, 0x8C, 0x7C, 0xFF, 0xFC, 0x07,
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- 0x60, 0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00,
- 0xC0, 0x03, 0xFF, 0xFC, 0x7F, 0xFF, 0x80, 0x01, 0xF8, 0x00, 0x0F, 0xFC,
- 0x7C, 0x38, 0x1C, 0xF8, 0xE0, 0x0D, 0x83, 0x00, 0x0F, 0x0E, 0x00, 0x1E,
- 0x18, 0x00, 0x1C, 0x70, 0x00, 0x38, 0xC0, 0x00, 0x31, 0x80, 0x00, 0x63,
- 0x00, 0x00, 0xC6, 0x00, 0x01, 0x8C, 0x00, 0x03, 0x18, 0x00, 0x06, 0x18,
- 0x00, 0x1C, 0x30, 0x00, 0x38, 0x30, 0x00, 0xF0, 0x70, 0x03, 0x60, 0x78,
- 0x1C, 0xC0, 0x3F, 0xF1, 0x80, 0x1F, 0x83, 0x00, 0x00, 0x06, 0x00, 0x00,
- 0x0C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03,
- 0x80, 0x00, 0x0E, 0x00, 0x3F, 0xF8, 0x00, 0x7F, 0xC0, 0x00, 0xF8, 0x00,
- 0x01, 0xF0, 0x00, 0x00, 0x60, 0x00, 0x00, 0xC0, 0x00, 0x01, 0x80, 0x00,
- 0x03, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x3F, 0x00, 0x18, 0xFF, 0x80,
- 0x37, 0x03, 0x80, 0x7C, 0x03, 0x80, 0xF0, 0x03, 0x81, 0xC0, 0x03, 0x03,
- 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30,
- 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03, 0x03, 0x00,
- 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30, 0x00,
- 0x63, 0xFC, 0x07, 0xFF, 0xF8, 0x0F, 0xF0, 0x01, 0xC0, 0x00, 0x70, 0x00,
- 0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x03, 0xFC, 0x00, 0x03, 0x00, 0x00, 0xC0,
- 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00,
- 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03,
- 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xC0, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xC0, 0x03, 0x00, 0x0C,
- 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03,
- 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00,
- 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00,
- 0x70, 0x03, 0x80, 0x1C, 0xFF, 0xE3, 0xFF, 0x00, 0xF8, 0x00, 0x03, 0xE0,
- 0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00,
- 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x1F, 0xE0, 0x60, 0x7F, 0x81,
- 0x80, 0x60, 0x06, 0x07, 0x00, 0x18, 0x38, 0x00, 0x61, 0xC0, 0x01, 0x8E,
- 0x00, 0x06, 0x70, 0x00, 0x1B, 0x80, 0x00, 0x7F, 0x00, 0x01, 0xCE, 0x00,
- 0x06, 0x1C, 0x00, 0x18, 0x38, 0x00, 0x60, 0x70, 0x01, 0x80, 0xE0, 0x06,
- 0x01, 0xC0, 0x18, 0x03, 0x80, 0x60, 0x07, 0x0F, 0x80, 0x7F, 0xFE, 0x01,
- 0xFF, 0x3F, 0xC0, 0x0F, 0xF0, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0,
- 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00,
- 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03,
- 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0,
- 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x0F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0x3C, 0x0F, 0x9F, 0x87, 0xE0, 0xFB,
- 0x1C, 0xC7, 0x01, 0xE0, 0xD8, 0x38, 0x1C, 0x07, 0x01, 0x81, 0x80, 0x60,
- 0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81,
- 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06,
- 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18,
- 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x8F, 0xE0,
- 0x7C, 0x1F, 0xFE, 0x07, 0xC1, 0xF0, 0x00, 0x1F, 0x00, 0xF8, 0xFF, 0x81,
- 0xF3, 0x83, 0x80, 0x6C, 0x03, 0x80, 0xF0, 0x03, 0x81, 0xC0, 0x03, 0x03,
- 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30,
- 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03, 0x03, 0x00,
- 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30, 0x00,
- 0x67, 0xFC, 0x03, 0xFF, 0xF8, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0xFE,
- 0x00, 0xF0, 0x3C, 0x07, 0x00, 0x38, 0x38, 0x00, 0x71, 0xC0, 0x00, 0xE6,
- 0x00, 0x01, 0x98, 0x00, 0x06, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00,
- 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x36, 0x00, 0x01,
- 0x98, 0x00, 0x06, 0x70, 0x00, 0x38, 0xE0, 0x01, 0xC1, 0xC0, 0x0E, 0x03,
- 0xC0, 0xF0, 0x07, 0xFF, 0x80, 0x03, 0xF0, 0x00, 0x00, 0x3F, 0x01, 0xF1,
- 0xFF, 0x83, 0xE7, 0x03, 0x80, 0xD8, 0x01, 0x81, 0xE0, 0x01, 0x83, 0xC0,
- 0x03, 0x87, 0x00, 0x03, 0x0E, 0x00, 0x07, 0x18, 0x00, 0x06, 0x30, 0x00,
- 0x0C, 0x60, 0x00, 0x18, 0xC0, 0x00, 0x31, 0x80, 0x00, 0x63, 0x00, 0x00,
- 0xC7, 0x00, 0x03, 0x0E, 0x00, 0x06, 0x1E, 0x00, 0x18, 0x36, 0x00, 0x70,
- 0x67, 0x03, 0xC0, 0xC7, 0xFE, 0x01, 0x83, 0xF0, 0x03, 0x00, 0x00, 0x06,
- 0x00, 0x00, 0x0C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0xC0, 0x00, 0x0F, 0xFC, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0x01,
- 0xF8, 0x00, 0x07, 0xFF, 0x1F, 0x0F, 0x07, 0x9F, 0x1C, 0x01, 0xD8, 0x38,
- 0x00, 0x78, 0x70, 0x00, 0x78, 0x60, 0x00, 0x38, 0xE0, 0x00, 0x38, 0xC0,
- 0x00, 0x18, 0xC0, 0x00, 0x18, 0xC0, 0x00, 0x18, 0xC0, 0x00, 0x18, 0xC0,
- 0x00, 0x18, 0xC0, 0x00, 0x18, 0x60, 0x00, 0x38, 0x70, 0x00, 0x78, 0x30,
- 0x00, 0x78, 0x1C, 0x01, 0xD8, 0x0F, 0x07, 0x98, 0x07, 0xFF, 0x18, 0x01,
- 0xFC, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00,
- 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00,
- 0x03, 0xFF, 0x00, 0x03, 0xFF, 0x7E, 0x03, 0xC3, 0xF0, 0x7F, 0x81, 0x8F,
- 0x0E, 0x0C, 0xE0, 0x00, 0x7E, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x00,
- 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00,
- 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06,
- 0x00, 0x00, 0x30, 0x00, 0x3F, 0xFF, 0xC1, 0xFF, 0xFE, 0x00, 0x07, 0xF0,
- 0x07, 0xFF, 0x63, 0xC0, 0xF9, 0xC0, 0x0E, 0x60, 0x01, 0x98, 0x00, 0x66,
- 0x00, 0x19, 0xC0, 0x00, 0x38, 0x00, 0x07, 0xC0, 0x00, 0x7F, 0xC0, 0x00,
- 0x7C, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00,
- 0xF8, 0x00, 0x7F, 0x00, 0x3B, 0xF0, 0x3C, 0xDF, 0xFE, 0x00, 0xFE, 0x00,
- 0x0C, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0,
- 0x00, 0x06, 0x00, 0x03, 0xFF, 0xFE, 0x1F, 0xFF, 0xF0, 0x0C, 0x00, 0x00,
- 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06, 0x00,
- 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x00, 0x03,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00,
- 0x00, 0xC0, 0x07, 0x07, 0x01, 0xF0, 0x1F, 0xFF, 0x00, 0x3F, 0x80, 0xF8,
- 0x03, 0xF1, 0xF0, 0x07, 0xE0, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80,
- 0x03, 0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00,
- 0x30, 0x30, 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03,
- 0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x38, 0x18, 0x00, 0xF0,
- 0x18, 0x03, 0x60, 0x38, 0x3C, 0xF8, 0x3F, 0xF1, 0xF0, 0x1F, 0x00, 0x00,
- 0x7F, 0xC0, 0xFF, 0xDF, 0xF0, 0x3F, 0xF0, 0xC0, 0x00, 0xC0, 0x30, 0x00,
- 0x30, 0x06, 0x00, 0x1C, 0x01, 0x80, 0x06, 0x00, 0x30, 0x01, 0x80, 0x0C,
- 0x00, 0xC0, 0x03, 0x80, 0x30, 0x00, 0x60, 0x18, 0x00, 0x18, 0x06, 0x00,
- 0x03, 0x03, 0x00, 0x00, 0xC0, 0xC0, 0x00, 0x18, 0x30, 0x00, 0x06, 0x18,
- 0x00, 0x00, 0xC6, 0x00, 0x00, 0x33, 0x00, 0x00, 0x0E, 0xC0, 0x00, 0x01,
- 0xE0, 0x00, 0x00, 0x78, 0x00, 0x7F, 0x00, 0x3F, 0xDF, 0xC0, 0x0F, 0xF1,
- 0x80, 0x00, 0x20, 0x60, 0x00, 0x18, 0x18, 0x00, 0x06, 0x06, 0x03, 0x01,
- 0x80, 0x81, 0xE0, 0x60, 0x30, 0x78, 0x10, 0x0C, 0x1E, 0x0C, 0x03, 0x0C,
- 0xC3, 0x00, 0xC3, 0x30, 0xC0, 0x10, 0xCC, 0x30, 0x06, 0x61, 0x98, 0x01,
- 0x98, 0x66, 0x00, 0x66, 0x19, 0x80, 0x0B, 0x03, 0x60, 0x03, 0xC0, 0xD0,
- 0x00, 0xF0, 0x1C, 0x00, 0x38, 0x07, 0x00, 0x0E, 0x01, 0xC0, 0x3F, 0x81,
- 0xFE, 0x3F, 0x81, 0xFE, 0x0C, 0x00, 0x38, 0x06, 0x00, 0x70, 0x03, 0x00,
- 0xE0, 0x01, 0x81, 0xC0, 0x00, 0xC3, 0x80, 0x00, 0x67, 0x00, 0x00, 0x3C,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x67, 0x00, 0x00, 0xC3,
- 0x80, 0x01, 0x81, 0xC0, 0x03, 0x00, 0xE0, 0x06, 0x00, 0x70, 0x0C, 0x00,
- 0x38, 0x18, 0x00, 0x1C, 0x7F, 0x81, 0xFF, 0x7F, 0x81, 0xFF, 0x7F, 0x00,
- 0xFF, 0x7F, 0x00, 0xFF, 0x18, 0x00, 0x0C, 0x18, 0x00, 0x18, 0x0C, 0x00,
- 0x18, 0x0C, 0x00, 0x30, 0x06, 0x00, 0x30, 0x06, 0x00, 0x60, 0x03, 0x00,
- 0x60, 0x03, 0x00, 0xC0, 0x01, 0x80, 0xC0, 0x01, 0x81, 0x80, 0x00, 0xC1,
- 0x80, 0x00, 0xC3, 0x00, 0x00, 0x63, 0x00, 0x00, 0x66, 0x00, 0x00, 0x36,
- 0x00, 0x00, 0x34, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0xC0, 0x00, 0x7F, 0xFC, 0x00, 0x7F, 0xFC,
- 0x00, 0xFF, 0xFF, 0x7F, 0xFF, 0xB0, 0x01, 0x98, 0x01, 0xCC, 0x01, 0xC0,
- 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xE0,
- 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x03, 0x70,
- 0x01, 0xB0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xE0, 0x7C, 0x0C,
- 0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03,
- 0x00, 0x60, 0x0C, 0x03, 0x00, 0xE0, 0xF0, 0x1E, 0x00, 0x70, 0x06, 0x00,
- 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60,
- 0x0C, 0x01, 0x80, 0x18, 0x03, 0xE0, 0x1C, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xF0, 0xE0, 0x1F, 0x00, 0x60, 0x06, 0x00, 0xC0, 0x18,
- 0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x01,
- 0x80, 0x38, 0x01, 0xE0, 0x3C, 0x1C, 0x03, 0x00, 0xC0, 0x18, 0x03, 0x00,
- 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0xC0,
- 0xF8, 0x1C, 0x00, 0x0F, 0x00, 0x03, 0xFC, 0x03, 0x70, 0xE0, 0x76, 0x07,
- 0x8E, 0xC0, 0x1F, 0xC0, 0x00, 0xF0 };
-
-const GFXglyph FreeMono24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 28, 0, 1 }, // 0x20 ' '
- { 0, 5, 30, 28, 11, -28 }, // 0x21 '!'
- { 19, 16, 14, 28, 6, -28 }, // 0x22 '"'
- { 47, 19, 32, 28, 4, -29 }, // 0x23 '#'
- { 123, 18, 33, 28, 5, -29 }, // 0x24 '$'
- { 198, 20, 29, 28, 4, -27 }, // 0x25 '%'
- { 271, 18, 25, 28, 5, -23 }, // 0x26 '&'
- { 328, 7, 14, 28, 11, -28 }, // 0x27 '''
- { 341, 7, 34, 28, 14, -27 }, // 0x28 '('
- { 371, 7, 34, 28, 8, -27 }, // 0x29 ')'
- { 401, 18, 16, 28, 5, -27 }, // 0x2A '*'
- { 437, 20, 22, 28, 4, -23 }, // 0x2B '+'
- { 492, 9, 14, 28, 6, -6 }, // 0x2C ','
- { 508, 22, 2, 28, 3, -13 }, // 0x2D '-'
- { 514, 7, 6, 28, 11, -4 }, // 0x2E '.'
- { 520, 18, 35, 28, 5, -30 }, // 0x2F '/'
- { 599, 18, 30, 28, 5, -28 }, // 0x30 '0'
- { 667, 16, 29, 28, 6, -28 }, // 0x31 '1'
- { 725, 18, 29, 28, 5, -28 }, // 0x32 '2'
- { 791, 19, 30, 28, 5, -28 }, // 0x33 '3'
- { 863, 16, 28, 28, 6, -27 }, // 0x34 '4'
- { 919, 19, 29, 28, 5, -27 }, // 0x35 '5'
- { 988, 18, 30, 28, 6, -28 }, // 0x36 '6'
- { 1056, 18, 28, 28, 5, -27 }, // 0x37 '7'
- { 1119, 18, 30, 28, 5, -28 }, // 0x38 '8'
- { 1187, 18, 30, 28, 6, -28 }, // 0x39 '9'
- { 1255, 7, 21, 28, 11, -19 }, // 0x3A ':'
- { 1274, 10, 27, 28, 7, -19 }, // 0x3B ';'
- { 1308, 22, 22, 28, 3, -23 }, // 0x3C '<'
- { 1369, 24, 9, 28, 2, -17 }, // 0x3D '='
- { 1396, 21, 22, 28, 4, -23 }, // 0x3E '>'
- { 1454, 17, 28, 28, 6, -26 }, // 0x3F '?'
- { 1514, 18, 32, 28, 5, -28 }, // 0x40 '@'
- { 1586, 28, 26, 28, 0, -25 }, // 0x41 'A'
- { 1677, 22, 26, 28, 3, -25 }, // 0x42 'B'
- { 1749, 22, 28, 28, 3, -26 }, // 0x43 'C'
- { 1826, 22, 26, 28, 3, -25 }, // 0x44 'D'
- { 1898, 22, 26, 28, 3, -25 }, // 0x45 'E'
- { 1970, 22, 26, 28, 3, -25 }, // 0x46 'F'
- { 2042, 23, 28, 28, 3, -26 }, // 0x47 'G'
- { 2123, 23, 26, 28, 3, -25 }, // 0x48 'H'
- { 2198, 16, 26, 28, 6, -25 }, // 0x49 'I'
- { 2250, 23, 27, 28, 4, -25 }, // 0x4A 'J'
- { 2328, 24, 26, 28, 3, -25 }, // 0x4B 'K'
- { 2406, 21, 26, 28, 4, -25 }, // 0x4C 'L'
- { 2475, 26, 26, 28, 1, -25 }, // 0x4D 'M'
- { 2560, 24, 26, 28, 2, -25 }, // 0x4E 'N'
- { 2638, 24, 28, 28, 2, -26 }, // 0x4F 'O'
- { 2722, 21, 26, 28, 3, -25 }, // 0x50 'P'
- { 2791, 24, 32, 28, 2, -26 }, // 0x51 'Q'
- { 2887, 24, 26, 28, 3, -25 }, // 0x52 'R'
- { 2965, 20, 28, 28, 4, -26 }, // 0x53 'S'
- { 3035, 22, 26, 28, 3, -25 }, // 0x54 'T'
- { 3107, 23, 27, 28, 3, -25 }, // 0x55 'U'
- { 3185, 28, 26, 28, 0, -25 }, // 0x56 'V'
- { 3276, 26, 26, 28, 1, -25 }, // 0x57 'W'
- { 3361, 24, 26, 28, 2, -25 }, // 0x58 'X'
- { 3439, 24, 26, 28, 2, -25 }, // 0x59 'Y'
- { 3517, 18, 26, 28, 5, -25 }, // 0x5A 'Z'
- { 3576, 7, 34, 28, 13, -27 }, // 0x5B '['
- { 3606, 18, 35, 28, 5, -30 }, // 0x5C '\'
- { 3685, 7, 34, 28, 8, -27 }, // 0x5D ']'
- { 3715, 18, 12, 28, 5, -28 }, // 0x5E '^'
- { 3742, 28, 2, 28, 0, 5 }, // 0x5F '_'
- { 3749, 8, 7, 28, 7, -29 }, // 0x60 '`'
- { 3756, 22, 22, 28, 3, -20 }, // 0x61 'a'
- { 3817, 23, 29, 28, 2, -27 }, // 0x62 'b'
- { 3901, 21, 22, 28, 4, -20 }, // 0x63 'c'
- { 3959, 24, 29, 28, 3, -27 }, // 0x64 'd'
- { 4046, 21, 22, 28, 3, -20 }, // 0x65 'e'
- { 4104, 19, 28, 28, 6, -27 }, // 0x66 'f'
- { 4171, 23, 30, 28, 3, -20 }, // 0x67 'g'
- { 4258, 23, 28, 28, 3, -27 }, // 0x68 'h'
- { 4339, 18, 29, 28, 5, -28 }, // 0x69 'i'
- { 4405, 14, 38, 28, 6, -28 }, // 0x6A 'j'
- { 4472, 22, 28, 28, 4, -27 }, // 0x6B 'k'
- { 4549, 18, 28, 28, 5, -27 }, // 0x6C 'l'
- { 4612, 28, 21, 28, 0, -20 }, // 0x6D 'm'
- { 4686, 23, 21, 28, 2, -20 }, // 0x6E 'n'
- { 4747, 22, 22, 28, 3, -20 }, // 0x6F 'o'
- { 4808, 23, 30, 28, 2, -20 }, // 0x70 'p'
- { 4895, 24, 30, 28, 3, -20 }, // 0x71 'q'
- { 4985, 21, 20, 28, 5, -19 }, // 0x72 'r'
- { 5038, 18, 22, 28, 5, -20 }, // 0x73 's'
- { 5088, 21, 27, 28, 3, -25 }, // 0x74 't'
- { 5159, 23, 21, 28, 3, -19 }, // 0x75 'u'
- { 5220, 26, 20, 28, 1, -19 }, // 0x76 'v'
- { 5285, 26, 20, 28, 1, -19 }, // 0x77 'w'
- { 5350, 24, 20, 28, 2, -19 }, // 0x78 'x'
- { 5410, 24, 29, 28, 2, -19 }, // 0x79 'y'
- { 5497, 17, 20, 28, 6, -19 }, // 0x7A 'z'
- { 5540, 11, 34, 28, 8, -27 }, // 0x7B '{'
- { 5587, 2, 34, 28, 13, -27 }, // 0x7C '|'
- { 5596, 11, 34, 28, 9, -27 }, // 0x7D '}'
- { 5643, 20, 6, 28, 4, -15 } }; // 0x7E '~'
-
-const GFXfont FreeMono24pt7b PROGMEM = {
- (uint8_t *)FreeMono24pt7bBitmaps,
- (GFXglyph *)FreeMono24pt7bGlyphs,
- 0x20, 0x7E, 47 };
-
-// Approx. 6330 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono9pt7b.h
deleted file mode 100644
index c82d786..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMono9pt7b.h
+++ /dev/null
@@ -1,176 +0,0 @@
-const uint8_t FreeMono9pt7bBitmaps[] PROGMEM = {
- 0xAA, 0xA8, 0x0C, 0xED, 0x24, 0x92, 0x48, 0x24, 0x48, 0x91, 0x2F, 0xE4,
- 0x89, 0x7F, 0x28, 0x51, 0x22, 0x40, 0x08, 0x3E, 0x62, 0x40, 0x30, 0x0E,
- 0x01, 0x81, 0xC3, 0xBE, 0x08, 0x08, 0x71, 0x12, 0x23, 0x80, 0x23, 0xB8,
- 0x0E, 0x22, 0x44, 0x70, 0x38, 0x81, 0x02, 0x06, 0x1A, 0x65, 0x46, 0xC8,
- 0xEC, 0xE9, 0x24, 0x5A, 0xAA, 0xA9, 0x40, 0xA9, 0x55, 0x5A, 0x80, 0x10,
- 0x22, 0x4B, 0xE3, 0x05, 0x11, 0x00, 0x10, 0x20, 0x47, 0xF1, 0x02, 0x04,
- 0x00, 0x6B, 0x48, 0xFF, 0x00, 0xF0, 0x02, 0x08, 0x10, 0x60, 0x81, 0x04,
- 0x08, 0x20, 0x41, 0x02, 0x08, 0x00, 0x38, 0x8A, 0x0C, 0x18, 0x30, 0x60,
- 0xC1, 0x82, 0x88, 0xE0, 0x27, 0x28, 0x42, 0x10, 0x84, 0x21, 0x3E, 0x38,
- 0x8A, 0x08, 0x10, 0x20, 0x82, 0x08, 0x61, 0x03, 0xF8, 0x7C, 0x06, 0x02,
- 0x02, 0x1C, 0x06, 0x01, 0x01, 0x01, 0x42, 0x3C, 0x18, 0xA2, 0x92, 0x8A,
- 0x28, 0xBF, 0x08, 0x21, 0xC0, 0x7C, 0x81, 0x03, 0xE4, 0x40, 0x40, 0x81,
- 0x03, 0x88, 0xE0, 0x1E, 0x41, 0x04, 0x0B, 0x98, 0xB0, 0xC1, 0xC2, 0x88,
- 0xE0, 0xFE, 0x04, 0x08, 0x20, 0x40, 0x82, 0x04, 0x08, 0x20, 0x40, 0x38,
- 0x8A, 0x0C, 0x14, 0x47, 0x11, 0x41, 0x83, 0x8C, 0xE0, 0x38, 0x8A, 0x1C,
- 0x18, 0x68, 0xCE, 0x81, 0x04, 0x13, 0xC0, 0xF0, 0x0F, 0x6C, 0x00, 0xD2,
- 0xD2, 0x00, 0x03, 0x04, 0x18, 0x60, 0x60, 0x18, 0x04, 0x03, 0xFF, 0x80,
- 0x00, 0x1F, 0xF0, 0x40, 0x18, 0x03, 0x00, 0x60, 0x20, 0x60, 0xC0, 0x80,
- 0x3D, 0x84, 0x08, 0x30, 0xC2, 0x00, 0x00, 0x00, 0x30, 0x3C, 0x46, 0x82,
- 0x8E, 0xB2, 0xA2, 0xA2, 0x9F, 0x80, 0x80, 0x40, 0x3C, 0x3C, 0x01, 0x40,
- 0x28, 0x09, 0x01, 0x10, 0x42, 0x0F, 0xC1, 0x04, 0x40, 0x9E, 0x3C, 0xFE,
- 0x21, 0x90, 0x48, 0x67, 0xE2, 0x09, 0x02, 0x81, 0x41, 0xFF, 0x80, 0x3E,
- 0xB0, 0xF0, 0x30, 0x08, 0x04, 0x02, 0x00, 0x80, 0x60, 0x8F, 0x80, 0xFE,
- 0x21, 0x90, 0x68, 0x14, 0x0A, 0x05, 0x02, 0x83, 0x43, 0x7F, 0x00, 0xFF,
- 0x20, 0x90, 0x08, 0x87, 0xC2, 0x21, 0x00, 0x81, 0x40, 0xFF, 0xC0, 0xFF,
- 0xA0, 0x50, 0x08, 0x87, 0xC2, 0x21, 0x00, 0x80, 0x40, 0x78, 0x00, 0x1E,
- 0x98, 0x6C, 0x0A, 0x00, 0x80, 0x20, 0xF8, 0x0B, 0x02, 0x60, 0x87, 0xC0,
- 0xE3, 0xA0, 0x90, 0x48, 0x27, 0xF2, 0x09, 0x04, 0x82, 0x41, 0x71, 0xC0,
- 0xF9, 0x08, 0x42, 0x10, 0x84, 0x27, 0xC0, 0x1F, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x82, 0x82, 0xC6, 0x78, 0xE3, 0xA1, 0x11, 0x09, 0x05, 0x83, 0x21,
- 0x08, 0x84, 0x41, 0x70, 0xC0, 0xE0, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41,
- 0x41, 0x41, 0xFF, 0xE0, 0xEC, 0x19, 0x45, 0x28, 0xA4, 0xA4, 0x94, 0x91,
- 0x12, 0x02, 0x40, 0x5C, 0x1C, 0xC3, 0xB0, 0x94, 0x4A, 0x24, 0x92, 0x49,
- 0x14, 0x8A, 0x43, 0x70, 0x80, 0x1E, 0x31, 0x90, 0x50, 0x18, 0x0C, 0x06,
- 0x02, 0x82, 0x63, 0x0F, 0x00, 0xFE, 0x43, 0x41, 0x41, 0x42, 0x7C, 0x40,
- 0x40, 0x40, 0xF0, 0x1C, 0x31, 0x90, 0x50, 0x18, 0x0C, 0x06, 0x02, 0x82,
- 0x63, 0x1F, 0x04, 0x07, 0x92, 0x30, 0xFE, 0x21, 0x90, 0x48, 0x24, 0x23,
- 0xE1, 0x10, 0x84, 0x41, 0x70, 0xC0, 0x3A, 0xCD, 0x0A, 0x03, 0x01, 0x80,
- 0xC1, 0xC7, 0x78, 0xFF, 0xC4, 0x62, 0x21, 0x00, 0x80, 0x40, 0x20, 0x10,
- 0x08, 0x1F, 0x00, 0xE3, 0xA0, 0x90, 0x48, 0x24, 0x12, 0x09, 0x04, 0x82,
- 0x22, 0x0E, 0x00, 0xF1, 0xE8, 0x10, 0x82, 0x10, 0x42, 0x10, 0x22, 0x04,
- 0x80, 0x50, 0x0C, 0x00, 0x80, 0xF1, 0xE8, 0x09, 0x11, 0x25, 0x44, 0xA8,
- 0x55, 0x0C, 0xA1, 0x8C, 0x31, 0x84, 0x30, 0xE3, 0xA0, 0x88, 0x82, 0x80,
- 0x80, 0xC0, 0x90, 0x44, 0x41, 0x71, 0xC0, 0xE3, 0xA0, 0x88, 0x82, 0x81,
- 0x40, 0x40, 0x20, 0x10, 0x08, 0x1F, 0x00, 0xFD, 0x0A, 0x20, 0x81, 0x04,
- 0x10, 0x21, 0x83, 0xFC, 0xEA, 0xAA, 0xAA, 0xC0, 0x80, 0x81, 0x03, 0x02,
- 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0xD5, 0x55, 0x55, 0xC0,
- 0x10, 0x51, 0x22, 0x28, 0x20, 0xFF, 0xE0, 0x88, 0x80, 0x7E, 0x00, 0x80,
- 0x47, 0xEC, 0x14, 0x0A, 0x0C, 0xFB, 0xC0, 0x20, 0x10, 0x0B, 0xC6, 0x12,
- 0x05, 0x02, 0x81, 0x40, 0xB0, 0xB7, 0x80, 0x3A, 0x8E, 0x0C, 0x08, 0x10,
- 0x10, 0x9E, 0x03, 0x00, 0x80, 0x47, 0xA4, 0x34, 0x0A, 0x05, 0x02, 0x81,
- 0x21, 0x8F, 0x60, 0x3C, 0x43, 0x81, 0xFF, 0x80, 0x80, 0x61, 0x3E, 0x3D,
- 0x04, 0x3E, 0x41, 0x04, 0x10, 0x41, 0x0F, 0x80, 0x3D, 0xA1, 0xA0, 0x50,
- 0x28, 0x14, 0x09, 0x0C, 0x7A, 0x01, 0x01, 0x87, 0x80, 0xC0, 0x20, 0x10,
- 0x0B, 0xC6, 0x32, 0x09, 0x04, 0x82, 0x41, 0x20, 0xB8, 0xE0, 0x10, 0x01,
- 0xC0, 0x81, 0x02, 0x04, 0x08, 0x11, 0xFC, 0x10, 0x3E, 0x10, 0x84, 0x21,
- 0x08, 0x42, 0x3F, 0x00, 0xC0, 0x40, 0x40, 0x4F, 0x44, 0x58, 0x70, 0x48,
- 0x44, 0x42, 0xC7, 0x70, 0x20, 0x40, 0x81, 0x02, 0x04, 0x08, 0x10, 0x23,
- 0xF8, 0xB7, 0x64, 0x62, 0x31, 0x18, 0x8C, 0x46, 0x23, 0x91, 0x5E, 0x31,
- 0x90, 0x48, 0x24, 0x12, 0x09, 0x05, 0xC7, 0x3E, 0x31, 0xA0, 0x30, 0x18,
- 0x0C, 0x05, 0x8C, 0x7C, 0xDE, 0x30, 0x90, 0x28, 0x14, 0x0A, 0x05, 0x84,
- 0xBC, 0x40, 0x20, 0x38, 0x00, 0x3D, 0xA1, 0xA0, 0x50, 0x28, 0x14, 0x09,
- 0x0C, 0x7A, 0x01, 0x00, 0x80, 0xE0, 0xCE, 0xA1, 0x82, 0x04, 0x08, 0x10,
- 0x7C, 0x3A, 0x8D, 0x0B, 0x80, 0xF0, 0x70, 0xDE, 0x40, 0x40, 0xFC, 0x40,
- 0x40, 0x40, 0x40, 0x40, 0x41, 0x3E, 0xC3, 0x41, 0x41, 0x41, 0x41, 0x41,
- 0x43, 0x3D, 0xE3, 0xA0, 0x90, 0x84, 0x42, 0x20, 0xA0, 0x50, 0x10, 0xE3,
- 0xC0, 0x92, 0x4B, 0x25, 0x92, 0xA9, 0x98, 0x44, 0xE3, 0x31, 0x05, 0x01,
- 0x01, 0x41, 0x11, 0x05, 0xC7, 0xE3, 0xA0, 0x90, 0x84, 0x42, 0x40, 0xA0,
- 0x60, 0x10, 0x10, 0x08, 0x3E, 0x00, 0xFD, 0x08, 0x20, 0x82, 0x08, 0x10,
- 0xBF, 0x29, 0x24, 0xA2, 0x49, 0x26, 0xFF, 0xF8, 0x89, 0x24, 0x8A, 0x49,
- 0x2C, 0x61, 0x24, 0x30 };
-
-const GFXglyph FreeMono9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 11, 0, 1 }, // 0x20 ' '
- { 0, 2, 11, 11, 4, -10 }, // 0x21 '!'
- { 3, 6, 5, 11, 2, -10 }, // 0x22 '"'
- { 7, 7, 12, 11, 2, -10 }, // 0x23 '#'
- { 18, 8, 12, 11, 1, -10 }, // 0x24 '$'
- { 30, 7, 11, 11, 2, -10 }, // 0x25 '%'
- { 40, 7, 10, 11, 2, -9 }, // 0x26 '&'
- { 49, 3, 5, 11, 4, -10 }, // 0x27 '''
- { 51, 2, 13, 11, 5, -10 }, // 0x28 '('
- { 55, 2, 13, 11, 4, -10 }, // 0x29 ')'
- { 59, 7, 7, 11, 2, -10 }, // 0x2A '*'
- { 66, 7, 7, 11, 2, -8 }, // 0x2B '+'
- { 73, 3, 5, 11, 2, -1 }, // 0x2C ','
- { 75, 9, 1, 11, 1, -5 }, // 0x2D '-'
- { 77, 2, 2, 11, 4, -1 }, // 0x2E '.'
- { 78, 7, 13, 11, 2, -11 }, // 0x2F '/'
- { 90, 7, 11, 11, 2, -10 }, // 0x30 '0'
- { 100, 5, 11, 11, 3, -10 }, // 0x31 '1'
- { 107, 7, 11, 11, 2, -10 }, // 0x32 '2'
- { 117, 8, 11, 11, 1, -10 }, // 0x33 '3'
- { 128, 6, 11, 11, 3, -10 }, // 0x34 '4'
- { 137, 7, 11, 11, 2, -10 }, // 0x35 '5'
- { 147, 7, 11, 11, 2, -10 }, // 0x36 '6'
- { 157, 7, 11, 11, 2, -10 }, // 0x37 '7'
- { 167, 7, 11, 11, 2, -10 }, // 0x38 '8'
- { 177, 7, 11, 11, 2, -10 }, // 0x39 '9'
- { 187, 2, 8, 11, 4, -7 }, // 0x3A ':'
- { 189, 3, 11, 11, 3, -7 }, // 0x3B ';'
- { 194, 8, 8, 11, 1, -8 }, // 0x3C '<'
- { 202, 9, 4, 11, 1, -6 }, // 0x3D '='
- { 207, 9, 8, 11, 1, -8 }, // 0x3E '>'
- { 216, 7, 10, 11, 2, -9 }, // 0x3F '?'
- { 225, 8, 12, 11, 2, -10 }, // 0x40 '@'
- { 237, 11, 10, 11, 0, -9 }, // 0x41 'A'
- { 251, 9, 10, 11, 1, -9 }, // 0x42 'B'
- { 263, 9, 10, 11, 1, -9 }, // 0x43 'C'
- { 275, 9, 10, 11, 1, -9 }, // 0x44 'D'
- { 287, 9, 10, 11, 1, -9 }, // 0x45 'E'
- { 299, 9, 10, 11, 1, -9 }, // 0x46 'F'
- { 311, 10, 10, 11, 1, -9 }, // 0x47 'G'
- { 324, 9, 10, 11, 1, -9 }, // 0x48 'H'
- { 336, 5, 10, 11, 3, -9 }, // 0x49 'I'
- { 343, 8, 10, 11, 2, -9 }, // 0x4A 'J'
- { 353, 9, 10, 11, 1, -9 }, // 0x4B 'K'
- { 365, 8, 10, 11, 2, -9 }, // 0x4C 'L'
- { 375, 11, 10, 11, 0, -9 }, // 0x4D 'M'
- { 389, 9, 10, 11, 1, -9 }, // 0x4E 'N'
- { 401, 9, 10, 11, 1, -9 }, // 0x4F 'O'
- { 413, 8, 10, 11, 1, -9 }, // 0x50 'P'
- { 423, 9, 13, 11, 1, -9 }, // 0x51 'Q'
- { 438, 9, 10, 11, 1, -9 }, // 0x52 'R'
- { 450, 7, 10, 11, 2, -9 }, // 0x53 'S'
- { 459, 9, 10, 11, 1, -9 }, // 0x54 'T'
- { 471, 9, 10, 11, 1, -9 }, // 0x55 'U'
- { 483, 11, 10, 11, 0, -9 }, // 0x56 'V'
- { 497, 11, 10, 11, 0, -9 }, // 0x57 'W'
- { 511, 9, 10, 11, 1, -9 }, // 0x58 'X'
- { 523, 9, 10, 11, 1, -9 }, // 0x59 'Y'
- { 535, 7, 10, 11, 2, -9 }, // 0x5A 'Z'
- { 544, 2, 13, 11, 5, -10 }, // 0x5B '['
- { 548, 7, 13, 11, 2, -11 }, // 0x5C '\'
- { 560, 2, 13, 11, 4, -10 }, // 0x5D ']'
- { 564, 7, 5, 11, 2, -10 }, // 0x5E '^'
- { 569, 11, 1, 11, 0, 2 }, // 0x5F '_'
- { 571, 3, 3, 11, 3, -11 }, // 0x60 '`'
- { 573, 9, 8, 11, 1, -7 }, // 0x61 'a'
- { 582, 9, 11, 11, 1, -10 }, // 0x62 'b'
- { 595, 7, 8, 11, 2, -7 }, // 0x63 'c'
- { 602, 9, 11, 11, 1, -10 }, // 0x64 'd'
- { 615, 8, 8, 11, 1, -7 }, // 0x65 'e'
- { 623, 6, 11, 11, 3, -10 }, // 0x66 'f'
- { 632, 9, 11, 11, 1, -7 }, // 0x67 'g'
- { 645, 9, 11, 11, 1, -10 }, // 0x68 'h'
- { 658, 7, 10, 11, 2, -9 }, // 0x69 'i'
- { 667, 5, 13, 11, 3, -9 }, // 0x6A 'j'
- { 676, 8, 11, 11, 2, -10 }, // 0x6B 'k'
- { 687, 7, 11, 11, 2, -10 }, // 0x6C 'l'
- { 697, 9, 8, 11, 1, -7 }, // 0x6D 'm'
- { 706, 9, 8, 11, 1, -7 }, // 0x6E 'n'
- { 715, 9, 8, 11, 1, -7 }, // 0x6F 'o'
- { 724, 9, 11, 11, 1, -7 }, // 0x70 'p'
- { 737, 9, 11, 11, 1, -7 }, // 0x71 'q'
- { 750, 7, 8, 11, 3, -7 }, // 0x72 'r'
- { 757, 7, 8, 11, 2, -7 }, // 0x73 's'
- { 764, 8, 10, 11, 2, -9 }, // 0x74 't'
- { 774, 8, 8, 11, 1, -7 }, // 0x75 'u'
- { 782, 9, 8, 11, 1, -7 }, // 0x76 'v'
- { 791, 9, 8, 11, 1, -7 }, // 0x77 'w'
- { 800, 9, 8, 11, 1, -7 }, // 0x78 'x'
- { 809, 9, 11, 11, 1, -7 }, // 0x79 'y'
- { 822, 7, 8, 11, 2, -7 }, // 0x7A 'z'
- { 829, 3, 13, 11, 4, -10 }, // 0x7B '{'
- { 834, 1, 13, 11, 5, -10 }, // 0x7C '|'
- { 836, 3, 13, 11, 4, -10 }, // 0x7D '}'
- { 841, 7, 3, 11, 2, -6 } }; // 0x7E '~'
-
-const GFXfont FreeMono9pt7b PROGMEM = {
- (uint8_t *)FreeMono9pt7bBitmaps,
- (GFXglyph *)FreeMono9pt7bGlyphs,
- 0x20, 0x7E, 18 };
-
-// Approx. 1516 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold12pt7b.h
deleted file mode 100644
index 4ad9d1a..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold12pt7b.h
+++ /dev/null
@@ -1,250 +0,0 @@
-const uint8_t FreeMonoBold12pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xF6, 0x66, 0x60, 0x6F, 0x60, 0xE7, 0xE7, 0x62, 0x42,
- 0x42, 0x42, 0x42, 0x11, 0x87, 0x30, 0xC6, 0x18, 0xC3, 0x31, 0xFF, 0xFF,
- 0xF9, 0x98, 0x33, 0x06, 0x60, 0xCC, 0x7F, 0xEF, 0xFC, 0x66, 0x0C, 0xC3,
- 0x98, 0x63, 0x04, 0x40, 0x0C, 0x03, 0x00, 0xC0, 0xFE, 0x7F, 0x9C, 0x66,
- 0x09, 0x80, 0x78, 0x0F, 0xE0, 0x7F, 0x03, 0xE0, 0xF8, 0x7F, 0xFB, 0xFC,
- 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x38, 0x1F, 0x0C, 0x42, 0x10, 0xC4, 0x1F,
- 0x03, 0x9C, 0x3C, 0x7F, 0x33, 0xE0, 0x8C, 0x21, 0x08, 0xC3, 0xE0, 0x70,
- 0x3E, 0x1F, 0xC6, 0x61, 0x80, 0x70, 0x0C, 0x07, 0x83, 0xEE, 0xDF, 0xB3,
- 0xCC, 0x73, 0xFE, 0x7F, 0x80, 0xFD, 0x24, 0x90, 0x39, 0xDC, 0xE6, 0x73,
- 0x18, 0xC6, 0x31, 0x8C, 0x31, 0x8E, 0x31, 0xC4, 0xE7, 0x1C, 0xE3, 0x1C,
- 0x63, 0x18, 0xC6, 0x31, 0x98, 0xCE, 0x67, 0x10, 0x0C, 0x03, 0x00, 0xC3,
- 0xB7, 0xFF, 0xDF, 0xE1, 0xE0, 0xFC, 0x33, 0x0C, 0xC0, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x06, 0x00, 0x3B, 0x9C, 0xCE, 0x62, 0x00, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x80, 0x00, 0x40, 0x30, 0x1C, 0x07, 0x03, 0x80, 0xE0, 0x30,
- 0x1C, 0x06, 0x03, 0x80, 0xC0, 0x70, 0x18, 0x0E, 0x03, 0x01, 0xC0, 0x60,
- 0x38, 0x0E, 0x01, 0x00, 0x1E, 0x0F, 0xC6, 0x1B, 0x87, 0xC0, 0xF0, 0x3C,
- 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x87, 0x61, 0x8F, 0xC1, 0xE0, 0x1C,
- 0x0F, 0x0F, 0xC3, 0xB0, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00,
- 0xC0, 0x30, 0x0C, 0x3F, 0xFF, 0xFC, 0x1F, 0x1F, 0xEE, 0x1F, 0x83, 0xC0,
- 0xC0, 0x70, 0x38, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE3, 0xF0, 0xFF, 0xFF,
- 0xFC, 0x3F, 0x0F, 0xF1, 0x87, 0x00, 0x60, 0x0C, 0x03, 0x83, 0xE0, 0x7C,
- 0x01, 0xC0, 0x0C, 0x01, 0x80, 0x3C, 0x0F, 0xFF, 0x9F, 0xC0, 0x07, 0x07,
- 0x83, 0xC3, 0xE1, 0xB1, 0xD8, 0xCC, 0xC6, 0xE3, 0x7F, 0xFF, 0xE0, 0x61,
- 0xF8, 0xFC, 0x7F, 0x9F, 0xE6, 0x01, 0x80, 0x60, 0x1F, 0x87, 0xF9, 0x86,
- 0x00, 0xC0, 0x30, 0x0C, 0x03, 0xC1, 0xBF, 0xE7, 0xE0, 0x07, 0xC7, 0xF3,
- 0xC1, 0xC0, 0x60, 0x38, 0x0E, 0xF3, 0xFE, 0xF1, 0xF8, 0x3E, 0x0F, 0x83,
- 0x71, 0xCF, 0xE1, 0xF0, 0xFF, 0xFF, 0xFC, 0x1F, 0x07, 0x01, 0x80, 0x60,
- 0x38, 0x0C, 0x03, 0x01, 0xC0, 0x60, 0x18, 0x0E, 0x03, 0x00, 0xC0, 0x1E,
- 0x1F, 0xEE, 0x1F, 0x03, 0xC0, 0xF0, 0x36, 0x19, 0xFE, 0x7F, 0xB8, 0x7C,
- 0x0F, 0x03, 0xE1, 0xDF, 0xE3, 0xF0, 0x3E, 0x1F, 0xCE, 0x3B, 0x07, 0xC1,
- 0xF0, 0x7E, 0x3D, 0xFF, 0x3D, 0xC0, 0x70, 0x18, 0x0E, 0x0F, 0x3F, 0x8F,
- 0x80, 0xFF, 0x80, 0x00, 0xFF, 0x80, 0x77, 0x70, 0x00, 0x00, 0x76, 0x6C,
- 0xC8, 0x80, 0x00, 0x30, 0x0F, 0x03, 0xE0, 0xF8, 0x3E, 0x0F, 0x80, 0x3E,
- 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x00, 0x20, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x0F, 0x80, 0x3E, 0x00, 0xF8,
- 0x03, 0xE0, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x0F, 0x00, 0x40, 0x00, 0x7C,
- 0x7F, 0xB0, 0xF8, 0x30, 0x18, 0x1C, 0x3C, 0x3C, 0x18, 0x08, 0x00, 0x07,
- 0x03, 0x81, 0xC0, 0x1E, 0x07, 0xF1, 0xC7, 0x30, 0x6C, 0x0D, 0x87, 0xB3,
- 0xF6, 0xE6, 0xD8, 0xDB, 0x1B, 0x73, 0x67, 0xFC, 0x7F, 0x80, 0x30, 0x03,
- 0x00, 0x71, 0xC7, 0xF8, 0x7C, 0x00, 0x3F, 0x80, 0x7F, 0x80, 0x1F, 0x00,
- 0x76, 0x00, 0xEE, 0x01, 0x8C, 0x07, 0x18, 0x0E, 0x38, 0x1F, 0xF0, 0x7F,
- 0xF0, 0xC0, 0x61, 0x80, 0xCF, 0xC7, 0xFF, 0x8F, 0xC0, 0xFF, 0xC7, 0xFF,
- 0x0C, 0x1C, 0x60, 0x63, 0x03, 0x18, 0x38, 0xFF, 0x87, 0xFE, 0x30, 0x39,
- 0x80, 0xCC, 0x06, 0x60, 0x7F, 0xFF, 0x7F, 0xF0, 0x0F, 0xF3, 0xFF, 0x70,
- 0x76, 0x03, 0xC0, 0x3C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0x60,
- 0x37, 0x07, 0x3F, 0xF0, 0xFC, 0xFF, 0x0F, 0xFC, 0x60, 0xE6, 0x06, 0x60,
- 0x36, 0x03, 0x60, 0x36, 0x03, 0x60, 0x36, 0x03, 0x60, 0x76, 0x0E, 0xFF,
- 0xCF, 0xF8, 0xFF, 0xF7, 0xFF, 0x8C, 0x0C, 0x60, 0x63, 0x1B, 0x18, 0xC0,
- 0xFE, 0x07, 0xF0, 0x31, 0x81, 0x8C, 0xCC, 0x06, 0x60, 0x3F, 0xFF, 0xFF,
- 0xFC, 0xFF, 0xFF, 0xFF, 0xCC, 0x06, 0x60, 0x33, 0x19, 0x98, 0xC0, 0xFE,
- 0x07, 0xF0, 0x31, 0x81, 0x8C, 0x0C, 0x00, 0x60, 0x0F, 0xF0, 0x7F, 0x80,
- 0x0F, 0xF1, 0xFF, 0x9C, 0x1C, 0xC0, 0x6C, 0x03, 0x60, 0x03, 0x00, 0x18,
- 0x7F, 0xC3, 0xFE, 0x01, 0xB8, 0x0C, 0xE0, 0xE3, 0xFF, 0x07, 0xE0, 0x7C,
- 0xF9, 0xF3, 0xE3, 0x03, 0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3, 0xFF, 0x0F,
- 0xFC, 0x30, 0x30, 0xC0, 0xC3, 0x03, 0x0C, 0x0C, 0xFC, 0xFF, 0xF3, 0xF0,
- 0xFF, 0xFF, 0xF0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03,
- 0x00, 0xC0, 0x30, 0xFF, 0xFF, 0xF0, 0x0F, 0xF8, 0x7F, 0xC0, 0x30, 0x01,
- 0x80, 0x0C, 0x00, 0x60, 0x03, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x30, 0x31,
- 0xC3, 0x0F, 0xF8, 0x1F, 0x00, 0xFC, 0xFB, 0xF3, 0xE3, 0x0E, 0x0C, 0x70,
- 0x33, 0x80, 0xFC, 0x03, 0xF0, 0x0F, 0xE0, 0x39, 0xC0, 0xC3, 0x03, 0x0E,
- 0x0C, 0x18, 0xFC, 0x7F, 0xF0, 0xF0, 0xFF, 0x0F, 0xF0, 0x18, 0x01, 0x80,
- 0x18, 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x31, 0x83, 0x18, 0x31, 0x83,
- 0xFF, 0xFF, 0xFF, 0xF0, 0x3F, 0xC0, 0xF7, 0x87, 0x9E, 0x1E, 0x7C, 0xF9,
- 0xB3, 0xE6, 0xFD, 0x99, 0xF6, 0x67, 0x99, 0x8E, 0x66, 0x31, 0x98, 0x06,
- 0xFC, 0xFF, 0xF3, 0xF0, 0xF1, 0xFF, 0xCF, 0xCF, 0x0C, 0x78, 0x63, 0xE3,
- 0x1B, 0x18, 0xDC, 0xC6, 0x76, 0x31, 0xB1, 0x8F, 0x8C, 0x3C, 0x61, 0xE7,
- 0xE7, 0x3F, 0x18, 0x0F, 0x03, 0xFC, 0x70, 0xE6, 0x06, 0xE0, 0x7C, 0x03,
- 0xC0, 0x3C, 0x03, 0xC0, 0x3E, 0x07, 0x60, 0x67, 0x0E, 0x3F, 0xC0, 0xF0,
- 0xFF, 0x8F, 0xFE, 0x30, 0x73, 0x03, 0x30, 0x33, 0x03, 0x30, 0x73, 0xFE,
- 0x3F, 0x83, 0x00, 0x30, 0x03, 0x00, 0xFF, 0x0F, 0xF0, 0x0F, 0x03, 0xFC,
- 0x70, 0xE6, 0x06, 0xE0, 0x7C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3E, 0x07,
- 0x60, 0x67, 0x0E, 0x3F, 0xC1, 0xF0, 0x18, 0x33, 0xFF, 0x3F, 0xE0, 0xFF,
- 0x83, 0xFF, 0x83, 0x07, 0x0C, 0x0C, 0x30, 0x30, 0xC1, 0xC3, 0xFE, 0x0F,
- 0xF0, 0x31, 0xE0, 0xC3, 0x83, 0x07, 0x0C, 0x0C, 0xFE, 0x3F, 0xF8, 0x70,
- 0x3F, 0xDF, 0xFE, 0x1F, 0x03, 0xC0, 0xF8, 0x07, 0xE0, 0x7E, 0x01, 0xF0,
- 0x3C, 0x0F, 0x87, 0xFF, 0xBF, 0xC0, 0xFF, 0xFF, 0xFF, 0xC6, 0x3C, 0x63,
- 0xC6, 0x3C, 0x63, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x3F, 0xC3, 0xFC, 0xFF, 0xFF, 0xFF, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06,
- 0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60, 0x63, 0x9C, 0x1F, 0xC0, 0xF0,
- 0xFC, 0x3F, 0xFC, 0x3F, 0x30, 0x0C, 0x38, 0x1C, 0x18, 0x18, 0x1C, 0x38,
- 0x1C, 0x38, 0x0E, 0x70, 0x0E, 0x70, 0x0F, 0x60, 0x07, 0xE0, 0x07, 0xE0,
- 0x03, 0xC0, 0x03, 0xC0, 0xFC, 0xFF, 0xF3, 0xF6, 0x01, 0xDC, 0xC6, 0x77,
- 0x99, 0xDE, 0x67, 0x79, 0x8D, 0xFE, 0x3F, 0xF8, 0xF3, 0xE3, 0xCF, 0x8F,
- 0x3C, 0x38, 0x70, 0xE1, 0xC0, 0xF8, 0xFB, 0xE3, 0xE3, 0x86, 0x0F, 0x38,
- 0x1F, 0xC0, 0x3E, 0x00, 0x70, 0x03, 0xE0, 0x0F, 0x80, 0x77, 0x03, 0x8E,
- 0x1E, 0x1C, 0xFC, 0xFF, 0xF3, 0xF0, 0xF9, 0xFF, 0x9F, 0x30, 0xC3, 0x9C,
- 0x19, 0x81, 0xF8, 0x0F, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x3F, 0xC3, 0xFC, 0xFF, 0xBF, 0xEC, 0x3B, 0x0C, 0xC6, 0x33, 0x80, 0xC0,
- 0x60, 0x38, 0xCC, 0x36, 0x0F, 0x03, 0xFF, 0xFF, 0xF0, 0xFF, 0xF1, 0x8C,
- 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC7, 0xFE, 0x40, 0x30, 0x0E,
- 0x01, 0x80, 0x70, 0x0C, 0x03, 0x80, 0x60, 0x1C, 0x03, 0x00, 0xE0, 0x18,
- 0x07, 0x00, 0xC0, 0x38, 0x0E, 0x01, 0xC0, 0x70, 0x0C, 0x01, 0xFF, 0xC6,
- 0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x1F, 0xFE, 0x04, 0x03,
- 0x01, 0xE0, 0xFC, 0x7B, 0x9C, 0x7E, 0x1F, 0x03, 0xFF, 0xFF, 0xFF, 0xF0,
- 0xCE, 0x73, 0x3F, 0x07, 0xF8, 0x00, 0xC0, 0x0C, 0x1F, 0xC7, 0xFC, 0x60,
- 0xCC, 0x0C, 0xC1, 0xCF, 0xFF, 0x3F, 0xF0, 0xF0, 0x07, 0x80, 0x0C, 0x00,
- 0x60, 0x03, 0x7C, 0x1F, 0xF8, 0xF1, 0xC7, 0x07, 0x30, 0x19, 0x80, 0xCC,
- 0x06, 0x60, 0x73, 0xC7, 0x7F, 0xFB, 0xDF, 0x00, 0x1F, 0xB3, 0xFF, 0x70,
- 0xFE, 0x07, 0xC0, 0x3C, 0x00, 0xC0, 0x0C, 0x00, 0x70, 0x77, 0xFF, 0x1F,
- 0xC0, 0x01, 0xE0, 0x0F, 0x00, 0x18, 0x00, 0xC1, 0xF6, 0x3F, 0xF1, 0xC7,
- 0x9C, 0x1C, 0xC0, 0x66, 0x03, 0x30, 0x19, 0x81, 0xC7, 0x1E, 0x3F, 0xFC,
- 0x7D, 0xE0, 0x1F, 0x83, 0xFC, 0x70, 0xEE, 0x07, 0xFF, 0xFF, 0xFF, 0xE0,
- 0x0E, 0x00, 0x70, 0x73, 0xFF, 0x1F, 0xC0, 0x07, 0xC3, 0xFC, 0x60, 0x0C,
- 0x0F, 0xFD, 0xFF, 0x86, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01,
- 0x81, 0xFF, 0xBF, 0xF0, 0x1F, 0x79, 0xFF, 0xDC, 0x79, 0x81, 0xCC, 0x06,
- 0x60, 0x33, 0x01, 0x9C, 0x1C, 0x71, 0xE1, 0xFF, 0x07, 0xD8, 0x00, 0xC0,
- 0x06, 0x00, 0x70, 0x7F, 0x03, 0xF0, 0xF0, 0x03, 0xC0, 0x03, 0x00, 0x0C,
- 0x00, 0x37, 0xC0, 0xFF, 0x83, 0xC7, 0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3,
- 0x03, 0x0C, 0x0C, 0x30, 0x33, 0xF3, 0xFF, 0xCF, 0xC0, 0x06, 0x00, 0xC0,
- 0x00, 0x3F, 0x07, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18,
- 0x03, 0x0F, 0xFF, 0xFF, 0xC0, 0x06, 0x06, 0x00, 0xFF, 0xFF, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x07, 0xFE, 0xFC,
- 0xF0, 0x07, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x3F, 0x19, 0xF8, 0xDE, 0x07,
- 0xE0, 0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x6F, 0x03, 0x1C, 0x78, 0xFF, 0xC7,
- 0xE0, 0x7E, 0x0F, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30,
- 0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x61, 0xFF, 0xFF, 0xF8, 0xFE, 0xF1,
- 0xFF, 0xF1, 0xCE, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31,
- 0x8C, 0x63, 0x19, 0xF7, 0xBF, 0xEF, 0x78, 0x77, 0xC1, 0xFF, 0x83, 0xC7,
- 0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3, 0x03, 0x0C, 0x0C, 0x30, 0x33, 0xF1,
- 0xFF, 0xC7, 0xC0, 0x1F, 0x83, 0xFC, 0x70, 0xEE, 0x07, 0xC0, 0x3C, 0x03,
- 0xC0, 0x3E, 0x07, 0x70, 0xE3, 0xFC, 0x1F, 0x80, 0xF7, 0xE3, 0xFF, 0xC3,
- 0xC3, 0x8E, 0x07, 0x30, 0x0C, 0xC0, 0x33, 0x00, 0xCE, 0x07, 0x3C, 0x38,
- 0xFF, 0xC3, 0x7E, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x0F, 0xE0, 0x3F, 0x80,
- 0x1F, 0xBC, 0xFF, 0xF7, 0x0F, 0x38, 0x1C, 0xC0, 0x33, 0x00, 0xCC, 0x03,
- 0x38, 0x1C, 0x70, 0xF0, 0xFF, 0xC1, 0xFB, 0x00, 0x0C, 0x00, 0x30, 0x00,
- 0xC0, 0x1F, 0xC0, 0x7F, 0x79, 0xE7, 0xFF, 0x1F, 0x31, 0xC0, 0x18, 0x01,
- 0x80, 0x18, 0x01, 0x80, 0x18, 0x0F, 0xFC, 0xFF, 0xC0, 0x3F, 0x9F, 0xFE,
- 0x1F, 0x82, 0xFE, 0x1F, 0xE0, 0xFF, 0x03, 0xE0, 0xFF, 0xFF, 0xF0, 0x30,
- 0x06, 0x00, 0xC0, 0x7F, 0xEF, 0xFC, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06,
- 0x00, 0xC0, 0x18, 0x71, 0xFE, 0x1F, 0x00, 0xF1, 0xF7, 0x8F, 0x8C, 0x0C,
- 0x60, 0x63, 0x03, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x38, 0xF0, 0xFF, 0xC3,
- 0xEE, 0xFC, 0xFF, 0xF3, 0xF3, 0x87, 0x0E, 0x1C, 0x1C, 0x60, 0x73, 0x80,
- 0xEC, 0x03, 0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xF8, 0x7F, 0xE1,
- 0xF7, 0x39, 0x8C, 0xE6, 0x37, 0xB0, 0xFF, 0xC3, 0xFF, 0x07, 0xBC, 0x1C,
- 0xF0, 0x73, 0x81, 0x86, 0x00, 0x7C, 0xF9, 0xF3, 0xE3, 0xCF, 0x07, 0xF8,
- 0x0F, 0xC0, 0x1E, 0x00, 0xFC, 0x07, 0x38, 0x38, 0x73, 0xF3, 0xFF, 0xCF,
- 0xC0, 0xF9, 0xFF, 0x9F, 0x70, 0xE3, 0x0C, 0x39, 0xC1, 0x98, 0x19, 0x81,
- 0xF8, 0x0F, 0x00, 0xF0, 0x06, 0x00, 0x60, 0x0E, 0x00, 0xC0, 0xFF, 0x0F,
- 0xF0, 0x7F, 0xCF, 0xF9, 0x8E, 0x33, 0x80, 0x70, 0x1C, 0x07, 0x01, 0xC6,
- 0x70, 0xFF, 0xFF, 0xFF, 0x80, 0x0E, 0x3C, 0x60, 0xC1, 0x83, 0x06, 0x0C,
- 0x39, 0xE3, 0xC0, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x3C, 0x38, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF0, 0xE1, 0xC0, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x3C,
- 0x79, 0x83, 0x06, 0x0C, 0x18, 0x31, 0xE3, 0x80, 0x3C, 0x37, 0xE7, 0x67,
- 0xE6, 0x1C };
-
-const GFXglyph FreeMonoBold12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 14, 0, 1 }, // 0x20 ' '
- { 0, 4, 15, 14, 5, -14 }, // 0x21 '!'
- { 8, 8, 7, 14, 3, -13 }, // 0x22 '"'
- { 15, 11, 18, 14, 2, -15 }, // 0x23 '#'
- { 40, 10, 20, 14, 2, -16 }, // 0x24 '$'
- { 65, 10, 15, 14, 2, -14 }, // 0x25 '%'
- { 84, 10, 13, 14, 2, -12 }, // 0x26 '&'
- { 101, 3, 7, 14, 5, -13 }, // 0x27 '''
- { 104, 5, 19, 14, 6, -14 }, // 0x28 '('
- { 116, 5, 19, 14, 3, -14 }, // 0x29 ')'
- { 128, 10, 10, 14, 2, -14 }, // 0x2A '*'
- { 141, 12, 13, 14, 1, -12 }, // 0x2B '+'
- { 161, 5, 7, 14, 4, -2 }, // 0x2C ','
- { 166, 12, 2, 14, 1, -7 }, // 0x2D '-'
- { 169, 3, 3, 14, 5, -2 }, // 0x2E '.'
- { 171, 10, 20, 14, 2, -16 }, // 0x2F '/'
- { 196, 10, 15, 14, 2, -14 }, // 0x30 '0'
- { 215, 10, 15, 14, 2, -14 }, // 0x31 '1'
- { 234, 10, 15, 14, 2, -14 }, // 0x32 '2'
- { 253, 11, 15, 14, 1, -14 }, // 0x33 '3'
- { 274, 9, 14, 14, 2, -13 }, // 0x34 '4'
- { 290, 10, 15, 14, 2, -14 }, // 0x35 '5'
- { 309, 10, 15, 14, 2, -14 }, // 0x36 '6'
- { 328, 10, 15, 14, 2, -14 }, // 0x37 '7'
- { 347, 10, 15, 14, 2, -14 }, // 0x38 '8'
- { 366, 10, 15, 14, 3, -14 }, // 0x39 '9'
- { 385, 3, 11, 14, 5, -10 }, // 0x3A ':'
- { 390, 4, 15, 14, 4, -10 }, // 0x3B ';'
- { 398, 12, 11, 14, 1, -11 }, // 0x3C '<'
- { 415, 12, 7, 14, 1, -9 }, // 0x3D '='
- { 426, 12, 11, 14, 1, -11 }, // 0x3E '>'
- { 443, 9, 14, 14, 3, -13 }, // 0x3F '?'
- { 459, 11, 19, 14, 2, -14 }, // 0x40 '@'
- { 486, 15, 14, 14, -1, -13 }, // 0x41 'A'
- { 513, 13, 14, 14, 0, -13 }, // 0x42 'B'
- { 536, 12, 14, 14, 1, -13 }, // 0x43 'C'
- { 557, 12, 14, 14, 1, -13 }, // 0x44 'D'
- { 578, 13, 14, 14, 0, -13 }, // 0x45 'E'
- { 601, 13, 14, 14, 0, -13 }, // 0x46 'F'
- { 624, 13, 14, 14, 1, -13 }, // 0x47 'G'
- { 647, 14, 14, 14, 0, -13 }, // 0x48 'H'
- { 672, 10, 14, 14, 2, -13 }, // 0x49 'I'
- { 690, 13, 14, 14, 1, -13 }, // 0x4A 'J'
- { 713, 14, 14, 14, 0, -13 }, // 0x4B 'K'
- { 738, 12, 14, 14, 1, -13 }, // 0x4C 'L'
- { 759, 14, 14, 14, 0, -13 }, // 0x4D 'M'
- { 784, 13, 14, 14, 0, -13 }, // 0x4E 'N'
- { 807, 12, 14, 14, 1, -13 }, // 0x4F 'O'
- { 828, 12, 14, 14, 0, -13 }, // 0x50 'P'
- { 849, 12, 17, 14, 1, -13 }, // 0x51 'Q'
- { 875, 14, 14, 14, 0, -13 }, // 0x52 'R'
- { 900, 10, 14, 14, 2, -13 }, // 0x53 'S'
- { 918, 12, 14, 14, 1, -13 }, // 0x54 'T'
- { 939, 12, 14, 14, 1, -13 }, // 0x55 'U'
- { 960, 16, 14, 14, -1, -13 }, // 0x56 'V'
- { 988, 14, 14, 14, 0, -13 }, // 0x57 'W'
- { 1013, 14, 14, 14, 0, -13 }, // 0x58 'X'
- { 1038, 12, 14, 14, 1, -13 }, // 0x59 'Y'
- { 1059, 10, 14, 14, 2, -13 }, // 0x5A 'Z'
- { 1077, 5, 19, 14, 6, -14 }, // 0x5B '['
- { 1089, 10, 20, 14, 2, -16 }, // 0x5C '\'
- { 1114, 5, 19, 14, 3, -14 }, // 0x5D ']'
- { 1126, 10, 8, 14, 2, -15 }, // 0x5E '^'
- { 1136, 14, 2, 14, 0, 4 }, // 0x5F '_'
- { 1140, 4, 4, 14, 4, -15 }, // 0x60 '`'
- { 1142, 12, 11, 14, 1, -10 }, // 0x61 'a'
- { 1159, 13, 15, 14, 0, -14 }, // 0x62 'b'
- { 1184, 12, 11, 14, 1, -10 }, // 0x63 'c'
- { 1201, 13, 15, 14, 1, -14 }, // 0x64 'd'
- { 1226, 12, 11, 14, 1, -10 }, // 0x65 'e'
- { 1243, 11, 15, 14, 2, -14 }, // 0x66 'f'
- { 1264, 13, 16, 14, 1, -10 }, // 0x67 'g'
- { 1290, 14, 15, 14, 0, -14 }, // 0x68 'h'
- { 1317, 11, 14, 14, 1, -13 }, // 0x69 'i'
- { 1337, 8, 19, 15, 3, -13 }, // 0x6A 'j'
- { 1356, 13, 15, 14, 1, -14 }, // 0x6B 'k'
- { 1381, 11, 15, 14, 1, -14 }, // 0x6C 'l'
- { 1402, 15, 11, 14, 0, -10 }, // 0x6D 'm'
- { 1423, 14, 11, 14, 0, -10 }, // 0x6E 'n'
- { 1443, 12, 11, 14, 1, -10 }, // 0x6F 'o'
- { 1460, 14, 16, 14, 0, -10 }, // 0x70 'p'
- { 1488, 14, 16, 14, 0, -10 }, // 0x71 'q'
- { 1516, 12, 11, 14, 1, -10 }, // 0x72 'r'
- { 1533, 10, 11, 14, 2, -10 }, // 0x73 's'
- { 1547, 11, 14, 14, 1, -13 }, // 0x74 't'
- { 1567, 13, 11, 14, 0, -10 }, // 0x75 'u'
- { 1585, 14, 11, 14, 0, -10 }, // 0x76 'v'
- { 1605, 14, 11, 14, 0, -10 }, // 0x77 'w'
- { 1625, 14, 11, 14, 0, -10 }, // 0x78 'x'
- { 1645, 12, 16, 14, 1, -10 }, // 0x79 'y'
- { 1669, 11, 11, 14, 1, -10 }, // 0x7A 'z'
- { 1685, 7, 19, 14, 3, -14 }, // 0x7B '{'
- { 1702, 2, 19, 14, 6, -14 }, // 0x7C '|'
- { 1707, 7, 19, 14, 4, -14 }, // 0x7D '}'
- { 1724, 12, 4, 14, 1, -7 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBold12pt7b PROGMEM = {
- (uint8_t *)FreeMonoBold12pt7bBitmaps,
- (GFXglyph *)FreeMonoBold12pt7bGlyphs,
- 0x20, 0x7E, 24 };
-
-// Approx. 2402 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold18pt7b.h
deleted file mode 100644
index 36e0be0..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold18pt7b.h
+++ /dev/null
@@ -1,423 +0,0 @@
-const uint8_t FreeMonoBold18pt7bBitmaps[] PROGMEM = {
- 0x77, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0x9C, 0xE7, 0x39, 0xC4, 0x03, 0xBF,
- 0xFF, 0xB8, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1E, 0xC1, 0x98, 0x33,
- 0x06, 0x60, 0xCC, 0x18, 0x0E, 0x1C, 0x0F, 0x3C, 0x1F, 0x3C, 0x1E, 0x3C,
- 0x1E, 0x3C, 0x1E, 0x78, 0x1E, 0x78, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFE, 0x1E, 0x78, 0x1E, 0x78, 0x1E, 0x78, 0x7F, 0xFE, 0x7F, 0xFE,
- 0x7F, 0xFE, 0x7F, 0xFE, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0xF0,
- 0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x03, 0x00, 0x1E, 0x00, 0x78, 0x01,
- 0xE0, 0x1F, 0xF1, 0xFF, 0xE7, 0xFF, 0xBE, 0x1E, 0xF0, 0x3B, 0xC0, 0xCF,
- 0xE0, 0x3F, 0xF8, 0x7F, 0xF0, 0x7F, 0xE0, 0x1F, 0xF0, 0x0F, 0xE0, 0x3F,
- 0x80, 0xFF, 0x87, 0xFF, 0xFE, 0xFF, 0xF3, 0x7F, 0x80, 0x78, 0x01, 0xE0,
- 0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xC0, 0x1E, 0x00, 0xFF, 0x03, 0x86,
- 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x38, 0x70, 0x3F, 0xC2, 0x1E, 0x3E,
- 0x03, 0xF8, 0x3F, 0x83, 0xF8, 0x0F, 0x8F, 0x18, 0x7F, 0x01, 0xC7, 0x03,
- 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x1C, 0x70, 0x1F, 0xC0, 0x0F, 0x00, 0x03,
- 0xD0, 0x1F, 0xF0, 0x7F, 0xE1, 0xFF, 0xC3, 0xE6, 0x07, 0x80, 0x0F, 0x00,
- 0x0F, 0x00, 0x1F, 0x00, 0x3E, 0x00, 0xFE, 0x03, 0xFE, 0xFF, 0xBD, 0xFE,
- 0x3F, 0xFC, 0x3F, 0x7C, 0x7C, 0xFF, 0xFE, 0xFF, 0xFC, 0xFF, 0xF8, 0x7E,
- 0xF0, 0xFF, 0xFF, 0xF6, 0x66, 0x66, 0x07, 0x0F, 0x1F, 0x1E, 0x3E, 0x3C,
- 0x78, 0x78, 0x78, 0x70, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
- 0x78, 0x78, 0x78, 0x3C, 0x3C, 0x1E, 0x1F, 0x0F, 0x07, 0xE0, 0xF0, 0xF8,
- 0x78, 0x7C, 0x3C, 0x3E, 0x1E, 0x1E, 0x1E, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x0F, 0x0F, 0x0E, 0x1E, 0x1E, 0x1E, 0x3C, 0x3C, 0x78, 0xF8, 0xF0, 0xE0,
- 0x01, 0x80, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x7F, 0xFE, 0x1F, 0xF8, 0x07, 0xE0, 0x0F, 0xF0, 0x1F, 0xF8,
- 0x1E, 0x78, 0x1C, 0x38, 0x18, 0x18, 0x01, 0xC0, 0x03, 0xC0, 0x03, 0xC0,
- 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0,
- 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0x80, 0x3E, 0x78, 0xF3, 0xC7,
- 0x8E, 0x1C, 0x70, 0xE1, 0x80, 0x7F, 0xFF, 0xDF, 0xFF, 0xF9, 0xFF, 0xFF,
- 0x3F, 0xFF, 0xE0, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x0E, 0x00, 0x3C, 0x00,
- 0x78, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x1E, 0x00, 0x38, 0x00, 0xF0,
- 0x01, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x3C, 0x00, 0x78, 0x01, 0xE0, 0x03,
- 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x78, 0x00, 0xF0, 0x03, 0xC0, 0x07, 0x80,
- 0x1E, 0x00, 0x3C, 0x00, 0x70, 0x01, 0xE0, 0x03, 0x80, 0x03, 0x00, 0x00,
- 0x07, 0xE0, 0x1F, 0xF8, 0x3F, 0xFC, 0x3F, 0xFC, 0x7C, 0x3E, 0x78, 0x1E,
- 0xF8, 0x1F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F,
- 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF8, 0x1F, 0x78, 0x1E,
- 0x7C, 0x3E, 0x3F, 0xFC, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0, 0x07, 0xC0,
- 0x1F, 0x80, 0xFF, 0x03, 0xFE, 0x0F, 0xBC, 0x0C, 0x78, 0x00, 0xF0, 0x01,
- 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78,
- 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x81, 0xFF, 0xFB, 0xFF, 0xF7,
- 0xFF, 0xE7, 0xFF, 0x80, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE3, 0xFF, 0xEF,
- 0x87, 0xDE, 0x07, 0xF8, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x01,
- 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00,
- 0x78, 0x03, 0xE0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80,
- 0x0F, 0xC0, 0x7F, 0xF0, 0xFF, 0xF8, 0xFF, 0xFC, 0x70, 0x3E, 0x00, 0x1E,
- 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x3C, 0x03, 0xFC, 0x03, 0xF0, 0x03, 0xF0,
- 0x03, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,
- 0xE0, 0x3F, 0xFF, 0xFE, 0xFF, 0xFC, 0x7F, 0xF8, 0x1F, 0xE0, 0x00, 0xF8,
- 0x03, 0xF0, 0x07, 0xE0, 0x1F, 0xC0, 0x77, 0x80, 0xEF, 0x03, 0x9E, 0x0F,
- 0x3C, 0x1C, 0x78, 0x70, 0xF1, 0xE1, 0xE3, 0x83, 0xCF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x78, 0x07, 0xFC, 0x0F, 0xF8, 0x1F, 0xF0,
- 0x1F, 0xC0, 0x3F, 0xFC, 0x1F, 0xFE, 0x0F, 0xFF, 0x07, 0xFF, 0x83, 0xC0,
- 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x7B, 0xE0, 0x3F, 0xFC, 0x1F, 0xFF, 0x0F,
- 0xFF, 0xC3, 0x83, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0F,
- 0x00, 0x0F, 0xB8, 0x0F, 0xBF, 0xFF, 0xCF, 0xFF, 0xC3, 0xFF, 0xC0, 0x7F,
- 0x80, 0x00, 0xFC, 0x07, 0xFC, 0x3F, 0xF8, 0xFF, 0xF1, 0xF8, 0x07, 0xC0,
- 0x1F, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xE7, 0xC3, 0xDF, 0xC7, 0x7F, 0xCF,
- 0xFF, 0xDF, 0x8F, 0xFC, 0x07, 0xF0, 0x0F, 0xF0, 0x1F, 0xE0, 0x3D, 0xE0,
- 0xFB, 0xFF, 0xE3, 0xFF, 0xC3, 0xFF, 0x01, 0xF8, 0x00, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x01, 0xE0, 0x03, 0x80, 0x0F, 0x00, 0x1E,
- 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00,
- 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38,
- 0x00, 0x70, 0x00, 0x07, 0xC0, 0x3F, 0xE0, 0xFF, 0xE3, 0xFF, 0xEF, 0x83,
- 0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x0F, 0xF0, 0x1E, 0xF0, 0x78, 0xFF, 0xE0,
- 0xFF, 0x81, 0xFF, 0x0F, 0xFF, 0x9E, 0x0F, 0x78, 0x0F, 0xF0, 0x1F, 0xE0,
- 0x3F, 0xE0, 0xFB, 0xFF, 0xE7, 0xFF, 0xC7, 0xFF, 0x03, 0xF8, 0x00, 0x0F,
- 0xC0, 0x3F, 0xE0, 0xFF, 0xE3, 0xFF, 0xEF, 0xC3, 0xDF, 0x03, 0xBC, 0x07,
- 0xF8, 0x0F, 0xF0, 0x1F, 0xF0, 0x3D, 0xF1, 0xFB, 0xFF, 0xF3, 0xFE, 0xE3,
- 0xFB, 0xC3, 0xE7, 0x80, 0x1E, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xE7, 0xFF,
- 0x8F, 0xFE, 0x1F, 0xF0, 0x1F, 0x80, 0x00, 0x77, 0xFF, 0xF7, 0x00, 0x00,
- 0x00, 0x00, 0xEF, 0xFF, 0xEE, 0x1C, 0x7C, 0xF9, 0xF1, 0xC0, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xF3, 0xC7, 0x8E, 0x3C, 0x70, 0xE1, 0x87, 0x0C, 0x00,
- 0x00, 0x00, 0x00, 0x80, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0xFE,
- 0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x07, 0xF0, 0x00,
- 0x7F, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xF0, 0x00, 0x7C, 0x00,
- 0x07, 0x7F, 0xFF, 0xDF, 0xFF, 0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE0, 0x00,
- 0x00, 0x00, 0x00, 0x1F, 0xFF, 0xF7, 0xFF, 0xFE, 0x7F, 0xFF, 0xCF, 0xFF,
- 0xF8, 0x00, 0x00, 0x3C, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0xC0,
- 0x01, 0xFC, 0x00, 0x1F, 0xC0, 0x01, 0xFC, 0x00, 0x3F, 0x80, 0x3F, 0x80,
- 0x3F, 0x80, 0x3F, 0x80, 0x3F, 0x80, 0x3F, 0x80, 0x0F, 0x80, 0x03, 0x80,
- 0x00, 0x1F, 0xC0, 0xFF, 0xE3, 0xFF, 0xF7, 0xFF, 0xEF, 0x07, 0xFE, 0x03,
- 0xDC, 0x07, 0x80, 0x0F, 0x00, 0x7C, 0x03, 0xF8, 0x1F, 0xC0, 0x1E, 0x00,
- 0x30, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x1F, 0x00, 0x3E,
- 0x00, 0x7C, 0x00, 0x70, 0x00, 0x07, 0xE0, 0x1F, 0xE0, 0x7F, 0xE1, 0xE1,
- 0xC7, 0x83, 0xCE, 0x03, 0xBC, 0x07, 0x70, 0x0E, 0xE0, 0x7D, 0xC3, 0xFB,
- 0x8F, 0xF7, 0x3C, 0xEE, 0x71, 0xDC, 0xE3, 0xB9, 0xC7, 0x73, 0xCE, 0xE3,
- 0xFF, 0xC3, 0xFF, 0x83, 0xFF, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x1E, 0x02,
- 0x1E, 0x1E, 0x3F, 0xFC, 0x1F, 0xF0, 0x1F, 0x80, 0x0F, 0xF8, 0x00, 0x7F,
- 0xF0, 0x01, 0xFF, 0xC0, 0x03, 0xFF, 0x00, 0x01, 0xFE, 0x00, 0x07, 0xF8,
- 0x00, 0x1C, 0xF0, 0x00, 0xF3, 0xC0, 0x03, 0xCF, 0x00, 0x1E, 0x1E, 0x00,
- 0x78, 0x78, 0x03, 0xC0, 0xF0, 0x0F, 0xFF, 0xC0, 0x3F, 0xFF, 0x01, 0xFF,
- 0xFE, 0x07, 0xFF, 0xF8, 0x3C, 0x00, 0xF3, 0xFC, 0x1F, 0xEF, 0xF8, 0x7F,
- 0xFF, 0xE1, 0xFF, 0x7F, 0x03, 0xF8, 0x7F, 0xFC, 0x0F, 0xFF, 0xF0, 0xFF,
- 0xFF, 0x8F, 0xFF, 0xF8, 0x3C, 0x07, 0xC3, 0xC0, 0x3C, 0x3C, 0x03, 0xC3,
- 0xC0, 0x7C, 0x3F, 0xFF, 0x83, 0xFF, 0xF0, 0x3F, 0xFF, 0x83, 0xFF, 0xFE,
- 0x3C, 0x03, 0xE3, 0xC0, 0x1F, 0x3C, 0x00, 0xF3, 0xC0, 0x0F, 0x3C, 0x01,
- 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xEF, 0xFF, 0xFC, 0x7F, 0xFF, 0x00, 0x01,
- 0xF8, 0xC1, 0xFF, 0xFC, 0x7F, 0xFF, 0x9F, 0xFF, 0xF7, 0xE0, 0x7E, 0xF8,
- 0x07, 0xFE, 0x00, 0x7F, 0x80, 0x0E, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,
- 0x00, 0x78, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0,
- 0x07, 0x7F, 0x03, 0xE7, 0xFF, 0xFC, 0x7F, 0xFF, 0x03, 0xFF, 0xC0, 0x1F,
- 0xE0, 0xFF, 0xF0, 0x3F, 0xFF, 0x0F, 0xFF, 0xE3, 0xFF, 0xFC, 0x78, 0x1F,
- 0x9E, 0x03, 0xE7, 0x80, 0x79, 0xE0, 0x0F, 0x78, 0x03, 0xDE, 0x00, 0xF7,
- 0x80, 0x3D, 0xE0, 0x0F, 0x78, 0x03, 0xDE, 0x00, 0xF7, 0x80, 0x7D, 0xE0,
- 0x1E, 0x78, 0x1F, 0xBF, 0xFF, 0xCF, 0xFF, 0xF3, 0xFF, 0xF0, 0x7F, 0xF0,
- 0x00, 0x7F, 0xFF, 0xDF, 0xFF, 0xFB, 0xFF, 0xFF, 0x7F, 0xFF, 0xE3, 0xC0,
- 0x3C, 0x78, 0x07, 0x8F, 0x1C, 0xF1, 0xE3, 0xCC, 0x3F, 0xF8, 0x07, 0xFF,
- 0x00, 0xFF, 0xE0, 0x1F, 0xFC, 0x03, 0xC7, 0x80, 0x78, 0xF1, 0x8F, 0x0C,
- 0x79, 0xE0, 0x0F, 0x3C, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF7, 0xFF, 0xFE, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF3, 0xC0, 0x1E, 0x78, 0x63, 0xCF, 0x1E, 0x79, 0xE3, 0xC6, 0x3F, 0xF8,
- 0x07, 0xFF, 0x00, 0xFF, 0xE0, 0x1F, 0xFC, 0x03, 0xC7, 0x80, 0x78, 0xE0,
- 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x1F, 0xFC, 0x03, 0xFF, 0x80,
- 0x7F, 0xF0, 0x07, 0xFC, 0x00, 0x01, 0xFC, 0xE0, 0x7F, 0xFE, 0x1F, 0xFF,
- 0xE3, 0xFF, 0xFE, 0x7F, 0x03, 0xE7, 0xC0, 0x1E, 0xF8, 0x00, 0xEF, 0x00,
- 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x03, 0xFE, 0xF0,
- 0x3F, 0xFF, 0x03, 0xFF, 0xF8, 0x3F, 0xF7, 0x80, 0x1E, 0x7E, 0x01, 0xE3,
- 0xFF, 0xFE, 0x1F, 0xFF, 0xE0, 0xFF, 0xF8, 0x01, 0xFE, 0x00, 0x7F, 0x0F,
- 0xE3, 0xFC, 0x7F, 0x9F, 0xE3, 0xFC, 0x7F, 0x1F, 0xC1, 0xE0, 0x3C, 0x0F,
- 0x01, 0xE0, 0x78, 0x0F, 0x03, 0xC0, 0x78, 0x1E, 0x03, 0xC0, 0xFF, 0xFE,
- 0x07, 0xFF, 0xF0, 0x3F, 0xFF, 0x81, 0xFF, 0xFC, 0x0F, 0x01, 0xE0, 0x78,
- 0x0F, 0x03, 0xC0, 0x78, 0x1E, 0x03, 0xC3, 0xFC, 0x7F, 0xBF, 0xE3, 0xFF,
- 0xFF, 0x1F, 0xF7, 0xF0, 0x7F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00,
- 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x83,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xF8, 0x01, 0xFF, 0xE0, 0x3F, 0xFC,
- 0x07, 0xFF, 0x80, 0xFF, 0xF0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,
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- 0x3F, 0xC0, 0x7E, 0x1E, 0x7F, 0x3F, 0xFF, 0xBF, 0xFF, 0xFF, 0xF1, 0xFE,
- 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0F, 0x00, 0x07,
- 0x80, 0x03, 0xC0, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0xFF, 0xE1, 0xFF, 0xE0,
- 0x07, 0xE6, 0x1F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFE, 0x78, 0x1E, 0x78, 0x0E,
- 0x7F, 0xE0, 0x3F, 0xFC, 0x03, 0xFE, 0x60, 0x1F, 0xE0, 0x0F, 0xF8, 0x1F,
- 0xFF, 0xFF, 0xFF, 0xFE, 0x7F, 0xFC, 0x07, 0xE0, 0x0C, 0x00, 0x0F, 0x00,
- 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x07, 0xFF, 0xF3, 0xFF, 0xF9, 0xFF,
- 0xFC, 0xFF, 0xFC, 0x0F, 0x00, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,
- 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E, 0x07, 0x8F, 0xFF, 0xC3, 0xFF,
- 0xC1, 0xFF, 0xC0, 0x3F, 0x80, 0xFC, 0x1F, 0xBF, 0x0F, 0xEF, 0xC3, 0xFB,
- 0xF0, 0xFE, 0x3C, 0x07, 0x8F, 0x01, 0xE3, 0xC0, 0x78, 0xF0, 0x1E, 0x3C,
- 0x07, 0x8F, 0x01, 0xE3, 0xC0, 0x78, 0xF8, 0x7E, 0x3F, 0xFF, 0xC7, 0xFF,
- 0xF0, 0xFF, 0x7C, 0x0F, 0x9E, 0x7F, 0x07, 0xF7, 0xFC, 0x7F, 0xFF, 0xE3,
- 0xFE, 0xFE, 0x0F, 0xE1, 0xE0, 0x3C, 0x0F, 0x01, 0xE0, 0x3C, 0x1E, 0x01,
- 0xE0, 0xF0, 0x07, 0x8F, 0x00, 0x3E, 0x78, 0x00, 0xF7, 0x80, 0x07, 0xFC,
- 0x00, 0x1F, 0xC0, 0x00, 0xFE, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x7E,
- 0x03, 0xF7, 0xF8, 0x3F, 0xFF, 0xC1, 0xFE, 0xFC, 0x07, 0xF3, 0xC7, 0x0F,
- 0x1E, 0x7C, 0xF0, 0x73, 0xE7, 0x83, 0x9F, 0x7C, 0x1F, 0xFF, 0xC0, 0xFF,
- 0xFE, 0x03, 0xF7, 0xF0, 0x1F, 0xBF, 0x80, 0xFC, 0xF8, 0x07, 0xC7, 0xC0,
- 0x1E, 0x3E, 0x00, 0xE0, 0xE0, 0x7E, 0x0F, 0xDF, 0xE3, 0xFF, 0xFC, 0x7F,
- 0xBF, 0x07, 0xE1, 0xF1, 0xF0, 0x1F, 0xFC, 0x01, 0xFF, 0x00, 0x1F, 0xC0,
- 0x07, 0xF8, 0x01, 0xFF, 0xC0, 0x7E, 0xFC, 0x1F, 0x8F, 0xC7, 0xE0, 0xFD,
- 0xFE, 0x3F, 0xFF, 0xC7, 0xFF, 0xF0, 0x7F, 0x7E, 0x0F, 0xDF, 0xE3, 0xFF,
- 0xFC, 0x7F, 0xBF, 0x07, 0xE3, 0xC0, 0x78, 0x3C, 0x0E, 0x07, 0x83, 0xC0,
- 0x78, 0x70, 0x0F, 0x1E, 0x00, 0xE3, 0x80, 0x1E, 0xF0, 0x01, 0xDC, 0x00,
- 0x3F, 0x80, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0x00, 0x01, 0xE0, 0x00,
- 0x38, 0x00, 0x0F, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x01, 0xFF, 0xE0, 0x1F,
- 0xF8, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF9, 0xC7,
- 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x78, 0x03, 0xC0, 0x1E, 0x07, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x81, 0xF0, 0xFC, 0x7E, 0x1F,
- 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0xF8, 0xFC, 0x3E, 0x0F,
- 0x83, 0xF0, 0x3E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xF0, 0x7E,
- 0x0F, 0xC3, 0xF0, 0x38, 0x6F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x70, 0x3E, 0x0F, 0xC1, 0xF8, 0x3E,
- 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x7C, 0x0F, 0xC1, 0xF0,
- 0x7C, 0x3F, 0x1F, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x83, 0xE1, 0xF8,
- 0xFC, 0x3F, 0x07, 0x00, 0x1E, 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xDF, 0xFC,
- 0xFF, 0x3F, 0xFB, 0x0F, 0xF8, 0x03, 0xF8, 0x00, 0x78 };
-
-const GFXglyph FreeMonoBold18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 21, 0, 1 }, // 0x20 ' '
- { 0, 5, 22, 21, 8, -21 }, // 0x21 '!'
- { 14, 11, 10, 21, 5, -20 }, // 0x22 '"'
- { 28, 16, 25, 21, 3, -22 }, // 0x23 '#'
- { 78, 14, 28, 21, 4, -23 }, // 0x24 '$'
- { 127, 15, 21, 21, 3, -20 }, // 0x25 '%'
- { 167, 15, 20, 21, 3, -19 }, // 0x26 '&'
- { 205, 4, 10, 21, 8, -20 }, // 0x27 '''
- { 210, 8, 27, 21, 9, -21 }, // 0x28 '('
- { 237, 8, 27, 21, 4, -21 }, // 0x29 ')'
- { 264, 16, 15, 21, 3, -21 }, // 0x2A '*'
- { 294, 16, 19, 21, 3, -18 }, // 0x2B '+'
- { 332, 7, 10, 21, 5, -3 }, // 0x2C ','
- { 341, 19, 4, 21, 1, -11 }, // 0x2D '-'
- { 351, 5, 5, 21, 8, -4 }, // 0x2E '.'
- { 355, 15, 28, 21, 3, -23 }, // 0x2F '/'
- { 408, 16, 23, 21, 3, -22 }, // 0x30 '0'
- { 454, 15, 22, 21, 3, -21 }, // 0x31 '1'
- { 496, 15, 23, 21, 3, -22 }, // 0x32 '2'
- { 540, 16, 23, 21, 3, -22 }, // 0x33 '3'
- { 586, 15, 21, 21, 3, -20 }, // 0x34 '4'
- { 626, 17, 22, 21, 2, -21 }, // 0x35 '5'
- { 673, 15, 23, 21, 4, -22 }, // 0x36 '6'
- { 717, 15, 22, 21, 3, -21 }, // 0x37 '7'
- { 759, 15, 23, 21, 3, -22 }, // 0x38 '8'
- { 803, 15, 23, 21, 4, -22 }, // 0x39 '9'
- { 847, 5, 16, 21, 8, -15 }, // 0x3A ':'
- { 857, 7, 22, 21, 5, -15 }, // 0x3B ';'
- { 877, 18, 16, 21, 1, -17 }, // 0x3C '<'
- { 913, 19, 10, 21, 1, -14 }, // 0x3D '='
- { 937, 18, 16, 21, 2, -17 }, // 0x3E '>'
- { 973, 15, 21, 21, 4, -20 }, // 0x3F '?'
- { 1013, 15, 27, 21, 3, -21 }, // 0x40 '@'
- { 1064, 22, 21, 21, -1, -20 }, // 0x41 'A'
- { 1122, 20, 21, 21, 1, -20 }, // 0x42 'B'
- { 1175, 19, 21, 21, 1, -20 }, // 0x43 'C'
- { 1225, 18, 21, 21, 2, -20 }, // 0x44 'D'
- { 1273, 19, 21, 21, 1, -20 }, // 0x45 'E'
- { 1323, 19, 21, 21, 1, -20 }, // 0x46 'F'
- { 1373, 20, 21, 21, 1, -20 }, // 0x47 'G'
- { 1426, 21, 21, 21, 0, -20 }, // 0x48 'H'
- { 1482, 14, 21, 21, 4, -20 }, // 0x49 'I'
- { 1519, 19, 21, 21, 2, -20 }, // 0x4A 'J'
- { 1569, 20, 21, 21, 1, -20 }, // 0x4B 'K'
- { 1622, 18, 21, 21, 2, -20 }, // 0x4C 'L'
- { 1670, 23, 21, 21, -1, -20 }, // 0x4D 'M'
- { 1731, 20, 21, 21, 1, -20 }, // 0x4E 'N'
- { 1784, 20, 21, 21, 1, -20 }, // 0x4F 'O'
- { 1837, 18, 21, 21, 1, -20 }, // 0x50 'P'
- { 1885, 20, 26, 21, 1, -20 }, // 0x51 'Q'
- { 1950, 21, 21, 21, 0, -20 }, // 0x52 'R'
- { 2006, 17, 21, 21, 2, -20 }, // 0x53 'S'
- { 2051, 19, 21, 21, 1, -20 }, // 0x54 'T'
- { 2101, 21, 21, 21, 0, -20 }, // 0x55 'U'
- { 2157, 23, 21, 21, -1, -20 }, // 0x56 'V'
- { 2218, 21, 21, 21, 0, -20 }, // 0x57 'W'
- { 2274, 19, 21, 21, 1, -20 }, // 0x58 'X'
- { 2324, 20, 21, 21, 1, -20 }, // 0x59 'Y'
- { 2377, 16, 21, 21, 3, -20 }, // 0x5A 'Z'
- { 2419, 8, 27, 21, 9, -21 }, // 0x5B '['
- { 2446, 15, 28, 21, 3, -23 }, // 0x5C '\'
- { 2499, 8, 27, 21, 4, -21 }, // 0x5D ']'
- { 2526, 15, 11, 21, 3, -21 }, // 0x5E '^'
- { 2547, 21, 4, 21, 0, 4 }, // 0x5F '_'
- { 2558, 6, 6, 21, 6, -22 }, // 0x60 '`'
- { 2563, 19, 16, 21, 1, -15 }, // 0x61 'a'
- { 2601, 19, 22, 21, 1, -21 }, // 0x62 'b'
- { 2654, 17, 16, 21, 2, -15 }, // 0x63 'c'
- { 2688, 20, 22, 21, 1, -21 }, // 0x64 'd'
- { 2743, 18, 16, 21, 1, -15 }, // 0x65 'e'
- { 2779, 16, 22, 21, 4, -21 }, // 0x66 'f'
- { 2823, 19, 23, 21, 1, -15 }, // 0x67 'g'
- { 2878, 21, 22, 21, 0, -21 }, // 0x68 'h'
- { 2936, 16, 22, 21, 3, -21 }, // 0x69 'i'
- { 2980, 12, 29, 21, 5, -21 }, // 0x6A 'j'
- { 3024, 18, 22, 21, 2, -21 }, // 0x6B 'k'
- { 3074, 16, 22, 21, 3, -21 }, // 0x6C 'l'
- { 3118, 22, 16, 21, -1, -15 }, // 0x6D 'm'
- { 3162, 20, 16, 21, 0, -15 }, // 0x6E 'n'
- { 3202, 19, 16, 21, 1, -15 }, // 0x6F 'o'
- { 3240, 21, 23, 21, 0, -15 }, // 0x70 'p'
- { 3301, 21, 23, 22, 1, -15 }, // 0x71 'q'
- { 3362, 17, 16, 21, 3, -15 }, // 0x72 'r'
- { 3396, 16, 16, 21, 3, -15 }, // 0x73 's'
- { 3428, 17, 21, 21, 1, -20 }, // 0x74 't'
- { 3473, 18, 16, 21, 1, -15 }, // 0x75 'u'
- { 3509, 21, 16, 21, 0, -15 }, // 0x76 'v'
- { 3551, 21, 16, 21, 0, -15 }, // 0x77 'w'
- { 3593, 19, 16, 21, 1, -15 }, // 0x78 'x'
- { 3631, 19, 23, 21, 1, -15 }, // 0x79 'y'
- { 3686, 14, 16, 21, 3, -15 }, // 0x7A 'z'
- { 3714, 10, 27, 21, 6, -21 }, // 0x7B '{'
- { 3748, 4, 27, 21, 9, -21 }, // 0x7C '|'
- { 3762, 10, 27, 21, 6, -21 }, // 0x7D '}'
- { 3796, 17, 8, 21, 2, -13 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBold18pt7b PROGMEM = {
- (uint8_t *)FreeMonoBold18pt7bBitmaps,
- (GFXglyph *)FreeMonoBold18pt7bGlyphs,
- 0x20, 0x7E, 35 };
-
-// Approx. 4485 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold24pt7b.h
deleted file mode 100644
index aa0dcd0..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold24pt7b.h
+++ /dev/null
@@ -1,672 +0,0 @@
-const uint8_t FreeMonoBold24pt7bBitmaps[] PROGMEM = {
- 0x38, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xF3, 0xE7, 0xCF,
- 0x9F, 0x3E, 0x7C, 0xF9, 0xF3, 0xE3, 0x82, 0x00, 0x00, 0x00, 0x71, 0xF7,
- 0xFF, 0xEF, 0x9E, 0x00, 0xFC, 0x7E, 0xF8, 0x7D, 0xF0, 0xFB, 0xE1, 0xF7,
- 0xC3, 0xEF, 0x87, 0xDF, 0x0F, 0xBE, 0x1F, 0x38, 0x1C, 0x70, 0x38, 0xE0,
- 0x71, 0xC0, 0xE3, 0x81, 0xC7, 0x03, 0x80, 0x01, 0xC1, 0xC0, 0x0F, 0x8F,
- 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0, 0x0F, 0x8F, 0x80,
- 0x7E, 0x3E, 0x01, 0xF0, 0xF8, 0x07, 0xC7, 0xC0, 0x1F, 0x1F, 0x03, 0xFF,
- 0xFF, 0x9F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFD, 0xFF, 0xFF, 0xF3, 0xFF, 0xFF,
- 0x81, 0xF1, 0xF0, 0x07, 0xC7, 0xC0, 0x1F, 0x1F, 0x00, 0x7C, 0x7C, 0x1F,
- 0xFF, 0xFC, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0x9F, 0xFF,
- 0xFC, 0x0F, 0x8F, 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0,
- 0x0F, 0x8F, 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0, 0x0F,
- 0x8F, 0x80, 0x3C, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0,
- 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x1F, 0xFF, 0x07, 0xFF, 0xF1, 0xFF, 0xFE,
- 0x7F, 0xFF, 0xDF, 0xC1, 0xFB, 0xF0, 0x1F, 0x7C, 0x01, 0xEF, 0x80, 0x39,
- 0xF8, 0x00, 0x3F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x03, 0xFF, 0xF0,
- 0x0F, 0xFF, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xC0, 0x07, 0xF8, 0x00, 0xFF,
- 0x80, 0x1F, 0xF8, 0x07, 0xFF, 0x81, 0xFB, 0xFF, 0xFF, 0x7F, 0xFF, 0xCF,
- 0xFF, 0xF1, 0xDF, 0xFC, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00,
- 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x01, 0xC0, 0x00,
- 0x0F, 0x80, 0x00, 0xFF, 0x00, 0x1F, 0xFC, 0x00, 0xF0, 0xE0, 0x0F, 0x07,
- 0x80, 0x70, 0x1C, 0x03, 0x80, 0xE0, 0x1C, 0x07, 0x00, 0xF0, 0x78, 0x03,
- 0xC3, 0x80, 0x1F, 0xFC, 0x00, 0x7F, 0xC1, 0xF0, 0xF8, 0x7F, 0x00, 0x3F,
- 0xF0, 0x0F, 0xFC, 0x03, 0xFF, 0x00, 0xFF, 0xC0, 0x07, 0xE0, 0xF8, 0x38,
- 0x1F, 0xE0, 0x01, 0xFF, 0x80, 0x0F, 0x1E, 0x00, 0xF0, 0x78, 0x07, 0x01,
- 0xC0, 0x38, 0x0E, 0x01, 0xC0, 0x70, 0x0F, 0x07, 0x80, 0x38, 0x78, 0x01,
- 0xFF, 0xC0, 0x07, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0xFC,
- 0x01, 0xFF, 0xE0, 0x1F, 0xFF, 0x00, 0xFF, 0xF8, 0x0F, 0xC7, 0x00, 0x7C,
- 0x10, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00,
- 0x1F, 0x80, 0x00, 0xFE, 0x00, 0x0F, 0xF8, 0x00, 0xFF, 0xC7, 0xCF, 0xFF,
- 0x3F, 0x7E, 0xFF, 0xFF, 0xE7, 0xFF, 0xBE, 0x1F, 0xF9, 0xF0, 0x7F, 0x8F,
- 0x83, 0xFC, 0x7C, 0x0F, 0xE3, 0xF0, 0x7F, 0xCF, 0xFF, 0xFF, 0x7F, 0xFF,
- 0xF9, 0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x0F, 0xE0, 0x00, 0xFD, 0xF7, 0xDF,
- 0x7D, 0xF7, 0xDF, 0x38, 0xE3, 0x8E, 0x38, 0xE0, 0x01, 0x80, 0xF0, 0x7C,
- 0x3F, 0x0F, 0xC7, 0xE1, 0xF8, 0xFC, 0x3E, 0x0F, 0x87, 0xC1, 0xF0, 0x7C,
- 0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F,
- 0x81, 0xF0, 0x7C, 0x1F, 0x07, 0xC0, 0xF8, 0x3E, 0x0F, 0xC1, 0xF0, 0x7E,
- 0x0F, 0x83, 0xF0, 0x7C, 0x1F, 0x03, 0xC0, 0x60, 0x3C, 0x0F, 0x83, 0xF0,
- 0xFC, 0x1F, 0x83, 0xE0, 0xFC, 0x1F, 0x07, 0xC1, 0xF8, 0x3E, 0x0F, 0x83,
- 0xE0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C,
- 0x1E, 0x0F, 0x83, 0xE0, 0xF8, 0x7C, 0x1F, 0x0F, 0xC3, 0xE1, 0xF8, 0x7C,
- 0x3F, 0x0F, 0x83, 0xE0, 0xF0, 0x00, 0x00, 0x70, 0x00, 0x07, 0xC0, 0x00,
- 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x10, 0x7C, 0x11, 0xF3, 0xE7,
- 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0x87, 0xFF, 0xF0, 0x07,
- 0xFC, 0x00, 0x3F, 0xE0, 0x03, 0xFF, 0x80, 0x3F, 0x7E, 0x01, 0xFB, 0xF0,
- 0x1F, 0x8F, 0xC0, 0xF8, 0x3E, 0x03, 0x80, 0xE0, 0x00, 0x38, 0x00, 0x00,
- 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F,
- 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8,
- 0x01, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xDF, 0xFF, 0xFF, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00,
- 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00,
- 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x70, 0x00, 0x1F,
- 0x8F, 0x87, 0xC7, 0xC3, 0xE1, 0xE1, 0xF0, 0xF0, 0x78, 0x38, 0x3C, 0x1C,
- 0x0E, 0x06, 0x00, 0x7F, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE, 0x7D, 0xFF, 0xFF, 0xFF, 0xEF, 0x80,
- 0x00, 0x00, 0x60, 0x00, 0x0F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01,
- 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00,
- 0xF8, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00,
- 0x3E, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0xC0, 0x00, 0xF8, 0x00,
- 0x1F, 0x80, 0x01, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00,
- 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x00,
- 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0,
- 0x00, 0xFC, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x00, 0x00, 0x01,
- 0xFC, 0x00, 0x3F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x83, 0xFF, 0xFE,
- 0x1F, 0x83, 0xF1, 0xF8, 0x0F, 0xCF, 0x80, 0x3E, 0x7C, 0x01, 0xF7, 0xC0,
- 0x07, 0xFE, 0x00, 0x3F, 0xF0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7F,
- 0xE0, 0x03, 0xFF, 0x00, 0x1F, 0xF8, 0x00, 0xFF, 0xC0, 0x07, 0xFE, 0x00,
- 0x3F, 0xF0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7D, 0xF0, 0x07, 0xCF,
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- 0x3F, 0x80, 0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xE0, 0x00, 0x3F, 0xE0, 0x00,
- 0x07, 0xF8, 0x00, 0x07, 0xFF, 0x00, 0x03, 0xFF, 0xE0, 0x01, 0xFF, 0xFE,
- 0x00, 0xFE, 0x1F, 0xC0, 0x7F, 0x03, 0xF8, 0x7F, 0xC0, 0xFF, 0xBF, 0xF8,
- 0x7F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFF, 0x87, 0xFF, 0x7F, 0xC0, 0xFF, 0x80,
- 0x7F, 0x80, 0x7F, 0xBF, 0xF0, 0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0x03,
- 0xFF, 0x7F, 0x80, 0x7F, 0x8F, 0xC0, 0x07, 0x81, 0xF0, 0x03, 0xE0, 0x7E,
- 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xF0, 0x3E, 0x00, 0x7C, 0x0F, 0x80,
- 0x0F, 0x87, 0xC0, 0x03, 0xE1, 0xF0, 0x00, 0x7C, 0xF8, 0x00, 0x1F, 0xFE,
- 0x00, 0x03, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xE0, 0x00, 0x07,
- 0xF0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x80, 0x00,
- 0x07, 0xC0, 0x00, 0x03, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0xFF, 0x80,
- 0x0F, 0xFF, 0xF0, 0x03, 0xFF, 0xFC, 0x00, 0xFF, 0xFF, 0x00, 0x1F, 0xFF,
- 0x80, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF0, 0x3F, 0xBE, 0x0F, 0xC3, 0x83, 0xF0, 0x00, 0xFC, 0x00,
- 0x3F, 0x00, 0x0F, 0xC0, 0x03, 0xF0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F,
- 0xC0, 0x3B, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x78, 0x03, 0xF0, 0x1F, 0xC0, 0xFF, 0x07,
- 0xF8, 0x1F, 0x80, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01,
- 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x0F, 0x81, 0xFE, 0x0F,
- 0xF0, 0x3F, 0x80, 0xFF, 0x01, 0xFE, 0x00, 0xFC, 0x01, 0xF0, 0x07, 0xC0,
- 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF8,
- 0x07, 0xF8, 0x0F, 0xF0, 0x3F, 0xC0, 0x7F, 0x00, 0x78, 0x77, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xE0, 0x78, 0x03, 0xF0, 0x0F,
- 0xE0, 0x3F, 0xC0, 0x7F, 0x00, 0x7E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80,
- 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0,
- 0x07, 0xC0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x03, 0xFC, 0x1F, 0xE0, 0xFC,
- 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,
- 0x00, 0xF8, 0x07, 0xE0, 0x7F, 0x83, 0xFC, 0x0F, 0xF0, 0x3F, 0x80, 0x78,
- 0x00, 0x07, 0x80, 0x00, 0x7F, 0x80, 0x03, 0xFF, 0x03, 0x9F, 0xFE, 0x1F,
- 0xFF, 0xFC, 0xFF, 0xF3, 0xFF, 0xFF, 0x87, 0xFF, 0x9C, 0x0F, 0xFC, 0x00,
- 0x0F, 0xE0, 0x00, 0x1F, 0x00 };
-
-const GFXglyph FreeMonoBold24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 28, 0, 1 }, // 0x20 ' '
- { 0, 7, 31, 28, 10, -29 }, // 0x21 '!'
- { 28, 15, 14, 28, 6, -28 }, // 0x22 '"'
- { 55, 22, 34, 28, 3, -30 }, // 0x23 '#'
- { 149, 19, 38, 28, 5, -31 }, // 0x24 '$'
- { 240, 21, 30, 28, 4, -28 }, // 0x25 '%'
- { 319, 21, 28, 28, 4, -26 }, // 0x26 '&'
- { 393, 6, 14, 28, 11, -28 }, // 0x27 '''
- { 404, 10, 37, 28, 12, -29 }, // 0x28 '('
- { 451, 10, 37, 28, 6, -29 }, // 0x29 ')'
- { 498, 21, 19, 28, 4, -28 }, // 0x2A '*'
- { 548, 23, 26, 28, 3, -25 }, // 0x2B '+'
- { 623, 9, 14, 28, 7, -6 }, // 0x2C ','
- { 639, 24, 5, 28, 2, -15 }, // 0x2D '-'
- { 654, 7, 6, 28, 11, -4 }, // 0x2E '.'
- { 660, 20, 38, 28, 4, -32 }, // 0x2F '/'
- { 755, 21, 31, 28, 4, -29 }, // 0x30 '0'
- { 837, 20, 29, 28, 4, -28 }, // 0x31 '1'
- { 910, 21, 30, 28, 3, -29 }, // 0x32 '2'
- { 989, 21, 31, 28, 4, -29 }, // 0x33 '3'
- { 1071, 20, 28, 28, 4, -27 }, // 0x34 '4'
- { 1141, 21, 31, 28, 4, -29 }, // 0x35 '5'
- { 1223, 20, 31, 28, 5, -29 }, // 0x36 '6'
- { 1301, 20, 30, 28, 4, -29 }, // 0x37 '7'
- { 1376, 20, 31, 28, 4, -29 }, // 0x38 '8'
- { 1454, 20, 31, 28, 5, -29 }, // 0x39 '9'
- { 1532, 7, 22, 28, 11, -20 }, // 0x3A ':'
- { 1552, 10, 28, 28, 6, -20 }, // 0x3B ';'
- { 1587, 24, 21, 28, 2, -23 }, // 0x3C '<'
- { 1650, 24, 14, 28, 2, -19 }, // 0x3D '='
- { 1692, 23, 22, 28, 3, -23 }, // 0x3E '>'
- { 1756, 20, 29, 28, 5, -27 }, // 0x3F '?'
- { 1829, 19, 36, 28, 4, -28 }, // 0x40 '@'
- { 1915, 29, 27, 28, -1, -26 }, // 0x41 'A'
- { 2013, 26, 27, 28, 1, -26 }, // 0x42 'B'
- { 2101, 25, 29, 28, 2, -27 }, // 0x43 'C'
- { 2192, 25, 27, 28, 1, -26 }, // 0x44 'D'
- { 2277, 25, 27, 28, 1, -26 }, // 0x45 'E'
- { 2362, 25, 27, 28, 1, -26 }, // 0x46 'F'
- { 2447, 25, 29, 28, 2, -27 }, // 0x47 'G'
- { 2538, 26, 27, 28, 1, -26 }, // 0x48 'H'
- { 2626, 19, 27, 28, 5, -26 }, // 0x49 'I'
- { 2691, 25, 28, 28, 3, -26 }, // 0x4A 'J'
- { 2779, 27, 27, 28, 1, -26 }, // 0x4B 'K'
- { 2871, 25, 27, 28, 2, -26 }, // 0x4C 'L'
- { 2956, 31, 27, 28, -1, -26 }, // 0x4D 'M'
- { 3061, 28, 27, 28, 0, -26 }, // 0x4E 'N'
- { 3156, 27, 29, 28, 1, -27 }, // 0x4F 'O'
- { 3254, 24, 27, 28, 1, -26 }, // 0x50 'P'
- { 3335, 27, 35, 28, 1, -27 }, // 0x51 'Q'
- { 3454, 28, 27, 28, 0, -26 }, // 0x52 'R'
- { 3549, 22, 29, 28, 3, -27 }, // 0x53 'S'
- { 3629, 25, 27, 28, 2, -26 }, // 0x54 'T'
- { 3714, 28, 28, 28, 0, -26 }, // 0x55 'U'
- { 3812, 30, 27, 28, -1, -26 }, // 0x56 'V'
- { 3914, 28, 27, 28, 0, -26 }, // 0x57 'W'
- { 4009, 26, 27, 28, 1, -26 }, // 0x58 'X'
- { 4097, 26, 27, 28, 1, -26 }, // 0x59 'Y'
- { 4185, 21, 27, 28, 4, -26 }, // 0x5A 'Z'
- { 4256, 10, 37, 28, 12, -29 }, // 0x5B '['
- { 4303, 20, 38, 28, 4, -32 }, // 0x5C '\'
- { 4398, 10, 37, 28, 6, -29 }, // 0x5D ']'
- { 4445, 20, 15, 28, 4, -29 }, // 0x5E '^'
- { 4483, 28, 5, 28, 0, 5 }, // 0x5F '_'
- { 4501, 9, 8, 28, 8, -30 }, // 0x60 '`'
- { 4510, 24, 23, 28, 2, -21 }, // 0x61 'a'
- { 4579, 27, 31, 28, 0, -29 }, // 0x62 'b'
- { 4684, 24, 23, 28, 3, -21 }, // 0x63 'c'
- { 4753, 26, 31, 28, 2, -29 }, // 0x64 'd'
- { 4854, 24, 23, 28, 2, -21 }, // 0x65 'e'
- { 4923, 22, 30, 28, 4, -29 }, // 0x66 'f'
- { 5006, 25, 31, 28, 2, -21 }, // 0x67 'g'
- { 5103, 26, 30, 28, 1, -29 }, // 0x68 'h'
- { 5201, 21, 29, 28, 4, -28 }, // 0x69 'i'
- { 5278, 17, 38, 28, 5, -28 }, // 0x6A 'j'
- { 5359, 25, 30, 28, 2, -29 }, // 0x6B 'k'
- { 5453, 21, 30, 28, 4, -29 }, // 0x6C 'l'
- { 5532, 30, 22, 28, -1, -21 }, // 0x6D 'm'
- { 5615, 25, 22, 28, 1, -21 }, // 0x6E 'n'
- { 5684, 25, 23, 28, 2, -21 }, // 0x6F 'o'
- { 5756, 28, 31, 28, 0, -21 }, // 0x70 'p'
- { 5865, 28, 31, 28, 1, -21 }, // 0x71 'q'
- { 5974, 24, 22, 28, 3, -21 }, // 0x72 'r'
- { 6040, 21, 23, 28, 4, -21 }, // 0x73 's'
- { 6101, 23, 28, 28, 1, -26 }, // 0x74 't'
- { 6182, 25, 22, 28, 1, -20 }, // 0x75 'u'
- { 6251, 28, 21, 28, 0, -20 }, // 0x76 'v'
- { 6325, 28, 21, 28, 0, -20 }, // 0x77 'w'
- { 6399, 26, 21, 28, 1, -20 }, // 0x78 'x'
- { 6468, 26, 30, 28, 1, -20 }, // 0x79 'y'
- { 6566, 19, 21, 28, 5, -20 }, // 0x7A 'z'
- { 6616, 14, 37, 28, 7, -29 }, // 0x7B '{'
- { 6681, 5, 36, 28, 12, -28 }, // 0x7C '|'
- { 6704, 14, 37, 28, 8, -29 }, // 0x7D '}'
- { 6769, 22, 10, 28, 3, -17 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBold24pt7b PROGMEM = {
- (uint8_t *)FreeMonoBold24pt7bBitmaps,
- (GFXglyph *)FreeMonoBold24pt7bGlyphs,
- 0x20, 0x7E, 47 };
-
-// Approx. 7469 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold9pt7b.h
deleted file mode 100644
index 75b1766..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBold9pt7b.h
+++ /dev/null
@@ -1,189 +0,0 @@
-const uint8_t FreeMonoBold9pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xD2, 0x1F, 0x80, 0xEC, 0x89, 0x12, 0x24, 0x40, 0x36, 0x36,
- 0x36, 0x7F, 0x7F, 0x36, 0xFF, 0xFF, 0x3C, 0x3C, 0x3C, 0x00, 0x18, 0xFF,
- 0xFE, 0x3C, 0x1F, 0x1F, 0x83, 0x46, 0x8D, 0xF0, 0xC1, 0x83, 0x00, 0x61,
- 0x22, 0x44, 0x86, 0x67, 0x37, 0x11, 0x22, 0x4C, 0x70, 0x3C, 0x7E, 0x60,
- 0x60, 0x30, 0x7B, 0xDF, 0xCE, 0xFF, 0x7F, 0xC9, 0x24, 0x37, 0x66, 0xCC,
- 0xCC, 0xCC, 0x66, 0x31, 0xCE, 0x66, 0x33, 0x33, 0x33, 0x66, 0xC8, 0x18,
- 0x18, 0xFF, 0xFF, 0x3C, 0x3C, 0x66, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x18,
- 0x18, 0x18, 0x18, 0x6B, 0x48, 0xFF, 0xFF, 0xC0, 0xF0, 0x02, 0x0C, 0x18,
- 0x60, 0xC3, 0x06, 0x0C, 0x30, 0x61, 0x83, 0x0C, 0x18, 0x20, 0x00, 0x38,
- 0xFB, 0xBE, 0x3C, 0x78, 0xF1, 0xE3, 0xC7, 0xDD, 0xF1, 0xC0, 0x38, 0xF3,
- 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0xFD, 0xF8, 0x3C, 0xFE, 0xC7, 0x03,
- 0x03, 0x06, 0x0C, 0x18, 0x70, 0xE3, 0xFF, 0xFF, 0x7C, 0xFE, 0x03, 0x03,
- 0x03, 0x1E, 0x1E, 0x07, 0x03, 0x03, 0xFE, 0x7C, 0x1C, 0x38, 0xB1, 0x64,
- 0xD9, 0xBF, 0xFF, 0x3E, 0x7C, 0x7E, 0x3F, 0x18, 0x0F, 0xC7, 0xF3, 0x1C,
- 0x06, 0x03, 0xC3, 0xFF, 0x9F, 0x80, 0x0F, 0x3F, 0x30, 0x60, 0x60, 0xDC,
- 0xFE, 0xE3, 0xC3, 0x63, 0x7E, 0x3C, 0xFF, 0xFF, 0xC3, 0x03, 0x06, 0x06,
- 0x06, 0x0C, 0x0C, 0x0C, 0x18, 0x38, 0xFB, 0x1E, 0x3C, 0x6F, 0x9F, 0x63,
- 0xC7, 0x8F, 0xF1, 0xC0, 0x3C, 0x7E, 0xE6, 0xC3, 0xC3, 0xE7, 0x7F, 0x3B,
- 0x06, 0x0E, 0xFC, 0xF0, 0xF0, 0x0F, 0x6C, 0x00, 0x1A, 0xD2, 0x00, 0x01,
- 0x83, 0x87, 0x0E, 0x0F, 0x80, 0xE0, 0x1C, 0x03, 0xFF, 0xFF, 0xC0, 0x00,
- 0x0F, 0xFF, 0xFC, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0xF9, 0xE3, 0xC1, 0x80,
- 0x7C, 0xFE, 0xC7, 0x03, 0x0E, 0x1C, 0x00, 0x00, 0x00, 0x30, 0x30, 0x1E,
- 0x1F, 0x1C, 0xDC, 0x6C, 0x76, 0x7B, 0x6D, 0xB6, 0xDB, 0x6F, 0xF3, 0xFC,
- 0x06, 0x33, 0xF8, 0x78, 0x3C, 0x07, 0xC0, 0x38, 0x05, 0x81, 0xB0, 0x36,
- 0x0F, 0xE1, 0xFC, 0x71, 0xDF, 0x7F, 0xEF, 0x80, 0xFF, 0x3F, 0xE6, 0x19,
- 0x86, 0x7F, 0x1F, 0xE6, 0x1D, 0x83, 0x60, 0xFF, 0xFF, 0xF0, 0x1F, 0xBF,
- 0xD8, 0xF8, 0x3C, 0x06, 0x03, 0x01, 0x80, 0x61, 0xBF, 0xC7, 0xC0, 0xFE,
- 0x3F, 0xE6, 0x19, 0x83, 0x60, 0xD8, 0x36, 0x0D, 0x83, 0x61, 0xBF, 0xEF,
- 0xE0, 0xFF, 0xFF, 0xD8, 0x6D, 0xB7, 0xC3, 0xE1, 0xB0, 0xC3, 0x61, 0xFF,
- 0xFF, 0xE0, 0xFF, 0xFF, 0xD8, 0x6D, 0xB7, 0xC3, 0xE1, 0xB0, 0xC0, 0x60,
- 0x7C, 0x3E, 0x00, 0x1F, 0x9F, 0xE6, 0x1B, 0x06, 0xC0, 0x30, 0x0C, 0x7F,
- 0x1F, 0xE1, 0x9F, 0xE3, 0xF0, 0xF7, 0xFB, 0xD8, 0xCC, 0x66, 0x33, 0xF9,
- 0xFC, 0xC6, 0x63, 0x7B, 0xFD, 0xE0, 0xFF, 0xF3, 0x0C, 0x30, 0xC3, 0x0C,
- 0x33, 0xFF, 0xC0, 0x1F, 0xC7, 0xF0, 0x30, 0x0C, 0x03, 0x00, 0xCC, 0x33,
- 0x0C, 0xC7, 0x3F, 0x87, 0xC0, 0xF7, 0xBD, 0xE6, 0x61, 0xB0, 0x78, 0x1F,
- 0x06, 0xE1, 0x98, 0x63, 0x3C, 0xFF, 0x3C, 0xFC, 0x7E, 0x0C, 0x06, 0x03,
- 0x01, 0x80, 0xC6, 0x63, 0x31, 0xFF, 0xFF, 0xE0, 0xE0, 0xFE, 0x3D, 0xC7,
- 0x3D, 0xE7, 0xBC, 0xD7, 0x9B, 0xB3, 0x76, 0x60, 0xDE, 0x3F, 0xC7, 0x80,
- 0xE1, 0xFE, 0x3D, 0xE3, 0x3C, 0x66, 0xCC, 0xDD, 0x99, 0xB3, 0x1E, 0x63,
- 0xDE, 0x3B, 0xC3, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x7C, 0x07, 0x80,
- 0xF0, 0x1F, 0x07, 0x71, 0xC7, 0xF0, 0x7C, 0x00, 0xFE, 0x7F, 0x98, 0x6C,
- 0x36, 0x1B, 0xF9, 0xF8, 0xC0, 0x60, 0x7C, 0x3E, 0x00, 0x1F, 0x07, 0xF1,
- 0xC7, 0x70, 0x7C, 0x07, 0x80, 0xF0, 0x1F, 0x07, 0x71, 0xC7, 0xF0, 0x7C,
- 0x0C, 0x33, 0xFE, 0x7F, 0x80, 0xFC, 0x7F, 0x18, 0xCC, 0x66, 0x73, 0xF1,
- 0xF0, 0xCC, 0x63, 0x7D, 0xFE, 0x60, 0x3F, 0xBF, 0xF0, 0x78, 0x0F, 0x03,
- 0xF8, 0x3F, 0x83, 0xC3, 0xFF, 0xBF, 0x80, 0xFF, 0xFF, 0xF6, 0x7B, 0x3D,
- 0x98, 0xC0, 0x60, 0x30, 0x18, 0x3F, 0x1F, 0x80, 0xF1, 0xFE, 0x3D, 0x83,
- 0x30, 0x66, 0x0C, 0xC1, 0x98, 0x33, 0x06, 0x60, 0xC7, 0xF0, 0x7C, 0x00,
- 0xFB, 0xFF, 0x7D, 0xC3, 0x18, 0xC3, 0x18, 0x36, 0x06, 0xC0, 0x50, 0x0E,
- 0x01, 0xC0, 0x10, 0x00, 0xFB, 0xFE, 0xF6, 0x0D, 0x93, 0x6E, 0xDB, 0xB7,
- 0xAD, 0xEE, 0x7B, 0x8E, 0xE3, 0x18, 0xF3, 0xFC, 0xF7, 0x38, 0xFC, 0x1E,
- 0x03, 0x01, 0xE0, 0xCC, 0x73, 0xBC, 0xFF, 0x3C, 0xF3, 0xFC, 0xF7, 0x38,
- 0xCC, 0x1E, 0x07, 0x80, 0xC0, 0x30, 0x0C, 0x0F, 0xC3, 0xF0, 0xFE, 0xFE,
- 0xC6, 0xCC, 0x18, 0x18, 0x30, 0x63, 0xC3, 0xFF, 0xFF, 0xFF, 0xCC, 0xCC,
- 0xCC, 0xCC, 0xCC, 0xFF, 0x01, 0x03, 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18,
- 0x30, 0x30, 0x60, 0x60, 0xC0, 0x80, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33,
- 0xFF, 0x10, 0x71, 0xE3, 0x6C, 0x70, 0x40, 0xFF, 0xFF, 0xFC, 0x88, 0x80,
- 0x7E, 0x3F, 0x8F, 0xCF, 0xEE, 0x36, 0x1B, 0xFE, 0xFF, 0xE0, 0x38, 0x06,
- 0x01, 0xBC, 0x7F, 0x9C, 0x76, 0x0D, 0x83, 0x71, 0xFF, 0xEE, 0xF0, 0x3F,
- 0xBF, 0xF8, 0x78, 0x3C, 0x07, 0x05, 0xFE, 0x7E, 0x03, 0x80, 0xE0, 0x18,
- 0xF6, 0x7F, 0xB8, 0xEC, 0x1B, 0x06, 0xE3, 0x9F, 0xF3, 0xFC, 0x3E, 0x3F,
- 0xB0, 0xFF, 0xFF, 0xFE, 0x01, 0xFE, 0x7E, 0x1F, 0x3F, 0x30, 0x7E, 0x7E,
- 0x30, 0x30, 0x30, 0x30, 0xFE, 0xFE, 0x3F, 0xBF, 0xF9, 0xD8, 0x6C, 0x37,
- 0x39, 0xFC, 0x76, 0x03, 0x01, 0x8F, 0xC7, 0xC0, 0xE0, 0x70, 0x18, 0x0D,
- 0xC7, 0xF3, 0x99, 0x8C, 0xC6, 0x63, 0x7B, 0xFD, 0xE0, 0x18, 0x18, 0x00,
- 0x78, 0x78, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x18, 0x60, 0x3F, 0xFC,
- 0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0F, 0xFF, 0x80, 0xE0, 0x70, 0x18, 0x0D,
- 0xE6, 0xF3, 0xE1, 0xE0, 0xF8, 0x6E, 0x73, 0xF9, 0xE0, 0x78, 0x78, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0xFD, 0x9F, 0xF9, 0x9B,
- 0x33, 0x66, 0x6C, 0xCD, 0xBD, 0xFF, 0xBF, 0xEE, 0x7F, 0x98, 0xCC, 0x66,
- 0x33, 0x1B, 0xDF, 0xEF, 0x3E, 0x3F, 0xB8, 0xF8, 0x3C, 0x1F, 0x1D, 0xFC,
- 0x7C, 0xEF, 0x1F, 0xF9, 0xC3, 0xB0, 0x36, 0x06, 0xE1, 0xDF, 0xF3, 0x78,
- 0x60, 0x0C, 0x03, 0xE0, 0x7C, 0x00, 0x1E, 0xEF, 0xFF, 0x87, 0x60, 0x6C,
- 0x0D, 0xC3, 0x9F, 0xF0, 0xF6, 0x00, 0xC0, 0x18, 0x0F, 0x81, 0xF0, 0x77,
- 0xBF, 0xCF, 0x06, 0x03, 0x01, 0x83, 0xF9, 0xFC, 0x3F, 0xFF, 0xC3, 0xFC,
- 0x3F, 0xC3, 0xFF, 0xFC, 0x60, 0x60, 0x60, 0xFE, 0xFE, 0x60, 0x60, 0x60,
- 0x61, 0x7F, 0x3E, 0xE7, 0x73, 0x98, 0xCC, 0x66, 0x33, 0x19, 0xFE, 0x7F,
- 0xFB, 0xFF, 0x7C, 0xC6, 0x18, 0xC1, 0xB0, 0x36, 0x03, 0x80, 0x70, 0xF1,
- 0xFE, 0x3D, 0xBB, 0x37, 0x63, 0xF8, 0x77, 0x0E, 0xE1, 0x8C, 0xF7, 0xFB,
- 0xCD, 0x83, 0x83, 0xC3, 0xBB, 0xDF, 0xEF, 0xF3, 0xFC, 0xF6, 0x18, 0xCC,
- 0x33, 0x07, 0x81, 0xE0, 0x30, 0x0C, 0x06, 0x0F, 0xC3, 0xF0, 0xFF, 0xFF,
- 0x30, 0xC3, 0x0C, 0x7F, 0xFF, 0x37, 0x66, 0x66, 0xCC, 0x66, 0x66, 0x73,
- 0xFF, 0xFF, 0xFF, 0xF0, 0xCE, 0x66, 0x66, 0x33, 0x66, 0x66, 0xEC, 0x70,
- 0x7C, 0xF3, 0xC0, 0xC0 };
-
-const GFXglyph FreeMonoBold9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 11, 0, 1 }, // 0x20 ' '
- { 0, 3, 11, 11, 4, -10 }, // 0x21 '!'
- { 5, 7, 5, 11, 2, -10 }, // 0x22 '"'
- { 10, 8, 12, 11, 1, -10 }, // 0x23 '#'
- { 22, 7, 14, 11, 2, -11 }, // 0x24 '$'
- { 35, 7, 11, 11, 2, -10 }, // 0x25 '%'
- { 45, 8, 10, 11, 1, -9 }, // 0x26 '&'
- { 55, 3, 5, 11, 4, -10 }, // 0x27 '''
- { 57, 4, 14, 11, 5, -10 }, // 0x28 '('
- { 64, 4, 14, 11, 2, -10 }, // 0x29 ')'
- { 71, 8, 7, 11, 2, -10 }, // 0x2A '*'
- { 78, 8, 9, 11, 2, -8 }, // 0x2B '+'
- { 87, 3, 5, 11, 3, -1 }, // 0x2C ','
- { 89, 9, 2, 11, 1, -5 }, // 0x2D '-'
- { 92, 2, 2, 11, 4, -1 }, // 0x2E '.'
- { 93, 7, 15, 11, 2, -12 }, // 0x2F '/'
- { 107, 7, 12, 11, 2, -11 }, // 0x30 '0'
- { 118, 7, 11, 11, 2, -10 }, // 0x31 '1'
- { 128, 8, 12, 11, 1, -11 }, // 0x32 '2'
- { 140, 8, 12, 11, 2, -11 }, // 0x33 '3'
- { 152, 7, 10, 11, 2, -9 }, // 0x34 '4'
- { 161, 9, 11, 11, 1, -10 }, // 0x35 '5'
- { 174, 8, 12, 11, 2, -11 }, // 0x36 '6'
- { 186, 8, 11, 11, 1, -10 }, // 0x37 '7'
- { 197, 7, 12, 11, 2, -11 }, // 0x38 '8'
- { 208, 8, 12, 11, 2, -11 }, // 0x39 '9'
- { 220, 2, 8, 11, 4, -7 }, // 0x3A ':'
- { 222, 3, 11, 11, 3, -7 }, // 0x3B ';'
- { 227, 9, 8, 11, 1, -8 }, // 0x3C '<'
- { 236, 9, 6, 11, 1, -7 }, // 0x3D '='
- { 243, 9, 8, 11, 1, -8 }, // 0x3E '>'
- { 252, 8, 11, 11, 2, -10 }, // 0x3F '?'
- { 263, 9, 15, 11, 1, -11 }, // 0x40 '@'
- { 280, 11, 11, 11, 0, -10 }, // 0x41 'A'
- { 296, 10, 11, 11, 1, -10 }, // 0x42 'B'
- { 310, 9, 11, 11, 1, -10 }, // 0x43 'C'
- { 323, 10, 11, 11, 0, -10 }, // 0x44 'D'
- { 337, 9, 11, 11, 1, -10 }, // 0x45 'E'
- { 350, 9, 11, 11, 1, -10 }, // 0x46 'F'
- { 363, 10, 11, 11, 1, -10 }, // 0x47 'G'
- { 377, 9, 11, 11, 1, -10 }, // 0x48 'H'
- { 390, 6, 11, 11, 3, -10 }, // 0x49 'I'
- { 399, 10, 11, 11, 1, -10 }, // 0x4A 'J'
- { 413, 10, 11, 11, 1, -10 }, // 0x4B 'K'
- { 427, 9, 11, 11, 1, -10 }, // 0x4C 'L'
- { 440, 11, 11, 11, 0, -10 }, // 0x4D 'M'
- { 456, 11, 11, 11, 0, -10 }, // 0x4E 'N'
- { 472, 11, 11, 11, 0, -10 }, // 0x4F 'O'
- { 488, 9, 11, 11, 1, -10 }, // 0x50 'P'
- { 501, 11, 14, 11, 0, -10 }, // 0x51 'Q'
- { 521, 9, 11, 11, 1, -10 }, // 0x52 'R'
- { 534, 9, 11, 11, 1, -10 }, // 0x53 'S'
- { 547, 9, 11, 11, 1, -10 }, // 0x54 'T'
- { 560, 11, 11, 11, 0, -10 }, // 0x55 'U'
- { 576, 11, 11, 11, 0, -10 }, // 0x56 'V'
- { 592, 10, 11, 11, 0, -10 }, // 0x57 'W'
- { 606, 10, 11, 11, 0, -10 }, // 0x58 'X'
- { 620, 10, 11, 11, 0, -10 }, // 0x59 'Y'
- { 634, 8, 11, 11, 2, -10 }, // 0x5A 'Z'
- { 645, 4, 14, 11, 5, -10 }, // 0x5B '['
- { 652, 7, 15, 11, 2, -12 }, // 0x5C '\'
- { 666, 4, 14, 11, 2, -10 }, // 0x5D ']'
- { 673, 7, 6, 11, 2, -11 }, // 0x5E '^'
- { 679, 11, 2, 11, 0, 3 }, // 0x5F '_'
- { 682, 3, 3, 11, 3, -11 }, // 0x60 '`'
- { 684, 9, 8, 11, 1, -7 }, // 0x61 'a'
- { 693, 10, 11, 11, 0, -10 }, // 0x62 'b'
- { 707, 9, 8, 11, 1, -7 }, // 0x63 'c'
- { 716, 10, 11, 11, 1, -10 }, // 0x64 'd'
- { 730, 9, 8, 11, 1, -7 }, // 0x65 'e'
- { 739, 8, 11, 11, 2, -10 }, // 0x66 'f'
- { 750, 9, 12, 11, 1, -7 }, // 0x67 'g'
- { 764, 9, 11, 11, 1, -10 }, // 0x68 'h'
- { 777, 8, 11, 11, 2, -10 }, // 0x69 'i'
- { 788, 6, 15, 11, 2, -10 }, // 0x6A 'j'
- { 800, 9, 11, 11, 1, -10 }, // 0x6B 'k'
- { 813, 8, 11, 11, 2, -10 }, // 0x6C 'l'
- { 824, 11, 8, 11, 0, -7 }, // 0x6D 'm'
- { 835, 9, 8, 11, 1, -7 }, // 0x6E 'n'
- { 844, 9, 8, 11, 1, -7 }, // 0x6F 'o'
- { 853, 11, 12, 11, 0, -7 }, // 0x70 'p'
- { 870, 11, 12, 11, 0, -7 }, // 0x71 'q'
- { 887, 9, 8, 11, 1, -7 }, // 0x72 'r'
- { 896, 8, 8, 11, 2, -7 }, // 0x73 's'
- { 904, 8, 11, 11, 1, -10 }, // 0x74 't'
- { 915, 9, 8, 11, 1, -7 }, // 0x75 'u'
- { 924, 11, 8, 11, 0, -7 }, // 0x76 'v'
- { 935, 11, 8, 11, 0, -7 }, // 0x77 'w'
- { 946, 9, 8, 11, 1, -7 }, // 0x78 'x'
- { 955, 10, 12, 11, 0, -7 }, // 0x79 'y'
- { 970, 7, 8, 11, 2, -7 }, // 0x7A 'z'
- { 977, 4, 14, 11, 3, -10 }, // 0x7B '{'
- { 984, 2, 14, 11, 5, -10 }, // 0x7C '|'
- { 988, 4, 14, 11, 4, -10 }, // 0x7D '}'
- { 995, 9, 4, 11, 1, -6 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBold9pt7b PROGMEM = {
- (uint8_t *)FreeMonoBold9pt7bBitmaps,
- (GFXglyph *)FreeMonoBold9pt7bGlyphs,
- 0x20, 0x7E, 18 };
-
-// Approx. 1672 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique12pt7b.h
deleted file mode 100644
index cc3ecb2..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique12pt7b.h
+++ /dev/null
@@ -1,269 +0,0 @@
-const uint8_t FreeMonoBoldOblique12pt7bBitmaps[] PROGMEM = {
- 0x1C, 0xF3, 0xCE, 0x38, 0xE7, 0x1C, 0x61, 0x86, 0x00, 0x63, 0x8C, 0x00,
- 0xE7, 0xE7, 0xE6, 0xC6, 0xC6, 0xC4, 0x84, 0x03, 0x30, 0x19, 0x81, 0xDC,
- 0x0C, 0xE0, 0x66, 0x1F, 0xFC, 0xFF, 0xE1, 0x98, 0x0C, 0xC0, 0xEE, 0x06,
- 0x70, 0xFF, 0xCF, 0xFE, 0x1D, 0xC0, 0xCC, 0x06, 0x60, 0x77, 0x03, 0x30,
- 0x00, 0x01, 0x00, 0x70, 0x0C, 0x07, 0xF1, 0xFE, 0x71, 0xCC, 0x11, 0x80,
- 0x3F, 0x03, 0xF0, 0x0F, 0x20, 0x6E, 0x0D, 0xC3, 0x3F, 0xE7, 0xF8, 0x1C,
- 0x03, 0x00, 0x60, 0x0C, 0x00, 0x0E, 0x03, 0xE0, 0xC4, 0x10, 0x82, 0x30,
- 0x7C, 0x07, 0x78, 0x7C, 0x7F, 0x19, 0xF0, 0x62, 0x08, 0x41, 0x18, 0x3E,
- 0x03, 0x80, 0x07, 0xC1, 0xF8, 0x62, 0x0C, 0x01, 0x80, 0x38, 0x0F, 0x03,
- 0xF7, 0x6F, 0xD8, 0xF3, 0x1E, 0x7F, 0xE7, 0xF8, 0xFF, 0x6D, 0x20, 0x06,
- 0x1C, 0x70, 0xC3, 0x06, 0x18, 0x30, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30,
- 0x70, 0x60, 0xC1, 0x00, 0x0C, 0x18, 0x38, 0x30, 0x60, 0xC1, 0x83, 0x06,
- 0x0C, 0x30, 0x61, 0xC3, 0x0E, 0x38, 0x61, 0xC2, 0x00, 0x06, 0x00, 0xC0,
- 0x18, 0x3F, 0x7F, 0xFE, 0xFF, 0x07, 0x81, 0xF8, 0x77, 0x0C, 0x60, 0x03,
- 0x00, 0x70, 0x07, 0x00, 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0xE0, 0x0C,
- 0x00, 0xC0, 0x0C, 0x01, 0xC0, 0x18, 0x00, 0x1C, 0xE3, 0x1C, 0x63, 0x08,
- 0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x7F, 0x00, 0x00, 0x08, 0x00, 0x70, 0x01,
- 0x80, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70, 0x03, 0x80, 0x0C,
- 0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70,
- 0x03, 0x80, 0x0C, 0x00, 0x20, 0x00, 0x07, 0x83, 0xF8, 0xE3, 0x98, 0x37,
- 0x06, 0xC0, 0xD8, 0x1B, 0x03, 0xE0, 0xF8, 0x1B, 0x03, 0x60, 0xEE, 0x38,
- 0xFE, 0x0F, 0x00, 0x03, 0xC1, 0xF0, 0x7E, 0x0C, 0xC0, 0x38, 0x07, 0x00,
- 0xC0, 0x18, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0x61, 0xFF, 0xFF, 0xF0,
- 0x03, 0xE0, 0x3F, 0x83, 0x8E, 0x38, 0x31, 0x81, 0x80, 0x18, 0x01, 0xC0,
- 0x1C, 0x01, 0xC0, 0x38, 0x03, 0x80, 0x38, 0x47, 0x87, 0x3F, 0xF3, 0xFF,
- 0x80, 0x07, 0xC1, 0xFF, 0x18, 0x70, 0x03, 0x00, 0x30, 0x06, 0x07, 0xC0,
- 0x7C, 0x00, 0xE0, 0x06, 0x00, 0x60, 0x06, 0xC1, 0xCF, 0xF8, 0x7E, 0x00,
- 0x01, 0xE0, 0x3C, 0x0F, 0x03, 0x60, 0xCC, 0x3B, 0x8E, 0x63, 0x8C, 0x61,
- 0x9F, 0xFB, 0xFF, 0x01, 0x81, 0xF8, 0x3F, 0x00, 0x0F, 0xF1, 0xFE, 0x18,
- 0x01, 0x80, 0x18, 0x03, 0xF8, 0x3F, 0xC3, 0x8E, 0x00, 0x60, 0x06, 0x00,
- 0x60, 0x0C, 0xC1, 0xCF, 0xF8, 0x7E, 0x00, 0x03, 0xE1, 0xFC, 0x70, 0x1C,
- 0x03, 0x00, 0xC0, 0x1B, 0xC7, 0xFC, 0xF3, 0x98, 0x33, 0x06, 0x60, 0xCE,
- 0x30, 0xFC, 0x0F, 0x00, 0xFF, 0xFF, 0xFB, 0x07, 0x60, 0xC0, 0x38, 0x06,
- 0x01, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x70, 0x1C, 0x03, 0x80, 0x60, 0x08,
- 0x00, 0x07, 0x83, 0xF8, 0xE3, 0xB0, 0x36, 0x06, 0xC0, 0xDC, 0x31, 0xFC,
- 0x3F, 0x8C, 0x3B, 0x03, 0x60, 0x6C, 0x39, 0xFE, 0x1F, 0x00, 0x07, 0x81,
- 0xF8, 0x63, 0x98, 0x33, 0x06, 0x60, 0xCE, 0x79, 0xFF, 0x1E, 0xC0, 0x18,
- 0x06, 0x01, 0xC0, 0x71, 0xFC, 0x3E, 0x00, 0x19, 0xCC, 0x00, 0x00, 0x00,
- 0x67, 0x30, 0x06, 0x1C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x38, 0x71, 0xC3,
- 0x0E, 0x18, 0x20, 0x00, 0x00, 0x18, 0x03, 0xC0, 0x7C, 0x1F, 0x03, 0xE0,
- 0x3E, 0x00, 0x7C, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0x80, 0x08, 0x7F, 0xFB,
- 0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFB, 0xFF, 0xC0, 0x30, 0x01,
- 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x3E, 0x00, 0x7C, 0x1F, 0x03, 0xE0, 0x7C,
- 0x07, 0x80, 0x20, 0x00, 0x3E, 0x7F, 0xB0, 0xF8, 0x30, 0x18, 0x1C, 0x1C,
- 0x3C, 0x38, 0x18, 0x00, 0x06, 0x07, 0x03, 0x00, 0x03, 0xC0, 0x7E, 0x0C,
- 0x71, 0x83, 0x30, 0x33, 0x0F, 0x33, 0xE6, 0x76, 0x6C, 0x66, 0xC6, 0x6C,
- 0x6C, 0xFC, 0xC7, 0xEC, 0x00, 0xC0, 0x0C, 0x00, 0xE3, 0x07, 0xF0, 0x3C,
- 0x00, 0x07, 0xF0, 0x1F, 0xE0, 0x07, 0xC0, 0x1F, 0x80, 0x3B, 0x00, 0xE7,
- 0x01, 0x8E, 0x07, 0x1C, 0x1F, 0xF8, 0x3F, 0xF0, 0xE0, 0x71, 0x80, 0xEF,
- 0xC7, 0xFF, 0x8F, 0xC0, 0x3F, 0xF1, 0xFF, 0xC3, 0x06, 0x38, 0x31, 0xC1,
- 0x8C, 0x18, 0x7F, 0xC3, 0xFE, 0x38, 0x39, 0xC0, 0xCC, 0x06, 0x60, 0x6F,
- 0xFF, 0x7F, 0xE0, 0x03, 0xEC, 0x3F, 0xF1, 0xC3, 0x8C, 0x06, 0x60, 0x19,
- 0x80, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x03, 0x3C, 0x1C,
- 0x7F, 0xE0, 0x7E, 0x00, 0x3F, 0xE1, 0xFF, 0x87, 0x0C, 0x30, 0x31, 0x81,
- 0x8C, 0x0C, 0xE0, 0x67, 0x03, 0x30, 0x31, 0x81, 0x8C, 0x0C, 0xE1, 0xCF,
- 0xFC, 0x7F, 0x80, 0x1F, 0xFE, 0x3F, 0xFC, 0x38, 0x38, 0x70, 0x70, 0xCC,
- 0xC1, 0x98, 0x03, 0xF0, 0x0F, 0xE0, 0x1D, 0x80, 0x31, 0x18, 0x60, 0x70,
- 0xC0, 0xE7, 0xFF, 0x9F, 0xFF, 0x00, 0x1F, 0xFF, 0x1F, 0xFE, 0x0E, 0x06,
- 0x0C, 0x0E, 0x0C, 0xC4, 0x0C, 0xC0, 0x1F, 0xC0, 0x1F, 0xC0, 0x19, 0xC0,
- 0x19, 0x80, 0x18, 0x00, 0x38, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x07, 0xEC,
- 0x7F, 0xF3, 0x83, 0x9C, 0x06, 0x60, 0x19, 0x80, 0x0C, 0x00, 0x30, 0xFE,
- 0xC3, 0xFB, 0x01, 0xCC, 0x07, 0x3C, 0x38, 0x7F, 0xE0, 0x7E, 0x00, 0x0F,
- 0xBF, 0x1F, 0xBE, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x1C, 0x1F,
- 0xF8, 0x1F, 0xF8, 0x18, 0x18, 0x18, 0x38, 0x18, 0x38, 0x38, 0x30, 0x7C,
- 0xFC, 0xFC, 0xF8, 0x3F, 0xF3, 0xFF, 0x03, 0x00, 0x70, 0x07, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xC0, 0xFF, 0xCF, 0xFC,
- 0x03, 0xFF, 0x03, 0xFF, 0x00, 0x38, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30,
- 0x00, 0x70, 0x20, 0x70, 0x60, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE1, 0xC0,
- 0xFF, 0x80, 0x3F, 0x00, 0x1F, 0x9F, 0x1F, 0x9E, 0x0E, 0x38, 0x0C, 0x70,
- 0x0C, 0xE0, 0x0F, 0xC0, 0x1F, 0xC0, 0x1F, 0xE0, 0x1C, 0xE0, 0x18, 0x60,
- 0x18, 0x70, 0x38, 0x70, 0xFE, 0x3C, 0xFC, 0x3C, 0x3F, 0xC1, 0xFE, 0x01,
- 0x80, 0x1C, 0x00, 0xE0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x1C, 0x18, 0xE0,
- 0xC6, 0x06, 0x30, 0x7F, 0xFF, 0xFF, 0xF8, 0x1E, 0x07, 0x87, 0x81, 0xE0,
- 0xF0, 0xF0, 0x7C, 0x7C, 0x1F, 0x1F, 0x06, 0xCF, 0x81, 0xBF, 0x60, 0xEF,
- 0x98, 0x3B, 0xEE, 0x0C, 0x73, 0x83, 0x1C, 0xC0, 0xC0, 0x30, 0xFC, 0x7E,
- 0x3F, 0x1F, 0x80, 0x3C, 0x3F, 0x3E, 0x3F, 0x1E, 0x0C, 0x1F, 0x1C, 0x1F,
- 0x1C, 0x1B, 0x98, 0x3B, 0x98, 0x3B, 0x98, 0x31, 0xF8, 0x31, 0xF8, 0x30,
- 0xF0, 0x70, 0xF0, 0xFC, 0x70, 0xF8, 0x70, 0x03, 0xE0, 0x3F, 0xE1, 0xC3,
- 0x8C, 0x07, 0x60, 0x0D, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1B, 0x00,
- 0x6E, 0x03, 0x1C, 0x38, 0x7F, 0xC0, 0x7C, 0x00, 0x3F, 0xE1, 0xFF, 0x83,
- 0x0E, 0x38, 0x31, 0xC1, 0x8C, 0x0C, 0x60, 0xC3, 0xFC, 0x3F, 0xC1, 0xC0,
- 0x0C, 0x00, 0x60, 0x0F, 0xF0, 0x7F, 0x80, 0x03, 0xE0, 0x3F, 0xE1, 0xC3,
- 0x8C, 0x07, 0x60, 0x0D, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1B, 0x00,
- 0x6E, 0x03, 0x1C, 0x38, 0x7F, 0xC0, 0xFC, 0x03, 0x02, 0x1F, 0xFC, 0xFF,
- 0xE0, 0x1F, 0xF0, 0x3F, 0xF0, 0x38, 0x70, 0x60, 0x60, 0xC0, 0xC1, 0x87,
- 0x07, 0xFC, 0x0F, 0xF0, 0x18, 0xF0, 0x30, 0xE0, 0x60, 0xC1, 0xC1, 0xCF,
- 0xE1, 0xFF, 0xC3, 0xC0, 0x0F, 0xB1, 0xFF, 0x30, 0xE6, 0x06, 0x60, 0x67,
- 0x80, 0x7F, 0x01, 0xFC, 0x01, 0xC4, 0x0C, 0xC0, 0xCE, 0x18, 0xFF, 0x8B,
- 0xE0, 0x7F, 0xFB, 0xFF, 0xD9, 0xCF, 0xCE, 0x7C, 0x63, 0x63, 0x18, 0x18,
- 0x01, 0xC0, 0x0E, 0x00, 0x60, 0x03, 0x00, 0x18, 0x0F, 0xF8, 0x7F, 0xC0,
- 0x7E, 0xFF, 0xF3, 0xF3, 0x03, 0x1C, 0x0C, 0x60, 0x31, 0x81, 0xC6, 0x06,
- 0x38, 0x18, 0xE0, 0x63, 0x03, 0x8C, 0x0C, 0x30, 0x70, 0x7F, 0x80, 0xF8,
- 0x00, 0xFC, 0x7F, 0xF8, 0xFD, 0xC0, 0x61, 0x81, 0xC3, 0x87, 0x07, 0x0C,
- 0x0E, 0x38, 0x0C, 0x60, 0x19, 0xC0, 0x3F, 0x00, 0x7C, 0x00, 0xF8, 0x00,
- 0xE0, 0x01, 0x80, 0x00, 0x7E, 0x7E, 0xFC, 0xFD, 0xC0, 0x73, 0x9C, 0xE7,
- 0x79, 0x8E, 0xF7, 0x1B, 0xEE, 0x36, 0xD8, 0x7D, 0xF0, 0xF3, 0xE1, 0xE7,
- 0x83, 0x8F, 0x07, 0x1E, 0x1C, 0x38, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x0E,
- 0x1C, 0x07, 0x38, 0x07, 0x70, 0x03, 0xE0, 0x03, 0xC0, 0x03, 0xC0, 0x07,
- 0xE0, 0x0E, 0xE0, 0x1C, 0x70, 0x38, 0x70, 0xFC, 0xFC, 0xFC, 0xFC, 0xF8,
- 0xFF, 0xC7, 0xCC, 0x38, 0x73, 0x83, 0x9C, 0x0F, 0xC0, 0x7C, 0x01, 0xC0,
- 0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x0F, 0xF8, 0x7F, 0x80, 0x0F, 0xF8,
- 0x7F, 0xE1, 0xC7, 0x86, 0x1C, 0x18, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0,
- 0x0E, 0x00, 0x70, 0xC3, 0x83, 0x1C, 0x1C, 0x7F, 0xF3, 0xFF, 0x80, 0x0F,
- 0x87, 0xC3, 0x03, 0x81, 0xC0, 0xC0, 0x60, 0x30, 0x38, 0x1C, 0x0C, 0x06,
- 0x03, 0x03, 0x81, 0xC0, 0xC0, 0x60, 0x3E, 0x3F, 0x00, 0x41, 0xC3, 0x83,
- 0x07, 0x0E, 0x1C, 0x18, 0x38, 0x70, 0xE0, 0xC1, 0xC3, 0x83, 0x06, 0x0E,
- 0x1C, 0x18, 0x20, 0x1F, 0x0F, 0x80, 0xC0, 0xE0, 0x70, 0x30, 0x18, 0x0C,
- 0x0E, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xE0, 0x70, 0x30, 0x18, 0x7C, 0x3E,
- 0x00, 0x02, 0x01, 0x80, 0xF0, 0x7E, 0x3B, 0x9C, 0x7E, 0x1F, 0x03, 0xFF,
- 0xFF, 0xFF, 0xFC, 0xCE, 0x73, 0x1F, 0xC3, 0xFE, 0x00, 0x60, 0x06, 0x0F,
- 0xE3, 0xFE, 0x70, 0xCC, 0x0C, 0xC3, 0xCF, 0xFF, 0x7F, 0xF0, 0x1E, 0x00,
- 0x3C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xDF, 0x81, 0xFF, 0x83, 0xC3, 0x8F,
- 0x03, 0x1C, 0x06, 0x38, 0x0C, 0x70, 0x18, 0xE0, 0x63, 0xE1, 0x9F, 0xFE,
- 0x3D, 0xF8, 0x00, 0x0F, 0xF3, 0xFF, 0x30, 0x76, 0x07, 0xE0, 0x6C, 0x00,
- 0xC0, 0x0C, 0x00, 0xE0, 0x67, 0xFE, 0x3F, 0x80, 0x00, 0x3C, 0x00, 0xF0,
- 0x01, 0xC0, 0x06, 0x07, 0xD8, 0x7F, 0xE3, 0x0F, 0x98, 0x1E, 0x60, 0x73,
- 0x01, 0xCC, 0x07, 0x30, 0x3C, 0xE1, 0xF1, 0xFF, 0xE3, 0xF7, 0x80, 0x0F,
- 0xC1, 0xFE, 0x78, 0x76, 0x03, 0xFF, 0xFF, 0xFF, 0xC0, 0x0C, 0x00, 0xE0,
- 0xE7, 0xFE, 0x1F, 0x80, 0x00, 0xFC, 0x07, 0xF8, 0x0C, 0x00, 0x38, 0x01,
- 0xFF, 0x07, 0xFE, 0x01, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x18, 0x00, 0x30,
- 0x00, 0x60, 0x01, 0xC0, 0x1F, 0xF8, 0x3F, 0xF0, 0x00, 0x0F, 0xBC, 0x7F,
- 0xF3, 0x0F, 0x18, 0x1C, 0xC0, 0x73, 0x01, 0x8C, 0x0E, 0x30, 0x38, 0xE3,
- 0xE1, 0xFF, 0x83, 0xEC, 0x00, 0x30, 0x01, 0xC0, 0x06, 0x07, 0xF0, 0x1F,
- 0x80, 0x1E, 0x01, 0xF0, 0x03, 0x00, 0x18, 0x00, 0xDE, 0x0F, 0xF8, 0x78,
- 0xC3, 0x86, 0x18, 0x30, 0xC1, 0x8E, 0x1C, 0x70, 0xE3, 0x06, 0x7E, 0xFF,
- 0xE7, 0xE0, 0x03, 0x80, 0x70, 0x00, 0x0F, 0xC1, 0xF0, 0x06, 0x00, 0xC0,
- 0x38, 0x07, 0x00, 0xC0, 0x18, 0x03, 0x0F, 0xFF, 0xFF, 0xC0, 0x00, 0x70,
- 0x07, 0x00, 0x00, 0xFF, 0x1F, 0xF0, 0x07, 0x00, 0x70, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0xE0, 0x0E, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x1C, 0x03, 0x87,
- 0xF0, 0xFE, 0x00, 0x1E, 0x00, 0x78, 0x00, 0xE0, 0x03, 0x80, 0x0C, 0xFC,
- 0x33, 0xE0, 0xDE, 0x07, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xF8, 0x06, 0xF0,
- 0x39, 0xC3, 0xE7, 0xEF, 0x1F, 0x80, 0x0F, 0x81, 0xF0, 0x06, 0x01, 0xC0,
- 0x38, 0x06, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0x61,
- 0xFF, 0xFF, 0xF8, 0x3F, 0xBC, 0x7F, 0xFC, 0xF3, 0x98, 0xC6, 0x33, 0x9C,
- 0xE7, 0x39, 0xCC, 0x63, 0x18, 0xC6, 0x31, 0x8D, 0xF7, 0xBF, 0xEF, 0x78,
- 0x3D, 0xE1, 0xFF, 0x8F, 0x8C, 0x38, 0x61, 0x83, 0x0C, 0x18, 0xE1, 0xC7,
- 0x0E, 0x30, 0x67, 0xEF, 0xFE, 0x7E, 0x07, 0xC1, 0xFE, 0x38, 0x76, 0x03,
- 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x06, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x1E,
- 0xFC, 0x1F, 0xFE, 0x0F, 0x87, 0x0F, 0x03, 0x0E, 0x03, 0x0E, 0x03, 0x0E,
- 0x07, 0x0E, 0x06, 0x1F, 0x0C, 0x1F, 0xF8, 0x19, 0xF0, 0x18, 0x00, 0x18,
- 0x00, 0x38, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x0F, 0xDE, 0x3F, 0xFC, 0xC3,
- 0xE3, 0x03, 0x84, 0x07, 0x18, 0x0E, 0x30, 0x1C, 0x60, 0x78, 0xE1, 0xE0,
- 0xFF, 0xC0, 0xF9, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x1C, 0x01, 0xFC, 0x03,
- 0xF8, 0x1E, 0x78, 0x7F, 0xF0, 0x7C, 0xC3, 0xC0, 0x0E, 0x00, 0x30, 0x00,
- 0xC0, 0x03, 0x00, 0x1C, 0x03, 0xFF, 0x0F, 0xFC, 0x00, 0x07, 0xF1, 0xFF,
- 0x30, 0x73, 0x86, 0x3F, 0x81, 0xFE, 0x03, 0xE6, 0x06, 0xE0, 0xEF, 0xFC,
- 0xFF, 0x00, 0x0C, 0x07, 0x01, 0x83, 0xFF, 0xFF, 0xCE, 0x03, 0x00, 0xC0,
- 0x30, 0x1C, 0x07, 0x01, 0x83, 0x7F, 0xCF, 0xC0, 0xF0, 0xFF, 0x1F, 0x60,
- 0x76, 0x07, 0x60, 0x76, 0x06, 0x60, 0x66, 0x0E, 0x61, 0xE7, 0xFF, 0x3E,
- 0xF0, 0x7E, 0x7E, 0xFC, 0xFC, 0xE0, 0xC0, 0xC3, 0x81, 0x86, 0x03, 0x98,
- 0x07, 0x70, 0x06, 0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x38, 0x00, 0xF8, 0x7F,
- 0xE3, 0xE6, 0x63, 0x1B, 0xDC, 0x6F, 0x61, 0xFF, 0x87, 0xFC, 0x1E, 0xF0,
- 0x73, 0x81, 0xCE, 0x06, 0x38, 0x00, 0x3E, 0x7C, 0xF9, 0xF1, 0xE7, 0x03,
- 0xF8, 0x07, 0xC0, 0x1F, 0x01, 0xFC, 0x0F, 0x38, 0x78, 0xFB, 0xF7, 0xEF,
- 0x9F, 0x80, 0x1F, 0x1F, 0x3E, 0x1F, 0x1C, 0x1C, 0x0C, 0x18, 0x0E, 0x38,
- 0x0E, 0x70, 0x06, 0x60, 0x07, 0xE0, 0x07, 0xC0, 0x07, 0xC0, 0x03, 0x80,
- 0x07, 0x00, 0x07, 0x00, 0x0E, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x1F, 0xF1,
- 0xFF, 0x38, 0xE3, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC6, 0x38, 0x67,
- 0xFE, 0x7F, 0xE0, 0x01, 0xC0, 0xF0, 0x70, 0x18, 0x06, 0x03, 0x80, 0xE0,
- 0x30, 0x1C, 0x3E, 0x0F, 0x00, 0x60, 0x18, 0x06, 0x03, 0x80, 0xC0, 0x30,
- 0x0F, 0x01, 0xC0, 0x0C, 0x71, 0xC7, 0x18, 0x63, 0x8E, 0x30, 0xC3, 0x1C,
- 0x71, 0x86, 0x38, 0xE3, 0x04, 0x00, 0x0E, 0x07, 0x80, 0xC0, 0x60, 0x70,
- 0x30, 0x18, 0x0C, 0x06, 0x01, 0xC1, 0xE1, 0xC0, 0xC0, 0xE0, 0x70, 0x30,
- 0x38, 0x78, 0x38, 0x00, 0x3C, 0x27, 0xE6, 0xEF, 0xCC, 0x38 };
-
-const GFXglyph FreeMonoBoldOblique12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 14, 0, 1 }, // 0x20 ' '
- { 0, 6, 15, 14, 6, -14 }, // 0x21 '!'
- { 12, 8, 7, 14, 6, -13 }, // 0x22 '"'
- { 19, 13, 18, 14, 2, -15 }, // 0x23 '#'
- { 49, 11, 20, 14, 3, -16 }, // 0x24 '$'
- { 77, 11, 15, 14, 3, -14 }, // 0x25 '%'
- { 98, 11, 13, 14, 2, -12 }, // 0x26 '&'
- { 116, 3, 7, 14, 8, -13 }, // 0x27 '''
- { 119, 7, 19, 14, 7, -14 }, // 0x28 '('
- { 136, 7, 19, 14, 2, -14 }, // 0x29 ')'
- { 153, 11, 10, 14, 4, -14 }, // 0x2A '*'
- { 167, 12, 13, 14, 3, -12 }, // 0x2B '+'
- { 187, 6, 7, 14, 3, -2 }, // 0x2C ','
- { 193, 13, 2, 14, 2, -7 }, // 0x2D '-'
- { 197, 3, 3, 14, 6, -2 }, // 0x2E '.'
- { 199, 14, 20, 14, 2, -16 }, // 0x2F '/'
- { 234, 11, 15, 14, 3, -14 }, // 0x30 '0'
- { 255, 11, 15, 14, 2, -14 }, // 0x31 '1'
- { 276, 13, 15, 14, 1, -14 }, // 0x32 '2'
- { 301, 12, 15, 14, 2, -14 }, // 0x33 '3'
- { 324, 11, 14, 14, 3, -13 }, // 0x34 '4'
- { 344, 12, 15, 14, 2, -14 }, // 0x35 '5'
- { 367, 11, 15, 14, 4, -14 }, // 0x36 '6'
- { 388, 11, 15, 14, 4, -14 }, // 0x37 '7'
- { 409, 11, 15, 14, 3, -14 }, // 0x38 '8'
- { 430, 11, 15, 14, 3, -14 }, // 0x39 '9'
- { 451, 5, 11, 14, 5, -10 }, // 0x3A ':'
- { 458, 7, 15, 14, 3, -10 }, // 0x3B ';'
- { 472, 13, 11, 14, 2, -11 }, // 0x3C '<'
- { 490, 13, 7, 14, 2, -9 }, // 0x3D '='
- { 502, 13, 11, 14, 2, -11 }, // 0x3E '>'
- { 520, 9, 14, 14, 5, -13 }, // 0x3F '?'
- { 536, 12, 19, 14, 2, -14 }, // 0x40 '@'
- { 565, 15, 14, 14, 0, -13 }, // 0x41 'A'
- { 592, 13, 14, 14, 1, -13 }, // 0x42 'B'
- { 615, 14, 14, 14, 2, -13 }, // 0x43 'C'
- { 640, 13, 14, 14, 1, -13 }, // 0x44 'D'
- { 663, 15, 14, 14, 0, -13 }, // 0x45 'E'
- { 690, 16, 14, 14, 0, -13 }, // 0x46 'F'
- { 718, 14, 14, 14, 1, -13 }, // 0x47 'G'
- { 743, 16, 14, 14, 0, -13 }, // 0x48 'H'
- { 771, 12, 14, 14, 2, -13 }, // 0x49 'I'
- { 792, 16, 14, 14, 0, -13 }, // 0x4A 'J'
- { 820, 16, 14, 14, 0, -13 }, // 0x4B 'K'
- { 848, 13, 14, 14, 1, -13 }, // 0x4C 'L'
- { 871, 18, 14, 14, 0, -13 }, // 0x4D 'M'
- { 903, 16, 14, 14, 1, -13 }, // 0x4E 'N'
- { 931, 14, 14, 14, 1, -13 }, // 0x4F 'O'
- { 956, 13, 14, 14, 1, -13 }, // 0x50 'P'
- { 979, 14, 17, 14, 1, -13 }, // 0x51 'Q'
- { 1009, 15, 14, 14, 0, -13 }, // 0x52 'R'
- { 1036, 12, 14, 14, 3, -13 }, // 0x53 'S'
- { 1057, 13, 14, 14, 2, -13 }, // 0x54 'T'
- { 1080, 14, 14, 14, 2, -13 }, // 0x55 'U'
- { 1105, 15, 14, 14, 1, -13 }, // 0x56 'V'
- { 1132, 15, 14, 14, 1, -13 }, // 0x57 'W'
- { 1159, 16, 14, 14, 0, -13 }, // 0x58 'X'
- { 1187, 13, 14, 14, 2, -13 }, // 0x59 'Y'
- { 1210, 14, 14, 14, 1, -13 }, // 0x5A 'Z'
- { 1235, 9, 19, 14, 5, -14 }, // 0x5B '['
- { 1257, 7, 20, 14, 5, -16 }, // 0x5C '\'
- { 1275, 9, 19, 14, 3, -14 }, // 0x5D ']'
- { 1297, 10, 8, 14, 4, -15 }, // 0x5E '^'
- { 1307, 15, 2, 14, -1, 4 }, // 0x5F '_'
- { 1311, 4, 4, 14, 7, -15 }, // 0x60 '`'
- { 1313, 12, 11, 14, 2, -10 }, // 0x61 'a'
- { 1330, 15, 15, 14, -1, -14 }, // 0x62 'b'
- { 1359, 12, 11, 14, 2, -10 }, // 0x63 'c'
- { 1376, 14, 15, 14, 2, -14 }, // 0x64 'd'
- { 1403, 12, 11, 14, 2, -10 }, // 0x65 'e'
- { 1420, 15, 15, 14, 2, -14 }, // 0x66 'f'
- { 1449, 14, 16, 14, 2, -10 }, // 0x67 'g'
- { 1477, 13, 15, 14, 1, -14 }, // 0x68 'h'
- { 1502, 11, 14, 14, 2, -13 }, // 0x69 'i'
- { 1522, 12, 19, 14, 1, -13 }, // 0x6A 'j'
- { 1551, 14, 15, 14, 1, -14 }, // 0x6B 'k'
- { 1578, 11, 15, 14, 2, -14 }, // 0x6C 'l'
- { 1599, 15, 11, 14, 0, -10 }, // 0x6D 'm'
- { 1620, 13, 11, 14, 1, -10 }, // 0x6E 'n'
- { 1638, 12, 11, 14, 2, -10 }, // 0x6F 'o'
- { 1655, 16, 16, 14, -1, -10 }, // 0x70 'p'
- { 1687, 15, 16, 14, 1, -10 }, // 0x71 'q'
- { 1717, 14, 11, 14, 1, -10 }, // 0x72 'r'
- { 1737, 12, 11, 14, 2, -10 }, // 0x73 's'
- { 1754, 10, 14, 14, 2, -13 }, // 0x74 't'
- { 1772, 12, 11, 14, 2, -10 }, // 0x75 'u'
- { 1789, 15, 11, 14, 1, -10 }, // 0x76 'v'
- { 1810, 14, 11, 14, 2, -10 }, // 0x77 'w'
- { 1830, 14, 11, 14, 1, -10 }, // 0x78 'x'
- { 1850, 16, 16, 14, 0, -10 }, // 0x79 'y'
- { 1882, 12, 11, 14, 2, -10 }, // 0x7A 'z'
- { 1899, 10, 19, 14, 4, -14 }, // 0x7B '{'
- { 1923, 6, 19, 14, 5, -14 }, // 0x7C '|'
- { 1938, 9, 19, 14, 3, -14 }, // 0x7D '}'
- { 1960, 12, 4, 14, 3, -7 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBoldOblique12pt7b PROGMEM = {
- (uint8_t *)FreeMonoBoldOblique12pt7bBitmaps,
- (GFXglyph *)FreeMonoBoldOblique12pt7bGlyphs,
- 0x20, 0x7E, 24 };
-
-// Approx. 2638 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique18pt7b.h
deleted file mode 100644
index bc4f20e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique18pt7b.h
+++ /dev/null
@@ -1,460 +0,0 @@
-const uint8_t FreeMonoBoldOblique18pt7bBitmaps[] PROGMEM = {
- 0x0F, 0x07, 0xC7, 0xE3, 0xF1, 0xF0, 0xF8, 0xFC, 0x7C, 0x3E, 0x1F, 0x0F,
- 0x07, 0x87, 0xC3, 0xC1, 0xE0, 0x60, 0x00, 0x38, 0x3E, 0x1F, 0x0F, 0x83,
- 0x80, 0xF8, 0xFF, 0x0E, 0xF1, 0xEF, 0x1E, 0xE1, 0xCE, 0x1C, 0xC1, 0xCC,
- 0x18, 0xC1, 0x88, 0x18, 0x00, 0xE3, 0x80, 0x79, 0xE0, 0x1C, 0x70, 0x07,
- 0x1C, 0x03, 0xCF, 0x00, 0xF3, 0xC0, 0x38, 0xE0, 0x7F, 0xFF, 0x3F, 0xFF,
- 0xCF, 0xFF, 0xF3, 0xFF, 0xF8, 0x3C, 0xF0, 0x0F, 0x3C, 0x03, 0x8E, 0x0F,
- 0xFF, 0xE3, 0xFF, 0xFC, 0xFF, 0xFF, 0x3F, 0xFF, 0x83, 0xCF, 0x00, 0xF3,
- 0xC0, 0x38, 0xE0, 0x1E, 0x78, 0x07, 0x9E, 0x01, 0xC7, 0x00, 0x71, 0xC0,
- 0x00, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x07, 0x80, 0x03, 0xF0, 0x03, 0xFF,
- 0x81, 0xFF, 0xF0, 0xFF, 0xF8, 0x3C, 0x1E, 0x1E, 0x07, 0x87, 0x80, 0x01,
- 0xF0, 0x00, 0x7F, 0xC0, 0x0F, 0xFC, 0x01, 0xFF, 0x80, 0x07, 0xF0, 0x00,
- 0x3C, 0x70, 0x0F, 0x3C, 0x03, 0xCF, 0x83, 0xE3, 0xFF, 0xF8, 0xFF, 0xFC,
- 0x3F, 0xFE, 0x0C, 0xFE, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x03, 0xC0, 0x00,
- 0xF0, 0x00, 0x18, 0x00, 0x03, 0xC0, 0x0F, 0xE0, 0x1C, 0x70, 0x30, 0x30,
- 0x30, 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1F, 0xC3, 0x0F, 0x1F, 0x01, 0xFC,
- 0x0F, 0xE0, 0x7F, 0x00, 0xF8, 0xF0, 0x83, 0xF8, 0x07, 0x1C, 0x0E, 0x0C,
- 0x0C, 0x0C, 0x0C, 0x1C, 0x0E, 0x38, 0x07, 0xF0, 0x03, 0xC0, 0x00, 0x7A,
- 0x01, 0xFF, 0x03, 0xFF, 0x07, 0xFE, 0x0F, 0x9C, 0x0F, 0x00, 0x0F, 0x00,
- 0x0F, 0x00, 0x07, 0x80, 0x1F, 0x80, 0x3F, 0xC0, 0x7F, 0xCF, 0x79, 0xFF,
- 0xF1, 0xFE, 0xF1, 0xFC, 0xF0, 0xF8, 0xFF, 0xFE, 0xFF, 0xFE, 0x7F, 0xFE,
- 0x1F, 0xBC, 0x7B, 0xFD, 0xEF, 0x73, 0x9C, 0xC6, 0x00, 0x01, 0xC0, 0xF0,
- 0x3C, 0x1E, 0x0F, 0x03, 0xC1, 0xE0, 0x70, 0x3C, 0x0F, 0x07, 0x81, 0xE0,
- 0x78, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3E,
- 0x07, 0x81, 0xE0, 0x7C, 0x1F, 0x03, 0x80, 0x07, 0x03, 0xC0, 0xF8, 0x3E,
- 0x07, 0x81, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0,
- 0xF0, 0x78, 0x1E, 0x07, 0x81, 0xC0, 0xF0, 0x3C, 0x1E, 0x07, 0x83, 0xC1,
- 0xE0, 0x78, 0x3C, 0x0E, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x07, 0x00, 0x0E,
- 0x02, 0x3C, 0x0F, 0xFF, 0xFF, 0xFF, 0xBF, 0xFE, 0x1F, 0xF0, 0x1F, 0x80,
- 0x7F, 0x81, 0xEF, 0x07, 0x8F, 0x0F, 0x1E, 0x08, 0x10, 0x00, 0x00, 0x70,
- 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xE0, 0x00, 0x38, 0x00,
- 0x1E, 0x03, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x0F,
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- 0xE1, 0xE0, 0x01, 0xE1, 0xC0, 0x01, 0xE3, 0xC0, 0x00, 0xF7, 0x80, 0x00,
- 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7C, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x7F,
- 0xF0, 0x00, 0xFF, 0xF8, 0x00, 0xFF, 0xF0, 0x00, 0x7F, 0xF0, 0x00, 0x1F,
- 0xFF, 0xC7, 0xFF, 0xF1, 0xFF, 0xF8, 0xFF, 0xFE, 0x3C, 0x1F, 0x0E, 0x1F,
- 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,
- 0xF8, 0x3C, 0xFF, 0xFF, 0x3F, 0xFF, 0xCF, 0xFF, 0xE3, 0xFF, 0xF8, 0x00,
- 0xF0, 0x1F, 0x03, 0xF0, 0x7E, 0x07, 0x80, 0x70, 0x0F, 0x00, 0xF0, 0x0E,
- 0x00, 0xE0, 0x1E, 0x01, 0xC0, 0xFC, 0x0F, 0x80, 0xF8, 0x0F, 0xC0, 0x3C,
- 0x03, 0xC0, 0x38, 0x03, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0xE0, 0x7E,
- 0x03, 0xE0, 0x1C, 0x00, 0x02, 0x07, 0x07, 0x0F, 0x0F, 0x0E, 0x0E, 0x0E,
- 0x1E, 0x1E, 0x1C, 0x1C, 0x1C, 0x3C, 0x3C, 0x38, 0x38, 0x38, 0x78, 0x78,
- 0x70, 0x70, 0x70, 0xF0, 0xF0, 0xE0, 0xE0, 0x01, 0xC0, 0x1F, 0x00, 0xFC,
- 0x07, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x0F, 0x00,
- 0x78, 0x03, 0xC0, 0x1F, 0x80, 0x7C, 0x03, 0xE0, 0x3F, 0x03, 0xC0, 0x1C,
- 0x00, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x0F, 0xE0, 0x7E, 0x07,
- 0xE0, 0x1E, 0x00, 0x0F, 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xFF, 0xFC, 0xFF,
- 0x3F, 0xFF, 0x0F, 0xF8, 0x03, 0xF8, 0x00, 0xF0 };
-
-const GFXglyph FreeMonoBoldOblique18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 21, 0, 1 }, // 0x20 ' '
- { 0, 9, 22, 21, 9, -21 }, // 0x21 '!'
- { 25, 12, 10, 21, 9, -20 }, // 0x22 '"'
- { 40, 18, 25, 21, 4, -22 }, // 0x23 '#'
- { 97, 18, 28, 21, 4, -23 }, // 0x24 '$'
- { 160, 16, 21, 21, 5, -20 }, // 0x25 '%'
- { 202, 16, 20, 21, 4, -19 }, // 0x26 '&'
- { 242, 5, 10, 21, 12, -20 }, // 0x27 '''
- { 249, 10, 27, 21, 11, -21 }, // 0x28 '('
- { 283, 10, 27, 21, 4, -21 }, // 0x29 ')'
- { 317, 15, 15, 21, 6, -21 }, // 0x2A '*'
- { 346, 18, 19, 21, 4, -18 }, // 0x2B '+'
- { 389, 9, 10, 21, 4, -3 }, // 0x2C ','
- { 401, 18, 4, 21, 4, -11 }, // 0x2D '-'
- { 410, 5, 5, 21, 8, -4 }, // 0x2E '.'
- { 414, 21, 28, 21, 2, -23 }, // 0x2F '/'
- { 488, 17, 23, 21, 5, -22 }, // 0x30 '0'
- { 537, 15, 22, 21, 3, -21 }, // 0x31 '1'
- { 579, 20, 23, 21, 2, -22 }, // 0x32 '2'
- { 637, 18, 23, 21, 3, -22 }, // 0x33 '3'
- { 689, 16, 21, 21, 4, -20 }, // 0x34 '4'
- { 731, 18, 22, 21, 4, -21 }, // 0x35 '5'
- { 781, 19, 23, 21, 5, -22 }, // 0x36 '6'
- { 836, 16, 22, 21, 6, -21 }, // 0x37 '7'
- { 880, 19, 23, 21, 3, -22 }, // 0x38 '8'
- { 935, 18, 23, 21, 4, -22 }, // 0x39 '9'
- { 987, 7, 16, 21, 9, -15 }, // 0x3A ':'
- { 1001, 11, 22, 21, 4, -15 }, // 0x3B ';'
- { 1032, 18, 16, 21, 4, -17 }, // 0x3C '<'
- { 1068, 19, 10, 21, 3, -14 }, // 0x3D '='
- { 1092, 19, 16, 21, 3, -17 }, // 0x3E '>'
- { 1130, 14, 21, 21, 8, -20 }, // 0x3F '?'
- { 1167, 18, 27, 21, 3, -21 }, // 0x40 '@'
- { 1228, 22, 21, 21, 0, -20 }, // 0x41 'A'
- { 1286, 21, 21, 21, 1, -20 }, // 0x42 'B'
- { 1342, 21, 21, 21, 2, -20 }, // 0x43 'C'
- { 1398, 21, 21, 21, 1, -20 }, // 0x44 'D'
- { 1454, 22, 21, 21, 0, -20 }, // 0x45 'E'
- { 1512, 23, 21, 21, 0, -20 }, // 0x46 'F'
- { 1573, 21, 21, 21, 2, -20 }, // 0x47 'G'
- { 1629, 23, 21, 21, 0, -20 }, // 0x48 'H'
- { 1690, 19, 21, 21, 2, -20 }, // 0x49 'I'
- { 1740, 23, 21, 21, 0, -20 }, // 0x4A 'J'
- { 1801, 23, 21, 21, 0, -20 }, // 0x4B 'K'
- { 1862, 20, 21, 21, 1, -20 }, // 0x4C 'L'
- { 1915, 25, 21, 21, 0, -20 }, // 0x4D 'M'
- { 1981, 24, 21, 21, 1, -20 }, // 0x4E 'N'
- { 2044, 20, 21, 21, 2, -20 }, // 0x4F 'O'
- { 2097, 21, 21, 21, 1, -20 }, // 0x50 'P'
- { 2153, 20, 26, 21, 2, -20 }, // 0x51 'Q'
- { 2218, 22, 21, 21, 0, -20 }, // 0x52 'R'
- { 2276, 19, 21, 21, 3, -20 }, // 0x53 'S'
- { 2326, 19, 21, 21, 3, -20 }, // 0x54 'T'
- { 2376, 21, 21, 21, 3, -20 }, // 0x55 'U'
- { 2432, 23, 21, 21, 1, -20 }, // 0x56 'V'
- { 2493, 22, 21, 21, 2, -20 }, // 0x57 'W'
- { 2551, 24, 21, 21, 0, -20 }, // 0x58 'X'
- { 2614, 20, 21, 21, 3, -20 }, // 0x59 'Y'
- { 2667, 19, 21, 21, 2, -20 }, // 0x5A 'Z'
- { 2717, 13, 27, 21, 8, -21 }, // 0x5B '['
- { 2761, 10, 28, 21, 8, -23 }, // 0x5C '\'
- { 2796, 13, 27, 21, 4, -21 }, // 0x5D ']'
- { 2840, 15, 11, 21, 6, -21 }, // 0x5E '^'
- { 2861, 21, 4, 21, -1, 4 }, // 0x5F '_'
- { 2872, 6, 6, 21, 10, -22 }, // 0x60 '`'
- { 2877, 19, 16, 21, 2, -15 }, // 0x61 'a'
- { 2915, 22, 22, 21, 0, -21 }, // 0x62 'b'
- { 2976, 19, 16, 21, 3, -15 }, // 0x63 'c'
- { 3014, 21, 22, 21, 3, -21 }, // 0x64 'd'
- { 3072, 18, 16, 21, 3, -15 }, // 0x65 'e'
- { 3108, 21, 22, 21, 3, -21 }, // 0x66 'f'
- { 3166, 21, 23, 21, 2, -15 }, // 0x67 'g'
- { 3227, 20, 22, 21, 1, -21 }, // 0x68 'h'
- { 3282, 16, 22, 21, 3, -21 }, // 0x69 'i'
- { 3326, 18, 29, 21, 2, -21 }, // 0x6A 'j'
- { 3392, 20, 22, 21, 1, -21 }, // 0x6B 'k'
- { 3447, 16, 22, 21, 3, -21 }, // 0x6C 'l'
- { 3491, 23, 16, 21, 0, -15 }, // 0x6D 'm'
- { 3537, 21, 16, 21, 1, -15 }, // 0x6E 'n'
- { 3579, 18, 16, 21, 3, -15 }, // 0x6F 'o'
- { 3615, 23, 23, 21, -1, -15 }, // 0x70 'p'
- { 3682, 22, 23, 21, 2, -15 }, // 0x71 'q'
- { 3746, 20, 16, 21, 2, -15 }, // 0x72 'r'
- { 3786, 16, 16, 21, 4, -15 }, // 0x73 's'
- { 3818, 16, 21, 21, 4, -20 }, // 0x74 't'
- { 3860, 18, 16, 21, 3, -15 }, // 0x75 'u'
- { 3896, 21, 16, 21, 2, -15 }, // 0x76 'v'
- { 3938, 21, 16, 21, 3, -15 }, // 0x77 'w'
- { 3980, 21, 16, 21, 1, -15 }, // 0x78 'x'
- { 4022, 24, 23, 21, -1, -15 }, // 0x79 'y'
- { 4091, 18, 16, 21, 3, -15 }, // 0x7A 'z'
- { 4127, 12, 27, 21, 8, -21 }, // 0x7B '{'
- { 4168, 8, 27, 21, 8, -21 }, // 0x7C '|'
- { 4195, 13, 27, 21, 4, -21 }, // 0x7D '}'
- { 4239, 17, 8, 21, 4, -13 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBoldOblique18pt7b PROGMEM = {
- (uint8_t *)FreeMonoBoldOblique18pt7bBitmaps,
- (GFXglyph *)FreeMonoBoldOblique18pt7bGlyphs,
- 0x20, 0x7E, 35 };
-
-// Approx. 4928 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique24pt7b.h
deleted file mode 100644
index a2bbbdf..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique24pt7b.h
+++ /dev/null
@@ -1,742 +0,0 @@
-const uint8_t FreeMonoBoldOblique24pt7bBitmaps[] PROGMEM = {
- 0x01, 0xE0, 0x3F, 0x07, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xE0, 0xFE,
- 0x0F, 0xE0, 0xFE, 0x0F, 0xC0, 0xFC, 0x1F, 0xC1, 0xF8, 0x1F, 0x81, 0xF8,
- 0x1F, 0x81, 0xF0, 0x1F, 0x01, 0xF0, 0x1E, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0xC0, 0x7E, 0x0F, 0xE0, 0xFE, 0x0F, 0xC0, 0x78, 0x00, 0x7E,
- 0x1F, 0xBF, 0x0F, 0xDF, 0x87, 0xCF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF1,
- 0xE0, 0xF8, 0xF0, 0x7C, 0x78, 0x3C, 0x38, 0x1E, 0x1C, 0x0F, 0x0E, 0x07,
- 0x0E, 0x03, 0x83, 0x01, 0x80, 0x00, 0x1C, 0x1C, 0x00, 0x3E, 0x3E, 0x00,
- 0x3E, 0x3E, 0x00, 0x3C, 0x3C, 0x00, 0x7C, 0x7C, 0x00, 0x7C, 0x7C, 0x00,
- 0x7C, 0x7C, 0x00, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x0F,
- 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F,
- 0xFF, 0xFE, 0x03, 0xE3, 0xE0, 0x03, 0xE3, 0xE0, 0x03, 0xC3, 0xC0, 0x07,
- 0xC7, 0xC0, 0x7F, 0xFF, 0xF8, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFC, 0xFF,
- 0xFF, 0xF8, 0xFF, 0xFF, 0xF0, 0x0F, 0x0F, 0x00, 0x1F, 0x1F, 0x00, 0x1F,
- 0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x3E, 0x1E, 0x00, 0x3E, 0x3E, 0x00, 0x3E,
- 0x3E, 0x00, 0x3C, 0x3C, 0x00, 0x7C, 0x7C, 0x00, 0x38, 0x38, 0x00, 0x00,
- 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x7C, 0x00,
- 0x00, 0xFF, 0x00, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFE, 0x03, 0xFF, 0xFF,
- 0x01, 0xFF, 0xFF, 0x81, 0xFC, 0x1F, 0xC1, 0xF8, 0x03, 0xC0, 0xF8, 0x01,
- 0xE0, 0x7C, 0x00, 0x40, 0x3F, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x0F, 0xFF,
- 0x80, 0x03, 0xFF, 0xF8, 0x00, 0xFF, 0xFE, 0x00, 0x0F, 0xFF, 0x00, 0x00,
- 0x7F, 0xC0, 0x00, 0x07, 0xE0, 0xE0, 0x01, 0xF0, 0xF0, 0x00, 0xF8, 0xF8,
- 0x00, 0xFC, 0x7E, 0x00, 0xFC, 0x3F, 0x81, 0xFE, 0x1F, 0xFF, 0xFE, 0x0F,
- 0xFF, 0xFE, 0x0F, 0xFF, 0xFE, 0x03, 0xFF, 0xFC, 0x00, 0x07, 0xF0, 0x00,
- 0x01, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7C, 0x00,
- 0x00, 0x3E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0xF8,
- 0x00, 0x0F, 0xF8, 0x00, 0x7F, 0xE0, 0x03, 0xC3, 0xC0, 0x0E, 0x07, 0x00,
- 0x70, 0x1C, 0x01, 0xC0, 0x70, 0x07, 0x01, 0xC0, 0x1C, 0x0E, 0x00, 0x78,
- 0x78, 0x00, 0xFF, 0xC0, 0x03, 0xFE, 0x1F, 0x03, 0xE3, 0xFC, 0x00, 0x7F,
- 0xC0, 0x0F, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xC0, 0x03, 0xF8, 0x7C, 0x0F,
- 0x07, 0xFC, 0x00, 0x3F, 0xF0, 0x01, 0xE1, 0xE0, 0x07, 0x03, 0x80, 0x38,
- 0x0E, 0x00, 0xE0, 0x38, 0x03, 0x80, 0xE0, 0x0E, 0x07, 0x00, 0x3C, 0x3C,
- 0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1F, 0x00,
- 0x01, 0xFF, 0x80, 0x3F, 0xFC, 0x03, 0xFF, 0xE0, 0x1F, 0xFE, 0x01, 0xF1,
- 0xE0, 0x1F, 0x04, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01,
- 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x07, 0xF8, 0x00, 0x7F, 0xE3,
- 0xE7, 0xFF, 0x3F, 0x7E, 0xFF, 0xFB, 0xE7, 0xFF, 0x9E, 0x1F, 0xF1, 0xF0,
- 0xFF, 0x8F, 0x83, 0xF8, 0x7C, 0x1F, 0xC3, 0xF0, 0xFF, 0x9F, 0xFF, 0xFC,
- 0x7F, 0xFF, 0xE3, 0xFF, 0xFF, 0x0F, 0xFD, 0xF0, 0x1F, 0x80, 0x00, 0x7E,
- 0xFD, 0xF3, 0xE7, 0xCF, 0x3E, 0x7C, 0xF1, 0xE3, 0xC7, 0x0E, 0x18, 0x00,
- 0x00, 0x18, 0x00, 0xF0, 0x07, 0xC0, 0x3F, 0x01, 0xF8, 0x07, 0xC0, 0x3E,
- 0x01, 0xF8, 0x07, 0xC0, 0x3E, 0x00, 0xF8, 0x07, 0xC0, 0x1F, 0x00, 0xF8,
- 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x3E, 0x00, 0xF8,
- 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,
- 0x00, 0xFC, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x80, 0x7E, 0x00, 0xFC, 0x03,
- 0xF0, 0x07, 0xC0, 0x1E, 0x00, 0x00, 0xC0, 0x07, 0x80, 0x3F, 0x00, 0xFC,
- 0x03, 0xF0, 0x07, 0xE0, 0x1F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xF0, 0x07,
- 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01,
- 0xF0, 0x07, 0xC0, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01,
- 0xF0, 0x0F, 0x80, 0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x3E, 0x01, 0xF0, 0x0F,
- 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x00, 0xF0, 0x00, 0x00, 0x3C,
- 0x00, 0x01, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x08,
- 0x3C, 0x09, 0xF9, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF,
- 0x87, 0xFF, 0xE0, 0x07, 0xF8, 0x00, 0x7F, 0xC0, 0x07, 0xFF, 0x00, 0x7F,
- 0xF8, 0x07, 0xE7, 0xE0, 0x3E, 0x3F, 0x01, 0xE0, 0xF8, 0x0E, 0x07, 0x80,
- 0x00, 0x07, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x0F, 0x00,
- 0x00, 0x1F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1E, 0x00,
- 0x00, 0x3E, 0x00, 0x00, 0x3E, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7C, 0x00,
- 0x00, 0x78, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00,
- 0x00, 0xF8, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xF0, 0x00,
- 0x01, 0xF0, 0x00, 0x00, 0xE0, 0x00, 0x03, 0xF0, 0x7E, 0x07, 0xC0, 0xFC,
- 0x0F, 0x81, 0xF0, 0x1E, 0x03, 0xE0, 0x3C, 0x07, 0x80, 0x78, 0x0F, 0x00,
- 0xE0, 0x0C, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0xFF, 0xFF, 0xFF, 0xCF, 0x00,
- 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xF0, 0x00,
- 0x00, 0x3E, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0F,
- 0x80, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x03, 0xE0, 0x00,
- 0x00, 0x3E, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1F,
- 0x80, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x07, 0xE0, 0x00,
- 0x00, 0x7C, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x1F,
- 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0, 0x00,
- 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x3E,
- 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0x80, 0x00,
- 0x01, 0xF0, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C,
- 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x07, 0x00, 0x00,
- 0x00, 0x00, 0x0F, 0xC0, 0x00, 0xFF, 0xE0, 0x03, 0xFF, 0xE0, 0x1F, 0xFF,
- 0xE0, 0x7F, 0xFF, 0xC0, 0xFC, 0x1F, 0x83, 0xF0, 0x1F, 0x8F, 0xC0, 0x1F,
- 0x1F, 0x00, 0x3E, 0x7C, 0x00, 0x7C, 0xF8, 0x00, 0xF9, 0xF0, 0x01, 0xF3,
- 0xC0, 0x07, 0xCF, 0x80, 0x0F, 0x9F, 0x00, 0x1E, 0x3E, 0x00, 0x3C, 0x78,
- 0x00, 0xF8, 0xF0, 0x01, 0xF3, 0xE0, 0x03, 0xE7, 0xC0, 0x07, 0x8F, 0x80,
- 0x1F, 0x1F, 0x00, 0x3E, 0x3E, 0x00, 0xF8, 0x7C, 0x01, 0xF0, 0xFC, 0x07,
- 0xC1, 0xFC, 0x3F, 0x81, 0xFF, 0xFE, 0x03, 0xFF, 0xF8, 0x03, 0xFF, 0xE0,
- 0x03, 0xFF, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x7E,
- 0x00, 0x0F, 0xF0, 0x01, 0xFF, 0x80, 0x1F, 0xFC, 0x03, 0xFB, 0xE0, 0x1F,
- 0x9E, 0x00, 0xF1, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0,
- 0x00, 0x1E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03,
- 0xC0, 0x00, 0x1E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00,
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- 0xE0, 0x7C, 0x00, 0x1F, 0x03, 0xE0, 0x00, 0xF8, 0x1E, 0x00, 0x07, 0xC1,
- 0xF0, 0x00, 0x3E, 0x0F, 0x80, 0x01, 0xE0, 0x7C, 0x00, 0x1F, 0x03, 0xF0,
- 0x01, 0xF8, 0x1F, 0x80, 0x1F, 0xC0, 0xFF, 0x03, 0xFC, 0x03, 0xFF, 0xFF,
- 0xE0, 0x1F, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xF8, 0x00, 0xFF, 0xE7, 0xC0,
- 0x01, 0xFC, 0x3C, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x1F, 0x00, 0x00,
- 0x00, 0xF8, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xFF, 0x80, 0x00, 0x7F,
- 0xFE, 0x00, 0x07, 0xFF, 0xF0, 0x00, 0x3F, 0xFF, 0x00, 0x00, 0xFF, 0xF0,
- 0x00, 0x00, 0x00, 0x0F, 0x80, 0x3F, 0xC3, 0xFE, 0x07, 0xFC, 0xFF, 0xE0,
- 0x7F, 0xDF, 0xFF, 0x07, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0x1C, 0x00, 0x7F,
- 0xC0, 0x00, 0x07, 0xF0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x0F, 0xC0, 0x00,
- 0x00, 0xF8, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1F,
- 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x01, 0xE0, 0x00,
- 0x07, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0x00, 0xFF,
- 0xFF, 0xF0, 0x07, 0xFF, 0xFE, 0x00, 0x00, 0x3F, 0xCE, 0x03, 0xFF, 0xFC,
- 0x0F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC3, 0xF8, 0x0F, 0x87,
- 0xC0, 0x0E, 0x0F, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xFF, 0x80, 0x3F,
- 0xFF, 0xC0, 0x3F, 0xFF, 0xC0, 0x1F, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x00,
- 0x3F, 0x1C, 0x00, 0x3E, 0x7C, 0x00, 0x7C, 0xFC, 0x03, 0xF3, 0xFF, 0xFF,
- 0xE7, 0xFF, 0xFF, 0x8F, 0xFF, 0xFE, 0x1F, 0xFF, 0xF0, 0x00, 0xFF, 0x00,
- 0x00, 0x03, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07,
- 0x80, 0x00, 0x78, 0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xE1, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xE0, 0x00,
- 0x1E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3C, 0x00,
- 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00, 0xF7, 0xFF,
- 0xFF, 0x7F, 0xFF, 0xF3, 0xFF, 0xFE, 0x1F, 0xFF, 0x80, 0x7F, 0x80, 0x7F,
- 0x01, 0xFF, 0xFE, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xF0, 0x3F, 0xFF, 0xE0,
- 0x3F, 0xC7, 0xC0, 0x07, 0x8F, 0x80, 0x1F, 0x3E, 0x00, 0x3E, 0x7C, 0x00,
- 0x7C, 0xF8, 0x00, 0xF1, 0xF0, 0x03, 0xE3, 0xE0, 0x07, 0xC7, 0xC0, 0x0F,
- 0x8F, 0x80, 0x1F, 0x1F, 0x00, 0x7C, 0x3E, 0x01, 0xF8, 0x7E, 0x0F, 0xFC,
- 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xF1, 0xFF, 0xEF, 0xE1, 0xFF, 0xBF, 0x80,
- 0xFC, 0x00, 0x00, 0x7F, 0xF0, 0x7F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF0,
- 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xE1, 0xF8, 0x03, 0xE0,
- 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x07, 0xC0, 0x0F, 0x80, 0xF8, 0x00, 0xFC,
- 0x1F, 0x80, 0x07, 0xC1, 0xF0, 0x00, 0x7C, 0x3E, 0x00, 0x07, 0xE7, 0xE0,
- 0x00, 0x3E, 0x7C, 0x00, 0x03, 0xEF, 0x80, 0x00, 0x3F, 0xF0, 0x00, 0x03,
- 0xFF, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F, 0xC0,
- 0x00, 0x00, 0xF8, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0xEF, 0xFC, 0x03, 0xFF,
- 0xFF, 0xC0, 0x7F, 0xFF, 0xFC, 0x07, 0xFE, 0x7F, 0x80, 0x3F, 0xC3, 0xE1,
- 0xF0, 0xF8, 0x3E, 0x3F, 0x0F, 0x03, 0xE3, 0xF1, 0xF0, 0x3E, 0x7F, 0x1E,
- 0x03, 0xE7, 0xF3, 0xE0, 0x3E, 0xFF, 0xBC, 0x03, 0xFF, 0xFF, 0xC0, 0x3F,
- 0xFF, 0xFC, 0x03, 0xFE, 0xFF, 0x80, 0x3F, 0xEF, 0xF8, 0x03, 0xFC, 0xFF,
- 0x00, 0x3F, 0x8F, 0xF0, 0x03, 0xF8, 0x7E, 0x00, 0x3F, 0x07, 0xE0, 0x01,
- 0xF0, 0x7C, 0x00, 0x1E, 0x07, 0xC0, 0x00, 0x03, 0xFE, 0x0F, 0xF8, 0x3F,
- 0xF0, 0xFF, 0xC1, 0xFF, 0x8F, 0xFE, 0x0F, 0xFC, 0x7F, 0xF0, 0x7F, 0xC1,
- 0xFF, 0x00, 0xFE, 0x1F, 0xC0, 0x03, 0xF9, 0xFC, 0x00, 0x0F, 0xFF, 0xC0,
- 0x00, 0x3F, 0xF8, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00,
- 0x7F, 0xE0, 0x00, 0x0F, 0xFF, 0x80, 0x00, 0xFE, 0xFE, 0x00, 0x0F, 0xE3,
- 0xF8, 0x00, 0xFE, 0x0F, 0xE0, 0x3F, 0xE0, 0x7F, 0xC3, 0xFF, 0x87, 0xFF,
- 0x3F, 0xFC, 0x7F, 0xF9, 0xFF, 0xE3, 0xFF, 0x87, 0xFE, 0x0F, 0xF8, 0x00,
- 0x01, 0xFE, 0x03, 0xFE, 0x03, 0xFF, 0x07, 0xFF, 0x07, 0xFF, 0x07, 0xFF,
- 0x07, 0xFF, 0x07, 0xFE, 0x03, 0xFC, 0x03, 0xFC, 0x01, 0xF8, 0x01, 0xF0,
- 0x00, 0xF8, 0x03, 0xF0, 0x00, 0xF8, 0x03, 0xE0, 0x00, 0xFC, 0x07, 0xC0,
- 0x00, 0x7C, 0x0F, 0x80, 0x00, 0x7C, 0x0F, 0x80, 0x00, 0x7E, 0x1F, 0x00,
- 0x00, 0x7E, 0x3E, 0x00, 0x00, 0x3E, 0x7C, 0x00, 0x00, 0x3E, 0x7C, 0x00,
- 0x00, 0x3F, 0xF8, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0x1F, 0xE0, 0x00,
- 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0x0F, 0x80, 0x00,
- 0x00, 0x1F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00,
- 0x00, 0x7C, 0x00, 0x00, 0x7F, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00,
- 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x7F, 0xFE, 0x00, 0x00,
- 0x07, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF,
- 0xE0, 0xFF, 0xFF, 0xE0, 0x7C, 0x0F, 0xE0, 0x3C, 0x0F, 0xE0, 0x1E, 0x0F,
- 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F,
- 0x80, 0x00, 0x3F, 0x80, 0x00, 0x3F, 0x80, 0x00, 0x3F, 0x80, 0xF0, 0x3F,
- 0x00, 0xF8, 0x3F, 0xFF, 0xFC, 0x3F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFE, 0x0F,
- 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x00, 0x1F, 0xC0, 0x1F,
- 0xE0, 0x1F, 0xF0, 0x0F, 0xE0, 0x0F, 0xC0, 0x07, 0xC0, 0x07, 0xC0, 0x03,
- 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x78, 0x00, 0x7C, 0x00, 0x3E, 0x00,
- 0x1F, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x3F, 0x80, 0x3F, 0xC0, 0x1F, 0xC0,
- 0x0F, 0xE0, 0x07, 0xF8, 0x00, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F,
- 0x80, 0x07, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00,
- 0x7E, 0x00, 0x3F, 0x80, 0x1F, 0xE0, 0x07, 0xF0, 0x03, 0xF8, 0x00, 0x78,
- 0x00, 0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0x80, 0xF0, 0x3E,
- 0x07, 0xC0, 0xF0, 0x1E, 0x03, 0xC0, 0xF8, 0x1F, 0x03, 0xC0, 0x78, 0x0F,
- 0x03, 0xE0, 0x7C, 0x0F, 0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xF0, 0x3C, 0x07,
- 0x80, 0xF0, 0x3E, 0x07, 0xC0, 0xF0, 0x1E, 0x07, 0xC0, 0xF8, 0x1F, 0x03,
- 0xC0, 0x70, 0x00, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0x7F, 0x00, 0x3F, 0xC0,
- 0x0F, 0xE0, 0x03, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F,
- 0x00, 0x0F, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,
- 0xF8, 0x00, 0x7E, 0x00, 0x3F, 0xC0, 0x0F, 0xE0, 0x07, 0xF0, 0x07, 0xF8,
- 0x07, 0xF8, 0x03, 0xE0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF0, 0x00, 0x78,
- 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x00, 0x1F, 0x80, 0x7F,
- 0xC0, 0x7F, 0xC0, 0x3F, 0xC0, 0x1F, 0xC0, 0x07, 0x80, 0x00, 0x03, 0xE0,
- 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xE0, 0x39, 0xFF, 0xE0, 0xF7, 0xFF, 0xE7,
- 0xFF, 0xCF, 0xFF, 0xFE, 0x0F, 0xFF, 0x38, 0x0F, 0xFC, 0x00, 0x0F, 0xE0,
- 0x00, 0x0F, 0x80 };
-
-const GFXglyph FreeMonoBoldOblique24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 28, 0, 1 }, // 0x20 ' '
- { 0, 12, 31, 28, 12, -29 }, // 0x21 '!'
- { 47, 17, 14, 28, 11, -28 }, // 0x22 '"'
- { 77, 24, 34, 28, 5, -30 }, // 0x23 '#'
- { 179, 25, 38, 28, 4, -31 }, // 0x24 '$'
- { 298, 22, 30, 28, 6, -28 }, // 0x25 '%'
- { 381, 21, 28, 28, 5, -26 }, // 0x26 '&'
- { 455, 7, 14, 28, 16, -28 }, // 0x27 '''
- { 468, 14, 37, 28, 14, -29 }, // 0x28 '('
- { 533, 14, 37, 28, 5, -29 }, // 0x29 ')'
- { 598, 21, 19, 28, 8, -28 }, // 0x2A '*'
- { 648, 24, 26, 28, 5, -25 }, // 0x2B '+'
- { 726, 12, 14, 28, 6, -6 }, // 0x2C ','
- { 747, 24, 5, 28, 5, -15 }, // 0x2D '-'
- { 762, 7, 6, 28, 11, -4 }, // 0x2E '.'
- { 768, 28, 38, 28, 3, -32 }, // 0x2F '/'
- { 901, 23, 31, 28, 6, -29 }, // 0x30 '0'
- { 991, 21, 30, 28, 4, -29 }, // 0x31 '1'
- { 1070, 26, 30, 28, 3, -29 }, // 0x32 '2'
- { 1168, 25, 31, 28, 4, -29 }, // 0x33 '3'
- { 1265, 22, 28, 28, 5, -27 }, // 0x34 '4'
- { 1342, 25, 31, 28, 4, -29 }, // 0x35 '5'
- { 1439, 24, 31, 28, 7, -29 }, // 0x36 '6'
- { 1532, 22, 30, 28, 9, -29 }, // 0x37 '7'
- { 1615, 23, 31, 28, 6, -29 }, // 0x38 '8'
- { 1705, 24, 31, 28, 5, -29 }, // 0x39 '9'
- { 1798, 10, 22, 28, 11, -20 }, // 0x3A ':'
- { 1826, 15, 28, 28, 5, -20 }, // 0x3B ';'
- { 1879, 25, 21, 28, 5, -23 }, // 0x3C '<'
- { 1945, 26, 14, 28, 4, -19 }, // 0x3D '='
- { 1991, 25, 22, 28, 4, -23 }, // 0x3E '>'
- { 2060, 19, 29, 28, 10, -27 }, // 0x3F '?'
- { 2129, 23, 36, 28, 5, -28 }, // 0x40 '@'
- { 2233, 30, 27, 28, 0, -26 }, // 0x41 'A'
- { 2335, 29, 27, 28, 1, -26 }, // 0x42 'B'
- { 2433, 28, 29, 28, 3, -27 }, // 0x43 'C'
- { 2535, 28, 27, 28, 1, -26 }, // 0x44 'D'
- { 2630, 29, 27, 28, 1, -26 }, // 0x45 'E'
- { 2728, 31, 27, 28, 0, -26 }, // 0x46 'F'
- { 2833, 28, 29, 28, 3, -27 }, // 0x47 'G'
- { 2935, 30, 27, 28, 1, -26 }, // 0x48 'H'
- { 3037, 25, 27, 28, 3, -26 }, // 0x49 'I'
- { 3122, 31, 28, 28, 0, -26 }, // 0x4A 'J'
- { 3231, 31, 27, 28, 0, -26 }, // 0x4B 'K'
- { 3336, 27, 27, 28, 1, -26 }, // 0x4C 'L'
- { 3428, 34, 27, 28, 0, -26 }, // 0x4D 'M'
- { 3543, 32, 27, 28, 1, -26 }, // 0x4E 'N'
- { 3651, 27, 29, 28, 3, -27 }, // 0x4F 'O'
- { 3749, 28, 27, 28, 1, -26 }, // 0x50 'P'
- { 3844, 27, 35, 28, 3, -27 }, // 0x51 'Q'
- { 3963, 29, 27, 28, 0, -26 }, // 0x52 'R'
- { 4061, 26, 29, 28, 3, -27 }, // 0x53 'S'
- { 4156, 26, 27, 28, 4, -26 }, // 0x54 'T'
- { 4244, 28, 28, 28, 4, -26 }, // 0x55 'U'
- { 4342, 30, 27, 28, 2, -26 }, // 0x56 'V'
- { 4444, 29, 27, 28, 3, -26 }, // 0x57 'W'
- { 4542, 32, 27, 28, 0, -26 }, // 0x58 'X'
- { 4650, 26, 27, 28, 4, -26 }, // 0x59 'Y'
- { 4738, 27, 27, 28, 2, -26 }, // 0x5A 'Z'
- { 4830, 18, 37, 28, 10, -29 }, // 0x5B '['
- { 4914, 13, 38, 28, 10, -32 }, // 0x5C '\'
- { 4976, 18, 37, 28, 5, -29 }, // 0x5D ']'
- { 5060, 20, 15, 28, 8, -29 }, // 0x5E '^'
- { 5098, 29, 5, 28, -2, 5 }, // 0x5F '_'
- { 5117, 8, 8, 28, 13, -30 }, // 0x60 '`'
- { 5125, 24, 23, 28, 3, -21 }, // 0x61 'a'
- { 5194, 29, 31, 28, 0, -29 }, // 0x62 'b'
- { 5307, 25, 23, 28, 3, -21 }, // 0x63 'c'
- { 5379, 28, 31, 28, 3, -29 }, // 0x64 'd'
- { 5488, 24, 23, 28, 3, -21 }, // 0x65 'e'
- { 5557, 28, 30, 28, 4, -29 }, // 0x66 'f'
- { 5662, 28, 31, 28, 3, -21 }, // 0x67 'g'
- { 5771, 26, 30, 28, 2, -29 }, // 0x68 'h'
- { 5869, 23, 29, 28, 3, -28 }, // 0x69 'i'
- { 5953, 23, 38, 28, 3, -28 }, // 0x6A 'j'
- { 6063, 26, 30, 28, 2, -29 }, // 0x6B 'k'
- { 6161, 23, 30, 28, 3, -29 }, // 0x6C 'l'
- { 6248, 30, 22, 28, 0, -21 }, // 0x6D 'm'
- { 6331, 26, 22, 28, 2, -21 }, // 0x6E 'n'
- { 6403, 25, 23, 28, 3, -21 }, // 0x6F 'o'
- { 6475, 31, 31, 28, -1, -21 }, // 0x70 'p'
- { 6596, 29, 31, 28, 2, -21 }, // 0x71 'q'
- { 6709, 28, 22, 28, 2, -21 }, // 0x72 'r'
- { 6786, 23, 23, 28, 4, -21 }, // 0x73 's'
- { 6853, 20, 28, 28, 5, -26 }, // 0x74 't'
- { 6923, 23, 22, 28, 5, -20 }, // 0x75 'u'
- { 6987, 28, 21, 28, 3, -20 }, // 0x76 'v'
- { 7061, 28, 21, 28, 3, -20 }, // 0x77 'w'
- { 7135, 29, 21, 28, 1, -20 }, // 0x78 'x'
- { 7212, 32, 30, 28, -1, -20 }, // 0x79 'y'
- { 7332, 25, 21, 28, 4, -20 }, // 0x7A 'z'
- { 7398, 17, 37, 28, 10, -29 }, // 0x7B '{'
- { 7477, 11, 36, 28, 11, -28 }, // 0x7C '|'
- { 7527, 17, 37, 28, 6, -29 }, // 0x7D '}'
- { 7606, 23, 10, 28, 5, -17 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBoldOblique24pt7b PROGMEM = {
- (uint8_t *)FreeMonoBoldOblique24pt7bBitmaps,
- (GFXglyph *)FreeMonoBoldOblique24pt7bGlyphs,
- 0x20, 0x7E, 47 };
-
-// Approx. 8307 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique9pt7b.h
deleted file mode 100644
index b530723..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoBoldOblique9pt7b.h
+++ /dev/null
@@ -1,203 +0,0 @@
-const uint8_t FreeMonoBoldOblique9pt7bBitmaps[] PROGMEM = {
- 0x39, 0xCC, 0x67, 0x31, 0x8C, 0x07, 0x38, 0x6C, 0xD9, 0x36, 0x48, 0x80,
- 0x09, 0x0D, 0x86, 0xCF, 0xF7, 0xF9, 0xB3, 0xFD, 0xFE, 0x6C, 0x36, 0x1B,
- 0x00, 0x00, 0x06, 0x07, 0x07, 0xE6, 0x33, 0x01, 0xE0, 0x7C, 0x06, 0x43,
- 0x33, 0xBF, 0x83, 0x03, 0x00, 0x80, 0x1C, 0x11, 0x10, 0x88, 0x83, 0xB8,
- 0xF3, 0xB8, 0x22, 0x21, 0x11, 0x07, 0x00, 0x0F, 0x1F, 0x30, 0x30, 0x38,
- 0x7B, 0xDF, 0xCE, 0xFF, 0x7E, 0xFA, 0x80, 0x19, 0x8C, 0xC6, 0x63, 0x18,
- 0xC6, 0x31, 0xC6, 0x30, 0x31, 0xC6, 0x31, 0x8C, 0x63, 0x31, 0x98, 0xCC,
- 0x40, 0x08, 0x08, 0xFF, 0xFF, 0x38, 0x6C, 0x6C, 0x0C, 0x06, 0x03, 0x1F,
- 0xFF, 0xF8, 0xC0, 0x60, 0x30, 0x10, 0x00, 0x36, 0x4C, 0x80, 0xFF, 0xFF,
- 0xC0, 0xFC, 0x00, 0x00, 0x0C, 0x03, 0x00, 0xC0, 0x18, 0x06, 0x01, 0x80,
- 0x30, 0x0C, 0x03, 0x00, 0x60, 0x18, 0x06, 0x00, 0xC0, 0x30, 0x00, 0x0F,
- 0x0F, 0xCC, 0x6C, 0x36, 0x1B, 0x0D, 0x05, 0x86, 0xC3, 0x63, 0x3F, 0x8F,
- 0x00, 0x06, 0x1C, 0x3C, 0x6C, 0x0C, 0x0C, 0x08, 0x18, 0x18, 0x18, 0xFE,
- 0xFE, 0x07, 0x83, 0xF1, 0x8C, 0x43, 0x00, 0xC0, 0xE0, 0x70, 0x38, 0x38,
- 0x1C, 0x6F, 0xF3, 0xFC, 0x1F, 0x1F, 0xC0, 0x60, 0x30, 0x30, 0x70, 0x38,
- 0x06, 0x03, 0x03, 0xBF, 0x9F, 0x80, 0x03, 0x07, 0x0B, 0x1B, 0x32, 0x66,
- 0xFF, 0xFF, 0x1E, 0x1E, 0x3F, 0x9F, 0x98, 0x0F, 0xC7, 0xF3, 0x18, 0x0C,
- 0x06, 0x06, 0x7F, 0x1E, 0x00, 0x07, 0x87, 0xCE, 0x06, 0x06, 0x03, 0xF3,
- 0xFD, 0xC6, 0xC3, 0x63, 0xBF, 0x8F, 0x80, 0xFF, 0xFF, 0xC3, 0x06, 0x06,
- 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60, 0x1F, 0x1F, 0xDC, 0x6C, 0x36, 0x31,
- 0xF1, 0xF8, 0xC6, 0xC3, 0x63, 0xBF, 0x8F, 0x80, 0x1E, 0x3F, 0x33, 0x63,
- 0x63, 0x67, 0x7F, 0x3E, 0x06, 0x1C, 0xF8, 0xF0, 0x77, 0x00, 0x00, 0xEE,
- 0x1C, 0x70, 0x00, 0x00, 0x03, 0x0C, 0x61, 0x08, 0x00, 0x00, 0xC1, 0xE1,
- 0xE1, 0xE0, 0xF0, 0x07, 0x00, 0xF0, 0x0C, 0x7F, 0xDF, 0xF0, 0x00, 0x00,
- 0x7F, 0xFF, 0xF0, 0x30, 0x0F, 0x00, 0xE0, 0x1E, 0x07, 0xC7, 0x87, 0x83,
- 0x00, 0x7D, 0xFF, 0x18, 0x30, 0xE3, 0x9C, 0x30, 0x01, 0xC3, 0x80, 0x0F,
- 0x0F, 0xCC, 0x6C, 0x36, 0x72, 0x79, 0x7D, 0xB6, 0xDA, 0x6F, 0xB3, 0xD8,
- 0x0C, 0x07, 0xE1, 0xE0, 0x0F, 0x83, 0xF0, 0x1E, 0x03, 0xC0, 0xD8, 0x31,
- 0x87, 0xF1, 0xFE, 0x30, 0xDF, 0x3F, 0xC7, 0x80, 0x3F, 0xC7, 0xFC, 0x61,
- 0x8C, 0x31, 0xFC, 0x3F, 0x84, 0x19, 0x83, 0x30, 0x6F, 0xFB, 0xFE, 0x00,
- 0x0F, 0xF1, 0xFF, 0x30, 0x66, 0x06, 0x60, 0x0C, 0x00, 0xC0, 0x0C, 0x00,
- 0xE0, 0xC7, 0xF8, 0x3F, 0x00, 0x3F, 0x87, 0xF8, 0x63, 0x8C, 0x31, 0x06,
- 0x60, 0xCC, 0x19, 0x86, 0x31, 0xCF, 0xF3, 0xF8, 0x00, 0x3F, 0xE3, 0xFE,
- 0x18, 0x61, 0xB6, 0x1F, 0x01, 0xF0, 0x32, 0x03, 0x00, 0x30, 0x4F, 0xFC,
- 0xFF, 0xC0, 0x3F, 0xF3, 0xFE, 0x18, 0x61, 0xB6, 0x1F, 0x03, 0xF0, 0x32,
- 0x03, 0x00, 0x30, 0x0F, 0xC0, 0xFC, 0x00, 0x0F, 0xE3, 0xFC, 0xC1, 0x30,
- 0x06, 0x01, 0x80, 0x31, 0xF6, 0x3E, 0xE1, 0x9F, 0xF0, 0xF8, 0x00, 0x1E,
- 0xF3, 0xCF, 0x18, 0x61, 0x84, 0x10, 0xC3, 0xFC, 0x3F, 0xC3, 0x08, 0x31,
- 0x8F, 0xBC, 0xFB, 0xC0, 0x3F, 0xCF, 0xF0, 0x60, 0x10, 0x0C, 0x03, 0x00,
- 0xC0, 0x20, 0x18, 0x3F, 0xCF, 0xF0, 0x07, 0xF0, 0x7F, 0x00, 0x80, 0x18,
- 0x01, 0x80, 0x18, 0x61, 0x84, 0x10, 0xC3, 0x0F, 0xE0, 0x7C, 0x00, 0x3E,
- 0xE7, 0xFC, 0x66, 0x0D, 0x81, 0x60, 0x7C, 0x0E, 0xC1, 0x98, 0x31, 0x1F,
- 0x3B, 0xE7, 0x00, 0x3F, 0x07, 0xE0, 0x30, 0x06, 0x00, 0xC0, 0x10, 0x06,
- 0x00, 0xC3, 0x18, 0x6F, 0xFB, 0xFF, 0x00, 0x38, 0x39, 0xC3, 0xC7, 0x3C,
- 0x79, 0xE3, 0xDA, 0x1F, 0xF0, 0x9D, 0x8C, 0xCC, 0x60, 0x67, 0xCF, 0x3C,
- 0x78, 0x3C, 0xF9, 0xE7, 0x87, 0x18, 0x3C, 0xC1, 0x66, 0x1B, 0xB0, 0xCD,
- 0x06, 0x78, 0x31, 0xC3, 0xCE, 0x3E, 0x30, 0x0F, 0x0F, 0xE7, 0x1D, 0x83,
- 0xC0, 0xF0, 0x3C, 0x0F, 0x06, 0xE3, 0x9F, 0xC3, 0xC0, 0x3F, 0xC7, 0xFC,
- 0x61, 0x8C, 0x31, 0x8E, 0x3F, 0x87, 0xE1, 0x80, 0x30, 0x0F, 0xC3, 0xF0,
- 0x00, 0x0F, 0x0F, 0xE7, 0x1D, 0x83, 0xC0, 0xF0, 0x3C, 0x0F, 0x06, 0xE3,
- 0x1F, 0xC3, 0xC0, 0x80, 0x7F, 0x3F, 0xC0, 0x3F, 0xC3, 0xFE, 0x18, 0x61,
- 0x86, 0x10, 0xE3, 0xFC, 0x3F, 0x83, 0x18, 0x31, 0xCF, 0x8F, 0xF8, 0x70,
- 0x1E, 0xCF, 0xF7, 0x19, 0x80, 0x70, 0x1F, 0x81, 0xF3, 0x0C, 0xC3, 0x3F,
- 0x8B, 0xC0, 0x7F, 0xCF, 0xF9, 0x93, 0x66, 0x60, 0xC0, 0x18, 0x02, 0x00,
- 0xC0, 0x18, 0x0F, 0xC1, 0xF8, 0x00, 0xF9, 0xFF, 0x7D, 0x83, 0x30, 0x64,
- 0x09, 0x83, 0x30, 0x66, 0x0C, 0xE3, 0x0F, 0xC0, 0xF0, 0x00, 0xF9, 0xFE,
- 0x3D, 0x83, 0x30, 0xC6, 0x30, 0xE6, 0x0D, 0x81, 0xB0, 0x3C, 0x07, 0x00,
- 0x60, 0x00, 0xF9, 0xFF, 0x3D, 0x83, 0x36, 0x64, 0xC8, 0xBF, 0x35, 0xE7,
- 0xB8, 0xE7, 0x1C, 0xE3, 0x18, 0x00, 0x3C, 0xF3, 0xCF, 0x1C, 0xC0, 0xD8,
- 0x0F, 0x00, 0x60, 0x0F, 0x01, 0xB8, 0x31, 0x8F, 0x3C, 0xF3, 0xC0, 0x79,
- 0xEE, 0x38, 0xC6, 0x19, 0x81, 0xE0, 0x38, 0x06, 0x00, 0xC0, 0x18, 0x0F,
- 0xC3, 0xF8, 0x00, 0x3F, 0xCF, 0xF3, 0x18, 0xCC, 0x06, 0x03, 0x01, 0x80,
- 0xC6, 0x61, 0xBF, 0xCF, 0xF0, 0x1E, 0x3C, 0xC1, 0x83, 0x06, 0x08, 0x30,
- 0x60, 0xC1, 0x06, 0x0F, 0x1E, 0x00, 0x06, 0x31, 0x86, 0x31, 0x8C, 0x31,
- 0x8C, 0x61, 0x8C, 0x60, 0x1E, 0x78, 0x30, 0x60, 0xC1, 0x86, 0x0C, 0x18,
- 0x30, 0x41, 0x8F, 0x1E, 0x00, 0x08, 0x1C, 0x3C, 0x76, 0xE7, 0xC3, 0x7F,
- 0xFF, 0xFC, 0x88, 0x80, 0x0F, 0x07, 0xE1, 0xF9, 0xFE, 0xE3, 0x30, 0xCF,
- 0xFD, 0xFF, 0x38, 0x07, 0x00, 0x60, 0x0F, 0xC1, 0xFC, 0x71, 0xCC, 0x19,
- 0x83, 0x30, 0xDF, 0xFB, 0xBC, 0x00, 0x1F, 0xCF, 0xF6, 0x1B, 0x00, 0xC0,
- 0x30, 0x0F, 0xF1, 0xF8, 0x01, 0xE0, 0x38, 0x03, 0x0F, 0x63, 0xFC, 0xC3,
- 0x30, 0x66, 0x0C, 0xC3, 0x9F, 0xF9, 0xF7, 0x00, 0x1F, 0x1F, 0xD8, 0x3F,
- 0xFF, 0xFE, 0x1B, 0xFC, 0xF8, 0x07, 0xC3, 0xF1, 0x81, 0xFE, 0x7F, 0x84,
- 0x03, 0x00, 0xC0, 0x30, 0x3F, 0x8F, 0xE0, 0x1E, 0xE7, 0xFD, 0x86, 0x60,
- 0xCC, 0x19, 0xC6, 0x3F, 0xC1, 0xD8, 0x03, 0x00, 0xE1, 0xF8, 0x3E, 0x00,
- 0x38, 0x1E, 0x01, 0x00, 0xDC, 0x3F, 0x8C, 0x62, 0x19, 0x84, 0x63, 0x3D,
- 0xFF, 0x7C, 0x06, 0x03, 0x00, 0x03, 0xC3, 0xE0, 0x20, 0x30, 0x18, 0x0C,
- 0x3F, 0xFF, 0xE0, 0x01, 0x81, 0x80, 0x07, 0xF3, 0xF8, 0x0C, 0x04, 0x06,
- 0x03, 0x01, 0x80, 0xC0, 0x40, 0x67, 0xE3, 0xE0, 0x38, 0x0E, 0x01, 0x80,
- 0x4F, 0x37, 0xCF, 0x83, 0xC0, 0xF0, 0x26, 0x39, 0xEE, 0x78, 0x1F, 0x0F,
- 0x01, 0x80, 0xC0, 0x60, 0x20, 0x30, 0x18, 0x0C, 0x3F, 0xFF, 0xE0, 0x7E,
- 0xE7, 0xFF, 0x33, 0x32, 0x63, 0x66, 0x36, 0x62, 0xF7, 0x7F, 0x67, 0x77,
- 0x8F, 0xF8, 0xC3, 0x10, 0x66, 0x08, 0xC3, 0x3C, 0x7F, 0x8F, 0x1F, 0x0F,
- 0xE6, 0x1F, 0x03, 0xC0, 0xF8, 0x67, 0xF0, 0xF8, 0x3F, 0xE3, 0xFF, 0x1C,
- 0x31, 0x83, 0x18, 0x31, 0x86, 0x3F, 0xE3, 0x78, 0x30, 0x03, 0x00, 0xFC,
- 0x0F, 0x80, 0x1E, 0xEF, 0xFD, 0x86, 0x60, 0xCC, 0x19, 0xC7, 0x3F, 0xE1,
- 0xE8, 0x03, 0x00, 0x60, 0x3E, 0x07, 0xC0, 0x39, 0xDF, 0xF1, 0xC0, 0x60,
- 0x10, 0x0C, 0x0F, 0xF3, 0xF8, 0x1F, 0x7F, 0x63, 0x7E, 0x1F, 0xC3, 0xFE,
- 0xFC, 0x10, 0x08, 0x0C, 0x1F, 0xEF, 0xF1, 0x80, 0x80, 0xC0, 0x60, 0x3F,
- 0x8F, 0x80, 0xF3, 0xFC, 0xF6, 0x09, 0x86, 0x61, 0x98, 0xE7, 0xF8, 0xFE,
- 0xFB, 0xFF, 0x7C, 0xC6, 0x19, 0x83, 0x60, 0x6C, 0x07, 0x00, 0xC0, 0xF1,
- 0xFE, 0x3D, 0xB3, 0x37, 0xC7, 0xF8, 0xEE, 0x1D, 0xC3, 0x30, 0x79, 0xEF,
- 0x38, 0xEE, 0x0F, 0x01, 0xE0, 0x6E, 0x3C, 0xE7, 0xBC, 0x3C, 0xF3, 0x8F,
- 0x18, 0xC1, 0x9C, 0x19, 0x81, 0xF0, 0x0E, 0x00, 0xE0, 0x0C, 0x01, 0x80,
- 0xFC, 0x0F, 0xC0, 0x7F, 0xBF, 0xD9, 0xC1, 0x83, 0x83, 0x1B, 0xFD, 0xFE,
- 0x06, 0x1C, 0x60, 0xC1, 0x86, 0x3C, 0x70, 0x30, 0x41, 0x83, 0x07, 0x06,
- 0x00, 0x33, 0x32, 0x26, 0x66, 0x44, 0xCC, 0xC8, 0x0C, 0x0E, 0x04, 0x0C,
- 0x0C, 0x0C, 0x0F, 0x0F, 0x18, 0x18, 0x10, 0x30, 0xF0, 0xE0, 0x38, 0x7C,
- 0xF7, 0xC1, 0xC0 };
-
-const GFXglyph FreeMonoBoldOblique9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 11, 0, 1 }, // 0x20 ' '
- { 0, 5, 11, 11, 4, -10 }, // 0x21 '!'
- { 7, 7, 5, 11, 4, -10 }, // 0x22 '"'
- { 12, 9, 12, 11, 2, -10 }, // 0x23 '#'
- { 26, 9, 14, 11, 2, -11 }, // 0x24 '$'
- { 42, 9, 11, 11, 2, -10 }, // 0x25 '%'
- { 55, 8, 10, 11, 2, -9 }, // 0x26 '&'
- { 65, 2, 5, 11, 6, -10 }, // 0x27 '''
- { 67, 5, 14, 11, 5, -10 }, // 0x28 '('
- { 76, 5, 14, 11, 2, -10 }, // 0x29 ')'
- { 85, 8, 7, 11, 3, -10 }, // 0x2A '*'
- { 92, 9, 9, 11, 2, -8 }, // 0x2B '+'
- { 103, 4, 5, 11, 2, -1 }, // 0x2C ','
- { 106, 9, 2, 11, 2, -5 }, // 0x2D '-'
- { 109, 3, 2, 11, 4, -1 }, // 0x2E '.'
- { 110, 11, 15, 11, 1, -12 }, // 0x2F '/'
- { 131, 9, 12, 11, 2, -11 }, // 0x30 '0'
- { 145, 8, 12, 11, 2, -11 }, // 0x31 '1'
- { 157, 10, 12, 11, 1, -11 }, // 0x32 '2'
- { 172, 9, 12, 11, 2, -11 }, // 0x33 '3'
- { 186, 8, 10, 11, 2, -9 }, // 0x34 '4'
- { 196, 9, 11, 11, 3, -10 }, // 0x35 '5'
- { 209, 9, 12, 11, 3, -11 }, // 0x36 '6'
- { 223, 8, 11, 11, 3, -10 }, // 0x37 '7'
- { 234, 9, 12, 11, 2, -11 }, // 0x38 '8'
- { 248, 8, 12, 11, 3, -11 }, // 0x39 '9'
- { 260, 4, 8, 11, 4, -7 }, // 0x3A ':'
- { 264, 6, 11, 11, 2, -7 }, // 0x3B ';'
- { 273, 10, 8, 11, 2, -8 }, // 0x3C '<'
- { 283, 10, 6, 11, 1, -7 }, // 0x3D '='
- { 291, 10, 8, 11, 1, -8 }, // 0x3E '>'
- { 301, 7, 11, 11, 4, -10 }, // 0x3F '?'
- { 311, 9, 15, 11, 2, -11 }, // 0x40 '@'
- { 328, 11, 11, 11, 0, -10 }, // 0x41 'A'
- { 344, 11, 11, 11, 0, -10 }, // 0x42 'B'
- { 360, 12, 11, 11, 1, -10 }, // 0x43 'C'
- { 377, 11, 11, 11, 0, -10 }, // 0x44 'D'
- { 393, 12, 11, 11, 0, -10 }, // 0x45 'E'
- { 410, 12, 11, 11, 0, -10 }, // 0x46 'F'
- { 427, 11, 11, 11, 1, -10 }, // 0x47 'G'
- { 443, 12, 11, 11, 0, -10 }, // 0x48 'H'
- { 460, 10, 11, 11, 1, -10 }, // 0x49 'I'
- { 474, 12, 11, 11, 0, -10 }, // 0x4A 'J'
- { 491, 11, 11, 11, 0, -10 }, // 0x4B 'K'
- { 507, 11, 11, 11, 0, -10 }, // 0x4C 'L'
- { 523, 13, 11, 11, 0, -10 }, // 0x4D 'M'
- { 541, 13, 11, 11, 0, -10 }, // 0x4E 'N'
- { 559, 10, 11, 11, 1, -10 }, // 0x4F 'O'
- { 573, 11, 11, 11, 0, -10 }, // 0x50 'P'
- { 589, 10, 14, 11, 1, -10 }, // 0x51 'Q'
- { 607, 12, 11, 11, 0, -10 }, // 0x52 'R'
- { 624, 10, 11, 11, 2, -10 }, // 0x53 'S'
- { 638, 11, 11, 11, 1, -10 }, // 0x54 'T'
- { 654, 11, 11, 11, 1, -10 }, // 0x55 'U'
- { 670, 11, 11, 11, 1, -10 }, // 0x56 'V'
- { 686, 11, 11, 11, 1, -10 }, // 0x57 'W'
- { 702, 12, 11, 11, 0, -10 }, // 0x58 'X'
- { 719, 11, 11, 11, 1, -10 }, // 0x59 'Y'
- { 735, 10, 11, 11, 1, -10 }, // 0x5A 'Z'
- { 749, 7, 14, 11, 4, -10 }, // 0x5B '['
- { 762, 5, 15, 11, 4, -12 }, // 0x5C '\'
- { 772, 7, 14, 11, 2, -10 }, // 0x5D ']'
- { 785, 8, 6, 11, 3, -11 }, // 0x5E '^'
- { 791, 11, 2, 11, -1, 3 }, // 0x5F '_'
- { 794, 3, 3, 11, 5, -11 }, // 0x60 '`'
- { 796, 10, 8, 11, 1, -7 }, // 0x61 'a'
- { 806, 11, 11, 11, 0, -10 }, // 0x62 'b'
- { 822, 10, 8, 11, 1, -7 }, // 0x63 'c'
- { 832, 11, 11, 11, 1, -10 }, // 0x64 'd'
- { 848, 9, 8, 11, 1, -7 }, // 0x65 'e'
- { 857, 10, 11, 11, 2, -10 }, // 0x66 'f'
- { 871, 11, 12, 11, 1, -7 }, // 0x67 'g'
- { 888, 10, 11, 11, 1, -10 }, // 0x68 'h'
- { 902, 9, 11, 11, 1, -10 }, // 0x69 'i'
- { 915, 9, 15, 11, 1, -10 }, // 0x6A 'j'
- { 932, 10, 11, 11, 1, -10 }, // 0x6B 'k'
- { 946, 9, 11, 11, 1, -10 }, // 0x6C 'l'
- { 959, 12, 8, 11, 0, -7 }, // 0x6D 'm'
- { 971, 11, 8, 11, 1, -7 }, // 0x6E 'n'
- { 982, 10, 8, 11, 1, -7 }, // 0x6F 'o'
- { 992, 12, 12, 11, -1, -7 }, // 0x70 'p'
- { 1010, 11, 12, 11, 1, -7 }, // 0x71 'q'
- { 1027, 10, 8, 11, 1, -7 }, // 0x72 'r'
- { 1037, 8, 8, 11, 2, -7 }, // 0x73 's'
- { 1045, 9, 11, 11, 1, -10 }, // 0x74 't'
- { 1058, 10, 8, 11, 1, -7 }, // 0x75 'u'
- { 1068, 11, 8, 11, 1, -7 }, // 0x76 'v'
- { 1079, 11, 8, 11, 1, -7 }, // 0x77 'w'
- { 1090, 11, 8, 11, 1, -7 }, // 0x78 'x'
- { 1101, 12, 12, 11, 0, -7 }, // 0x79 'y'
- { 1119, 9, 8, 11, 2, -7 }, // 0x7A 'z'
- { 1128, 7, 14, 11, 3, -10 }, // 0x7B '{'
- { 1141, 4, 14, 11, 4, -10 }, // 0x7C '|'
- { 1148, 8, 14, 11, 2, -10 }, // 0x7D '}'
- { 1162, 9, 4, 11, 2, -6 } }; // 0x7E '~'
-
-const GFXfont FreeMonoBoldOblique9pt7b PROGMEM = {
- (uint8_t *)FreeMonoBoldOblique9pt7bBitmaps,
- (GFXglyph *)FreeMonoBoldOblique9pt7bGlyphs,
- 0x20, 0x7E, 18 };
-
-// Approx. 1839 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique12pt7b.h
deleted file mode 100644
index 83a9a77..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique12pt7b.h
+++ /dev/null
@@ -1,248 +0,0 @@
-const uint8_t FreeMonoOblique12pt7bBitmaps[] PROGMEM = {
- 0x11, 0x11, 0x12, 0x22, 0x22, 0x00, 0x0E, 0xE0, 0xE7, 0xE7, 0xC6, 0xC6,
- 0xC6, 0x84, 0x84, 0x02, 0x40, 0x88, 0x12, 0x02, 0x40, 0x48, 0x7F, 0xC2,
- 0x40, 0x48, 0x11, 0x1F, 0xF8, 0x48, 0x09, 0x02, 0x40, 0x48, 0x09, 0x02,
- 0x20, 0x02, 0x01, 0x00, 0xF4, 0xC3, 0x60, 0x50, 0x04, 0x00, 0xC0, 0x0F,
- 0x00, 0x60, 0x0A, 0x02, 0x81, 0x30, 0xC7, 0xC0, 0x80, 0x20, 0x08, 0x00,
- 0x0E, 0x02, 0x20, 0x84, 0x10, 0x82, 0x20, 0x38, 0x00, 0x38, 0x38, 0x38,
- 0x08, 0xE0, 0x22, 0x08, 0x41, 0x08, 0x22, 0x03, 0x80, 0x07, 0x84, 0x04,
- 0x02, 0x01, 0x00, 0xC1, 0xA2, 0x8A, 0x85, 0x43, 0x31, 0x8F, 0x60, 0xFF,
- 0x6D, 0x20, 0x00, 0x44, 0x42, 0x21, 0x08, 0x84, 0x21, 0x08, 0x42, 0x10,
- 0x42, 0x00, 0x00, 0x84, 0x10, 0x84, 0x21, 0x08, 0x46, 0x21, 0x10, 0x88,
- 0x44, 0x00, 0x04, 0x02, 0x02, 0x1D, 0x13, 0xF0, 0x40, 0x50, 0x48, 0x44,
- 0x00, 0x02, 0x00, 0x40, 0x08, 0x02, 0x00, 0x41, 0xFF, 0xC1, 0x00, 0x20,
- 0x08, 0x01, 0x00, 0x20, 0x00, 0x1C, 0xE3, 0x18, 0x63, 0x08, 0x00, 0xFF,
- 0xE0, 0x7F, 0x00, 0x00, 0x08, 0x00, 0x80, 0x04, 0x00, 0x40, 0x04, 0x00,
- 0x60, 0x02, 0x00, 0x20, 0x03, 0x00, 0x10, 0x01, 0x00, 0x18, 0x00, 0x80,
- 0x08, 0x00, 0x80, 0x04, 0x00, 0x40, 0x04, 0x00, 0x00, 0x07, 0x06, 0x23,
- 0x04, 0x81, 0x40, 0x50, 0x14, 0x06, 0x02, 0x80, 0xA0, 0x28, 0x0A, 0x04,
- 0x83, 0x11, 0x83, 0x80, 0x03, 0x03, 0x83, 0x83, 0x43, 0x20, 0x10, 0x08,
- 0x08, 0x04, 0x02, 0x01, 0x01, 0x00, 0x80, 0x43, 0xFE, 0x01, 0xC0, 0x62,
- 0x0C, 0x10, 0x81, 0x00, 0x10, 0x02, 0x00, 0x60, 0x0C, 0x01, 0x00, 0x20,
- 0x0C, 0x01, 0x80, 0x20, 0x04, 0x04, 0xFF, 0xC0, 0x07, 0xC3, 0x0C, 0x00,
- 0x80, 0x10, 0x06, 0x01, 0x81, 0xC0, 0x0C, 0x00, 0x40, 0x08, 0x01, 0x00,
- 0x20, 0x09, 0x86, 0x0F, 0x00, 0x00, 0xC0, 0x50, 0x24, 0x12, 0x04, 0x82,
- 0x21, 0x08, 0x82, 0x21, 0x10, 0x4F, 0xF8, 0x04, 0x01, 0x00, 0x80, 0xF8,
- 0x0F, 0xE2, 0x00, 0x40, 0x08, 0x01, 0x00, 0x4E, 0x0E, 0x20, 0x02, 0x00,
- 0x40, 0x08, 0x01, 0x00, 0x40, 0x19, 0x06, 0x1F, 0x00, 0x01, 0xE0, 0xC0,
- 0x60, 0x18, 0x02, 0x00, 0x80, 0x13, 0xC5, 0x88, 0xE0, 0x98, 0x12, 0x02,
- 0x40, 0x48, 0x10, 0x84, 0x0F, 0x00, 0xFF, 0xA0, 0x20, 0x08, 0x04, 0x01,
- 0x00, 0x80, 0x20, 0x10, 0x04, 0x02, 0x00, 0x80, 0x40, 0x10, 0x08, 0x02,
- 0x00, 0x07, 0x81, 0x08, 0x40, 0x90, 0x12, 0x02, 0x40, 0x84, 0x20, 0x78,
- 0x30, 0x88, 0x0A, 0x01, 0x40, 0x28, 0x08, 0x82, 0x0F, 0x80, 0x07, 0x81,
- 0x08, 0x40, 0x90, 0x12, 0x02, 0x40, 0xC8, 0x39, 0x8D, 0x1E, 0x40, 0x08,
- 0x02, 0x00, 0xC0, 0x30, 0x18, 0x3E, 0x00, 0x19, 0xCC, 0x00, 0x00, 0x0C,
- 0xE6, 0x00, 0x06, 0x1C, 0x30, 0x00, 0x00, 0x00, 0x1C, 0x30, 0xE1, 0x86,
- 0x08, 0x00, 0x00, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x06, 0x00, 0x30,
- 0x00, 0xC0, 0x06, 0x00, 0x18, 0x00, 0xC0, 0x7F, 0xF8, 0x00, 0x00, 0x01,
- 0xFF, 0xE0, 0x18, 0x00, 0xC0, 0x03, 0x00, 0x18, 0x00, 0x60, 0x03, 0x00,
- 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x00, 0x3E, 0xC3, 0x81, 0x01, 0x03,
- 0x06, 0x18, 0x20, 0x20, 0x00, 0x00, 0x00, 0xE0, 0xE0, 0x07, 0x82, 0x31,
- 0x04, 0x81, 0x20, 0x48, 0x74, 0x65, 0x21, 0x48, 0x92, 0x28, 0x7A, 0x00,
- 0x80, 0x20, 0x04, 0x00, 0xF8, 0x07, 0xE0, 0x02, 0x80, 0x0A, 0x00, 0x48,
- 0x01, 0x20, 0x08, 0x40, 0x41, 0x01, 0x04, 0x0F, 0xF0, 0x20, 0x41, 0x01,
- 0x04, 0x02, 0x20, 0x0B, 0xE1, 0xF0, 0x1F, 0xF0, 0x40, 0xC2, 0x02, 0x10,
- 0x10, 0x81, 0x84, 0x18, 0x7F, 0x82, 0x02, 0x10, 0x08, 0x80, 0x44, 0x02,
- 0x60, 0x22, 0x03, 0x7F, 0xE0, 0x07, 0x91, 0x87, 0x20, 0x34, 0x02, 0x40,
- 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x04, 0x61,
- 0x81, 0xE0, 0x1F, 0xE0, 0x41, 0x82, 0x06, 0x10, 0x11, 0x00, 0x88, 0x04,
- 0x40, 0x22, 0x01, 0x10, 0x11, 0x00, 0x88, 0x08, 0x40, 0xC2, 0x0C, 0x7F,
- 0x80, 0x1F, 0xFC, 0x20, 0x10, 0x80, 0x82, 0x00, 0x08, 0x00, 0x22, 0x01,
- 0xF8, 0x04, 0x20, 0x10, 0x00, 0x40, 0x01, 0x01, 0x0C, 0x04, 0x20, 0x13,
- 0xFF, 0xC0, 0x1F, 0xFC, 0x20, 0x10, 0x80, 0x42, 0x01, 0x08, 0x00, 0x22,
- 0x01, 0xF8, 0x04, 0x20, 0x10, 0x00, 0x40, 0x01, 0x00, 0x0C, 0x00, 0x20,
- 0x03, 0xF8, 0x00, 0x07, 0xD0, 0x83, 0x30, 0x12, 0x00, 0x40, 0x04, 0x00,
- 0x80, 0x08, 0x00, 0x83, 0xE8, 0x04, 0x80, 0x4C, 0x04, 0x60, 0x41, 0xF8,
- 0x0F, 0x3C, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x81, 0x01, 0x02, 0x03,
- 0xFC, 0x08, 0x08, 0x10, 0x10, 0x20, 0x40, 0x40, 0x80, 0x81, 0x02, 0x02,
- 0x1F, 0x1E, 0x00, 0x3F, 0xE0, 0x40, 0x08, 0x01, 0x00, 0x20, 0x08, 0x01,
- 0x00, 0x20, 0x04, 0x00, 0x80, 0x20, 0x04, 0x00, 0x81, 0xFF, 0x00, 0x03,
- 0xFE, 0x00, 0x20, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08,
- 0x00, 0x20, 0x40, 0x40, 0x80, 0x81, 0x01, 0x02, 0x04, 0x06, 0x10, 0x07,
- 0xC0, 0x00, 0x1F, 0x1E, 0x10, 0x10, 0x20, 0xC0, 0x43, 0x00, 0x88, 0x01,
- 0x20, 0x07, 0xC0, 0x0C, 0x40, 0x10, 0x40, 0x20, 0x80, 0x41, 0x01, 0x81,
- 0x02, 0x02, 0x1F, 0x87, 0x00, 0x3F, 0x80, 0x40, 0x04, 0x00, 0x40, 0x08,
- 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x01, 0x01, 0x10, 0x11, 0x02, 0x10,
- 0x2F, 0xFE, 0x1C, 0x03, 0x85, 0x03, 0x02, 0x82, 0x81, 0x41, 0x40, 0xA1,
- 0x20, 0x89, 0x30, 0x44, 0x90, 0x22, 0x88, 0x11, 0x44, 0x08, 0x42, 0x08,
- 0x03, 0x04, 0x01, 0x02, 0x00, 0x87, 0xC3, 0xE0, 0x3C, 0x3E, 0x18, 0x08,
- 0x38, 0x20, 0x50, 0x41, 0x20, 0x82, 0x61, 0x04, 0x42, 0x08, 0x88, 0x10,
- 0x90, 0x41, 0x20, 0x83, 0x41, 0x02, 0x82, 0x06, 0x1F, 0x04, 0x00, 0x03,
- 0xC0, 0x61, 0x84, 0x04, 0x40, 0x14, 0x00, 0xA0, 0x06, 0x00, 0x30, 0x01,
- 0x80, 0x14, 0x00, 0xA0, 0x08, 0x80, 0x86, 0x18, 0x0F, 0x00, 0x1F, 0xE0,
- 0x40, 0x82, 0x02, 0x10, 0x10, 0x80, 0x84, 0x08, 0x40, 0x83, 0xF8, 0x10,
- 0x00, 0x80, 0x04, 0x00, 0x60, 0x02, 0x00, 0x7F, 0x00, 0x03, 0xC0, 0x61,
- 0x84, 0x04, 0x40, 0x14, 0x00, 0xA0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x14,
- 0x00, 0xA0, 0x08, 0x80, 0x86, 0x18, 0x1F, 0x00, 0x40, 0x0F, 0xC4, 0x41,
- 0xC0, 0x1F, 0xE0, 0x40, 0x82, 0x02, 0x10, 0x10, 0x80, 0x84, 0x08, 0x60,
- 0x83, 0xF8, 0x10, 0xC0, 0x82, 0x04, 0x08, 0x40, 0x42, 0x03, 0x7E, 0x0C,
- 0x07, 0xA3, 0x0C, 0x40, 0x90, 0x12, 0x00, 0x40, 0x06, 0x00, 0x3C, 0x00,
- 0x40, 0x0A, 0x01, 0x40, 0x4C, 0x11, 0x7C, 0x00, 0xFF, 0xE8, 0x42, 0x84,
- 0x20, 0x40, 0x04, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x10,
- 0x01, 0x00, 0x10, 0x0F, 0xE0, 0xF8, 0xF9, 0x00, 0x88, 0x08, 0x80, 0x44,
- 0x02, 0x20, 0x11, 0x01, 0x08, 0x08, 0x80, 0x44, 0x02, 0x20, 0x31, 0x01,
- 0x04, 0x30, 0x1E, 0x00, 0xF8, 0x7D, 0x00, 0x42, 0x01, 0x08, 0x08, 0x20,
- 0x40, 0x81, 0x02, 0x08, 0x08, 0x20, 0x11, 0x00, 0x48, 0x01, 0x20, 0x05,
- 0x00, 0x14, 0x00, 0x60, 0x00, 0xF8, 0x7D, 0x00, 0x44, 0x01, 0x11, 0x84,
- 0x46, 0x21, 0x18, 0x84, 0xA2, 0x12, 0x90, 0x91, 0x42, 0x45, 0x0A, 0x14,
- 0x28, 0x60, 0xC1, 0x83, 0x06, 0x00, 0x1E, 0x1E, 0x10, 0x10, 0x10, 0x40,
- 0x21, 0x00, 0x24, 0x00, 0x78, 0x00, 0x60, 0x01, 0xC0, 0x06, 0x80, 0x09,
- 0x80, 0x21, 0x00, 0x81, 0x02, 0x02, 0x1E, 0x1F, 0x00, 0xF0, 0xF4, 0x04,
- 0x20, 0x82, 0x18, 0x11, 0x01, 0x20, 0x1C, 0x00, 0x80, 0x08, 0x00, 0x80,
- 0x10, 0x01, 0x00, 0x10, 0x0F, 0xE0, 0x0F, 0xF1, 0x01, 0x10, 0x21, 0x04,
- 0x00, 0x80, 0x10, 0x02, 0x00, 0x40, 0x0C, 0x01, 0x82, 0x10, 0x22, 0x04,
- 0x40, 0x47, 0xFC, 0x0E, 0x20, 0x40, 0x81, 0x02, 0x08, 0x10, 0x20, 0x40,
- 0x82, 0x04, 0x08, 0x10, 0x20, 0x81, 0xE0, 0x84, 0x20, 0x84, 0x20, 0x84,
- 0x21, 0x04, 0x21, 0x08, 0x21, 0x08, 0x40, 0x1E, 0x04, 0x08, 0x20, 0x40,
- 0x81, 0x02, 0x04, 0x10, 0x20, 0x40, 0x81, 0x02, 0x08, 0x11, 0xE0, 0x04,
- 0x06, 0x04, 0x84, 0x44, 0x14, 0x0C, 0xFF, 0xFE, 0x99, 0x90, 0x1F, 0xC0,
- 0x06, 0x00, 0x20, 0x02, 0x1F, 0xE6, 0x04, 0xC0, 0x48, 0x04, 0x81, 0xC7,
- 0xEF, 0x18, 0x00, 0x40, 0x02, 0x00, 0x10, 0x00, 0x80, 0x09, 0xF0, 0x50,
- 0xC3, 0x03, 0x10, 0x08, 0x80, 0x48, 0x02, 0x40, 0x23, 0x03, 0x1C, 0x33,
- 0xBE, 0x00, 0x0F, 0xD3, 0x07, 0x60, 0x24, 0x02, 0x80, 0x08, 0x00, 0x80,
- 0x08, 0x06, 0x41, 0xC3, 0xF0, 0x00, 0x38, 0x00, 0x40, 0x02, 0x00, 0x20,
- 0x01, 0x07, 0xC8, 0x43, 0x44, 0x0E, 0x40, 0x24, 0x01, 0x20, 0x09, 0x00,
- 0xC8, 0x0E, 0x20, 0xE0, 0xF9, 0xC0, 0x0F, 0x86, 0x09, 0x00, 0xA0, 0x1F,
- 0xFF, 0x00, 0x20, 0x06, 0x00, 0x60, 0xC7, 0xE0, 0x01, 0xF8, 0x10, 0x01,
- 0x00, 0x08, 0x00, 0x40, 0x1F, 0xF0, 0x20, 0x01, 0x00, 0x08, 0x00, 0x40,
- 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x03, 0xFE, 0x00, 0x0F, 0x31, 0x86,
- 0x10, 0x10, 0x80, 0x88, 0x04, 0x40, 0x22, 0x02, 0x10, 0x10, 0x43, 0x81,
- 0xE4, 0x00, 0x40, 0x02, 0x00, 0x20, 0x3E, 0x00, 0x1C, 0x00, 0x20, 0x03,
- 0x00, 0x10, 0x00, 0x80, 0x05, 0xF0, 0x30, 0xC3, 0x02, 0x10, 0x10, 0x80,
- 0x84, 0x0C, 0x20, 0x63, 0x02, 0x10, 0x13, 0xE3, 0xE0, 0x01, 0x80, 0x40,
- 0x10, 0x00, 0x00, 0x07, 0xC0, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x10,
- 0x04, 0x01, 0x0F, 0xFC, 0x00, 0x40, 0x10, 0x0C, 0x00, 0x00, 0x07, 0xF0,
- 0x04, 0x01, 0x00, 0x40, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04,
- 0x01, 0x00, 0x8F, 0xC0, 0x18, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x01,
- 0x1F, 0x10, 0x81, 0x30, 0x14, 0x01, 0xC0, 0x26, 0x02, 0x20, 0x21, 0x02,
- 0x08, 0xE1, 0xE0, 0x0F, 0x80, 0x40, 0x10, 0x04, 0x01, 0x00, 0x40, 0x20,
- 0x08, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04, 0x01, 0x0F, 0xFC, 0x3B, 0xB8,
- 0x33, 0x91, 0x08, 0x44, 0x21, 0x10, 0x84, 0x42, 0x12, 0x10, 0x48, 0x42,
- 0x21, 0x0B, 0xC6, 0x30, 0x19, 0xE0, 0xE3, 0x08, 0x11, 0x01, 0x10, 0x11,
- 0x02, 0x10, 0x21, 0x02, 0x20, 0x2F, 0x87, 0x0F, 0x86, 0x19, 0x80, 0xA0,
- 0x18, 0x03, 0x00, 0x60, 0x14, 0x06, 0x61, 0x87, 0xC0, 0x19, 0xF0, 0x28,
- 0x20, 0xC0, 0x42, 0x01, 0x10, 0x04, 0x40, 0x11, 0x00, 0x86, 0x06, 0x14,
- 0x30, 0xCF, 0x02, 0x00, 0x08, 0x00, 0x20, 0x03, 0xF0, 0x00, 0x0F, 0x39,
- 0x85, 0x18, 0x18, 0x80, 0x88, 0x04, 0x40, 0x22, 0x01, 0x18, 0x18, 0x63,
- 0x81, 0xE4, 0x00, 0x20, 0x01, 0x00, 0x10, 0x07, 0xE0, 0x1C, 0x78, 0x2C,
- 0x01, 0x80, 0x18, 0x00, 0x80, 0x04, 0x00, 0x20, 0x02, 0x00, 0x10, 0x07,
- 0xFC, 0x00, 0x0F, 0x44, 0x32, 0x04, 0x80, 0x1E, 0x00, 0x60, 0x0A, 0x02,
- 0xC1, 0x2F, 0x80, 0x10, 0x08, 0x04, 0x02, 0x0F, 0xF9, 0x00, 0x80, 0x40,
- 0x20, 0x20, 0x10, 0x08, 0x04, 0x19, 0xF0, 0xE0, 0xF2, 0x02, 0x40, 0x24,
- 0x02, 0x40, 0x24, 0x06, 0x40, 0x44, 0x04, 0x41, 0xC3, 0xE6, 0xF8, 0xFA,
- 0x01, 0x08, 0x10, 0x41, 0x02, 0x08, 0x10, 0x80, 0x48, 0x02, 0x40, 0x14,
- 0x00, 0xC0, 0x00, 0xE0, 0x7A, 0x01, 0x10, 0x08, 0x8C, 0x84, 0xA4, 0x25,
- 0x21, 0x4A, 0x0A, 0x50, 0x63, 0x02, 0x18, 0x00, 0x1E, 0x3C, 0x20, 0x40,
- 0x46, 0x00, 0xB0, 0x03, 0x00, 0x0E, 0x00, 0xC8, 0x06, 0x10, 0x20, 0x23,
- 0xE3, 0xC0, 0x3C, 0x3C, 0x40, 0x20, 0x81, 0x02, 0x08, 0x08, 0x20, 0x31,
- 0x00, 0x48, 0x01, 0x40, 0x05, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00, 0x08,
- 0x03, 0xF0, 0x00, 0x3F, 0xC4, 0x18, 0x06, 0x01, 0x80, 0x60, 0x10, 0x04,
- 0x01, 0x00, 0x40, 0x9F, 0xF0, 0x06, 0x10, 0x20, 0x41, 0x02, 0x04, 0x08,
- 0x21, 0x80, 0x81, 0x02, 0x08, 0x10, 0x20, 0x40, 0xC0, 0x01, 0x11, 0x12,
- 0x22, 0x24, 0x44, 0x44, 0x88, 0x80, 0x0C, 0x08, 0x10, 0x20, 0x40, 0x82,
- 0x04, 0x08, 0x0C, 0x20, 0x81, 0x02, 0x04, 0x08, 0x21, 0x80, 0x38, 0x28,
- 0x88, 0x0E, 0x00 };
-
-const GFXglyph FreeMonoOblique12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 14, 0, 1 }, // 0x20 ' '
- { 0, 4, 15, 14, 6, -14 }, // 0x21 '!'
- { 8, 8, 7, 14, 5, -14 }, // 0x22 '"'
- { 15, 11, 16, 14, 3, -14 }, // 0x23 '#'
- { 37, 10, 18, 14, 4, -15 }, // 0x24 '$'
- { 60, 11, 15, 14, 3, -14 }, // 0x25 '%'
- { 81, 9, 12, 14, 3, -11 }, // 0x26 '&'
- { 95, 3, 7, 14, 8, -14 }, // 0x27 '''
- { 98, 5, 18, 14, 8, -14 }, // 0x28 '('
- { 110, 5, 18, 14, 4, -14 }, // 0x29 ')'
- { 122, 9, 9, 14, 5, -14 }, // 0x2A '*'
- { 133, 11, 11, 14, 3, -11 }, // 0x2B '+'
- { 149, 6, 7, 14, 3, -3 }, // 0x2C ','
- { 155, 11, 1, 14, 3, -6 }, // 0x2D '-'
- { 157, 3, 3, 14, 6, -2 }, // 0x2E '.'
- { 159, 13, 18, 14, 2, -15 }, // 0x2F '/'
- { 189, 10, 15, 14, 4, -14 }, // 0x30 '0'
- { 208, 9, 15, 14, 3, -14 }, // 0x31 '1'
- { 225, 12, 15, 14, 2, -14 }, // 0x32 '2'
- { 248, 11, 15, 14, 3, -14 }, // 0x33 '3'
- { 269, 10, 15, 14, 3, -14 }, // 0x34 '4'
- { 288, 11, 15, 14, 3, -14 }, // 0x35 '5'
- { 309, 11, 15, 14, 4, -14 }, // 0x36 '6'
- { 330, 10, 15, 14, 5, -14 }, // 0x37 '7'
- { 349, 11, 15, 14, 3, -14 }, // 0x38 '8'
- { 370, 11, 15, 14, 3, -14 }, // 0x39 '9'
- { 391, 5, 10, 14, 5, -9 }, // 0x3A ':'
- { 398, 7, 13, 14, 3, -9 }, // 0x3B ';'
- { 410, 12, 11, 14, 3, -11 }, // 0x3C '<'
- { 427, 13, 4, 14, 2, -8 }, // 0x3D '='
- { 434, 12, 11, 14, 2, -11 }, // 0x3E '>'
- { 451, 8, 14, 14, 6, -13 }, // 0x3F '?'
- { 465, 10, 16, 14, 3, -14 }, // 0x40 '@'
- { 485, 14, 14, 14, 0, -13 }, // 0x41 'A'
- { 510, 13, 14, 14, 1, -13 }, // 0x42 'B'
- { 533, 12, 14, 14, 3, -13 }, // 0x43 'C'
- { 554, 13, 14, 14, 1, -13 }, // 0x44 'D'
- { 577, 14, 14, 14, 1, -13 }, // 0x45 'E'
- { 602, 14, 14, 14, 1, -13 }, // 0x46 'F'
- { 627, 12, 14, 14, 3, -13 }, // 0x47 'G'
- { 648, 15, 14, 14, 1, -13 }, // 0x48 'H'
- { 675, 11, 14, 14, 3, -13 }, // 0x49 'I'
- { 695, 15, 14, 14, 2, -13 }, // 0x4A 'J'
- { 722, 15, 14, 14, 1, -13 }, // 0x4B 'K'
- { 749, 12, 14, 14, 2, -13 }, // 0x4C 'L'
- { 770, 17, 14, 14, 0, -13 }, // 0x4D 'M'
- { 800, 15, 14, 14, 1, -13 }, // 0x4E 'N'
- { 827, 13, 14, 14, 2, -13 }, // 0x4F 'O'
- { 850, 13, 14, 14, 1, -13 }, // 0x50 'P'
- { 873, 13, 17, 14, 2, -13 }, // 0x51 'Q'
- { 901, 13, 14, 14, 1, -13 }, // 0x52 'R'
- { 924, 11, 14, 14, 3, -13 }, // 0x53 'S'
- { 944, 12, 14, 14, 4, -13 }, // 0x54 'T'
- { 965, 13, 14, 14, 3, -13 }, // 0x55 'U'
- { 988, 14, 14, 14, 3, -13 }, // 0x56 'V'
- { 1013, 14, 14, 14, 3, -13 }, // 0x57 'W'
- { 1038, 15, 14, 14, 1, -13 }, // 0x58 'X'
- { 1065, 12, 14, 14, 4, -13 }, // 0x59 'Y'
- { 1086, 12, 14, 14, 2, -13 }, // 0x5A 'Z'
- { 1107, 7, 18, 14, 6, -14 }, // 0x5B '['
- { 1123, 5, 18, 14, 6, -15 }, // 0x5C '\'
- { 1135, 7, 18, 14, 3, -14 }, // 0x5D ']'
- { 1151, 9, 6, 14, 5, -14 }, // 0x5E '^'
- { 1158, 15, 1, 14, -1, 3 }, // 0x5F '_'
- { 1160, 3, 4, 14, 6, -15 }, // 0x60 '`'
- { 1162, 12, 10, 14, 2, -9 }, // 0x61 'a'
- { 1177, 13, 15, 14, 1, -14 }, // 0x62 'b'
- { 1202, 12, 10, 14, 3, -9 }, // 0x63 'c'
- { 1217, 13, 15, 14, 2, -14 }, // 0x64 'd'
- { 1242, 11, 10, 14, 3, -9 }, // 0x65 'e'
- { 1256, 13, 15, 14, 3, -14 }, // 0x66 'f'
- { 1281, 13, 14, 14, 3, -9 }, // 0x67 'g'
- { 1304, 13, 15, 14, 1, -14 }, // 0x68 'h'
- { 1329, 10, 15, 14, 2, -14 }, // 0x69 'i'
- { 1348, 10, 19, 14, 2, -14 }, // 0x6A 'j'
- { 1372, 12, 15, 14, 2, -14 }, // 0x6B 'k'
- { 1395, 10, 15, 14, 2, -14 }, // 0x6C 'l'
- { 1414, 14, 10, 14, 0, -9 }, // 0x6D 'm'
- { 1432, 12, 10, 14, 1, -9 }, // 0x6E 'n'
- { 1447, 11, 10, 14, 3, -9 }, // 0x6F 'o'
- { 1461, 14, 14, 14, 0, -9 }, // 0x70 'p'
- { 1486, 13, 14, 14, 3, -9 }, // 0x71 'q'
- { 1509, 13, 10, 14, 2, -9 }, // 0x72 'r'
- { 1526, 10, 10, 14, 3, -9 }, // 0x73 's'
- { 1539, 9, 14, 14, 3, -13 }, // 0x74 't'
- { 1555, 12, 10, 14, 2, -9 }, // 0x75 'u'
- { 1570, 13, 10, 14, 3, -9 }, // 0x76 'v'
- { 1587, 13, 10, 14, 3, -9 }, // 0x77 'w'
- { 1604, 14, 10, 14, 1, -9 }, // 0x78 'x'
- { 1622, 14, 14, 14, 1, -9 }, // 0x79 'y'
- { 1647, 11, 10, 14, 3, -9 }, // 0x7A 'z'
- { 1661, 7, 18, 14, 5, -14 }, // 0x7B '{'
- { 1677, 4, 17, 14, 6, -13 }, // 0x7C '|'
- { 1686, 7, 18, 14, 4, -14 }, // 0x7D '}'
- { 1702, 11, 3, 14, 3, -7 } }; // 0x7E '~'
-
-const GFXfont FreeMonoOblique12pt7b PROGMEM = {
- (uint8_t *)FreeMonoOblique12pt7bBitmaps,
- (GFXglyph *)FreeMonoOblique12pt7bGlyphs,
- 0x20, 0x7E, 24 };
-
-// Approx. 2379 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique18pt7b.h
deleted file mode 100644
index 1979e72..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique18pt7b.h
+++ /dev/null
@@ -1,398 +0,0 @@
-const uint8_t FreeMonoOblique18pt7bBitmaps[] PROGMEM = {
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- 0x3D, 0xE1, 0xEF, 0x0F, 0x70, 0x73, 0x83, 0x98, 0x18, 0xC0, 0xC6, 0x06,
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- 0x40, 0x80, 0x10, 0x40, 0x04, 0x10, 0x02, 0x04, 0x01, 0x01, 0x01, 0x80,
- 0x7F, 0x80, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x40,
- 0x00, 0x10, 0x00, 0x04, 0x00, 0x01, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xF8,
- 0x01, 0x83, 0x01, 0x00, 0xC1, 0x00, 0x21, 0x00, 0x19, 0x00, 0x05, 0x00,
- 0x02, 0x80, 0x01, 0x40, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x28,
- 0x00, 0x14, 0x00, 0x12, 0x00, 0x09, 0x80, 0x08, 0x40, 0x08, 0x30, 0x08,
- 0x0C, 0x18, 0x03, 0xF0, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0xFE, 0x18, 0xC0,
- 0xF0, 0x0F, 0xFE, 0x00, 0x40, 0x60, 0x20, 0x0C, 0x08, 0x01, 0x02, 0x00,
- 0x40, 0x80, 0x10, 0x40, 0x04, 0x10, 0x02, 0x04, 0x01, 0x01, 0x01, 0x80,
- 0x7F, 0x80, 0x20, 0x60, 0x08, 0x0C, 0x02, 0x03, 0x80, 0x80, 0x60, 0x40,
- 0x18, 0x10, 0x03, 0x04, 0x00, 0xC1, 0x00, 0x1B, 0xF8, 0x07, 0x00, 0x7E,
- 0x40, 0x60, 0xF0, 0x20, 0x1C, 0x10, 0x02, 0x08, 0x00, 0x82, 0x00, 0x00,
- 0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xC0, 0x00,
- 0x18, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x11, 0x00, 0x04, 0x40, 0x02,
- 0x38, 0x01, 0x0B, 0x81, 0x82, 0x3F, 0x80, 0x3F, 0xFF, 0xA0, 0x20, 0x50,
- 0x10, 0x28, 0x08, 0x24, 0x08, 0x10, 0x04, 0x00, 0x02, 0x00, 0x01, 0x00,
- 0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10,
- 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00, 0x1F,
- 0xFC, 0x00, 0x7E, 0x0F, 0xC4, 0x00, 0x42, 0x00, 0x10, 0x80, 0x08, 0x20,
- 0x02, 0x08, 0x00, 0x82, 0x00, 0x21, 0x00, 0x08, 0x40, 0x04, 0x10, 0x01,
- 0x04, 0x00, 0x41, 0x00, 0x10, 0x80, 0x0C, 0x20, 0x02, 0x08, 0x00, 0x82,
- 0x00, 0x60, 0x80, 0x10, 0x10, 0x08, 0x06, 0x0C, 0x00, 0x7C, 0x00, 0xFE,
- 0x03, 0xF9, 0x80, 0x02, 0x0C, 0x00, 0x30, 0x20, 0x01, 0x01, 0x00, 0x10,
- 0x08, 0x01, 0x80, 0x60, 0x08, 0x03, 0x00, 0xC0, 0x18, 0x04, 0x00, 0x40,
- 0x60, 0x02, 0x06, 0x00, 0x10, 0x20, 0x00, 0xC3, 0x00, 0x06, 0x10, 0x00,
- 0x31, 0x80, 0x00, 0x88, 0x00, 0x04, 0x80, 0x00, 0x2C, 0x00, 0x01, 0xC0,
- 0x00, 0x0E, 0x00, 0x00, 0x7F, 0x07, 0xF2, 0x00, 0x04, 0x20, 0x00, 0xC2,
- 0x00, 0x08, 0x20, 0xC0, 0x82, 0x0C, 0x18, 0x21, 0xA1, 0x02, 0x1A, 0x10,
- 0x23, 0x23, 0x04, 0x32, 0x30, 0x46, 0x22, 0x04, 0x62, 0x60, 0x4C, 0x26,
- 0x04, 0xC2, 0x40, 0x58, 0x24, 0x05, 0x82, 0xC0, 0x70, 0x28, 0x07, 0x02,
- 0x80, 0xE0, 0x38, 0x0E, 0x03, 0x00, 0x0F, 0xC1, 0xF8, 0x30, 0x03, 0x00,
- 0xC0, 0x30, 0x06, 0x03, 0x00, 0x18, 0x10, 0x00, 0xC1, 0x00, 0x03, 0x18,
- 0x00, 0x09, 0x80, 0x00, 0x78, 0x00, 0x01, 0x80, 0x00, 0x1C, 0x00, 0x01,
- 0xA0, 0x00, 0x19, 0x80, 0x01, 0x84, 0x00, 0x18, 0x30, 0x01, 0x80, 0xC0,
- 0x08, 0x06, 0x00, 0x80, 0x18, 0x08, 0x00, 0xC1, 0xF8, 0x3F, 0x80, 0x7E,
- 0x0F, 0xC4, 0x00, 0xC1, 0x80, 0x60, 0x20, 0x30, 0x0C, 0x08, 0x03, 0x04,
- 0x00, 0x43, 0x00, 0x19, 0x80, 0x02, 0xC0, 0x00, 0xE0, 0x00, 0x10, 0x00,
- 0x04, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x20, 0x00, 0x08, 0x00, 0x02,
- 0x00, 0x01, 0x00, 0x00, 0x40, 0x03, 0xFF, 0x80, 0x0F, 0xFF, 0x86, 0x00,
- 0x82, 0x00, 0x81, 0x00, 0xC1, 0x80, 0xC0, 0xC0, 0xC0, 0x00, 0xC0, 0x00,
- 0xC0, 0x00, 0x40, 0x00, 0x40, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00,
- 0x60, 0x10, 0x60, 0x18, 0x20, 0x08, 0x20, 0x04, 0x20, 0x02, 0x30, 0x03,
- 0x1F, 0xFF, 0x80, 0x07, 0xE0, 0x80, 0x10, 0x02, 0x00, 0xC0, 0x18, 0x02,
- 0x00, 0x40, 0x18, 0x03, 0x00, 0x40, 0x08, 0x01, 0x00, 0x60, 0x0C, 0x01,
- 0x00, 0x20, 0x04, 0x01, 0x80, 0x30, 0x04, 0x00, 0x80, 0x10, 0x06, 0x00,
- 0xFC, 0x00, 0x80, 0x80, 0x80, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x20,
- 0x10, 0x10, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x04,
- 0x02, 0x02, 0x02, 0x02, 0x00, 0x07, 0xE0, 0x0C, 0x01, 0x00, 0x20, 0x04,
- 0x01, 0x80, 0x30, 0x04, 0x00, 0x80, 0x30, 0x06, 0x00, 0x80, 0x10, 0x02,
- 0x00, 0xC0, 0x18, 0x02, 0x00, 0x40, 0x18, 0x03, 0x00, 0x40, 0x08, 0x03,
- 0x00, 0x60, 0xF8, 0x00, 0x01, 0x00, 0x1C, 0x01, 0xB0, 0x19, 0x81, 0x86,
- 0x18, 0x11, 0x80, 0xD8, 0x03, 0x80, 0x18, 0xFF, 0xFF, 0xF8, 0xC7, 0x1C,
- 0x71, 0x80, 0x03, 0xF8, 0x0C, 0x0C, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02,
- 0x00, 0x02, 0x07, 0xFC, 0x18, 0x0C, 0x20, 0x04, 0x40, 0x04, 0x80, 0x04,
- 0x80, 0x08, 0x80, 0x38, 0xC0, 0xE8, 0x3F, 0x0F, 0x0F, 0x00, 0x00, 0x20,
- 0x00, 0x04, 0x00, 0x01, 0x80, 0x00, 0x30, 0x00, 0x04, 0x00, 0x00, 0x87,
- 0xC0, 0x13, 0x0C, 0x06, 0x80, 0x40, 0xE0, 0x0C, 0x18, 0x00, 0x82, 0x00,
- 0x10, 0xC0, 0x02, 0x10, 0x00, 0x42, 0x00, 0x08, 0x40, 0x02, 0x08, 0x00,
- 0x43, 0x80, 0x10, 0x70, 0x04, 0x09, 0x83, 0x0F, 0x1F, 0x80, 0x01, 0xFC,
- 0x83, 0x03, 0xC6, 0x00, 0xE4, 0x00, 0x22, 0x00, 0x12, 0x00, 0x01, 0x00,
- 0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x18, 0x00, 0x64,
- 0x00, 0x61, 0x81, 0xC0, 0x7F, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x30, 0x00,
- 0x0C, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x60, 0x3F, 0x18, 0x10, 0x64,
- 0x18, 0x0D, 0x08, 0x01, 0xC2, 0x00, 0x71, 0x00, 0x0C, 0x80, 0x02, 0x20,
- 0x00, 0x88, 0x00, 0x62, 0x00, 0x18, 0x80, 0x0E, 0x20, 0x03, 0x04, 0x03,
- 0x40, 0xC1, 0xB0, 0x1F, 0x8F, 0x00, 0x01, 0xF0, 0x0E, 0x0C, 0x18, 0x06,
- 0x30, 0x02, 0x60, 0x01, 0x40, 0x01, 0xC0, 0x01, 0xFF, 0xFF, 0x80, 0x00,
- 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, 0x60, 0x06, 0x30, 0x1C, 0x0F, 0xE0,
- 0x00, 0x1F, 0xE0, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x40, 0x00, 0x08, 0x00,
- 0x02, 0x00, 0x07, 0xFF, 0xC0, 0x08, 0x00, 0x01, 0x00, 0x00, 0x20, 0x00,
- 0x08, 0x00, 0x01, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00, 0x00, 0x80, 0x00,
- 0x20, 0x00, 0x04, 0x00, 0x00, 0x80, 0x00, 0x10, 0x00, 0x04, 0x00, 0x0F,
- 0xFF, 0x00, 0x03, 0xE3, 0xE1, 0x83, 0x60, 0x40, 0x38, 0x10, 0x03, 0x04,
- 0x00, 0x60, 0x80, 0x0C, 0x20, 0x01, 0x84, 0x00, 0x20, 0x80, 0x04, 0x10,
- 0x01, 0x82, 0x00, 0x30, 0x60, 0x0C, 0x04, 0x02, 0x80, 0x61, 0x90, 0x07,
- 0xC6, 0x00, 0x00, 0xC0, 0x00, 0x10, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00,
- 0x30, 0x00, 0x0C, 0x00, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x40, 0x00,
- 0x10, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x23, 0xE0, 0x0B,
- 0x0C, 0x05, 0x00, 0x81, 0x80, 0x20, 0x40, 0x08, 0x10, 0x02, 0x08, 0x00,
- 0x82, 0x00, 0x60, 0x80, 0x18, 0x20, 0x06, 0x10, 0x01, 0x84, 0x00, 0x61,
- 0x00, 0x30, 0x40, 0x0C, 0xFC, 0x1F, 0xC0, 0x00, 0x30, 0x00, 0x60, 0x00,
- 0xC0, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xF0, 0x00, 0x20,
- 0x00, 0x40, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00,
- 0x40, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x08, 0x00, 0x10, 0x1F, 0xFF,
- 0x80, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x07, 0xFE, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20,
- 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x20, 0x00,
- 0x40, 0x00, 0x80, 0x01, 0x00, 0x06, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20,
- 0x00, 0x80, 0x03, 0x00, 0x0C, 0x0F, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x60,
- 0x00, 0x10, 0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0xC0, 0x00, 0x30, 0xFC,
- 0x08, 0x18, 0x02, 0x0C, 0x00, 0x8C, 0x00, 0x66, 0x00, 0x1B, 0x00, 0x05,
- 0x80, 0x01, 0xB0, 0x00, 0x46, 0x00, 0x31, 0xC0, 0x0C, 0x30, 0x02, 0x06,
- 0x00, 0x80, 0xC0, 0x60, 0x30, 0xF8, 0x1F, 0x80, 0x01, 0xF8, 0x00, 0x20,
- 0x00, 0x40, 0x00, 0x80, 0x01, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00,
- 0x20, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x20,
- 0x00, 0x40, 0x00, 0x80, 0x01, 0x00, 0x04, 0x00, 0x08, 0x0F, 0xFF, 0xC0,
- 0x1C, 0xF1, 0xE0, 0xF1, 0xE3, 0x0E, 0x1C, 0x10, 0xC1, 0x81, 0x08, 0x10,
- 0x30, 0x81, 0x03, 0x18, 0x10, 0x21, 0x83, 0x02, 0x10, 0x30, 0x21, 0x02,
- 0x06, 0x10, 0x20, 0x63, 0x02, 0x04, 0x30, 0x60, 0x42, 0x06, 0x04, 0xF8,
- 0x70, 0xF0, 0x0E, 0x3E, 0x01, 0x60, 0x81, 0xC0, 0x20, 0xC0, 0x10, 0x40,
- 0x08, 0x20, 0x04, 0x30, 0x02, 0x10, 0x02, 0x08, 0x01, 0x04, 0x00, 0x82,
- 0x00, 0x42, 0x00, 0x21, 0x00, 0x20, 0x80, 0x13, 0xF0, 0x3E, 0x01, 0xF0,
- 0x06, 0x0C, 0x18, 0x06, 0x20, 0x03, 0x60, 0x01, 0x40, 0x01, 0x80, 0x01,
- 0x80, 0x01, 0x80, 0x01, 0x80, 0x02, 0x80, 0x06, 0xC0, 0x04, 0x40, 0x18,
- 0x30, 0x60, 0x1F, 0x80, 0x0F, 0x1F, 0x80, 0x16, 0x0C, 0x01, 0xC0, 0x20,
- 0x30, 0x03, 0x03, 0x00, 0x10, 0x20, 0x01, 0x02, 0x00, 0x10, 0x40, 0x01,
- 0x04, 0x00, 0x10, 0x40, 0x02, 0x06, 0x00, 0x60, 0x60, 0x04, 0x0B, 0x00,
- 0x80, 0x98, 0x30, 0x08, 0xFC, 0x00, 0x80, 0x00, 0x08, 0x00, 0x01, 0x00,
- 0x00, 0x10, 0x00, 0x01, 0x00, 0x00, 0x10, 0x00, 0x0F, 0xF0, 0x00, 0x03,
- 0xF1, 0xE1, 0x83, 0x20, 0x40, 0x34, 0x10, 0x03, 0x84, 0x00, 0x30, 0x80,
- 0x04, 0x20, 0x00, 0x84, 0x00, 0x10, 0x80, 0x06, 0x10, 0x00, 0xC2, 0x00,
- 0x30, 0x60, 0x0E, 0x04, 0x03, 0x40, 0x60, 0xC8, 0x07, 0xE2, 0x00, 0x00,
- 0x40, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x20, 0x00, 0x08, 0x00, 0x01,
- 0x00, 0x03, 0xFC, 0x00, 0x0F, 0x87, 0xC0, 0x23, 0x08, 0x04, 0xC0, 0x00,
- 0xE0, 0x00, 0x18, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x10, 0x00, 0x02,
- 0x00, 0x00, 0x40, 0x00, 0x10, 0x00, 0x02, 0x00, 0x00, 0x40, 0x00, 0x08,
- 0x00, 0x3F, 0xFE, 0x00, 0x01, 0xFA, 0x0C, 0x1C, 0x20, 0x08, 0x80, 0x11,
- 0x00, 0x03, 0x00, 0x03, 0xF8, 0x00, 0x7C, 0x00, 0x0C, 0x00, 0x09, 0x00,
- 0x16, 0x00, 0x2C, 0x00, 0x9E, 0x06, 0x27, 0xF0, 0x00, 0x08, 0x00, 0x40,
- 0x02, 0x00, 0x10, 0x00, 0x80, 0x7F, 0xFC, 0x40, 0x02, 0x00, 0x10, 0x00,
- 0x80, 0x08, 0x00, 0x40, 0x02, 0x00, 0x10, 0x01, 0x00, 0x08, 0x00, 0x40,
- 0x02, 0x00, 0xD8, 0x1C, 0x3F, 0x00, 0xF0, 0x1E, 0x20, 0x04, 0x80, 0x09,
- 0x00, 0x12, 0x00, 0x24, 0x00, 0xC8, 0x01, 0x20, 0x02, 0x40, 0x04, 0x80,
- 0x09, 0x00, 0x12, 0x00, 0x64, 0x03, 0x8C, 0x1D, 0x0F, 0xC3, 0x80, 0xFE,
- 0x0F, 0xE6, 0x00, 0x20, 0x40, 0x08, 0x08, 0x03, 0x01, 0x80, 0x40, 0x30,
- 0x18, 0x06, 0x02, 0x00, 0x40, 0x80, 0x08, 0x30, 0x01, 0x84, 0x00, 0x31,
- 0x80, 0x02, 0x20, 0x00, 0x48, 0x00, 0x09, 0x00, 0x01, 0xC0, 0x00, 0xF8,
- 0x0F, 0xA0, 0x01, 0x90, 0x00, 0x88, 0x40, 0xC4, 0x30, 0x42, 0x18, 0x61,
- 0x1A, 0x20, 0x8D, 0x10, 0x4C, 0x98, 0x26, 0x48, 0x16, 0x2C, 0x0B, 0x14,
- 0x07, 0x0A, 0x03, 0x07, 0x01, 0x81, 0x00, 0x0F, 0x83, 0xE0, 0xC0, 0x18,
- 0x0C, 0x0C, 0x01, 0x83, 0x00, 0x18, 0xC0, 0x01, 0xB0, 0x00, 0x1C, 0x00,
- 0x03, 0x00, 0x00, 0xF0, 0x00, 0x63, 0x00, 0x18, 0x30, 0x06, 0x06, 0x01,
- 0x80, 0x60, 0x60, 0x06, 0x3F, 0x07, 0xE0, 0x0F, 0xC0, 0xF8, 0x30, 0x01,
- 0x00, 0x80, 0x18, 0x04, 0x00, 0x80, 0x30, 0x0C, 0x01, 0x80, 0xC0, 0x04,
- 0x04, 0x00, 0x30, 0x60, 0x01, 0x86, 0x00, 0x04, 0x20, 0x00, 0x23, 0x00,
- 0x01, 0xB0, 0x00, 0x0D, 0x00, 0x00, 0x38, 0x00, 0x01, 0x80, 0x00, 0x08,
- 0x00, 0x00, 0xC0, 0x00, 0x04, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00,
- 0x20, 0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xFF, 0x10, 0x06, 0x10, 0x0C, 0x10,
- 0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06,
- 0x00, 0x0C, 0x00, 0x18, 0x04, 0x30, 0x0C, 0x60, 0x0C, 0xFF, 0xF8, 0x00,
- 0xE0, 0x20, 0x08, 0x01, 0x00, 0x20, 0x04, 0x01, 0x00, 0x20, 0x04, 0x00,
- 0x80, 0x20, 0x08, 0x0E, 0x00, 0x60, 0x04, 0x00, 0x80, 0x10, 0x02, 0x00,
- 0x40, 0x08, 0x02, 0x00, 0x40, 0x08, 0x01, 0x00, 0x18, 0x00, 0x00, 0x10,
- 0xC3, 0x08, 0x20, 0x86, 0x18, 0x41, 0x04, 0x30, 0xC2, 0x08, 0x21, 0x86,
- 0x10, 0x43, 0x0C, 0x20, 0x06, 0x00, 0x40, 0x10, 0x04, 0x01, 0x00, 0x40,
- 0x10, 0x04, 0x02, 0x00, 0x80, 0x20, 0x0C, 0x01, 0xC0, 0xC0, 0x40, 0x10,
- 0x04, 0x03, 0x00, 0x80, 0x20, 0x08, 0x02, 0x01, 0x00, 0xC0, 0xE0, 0x00,
- 0x1E, 0x02, 0x66, 0x0D, 0x86, 0x16, 0x06, 0x48, 0x07, 0x00 };
-
-const GFXglyph FreeMonoOblique18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 21, 0, 1 }, // 0x20 ' '
- { 0, 7, 22, 21, 9, -21 }, // 0x21 '!'
- { 20, 13, 10, 21, 7, -20 }, // 0x22 '"'
- { 37, 15, 24, 21, 5, -21 }, // 0x23 '#'
- { 82, 16, 26, 21, 4, -22 }, // 0x24 '$'
- { 134, 16, 21, 21, 5, -20 }, // 0x25 '%'
- { 176, 13, 18, 21, 5, -17 }, // 0x26 '&'
- { 206, 5, 10, 21, 12, -20 }, // 0x27 '''
- { 213, 8, 25, 21, 12, -20 }, // 0x28 '('
- { 238, 8, 25, 21, 5, -20 }, // 0x29 ')'
- { 263, 14, 11, 21, 7, -19 }, // 0x2A '*'
- { 283, 15, 17, 21, 5, -17 }, // 0x2B '+'
- { 315, 9, 10, 21, 4, -4 }, // 0x2C ','
- { 327, 16, 1, 21, 5, -9 }, // 0x2D '-'
- { 329, 5, 5, 21, 8, -4 }, // 0x2E '.'
- { 333, 19, 26, 21, 3, -22 }, // 0x2F '/'
- { 395, 14, 21, 21, 5, -20 }, // 0x30 '0'
- { 432, 13, 21, 21, 4, -20 }, // 0x31 '1'
- { 467, 17, 21, 21, 3, -20 }, // 0x32 '2'
- { 512, 16, 21, 21, 3, -20 }, // 0x33 '3'
- { 554, 14, 21, 21, 5, -20 }, // 0x34 '4'
- { 591, 17, 21, 21, 4, -20 }, // 0x35 '5'
- { 636, 16, 21, 21, 6, -20 }, // 0x36 '6'
- { 678, 13, 21, 21, 8, -20 }, // 0x37 '7'
- { 713, 15, 21, 21, 5, -20 }, // 0x38 '8'
- { 753, 15, 21, 21, 5, -20 }, // 0x39 '9'
- { 793, 7, 15, 21, 8, -14 }, // 0x3A ':'
- { 807, 11, 20, 21, 4, -14 }, // 0x3B ';'
- { 835, 17, 16, 21, 5, -17 }, // 0x3C '<'
- { 869, 19, 6, 21, 3, -12 }, // 0x3D '='
- { 884, 18, 16, 21, 3, -17 }, // 0x3E '>'
- { 920, 12, 20, 21, 8, -19 }, // 0x3F '?'
- { 950, 15, 23, 21, 5, -20 }, // 0x40 '@'
- { 994, 21, 20, 21, 0, -19 }, // 0x41 'A'
- { 1047, 18, 20, 21, 2, -19 }, // 0x42 'B'
- { 1092, 18, 20, 21, 4, -19 }, // 0x43 'C'
- { 1137, 18, 20, 21, 2, -19 }, // 0x44 'D'
- { 1182, 20, 20, 21, 2, -19 }, // 0x45 'E'
- { 1232, 20, 20, 21, 2, -19 }, // 0x46 'F'
- { 1282, 18, 20, 21, 4, -19 }, // 0x47 'G'
- { 1327, 21, 20, 21, 2, -19 }, // 0x48 'H'
- { 1380, 17, 20, 21, 4, -19 }, // 0x49 'I'
- { 1423, 20, 20, 21, 4, -19 }, // 0x4A 'J'
- { 1473, 21, 20, 21, 2, -19 }, // 0x4B 'K'
- { 1526, 18, 20, 21, 2, -19 }, // 0x4C 'L'
- { 1571, 24, 20, 21, 1, -19 }, // 0x4D 'M'
- { 1631, 22, 20, 21, 2, -19 }, // 0x4E 'N'
- { 1686, 17, 20, 21, 4, -19 }, // 0x4F 'O'
- { 1729, 18, 20, 21, 2, -19 }, // 0x50 'P'
- { 1774, 17, 24, 21, 4, -19 }, // 0x51 'Q'
- { 1825, 18, 20, 21, 2, -19 }, // 0x52 'R'
- { 1870, 18, 20, 21, 3, -19 }, // 0x53 'S'
- { 1915, 17, 20, 21, 5, -19 }, // 0x54 'T'
- { 1958, 18, 20, 21, 5, -19 }, // 0x55 'U'
- { 2003, 21, 20, 21, 4, -19 }, // 0x56 'V'
- { 2056, 20, 20, 21, 4, -19 }, // 0x57 'W'
- { 2106, 21, 20, 21, 2, -19 }, // 0x58 'X'
- { 2159, 18, 20, 21, 5, -19 }, // 0x59 'Y'
- { 2204, 17, 20, 21, 4, -19 }, // 0x5A 'Z'
- { 2247, 11, 25, 21, 9, -20 }, // 0x5B '['
- { 2282, 8, 27, 21, 9, -22 }, // 0x5C '\'
- { 2309, 11, 25, 21, 5, -20 }, // 0x5D ']'
- { 2344, 13, 9, 21, 7, -20 }, // 0x5E '^'
- { 2359, 21, 1, 21, -1, 4 }, // 0x5F '_'
- { 2362, 5, 5, 21, 9, -21 }, // 0x60 '`'
- { 2366, 16, 15, 21, 3, -14 }, // 0x61 'a'
- { 2396, 19, 21, 21, 1, -20 }, // 0x62 'b'
- { 2446, 17, 15, 21, 4, -14 }, // 0x63 'c'
- { 2478, 18, 21, 21, 4, -20 }, // 0x64 'd'
- { 2526, 16, 15, 21, 4, -14 }, // 0x65 'e'
- { 2556, 19, 21, 21, 4, -20 }, // 0x66 'f'
- { 2606, 19, 22, 21, 4, -14 }, // 0x67 'g'
- { 2659, 18, 21, 21, 2, -20 }, // 0x68 'h'
- { 2707, 15, 22, 21, 3, -21 }, // 0x69 'i'
- { 2749, 15, 29, 21, 3, -21 }, // 0x6A 'j'
- { 2804, 18, 21, 21, 2, -20 }, // 0x6B 'k'
- { 2852, 15, 21, 21, 3, -20 }, // 0x6C 'l'
- { 2892, 20, 15, 21, 1, -14 }, // 0x6D 'm'
- { 2930, 17, 15, 21, 2, -14 }, // 0x6E 'n'
- { 2962, 16, 15, 21, 4, -14 }, // 0x6F 'o'
- { 2992, 20, 22, 21, 0, -14 }, // 0x70 'p'
- { 3047, 19, 22, 21, 4, -14 }, // 0x71 'q'
- { 3100, 19, 15, 21, 3, -14 }, // 0x72 'r'
- { 3136, 15, 15, 21, 4, -14 }, // 0x73 's'
- { 3165, 13, 20, 21, 5, -19 }, // 0x74 't'
- { 3198, 15, 15, 21, 4, -14 }, // 0x75 'u'
- { 3227, 19, 15, 21, 4, -14 }, // 0x76 'v'
- { 3263, 17, 15, 21, 5, -14 }, // 0x77 'w'
- { 3295, 19, 15, 21, 2, -14 }, // 0x78 'x'
- { 3331, 21, 22, 21, 1, -14 }, // 0x79 'y'
- { 3389, 16, 15, 21, 4, -14 }, // 0x7A 'z'
- { 3419, 11, 25, 21, 8, -20 }, // 0x7B '{'
- { 3454, 6, 24, 21, 9, -19 }, // 0x7C '|'
- { 3472, 10, 25, 21, 6, -20 }, // 0x7D '}'
- { 3504, 15, 5, 21, 5, -11 } }; // 0x7E '~'
-
-const GFXfont FreeMonoOblique18pt7b PROGMEM = {
- (uint8_t *)FreeMonoOblique18pt7bBitmaps,
- (GFXglyph *)FreeMonoOblique18pt7bGlyphs,
- 0x20, 0x7E, 35 };
-
-// Approx. 4186 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique24pt7b.h
deleted file mode 100644
index 8a5592c..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique24pt7b.h
+++ /dev/null
@@ -1,643 +0,0 @@
-const uint8_t FreeMonoOblique24pt7bBitmaps[] PROGMEM = {
- 0x01, 0xC0, 0xF0, 0x3C, 0x0E, 0x03, 0x81, 0xE0, 0x78, 0x1C, 0x07, 0x01,
- 0xC0, 0xE0, 0x38, 0x0E, 0x03, 0x00, 0xC0, 0x70, 0x1C, 0x06, 0x01, 0x80,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x0F, 0x83, 0xE0, 0xF8,
- 0x1C, 0x00, 0x7E, 0x3F, 0x7E, 0x3F, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E,
- 0x78, 0x3C, 0xF8, 0x7C, 0xF0, 0x78, 0xF0, 0x78, 0xF0, 0x78, 0xE0, 0x70,
- 0xE0, 0x70, 0xE0, 0x70, 0xC0, 0x60, 0x00, 0x18, 0x30, 0x00, 0x61, 0x80,
- 0x01, 0x86, 0x00, 0x04, 0x18, 0x00, 0x30, 0xC0, 0x00, 0xC3, 0x00, 0x03,
- 0x0C, 0x00, 0x18, 0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18,
- 0x07, 0xFF, 0xFF, 0x1F, 0xFF, 0xFC, 0x03, 0x0C, 0x00, 0x18, 0x30, 0x00,
- 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18, 0x00, 0x30, 0xC0, 0x1F, 0xFF,
- 0xF8, 0x7F, 0xFF, 0xE0, 0x18, 0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00,
- 0x06, 0x18, 0x00, 0x30, 0x40, 0x00, 0xC3, 0x00, 0x03, 0x0C, 0x00, 0x18,
- 0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18, 0x00, 0x00, 0x03,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0x80, 0x00, 0x3F, 0x00, 0x07, 0xFD, 0x80,
- 0x70, 0x7C, 0x06, 0x00, 0xE0, 0x60, 0x02, 0x07, 0x00, 0x10, 0x30, 0x00,
- 0x01, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x70, 0x00, 0x01, 0xF0, 0x00, 0x07,
- 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18,
- 0x00, 0x00, 0xC2, 0x00, 0x06, 0x30, 0x00, 0x61, 0x80, 0x03, 0x1E, 0x00,
- 0x30, 0xFC, 0x07, 0x06, 0x7F, 0xF0, 0x00, 0xFE, 0x00, 0x01, 0x80, 0x00,
- 0x0C, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80,
- 0x00, 0x00, 0x78, 0x00, 0x07, 0xF8, 0x00, 0x38, 0x60, 0x01, 0xC0, 0xC0,
- 0x06, 0x03, 0x00, 0x30, 0x0C, 0x00, 0xC0, 0x30, 0x03, 0x01, 0x80, 0x0C,
- 0x0E, 0x00, 0x38, 0x70, 0x00, 0x7F, 0x81, 0xC0, 0xF8, 0x3F, 0x00, 0x07,
- 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xC0, 0x00, 0x78, 0x00, 0x01,
- 0x00, 0x78, 0x00, 0x07, 0xF8, 0x00, 0x38, 0x60, 0x01, 0x80, 0xC0, 0x06,
- 0x03, 0x00, 0x30, 0x0C, 0x00, 0xC0, 0x30, 0x03, 0x01, 0x80, 0x0C, 0x0E,
- 0x00, 0x18, 0x70, 0x00, 0x7F, 0x80, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00,
- 0x0F, 0xF8, 0x03, 0x8E, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x06, 0x00, 0x00,
- 0xC0, 0x00, 0x18, 0x00, 0x01, 0x00, 0x00, 0x30, 0x00, 0x06, 0x00, 0x03,
- 0xE0, 0x01, 0xCC, 0x0E, 0x60, 0xC3, 0xD8, 0x18, 0x63, 0x03, 0x18, 0xC0,
- 0x33, 0x18, 0x06, 0xC3, 0x00, 0x70, 0x60, 0x0E, 0x0C, 0x01, 0xC0, 0xC0,
- 0x78, 0x1C, 0x3B, 0xE1, 0xFE, 0x3C, 0x1F, 0x00, 0x00, 0x7E, 0xFD, 0xF3,
- 0xE7, 0xCF, 0x3E, 0x78, 0xF1, 0xE3, 0x87, 0x0E, 0x18, 0x00, 0x00, 0x60,
- 0x18, 0x07, 0x00, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x70, 0x0C, 0x03, 0x80,
- 0x60, 0x1C, 0x03, 0x80, 0xE0, 0x1C, 0x03, 0x80, 0xF0, 0x1C, 0x03, 0x80,
- 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x30,
- 0x06, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x30, 0x02, 0x00, 0x01, 0x80, 0x30,
- 0x06, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x07, 0x00, 0xE0, 0x1C, 0x03,
- 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x00,
- 0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x01, 0xC0, 0x38, 0x0E, 0x01,
- 0x80, 0x70, 0x0C, 0x03, 0x00, 0xC0, 0x10, 0x00, 0x00, 0x20, 0x00, 0x18,
- 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x30, 0x0E, 0x0C, 0x0B,
- 0xF3, 0x3E, 0x3F, 0xFE, 0x01, 0xFC, 0x00, 0x3C, 0x00, 0x1F, 0x00, 0x0E,
- 0x60, 0x07, 0x18, 0x01, 0x83, 0x00, 0xC0, 0xC0, 0x60, 0x30, 0x00, 0x00,
- 0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18,
- 0x00, 0x00, 0x60, 0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00,
- 0x00, 0xC0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x30, 0x00, 0x01,
- 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0x01, 0x80,
- 0x00, 0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00,
- 0x03, 0xF0, 0x7E, 0x07, 0xC0, 0xF8, 0x0F, 0x81, 0xF0, 0x1E, 0x03, 0xE0,
- 0x3C, 0x07, 0x80, 0x70, 0x0F, 0x00, 0xE0, 0x0C, 0x00, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xE0, 0x3C, 0xFF, 0xFF, 0xFF, 0xCF, 0x00, 0x00, 0x00, 0x03,
- 0x00, 0x00, 0x03, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0C,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x03, 0x00,
- 0x00, 0x07, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x1C, 0x00,
- 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x70, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x01, 0x80, 0x00, 0x03, 0x00, 0x00,
- 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x18, 0x00, 0x00,
- 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60, 0x00, 0x00, 0xE0, 0x00, 0x00,
- 0xC0, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x0F, 0xF8, 0x01,
- 0xC1, 0xC0, 0x38, 0x0E, 0x07, 0x00, 0x60, 0xE0, 0x03, 0x0C, 0x00, 0x31,
- 0x80, 0x03, 0x18, 0x00, 0x33, 0x00, 0x03, 0x30, 0x00, 0x33, 0x00, 0x03,
- 0x20, 0x00, 0x26, 0x00, 0x06, 0x60, 0x00, 0x66, 0x00, 0x06, 0x40, 0x00,
- 0x4C, 0x00, 0x0C, 0xC0, 0x00, 0xCC, 0x00, 0x0C, 0xC0, 0x01, 0x8C, 0x00,
- 0x18, 0xC0, 0x01, 0x8C, 0x00, 0x30, 0xC0, 0x07, 0x06, 0x00, 0xE0, 0x60,
- 0x1C, 0x03, 0x87, 0x80, 0x3F, 0xF0, 0x00, 0xFC, 0x00, 0x00, 0x0E, 0x00,
- 0x0F, 0x00, 0x0F, 0x80, 0x0E, 0xC0, 0x1C, 0xC0, 0x1C, 0x60, 0x1C, 0x30,
- 0x08, 0x18, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01,
- 0x80, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00,
- 0x18, 0x00, 0x0C, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x01, 0x80,
- 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x1F, 0xFF, 0xFF, 0xFF, 0xF8, 0x00,
- 0x07, 0xE0, 0x00, 0x3F, 0xE0, 0x01, 0xE0, 0xE0, 0x07, 0x00, 0xE0, 0x1C,
- 0x00, 0xE0, 0x30, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x00, 0x03, 0x00, 0x00,
- 0x06, 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03,
- 0x00, 0x00, 0x1C, 0x00, 0x00, 0x70, 0x00, 0x01, 0xC0, 0x00, 0x07, 0x00,
- 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x03, 0x80, 0x00, 0x0E, 0x00, 0x00,
- 0x70, 0x00, 0x01, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x3C, 0x00, 0x00, 0xE0,
- 0x00, 0xC3, 0x80, 0x01, 0x87, 0xFF, 0xFF, 0x0F, 0xFF, 0xFC, 0x00, 0x00,
- 0x0F, 0xC0, 0x01, 0xFF, 0xC0, 0x1E, 0x07, 0x80, 0xE0, 0x06, 0x03, 0x00,
- 0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x0C,
- 0x00, 0x00, 0x60, 0x00, 0x03, 0x80, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x00,
- 0xFE, 0x00, 0x03, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xE0, 0x00, 0x01,
- 0x80, 0x00, 0x03, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0,
- 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xE3, 0x00, 0x07, 0x0E, 0x00,
- 0x38, 0x1E, 0x03, 0xC0, 0x3F, 0xFC, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x03,
- 0xE0, 0x00, 0xF8, 0x00, 0x1B, 0x00, 0x06, 0x60, 0x01, 0x8C, 0x00, 0x63,
- 0x00, 0x18, 0x60, 0x07, 0x0C, 0x00, 0xC1, 0x80, 0x30, 0x30, 0x0C, 0x0C,
- 0x03, 0x01, 0x80, 0xC0, 0x30, 0x18, 0x06, 0x06, 0x00, 0xC1, 0x80, 0x30,
- 0x60, 0x06, 0x18, 0x00, 0xC3, 0xFF, 0xFE, 0x7F, 0xFF, 0xC0, 0x00, 0xC0,
- 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x18, 0x00, 0x03, 0x00,
- 0x0F, 0xFC, 0x01, 0xFF, 0x80, 0x01, 0xFF, 0xF8, 0x0F, 0xFF, 0xC0, 0x40,
- 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00, 0x00,
- 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0xBF, 0xC0, 0x0F, 0xFF,
- 0x80, 0xF8, 0x1E, 0x02, 0x00, 0x30, 0x00, 0x01, 0xC0, 0x00, 0x06, 0x00,
- 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x00, 0x06,
- 0x00, 0x00, 0x30, 0x00, 0x03, 0x80, 0x00, 0x18, 0xC0, 0x01, 0x87, 0x00,
- 0x38, 0x1E, 0x07, 0x80, 0x7F, 0xF8, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x03,
- 0xF0, 0x00, 0xFF, 0xC0, 0x1F, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x01,
- 0x80, 0x00, 0x18, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x00, 0xC0, 0x00,
- 0x0E, 0x00, 0x00, 0x60, 0x00, 0x07, 0x0F, 0x80, 0x31, 0xFF, 0x01, 0x9C,
- 0x3C, 0x0D, 0x80, 0x60, 0xD8, 0x03, 0x87, 0x80, 0x0C, 0x38, 0x00, 0x61,
- 0xC0, 0x03, 0x0C, 0x00, 0x18, 0x60, 0x00, 0xC3, 0x00, 0x0C, 0x18, 0x00,
- 0x60, 0xE0, 0x06, 0x03, 0x00, 0x30, 0x1C, 0x07, 0x00, 0x70, 0x70, 0x01,
- 0xFF, 0x00, 0x07, 0xE0, 0x00, 0x7F, 0xFF, 0xDF, 0xFF, 0xFC, 0x00, 0x0F,
- 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00,
- 0x06, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x18, 0x00, 0x0C,
- 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x30, 0x00, 0x0C, 0x00,
- 0x06, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x18, 0x00, 0x0C,
- 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x00, 0x3F, 0x00, 0x0F,
- 0xFC, 0x01, 0xC1, 0xE0, 0x70, 0x06, 0x06, 0x00, 0x30, 0xC0, 0x03, 0x1C,
- 0x00, 0x31, 0x80, 0x03, 0x18, 0x00, 0x31, 0x80, 0x06, 0x18, 0x00, 0xE0,
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- 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0xC0, 0x00, 0x0C, 0x00, 0x00,
- 0xC0, 0x00, 0x0C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x01, 0x80, 0x00,
- 0x18, 0x00, 0x01, 0x80, 0x00, 0x38, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00,
- 0x03, 0x00, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00,
- 0x03, 0x80, 0xFF, 0xF0, 0x0F, 0xFC, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xE0,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0xC1,
- 0xFF, 0x00, 0x80, 0x70, 0x01, 0x80, 0xC0, 0x01, 0x83, 0x80, 0x01, 0x87,
- 0x00, 0x01, 0x8C, 0x00, 0x03, 0x38, 0x00, 0x03, 0x70, 0x00, 0x03, 0xF8,
- 0x00, 0x03, 0x9C, 0x00, 0x03, 0x0C, 0x00, 0x06, 0x0E, 0x00, 0x06, 0x07,
- 0x00, 0x06, 0x03, 0x80, 0x06, 0x01, 0x80, 0x04, 0x00, 0xC0, 0x0C, 0x00,
- 0xE0, 0xFC, 0x03, 0xFE, 0xFC, 0x03, 0xFC, 0x01, 0xFF, 0x00, 0x3F, 0xE0,
- 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x0C, 0x00, 0x01, 0x80,
- 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0x30, 0x00, 0x06, 0x00,
- 0x01, 0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xC0, 0x00, 0x18, 0x00,
- 0x06, 0x00, 0x00, 0xC0, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0xE0, 0x00,
- 0x18, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x0C, 0x03, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xF0, 0x00, 0x1E, 0x07, 0x81, 0xE7, 0xE1, 0xF8, 0x3D, 0x8E, 0xE3,
- 0x81, 0xE0, 0xF8, 0x30, 0x38, 0x1E, 0x06, 0x06, 0x03, 0x80, 0xC1, 0x80,
- 0x60, 0x18, 0x30, 0x0C, 0x03, 0x06, 0x01, 0x80, 0x60, 0xC0, 0x30, 0x08,
- 0x18, 0x0C, 0x03, 0x06, 0x01, 0x80, 0x60, 0xC0, 0x30, 0x0C, 0x18, 0x06,
- 0x01, 0x83, 0x00, 0x80, 0x60, 0x40, 0x30, 0x0C, 0x18, 0x06, 0x01, 0x83,
- 0x00, 0xC0, 0x30, 0x60, 0x18, 0x06, 0x7F, 0x03, 0xC1, 0xFF, 0xE0, 0xF8,
- 0x3E, 0x00, 0x03, 0xE0, 0x1F, 0x1F, 0xF0, 0x3E, 0x60, 0x70, 0x0F, 0x80,
- 0x70, 0x3C, 0x00, 0x60, 0x70, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03,
- 0x07, 0x00, 0x06, 0x0C, 0x00, 0x1C, 0x18, 0x00, 0x30, 0x30, 0x00, 0x60,
- 0x60, 0x00, 0xC1, 0xC0, 0x01, 0x83, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C,
- 0x00, 0x18, 0x18, 0x00, 0x30, 0x70, 0x00, 0x67, 0xFC, 0x07, 0xFF, 0xF0,
- 0x0F, 0xE0, 0x00, 0x3F, 0x00, 0x07, 0xFF, 0x00, 0x3C, 0x0F, 0x01, 0xC0,
- 0x1C, 0x0C, 0x00, 0x38, 0x60, 0x00, 0x63, 0x00, 0x00, 0xDC, 0x00, 0x03,
- 0x60, 0x00, 0x0D, 0x80, 0x00, 0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0,
- 0x00, 0x1B, 0x00, 0x00, 0x6C, 0x00, 0x03, 0xB0, 0x00, 0x0C, 0x60, 0x00,
- 0x61, 0xC0, 0x03, 0x03, 0x80, 0x38, 0x0F, 0x03, 0xC0, 0x0F, 0xFE, 0x00,
- 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x1F, 0x8F, 0xFE, 0x00, 0xFC,
- 0xE0, 0x78, 0x00, 0xCC, 0x00, 0xE0, 0x06, 0xC0, 0x03, 0x00, 0x3C, 0x00,
- 0x1C, 0x01, 0xC0, 0x00, 0x60, 0x0C, 0x00, 0x03, 0x00, 0xE0, 0x00, 0x18,
- 0x06, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x06, 0x01, 0x80, 0x00, 0x30, 0x0C,
- 0x00, 0x03, 0x00, 0xE0, 0x00, 0x18, 0x07, 0x00, 0x01, 0x80, 0x3C, 0x00,
- 0x1C, 0x01, 0xE0, 0x01, 0xC0, 0x0D, 0x80, 0x1C, 0x00, 0xCF, 0x03, 0xC0,
- 0x06, 0x3F, 0xF8, 0x00, 0x30, 0x7F, 0x00, 0x01, 0x80, 0x00, 0x00, 0x0C,
- 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x30, 0x00,
- 0x00, 0x01, 0x80, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x07, 0xFF, 0x00, 0x00,
- 0x7F, 0xF8, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7F, 0xE1, 0xF0, 0x78,
- 0x1C, 0xFC, 0x38, 0x01, 0xB0, 0x1C, 0x00, 0x2C, 0x0E, 0x00, 0x0F, 0x03,
- 0x00, 0x01, 0xC1, 0x80, 0x00, 0x60, 0x60, 0x00, 0x18, 0x30, 0x00, 0x06,
- 0x0C, 0x00, 0x01, 0x83, 0x00, 0x00, 0x60, 0xC0, 0x00, 0x30, 0x30, 0x00,
- 0x0C, 0x0C, 0x00, 0x07, 0x03, 0x80, 0x03, 0xC0, 0x60, 0x01, 0xB0, 0x1C,
- 0x00, 0xD8, 0x03, 0xC0, 0xE6, 0x00, 0x7F, 0xF1, 0x80, 0x07, 0xE0, 0x60,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
- 0xC0, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00,
- 0x7F, 0xF8, 0x00, 0x1F, 0xFE, 0x00, 0x07, 0xF0, 0x3E, 0x03, 0xF8, 0x7F,
- 0xC0, 0x18, 0xF0, 0x60, 0x0C, 0xE0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xC0,
- 0x00, 0x03, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0x30, 0x00, 0x00, 0x38, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C,
- 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x80, 0x00, 0x01,
- 0x80, 0x00, 0x3F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF0, 0x00, 0x00, 0x3F, 0x00,
- 0x0F, 0xFE, 0xC0, 0xF0, 0x3E, 0x0E, 0x00, 0x70, 0xE0, 0x01, 0x06, 0x00,
- 0x08, 0x30, 0x00, 0x41, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x3F, 0xF0, 0x00,
- 0x3F, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00,
- 0xCC, 0x00, 0x06, 0x60, 0x00, 0x33, 0x00, 0x03, 0x3C, 0x00, 0x71, 0xF8,
- 0x0F, 0x0D, 0xFF, 0xF0, 0x01, 0xFC, 0x00, 0x03, 0x00, 0x03, 0x00, 0x01,
- 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x70, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x0C, 0x00, 0x06, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0xC0,
- 0x00, 0xE0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x0E,
- 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x03, 0x38, 0x0F,
- 0x9F, 0xFF, 0x03, 0xF8, 0x00, 0xFC, 0x03, 0xFF, 0xE0, 0x1F, 0xC6, 0x00,
- 0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x18, 0x60, 0x01, 0x86,
- 0x00, 0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x18, 0x60, 0x01,
- 0x86, 0x00, 0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x38, 0x60,
- 0x07, 0x83, 0x80, 0x6C, 0x1E, 0x1E, 0x7C, 0x7F, 0xE3, 0xE0, 0xF8, 0x00,
- 0x00, 0x7F, 0xC0, 0xFF, 0xFF, 0xF0, 0x3F, 0xF1, 0xC0, 0x00, 0xC0, 0x30,
- 0x00, 0x60, 0x0C, 0x00, 0x18, 0x03, 0x00, 0x0C, 0x00, 0xE0, 0x06, 0x00,
- 0x18, 0x01, 0x80, 0x06, 0x00, 0xC0, 0x01, 0x80, 0x30, 0x00, 0x60, 0x18,
- 0x00, 0x0C, 0x0C, 0x00, 0x03, 0x03, 0x00, 0x00, 0xC1, 0x80, 0x00, 0x30,
- 0xC0, 0x00, 0x06, 0x30, 0x00, 0x01, 0x98, 0x00, 0x00, 0x6C, 0x00, 0x00,
- 0x1F, 0x00, 0x00, 0x07, 0x80, 0x00, 0xFE, 0x00, 0x7F, 0xFF, 0x00, 0x3F,
- 0xCC, 0x00, 0x03, 0x06, 0x00, 0x01, 0x83, 0x00, 0x01, 0x81, 0x81, 0x80,
- 0xC0, 0xC1, 0xE0, 0x60, 0x60, 0xF0, 0x60, 0x30, 0xD8, 0x30, 0x18, 0x6C,
- 0x30, 0x0C, 0x66, 0x18, 0x06, 0x33, 0x18, 0x03, 0x31, 0x8C, 0x01, 0x98,
- 0x66, 0x00, 0xD8, 0x36, 0x00, 0x6C, 0x1B, 0x00, 0x3C, 0x0F, 0x00, 0x1E,
- 0x07, 0x80, 0x0E, 0x03, 0x80, 0x07, 0x01, 0xC0, 0x00, 0x07, 0xF0, 0x3F,
- 0xC3, 0xFC, 0x0F, 0xF0, 0x38, 0x00, 0x60, 0x07, 0x00, 0x70, 0x00, 0xE0,
- 0x38, 0x00, 0x18, 0x1C, 0x00, 0x03, 0x0C, 0x00, 0x00, 0xEE, 0x00, 0x00,
- 0x1F, 0x00, 0x00, 0x03, 0x80, 0x00, 0x01, 0xE0, 0x00, 0x01, 0xDC, 0x00,
- 0x00, 0xE3, 0x80, 0x00, 0x70, 0x70, 0x00, 0x38, 0x0E, 0x00, 0x18, 0x01,
- 0x80, 0x1C, 0x00, 0x30, 0x0E, 0x00, 0x0E, 0x0F, 0xF0, 0x3F, 0xE3, 0xFC,
- 0x0F, 0xF8, 0x03, 0xF8, 0x07, 0xF8, 0x3F, 0xC0, 0x3F, 0xC0, 0x60, 0x00,
- 0x30, 0x01, 0x80, 0x01, 0x80, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x01, 0x80,
- 0x03, 0x80, 0x0C, 0x00, 0x0C, 0x00, 0xC0, 0x00, 0x60, 0x0C, 0x00, 0x03,
- 0x00, 0x60, 0x00, 0x0C, 0x06, 0x00, 0x00, 0x60, 0x60, 0x00, 0x03, 0x06,
- 0x00, 0x00, 0x1C, 0x30, 0x00, 0x00, 0x63, 0x00, 0x00, 0x03, 0x30, 0x00,
- 0x00, 0x19, 0x80, 0x00, 0x00, 0x78, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00,
- 0x1C, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x60,
- 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x03, 0x00, 0x00,
- 0x00, 0x30, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x0F, 0xFF, 0x80, 0x00, 0x00,
- 0x07, 0xFF, 0xF8, 0x3F, 0xFF, 0xC3, 0x00, 0x0C, 0x18, 0x00, 0xC0, 0xC0,
- 0x0C, 0x00, 0x00, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00,
- 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x01, 0x80,
- 0x00, 0x18, 0x00, 0x01, 0x80, 0x0C, 0x18, 0x00, 0x61, 0x80, 0x02, 0x1F,
- 0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0x00, 0x0E, 0x00, 0x7C, 0x01, 0xC0, 0x03,
- 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x01, 0xC0, 0x03, 0x00,
- 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x01, 0xC0, 0x0F, 0x00, 0xF8,
- 0x01, 0xF0, 0x00, 0x30, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x80,
- 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0xE0, 0x01, 0x80, 0x03,
- 0x00, 0x06, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x01, 0x80, 0xC0,
- 0x60, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x40,
- 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60,
- 0x30, 0x18, 0x08, 0x0C, 0x06, 0x03, 0x01, 0x80, 0x80, 0xC0, 0x60, 0x30,
- 0x00, 0x01, 0xC0, 0x03, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06,
- 0x00, 0x0C, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00,
- 0x0C, 0x00, 0x18, 0x00, 0x38, 0x00, 0x38, 0x00, 0x3E, 0x00, 0x7C, 0x03,
- 0xC0, 0x0E, 0x00, 0x18, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00,
- 0x06, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x00, 0x0E,
- 0x00, 0xF8, 0x01, 0xC0, 0x00, 0x0F, 0x00, 0x01, 0xFC, 0x03, 0x70, 0xE0,
- 0x7E, 0x07, 0x1E, 0xC0, 0x3F, 0x80, 0x01, 0xE0 };
-
-const GFXglyph FreeMonoOblique24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 28, 0, 1 }, // 0x20 ' '
- { 0, 10, 30, 28, 12, -28 }, // 0x21 '!'
- { 38, 16, 14, 28, 10, -28 }, // 0x22 '"'
- { 66, 22, 32, 28, 6, -29 }, // 0x23 '#'
- { 154, 21, 33, 28, 6, -29 }, // 0x24 '$'
- { 241, 22, 29, 28, 6, -27 }, // 0x25 '%'
- { 321, 19, 25, 28, 6, -23 }, // 0x26 '&'
- { 381, 7, 14, 28, 16, -28 }, // 0x27 '''
- { 394, 11, 34, 28, 16, -27 }, // 0x28 '('
- { 441, 11, 34, 28, 7, -27 }, // 0x29 ')'
- { 488, 18, 17, 28, 10, -28 }, // 0x2A '*'
- { 527, 22, 22, 28, 6, -23 }, // 0x2B '+'
- { 588, 12, 14, 28, 5, -6 }, // 0x2C ','
- { 609, 22, 2, 28, 6, -13 }, // 0x2D '-'
- { 615, 7, 6, 28, 11, -4 }, // 0x2E '.'
- { 621, 24, 35, 28, 5, -30 }, // 0x2F '/'
- { 726, 20, 30, 28, 7, -28 }, // 0x30 '0'
- { 801, 17, 29, 28, 6, -28 }, // 0x31 '1'
- { 863, 23, 29, 28, 4, -28 }, // 0x32 '2'
- { 947, 22, 30, 28, 5, -28 }, // 0x33 '3'
- { 1030, 19, 28, 28, 7, -27 }, // 0x34 '4'
- { 1097, 21, 29, 28, 6, -27 }, // 0x35 '5'
- { 1174, 21, 30, 28, 9, -28 }, // 0x36 '6'
- { 1253, 18, 28, 28, 10, -27 }, // 0x37 '7'
- { 1316, 20, 30, 28, 7, -28 }, // 0x38 '8'
- { 1391, 22, 30, 28, 6, -28 }, // 0x39 '9'
- { 1474, 10, 21, 28, 11, -19 }, // 0x3A ':'
- { 1501, 15, 27, 28, 5, -19 }, // 0x3B ';'
- { 1552, 23, 22, 28, 6, -23 }, // 0x3C '<'
- { 1616, 25, 9, 28, 4, -17 }, // 0x3D '='
- { 1645, 24, 22, 28, 4, -23 }, // 0x3E '>'
- { 1711, 16, 28, 28, 11, -26 }, // 0x3F '?'
- { 1767, 19, 32, 28, 7, -28 }, // 0x40 '@'
- { 1843, 27, 26, 28, 1, -25 }, // 0x41 'A'
- { 1931, 26, 26, 28, 2, -25 }, // 0x42 'B'
- { 2016, 25, 28, 28, 5, -26 }, // 0x43 'C'
- { 2104, 26, 26, 28, 2, -25 }, // 0x44 'D'
- { 2189, 27, 26, 28, 2, -25 }, // 0x45 'E'
- { 2277, 28, 26, 28, 2, -25 }, // 0x46 'F'
- { 2368, 25, 28, 28, 5, -26 }, // 0x47 'G'
- { 2456, 27, 26, 28, 3, -25 }, // 0x48 'H'
- { 2544, 22, 26, 28, 6, -25 }, // 0x49 'I'
- { 2616, 28, 27, 28, 5, -25 }, // 0x4A 'J'
- { 2711, 29, 26, 28, 2, -25 }, // 0x4B 'K'
- { 2806, 25, 26, 28, 3, -25 }, // 0x4C 'L'
- { 2888, 32, 26, 28, 1, -25 }, // 0x4D 'M'
- { 2992, 30, 26, 28, 2, -25 }, // 0x4E 'N'
- { 3090, 24, 28, 28, 5, -26 }, // 0x4F 'O'
- { 3174, 26, 26, 28, 2, -25 }, // 0x50 'P'
- { 3259, 24, 32, 28, 5, -26 }, // 0x51 'Q'
- { 3355, 26, 26, 28, 2, -25 }, // 0x52 'R'
- { 3440, 24, 28, 28, 5, -26 }, // 0x53 'S'
- { 3524, 24, 26, 28, 7, -25 }, // 0x54 'T'
- { 3602, 26, 27, 28, 6, -25 }, // 0x55 'U'
- { 3690, 27, 26, 28, 6, -25 }, // 0x56 'V'
- { 3778, 27, 26, 28, 6, -25 }, // 0x57 'W'
- { 3866, 29, 26, 28, 2, -25 }, // 0x58 'X'
- { 3961, 24, 26, 28, 7, -25 }, // 0x59 'Y'
- { 4039, 23, 26, 28, 5, -25 }, // 0x5A 'Z'
- { 4114, 15, 34, 28, 12, -27 }, // 0x5B '['
- { 4178, 10, 35, 28, 12, -30 }, // 0x5C '\'
- { 4222, 15, 34, 28, 6, -27 }, // 0x5D ']'
- { 4286, 18, 12, 28, 9, -28 }, // 0x5E '^'
- { 4313, 28, 2, 28, -1, 5 }, // 0x5F '_'
- { 4320, 6, 7, 28, 13, -29 }, // 0x60 '`'
- { 4326, 22, 22, 28, 4, -20 }, // 0x61 'a'
- { 4387, 27, 29, 28, 1, -27 }, // 0x62 'b'
- { 4485, 22, 22, 28, 6, -20 }, // 0x63 'c'
- { 4546, 25, 29, 28, 5, -27 }, // 0x64 'd'
- { 4637, 22, 22, 28, 5, -20 }, // 0x65 'e'
- { 4698, 26, 28, 28, 5, -27 }, // 0x66 'f'
- { 4789, 25, 30, 28, 5, -20 }, // 0x67 'g'
- { 4883, 24, 28, 28, 3, -27 }, // 0x68 'h'
- { 4967, 19, 29, 28, 5, -28 }, // 0x69 'i'
- { 5036, 20, 38, 28, 4, -28 }, // 0x6A 'j'
- { 5131, 24, 28, 28, 3, -27 }, // 0x6B 'k'
- { 5215, 19, 28, 28, 5, -27 }, // 0x6C 'l'
- { 5282, 27, 21, 28, 1, -20 }, // 0x6D 'm'
- { 5353, 23, 21, 28, 3, -20 }, // 0x6E 'n'
- { 5414, 22, 22, 28, 5, -20 }, // 0x6F 'o'
- { 5475, 29, 30, 28, -1, -20 }, // 0x70 'p'
- { 5584, 26, 30, 28, 5, -20 }, // 0x71 'q'
- { 5682, 25, 20, 28, 4, -19 }, // 0x72 'r'
- { 5745, 21, 22, 28, 5, -20 }, // 0x73 's'
- { 5803, 17, 27, 28, 7, -25 }, // 0x74 't'
- { 5861, 21, 21, 28, 6, -19 }, // 0x75 'u'
- { 5917, 26, 20, 28, 5, -19 }, // 0x76 'v'
- { 5982, 25, 20, 28, 6, -19 }, // 0x77 'w'
- { 6045, 26, 20, 28, 3, -19 }, // 0x78 'x'
- { 6110, 29, 29, 28, 1, -19 }, // 0x79 'y'
- { 6216, 21, 20, 28, 5, -19 }, // 0x7A 'z'
- { 6269, 15, 34, 28, 10, -27 }, // 0x7B '{'
- { 6333, 9, 35, 28, 12, -28 }, // 0x7C '|'
- { 6373, 15, 34, 28, 8, -27 }, // 0x7D '}'
- { 6437, 20, 6, 28, 7, -15 } }; // 0x7E '~'
-
-const GFXfont FreeMonoOblique24pt7b PROGMEM = {
- (uint8_t *)FreeMonoOblique24pt7bBitmaps,
- (GFXglyph *)FreeMonoOblique24pt7bGlyphs,
- 0x20, 0x7E, 47 };
-
-// Approx. 7124 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique9pt7b.h
deleted file mode 100644
index a00ca82..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeMonoOblique9pt7b.h
+++ /dev/null
@@ -1,187 +0,0 @@
-const uint8_t FreeMonoOblique9pt7bBitmaps[] PROGMEM = {
- 0x11, 0x22, 0x24, 0x40, 0x00, 0xC0, 0xDE, 0xE5, 0x29, 0x00, 0x09, 0x05,
- 0x02, 0x82, 0x47, 0xF8, 0xA0, 0x51, 0xFE, 0x28, 0x14, 0x0A, 0x09, 0x00,
- 0x08, 0x1D, 0x23, 0x40, 0x70, 0x1C, 0x02, 0x82, 0x84, 0x78, 0x20, 0x20,
- 0x1C, 0x11, 0x08, 0x83, 0x80, 0x18, 0x71, 0xC0, 0x1C, 0x11, 0x08, 0x83,
- 0x80, 0x1E, 0x60, 0x81, 0x03, 0x0A, 0x65, 0x46, 0x88, 0xE8, 0xFA, 0x80,
- 0x12, 0x24, 0x48, 0x88, 0x88, 0x88, 0x80, 0x01, 0x11, 0x11, 0x11, 0x22,
- 0x44, 0x80, 0x10, 0x22, 0x5B, 0xC3, 0x0A, 0x22, 0x00, 0x04, 0x02, 0x02,
- 0x1F, 0xF0, 0x80, 0x40, 0x20, 0x00, 0x36, 0x4C, 0x80, 0xFF, 0x80, 0xF0,
- 0x00, 0x80, 0x80, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x10, 0x10, 0x10,
- 0x08, 0x08, 0x00, 0x1C, 0x45, 0x0A, 0x18, 0x30, 0x61, 0x42, 0x85, 0x11,
- 0xC0, 0x04, 0x38, 0x90, 0x20, 0x81, 0x02, 0x04, 0x08, 0x23, 0xF8, 0x07,
- 0x04, 0xC4, 0x20, 0x10, 0x10, 0x30, 0x20, 0x20, 0x60, 0x40, 0x3F, 0x80,
- 0x0F, 0x00, 0x40, 0x20, 0x20, 0x60, 0x18, 0x04, 0x02, 0x01, 0x43, 0x1E,
- 0x00, 0x03, 0x05, 0x0A, 0x12, 0x22, 0x22, 0x42, 0x7F, 0x04, 0x04, 0x1E,
- 0x1F, 0x88, 0x08, 0x05, 0xC3, 0x30, 0x08, 0x04, 0x02, 0x02, 0x42, 0x1E,
- 0x00, 0x07, 0x18, 0x20, 0x40, 0x5C, 0xA6, 0xC2, 0x82, 0x82, 0xC4, 0x78,
- 0xFF, 0x04, 0x10, 0x20, 0x82, 0x04, 0x10, 0x20, 0x81, 0x00, 0x1E, 0x23,
- 0x41, 0x41, 0x62, 0x1C, 0x66, 0x82, 0x82, 0x84, 0x78, 0x1E, 0x23, 0x41,
- 0x41, 0x43, 0x65, 0x3A, 0x02, 0x04, 0x18, 0xE0, 0x6C, 0x00, 0x36, 0x18,
- 0xC0, 0x00, 0x19, 0x8C, 0xC4, 0x00, 0x01, 0x83, 0x06, 0x0C, 0x06, 0x00,
- 0x80, 0x30, 0x04, 0xFF, 0x80, 0x00, 0x1F, 0xF0, 0x20, 0x0C, 0x01, 0x00,
- 0x60, 0x20, 0x60, 0xC1, 0x80, 0x3D, 0x8E, 0x08, 0x10, 0xC6, 0x08, 0x00,
- 0x01, 0x80, 0x1C, 0x45, 0x0A, 0x79, 0x34, 0x69, 0x4E, 0x81, 0x03, 0x03,
- 0xC0, 0x0F, 0x00, 0x60, 0x12, 0x02, 0x40, 0x88, 0x21, 0x07, 0xE1, 0x04,
- 0x20, 0x5E, 0x3C, 0x3F, 0x84, 0x11, 0x04, 0x82, 0x3F, 0x88, 0x32, 0x04,
- 0x81, 0x60, 0xBF, 0xC0, 0x1E, 0x98, 0xD0, 0x28, 0x08, 0x04, 0x02, 0x01,
- 0x00, 0x41, 0x1F, 0x00, 0x3F, 0x0C, 0x22, 0x04, 0x81, 0x20, 0x48, 0x12,
- 0x09, 0x02, 0x43, 0x3F, 0x00, 0x3F, 0xC4, 0x11, 0x00, 0x88, 0x3E, 0x08,
- 0x82, 0x00, 0x82, 0x60, 0xBF, 0xE0, 0x3F, 0xE2, 0x08, 0x40, 0x11, 0x03,
- 0xE0, 0x44, 0x08, 0x01, 0x00, 0x60, 0x1F, 0x00, 0x1E, 0x98, 0xD0, 0x08,
- 0x08, 0x04, 0x7A, 0x05, 0x02, 0x41, 0x1F, 0x00, 0x3D, 0xE2, 0x18, 0x42,
- 0x08, 0x43, 0xF8, 0x41, 0x08, 0x21, 0x08, 0x21, 0x1E, 0xF0, 0x3F, 0x82,
- 0x02, 0x01, 0x00, 0x80, 0x40, 0x20, 0x20, 0x10, 0x7F, 0x00, 0x0F, 0xE0,
- 0x20, 0x04, 0x00, 0x80, 0x10, 0x02, 0x20, 0x84, 0x10, 0x84, 0x0F, 0x00,
- 0x3C, 0xE2, 0x10, 0x44, 0x11, 0x02, 0xC0, 0x64, 0x08, 0x81, 0x08, 0x61,
- 0x1E, 0x38, 0x3E, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04, 0x01, 0x04, 0x42,
- 0x10, 0xBF, 0xE0, 0x38, 0x38, 0xC3, 0x05, 0x28, 0x29, 0x42, 0x52, 0x13,
- 0x10, 0x99, 0x84, 0x08, 0x20, 0x47, 0x8F, 0x00, 0x70, 0xE6, 0x08, 0xA1,
- 0x14, 0x22, 0x48, 0x49, 0x11, 0x22, 0x14, 0x43, 0x1E, 0x20, 0x1E, 0x18,
- 0x90, 0x28, 0x18, 0x0C, 0x06, 0x05, 0x02, 0x46, 0x1E, 0x00, 0x3F, 0x84,
- 0x31, 0x04, 0x81, 0x20, 0x8F, 0xC2, 0x00, 0x80, 0x60, 0x3E, 0x00, 0x1E,
- 0x18, 0x90, 0x28, 0x18, 0x0C, 0x06, 0x05, 0x02, 0x46, 0x1E, 0x08, 0x0F,
- 0x44, 0x60, 0x3F, 0x84, 0x31, 0x04, 0x81, 0x20, 0x8F, 0xC2, 0x10, 0x84,
- 0x60, 0xBC, 0x10, 0x0F, 0x88, 0xC8, 0x24, 0x01, 0x80, 0x38, 0x05, 0x02,
- 0xC2, 0x5E, 0x00, 0xFF, 0xC4, 0x44, 0x02, 0x01, 0x00, 0x80, 0x40, 0x60,
- 0x20, 0x7E, 0x00, 0xF1, 0xD0, 0x24, 0x09, 0x02, 0x41, 0xA0, 0x48, 0x12,
- 0x04, 0xC6, 0x1F, 0x00, 0xF1, 0xE8, 0x11, 0x02, 0x20, 0x82, 0x20, 0x44,
- 0x09, 0x01, 0x40, 0x28, 0x02, 0x00, 0xF1, 0xE8, 0x09, 0x12, 0x26, 0x45,
- 0x48, 0xAA, 0x29, 0x45, 0x28, 0xC6, 0x18, 0xC0, 0x38, 0xE2, 0x08, 0x26,
- 0x05, 0x00, 0x40, 0x18, 0x04, 0x81, 0x08, 0x41, 0x1C, 0x70, 0xE3, 0xA0,
- 0x90, 0x84, 0x81, 0x80, 0x80, 0x40, 0x20, 0x20, 0x7E, 0x00, 0x3F, 0x90,
- 0x88, 0x80, 0x80, 0x80, 0x80, 0x80, 0x82, 0x82, 0x7F, 0x00, 0x39, 0x08,
- 0x44, 0x21, 0x08, 0x42, 0x21, 0x0E, 0x00, 0x88, 0x44, 0x44, 0x22, 0x22,
- 0x11, 0x11, 0x38, 0x42, 0x11, 0x08, 0x42, 0x10, 0x84, 0x2E, 0x00, 0x08,
- 0x28, 0x92, 0x18, 0x20, 0xFF, 0xC0, 0xA4, 0x3E, 0x00, 0x80, 0x47, 0xA4,
- 0x34, 0x12, 0x18, 0xF7, 0x38, 0x01, 0x00, 0x40, 0x09, 0xE1, 0xC6, 0x20,
- 0x44, 0x09, 0x01, 0x30, 0x46, 0x13, 0xBC, 0x00, 0x1F, 0x48, 0x74, 0x0A,
- 0x00, 0x80, 0x20, 0x0C, 0x18, 0xF8, 0x01, 0x80, 0x40, 0x23, 0x96, 0x32,
- 0x0A, 0x05, 0x02, 0x81, 0x61, 0x1F, 0xE0, 0x1F, 0x30, 0xD0, 0x3F, 0xF8,
- 0x04, 0x01, 0x00, 0x7C, 0x07, 0xC3, 0x00, 0x80, 0xFE, 0x10, 0x04, 0x01,
- 0x00, 0x40, 0x10, 0x08, 0x0F, 0xE0, 0x1D, 0xD8, 0xC4, 0x12, 0x04, 0x82,
- 0x20, 0x8C, 0x61, 0xE8, 0x02, 0x01, 0x07, 0x80, 0x30, 0x04, 0x01, 0x00,
- 0x5C, 0x38, 0x88, 0x22, 0x08, 0x82, 0x21, 0x18, 0x4F, 0x3C, 0x04, 0x04,
- 0x00, 0x38, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0xFF, 0x01, 0x00, 0x80,
- 0x03, 0xF0, 0x10, 0x08, 0x04, 0x02, 0x02, 0x01, 0x00, 0x80, 0x40, 0x47,
- 0xC0, 0x38, 0x08, 0x04, 0x02, 0x71, 0x20, 0xA0, 0xA0, 0x68, 0x24, 0x11,
- 0x38, 0xE0, 0x3C, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10,
- 0xFF, 0x3E, 0xE2, 0x64, 0x88, 0x91, 0x12, 0x24, 0x48, 0x91, 0x17, 0x33,
- 0x37, 0x14, 0x4C, 0x24, 0x12, 0x09, 0x08, 0x85, 0xE3, 0x1E, 0x10, 0x90,
- 0x30, 0x18, 0x0C, 0x0B, 0x08, 0x78, 0x33, 0xC3, 0x8C, 0x40, 0x88, 0x12,
- 0x02, 0x60, 0x8C, 0x31, 0x78, 0x20, 0x08, 0x03, 0xE0, 0x00, 0x1C, 0xD8,
- 0xC4, 0x12, 0x04, 0x81, 0x20, 0x4C, 0x21, 0xF8, 0x02, 0x00, 0x81, 0xF0,
- 0x73, 0x8E, 0x04, 0x04, 0x02, 0x01, 0x00, 0x81, 0xFC, 0x1F, 0x61, 0x40,
- 0x3C, 0x03, 0x81, 0x82, 0xFC, 0x10, 0x63, 0xF9, 0x02, 0x04, 0x10, 0x20,
- 0x40, 0x7C, 0xE3, 0x10, 0x90, 0x48, 0x24, 0x22, 0x11, 0x18, 0xF6, 0xF3,
- 0xD0, 0x44, 0x10, 0x88, 0x24, 0x09, 0x02, 0x80, 0x40, 0xE1, 0xD0, 0x24,
- 0x91, 0x24, 0x55, 0x19, 0x86, 0x61, 0x10, 0x39, 0xC4, 0x20, 0xB0, 0x30,
- 0x0C, 0x04, 0x86, 0x13, 0x8E, 0x3C, 0x71, 0x04, 0x10, 0x40, 0x88, 0x09,
- 0x00, 0xA0, 0x06, 0x00, 0x40, 0x08, 0x01, 0x00, 0xFC, 0x00, 0x7F, 0x42,
- 0x04, 0x08, 0x10, 0x20, 0x42, 0xFE, 0x0C, 0x41, 0x04, 0x30, 0x8C, 0x08,
- 0x21, 0x04, 0x10, 0x60, 0x24, 0x94, 0x92, 0x52, 0x40, 0x18, 0x20, 0x82,
- 0x10, 0x40, 0xC4, 0x10, 0x82, 0x08, 0xC0, 0x61, 0x24, 0x30 };
-
-const GFXglyph FreeMonoOblique9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 11, 0, 1 }, // 0x20 ' '
- { 0, 4, 11, 11, 4, -10 }, // 0x21 '!'
- { 6, 5, 5, 11, 4, -10 }, // 0x22 '"'
- { 10, 9, 12, 11, 2, -10 }, // 0x23 '#'
- { 24, 8, 12, 11, 3, -10 }, // 0x24 '$'
- { 36, 9, 11, 11, 2, -10 }, // 0x25 '%'
- { 49, 7, 10, 11, 2, -9 }, // 0x26 '&'
- { 58, 2, 5, 11, 6, -10 }, // 0x27 '''
- { 60, 4, 13, 11, 6, -10 }, // 0x28 '('
- { 67, 4, 13, 11, 3, -10 }, // 0x29 ')'
- { 74, 7, 7, 11, 4, -10 }, // 0x2A '*'
- { 81, 9, 8, 11, 2, -8 }, // 0x2B '+'
- { 90, 4, 5, 11, 2, -1 }, // 0x2C ','
- { 93, 9, 1, 11, 2, -5 }, // 0x2D '-'
- { 95, 2, 2, 11, 4, -1 }, // 0x2E '.'
- { 96, 9, 13, 11, 2, -11 }, // 0x2F '/'
- { 111, 7, 11, 11, 3, -10 }, // 0x30 '0'
- { 121, 7, 11, 11, 2, -10 }, // 0x31 '1'
- { 131, 9, 11, 11, 2, -10 }, // 0x32 '2'
- { 144, 9, 11, 11, 2, -10 }, // 0x33 '3'
- { 157, 8, 11, 11, 2, -10 }, // 0x34 '4'
- { 168, 9, 11, 11, 2, -10 }, // 0x35 '5'
- { 181, 8, 11, 11, 3, -10 }, // 0x36 '6'
- { 192, 7, 11, 11, 4, -10 }, // 0x37 '7'
- { 202, 8, 11, 11, 3, -10 }, // 0x38 '8'
- { 213, 8, 11, 11, 3, -10 }, // 0x39 '9'
- { 224, 3, 8, 11, 4, -7 }, // 0x3A ':'
- { 227, 5, 11, 11, 2, -7 }, // 0x3B ';'
- { 234, 9, 8, 11, 2, -8 }, // 0x3C '<'
- { 243, 9, 4, 11, 2, -6 }, // 0x3D '='
- { 248, 9, 8, 11, 2, -8 }, // 0x3E '>'
- { 257, 7, 10, 11, 4, -9 }, // 0x3F '?'
- { 266, 7, 12, 11, 3, -10 }, // 0x40 '@'
- { 277, 11, 10, 11, 0, -9 }, // 0x41 'A'
- { 291, 10, 10, 11, 1, -9 }, // 0x42 'B'
- { 304, 9, 10, 11, 2, -9 }, // 0x43 'C'
- { 316, 10, 10, 11, 1, -9 }, // 0x44 'D'
- { 329, 10, 10, 11, 1, -9 }, // 0x45 'E'
- { 342, 11, 10, 11, 1, -9 }, // 0x46 'F'
- { 356, 9, 10, 11, 2, -9 }, // 0x47 'G'
- { 368, 11, 10, 11, 1, -9 }, // 0x48 'H'
- { 382, 9, 10, 11, 2, -9 }, // 0x49 'I'
- { 394, 11, 10, 11, 2, -9 }, // 0x4A 'J'
- { 408, 11, 10, 11, 1, -9 }, // 0x4B 'K'
- { 422, 10, 10, 11, 1, -9 }, // 0x4C 'L'
- { 435, 13, 10, 11, 0, -9 }, // 0x4D 'M'
- { 452, 11, 10, 11, 1, -9 }, // 0x4E 'N'
- { 466, 9, 10, 11, 2, -9 }, // 0x4F 'O'
- { 478, 10, 10, 11, 1, -9 }, // 0x50 'P'
- { 491, 9, 13, 11, 2, -9 }, // 0x51 'Q'
- { 506, 10, 10, 11, 1, -9 }, // 0x52 'R'
- { 519, 9, 10, 11, 2, -9 }, // 0x53 'S'
- { 531, 9, 10, 11, 3, -9 }, // 0x54 'T'
- { 543, 10, 10, 11, 2, -9 }, // 0x55 'U'
- { 556, 11, 10, 11, 2, -9 }, // 0x56 'V'
- { 570, 11, 10, 11, 2, -9 }, // 0x57 'W'
- { 584, 11, 10, 11, 1, -9 }, // 0x58 'X'
- { 598, 9, 10, 11, 3, -9 }, // 0x59 'Y'
- { 610, 9, 10, 11, 2, -9 }, // 0x5A 'Z'
- { 622, 5, 13, 11, 5, -10 }, // 0x5B '['
- { 631, 4, 14, 11, 4, -11 }, // 0x5C '\'
- { 638, 5, 13, 11, 2, -10 }, // 0x5D ']'
- { 647, 7, 5, 11, 3, -10 }, // 0x5E '^'
- { 652, 11, 1, 11, 0, 2 }, // 0x5F '_'
- { 654, 2, 3, 11, 5, -11 }, // 0x60 '`'
- { 655, 9, 8, 11, 2, -7 }, // 0x61 'a'
- { 664, 11, 11, 11, 0, -10 }, // 0x62 'b'
- { 680, 10, 8, 11, 2, -7 }, // 0x63 'c'
- { 690, 9, 11, 11, 2, -10 }, // 0x64 'd'
- { 703, 9, 8, 11, 2, -7 }, // 0x65 'e'
- { 712, 10, 11, 11, 2, -10 }, // 0x66 'f'
- { 726, 10, 11, 11, 2, -7 }, // 0x67 'g'
- { 740, 10, 11, 11, 1, -10 }, // 0x68 'h'
- { 754, 8, 11, 11, 2, -10 }, // 0x69 'i'
- { 765, 9, 14, 11, 1, -10 }, // 0x6A 'j'
- { 781, 9, 11, 11, 1, -10 }, // 0x6B 'k'
- { 794, 8, 11, 11, 2, -10 }, // 0x6C 'l'
- { 805, 11, 8, 11, 0, -7 }, // 0x6D 'm'
- { 816, 9, 8, 11, 1, -7 }, // 0x6E 'n'
- { 825, 9, 8, 11, 2, -7 }, // 0x6F 'o'
- { 834, 11, 11, 11, 0, -7 }, // 0x70 'p'
- { 850, 10, 11, 11, 2, -7 }, // 0x71 'q'
- { 864, 9, 8, 11, 2, -7 }, // 0x72 'r'
- { 873, 8, 8, 11, 2, -7 }, // 0x73 's'
- { 881, 7, 10, 11, 2, -9 }, // 0x74 't'
- { 890, 9, 8, 11, 2, -7 }, // 0x75 'u'
- { 899, 10, 8, 11, 2, -7 }, // 0x76 'v'
- { 909, 10, 8, 11, 2, -7 }, // 0x77 'w'
- { 919, 10, 8, 11, 1, -7 }, // 0x78 'x'
- { 929, 12, 11, 11, 0, -7 }, // 0x79 'y'
- { 946, 8, 8, 11, 2, -7 }, // 0x7A 'z'
- { 954, 6, 13, 11, 4, -10 }, // 0x7B '{'
- { 964, 3, 12, 11, 5, -9 }, // 0x7C '|'
- { 969, 6, 13, 11, 3, -10 }, // 0x7D '}'
- { 979, 7, 3, 11, 3, -6 } }; // 0x7E '~'
-
-const GFXfont FreeMonoOblique9pt7b PROGMEM = {
- (uint8_t *)FreeMonoOblique9pt7bBitmaps,
- (GFXglyph *)FreeMonoOblique9pt7bGlyphs,
- 0x20, 0x7E, 18 };
-
-// Approx. 1654 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans12pt7b.h
deleted file mode 100644
index 9ecbb8f..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans12pt7b.h
+++ /dev/null
@@ -1,270 +0,0 @@
-const uint8_t FreeSans12pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0xCF, 0x3C, 0xF3, 0x8A, 0x20, 0x06, 0x30,
- 0x31, 0x03, 0x18, 0x18, 0xC7, 0xFF, 0xBF, 0xFC, 0x31, 0x03, 0x18, 0x18,
- 0xC7, 0xFF, 0xBF, 0xFC, 0x31, 0x01, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x30,
- 0x04, 0x03, 0xE1, 0xFF, 0x72, 0x6C, 0x47, 0x88, 0xF1, 0x07, 0x20, 0x7E,
- 0x03, 0xF0, 0x17, 0x02, 0x3C, 0x47, 0x88, 0xF1, 0x1B, 0x26, 0x7F, 0xC3,
- 0xE0, 0x10, 0x02, 0x00, 0x00, 0x06, 0x03, 0xC0, 0x40, 0x7E, 0x0C, 0x0E,
- 0x70, 0x80, 0xC3, 0x18, 0x0C, 0x31, 0x00, 0xE7, 0x30, 0x07, 0xE6, 0x00,
- 0x3C, 0x40, 0x00, 0x0C, 0x7C, 0x00, 0x8F, 0xE0, 0x19, 0xC7, 0x01, 0x18,
- 0x30, 0x31, 0x83, 0x02, 0x1C, 0x70, 0x40, 0xFE, 0x04, 0x07, 0xC0, 0x0F,
- 0x00, 0x7E, 0x03, 0x9C, 0x0C, 0x30, 0x30, 0xC0, 0xE7, 0x01, 0xF8, 0x03,
- 0x80, 0x3E, 0x01, 0xCC, 0x6E, 0x19, 0xB0, 0x7C, 0xC0, 0xF3, 0x03, 0xCE,
- 0x1F, 0x9F, 0xE6, 0x1E, 0x1C, 0xFF, 0xA0, 0x08, 0x8C, 0x66, 0x31, 0x98,
- 0xC6, 0x31, 0x8C, 0x63, 0x08, 0x63, 0x08, 0x61, 0x0C, 0x20, 0x82, 0x18,
- 0xC3, 0x18, 0xC3, 0x18, 0xC6, 0x31, 0x8C, 0x62, 0x31, 0x88, 0xC4, 0x62,
- 0x00, 0x10, 0x23, 0x5B, 0xE3, 0x8D, 0x91, 0x00, 0x0C, 0x03, 0x00, 0xC0,
- 0x30, 0xFF, 0xFF, 0xF0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0xF5, 0x60,
- 0xFF, 0xF0, 0xF0, 0x02, 0x0C, 0x10, 0x20, 0xC1, 0x02, 0x0C, 0x10, 0x20,
- 0xC1, 0x02, 0x0C, 0x10, 0x20, 0xC1, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x30,
- 0x6E, 0x0F, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C,
- 0x0E, 0xC1, 0x9C, 0x71, 0xFC, 0x1F, 0x00, 0x08, 0xCF, 0xFF, 0x8C, 0x63,
- 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0x1F, 0x0F, 0xF9, 0x87, 0x60, 0x7C,
- 0x06, 0x00, 0xC0, 0x18, 0x07, 0x01, 0xC0, 0xF0, 0x78, 0x1C, 0x06, 0x00,
- 0x80, 0x30, 0x07, 0xFF, 0xFF, 0xE0, 0x3F, 0x0F, 0xF3, 0x87, 0x60, 0x6C,
- 0x0C, 0x01, 0x80, 0x70, 0x7C, 0x0F, 0x80, 0x18, 0x01, 0x80, 0x3C, 0x07,
- 0x80, 0xD8, 0x73, 0xFC, 0x1F, 0x00, 0x01, 0x80, 0x70, 0x0E, 0x03, 0xC0,
- 0xD8, 0x1B, 0x06, 0x61, 0x8C, 0x21, 0x8C, 0x33, 0x06, 0x7F, 0xFF, 0xFE,
- 0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x3F, 0xCF, 0xF9, 0x80, 0x30, 0x06,
- 0x00, 0xDE, 0x1F, 0xE7, 0x0E, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x07,
- 0x81, 0xF8, 0x73, 0xFC, 0x1F, 0x00, 0x0F, 0x07, 0xF9, 0xC3, 0x30, 0x74,
- 0x01, 0x80, 0x33, 0xC7, 0xFE, 0xF0, 0xDC, 0x1F, 0x01, 0xE0, 0x3C, 0x06,
- 0xC1, 0xDC, 0x71, 0xFC, 0x1F, 0x00, 0xFF, 0xFF, 0xFC, 0x01, 0x00, 0x60,
- 0x18, 0x02, 0x00, 0xC0, 0x30, 0x06, 0x01, 0x80, 0x30, 0x04, 0x01, 0x80,
- 0x30, 0x06, 0x01, 0x80, 0x30, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x30, 0x66,
- 0x0C, 0xC1, 0x8C, 0x61, 0xFC, 0x3F, 0x8E, 0x3B, 0x01, 0xE0, 0x3C, 0x07,
- 0x80, 0xD8, 0x31, 0xFC, 0x1F, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x6C,
- 0x07, 0x80, 0xF0, 0x1E, 0x07, 0x61, 0xEF, 0xFC, 0x79, 0x80, 0x30, 0x05,
- 0x81, 0x98, 0x73, 0xFC, 0x1E, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0xF0, 0x00,
- 0x0F, 0x56, 0x00, 0x00, 0x07, 0x01, 0xE0, 0xF8, 0x3C, 0x0F, 0x00, 0xE0,
- 0x07, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xFF, 0xFF, 0xFF, 0x00,
- 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0E, 0x00, 0x78, 0x01, 0xF0, 0x07,
- 0xC0, 0x0F, 0x00, 0x70, 0x1E, 0x0F, 0x03, 0xC0, 0xF0, 0x08, 0x00, 0x1F,
- 0x1F, 0xEE, 0x1B, 0x03, 0xC0, 0xC0, 0x30, 0x0C, 0x06, 0x03, 0x81, 0xC0,
- 0xE0, 0x30, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0xFE,
- 0x00, 0x0F, 0xFE, 0x00, 0xF0, 0x3E, 0x07, 0x00, 0x3C, 0x38, 0x00, 0x30,
- 0xC1, 0xE0, 0x66, 0x0F, 0xD9, 0xD8, 0x61, 0xC3, 0xC3, 0x07, 0x0F, 0x1C,
- 0x1C, 0x3C, 0x60, 0x60, 0xF1, 0x81, 0x83, 0xC6, 0x06, 0x1B, 0x18, 0x38,
- 0xEE, 0x71, 0xE7, 0x18, 0xFD, 0xF8, 0x71, 0xE7, 0xC0, 0xE0, 0x00, 0x01,
- 0xE0, 0x00, 0x01, 0xFF, 0xC0, 0x01, 0xFC, 0x00, 0x03, 0xC0, 0x03, 0xC0,
- 0x03, 0xC0, 0x07, 0xE0, 0x06, 0x60, 0x06, 0x60, 0x0E, 0x70, 0x0C, 0x30,
- 0x0C, 0x30, 0x1C, 0x38, 0x18, 0x18, 0x1F, 0xF8, 0x3F, 0xFC, 0x30, 0x1C,
- 0x30, 0x0C, 0x70, 0x0E, 0x60, 0x06, 0x60, 0x06, 0xFF, 0xC7, 0xFF, 0x30,
- 0x19, 0x80, 0x6C, 0x03, 0x60, 0x1B, 0x00, 0xD8, 0x0C, 0xFF, 0xC7, 0xFF,
- 0x30, 0x0D, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x06, 0xFF, 0xF7,
- 0xFE, 0x00, 0x07, 0xE0, 0x3F, 0xF0, 0xE0, 0x73, 0x80, 0x66, 0x00, 0x6C,
- 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06, 0x00,
- 0x06, 0x00, 0x6C, 0x00, 0xDC, 0x03, 0x1E, 0x0E, 0x1F, 0xF8, 0x0F, 0xC0,
- 0xFF, 0x83, 0xFF, 0x8C, 0x07, 0x30, 0x0E, 0xC0, 0x1B, 0x00, 0x7C, 0x00,
- 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1F, 0x00,
- 0x6C, 0x03, 0xB0, 0x1C, 0xFF, 0xE3, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xC0,
- 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xFF, 0xEF, 0xFE, 0xC0,
- 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xFF, 0xDF,
- 0xFB, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x00,
- 0x07, 0xF0, 0x1F, 0xFC, 0x3C, 0x1E, 0x70, 0x06, 0x60, 0x03, 0xE0, 0x00,
- 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x7F, 0xC0, 0x7F, 0xC0, 0x03, 0xC0, 0x03,
- 0x60, 0x03, 0x60, 0x07, 0x30, 0x0F, 0x3C, 0x1F, 0x1F, 0xFB, 0x07, 0xE1,
- 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78,
- 0x03, 0xFF, 0xFF, 0xFF, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00,
- 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x01,
- 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x60,
- 0x3C, 0x1E, 0x0F, 0x07, 0xC7, 0x7F, 0x1F, 0x00, 0xC0, 0x3B, 0x01, 0xCC,
- 0x0E, 0x30, 0x70, 0xC3, 0x83, 0x1C, 0x0C, 0xE0, 0x33, 0x80, 0xDE, 0x03,
- 0xDC, 0x0E, 0x38, 0x30, 0x60, 0xC1, 0xC3, 0x03, 0x8C, 0x06, 0x30, 0x1C,
- 0xC0, 0x3B, 0x00, 0x60, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C,
- 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00,
- 0xFF, 0xFF, 0xF0, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0F, 0xF0, 0x0F, 0xD0,
- 0x0F, 0xD8, 0x1B, 0xD8, 0x1B, 0xD8, 0x1B, 0xCC, 0x33, 0xCC, 0x33, 0xCC,
- 0x33, 0xC6, 0x63, 0xC6, 0x63, 0xC6, 0x63, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0xC1, 0x83, 0xE0, 0x1F, 0x00, 0xFC, 0x07, 0xE0, 0x3D, 0x81, 0xEE,
- 0x0F, 0x30, 0x79, 0xC3, 0xC6, 0x1E, 0x18, 0xF0, 0xE7, 0x83, 0x3C, 0x1D,
- 0xE0, 0x6F, 0x01, 0xF8, 0x0F, 0xC0, 0x3E, 0x01, 0xC0, 0x03, 0xE0, 0x0F,
- 0xFC, 0x0F, 0x07, 0x86, 0x00, 0xC6, 0x00, 0x33, 0x00, 0x1B, 0x00, 0x07,
- 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x36, 0x00,
- 0x33, 0x00, 0x18, 0xC0, 0x18, 0x78, 0x3C, 0x1F, 0xFC, 0x03, 0xF8, 0x00,
- 0xFF, 0x8F, 0xFE, 0xC0, 0x6C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x07,
- 0xFF, 0xEF, 0xFC, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00,
- 0xC0, 0x0C, 0x00, 0x03, 0xE0, 0x0F, 0xFC, 0x0F, 0x07, 0x86, 0x00, 0xC6,
- 0x00, 0x33, 0x00, 0x1B, 0x00, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,
- 0xF0, 0x00, 0x78, 0x00, 0x36, 0x00, 0x33, 0x01, 0x98, 0xC0, 0xFC, 0x78,
- 0x3C, 0x1F, 0xFF, 0x03, 0xF9, 0x80, 0x00, 0x40, 0xFF, 0xC3, 0xFF, 0xCC,
- 0x03, 0xB0, 0x06, 0xC0, 0x1B, 0x00, 0x6C, 0x01, 0xB0, 0x0C, 0xFF, 0xE3,
- 0xFF, 0xCC, 0x03, 0xB0, 0x06, 0xC0, 0x1B, 0x00, 0x6C, 0x01, 0xB0, 0x06,
- 0xC0, 0x1B, 0x00, 0x70, 0x0F, 0xE0, 0x7F, 0xC3, 0x83, 0x9C, 0x07, 0x60,
- 0x0D, 0x80, 0x06, 0x00, 0x1E, 0x00, 0x3F, 0x80, 0x3F, 0xC0, 0x0F, 0x80,
- 0x07, 0xC0, 0x0F, 0x00, 0x3E, 0x00, 0xDE, 0x0E, 0x3F, 0xF0, 0x3F, 0x80,
- 0xFF, 0xFF, 0xFF, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0,
- 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01,
- 0xE0, 0x0F, 0x80, 0xEE, 0x0E, 0x3F, 0xE0, 0x7C, 0x00, 0x60, 0x06, 0xC0,
- 0x1D, 0xC0, 0x31, 0x80, 0x63, 0x01, 0xC7, 0x03, 0x06, 0x06, 0x0C, 0x1C,
- 0x1C, 0x30, 0x18, 0x60, 0x31, 0xC0, 0x73, 0x00, 0x66, 0x00, 0xDC, 0x01,
- 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0xE0, 0x30, 0x1D, 0x80, 0xE0,
- 0x76, 0x07, 0x81, 0xD8, 0x1E, 0x06, 0x70, 0x7C, 0x18, 0xC1, 0xB0, 0xE3,
- 0x0C, 0xC3, 0x8C, 0x33, 0x0C, 0x38, 0xC6, 0x30, 0x67, 0x18, 0xC1, 0x98,
- 0x67, 0x06, 0x61, 0xD8, 0x1D, 0x83, 0x60, 0x3C, 0x0D, 0x80, 0xF0, 0x3E,
- 0x03, 0xC0, 0x70, 0x0F, 0x01, 0xC0, 0x18, 0x07, 0x00, 0x70, 0x0E, 0x60,
- 0x38, 0xE0, 0x60, 0xE1, 0xC0, 0xC3, 0x01, 0xCC, 0x01, 0xF8, 0x01, 0xE0,
- 0x03, 0x80, 0x07, 0x80, 0x1F, 0x00, 0x33, 0x00, 0xE7, 0x03, 0x86, 0x06,
- 0x0E, 0x1C, 0x0E, 0x70, 0x0C, 0xC0, 0x1C, 0x60, 0x06, 0x70, 0x0E, 0x30,
- 0x1C, 0x38, 0x18, 0x1C, 0x38, 0x0C, 0x30, 0x0E, 0x70, 0x06, 0x60, 0x03,
- 0xC0, 0x03, 0xC0, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
- 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xC0, 0x0E,
- 0x00, 0xE0, 0x0E, 0x00, 0x60, 0x07, 0x00, 0x70, 0x07, 0x00, 0x30, 0x03,
- 0x80, 0x38, 0x03, 0x80, 0x18, 0x01, 0xC0, 0x1C, 0x00, 0xFF, 0xFF, 0xFF,
- 0xC0, 0xFF, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCF,
- 0xF0, 0x81, 0x81, 0x02, 0x06, 0x04, 0x08, 0x18, 0x10, 0x20, 0x60, 0x40,
- 0x81, 0x81, 0x02, 0x06, 0x04, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x3F, 0xF0, 0x0C, 0x0E, 0x05, 0x86, 0xC3, 0x21, 0x19,
- 0x8C, 0x83, 0xC1, 0x80, 0xFF, 0xFE, 0xE3, 0x8C, 0x30, 0x3F, 0x07, 0xF8,
- 0xE1, 0xCC, 0x0C, 0x00, 0xC0, 0x1C, 0x3F, 0xCF, 0x8C, 0xC0, 0xCC, 0x0C,
- 0xE3, 0xC7, 0xEF, 0x3C, 0x70, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0,
- 0x0C, 0xF8, 0xDF, 0xCF, 0x0E, 0xE0, 0x7C, 0x03, 0xC0, 0x3C, 0x03, 0xC0,
- 0x3C, 0x03, 0xE0, 0x6F, 0x0E, 0xDF, 0xCC, 0xF8, 0x1F, 0x0F, 0xE7, 0x1B,
- 0x83, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x38, 0x37, 0x1C, 0xFE, 0x1F,
- 0x00, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x3C, 0xCF, 0xFB, 0x8F,
- 0xE0, 0xF8, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF8, 0x3B, 0x8F, 0x3F,
- 0x63, 0xCC, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x3C, 0x07, 0xFF, 0xFF, 0xFE,
- 0x00, 0xC0, 0x1C, 0x0D, 0xC3, 0x1F, 0xE1, 0xF0, 0x3B, 0xD8, 0xC6, 0x7F,
- 0xEC, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x00, 0x1E, 0x67, 0xFD, 0xC7,
- 0xF0, 0x7C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x7C, 0x1D, 0xC7, 0x9F,
- 0xB1, 0xE6, 0x00, 0xC0, 0x3E, 0x0E, 0x7F, 0xC7, 0xE0, 0xC0, 0x30, 0x0C,
- 0x03, 0x00, 0xC0, 0x33, 0xCD, 0xFB, 0xC7, 0xE0, 0xF0, 0x3C, 0x0F, 0x03,
- 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x30, 0xF0, 0x3F, 0xFF, 0xFF,
- 0xF0, 0x33, 0x00, 0x03, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F,
- 0xE0, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01, 0x83, 0x30, 0xC6, 0x30,
- 0xCC, 0x1B, 0x83, 0xF0, 0x77, 0x0C, 0x61, 0x8E, 0x30, 0xE6, 0x0C, 0xC1,
- 0xD8, 0x18, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xCF, 0x1F, 0x6F, 0xDF, 0xFC,
- 0x78, 0xFC, 0x18, 0x3C, 0x0C, 0x1E, 0x06, 0x0F, 0x03, 0x07, 0x81, 0x83,
- 0xC0, 0xC1, 0xE0, 0x60, 0xF0, 0x30, 0x78, 0x18, 0x3C, 0x0C, 0x18, 0xCF,
- 0x37, 0xEF, 0x1F, 0x83, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C,
- 0x0F, 0x03, 0xC0, 0xC0, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x7C, 0x07, 0x80,
- 0xF0, 0x1E, 0x03, 0xC0, 0x7C, 0x1D, 0xC7, 0x1F, 0xC1, 0xF0, 0xCF, 0x8D,
- 0xFC, 0xF0, 0xEE, 0x06, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3E,
- 0x07, 0xF0, 0xEF, 0xFC, 0xCF, 0x8C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x00,
- 0x1E, 0x67, 0xFD, 0xC7, 0xF0, 0x7C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0,
- 0x7C, 0x1D, 0xC7, 0x9F, 0xF1, 0xE6, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60,
- 0xCF, 0x7F, 0x38, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC0, 0x3E, 0x1F,
- 0xEE, 0x1B, 0x00, 0xC0, 0x3C, 0x07, 0xF0, 0x3E, 0x01, 0xF0, 0x3E, 0x1D,
- 0xFE, 0x3E, 0x00, 0x63, 0x19, 0xFF, 0xB1, 0x8C, 0x63, 0x18, 0xC6, 0x31,
- 0xE7, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0,
- 0xF0, 0x7E, 0x3D, 0xFB, 0x3C, 0xC0, 0xE0, 0x66, 0x06, 0x60, 0x67, 0x0C,
- 0x30, 0xC3, 0x0C, 0x39, 0x81, 0x98, 0x19, 0x81, 0xF0, 0x0F, 0x00, 0xE0,
- 0x0E, 0x00, 0xC1, 0xC1, 0xB0, 0xE1, 0xD8, 0x70, 0xCC, 0x2C, 0x66, 0x36,
- 0x31, 0x9B, 0x18, 0xCD, 0x98, 0x64, 0x6C, 0x16, 0x36, 0x0F, 0x1A, 0x07,
- 0x8F, 0x03, 0x83, 0x80, 0xC1, 0xC0, 0x60, 0xEE, 0x18, 0xC6, 0x0C, 0xC1,
- 0xF0, 0x1C, 0x01, 0x80, 0x78, 0x1B, 0x03, 0x30, 0xC7, 0x30, 0x66, 0x06,
- 0xE0, 0x6C, 0x0D, 0x83, 0x38, 0x63, 0x0C, 0x63, 0x0E, 0x60, 0xCC, 0x1B,
- 0x03, 0x60, 0x3C, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0xE0, 0x78, 0x0E,
- 0x00, 0xFF, 0xFF, 0xF0, 0x18, 0x0C, 0x07, 0x03, 0x81, 0xC0, 0x60, 0x30,
- 0x18, 0x0E, 0x03, 0xFF, 0xFF, 0xC0, 0x19, 0xCC, 0x63, 0x18, 0xC6, 0x31,
- 0x99, 0x86, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x1C, 0x60, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFC, 0xC7, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x0C, 0x33, 0x31,
- 0x8C, 0x63, 0x18, 0xC6, 0x73, 0x00, 0x70, 0x3E, 0x09, 0xE4, 0x1F, 0x03,
- 0x80 };
-
-const GFXglyph FreeSans12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 2, 18, 8, 3, -17 }, // 0x21 '!'
- { 5, 6, 6, 8, 1, -16 }, // 0x22 '"'
- { 10, 13, 16, 13, 0, -15 }, // 0x23 '#'
- { 36, 11, 20, 13, 1, -17 }, // 0x24 '$'
- { 64, 20, 17, 21, 1, -16 }, // 0x25 '%'
- { 107, 14, 17, 16, 1, -16 }, // 0x26 '&'
- { 137, 2, 6, 5, 1, -16 }, // 0x27 '''
- { 139, 5, 23, 8, 2, -17 }, // 0x28 '('
- { 154, 5, 23, 8, 1, -17 }, // 0x29 ')'
- { 169, 7, 7, 9, 1, -17 }, // 0x2A '*'
- { 176, 10, 11, 14, 2, -10 }, // 0x2B '+'
- { 190, 2, 6, 7, 2, -1 }, // 0x2C ','
- { 192, 6, 2, 8, 1, -7 }, // 0x2D '-'
- { 194, 2, 2, 6, 2, -1 }, // 0x2E '.'
- { 195, 7, 18, 7, 0, -17 }, // 0x2F '/'
- { 211, 11, 17, 13, 1, -16 }, // 0x30 '0'
- { 235, 5, 17, 13, 3, -16 }, // 0x31 '1'
- { 246, 11, 17, 13, 1, -16 }, // 0x32 '2'
- { 270, 11, 17, 13, 1, -16 }, // 0x33 '3'
- { 294, 11, 17, 13, 1, -16 }, // 0x34 '4'
- { 318, 11, 17, 13, 1, -16 }, // 0x35 '5'
- { 342, 11, 17, 13, 1, -16 }, // 0x36 '6'
- { 366, 11, 17, 13, 1, -16 }, // 0x37 '7'
- { 390, 11, 17, 13, 1, -16 }, // 0x38 '8'
- { 414, 11, 17, 13, 1, -16 }, // 0x39 '9'
- { 438, 2, 13, 6, 2, -12 }, // 0x3A ':'
- { 442, 2, 16, 6, 2, -11 }, // 0x3B ';'
- { 446, 12, 12, 14, 1, -11 }, // 0x3C '<'
- { 464, 12, 6, 14, 1, -8 }, // 0x3D '='
- { 473, 12, 12, 14, 1, -11 }, // 0x3E '>'
- { 491, 10, 18, 13, 2, -17 }, // 0x3F '?'
- { 514, 22, 21, 24, 1, -17 }, // 0x40 '@'
- { 572, 16, 18, 16, 0, -17 }, // 0x41 'A'
- { 608, 13, 18, 16, 2, -17 }, // 0x42 'B'
- { 638, 15, 18, 17, 1, -17 }, // 0x43 'C'
- { 672, 14, 18, 17, 2, -17 }, // 0x44 'D'
- { 704, 12, 18, 15, 2, -17 }, // 0x45 'E'
- { 731, 11, 18, 14, 2, -17 }, // 0x46 'F'
- { 756, 16, 18, 18, 1, -17 }, // 0x47 'G'
- { 792, 13, 18, 17, 2, -17 }, // 0x48 'H'
- { 822, 2, 18, 7, 2, -17 }, // 0x49 'I'
- { 827, 9, 18, 13, 1, -17 }, // 0x4A 'J'
- { 848, 14, 18, 16, 2, -17 }, // 0x4B 'K'
- { 880, 10, 18, 14, 2, -17 }, // 0x4C 'L'
- { 903, 16, 18, 20, 2, -17 }, // 0x4D 'M'
- { 939, 13, 18, 18, 2, -17 }, // 0x4E 'N'
- { 969, 17, 18, 19, 1, -17 }, // 0x4F 'O'
- { 1008, 12, 18, 16, 2, -17 }, // 0x50 'P'
- { 1035, 17, 19, 19, 1, -17 }, // 0x51 'Q'
- { 1076, 14, 18, 17, 2, -17 }, // 0x52 'R'
- { 1108, 14, 18, 16, 1, -17 }, // 0x53 'S'
- { 1140, 12, 18, 15, 1, -17 }, // 0x54 'T'
- { 1167, 13, 18, 17, 2, -17 }, // 0x55 'U'
- { 1197, 15, 18, 15, 0, -17 }, // 0x56 'V'
- { 1231, 22, 18, 22, 0, -17 }, // 0x57 'W'
- { 1281, 15, 18, 16, 0, -17 }, // 0x58 'X'
- { 1315, 16, 18, 16, 0, -17 }, // 0x59 'Y'
- { 1351, 13, 18, 15, 1, -17 }, // 0x5A 'Z'
- { 1381, 4, 23, 7, 2, -17 }, // 0x5B '['
- { 1393, 7, 18, 7, 0, -17 }, // 0x5C '\'
- { 1409, 4, 23, 7, 1, -17 }, // 0x5D ']'
- { 1421, 9, 9, 11, 1, -16 }, // 0x5E '^'
- { 1432, 15, 1, 13, -1, 4 }, // 0x5F '_'
- { 1434, 5, 4, 6, 1, -17 }, // 0x60 '`'
- { 1437, 12, 13, 13, 1, -12 }, // 0x61 'a'
- { 1457, 12, 18, 13, 1, -17 }, // 0x62 'b'
- { 1484, 10, 13, 12, 1, -12 }, // 0x63 'c'
- { 1501, 11, 18, 13, 1, -17 }, // 0x64 'd'
- { 1526, 11, 13, 13, 1, -12 }, // 0x65 'e'
- { 1544, 5, 18, 7, 1, -17 }, // 0x66 'f'
- { 1556, 11, 18, 13, 1, -12 }, // 0x67 'g'
- { 1581, 10, 18, 13, 1, -17 }, // 0x68 'h'
- { 1604, 2, 18, 5, 2, -17 }, // 0x69 'i'
- { 1609, 4, 23, 6, 0, -17 }, // 0x6A 'j'
- { 1621, 11, 18, 12, 1, -17 }, // 0x6B 'k'
- { 1646, 2, 18, 5, 1, -17 }, // 0x6C 'l'
- { 1651, 17, 13, 19, 1, -12 }, // 0x6D 'm'
- { 1679, 10, 13, 13, 1, -12 }, // 0x6E 'n'
- { 1696, 11, 13, 13, 1, -12 }, // 0x6F 'o'
- { 1714, 12, 17, 13, 1, -12 }, // 0x70 'p'
- { 1740, 11, 17, 13, 1, -12 }, // 0x71 'q'
- { 1764, 6, 13, 8, 1, -12 }, // 0x72 'r'
- { 1774, 10, 13, 12, 1, -12 }, // 0x73 's'
- { 1791, 5, 16, 7, 1, -15 }, // 0x74 't'
- { 1801, 10, 13, 13, 1, -12 }, // 0x75 'u'
- { 1818, 12, 13, 12, 0, -12 }, // 0x76 'v'
- { 1838, 17, 13, 17, 0, -12 }, // 0x77 'w'
- { 1866, 11, 13, 11, 0, -12 }, // 0x78 'x'
- { 1884, 11, 18, 11, 0, -12 }, // 0x79 'y'
- { 1909, 10, 13, 12, 1, -12 }, // 0x7A 'z'
- { 1926, 5, 23, 8, 1, -17 }, // 0x7B '{'
- { 1941, 2, 23, 6, 2, -17 }, // 0x7C '|'
- { 1947, 5, 23, 8, 2, -17 }, // 0x7D '}'
- { 1962, 10, 5, 12, 1, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSans12pt7b PROGMEM = {
- (uint8_t *)FreeSans12pt7bBitmaps,
- (GFXglyph *)FreeSans12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2641 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans18pt7b.h
deleted file mode 100644
index 3fdc591..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans18pt7b.h
+++ /dev/null
@@ -1,452 +0,0 @@
-const uint8_t FreeSans18pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE9, 0x20, 0x3F, 0xFC, 0xE3, 0xF1,
- 0xF8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8E, 0x82, 0x41, 0x00, 0x01, 0xC3, 0x80,
- 0x38, 0x70, 0x06, 0x0E, 0x00, 0xC1, 0x80, 0x38, 0x70, 0x07, 0x0E, 0x0F,
- 0xFF, 0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE0, 0xE1, 0xC0, 0x1C, 0x38, 0x03,
- 0x87, 0x00, 0x70, 0xE0, 0x0C, 0x18, 0x3F, 0xFF, 0xF7, 0xFF, 0xFE, 0xFF,
- 0xFF, 0xC1, 0xC3, 0x80, 0x30, 0x60, 0x06, 0x0C, 0x01, 0xC3, 0x80, 0x38,
- 0x70, 0x07, 0x0E, 0x00, 0xC1, 0x80, 0x03, 0x00, 0x0F, 0xC0, 0x3F, 0xF0,
- 0x3F, 0xF8, 0x7B, 0x3C, 0xF3, 0x1C, 0xE3, 0x0E, 0xE3, 0x0E, 0xE3, 0x0E,
- 0xE3, 0x00, 0xE3, 0x00, 0xF3, 0x00, 0x7B, 0x00, 0x7F, 0x80, 0x1F, 0xF0,
- 0x07, 0xFC, 0x03, 0x7E, 0x03, 0x0F, 0x03, 0x07, 0xE3, 0x07, 0xE3, 0x07,
- 0xE3, 0x07, 0xE3, 0x0F, 0x73, 0x3E, 0x7F, 0xFC, 0x3F, 0xF8, 0x0F, 0xE0,
- 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x78, 0x00,
- 0xE0, 0x0F, 0xF0, 0x06, 0x00, 0xFF, 0xC0, 0x70, 0x07, 0x0E, 0x07, 0x00,
- 0x70, 0x38, 0x38, 0x03, 0x00, 0xC3, 0x80, 0x18, 0x06, 0x1C, 0x00, 0xE0,
- 0x71, 0xC0, 0x03, 0x87, 0x8C, 0x00, 0x1F, 0xF8, 0xE0, 0x00, 0x7F, 0x86,
- 0x00, 0x01, 0xF8, 0x70, 0x00, 0x00, 0x03, 0x03, 0xC0, 0x00, 0x38, 0x7F,
- 0x80, 0x01, 0x87, 0xFE, 0x00, 0x1C, 0x38, 0x70, 0x00, 0xC3, 0x81, 0xC0,
- 0x0E, 0x18, 0x06, 0x00, 0xE0, 0xC0, 0x30, 0x07, 0x07, 0x03, 0x80, 0x70,
- 0x1C, 0x38, 0x03, 0x80, 0xFF, 0xC0, 0x38, 0x03, 0xFC, 0x01, 0x80, 0x07,
- 0x80, 0x01, 0xF0, 0x00, 0x7F, 0x80, 0x0F, 0xFC, 0x01, 0xE1, 0xE0, 0x1C,
- 0x0E, 0x01, 0xC0, 0xE0, 0x1C, 0x0E, 0x01, 0xE1, 0xE0, 0x0E, 0x3C, 0x00,
- 0x77, 0x80, 0x07, 0xF0, 0x00, 0x7C, 0x00, 0x0F, 0xE0, 0x03, 0xCF, 0x1C,
- 0x78, 0x79, 0xC7, 0x03, 0xDC, 0xE0, 0x1F, 0x8E, 0x00, 0xF8, 0xE0, 0x0F,
- 0x0E, 0x00, 0x70, 0xF0, 0x0F, 0x87, 0xC3, 0xFC, 0x7F, 0xFD, 0xC3, 0xFF,
- 0x0E, 0x0F, 0xC0, 0xF0, 0xFF, 0xFF, 0xFA, 0x40, 0x06, 0x06, 0x0C, 0x0C,
- 0x18, 0x18, 0x38, 0x30, 0x70, 0x70, 0x70, 0x60, 0xE0, 0xE0, 0xE0, 0xE0,
- 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x70, 0x70, 0x70, 0x30, 0x38, 0x18,
- 0x18, 0x0C, 0x0C, 0x06, 0x03, 0xC0, 0x60, 0x30, 0x30, 0x38, 0x18, 0x1C,
- 0x0C, 0x0E, 0x0E, 0x0E, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
- 0x07, 0x07, 0x06, 0x0E, 0x0E, 0x0E, 0x0C, 0x1C, 0x18, 0x38, 0x30, 0x30,
- 0x60, 0xC0, 0x0C, 0x03, 0x00, 0xC3, 0xB7, 0xFF, 0xC7, 0x81, 0xE0, 0xEC,
- 0x73, 0x88, 0x40, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
- 0x80, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01,
- 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0xFF,
- 0xF6, 0xDA, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xC0, 0x30, 0x18,
- 0x06, 0x01, 0x80, 0xC0, 0x30, 0x0C, 0x06, 0x01, 0x80, 0x60, 0x30, 0x0C,
- 0x03, 0x00, 0xC0, 0x60, 0x18, 0x06, 0x03, 0x00, 0xC0, 0x30, 0x18, 0x06,
- 0x01, 0x80, 0xC0, 0x30, 0x00, 0x07, 0xE0, 0x0F, 0xF8, 0x1F, 0xFC, 0x3C,
- 0x3C, 0x78, 0x1E, 0x70, 0x0E, 0x70, 0x0E, 0xE0, 0x07, 0xE0, 0x07, 0xE0,
- 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0,
- 0x07, 0xE0, 0x07, 0xE0, 0x0F, 0x70, 0x0E, 0x70, 0x0E, 0x78, 0x1E, 0x3C,
- 0x3C, 0x1F, 0xF8, 0x1F, 0xF0, 0x07, 0xE0, 0x03, 0x03, 0x07, 0x0F, 0x3F,
- 0xFF, 0xFF, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
- 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xE0, 0x1F, 0xF8,
- 0x3F, 0xFC, 0x7C, 0x3E, 0x70, 0x0F, 0xF0, 0x0F, 0xE0, 0x07, 0xE0, 0x07,
- 0x00, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF8,
- 0x03, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x70, 0x00,
- 0x60, 0x00, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xF0,
- 0x07, 0xFE, 0x07, 0xFF, 0x87, 0x83, 0xC3, 0x80, 0xF3, 0x80, 0x39, 0xC0,
- 0x1C, 0xE0, 0x0E, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x7F, 0x00, 0x3F, 0x00,
- 0x1F, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x07, 0x00, 0x03, 0xF0, 0x01,
- 0xF8, 0x00, 0xFE, 0x00, 0x77, 0x00, 0x73, 0xE0, 0xF8, 0xFF, 0xF8, 0x3F,
- 0xF8, 0x07, 0xF0, 0x00, 0x00, 0x38, 0x00, 0x38, 0x00, 0x78, 0x00, 0xF8,
- 0x00, 0xF8, 0x01, 0xF8, 0x03, 0xB8, 0x03, 0x38, 0x07, 0x38, 0x0E, 0x38,
- 0x1C, 0x38, 0x18, 0x38, 0x38, 0x38, 0x70, 0x38, 0x60, 0x38, 0xE0, 0x38,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38,
- 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x1F, 0xFF, 0x0F, 0xFF, 0x8F, 0xFF,
- 0xC7, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x39,
- 0xF0, 0x3F, 0xFE, 0x1F, 0xFF, 0x8F, 0x83, 0xE7, 0x00, 0xF0, 0x00, 0x3C,
- 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xFC, 0x00,
- 0xEF, 0x00, 0x73, 0xC0, 0xF0, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xE0, 0x00,
- 0x03, 0xE0, 0x0F, 0xF8, 0x1F, 0xFC, 0x3C, 0x1E, 0x38, 0x0E, 0x70, 0x0E,
- 0x70, 0x00, 0x60, 0x00, 0xE0, 0x00, 0xE3, 0xE0, 0xEF, 0xF8, 0xFF, 0xFC,
- 0xFC, 0x3E, 0xF0, 0x0E, 0xF0, 0x0F, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07,
- 0x60, 0x07, 0x70, 0x0F, 0x70, 0x0E, 0x3C, 0x3E, 0x3F, 0xFC, 0x1F, 0xF8,
- 0x07, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x06, 0x00, 0x0E,
- 0x00, 0x1C, 0x00, 0x18, 0x00, 0x38, 0x00, 0x70, 0x00, 0x60, 0x00, 0xE0,
- 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x80, 0x03, 0x80, 0x07, 0x00,
- 0x07, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0C, 0x00,
- 0x1C, 0x00, 0x1C, 0x00, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0x83,
- 0xC7, 0x80, 0xF3, 0x80, 0x39, 0xC0, 0x1C, 0xE0, 0x0E, 0x78, 0x0F, 0x1E,
- 0x0F, 0x07, 0xFF, 0x01, 0xFF, 0x03, 0xFF, 0xE3, 0xE0, 0xF9, 0xC0, 0x1D,
- 0xC0, 0x0F, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0xF7, 0x00,
- 0x73, 0xE0, 0xF8, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x07, 0xE0,
- 0x1F, 0xF8, 0x3F, 0xFC, 0x7C, 0x3C, 0x70, 0x0E, 0xF0, 0x0E, 0xE0, 0x06,
- 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x0F, 0x70, 0x0F, 0x78, 0x3F,
- 0x3F, 0xFF, 0x1F, 0xF7, 0x07, 0xC7, 0x00, 0x07, 0x00, 0x06, 0x00, 0x0E,
- 0x70, 0x0E, 0x70, 0x1C, 0x78, 0x3C, 0x3F, 0xF8, 0x1F, 0xF0, 0x07, 0xC0,
- 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x07, 0xFF, 0x80, 0xFF, 0xF0, 0x00, 0x00,
- 0x00, 0x07, 0xFF, 0xB6, 0xD6, 0x00, 0x00, 0x80, 0x03, 0xC0, 0x07, 0xE0,
- 0x0F, 0xC0, 0x3F, 0x80, 0x7E, 0x00, 0xFC, 0x01, 0xF0, 0x00, 0xE0, 0x00,
- 0x7C, 0x00, 0x1F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x80, 0x07, 0xF0, 0x00,
- 0x7E, 0x00, 0x0F, 0x00, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0x80, 0x80, 0x00, 0x70, 0x00, 0x3E, 0x00, 0x0F, 0xE0, 0x00, 0xFC,
- 0x00, 0x1F, 0xC0, 0x03, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0x80, 0x0F, 0xC0,
- 0x1F, 0x80, 0x7F, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x01, 0xC0, 0x00,
- 0x80, 0x00, 0x00, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE3, 0xC3, 0xEF, 0x01,
- 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0x00, 0x0E, 0x00, 0x38, 0x00, 0xF0,
- 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x00, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E,
- 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x03, 0x80,
- 0x07, 0x00, 0x0E, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x3F, 0xFF, 0x00,
- 0x00, 0xFF, 0xFF, 0xC0, 0x01, 0xF8, 0x0F, 0xE0, 0x03, 0xE0, 0x01, 0xF0,
- 0x07, 0x80, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x1E,
- 0x3C, 0x03, 0xE0, 0x1E, 0x38, 0x0F, 0xF3, 0x8E, 0x78, 0x1E, 0x3F, 0x0F,
- 0x70, 0x38, 0x1F, 0x07, 0x70, 0x78, 0x0F, 0x07, 0xE0, 0x70, 0x0E, 0x07,
- 0xE0, 0x70, 0x0E, 0x07, 0xE0, 0xE0, 0x0E, 0x07, 0xE0, 0xE0, 0x1C, 0x07,
- 0xE0, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x38, 0x1C,
- 0xF0, 0x70, 0x78, 0x3C, 0x70, 0x78, 0xFC, 0x78, 0x78, 0x3F, 0xDF, 0xF0,
- 0x38, 0x1F, 0x0F, 0xC0, 0x3C, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00,
- 0x0F, 0x80, 0x00, 0x00, 0x07, 0xF0, 0x0E, 0x00, 0x01, 0xFF, 0xFE, 0x00,
- 0x00, 0x7F, 0xFE, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x03,
- 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x7F, 0x00, 0x01, 0xDC, 0x00, 0x07, 0x78,
- 0x00, 0x3C, 0xE0, 0x00, 0xE3, 0x80, 0x03, 0x8F, 0x00, 0x1E, 0x1C, 0x00,
- 0x70, 0x70, 0x01, 0xC1, 0xE0, 0x0E, 0x03, 0x80, 0x38, 0x0E, 0x00, 0xE0,
- 0x3C, 0x07, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0xFF, 0xFF, 0x83, 0xC0, 0x0E,
- 0x0E, 0x00, 0x3C, 0x78, 0x00, 0xF1, 0xE0, 0x01, 0xC7, 0x00, 0x07, 0xBC,
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- 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0E,
- 0xF8, 0x1E, 0xFC, 0x3C, 0xEF, 0xFC, 0xEF, 0xF8, 0xE3, 0xE0, 0x07, 0xF0,
- 0x1F, 0xF8, 0x3F, 0xFC, 0x3C, 0x1E, 0x78, 0x0E, 0x70, 0x07, 0xE0, 0x00,
- 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x07,
- 0x70, 0x07, 0x78, 0x0E, 0x7C, 0x1E, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0,
- 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00,
- 0x1C, 0x00, 0x0E, 0x0F, 0xC7, 0x1F, 0xFB, 0x9F, 0xFF, 0xDF, 0x07, 0xEF,
- 0x01, 0xF7, 0x00, 0x7F, 0x80, 0x3F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x03,
- 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0x77, 0x00, 0x7B, 0xC0, 0x7D, 0xF0,
- 0x7E, 0x7F, 0xFB, 0x1F, 0xF9, 0x83, 0xF0, 0xC0, 0x07, 0xE0, 0x1F, 0xF8,
- 0x3F, 0xFC, 0x7C, 0x1E, 0x70, 0x0E, 0x60, 0x06, 0xE0, 0x07, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0x70, 0x07,
- 0x78, 0x0E, 0x3C, 0x1E, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0, 0x0E, 0x3C,
- 0xF9, 0xC3, 0x87, 0x0E, 0x7F, 0xFF, 0xFC, 0xE1, 0xC3, 0x87, 0x0E, 0x1C,
- 0x38, 0x70, 0xE1, 0xC3, 0x87, 0x0E, 0x1C, 0x38, 0x70, 0x07, 0xC7, 0x1F,
- 0xF7, 0x3F, 0xFF, 0x3C, 0x3F, 0x78, 0x0F, 0x70, 0x0F, 0xE0, 0x07, 0xE0,
- 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0x70,
- 0x0F, 0x78, 0x0F, 0x7C, 0x3F, 0x3F, 0xF7, 0x1F, 0xE7, 0x07, 0xC7, 0x00,
- 0x07, 0x00, 0x07, 0x00, 0x0E, 0x70, 0x0E, 0x78, 0x1E, 0x3F, 0xFC, 0x1F,
- 0xF8, 0x07, 0xE0, 0xE0, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,
- 0x1C, 0x00, 0x38, 0x00, 0x71, 0xF8, 0xE7, 0xFD, 0xDF, 0xFB, 0xF0, 0xFF,
- 0xC0, 0xFF, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0,
- 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07,
- 0xE0, 0x0F, 0xC0, 0x1C, 0xFF, 0xF0, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFC, 0x1C, 0x71, 0xC7, 0x00, 0x00, 0x07, 0x1C, 0x71, 0xC7, 0x1C,
- 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C,
- 0x73, 0xFF, 0xFB, 0xC0, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00,
- 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x3C, 0xE0, 0x78, 0xE0, 0xF0,
- 0xE1, 0xE0, 0xE3, 0xC0, 0xE7, 0x80, 0xEF, 0x00, 0xEF, 0x80, 0xFF, 0x80,
- 0xFB, 0xC0, 0xF1, 0xE0, 0xE0, 0xE0, 0xE0, 0xF0, 0xE0, 0x70, 0xE0, 0x78,
- 0xE0, 0x3C, 0xE0, 0x1C, 0xE0, 0x1E, 0xE0, 0x0E, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xE3, 0xE0, 0xF8, 0xE7, 0xF1, 0xFE,
- 0xEF, 0xFB, 0xFE, 0xF8, 0x7F, 0x0F, 0xF0, 0x3E, 0x07, 0xF0, 0x1C, 0x07,
- 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,
- 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,
- 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,
- 0xE0, 0x1C, 0x07, 0xE3, 0xF1, 0xCF, 0xFB, 0xBF, 0xF7, 0xE1, 0xFF, 0x81,
- 0xFE, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F,
- 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0,
- 0x1F, 0x80, 0x38, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0x83, 0xC7,
- 0x80, 0xF3, 0x80, 0x3B, 0x80, 0x1F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x01,
- 0xF8, 0x00, 0xFC, 0x00, 0x7E, 0x00, 0x3B, 0x80, 0x39, 0xE0, 0x3C, 0x78,
- 0x3C, 0x3F, 0xFE, 0x0F, 0xFE, 0x01, 0xFC, 0x00, 0xE3, 0xE0, 0xE7, 0xF8,
- 0xEF, 0xFC, 0xFC, 0x3E, 0xF8, 0x1E, 0xF0, 0x0E, 0xE0, 0x0F, 0xE0, 0x07,
- 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0E,
- 0xF8, 0x1E, 0xFC, 0x3E, 0xFF, 0xFC, 0xEF, 0xF8, 0xE3, 0xE0, 0xE0, 0x00,
- 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0x07, 0xE1,
- 0x8F, 0xFC, 0xCF, 0xFF, 0x67, 0x83, 0xF7, 0x80, 0xFB, 0x80, 0x3F, 0xC0,
- 0x1F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0x7E,
- 0x00, 0x3B, 0x80, 0x3D, 0xE0, 0x3E, 0xF8, 0x3F, 0x3F, 0xFF, 0x8F, 0xFD,
- 0xC1, 0xF8, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00,
- 0x07, 0x00, 0x03, 0x80, 0xE3, 0xF7, 0xFB, 0xFF, 0x8F, 0x07, 0x83, 0x81,
- 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70,
- 0x38, 0x00, 0x0F, 0xC0, 0xFF, 0x87, 0xFF, 0x3C, 0x1E, 0xE0, 0x3B, 0x80,
- 0x0E, 0x00, 0x3C, 0x00, 0x7F, 0x00, 0xFF, 0x80, 0xFF, 0x80, 0x7F, 0x00,
- 0x3F, 0x80, 0x7E, 0x01, 0xFC, 0x1F, 0x7F, 0xF8, 0xFF, 0xC1, 0xFC, 0x00,
- 0x38, 0x70, 0xE1, 0xCF, 0xFF, 0xFF, 0x9C, 0x38, 0x70, 0xE1, 0xC3, 0x87,
- 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC3, 0xE7, 0xC7, 0x80, 0xE0, 0x0F, 0xC0,
- 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07,
- 0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x03, 0xFC,
- 0x0F, 0xFC, 0x3F, 0x7F, 0xEE, 0xFF, 0x9C, 0x7E, 0x38, 0x70, 0x03, 0xB8,
- 0x03, 0x9C, 0x01, 0xC7, 0x00, 0xE3, 0x80, 0xE1, 0xC0, 0x70, 0x70, 0x38,
- 0x38, 0x38, 0x1C, 0x1C, 0x07, 0x0E, 0x03, 0x8E, 0x01, 0xC7, 0x00, 0x77,
- 0x00, 0x3B, 0x80, 0x1D, 0xC0, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,
- 0x70, 0x00, 0xF0, 0x1C, 0x03, 0xB8, 0x1F, 0x03, 0xDC, 0x0F, 0x81, 0xCE,
- 0x07, 0xC0, 0xE7, 0x83, 0xE0, 0x71, 0xC3, 0xB8, 0x70, 0xE1, 0xDC, 0x38,
- 0x70, 0xEE, 0x1C, 0x1C, 0x63, 0x0E, 0x0E, 0x71, 0xCE, 0x07, 0x38, 0xE7,
- 0x03, 0x9C, 0x73, 0x80, 0xEC, 0x19, 0x80, 0x7E, 0x0F, 0xC0, 0x3F, 0x07,
- 0xE0, 0x0F, 0x83, 0xF0, 0x07, 0x80, 0xF0, 0x03, 0xC0, 0x78, 0x01, 0xE0,
- 0x3C, 0x00, 0x70, 0x07, 0x38, 0x0E, 0x3C, 0x1C, 0x1C, 0x1C, 0x0E, 0x38,
- 0x0F, 0x70, 0x07, 0x70, 0x03, 0xE0, 0x03, 0xC0, 0x01, 0xC0, 0x03, 0xE0,
- 0x07, 0xE0, 0x07, 0x70, 0x0E, 0x78, 0x1E, 0x38, 0x1C, 0x1C, 0x38, 0x1E,
- 0x78, 0x0E, 0x70, 0x07, 0x70, 0x07, 0x38, 0x03, 0x9C, 0x01, 0xC7, 0x01,
- 0xC3, 0x80, 0xE1, 0xC0, 0x70, 0x70, 0x70, 0x38, 0x38, 0x1C, 0x3C, 0x07,
- 0x1C, 0x03, 0x8E, 0x01, 0xCE, 0x00, 0x77, 0x00, 0x3B, 0x80, 0x1F, 0x80,
- 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x38,
- 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x3F, 0x00, 0x1F, 0x00, 0x0F,
- 0x00, 0x00, 0x7F, 0xFC, 0xFF, 0xF9, 0xFF, 0xF0, 0x00, 0xE0, 0x03, 0x80,
- 0x0E, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x1C, 0x00, 0x70,
- 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xF8, 0x07, 0x0F, 0x1F, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x38, 0xF8, 0xE0, 0xF8, 0x38, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1F, 0x0F, 0x07, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xE0, 0xF0, 0xF8, 0x38,
- 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x1C, 0x1F,
- 0x07, 0x1F, 0x1C, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
- 0x38, 0x38, 0xF8, 0xF0, 0xE0, 0x38, 0x00, 0xFC, 0x03, 0xFC, 0x1F, 0x3E,
- 0x3C, 0x1F, 0xE0, 0x1F, 0x80, 0x1E, 0x00 };
-
-const GFXglyph FreeSans18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 9, 0, 1 }, // 0x20 ' '
- { 0, 3, 26, 12, 4, -25 }, // 0x21 '!'
- { 10, 9, 9, 12, 1, -24 }, // 0x22 '"'
- { 21, 19, 24, 19, 0, -23 }, // 0x23 '#'
- { 78, 16, 30, 19, 2, -26 }, // 0x24 '$'
- { 138, 29, 25, 31, 1, -24 }, // 0x25 '%'
- { 229, 20, 25, 23, 2, -24 }, // 0x26 '&'
- { 292, 3, 9, 7, 2, -24 }, // 0x27 '''
- { 296, 8, 33, 12, 3, -25 }, // 0x28 '('
- { 329, 8, 33, 12, 1, -25 }, // 0x29 ')'
- { 362, 10, 10, 14, 2, -25 }, // 0x2A '*'
- { 375, 16, 16, 20, 2, -15 }, // 0x2B '+'
- { 407, 3, 9, 10, 3, -3 }, // 0x2C ','
- { 411, 8, 3, 12, 2, -10 }, // 0x2D '-'
- { 414, 3, 4, 9, 3, -3 }, // 0x2E '.'
- { 416, 10, 26, 10, 0, -25 }, // 0x2F '/'
- { 449, 16, 25, 19, 2, -24 }, // 0x30 '0'
- { 499, 8, 25, 19, 4, -24 }, // 0x31 '1'
- { 524, 16, 25, 19, 2, -24 }, // 0x32 '2'
- { 574, 17, 25, 19, 1, -24 }, // 0x33 '3'
- { 628, 16, 25, 19, 1, -24 }, // 0x34 '4'
- { 678, 17, 25, 19, 1, -24 }, // 0x35 '5'
- { 732, 16, 25, 19, 2, -24 }, // 0x36 '6'
- { 782, 16, 25, 19, 2, -24 }, // 0x37 '7'
- { 832, 17, 25, 19, 1, -24 }, // 0x38 '8'
- { 886, 16, 25, 19, 1, -24 }, // 0x39 '9'
- { 936, 3, 19, 9, 3, -18 }, // 0x3A ':'
- { 944, 3, 24, 9, 3, -18 }, // 0x3B ';'
- { 953, 17, 17, 20, 2, -16 }, // 0x3C '<'
- { 990, 17, 9, 20, 2, -12 }, // 0x3D '='
- { 1010, 17, 17, 20, 2, -16 }, // 0x3E '>'
- { 1047, 15, 26, 19, 3, -25 }, // 0x3F '?'
- { 1096, 32, 31, 36, 1, -25 }, // 0x40 '@'
- { 1220, 22, 26, 23, 1, -25 }, // 0x41 'A'
- { 1292, 19, 26, 23, 3, -25 }, // 0x42 'B'
- { 1354, 22, 26, 25, 1, -25 }, // 0x43 'C'
- { 1426, 20, 26, 24, 3, -25 }, // 0x44 'D'
- { 1491, 18, 26, 22, 3, -25 }, // 0x45 'E'
- { 1550, 17, 26, 21, 3, -25 }, // 0x46 'F'
- { 1606, 24, 26, 27, 1, -25 }, // 0x47 'G'
- { 1684, 19, 26, 25, 3, -25 }, // 0x48 'H'
- { 1746, 3, 26, 10, 4, -25 }, // 0x49 'I'
- { 1756, 14, 26, 18, 1, -25 }, // 0x4A 'J'
- { 1802, 20, 26, 24, 3, -25 }, // 0x4B 'K'
- { 1867, 15, 26, 20, 3, -25 }, // 0x4C 'L'
- { 1916, 24, 26, 30, 3, -25 }, // 0x4D 'M'
- { 1994, 20, 26, 26, 3, -25 }, // 0x4E 'N'
- { 2059, 25, 26, 27, 1, -25 }, // 0x4F 'O'
- { 2141, 18, 26, 23, 3, -25 }, // 0x50 'P'
- { 2200, 25, 28, 27, 1, -25 }, // 0x51 'Q'
- { 2288, 20, 26, 25, 3, -25 }, // 0x52 'R'
- { 2353, 20, 26, 23, 1, -25 }, // 0x53 'S'
- { 2418, 19, 26, 22, 1, -25 }, // 0x54 'T'
- { 2480, 19, 26, 25, 3, -25 }, // 0x55 'U'
- { 2542, 21, 26, 23, 1, -25 }, // 0x56 'V'
- { 2611, 32, 26, 33, 0, -25 }, // 0x57 'W'
- { 2715, 21, 26, 23, 1, -25 }, // 0x58 'X'
- { 2784, 23, 26, 24, 0, -25 }, // 0x59 'Y'
- { 2859, 19, 26, 22, 1, -25 }, // 0x5A 'Z'
- { 2921, 6, 33, 10, 2, -25 }, // 0x5B '['
- { 2946, 10, 26, 10, 0, -25 }, // 0x5C '\'
- { 2979, 6, 33, 10, 1, -25 }, // 0x5D ']'
- { 3004, 13, 13, 16, 2, -24 }, // 0x5E '^'
- { 3026, 21, 2, 19, -1, 5 }, // 0x5F '_'
- { 3032, 7, 5, 9, 1, -25 }, // 0x60 '`'
- { 3037, 17, 19, 19, 1, -18 }, // 0x61 'a'
- { 3078, 16, 26, 20, 2, -25 }, // 0x62 'b'
- { 3130, 16, 19, 18, 1, -18 }, // 0x63 'c'
- { 3168, 17, 26, 20, 1, -25 }, // 0x64 'd'
- { 3224, 16, 19, 19, 1, -18 }, // 0x65 'e'
- { 3262, 7, 26, 10, 1, -25 }, // 0x66 'f'
- { 3285, 16, 27, 19, 1, -18 }, // 0x67 'g'
- { 3339, 15, 26, 19, 2, -25 }, // 0x68 'h'
- { 3388, 3, 26, 8, 2, -25 }, // 0x69 'i'
- { 3398, 6, 34, 9, 0, -25 }, // 0x6A 'j'
- { 3424, 16, 26, 18, 2, -25 }, // 0x6B 'k'
- { 3476, 3, 26, 7, 2, -25 }, // 0x6C 'l'
- { 3486, 24, 19, 28, 2, -18 }, // 0x6D 'm'
- { 3543, 15, 19, 19, 2, -18 }, // 0x6E 'n'
- { 3579, 17, 19, 19, 1, -18 }, // 0x6F 'o'
- { 3620, 16, 25, 20, 2, -18 }, // 0x70 'p'
- { 3670, 17, 25, 20, 1, -18 }, // 0x71 'q'
- { 3724, 9, 19, 12, 2, -18 }, // 0x72 'r'
- { 3746, 14, 19, 17, 2, -18 }, // 0x73 's'
- { 3780, 7, 23, 10, 1, -22 }, // 0x74 't'
- { 3801, 15, 19, 19, 2, -18 }, // 0x75 'u'
- { 3837, 17, 19, 17, 0, -18 }, // 0x76 'v'
- { 3878, 25, 19, 25, 0, -18 }, // 0x77 'w'
- { 3938, 16, 19, 17, 0, -18 }, // 0x78 'x'
- { 3976, 17, 27, 17, 0, -18 }, // 0x79 'y'
- { 4034, 15, 19, 17, 1, -18 }, // 0x7A 'z'
- { 4070, 8, 33, 12, 1, -25 }, // 0x7B '{'
- { 4103, 2, 33, 9, 3, -25 }, // 0x7C '|'
- { 4112, 8, 33, 12, 3, -25 }, // 0x7D '}'
- { 4145, 15, 7, 18, 1, -15 } }; // 0x7E '~'
-
-const GFXfont FreeSans18pt7b PROGMEM = {
- (uint8_t *)FreeSans18pt7bBitmaps,
- (GFXglyph *)FreeSans18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 4831 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans24pt7b.h
deleted file mode 100644
index ff2d174..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans24pt7b.h
+++ /dev/null
@@ -1,727 +0,0 @@
-const uint8_t FreeSans24pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x76, 0x66,
- 0x66, 0x00, 0x0F, 0xFF, 0xFF, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1F,
- 0xE3, 0xFC, 0x7F, 0x8F, 0xF1, 0xEC, 0x19, 0x83, 0x30, 0x60, 0x00, 0x70,
- 0x3C, 0x00, 0x70, 0x3C, 0x00, 0xF0, 0x38, 0x00, 0xF0, 0x38, 0x00, 0xF0,
- 0x78, 0x00, 0xE0, 0x78, 0x00, 0xE0, 0x78, 0x01, 0xE0, 0x70, 0x01, 0xE0,
- 0x70, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x03, 0xC0,
- 0xE0, 0x03, 0xC0, 0xE0, 0x03, 0xC0, 0xE0, 0x03, 0x81, 0xE0, 0x03, 0x81,
- 0xE0, 0x03, 0x81, 0xE0, 0x07, 0x81, 0xC0, 0x07, 0x81, 0xC0, 0xFF, 0xFF,
- 0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0x0F, 0x03, 0x80, 0x0F, 0x03,
- 0x80, 0x0F, 0x07, 0x80, 0x0E, 0x07, 0x80, 0x0E, 0x07, 0x80, 0x1E, 0x07,
- 0x00, 0x1E, 0x07, 0x00, 0x1E, 0x07, 0x00, 0x1C, 0x0F, 0x00, 0x1C, 0x0F,
- 0x00, 0x00, 0x38, 0x00, 0x01, 0xFC, 0x00, 0x1F, 0xFE, 0x00, 0x7F, 0xFE,
- 0x01, 0xFF, 0xFE, 0x07, 0xE7, 0x3E, 0x0F, 0x8E, 0x3C, 0x3E, 0x1C, 0x3C,
- 0x78, 0x38, 0x38, 0xF0, 0x70, 0x71, 0xE0, 0xE0, 0xE3, 0xC1, 0xC0, 0x07,
- 0x83, 0x80, 0x0F, 0x87, 0x00, 0x0F, 0x8E, 0x00, 0x1F, 0xDC, 0x00, 0x1F,
- 0xF8, 0x00, 0x1F, 0xFF, 0x00, 0x0F, 0xFF, 0x80, 0x07, 0xFF, 0x80, 0x03,
- 0xFF, 0x80, 0x07, 0x1F, 0x80, 0x0E, 0x1F, 0x00, 0x1C, 0x1F, 0x00, 0x38,
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- 0xC0, 0x1F, 0xCF, 0xE0, 0xFF, 0x8F, 0xFF, 0xF7, 0x0F, 0xFF, 0xCE, 0x0F,
- 0xFF, 0x1C, 0x07, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x0F, 0xFE, 0x00, 0xFF,
- 0xFC, 0x07, 0xFF, 0xF8, 0x1F, 0x83, 0xF0, 0xF8, 0x07, 0xC7, 0xC0, 0x0F,
- 0x9E, 0x00, 0x1E, 0x78, 0x00, 0x7B, 0xC0, 0x00, 0xFF, 0x00, 0x03, 0xFC,
- 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00,
- 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x1E,
- 0x7C, 0x00, 0x78, 0xF8, 0x03, 0xE3, 0xF0, 0x3F, 0x07, 0xFF, 0xF8, 0x0F,
- 0xFF, 0xE0, 0x1F, 0xFE, 0x00, 0x0F, 0xE0, 0x00, 0x03, 0xC3, 0xF0, 0xFC,
- 0x7F, 0x1F, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x3F, 0xFF, 0xFF, 0xFF, 0x1E,
- 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81,
- 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78,
- 0x1E, 0x07, 0x80, 0x00, 0xFC, 0x00, 0x1F, 0xF8, 0xF0, 0xFF, 0xFB, 0xC7,
- 0xFF, 0xFF, 0x3F, 0x83, 0xFC, 0xF8, 0x07, 0xF7, 0xC0, 0x0F, 0xDE, 0x00,
- 0x1F, 0x78, 0x00, 0x7F, 0xE0, 0x00, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F,
- 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0,
- 0x00, 0x3F, 0xC0, 0x00, 0xF7, 0x80, 0x07, 0xDE, 0x00, 0x1F, 0x7C, 0x00,
- 0xFC, 0xF8, 0x07, 0xF3, 0xF8, 0x3F, 0xC7, 0xFF, 0xEF, 0x0F, 0xFF, 0x3C,
- 0x1F, 0xF8, 0xF0, 0x1F, 0x83, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x79, 0xE0,
- 0x01, 0xE7, 0xC0, 0x0F, 0x8F, 0x80, 0xFC, 0x3F, 0xFF, 0xF0, 0x7F, 0xFF,
- 0x80, 0xFF, 0xFC, 0x00, 0x7F, 0x80, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,
- 0x00, 0x78, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x07, 0x80,
- 0x00, 0xF0, 0xFE, 0x1E, 0x3F, 0xE3, 0xCF, 0xFF, 0x7B, 0xFF, 0xEF, 0xF0,
- 0xFF, 0xF8, 0x07, 0xFF, 0x00, 0x7F, 0xC0, 0x0F, 0xF8, 0x01, 0xFE, 0x00,
- 0x3F, 0xC0, 0x07, 0xF8, 0x00, 0xFF, 0x00, 0x1F, 0xE0, 0x03, 0xFC, 0x00,
- 0x7F, 0x80, 0x0F, 0xF0, 0x01, 0xFE, 0x00, 0x3F, 0xC0, 0x07, 0xF8, 0x00,
- 0xFF, 0x00, 0x1F, 0xE0, 0x03, 0xFC, 0x00, 0x7F, 0x80, 0x0F, 0xF0, 0x01,
- 0xFE, 0x00, 0x3C, 0xFF, 0xFF, 0xF0, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x1F,
- 0xFF, 0xFE, 0xFE, 0xF8, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x3C, 0x00, 0x01,
- 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00,
- 0x00, 0xF0, 0x00, 0x07, 0x80, 0x1F, 0x3C, 0x01, 0xF1, 0xE0, 0x1F, 0x0F,
- 0x01, 0xF0, 0x78, 0x1F, 0x03, 0xC1, 0xF0, 0x1E, 0x1F, 0x00, 0xF1, 0xF0,
- 0x07, 0x9F, 0x00, 0x3D, 0xF8, 0x01, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x7F,
- 0x7C, 0x03, 0xF1, 0xF0, 0x1F, 0x07, 0xC0, 0xF0, 0x3E, 0x07, 0x80, 0xF8,
- 0x3C, 0x03, 0xC1, 0xE0, 0x1F, 0x0F, 0x00, 0x7C, 0x78, 0x03, 0xE3, 0xC0,
- 0x0F, 0x9E, 0x00, 0x3C, 0xF0, 0x01, 0xF7, 0x80, 0x07, 0xC0, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0x00, 0xFC, 0x03, 0xF0, 0xE3, 0xFE, 0x0F, 0xFC, 0xE7,
- 0xFF, 0x1F, 0xFE, 0xEF, 0xFF, 0xBF, 0xFE, 0xFE, 0x0F, 0xF8, 0x3F, 0xFC,
- 0x07, 0xF0, 0x1F, 0xF8, 0x03, 0xE0, 0x0F, 0xF8, 0x03, 0xE0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,
- 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0x00,
- 0x7E, 0x0E, 0x1F, 0xF8, 0xE7, 0xFF, 0xCE, 0xFF, 0xFE, 0xEF, 0x07, 0xFF,
- 0xE0, 0x1F, 0xFC, 0x01, 0xFF, 0x80, 0x0F, 0xF8, 0x00, 0xFF, 0x00, 0x0F,
- 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00,
- 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00,
- 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0,
- 0x00, 0xFF, 0x00, 0x0F, 0x00, 0xFE, 0x00, 0x07, 0xFF, 0x00, 0x3F, 0xFF,
- 0x80, 0xFF, 0xFF, 0x83, 0xF8, 0x3F, 0x87, 0xC0, 0x1F, 0x1F, 0x00, 0x1F,
- 0x3C, 0x00, 0x1E, 0x78, 0x00, 0x3D, 0xF0, 0x00, 0x7F, 0xC0, 0x00, 0x7F,
- 0x80, 0x00, 0xFF, 0x00, 0x01, 0xFE, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xF8,
- 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0xF0, 0x00, 0x7D, 0xE0, 0x00, 0xF3, 0xC0,
- 0x01, 0xE7, 0xC0, 0x07, 0xC7, 0xC0, 0x1F, 0x0F, 0xE0, 0xFE, 0x0F, 0xFF,
- 0xF8, 0x0F, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x03, 0xF8, 0x00, 0x00, 0xFE,
- 0x03, 0x8F, 0xFE, 0x0E, 0x7F, 0xFC, 0x3B, 0xFF, 0xF8, 0xFF, 0x87, 0xF3,
- 0xF8, 0x07, 0xCF, 0xC0, 0x0F, 0xBE, 0x00, 0x1E, 0xF8, 0x00, 0x7B, 0xE0,
- 0x01, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00,
- 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x01, 0xFF,
- 0x80, 0x07, 0xBE, 0x00, 0x1E, 0xFC, 0x00, 0xFB, 0xF8, 0x07, 0xCF, 0xF0,
- 0x7F, 0x3F, 0xFF, 0xF8, 0xF7, 0xFF, 0xC3, 0xC7, 0xFE, 0x0F, 0x07, 0xE0,
- 0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C,
- 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,
- 0xFE, 0x00, 0x07, 0xFF, 0x1C, 0x3F, 0xFF, 0x38, 0xFF, 0xFF, 0x73, 0xF8,
- 0x3F, 0xE7, 0xC0, 0x1F, 0xDF, 0x00, 0x1F, 0xBE, 0x00, 0x1F, 0x78, 0x00,
- 0x3F, 0xF0, 0x00, 0x7F, 0xC0, 0x00, 0x7F, 0x80, 0x00, 0xFF, 0x00, 0x01,
- 0xFE, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x1F,
- 0xF0, 0x00, 0x7D, 0xE0, 0x00, 0xFB, 0xC0, 0x01, 0xF7, 0xC0, 0x07, 0xE7,
- 0xC0, 0x1F, 0xCF, 0xE0, 0xFF, 0x8F, 0xFF, 0xEF, 0x0F, 0xFF, 0xDE, 0x0F,
- 0xFE, 0x3C, 0x07, 0xF0, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00,
- 0x03, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x1E, 0x00, 0x00,
- 0x3C, 0x00, 0x00, 0x78, 0x00, 0xFE, 0x1F, 0xE7, 0xFE, 0xFF, 0xFF, 0x8F,
- 0xC0, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0x01, 0xFC, 0x00, 0xFF, 0xF0,
- 0x1F, 0xFF, 0x83, 0xFF, 0xFC, 0x3E, 0x07, 0xE7, 0xC0, 0x3E, 0x78, 0x01,
- 0xE7, 0x80, 0x00, 0x78, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00, 0x03, 0xFC,
- 0x00, 0x1F, 0xFC, 0x00, 0xFF, 0xF8, 0x03, 0xFF, 0xC0, 0x03, 0xFE, 0x00,
- 0x03, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF,
- 0x80, 0x1F, 0x7E, 0x07, 0xE7, 0xFF, 0xFE, 0x3F, 0xFF, 0xC1, 0xFF, 0xF0,
- 0x03, 0xFC, 0x00, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x8F, 0xFF,
- 0xFF, 0xFF, 0xC7, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E,
- 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81,
- 0xE0, 0x78, 0x1F, 0xC7, 0xF0, 0xFC, 0x1F, 0xF0, 0x00, 0xFF, 0x00, 0x0F,
- 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00,
- 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00,
- 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0,
- 0x00, 0xFF, 0x00, 0x1F, 0xF0, 0x01, 0xFF, 0x00, 0x3F, 0xF8, 0x07, 0xFF,
- 0xE0, 0xFF, 0x7F, 0xFF, 0x77, 0xFF, 0xE7, 0x1F, 0xFC, 0x70, 0x7E, 0x00,
- 0x78, 0x00, 0x3E, 0xF0, 0x00, 0x79, 0xF0, 0x00, 0xF1, 0xE0, 0x03, 0xE3,
- 0xC0, 0x07, 0x87, 0xC0, 0x0F, 0x07, 0x80, 0x3C, 0x0F, 0x00, 0x78, 0x1F,
- 0x01, 0xF0, 0x1E, 0x03, 0xC0, 0x3C, 0x07, 0x80, 0x7C, 0x1F, 0x00, 0x78,
- 0x3C, 0x00, 0xF0, 0x78, 0x01, 0xF1, 0xE0, 0x01, 0xE3, 0xC0, 0x03, 0xC7,
- 0x80, 0x03, 0xDE, 0x00, 0x07, 0xBC, 0x00, 0x0F, 0x70, 0x00, 0x0F, 0xE0,
- 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00,
- 0xF8, 0x03, 0xE0, 0x07, 0x9E, 0x00, 0xFC, 0x01, 0xE7, 0x80, 0x3F, 0x00,
- 0x79, 0xF0, 0x0F, 0xC0, 0x3E, 0x3C, 0x07, 0xF0, 0x0F, 0x0F, 0x01, 0xFE,
- 0x03, 0xC3, 0xC0, 0x7F, 0x80, 0xF0, 0x78, 0x1D, 0xE0, 0x78, 0x1E, 0x0F,
- 0x38, 0x1E, 0x07, 0x83, 0xCF, 0x07, 0x81, 0xE0, 0xF3, 0xC1, 0xE0, 0x3C,
- 0x38, 0xF0, 0xF0, 0x0F, 0x1E, 0x1C, 0x3C, 0x03, 0xC7, 0x87, 0x8F, 0x00,
- 0x71, 0xE1, 0xE3, 0x80, 0x1E, 0x70, 0x79, 0xE0, 0x07, 0xBC, 0x0E, 0x78,
- 0x01, 0xEF, 0x03, 0xDE, 0x00, 0x3B, 0xC0, 0xF7, 0x00, 0x0F, 0xE0, 0x3F,
- 0xC0, 0x03, 0xF8, 0x07, 0xF0, 0x00, 0x7E, 0x01, 0xF8, 0x00, 0x1F, 0x80,
- 0x7E, 0x00, 0x07, 0xC0, 0x1F, 0x80, 0x01, 0xF0, 0x03, 0xC0, 0x00, 0x7C,
- 0x00, 0x78, 0xF0, 0x03, 0xE1, 0xE0, 0x0F, 0x07, 0xC0, 0x78, 0x0F, 0x03,
- 0xE0, 0x1E, 0x0F, 0x00, 0x7C, 0x78, 0x00, 0xF3, 0xE0, 0x01, 0xEF, 0x00,
- 0x07, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x03,
- 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x7F, 0xC0, 0x03, 0xCF, 0x00, 0x0F, 0x1E,
- 0x00, 0x78, 0x7C, 0x03, 0xE0, 0xF0, 0x0F, 0x03, 0xE0, 0x78, 0x07, 0xC3,
- 0xE0, 0x0F, 0x1F, 0x00, 0x3E, 0x78, 0x00, 0x7C, 0x78, 0x00, 0x3D, 0xE0,
- 0x01, 0xF7, 0x80, 0x07, 0x8F, 0x00, 0x1E, 0x3C, 0x00, 0xF0, 0xF0, 0x03,
- 0xC1, 0xE0, 0x0F, 0x07, 0x80, 0x78, 0x1E, 0x01, 0xE0, 0x3C, 0x07, 0x80,
- 0xF0, 0x3C, 0x03, 0xC0, 0xF0, 0x07, 0x87, 0xC0, 0x1E, 0x1E, 0x00, 0x78,
- 0x78, 0x00, 0xF3, 0xC0, 0x03, 0xCF, 0x00, 0x0F, 0x3C, 0x00, 0x1F, 0xE0,
- 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00,
- 0x3E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x3C,
- 0x00, 0x01, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x3E, 0x00, 0x0F, 0xF0, 0x00,
- 0x3F, 0xC0, 0x00, 0xFE, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x7F, 0xFF, 0xF7,
- 0xFF, 0xFF, 0x7F, 0xFF, 0xF7, 0xFF, 0xFF, 0x00, 0x01, 0xE0, 0x00, 0x3E,
- 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C,
- 0x00, 0x07, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C,
- 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xC0, 0x00, 0x7C,
- 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,
- 0x01, 0xE0, 0xFC, 0x1F, 0x87, 0x80, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E,
- 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01,
- 0xC0, 0x78, 0x1E, 0x0F, 0x81, 0xE0, 0x3C, 0x07, 0xC0, 0x3C, 0x03, 0x80,
- 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38,
- 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0F, 0x00, 0xFC, 0x1F, 0x80,
- 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x1F, 0x83, 0xF0, 0x0F, 0x00,
- 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0,
- 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x1C, 0x03, 0xC0, 0x3E, 0x03,
- 0xC0, 0x78, 0x1F, 0x07, 0x80, 0xE0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03,
- 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80,
- 0x70, 0x1E, 0x1F, 0x83, 0xF0, 0x78, 0x00, 0x3E, 0x00, 0x0F, 0xF0, 0x0D,
- 0xFF, 0x01, 0xF0, 0xF8, 0x7C, 0x0F, 0xFD, 0x80, 0x7F, 0x80, 0x03, 0xE0 };
-
-const GFXglyph FreeSans24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 12, 0, 1 }, // 0x20 ' '
- { 0, 4, 34, 16, 6, -33 }, // 0x21 '!'
- { 17, 11, 12, 16, 2, -32 }, // 0x22 '"'
- { 34, 24, 33, 26, 1, -31 }, // 0x23 '#'
- { 133, 23, 41, 26, 1, -34 }, // 0x24 '$'
- { 251, 39, 34, 42, 1, -32 }, // 0x25 '%'
- { 417, 28, 34, 31, 2, -32 }, // 0x26 '&'
- { 536, 4, 12, 9, 2, -32 }, // 0x27 '''
- { 542, 10, 44, 16, 3, -33 }, // 0x28 '('
- { 597, 10, 44, 16, 2, -33 }, // 0x29 ')'
- { 652, 14, 14, 18, 2, -33 }, // 0x2A '*'
- { 677, 23, 22, 27, 2, -21 }, // 0x2B '+'
- { 741, 4, 12, 13, 4, -4 }, // 0x2C ','
- { 747, 11, 4, 16, 2, -14 }, // 0x2D '-'
- { 753, 4, 5, 12, 4, -4 }, // 0x2E '.'
- { 756, 13, 35, 13, 0, -33 }, // 0x2F '/'
- { 813, 22, 34, 26, 2, -32 }, // 0x30 '0'
- { 907, 11, 33, 26, 5, -32 }, // 0x31 '1'
- { 953, 22, 33, 26, 2, -32 }, // 0x32 '2'
- { 1044, 23, 34, 26, 1, -32 }, // 0x33 '3'
- { 1142, 23, 33, 26, 1, -32 }, // 0x34 '4'
- { 1237, 22, 34, 26, 2, -32 }, // 0x35 '5'
- { 1331, 22, 34, 26, 2, -32 }, // 0x36 '6'
- { 1425, 21, 33, 26, 2, -32 }, // 0x37 '7'
- { 1512, 22, 34, 26, 2, -32 }, // 0x38 '8'
- { 1606, 21, 34, 26, 2, -32 }, // 0x39 '9'
- { 1696, 4, 25, 12, 4, -24 }, // 0x3A ':'
- { 1709, 4, 32, 12, 4, -24 }, // 0x3B ';'
- { 1725, 23, 23, 27, 2, -22 }, // 0x3C '<'
- { 1792, 23, 12, 27, 2, -16 }, // 0x3D '='
- { 1827, 23, 23, 27, 2, -22 }, // 0x3E '>'
- { 1894, 20, 35, 26, 4, -34 }, // 0x3F '?'
- { 1982, 43, 42, 48, 2, -34 }, // 0x40 '@'
- { 2208, 30, 34, 31, 1, -33 }, // 0x41 'A'
- { 2336, 25, 34, 31, 4, -33 }, // 0x42 'B'
- { 2443, 29, 36, 33, 2, -34 }, // 0x43 'C'
- { 2574, 27, 34, 33, 4, -33 }, // 0x44 'D'
- { 2689, 24, 34, 30, 4, -33 }, // 0x45 'E'
- { 2791, 22, 34, 28, 4, -33 }, // 0x46 'F'
- { 2885, 31, 36, 36, 2, -34 }, // 0x47 'G'
- { 3025, 26, 34, 34, 4, -33 }, // 0x48 'H'
- { 3136, 4, 34, 13, 5, -33 }, // 0x49 'I'
- { 3153, 19, 35, 25, 2, -33 }, // 0x4A 'J'
- { 3237, 27, 34, 32, 4, -33 }, // 0x4B 'K'
- { 3352, 21, 34, 26, 4, -33 }, // 0x4C 'L'
- { 3442, 32, 34, 40, 4, -33 }, // 0x4D 'M'
- { 3578, 26, 34, 34, 4, -33 }, // 0x4E 'N'
- { 3689, 33, 36, 37, 2, -34 }, // 0x4F 'O'
- { 3838, 24, 34, 31, 4, -33 }, // 0x50 'P'
- { 3940, 33, 38, 37, 2, -34 }, // 0x51 'Q'
- { 4097, 26, 34, 33, 4, -33 }, // 0x52 'R'
- { 4208, 27, 36, 31, 2, -34 }, // 0x53 'S'
- { 4330, 26, 34, 30, 2, -33 }, // 0x54 'T'
- { 4441, 26, 35, 34, 4, -33 }, // 0x55 'U'
- { 4555, 29, 34, 30, 1, -33 }, // 0x56 'V'
- { 4679, 42, 34, 44, 1, -33 }, // 0x57 'W'
- { 4858, 29, 34, 31, 1, -33 }, // 0x58 'X'
- { 4982, 30, 34, 32, 1, -33 }, // 0x59 'Y'
- { 5110, 27, 34, 29, 1, -33 }, // 0x5A 'Z'
- { 5225, 8, 44, 13, 3, -33 }, // 0x5B '['
- { 5269, 13, 35, 13, 0, -33 }, // 0x5C '\'
- { 5326, 8, 44, 13, 1, -33 }, // 0x5D ']'
- { 5370, 18, 18, 22, 2, -32 }, // 0x5E '^'
- { 5411, 28, 2, 26, -1, 7 }, // 0x5F '_'
- { 5418, 10, 7, 12, 1, -34 }, // 0x60 '`'
- { 5427, 24, 27, 26, 1, -25 }, // 0x61 'a'
- { 5508, 22, 35, 26, 3, -33 }, // 0x62 'b'
- { 5605, 21, 27, 24, 1, -25 }, // 0x63 'c'
- { 5676, 23, 35, 26, 1, -33 }, // 0x64 'd'
- { 5777, 22, 27, 25, 1, -25 }, // 0x65 'e'
- { 5852, 10, 34, 13, 1, -33 }, // 0x66 'f'
- { 5895, 22, 36, 26, 1, -25 }, // 0x67 'g'
- { 5994, 19, 34, 25, 3, -33 }, // 0x68 'h'
- { 6075, 4, 34, 10, 3, -33 }, // 0x69 'i'
- { 6092, 8, 44, 11, 0, -33 }, // 0x6A 'j'
- { 6136, 21, 34, 24, 3, -33 }, // 0x6B 'k'
- { 6226, 4, 34, 10, 3, -33 }, // 0x6C 'l'
- { 6243, 32, 26, 38, 3, -25 }, // 0x6D 'm'
- { 6347, 20, 26, 25, 3, -25 }, // 0x6E 'n'
- { 6412, 23, 27, 25, 1, -25 }, // 0x6F 'o'
- { 6490, 22, 35, 26, 3, -25 }, // 0x70 'p'
- { 6587, 23, 35, 26, 1, -25 }, // 0x71 'q'
- { 6688, 12, 26, 16, 3, -25 }, // 0x72 'r'
- { 6727, 20, 27, 23, 1, -25 }, // 0x73 's'
- { 6795, 10, 32, 13, 1, -30 }, // 0x74 't'
- { 6835, 20, 26, 25, 3, -24 }, // 0x75 'u'
- { 6900, 23, 25, 23, 0, -24 }, // 0x76 'v'
- { 6972, 34, 25, 34, 0, -24 }, // 0x77 'w'
- { 7079, 22, 25, 22, 0, -24 }, // 0x78 'x'
- { 7148, 22, 35, 22, 0, -24 }, // 0x79 'y'
- { 7245, 20, 25, 23, 1, -24 }, // 0x7A 'z'
- { 7308, 11, 44, 16, 2, -33 }, // 0x7B '{'
- { 7369, 3, 44, 12, 4, -33 }, // 0x7C '|'
- { 7386, 11, 44, 16, 2, -33 }, // 0x7D '}'
- { 7447, 19, 7, 24, 2, -19 } }; // 0x7E '~'
-
-const GFXfont FreeSans24pt7b PROGMEM = {
- (uint8_t *)FreeSans24pt7bBitmaps,
- (GFXglyph *)FreeSans24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 8136 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans9pt7b.h
deleted file mode 100644
index 1f006a1..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSans9pt7b.h
+++ /dev/null
@@ -1,201 +0,0 @@
-const uint8_t FreeSans9pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xF8, 0xC0, 0xDE, 0xF7, 0x20, 0x09, 0x86, 0x41, 0x91, 0xFF,
- 0x13, 0x04, 0xC3, 0x20, 0xC8, 0xFF, 0x89, 0x82, 0x61, 0x90, 0x10, 0x1F,
- 0x14, 0xDA, 0x3D, 0x1E, 0x83, 0x40, 0x78, 0x17, 0x08, 0xF4, 0x7A, 0x35,
- 0x33, 0xF0, 0x40, 0x20, 0x38, 0x10, 0xEC, 0x20, 0xC6, 0x20, 0xC6, 0x40,
- 0xC6, 0x40, 0x6C, 0x80, 0x39, 0x00, 0x01, 0x3C, 0x02, 0x77, 0x02, 0x63,
- 0x04, 0x63, 0x04, 0x77, 0x08, 0x3C, 0x0E, 0x06, 0x60, 0xCC, 0x19, 0x81,
- 0xE0, 0x18, 0x0F, 0x03, 0x36, 0xC2, 0xD8, 0x73, 0x06, 0x31, 0xE3, 0xC4,
- 0xFE, 0x13, 0x26, 0x6C, 0xCC, 0xCC, 0xC4, 0x66, 0x23, 0x10, 0x8C, 0x46,
- 0x63, 0x33, 0x33, 0x32, 0x66, 0x4C, 0x80, 0x25, 0x7E, 0xA5, 0x00, 0x30,
- 0xC3, 0x3F, 0x30, 0xC3, 0x0C, 0xD6, 0xF0, 0xC0, 0x08, 0x44, 0x21, 0x10,
- 0x84, 0x42, 0x11, 0x08, 0x00, 0x3C, 0x66, 0x42, 0xC3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0xC3, 0xC3, 0x42, 0x66, 0x3C, 0x11, 0x3F, 0x33, 0x33, 0x33, 0x33,
- 0x30, 0x3E, 0x31, 0xB0, 0x78, 0x30, 0x18, 0x1C, 0x1C, 0x1C, 0x18, 0x18,
- 0x10, 0x08, 0x07, 0xF8, 0x3C, 0x66, 0xC3, 0xC3, 0x03, 0x06, 0x1C, 0x07,
- 0x03, 0xC3, 0xC3, 0x66, 0x3C, 0x0C, 0x18, 0x71, 0x62, 0xC9, 0xA3, 0x46,
- 0xFE, 0x18, 0x30, 0x60, 0xC0, 0x7F, 0x20, 0x10, 0x08, 0x08, 0x07, 0xF3,
- 0x8C, 0x03, 0x01, 0x80, 0xF0, 0x6C, 0x63, 0xE0, 0x1E, 0x31, 0x98, 0x78,
- 0x0C, 0x06, 0xF3, 0x8D, 0x83, 0xC1, 0xE0, 0xD0, 0x6C, 0x63, 0xE0, 0xFF,
- 0x03, 0x02, 0x06, 0x04, 0x0C, 0x08, 0x18, 0x18, 0x18, 0x10, 0x30, 0x30,
- 0x3E, 0x31, 0xB0, 0x78, 0x3C, 0x1B, 0x18, 0xF8, 0xC6, 0xC1, 0xE0, 0xF0,
- 0x6C, 0x63, 0xE0, 0x3C, 0x66, 0xC2, 0xC3, 0xC3, 0xC3, 0x67, 0x3B, 0x03,
- 0x03, 0xC2, 0x66, 0x3C, 0xC0, 0x00, 0x30, 0xC0, 0x00, 0x00, 0x64, 0xA0,
- 0x00, 0x81, 0xC7, 0x8E, 0x0C, 0x07, 0x80, 0x70, 0x0E, 0x01, 0x80, 0xFF,
- 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x70, 0x0E, 0x01, 0xC0, 0x18, 0x38, 0x71,
- 0xC0, 0x80, 0x00, 0x3E, 0x31, 0xB0, 0x78, 0x30, 0x18, 0x18, 0x38, 0x18,
- 0x18, 0x0C, 0x00, 0x00, 0x01, 0x80, 0x03, 0xF0, 0x06, 0x0E, 0x06, 0x01,
- 0x86, 0x00, 0x66, 0x1D, 0xBB, 0x31, 0xCF, 0x18, 0xC7, 0x98, 0x63, 0xCC,
- 0x31, 0xE6, 0x11, 0xB3, 0x99, 0xCC, 0xF7, 0x86, 0x00, 0x01, 0x80, 0x00,
- 0x70, 0x40, 0x0F, 0xE0, 0x06, 0x00, 0xF0, 0x0F, 0x00, 0x90, 0x19, 0x81,
- 0x98, 0x10, 0x83, 0x0C, 0x3F, 0xC2, 0x04, 0x60, 0x66, 0x06, 0xC0, 0x30,
- 0xFF, 0x18, 0x33, 0x03, 0x60, 0x6C, 0x0D, 0x83, 0x3F, 0xC6, 0x06, 0xC0,
- 0x78, 0x0F, 0x01, 0xE0, 0x6F, 0xF8, 0x1F, 0x86, 0x19, 0x81, 0xA0, 0x3C,
- 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x68, 0x0D, 0x83, 0x18, 0x61, 0xF0,
- 0xFF, 0x18, 0x33, 0x03, 0x60, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0,
- 0x78, 0x0F, 0x03, 0x60, 0xCF, 0xF0, 0xFF, 0xE0, 0x30, 0x18, 0x0C, 0x06,
- 0x03, 0xFD, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0F, 0xF8, 0xFF, 0xC0, 0xC0,
- 0xC0, 0xC0, 0xC0, 0xFE, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x0F, 0x83,
- 0x0E, 0x60, 0x66, 0x03, 0xC0, 0x0C, 0x00, 0xC1, 0xFC, 0x03, 0xC0, 0x36,
- 0x03, 0x60, 0x73, 0x0F, 0x0F, 0x10, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C,
- 0x07, 0x80, 0xFF, 0xFE, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x06,
- 0xFF, 0xFF, 0xFF, 0xC0, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x07,
- 0x8F, 0x1E, 0x27, 0x80, 0xC0, 0xD8, 0x33, 0x0C, 0x63, 0x0C, 0xC1, 0xB8,
- 0x3F, 0x07, 0x30, 0xC3, 0x18, 0x63, 0x06, 0x60, 0x6C, 0x0C, 0xC0, 0xC0,
- 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFF, 0xE0,
- 0x3F, 0x01, 0xFC, 0x1F, 0xE0, 0xFD, 0x05, 0xEC, 0x6F, 0x63, 0x79, 0x13,
- 0xCD, 0x9E, 0x6C, 0xF1, 0x47, 0x8E, 0x3C, 0x71, 0x80, 0xE0, 0x7C, 0x0F,
- 0xC1, 0xE8, 0x3D, 0x87, 0x98, 0xF1, 0x1E, 0x33, 0xC3, 0x78, 0x6F, 0x07,
- 0xE0, 0x7C, 0x0E, 0x0F, 0x81, 0x83, 0x18, 0x0C, 0xC0, 0x6C, 0x01, 0xE0,
- 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1B, 0x01, 0x98, 0x0C, 0x60, 0xC0, 0xF8,
- 0x00, 0xFF, 0x30, 0x6C, 0x0F, 0x03, 0xC0, 0xF0, 0x6F, 0xF3, 0x00, 0xC0,
- 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x00, 0x0F, 0x81, 0x83, 0x18, 0x0C, 0xC0,
- 0x6C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1B, 0x01, 0x98, 0x6C,
- 0x60, 0xC0, 0xFB, 0x00, 0x08, 0xFF, 0x8C, 0x0E, 0xC0, 0x6C, 0x06, 0xC0,
- 0x6C, 0x0C, 0xFF, 0x8C, 0x0E, 0xC0, 0x6C, 0x06, 0xC0, 0x6C, 0x06, 0xC0,
- 0x70, 0x3F, 0x18, 0x6C, 0x0F, 0x03, 0xC0, 0x1E, 0x01, 0xF0, 0x0E, 0x00,
- 0xF0, 0x3C, 0x0D, 0x86, 0x3F, 0x00, 0xFF, 0x86, 0x03, 0x01, 0x80, 0xC0,
- 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x78, 0x0F,
- 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01,
- 0xB0, 0x61, 0xF0, 0xC0, 0x6C, 0x0D, 0x81, 0x10, 0x63, 0x0C, 0x61, 0x04,
- 0x60, 0xCC, 0x19, 0x01, 0x60, 0x3C, 0x07, 0x00, 0x60, 0xC1, 0x81, 0x30,
- 0xE1, 0x98, 0x70, 0xCC, 0x28, 0x66, 0x26, 0x21, 0x13, 0x30, 0xC8, 0x98,
- 0x6C, 0x4C, 0x14, 0x34, 0x0A, 0x1A, 0x07, 0x07, 0x03, 0x03, 0x80, 0x81,
- 0x80, 0x60, 0x63, 0x0C, 0x30, 0xC1, 0x98, 0x0F, 0x00, 0xE0, 0x06, 0x00,
- 0xF0, 0x19, 0x01, 0x98, 0x30, 0xC6, 0x0E, 0x60, 0x60, 0xC0, 0x36, 0x06,
- 0x30, 0xC3, 0x0C, 0x19, 0x81, 0xD8, 0x0F, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x06, 0x00, 0xFF, 0xC0, 0x60, 0x30, 0x0C, 0x06, 0x03,
- 0x01, 0xC0, 0x60, 0x30, 0x18, 0x06, 0x03, 0x00, 0xFF, 0xC0, 0xFB, 0x6D,
- 0xB6, 0xDB, 0x6D, 0xB6, 0xE0, 0x84, 0x10, 0x84, 0x10, 0x84, 0x10, 0x84,
- 0x10, 0x80, 0xED, 0xB6, 0xDB, 0x6D, 0xB6, 0xDB, 0xE0, 0x30, 0x60, 0xA2,
- 0x44, 0xD8, 0xA1, 0x80, 0xFF, 0xC0, 0xC6, 0x30, 0x7E, 0x71, 0xB0, 0xC0,
- 0x60, 0xF3, 0xDB, 0x0D, 0x86, 0xC7, 0x3D, 0xC0, 0xC0, 0x60, 0x30, 0x1B,
- 0xCE, 0x36, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x7C, 0x6D, 0xE0, 0x3C,
- 0x66, 0xC3, 0xC0, 0xC0, 0xC0, 0xC0, 0xC3, 0x66, 0x3C, 0x03, 0x03, 0x03,
- 0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x67, 0x3B, 0x3C, 0x66,
- 0xC3, 0xC3, 0xFF, 0xC0, 0xC0, 0xC3, 0x66, 0x3C, 0x36, 0x6F, 0x66, 0x66,
- 0x66, 0x66, 0x60, 0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x67,
- 0x3B, 0x03, 0x03, 0xC6, 0x7C, 0xC0, 0xC0, 0xC0, 0xDE, 0xE3, 0xC3, 0xC3,
- 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xFF, 0xFF, 0xC0, 0x30, 0x03,
- 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xE0, 0xC0, 0x60, 0x30, 0x18, 0x4C,
- 0x46, 0x63, 0x61, 0xF0, 0xEC, 0x62, 0x31, 0x98, 0x6C, 0x30, 0xFF, 0xFF,
- 0xFF, 0xC0, 0xDE, 0xF7, 0x1C, 0xF0, 0xC7, 0x86, 0x3C, 0x31, 0xE1, 0x8F,
- 0x0C, 0x78, 0x63, 0xC3, 0x1E, 0x18, 0xC0, 0xDE, 0xE3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x3C, 0x66, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0x66, 0x3C, 0xDE, 0x71, 0xB0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83,
- 0xE3, 0x6F, 0x30, 0x18, 0x0C, 0x00, 0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0xC3, 0x67, 0x3B, 0x03, 0x03, 0x03, 0xDF, 0x31, 0x8C, 0x63, 0x18,
- 0xC6, 0x00, 0x3E, 0xE3, 0xC0, 0xC0, 0xE0, 0x3C, 0x07, 0xC3, 0xE3, 0x7E,
- 0x66, 0xF6, 0x66, 0x66, 0x66, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
- 0xC3, 0xC3, 0xC7, 0x7B, 0xC1, 0xA0, 0x98, 0xCC, 0x42, 0x21, 0xB0, 0xD0,
- 0x28, 0x1C, 0x0C, 0x00, 0xC6, 0x1E, 0x38, 0x91, 0xC4, 0xCA, 0x66, 0xD3,
- 0x16, 0xD0, 0xA6, 0x87, 0x1C, 0x38, 0xC0, 0xC6, 0x00, 0x43, 0x62, 0x36,
- 0x1C, 0x18, 0x1C, 0x3C, 0x26, 0x62, 0x43, 0xC1, 0x21, 0x98, 0xCC, 0x42,
- 0x61, 0xB0, 0xD0, 0x38, 0x1C, 0x0C, 0x06, 0x03, 0x01, 0x03, 0x00, 0xFE,
- 0x0C, 0x30, 0xC1, 0x86, 0x18, 0x20, 0xC1, 0xFC, 0x36, 0x66, 0x66, 0x6E,
- 0xCE, 0x66, 0x66, 0x66, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xC6, 0x66,
- 0x66, 0x67, 0x37, 0x66, 0x66, 0x66, 0xC0, 0x61, 0x24, 0x38 };
-
-const GFXglyph FreeSans9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 2, 13, 6, 2, -12 }, // 0x21 '!'
- { 4, 5, 4, 6, 1, -12 }, // 0x22 '"'
- { 7, 10, 12, 10, 0, -11 }, // 0x23 '#'
- { 22, 9, 16, 10, 1, -13 }, // 0x24 '$'
- { 40, 16, 13, 16, 1, -12 }, // 0x25 '%'
- { 66, 11, 13, 12, 1, -12 }, // 0x26 '&'
- { 84, 2, 4, 4, 1, -12 }, // 0x27 '''
- { 85, 4, 17, 6, 1, -12 }, // 0x28 '('
- { 94, 4, 17, 6, 1, -12 }, // 0x29 ')'
- { 103, 5, 5, 7, 1, -12 }, // 0x2A '*'
- { 107, 6, 8, 11, 3, -7 }, // 0x2B '+'
- { 113, 2, 4, 5, 2, 0 }, // 0x2C ','
- { 114, 4, 1, 6, 1, -4 }, // 0x2D '-'
- { 115, 2, 1, 5, 1, 0 }, // 0x2E '.'
- { 116, 5, 13, 5, 0, -12 }, // 0x2F '/'
- { 125, 8, 13, 10, 1, -12 }, // 0x30 '0'
- { 138, 4, 13, 10, 3, -12 }, // 0x31 '1'
- { 145, 9, 13, 10, 1, -12 }, // 0x32 '2'
- { 160, 8, 13, 10, 1, -12 }, // 0x33 '3'
- { 173, 7, 13, 10, 2, -12 }, // 0x34 '4'
- { 185, 9, 13, 10, 1, -12 }, // 0x35 '5'
- { 200, 9, 13, 10, 1, -12 }, // 0x36 '6'
- { 215, 8, 13, 10, 0, -12 }, // 0x37 '7'
- { 228, 9, 13, 10, 1, -12 }, // 0x38 '8'
- { 243, 8, 13, 10, 1, -12 }, // 0x39 '9'
- { 256, 2, 10, 5, 1, -9 }, // 0x3A ':'
- { 259, 3, 12, 5, 1, -8 }, // 0x3B ';'
- { 264, 9, 9, 11, 1, -8 }, // 0x3C '<'
- { 275, 9, 4, 11, 1, -5 }, // 0x3D '='
- { 280, 9, 9, 11, 1, -8 }, // 0x3E '>'
- { 291, 9, 13, 10, 1, -12 }, // 0x3F '?'
- { 306, 17, 16, 18, 1, -12 }, // 0x40 '@'
- { 340, 12, 13, 12, 0, -12 }, // 0x41 'A'
- { 360, 11, 13, 12, 1, -12 }, // 0x42 'B'
- { 378, 11, 13, 13, 1, -12 }, // 0x43 'C'
- { 396, 11, 13, 13, 1, -12 }, // 0x44 'D'
- { 414, 9, 13, 11, 1, -12 }, // 0x45 'E'
- { 429, 8, 13, 11, 1, -12 }, // 0x46 'F'
- { 442, 12, 13, 14, 1, -12 }, // 0x47 'G'
- { 462, 11, 13, 13, 1, -12 }, // 0x48 'H'
- { 480, 2, 13, 5, 2, -12 }, // 0x49 'I'
- { 484, 7, 13, 10, 1, -12 }, // 0x4A 'J'
- { 496, 11, 13, 12, 1, -12 }, // 0x4B 'K'
- { 514, 8, 13, 10, 1, -12 }, // 0x4C 'L'
- { 527, 13, 13, 15, 1, -12 }, // 0x4D 'M'
- { 549, 11, 13, 13, 1, -12 }, // 0x4E 'N'
- { 567, 13, 13, 14, 1, -12 }, // 0x4F 'O'
- { 589, 10, 13, 12, 1, -12 }, // 0x50 'P'
- { 606, 13, 14, 14, 1, -12 }, // 0x51 'Q'
- { 629, 12, 13, 13, 1, -12 }, // 0x52 'R'
- { 649, 10, 13, 12, 1, -12 }, // 0x53 'S'
- { 666, 9, 13, 11, 1, -12 }, // 0x54 'T'
- { 681, 11, 13, 13, 1, -12 }, // 0x55 'U'
- { 699, 11, 13, 12, 0, -12 }, // 0x56 'V'
- { 717, 17, 13, 17, 0, -12 }, // 0x57 'W'
- { 745, 12, 13, 12, 0, -12 }, // 0x58 'X'
- { 765, 12, 13, 12, 0, -12 }, // 0x59 'Y'
- { 785, 10, 13, 11, 1, -12 }, // 0x5A 'Z'
- { 802, 3, 17, 5, 1, -12 }, // 0x5B '['
- { 809, 5, 13, 5, 0, -12 }, // 0x5C '\'
- { 818, 3, 17, 5, 0, -12 }, // 0x5D ']'
- { 825, 7, 7, 8, 1, -12 }, // 0x5E '^'
- { 832, 10, 1, 10, 0, 3 }, // 0x5F '_'
- { 834, 4, 3, 5, 0, -12 }, // 0x60 '`'
- { 836, 9, 10, 10, 1, -9 }, // 0x61 'a'
- { 848, 9, 13, 10, 1, -12 }, // 0x62 'b'
- { 863, 8, 10, 9, 1, -9 }, // 0x63 'c'
- { 873, 8, 13, 10, 1, -12 }, // 0x64 'd'
- { 886, 8, 10, 10, 1, -9 }, // 0x65 'e'
- { 896, 4, 13, 5, 1, -12 }, // 0x66 'f'
- { 903, 8, 14, 10, 1, -9 }, // 0x67 'g'
- { 917, 8, 13, 10, 1, -12 }, // 0x68 'h'
- { 930, 2, 13, 4, 1, -12 }, // 0x69 'i'
- { 934, 4, 17, 4, 0, -12 }, // 0x6A 'j'
- { 943, 9, 13, 9, 1, -12 }, // 0x6B 'k'
- { 958, 2, 13, 4, 1, -12 }, // 0x6C 'l'
- { 962, 13, 10, 15, 1, -9 }, // 0x6D 'm'
- { 979, 8, 10, 10, 1, -9 }, // 0x6E 'n'
- { 989, 8, 10, 10, 1, -9 }, // 0x6F 'o'
- { 999, 9, 13, 10, 1, -9 }, // 0x70 'p'
- { 1014, 8, 13, 10, 1, -9 }, // 0x71 'q'
- { 1027, 5, 10, 6, 1, -9 }, // 0x72 'r'
- { 1034, 8, 10, 9, 1, -9 }, // 0x73 's'
- { 1044, 4, 12, 5, 1, -11 }, // 0x74 't'
- { 1050, 8, 10, 10, 1, -9 }, // 0x75 'u'
- { 1060, 9, 10, 9, 0, -9 }, // 0x76 'v'
- { 1072, 13, 10, 13, 0, -9 }, // 0x77 'w'
- { 1089, 8, 10, 9, 0, -9 }, // 0x78 'x'
- { 1099, 9, 14, 9, 0, -9 }, // 0x79 'y'
- { 1115, 7, 10, 9, 1, -9 }, // 0x7A 'z'
- { 1124, 4, 17, 6, 1, -12 }, // 0x7B '{'
- { 1133, 2, 17, 4, 2, -12 }, // 0x7C '|'
- { 1138, 4, 17, 6, 1, -12 }, // 0x7D '}'
- { 1147, 7, 3, 9, 1, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSans9pt7b PROGMEM = {
- (uint8_t *)FreeSans9pt7bBitmaps,
- (GFXglyph *)FreeSans9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1822 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold12pt7b.h
deleted file mode 100644
index e0922be..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold12pt7b.h
+++ /dev/null
@@ -1,288 +0,0 @@
-const uint8_t FreeSansBold12pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x60, 0xFF, 0xF0, 0xF3, 0xFC, 0xFF,
- 0x3F, 0xCF, 0x61, 0x98, 0x60, 0x0E, 0x70, 0x73, 0x83, 0x18, 0xFF, 0xF7,
- 0xFF, 0xBF, 0xFC, 0x73, 0x83, 0x18, 0x18, 0xC7, 0xFF, 0xBF, 0xFD, 0xFF,
- 0xE3, 0x18, 0x39, 0xC1, 0xCE, 0x0E, 0x70, 0x02, 0x00, 0x7E, 0x0F, 0xF8,
- 0x7F, 0xE7, 0xAF, 0xB9, 0x3D, 0xC8, 0x0F, 0x40, 0x3F, 0x00, 0xFF, 0x00,
- 0xFC, 0x05, 0xFF, 0x27, 0xF9, 0x3F, 0xEB, 0xEF, 0xFE, 0x3F, 0xE0, 0x7C,
- 0x00, 0x80, 0x04, 0x00, 0x3C, 0x06, 0x0F, 0xC1, 0x81, 0xFC, 0x30, 0x73,
- 0x8C, 0x0C, 0x31, 0x81, 0xCE, 0x60, 0x1F, 0xCC, 0x03, 0xF3, 0x00, 0x3C,
- 0x67, 0x80, 0x19, 0xF8, 0x02, 0x7F, 0x80, 0xCE, 0x70, 0x11, 0x86, 0x06,
- 0x39, 0xC1, 0x87, 0xF8, 0x30, 0x7E, 0x0C, 0x07, 0x80, 0x07, 0x80, 0x1F,
- 0xC0, 0x3F, 0xE0, 0x3C, 0xE0, 0x3C, 0xE0, 0x3E, 0xE0, 0x0F, 0xC0, 0x07,
- 0x00, 0x3F, 0x8C, 0x7F, 0xCC, 0xF1, 0xFC, 0xF0, 0xF8, 0xF0, 0x78, 0xF8,
- 0xF8, 0x7F, 0xFC, 0x3F, 0xDE, 0x1F, 0x8E, 0xFF, 0xFF, 0x66, 0x0C, 0x73,
- 0x8E, 0x71, 0xC7, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x8E, 0x1C, 0x71, 0xC3,
- 0x8E, 0x18, 0x70, 0xC3, 0x87, 0x1C, 0x38, 0xE3, 0x87, 0x1C, 0x71, 0xC7,
- 0x1C, 0x71, 0xCE, 0x38, 0xE7, 0x1C, 0x63, 0x80, 0x10, 0x23, 0x5F, 0xF3,
- 0x87, 0x1B, 0x14, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x0F, 0xFF, 0xFF, 0xFF,
- 0xF8, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x00, 0xFF, 0xF3, 0x36, 0xC0, 0xFF,
- 0xFF, 0xC0, 0xFF, 0xF0, 0x0C, 0x30, 0x86, 0x18, 0x61, 0x0C, 0x30, 0xC2,
- 0x18, 0x61, 0x84, 0x30, 0xC0, 0x1F, 0x83, 0xFC, 0x7F, 0xE7, 0x9E, 0xF0,
- 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0,
- 0xF7, 0x9E, 0x7F, 0xE3, 0xFC, 0x0F, 0x00, 0x06, 0x1C, 0x7F, 0xFF, 0xE3,
- 0xC7, 0x8F, 0x1E, 0x3C, 0x78, 0xF1, 0xE3, 0xC7, 0x8F, 0x1E, 0x1F, 0x83,
- 0xFC, 0x7F, 0xEF, 0x9F, 0xF0, 0xFF, 0x0F, 0x00, 0xF0, 0x0F, 0x01, 0xE0,
- 0x3C, 0x0F, 0x81, 0xE0, 0x3C, 0x03, 0x80, 0x7F, 0xF7, 0xFF, 0x7F, 0xF0,
- 0x1F, 0x07, 0xFC, 0xFF, 0xEF, 0x1E, 0xF1, 0xE0, 0x1E, 0x03, 0xC0, 0x78,
- 0x07, 0xC0, 0x1E, 0x00, 0xF0, 0x0F, 0xF0, 0xFF, 0x1F, 0x7F, 0xE7, 0xFC,
- 0x1F, 0x80, 0x03, 0xC0, 0xF8, 0x1F, 0x07, 0xE1, 0xBC, 0x27, 0x8C, 0xF3,
- 0x1E, 0x63, 0xD8, 0x7B, 0xFF, 0xFF, 0xFF, 0xFE, 0x07, 0x80, 0xF0, 0x1E,
- 0x03, 0xC0, 0x3F, 0xE7, 0xFE, 0x7F, 0xE7, 0x00, 0x60, 0x06, 0xF8, 0x7F,
- 0xCF, 0xFE, 0xF1, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xFE, 0x1E, 0xFF,
- 0xE7, 0xFC, 0x3F, 0x00, 0x0F, 0x83, 0xFC, 0x7F, 0xE7, 0x9F, 0xF0, 0x0F,
- 0x78, 0xFF, 0xCF, 0xFE, 0xF9, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xF7,
- 0x9F, 0x7F, 0xE3, 0xFC, 0x0F, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0xE0,
- 0x1C, 0x07, 0x01, 0xE0, 0x38, 0x0F, 0x01, 0xC0, 0x78, 0x0F, 0x01, 0xE0,
- 0x38, 0x0F, 0x01, 0xE0, 0x3C, 0x00, 0x0F, 0x03, 0xFC, 0x7F, 0xC7, 0x9E,
- 0x70, 0xE7, 0x0E, 0x39, 0xC1, 0xF8, 0x3F, 0xC7, 0x9E, 0xF0, 0xFF, 0x0F,
- 0xF0, 0xFF, 0x9F, 0x7F, 0xE3, 0xFC, 0x1F, 0x80, 0x1F, 0x03, 0xFC, 0x7F,
- 0xEF, 0x9E, 0xF0, 0xEF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF9, 0xF7, 0xFF, 0x3F,
- 0xF1, 0xEF, 0x00, 0xEF, 0x1E, 0x7F, 0xE7, 0xFC, 0x1F, 0x00, 0xFF, 0xF0,
- 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xFF, 0x11, 0x6C,
- 0x00, 0x10, 0x07, 0x03, 0xF1, 0xFC, 0x7E, 0x0F, 0x80, 0xE0, 0x0F, 0xC0,
- 0x3F, 0x80, 0x7F, 0x00, 0xF0, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00,
- 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x0E, 0x00, 0xFC,
- 0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0x00, 0xF0, 0x7F, 0x1F, 0x8F, 0xE0, 0xF0,
- 0x08, 0x00, 0x1F, 0x07, 0xFC, 0x7F, 0xEF, 0x9F, 0xF0, 0xFF, 0x0F, 0x00,
- 0xF0, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x0E, 0x00, 0xE0, 0x00,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x00, 0xFE, 0x00, 0x1F, 0xFC, 0x03, 0xC0,
- 0xF0, 0x38, 0x01, 0xC3, 0x80, 0x07, 0x18, 0x3D, 0x99, 0x87, 0xEC, 0x6C,
- 0x71, 0xC3, 0xC3, 0x06, 0x1E, 0x18, 0x30, 0xF1, 0x81, 0x87, 0x8C, 0x18,
- 0x7C, 0x60, 0xC3, 0x63, 0x8E, 0x3B, 0x8F, 0xDF, 0x8C, 0x3C, 0xF0, 0x70,
- 0x00, 0x01, 0xC0, 0x00, 0x07, 0x80, 0x80, 0x1F, 0xFE, 0x00, 0x1F, 0xC0,
- 0x00, 0x03, 0xE0, 0x03, 0xE0, 0x03, 0xE0, 0x07, 0xF0, 0x07, 0xF0, 0x07,
- 0x70, 0x0F, 0x78, 0x0E, 0x78, 0x0E, 0x38, 0x1E, 0x3C, 0x1C, 0x3C, 0x3F,
- 0xFC, 0x3F, 0xFE, 0x3F, 0xFE, 0x78, 0x0E, 0x78, 0x0F, 0x70, 0x0F, 0xF0,
- 0x07, 0xFF, 0xC3, 0xFF, 0xCF, 0xFF, 0x3C, 0x3E, 0xF0, 0x7B, 0xC1, 0xEF,
- 0x0F, 0xBF, 0xFC, 0xFF, 0xE3, 0xFF, 0xCF, 0x07, 0xBC, 0x0F, 0xF0, 0x3F,
- 0xC0, 0xFF, 0x07, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0x80, 0x07, 0xE0, 0x1F,
- 0xF8, 0x3F, 0xFC, 0x7C, 0x3E, 0x78, 0x1F, 0xF8, 0x0F, 0xF0, 0x00, 0xF0,
- 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF8, 0x0F, 0x78,
- 0x1F, 0x7C, 0x3E, 0x3F, 0xFE, 0x1F, 0xFC, 0x07, 0xF0, 0xFF, 0xE1, 0xFF,
- 0xE3, 0xFF, 0xE7, 0x83, 0xEF, 0x03, 0xDE, 0x07, 0xFC, 0x07, 0xF8, 0x0F,
- 0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x80, 0xFF, 0x03, 0xFE, 0x07, 0xBC,
- 0x1F, 0x7F, 0xFC, 0xFF, 0xF1, 0xFF, 0x80, 0xFF, 0xF7, 0xFF, 0xBF, 0xFD,
- 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1F, 0xFC, 0xFF, 0xE7, 0xFF, 0x3C,
- 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0xFE, 0xFF, 0xEF, 0xFE, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0x03, 0xF0, 0x0F, 0xFC, 0x3F, 0xFE, 0x3E, 0x1F,
- 0x78, 0x07, 0x78, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x7F, 0xF0, 0x7F,
- 0xF0, 0x7F, 0xF0, 0x07, 0x78, 0x07, 0x7C, 0x0F, 0x3E, 0x1F, 0x3F, 0xFB,
- 0x0F, 0xFB, 0x03, 0xE3, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0,
- 0x3F, 0xC0, 0xFF, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xFC,
- 0x0F, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xF0,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0x3C,
- 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07,
- 0xF8, 0xFF, 0x1F, 0xE3, 0xFC, 0x7B, 0xFE, 0x7F, 0xC3, 0xE0, 0xF0, 0x3E,
- 0xF0, 0x3C, 0xF0, 0x78, 0xF0, 0xF0, 0xF1, 0xE0, 0xF3, 0xC0, 0xF7, 0x80,
- 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x80, 0xFB, 0xC0, 0xF1, 0xE0, 0xF0, 0xF0,
- 0xF0, 0xF0, 0xF0, 0x78, 0xF0, 0x3C, 0xF0, 0x3E, 0xF0, 0x1E, 0xF0, 0x1E,
- 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03,
- 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0xFF, 0xFF, 0xFF, 0xFC, 0xF8,
- 0x1F, 0xFE, 0x0F, 0xFF, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0xFF, 0xE1, 0xFF,
- 0xF9, 0xFF, 0xFC, 0xEF, 0xFE, 0x77, 0xFB, 0x3B, 0xFD, 0xDD, 0xFE, 0xFC,
- 0xFF, 0x7E, 0x7F, 0x9F, 0x3F, 0xCF, 0x9F, 0xE7, 0x8F, 0xF3, 0xC7, 0xF8,
- 0xE3, 0xC0, 0xF0, 0x1F, 0xF0, 0x3F, 0xF0, 0x7F, 0xE0, 0xFF, 0xE1, 0xFF,
- 0xC3, 0xFD, 0xC7, 0xFB, 0x8F, 0xF3, 0x9F, 0xE7, 0x3F, 0xC7, 0x7F, 0x8F,
- 0xFF, 0x0F, 0xFE, 0x1F, 0xFC, 0x1F, 0xF8, 0x1F, 0xF0, 0x3F, 0xE0, 0x3C,
- 0x03, 0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x87, 0xC7, 0xC7, 0x80, 0xF3, 0xC0,
- 0x7B, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x01, 0xFE,
- 0x00, 0xF7, 0x80, 0xF3, 0xC0, 0x78, 0xF0, 0xF8, 0x7F, 0xFC, 0x1F, 0xFC,
- 0x03, 0xF8, 0x00, 0xFF, 0xE3, 0xFF, 0xEF, 0xFF, 0xBC, 0x1F, 0xF0, 0x3F,
- 0xC0, 0xFF, 0x03, 0xFC, 0x1F, 0xFF, 0xFB, 0xFF, 0xCF, 0xFE, 0x3C, 0x00,
- 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x00, 0x03,
- 0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x87, 0xC7, 0xC7, 0x80, 0xF3, 0xC0, 0x7B,
- 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x01, 0xFE, 0x04,
- 0xF7, 0x87, 0xF3, 0xC3, 0xF8, 0xF0, 0xF8, 0x7F, 0xFC, 0x1F, 0xFF, 0x83,
- 0xF1, 0x80, 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFC, 0xFF, 0xFC, 0xF0, 0x3E,
- 0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x3C, 0xFF, 0xF8, 0xFF, 0xF0,
- 0xFF, 0xF8, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C,
- 0xF0, 0x3C, 0xF0, 0x1F, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE7, 0xC3, 0xEF,
- 0x03, 0xDE, 0x00, 0x3C, 0x00, 0x7F, 0x00, 0x7F, 0xF0, 0x3F, 0xF8, 0x0F,
- 0xF8, 0x01, 0xF0, 0x01, 0xFE, 0x03, 0xDE, 0x0F, 0xBF, 0xFE, 0x3F, 0xF8,
- 0x1F, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F,
- 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xFF, 0x03,
- 0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xF7, 0x87, 0x9F, 0xFE, 0x3F, 0xF0, 0x3F,
- 0x00, 0x70, 0x0E, 0xF0, 0x3D, 0xE0, 0x79, 0xC0, 0xE3, 0x81, 0xC7, 0x87,
- 0x87, 0x0E, 0x0E, 0x1C, 0x1E, 0x78, 0x1C, 0xE0, 0x39, 0xC0, 0x73, 0x80,
- 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x70,
- 0x38, 0x1C, 0xE0, 0xF0, 0x79, 0xE1, 0xF0, 0xF3, 0xC3, 0xE1, 0xE3, 0x87,
- 0xC3, 0x87, 0x0F, 0x87, 0x0E, 0x3B, 0x9E, 0x1E, 0x77, 0x38, 0x1C, 0xEE,
- 0x70, 0x39, 0xCC, 0xE0, 0x73, 0x99, 0xC0, 0x6E, 0x3F, 0x00, 0xFC, 0x7E,
- 0x01, 0xF8, 0xFC, 0x03, 0xF0, 0xF8, 0x03, 0xE1, 0xE0, 0x07, 0x83, 0xC0,
- 0x0F, 0x07, 0x80, 0xF0, 0x3C, 0xF0, 0xF9, 0xE1, 0xE1, 0xE7, 0x83, 0xCF,
- 0x03, 0xFC, 0x03, 0xF0, 0x07, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x3F, 0x00,
- 0xFF, 0x01, 0xFE, 0x07, 0x9E, 0x0F, 0x1E, 0x3C, 0x3C, 0xF8, 0x3D, 0xE0,
- 0x78, 0xF0, 0x1E, 0x78, 0x1E, 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x78, 0x1E,
- 0x78, 0x0E, 0x70, 0x0F, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x03, 0xC0, 0x03,
- 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03,
- 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x01, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF8, 0x07, 0x80, 0x78, 0x07, 0x80, 0x7C, 0x03, 0xC0, 0x3C, 0x03,
- 0xC0, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFC, 0xF3, 0xCF,
- 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xFF, 0xFF,
- 0xC0, 0xC1, 0x81, 0x03, 0x06, 0x04, 0x0C, 0x18, 0x10, 0x30, 0x60, 0x40,
- 0xC1, 0x81, 0x03, 0x06, 0xFF, 0xFF, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3,
- 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0xFF, 0xFF, 0xC0, 0x0F, 0x00,
- 0xF0, 0x0F, 0x01, 0xF8, 0x1B, 0x83, 0x9C, 0x39, 0xC3, 0x0C, 0x70, 0xE7,
- 0x0E, 0xE0, 0x70, 0xFF, 0xFF, 0xFF, 0xFC, 0xE6, 0x30, 0x1F, 0x83, 0xFF,
- 0x1F, 0xFD, 0xE1, 0xE0, 0x0F, 0x03, 0xF9, 0xFF, 0xDF, 0x1E, 0xF0, 0xF7,
- 0x8F, 0xBF, 0xFC, 0xFF, 0xE3, 0xCF, 0x80, 0xF0, 0x07, 0x80, 0x3C, 0x01,
- 0xE0, 0x0F, 0x00, 0x7B, 0xC3, 0xFF, 0x9F, 0xFE, 0xF8, 0xF7, 0x83, 0xFC,
- 0x1F, 0xE0, 0xFF, 0x07, 0xF8, 0x3F, 0xE3, 0xDF, 0xFE, 0xFF, 0xE7, 0xBE,
- 0x00, 0x0F, 0x83, 0xFE, 0x7F, 0xF7, 0x8F, 0xF0, 0x7F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x77, 0x8F, 0x7F, 0xF3, 0xFE, 0x0F, 0x80, 0x00, 0x78, 0x03,
- 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x8F, 0xBC, 0xFF, 0xEF, 0xFF, 0x78, 0xFF,
- 0x83, 0xFC, 0x1F, 0xE0, 0xFF, 0x07, 0xF8, 0x3D, 0xE3, 0xEF, 0xFF, 0x3F,
- 0xF8, 0xFB, 0xC0, 0x1F, 0x81, 0xFE, 0x1F, 0xF9, 0xF1, 0xCF, 0x07, 0x7F,
- 0xFB, 0xFF, 0xDE, 0x00, 0xF0, 0x03, 0xC3, 0x9F, 0xFC, 0x7F, 0xC0, 0xF8,
- 0x00, 0x3E, 0xFD, 0xFB, 0xC7, 0x9F, 0xBF, 0x3C, 0x78, 0xF1, 0xE3, 0xC7,
- 0x8F, 0x1E, 0x3C, 0x78, 0xF0, 0x1E, 0x79, 0xFB, 0xDF, 0xFE, 0xF1, 0xFF,
- 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7F, 0xC7, 0xDF, 0xFE, 0x7F,
- 0xF1, 0xF7, 0x80, 0x3C, 0x01, 0xFF, 0x1E, 0x7F, 0xF0, 0xFE, 0x00, 0xF0,
- 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x7C, 0xFF, 0xEF, 0xFF, 0xF9,
- 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0,
- 0xFF, 0x0F, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3C,
- 0xF3, 0xC0, 0x00, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C,
- 0xF3, 0xCF, 0xFF, 0xFF, 0x80, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0,
- 0x0F, 0x0F, 0xF1, 0xEF, 0x3C, 0xF7, 0x8F, 0xF0, 0xFF, 0x0F, 0xF8, 0xFF,
- 0x8F, 0x3C, 0xF1, 0xCF, 0x1E, 0xF0, 0xEF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7, 0x8F, 0x9F, 0xFB, 0xFB, 0xFF, 0xFF,
- 0xFC, 0xF8, 0xFF, 0x1E, 0x1F, 0xE3, 0xC3, 0xFC, 0x78, 0x7F, 0x8F, 0x0F,
- 0xF1, 0xE1, 0xFE, 0x3C, 0x3F, 0xC7, 0x87, 0xF8, 0xF0, 0xFF, 0x1E, 0x1E,
- 0xF7, 0xCF, 0xFE, 0xFF, 0xFF, 0x9F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F,
- 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xF0, 0x0F, 0x81, 0xFF, 0x1F,
- 0xFC, 0xF1, 0xEF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7B, 0xC7,
- 0x9F, 0xFC, 0x7F, 0xC0, 0xF8, 0x00, 0xF7, 0xC7, 0xFF, 0x3F, 0xFD, 0xF1,
- 0xEF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7F, 0xC7, 0xBF, 0xFD,
- 0xFF, 0xCF, 0x78, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x00,
- 0x0F, 0x79, 0xFF, 0xDF, 0xFE, 0xF1, 0xFF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE,
- 0x0F, 0xF0, 0x7B, 0xC7, 0xDF, 0xFE, 0x7F, 0xF1, 0xF7, 0x80, 0x3C, 0x01,
- 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0xF3, 0xF7, 0xFF, 0xF8, 0xF0, 0xF0,
- 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0x1F, 0x87, 0xFC, 0xFF, 0xEF,
- 0x0F, 0xF8, 0x0F, 0xF0, 0x7F, 0xE0, 0xFF, 0x01, 0xFF, 0x0F, 0xFF, 0xE7,
- 0xFE, 0x1F, 0x80, 0x79, 0xE7, 0xBF, 0xFD, 0xE7, 0x9E, 0x79, 0xE7, 0x9E,
- 0x7D, 0xF3, 0xC0, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F,
- 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x1F, 0xFF, 0xF7, 0xFF, 0x3E, 0xF0, 0xF0,
- 0x7B, 0x83, 0x9E, 0x1C, 0xF1, 0xE3, 0x8E, 0x1C, 0x70, 0x77, 0x83, 0xB8,
- 0x1D, 0xC0, 0x7E, 0x03, 0xE0, 0x1F, 0x00, 0x70, 0x00, 0xF0, 0xE1, 0xDC,
- 0x78, 0x77, 0x1F, 0x3D, 0xE7, 0xCF, 0x79, 0xB3, 0x8E, 0x6C, 0xE3, 0xBB,
- 0x38, 0xEE, 0xFC, 0x1F, 0x3F, 0x07, 0xC7, 0xC1, 0xF1, 0xF0, 0x7C, 0x78,
- 0x0E, 0x1E, 0x00, 0x78, 0xF3, 0xC7, 0x8F, 0x78, 0x3B, 0x81, 0xFC, 0x07,
- 0xC0, 0x1E, 0x01, 0xF0, 0x1F, 0xC0, 0xEF, 0x0F, 0x78, 0xF1, 0xE7, 0x87,
- 0x00, 0xF0, 0x7B, 0x83, 0x9E, 0x1C, 0x71, 0xE3, 0x8E, 0x1E, 0x70, 0x73,
- 0x83, 0xB8, 0x1F, 0xC0, 0x7E, 0x03, 0xE0, 0x0F, 0x00, 0x70, 0x03, 0x80,
- 0x3C, 0x07, 0xC0, 0x3E, 0x01, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFC, 0x0F,
- 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x0F, 0xFF, 0xFF, 0xFF, 0xC0,
- 0x1C, 0xF3, 0xCE, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0xBC, 0xF0, 0xE3, 0x8E,
- 0x38, 0xE3, 0x8E, 0x3C, 0xF1, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,
- 0xE3, 0x8F, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x0F, 0x3D, 0xC7, 0x1C,
- 0x71, 0xC7, 0x1C, 0xF3, 0xCE, 0x00, 0x78, 0x0F, 0xE0, 0xCF, 0x30, 0x7F,
- 0x01, 0xE0 };
-
-const GFXglyph FreeSansBold12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 7, 0, 1 }, // 0x20 ' '
- { 0, 4, 17, 8, 3, -16 }, // 0x21 '!'
- { 9, 10, 6, 11, 1, -17 }, // 0x22 '"'
- { 17, 13, 16, 13, 0, -15 }, // 0x23 '#'
- { 43, 13, 20, 13, 0, -17 }, // 0x24 '$'
- { 76, 19, 17, 21, 1, -16 }, // 0x25 '%'
- { 117, 16, 17, 17, 1, -16 }, // 0x26 '&'
- { 151, 4, 6, 6, 1, -17 }, // 0x27 '''
- { 154, 6, 22, 8, 1, -17 }, // 0x28 '('
- { 171, 6, 22, 8, 1, -17 }, // 0x29 ')'
- { 188, 7, 8, 9, 1, -17 }, // 0x2A '*'
- { 195, 11, 11, 14, 2, -10 }, // 0x2B '+'
- { 211, 4, 7, 6, 1, -2 }, // 0x2C ','
- { 215, 6, 3, 8, 1, -7 }, // 0x2D '-'
- { 218, 4, 3, 6, 1, -2 }, // 0x2E '.'
- { 220, 6, 17, 7, 0, -16 }, // 0x2F '/'
- { 233, 12, 17, 13, 1, -16 }, // 0x30 '0'
- { 259, 7, 17, 14, 3, -16 }, // 0x31 '1'
- { 274, 12, 17, 13, 1, -16 }, // 0x32 '2'
- { 300, 12, 17, 13, 1, -16 }, // 0x33 '3'
- { 326, 11, 17, 13, 1, -16 }, // 0x34 '4'
- { 350, 12, 17, 13, 1, -16 }, // 0x35 '5'
- { 376, 12, 17, 13, 1, -16 }, // 0x36 '6'
- { 402, 11, 17, 13, 1, -16 }, // 0x37 '7'
- { 426, 12, 17, 13, 1, -16 }, // 0x38 '8'
- { 452, 12, 17, 13, 1, -16 }, // 0x39 '9'
- { 478, 4, 12, 6, 1, -11 }, // 0x3A ':'
- { 484, 4, 16, 6, 1, -11 }, // 0x3B ';'
- { 492, 12, 12, 14, 1, -11 }, // 0x3C '<'
- { 510, 12, 9, 14, 1, -9 }, // 0x3D '='
- { 524, 12, 12, 14, 1, -11 }, // 0x3E '>'
- { 542, 12, 18, 15, 2, -17 }, // 0x3F '?'
- { 569, 21, 21, 23, 1, -17 }, // 0x40 '@'
- { 625, 16, 18, 17, 0, -17 }, // 0x41 'A'
- { 661, 14, 18, 17, 2, -17 }, // 0x42 'B'
- { 693, 16, 18, 17, 1, -17 }, // 0x43 'C'
- { 729, 15, 18, 17, 2, -17 }, // 0x44 'D'
- { 763, 13, 18, 16, 2, -17 }, // 0x45 'E'
- { 793, 12, 18, 15, 2, -17 }, // 0x46 'F'
- { 820, 16, 18, 18, 1, -17 }, // 0x47 'G'
- { 856, 14, 18, 18, 2, -17 }, // 0x48 'H'
- { 888, 4, 18, 7, 2, -17 }, // 0x49 'I'
- { 897, 11, 18, 14, 1, -17 }, // 0x4A 'J'
- { 922, 16, 18, 17, 2, -17 }, // 0x4B 'K'
- { 958, 11, 18, 15, 2, -17 }, // 0x4C 'L'
- { 983, 17, 18, 21, 2, -17 }, // 0x4D 'M'
- { 1022, 15, 18, 18, 2, -17 }, // 0x4E 'N'
- { 1056, 17, 18, 19, 1, -17 }, // 0x4F 'O'
- { 1095, 14, 18, 16, 2, -17 }, // 0x50 'P'
- { 1127, 17, 19, 19, 1, -17 }, // 0x51 'Q'
- { 1168, 16, 18, 17, 2, -17 }, // 0x52 'R'
- { 1204, 15, 18, 16, 1, -17 }, // 0x53 'S'
- { 1238, 12, 18, 15, 2, -17 }, // 0x54 'T'
- { 1265, 14, 18, 18, 2, -17 }, // 0x55 'U'
- { 1297, 15, 18, 16, 0, -17 }, // 0x56 'V'
- { 1331, 23, 18, 23, 0, -17 }, // 0x57 'W'
- { 1383, 15, 18, 16, 1, -17 }, // 0x58 'X'
- { 1417, 16, 18, 15, 0, -17 }, // 0x59 'Y'
- { 1453, 13, 18, 15, 1, -17 }, // 0x5A 'Z'
- { 1483, 6, 23, 8, 2, -17 }, // 0x5B '['
- { 1501, 7, 17, 7, 0, -16 }, // 0x5C '\'
- { 1516, 6, 23, 8, 0, -17 }, // 0x5D ']'
- { 1534, 12, 11, 14, 1, -16 }, // 0x5E '^'
- { 1551, 15, 2, 13, -1, 4 }, // 0x5F '_'
- { 1555, 4, 3, 6, 0, -17 }, // 0x60 '`'
- { 1557, 13, 13, 14, 1, -12 }, // 0x61 'a'
- { 1579, 13, 18, 15, 2, -17 }, // 0x62 'b'
- { 1609, 12, 13, 13, 1, -12 }, // 0x63 'c'
- { 1629, 13, 18, 15, 1, -17 }, // 0x64 'd'
- { 1659, 13, 13, 14, 1, -12 }, // 0x65 'e'
- { 1681, 7, 18, 8, 1, -17 }, // 0x66 'f'
- { 1697, 13, 18, 15, 1, -12 }, // 0x67 'g'
- { 1727, 12, 18, 14, 2, -17 }, // 0x68 'h'
- { 1754, 4, 18, 7, 2, -17 }, // 0x69 'i'
- { 1763, 6, 23, 7, 0, -17 }, // 0x6A 'j'
- { 1781, 12, 18, 14, 2, -17 }, // 0x6B 'k'
- { 1808, 4, 18, 6, 2, -17 }, // 0x6C 'l'
- { 1817, 19, 13, 21, 2, -12 }, // 0x6D 'm'
- { 1848, 12, 13, 15, 2, -12 }, // 0x6E 'n'
- { 1868, 13, 13, 15, 1, -12 }, // 0x6F 'o'
- { 1890, 13, 18, 15, 2, -12 }, // 0x70 'p'
- { 1920, 13, 18, 15, 1, -12 }, // 0x71 'q'
- { 1950, 8, 13, 9, 2, -12 }, // 0x72 'r'
- { 1963, 12, 13, 13, 1, -12 }, // 0x73 's'
- { 1983, 6, 15, 8, 1, -14 }, // 0x74 't'
- { 1995, 12, 13, 15, 2, -12 }, // 0x75 'u'
- { 2015, 13, 13, 13, 0, -12 }, // 0x76 'v'
- { 2037, 18, 13, 19, 0, -12 }, // 0x77 'w'
- { 2067, 13, 13, 13, 0, -12 }, // 0x78 'x'
- { 2089, 13, 18, 13, 0, -12 }, // 0x79 'y'
- { 2119, 10, 13, 12, 1, -12 }, // 0x7A 'z'
- { 2136, 6, 23, 9, 1, -17 }, // 0x7B '{'
- { 2154, 2, 22, 7, 2, -17 }, // 0x7C '|'
- { 2160, 6, 23, 9, 3, -17 }, // 0x7D '}'
- { 2178, 12, 5, 12, 0, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSansBold12pt7b PROGMEM = {
- (uint8_t *)FreeSansBold12pt7bBitmaps,
- (GFXglyph *)FreeSansBold12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2858 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold18pt7b.h
deleted file mode 100644
index d5927cd..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold18pt7b.h
+++ /dev/null
@@ -1,481 +0,0 @@
-const uint8_t FreeSansBold18pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xE7, 0x39, 0xCE, 0x73, 0x80,
- 0x0F, 0xFF, 0xFF, 0xF8, 0xF8, 0xFF, 0xC7, 0xFE, 0x3F, 0xF1, 0xFF, 0x8F,
- 0xFC, 0x7D, 0xC1, 0xCE, 0x0E, 0x70, 0x70, 0x03, 0xC3, 0x80, 0x3C, 0x78,
- 0x03, 0xC7, 0x80, 0x38, 0x78, 0x07, 0x87, 0x07, 0xFF, 0xFF, 0x7F, 0xFF,
- 0xF7, 0xFF, 0xFF, 0x7F, 0xFF, 0xF0, 0xF0, 0xE0, 0x0F, 0x0E, 0x00, 0xF1,
- 0xE0, 0x0F, 0x1E, 0x00, 0xE1, 0xE0, 0xFF, 0xFF, 0xCF, 0xFF, 0xFC, 0xFF,
- 0xFF, 0xCF, 0xFF, 0xFC, 0x1C, 0x3C, 0x03, 0xC3, 0x80, 0x3C, 0x78, 0x03,
- 0xC7, 0x80, 0x38, 0x78, 0x03, 0x87, 0x80, 0x00, 0x60, 0x00, 0x7F, 0x80,
- 0x3F, 0xFC, 0x0F, 0xFF, 0xC3, 0xFF, 0xFC, 0xFC, 0xDF, 0x9F, 0x19, 0xFB,
- 0xC3, 0x1F, 0x78, 0x63, 0xEF, 0x8C, 0x01, 0xFD, 0x80, 0x1F, 0xF0, 0x01,
- 0xFF, 0xC0, 0x1F, 0xFE, 0x00, 0x7F, 0xE0, 0x03, 0xFE, 0x00, 0x67, 0xE0,
- 0x0C, 0x7F, 0xE1, 0x8F, 0xFC, 0x31, 0xFF, 0xC6, 0x3E, 0xFC, 0xDF, 0x9F,
- 0xFF, 0xF1, 0xFF, 0xFC, 0x0F, 0xFF, 0x00, 0x7F, 0x80, 0x01, 0x80, 0x00,
- 0x30, 0x00, 0x06, 0x00, 0x0F, 0x00, 0x1C, 0x01, 0xFE, 0x00, 0xE0, 0x1F,
- 0xF8, 0x0E, 0x00, 0xFF, 0xC0, 0x70, 0x0F, 0x0F, 0x07, 0x00, 0x70, 0x38,
- 0x38, 0x03, 0x81, 0xC3, 0x80, 0x1C, 0x0E, 0x3C, 0x00, 0xF0, 0xF1, 0xC0,
- 0x03, 0xFF, 0x1C, 0x00, 0x1F, 0xF8, 0xE0, 0x00, 0x7F, 0x8E, 0x00, 0x00,
- 0xF0, 0x70, 0xF8, 0x00, 0x07, 0x1F, 0xF0, 0x00, 0x39, 0xFF, 0xC0, 0x03,
- 0x8F, 0xFE, 0x00, 0x1C, 0xF0, 0x78, 0x01, 0xC7, 0x01, 0xC0, 0x0C, 0x38,
- 0x0E, 0x00, 0xE1, 0xC0, 0x70, 0x06, 0x0F, 0x07, 0x80, 0x70, 0x3F, 0xF8,
- 0x07, 0x01, 0xFF, 0xC0, 0x38, 0x07, 0xFC, 0x03, 0x80, 0x0F, 0x80, 0x01,
- 0xF0, 0x00, 0x1F, 0xE0, 0x00, 0xFF, 0xC0, 0x03, 0xFF, 0x80, 0x1F, 0x1E,
- 0x00, 0x7C, 0x78, 0x01, 0xF1, 0xE0, 0x07, 0xE7, 0x80, 0x0F, 0xBC, 0x00,
- 0x1F, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8, 0x00, 0x1F, 0xF0, 0xF0, 0xFF,
- 0xE3, 0xC7, 0xE7, 0xCF, 0x3F, 0x0F, 0xF8, 0xF8, 0x3F, 0xE3, 0xE0, 0x7F,
- 0x8F, 0x80, 0xFC, 0x3F, 0x03, 0xF0, 0x7E, 0x3F, 0xE1, 0xFF, 0xFF, 0x83,
- 0xFF, 0xFF, 0x07, 0xFE, 0x7E, 0x07, 0xF0, 0xFC, 0xFF, 0xFF, 0xFF, 0xFD,
- 0xCE, 0x70, 0x07, 0x87, 0x83, 0xC3, 0xC1, 0xE1, 0xE0, 0xF0, 0x78, 0x78,
- 0x3C, 0x1E, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E,
- 0x0F, 0x03, 0x81, 0xE0, 0xF0, 0x78, 0x1E, 0x0F, 0x03, 0x81, 0xE0, 0x70,
- 0x3C, 0x0E, 0x07, 0x80, 0xF0, 0x38, 0x1E, 0x07, 0x83, 0xC0, 0xF0, 0x78,
- 0x3C, 0x0F, 0x07, 0x83, 0xC0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83,
- 0xC1, 0xE0, 0xF0, 0x78, 0x78, 0x3C, 0x1E, 0x0F, 0x0F, 0x07, 0x87, 0x83,
- 0xC1, 0xC1, 0xE0, 0xE0, 0xF0, 0x00, 0x06, 0x00, 0x60, 0x06, 0x07, 0x6E,
- 0x7F, 0xE3, 0xFC, 0x0F, 0x01, 0xF8, 0x1F, 0x83, 0x9C, 0x10, 0x80, 0x03,
- 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x03, 0xC0, 0x03,
- 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF, 0xFF, 0x8C, 0x63,
- 0x37, 0xB0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x80, 0x01,
- 0x81, 0xC0, 0xC0, 0x60, 0x70, 0x38, 0x18, 0x0C, 0x0E, 0x06, 0x03, 0x01,
- 0x81, 0xC0, 0xC0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x01,
- 0x81, 0xC0, 0xC0, 0x00, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0xFF,
- 0xC7, 0xE3, 0xF3, 0xE0, 0xF9, 0xF0, 0x7D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC,
- 0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F,
- 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xDF, 0x07, 0xCF, 0x83, 0xE7, 0xE3,
- 0xF1, 0xFF, 0xF0, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x01, 0xC0,
- 0xF0, 0x3C, 0x1F, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC1, 0xF0, 0x7C,
- 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07,
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- 0x8F, 0xFF, 0xE7, 0xE3, 0xF7, 0xE0, 0xFF, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8,
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- 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83, 0xF7, 0xC3, 0xF3, 0xFF, 0xF8, 0xFF,
- 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x00, 0xFC, 0x00, 0xFC, 0x01, 0xFC,
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- 0x7D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83, 0xF7,
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- 0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F, 0xFF, 0xC7, 0xE3, 0xF7, 0xE0, 0xFB,
- 0xE0, 0x3D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83,
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- 0x07, 0x80, 0x03, 0xDF, 0x03, 0xE7, 0xC3, 0xE3, 0xFF, 0xF0, 0xFF, 0xF0,
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- 0x00, 0x7F, 0xFF, 0xFF, 0xC6, 0x33, 0x9B, 0xD8, 0x00, 0x00, 0xC0, 0x00,
- 0xF0, 0x01, 0xFC, 0x03, 0xFF, 0x03, 0xFF, 0x07, 0xFE, 0x0F, 0xFC, 0x03,
- 0xF8, 0x00, 0xF0, 0x00, 0x3F, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0xE0, 0x07,
- 0xFF, 0x00, 0x3F, 0xF0, 0x01, 0xFC, 0x00, 0x1F, 0x00, 0x00, 0xC0, 0xFF,
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- 0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0xC3, 0xF8, 0x1F, 0x87, 0xE0, 0x1F, 0x9F,
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- 0x03, 0xEF, 0x80, 0x3E, 0x7C, 0x07, 0xF3, 0xFF, 0xFF, 0x1F, 0xFF, 0xF0,
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- 0xFF, 0x80, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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- 0x1F, 0x83, 0xE0, 0xFC, 0x0F, 0x87, 0xE0, 0x3E, 0x3F, 0x00, 0xF8, 0xF8,
- 0x03, 0xE7, 0xE0, 0x0F, 0xBF, 0x00, 0x3F, 0xF8, 0x00, 0xFF, 0xF0, 0x03,
- 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x3F, 0xBF, 0x00, 0xFC, 0x7E, 0x03, 0xE0,
- 0xFC, 0x0F, 0x81, 0xF8, 0x3E, 0x07, 0xE0, 0xF8, 0x0F, 0xC3, 0xE0, 0x1F,
- 0x8F, 0x80, 0x7F, 0x3E, 0x00, 0xFC, 0xF8, 0x01, 0xFB, 0xE0, 0x03, 0xF0,
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- 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F,
- 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00,
- 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF,
- 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0x81, 0xFF, 0xFF,
- 0x81, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x81, 0xFF, 0xFB, 0xC3, 0xDF, 0xFB,
- 0xC3, 0xDF, 0xFB, 0xC3, 0xDF, 0xFB, 0xC3, 0xDF, 0xF9, 0xC7, 0xDF, 0xF9,
- 0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF8,
- 0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8,
- 0x7F, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8,
- 0x3E, 0x1F, 0xF8, 0x01, 0xFF, 0xC0, 0x1F, 0xFE, 0x01, 0xFF, 0xE0, 0x1F,
- 0xFF, 0x01, 0xFF, 0xF0, 0x1F, 0xFF, 0x81, 0xFF, 0xF8, 0x1F, 0xFF, 0xC1,
- 0xFF, 0xBC, 0x1F, 0xFB, 0xE1, 0xFF, 0x9F, 0x1F, 0xF9, 0xF1, 0xFF, 0x8F,
- 0x9F, 0xF8, 0x79, 0xFF, 0x87, 0xDF, 0xF8, 0x3D, 0xFF, 0x83, 0xFF, 0xF8,
- 0x1F, 0xFF, 0x81, 0xFF, 0xF8, 0x0F, 0xFF, 0x80, 0xFF, 0xF8, 0x07, 0xFF,
- 0x80, 0x3F, 0xF8, 0x03, 0xFF, 0x80, 0x1F, 0x00, 0x7F, 0x00, 0x01, 0xFF,
- 0xF0, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x01, 0xFC, 0x1F, 0xC1, 0xF8,
- 0x03, 0xF1, 0xF8, 0x00, 0xFC, 0xF8, 0x00, 0x3E, 0x7C, 0x00, 0x1F, 0x7C,
- 0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF,
- 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00, 0x1F, 0xF8, 0x00, 0x0F,
- 0xBE, 0x00, 0x0F, 0x9F, 0x00, 0x07, 0xCF, 0xC0, 0x07, 0xE3, 0xF0, 0x07,
- 0xE0, 0xFE, 0x0F, 0xE0, 0x7F, 0xFF, 0xE0, 0x0F, 0xFF, 0xE0, 0x03, 0xFF,
- 0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFF, 0xFC, 0x1F, 0xFF, 0xE3, 0xFF, 0xFE,
- 0x7F, 0xFF, 0xEF, 0x80, 0xFF, 0xF0, 0x0F, 0xFE, 0x00, 0xFF, 0xC0, 0x1F,
- 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xE0, 0x1F, 0xFC, 0x07, 0xEF, 0xFF, 0xFD,
- 0xFF, 0xFF, 0x3F, 0xFF, 0xC7, 0xFF, 0xE0, 0xF8, 0x00, 0x1F, 0x00, 0x03,
- 0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07,
- 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x01, 0xFF,
- 0xF0, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x01, 0xFC, 0x1F, 0xC1, 0xF8,
- 0x03, 0xF1, 0xF8, 0x00, 0xFC, 0xF8, 0x00, 0x3E, 0x7C, 0x00, 0x1F, 0x7C,
- 0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF,
- 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00, 0x1F, 0xF8, 0x01, 0x0F,
- 0xBE, 0x01, 0xCF, 0x9F, 0x01, 0xFF, 0xCF, 0xC0, 0x7F, 0xE3, 0xF0, 0x1F,
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- 0x00, 0xFF, 0x80, 0x1F, 0xE0, 0x07, 0xF0, 0x00, 0xF8, 0x00, 0x7F, 0x00,
- 0x3F, 0xE0, 0x0F, 0xF8, 0x07, 0xDF, 0x03, 0xF7, 0xE0, 0xF8, 0xF8, 0x7E,
- 0x3F, 0x1F, 0x07, 0xEF, 0xC0, 0xF8, 0x7C, 0x03, 0xEF, 0x80, 0xF9, 0xF8,
- 0x1F, 0x1F, 0x03, 0xE3, 0xE0, 0xF8, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8,
- 0x78, 0x0F, 0x1F, 0x01, 0xF3, 0xC0, 0x3E, 0x78, 0x03, 0xDF, 0x00, 0x7F,
- 0xC0, 0x0F, 0xF8, 0x00, 0xFF, 0x00, 0x1F, 0xC0, 0x01, 0xF8, 0x00, 0x3F,
- 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x07, 0xC0, 0x07, 0xF8,
- 0x00, 0xFE, 0x00, 0x1F, 0x80, 0x03, 0xE0, 0x00, 0x7F, 0xFE, 0x7F, 0xFE,
- 0x7F, 0xFE, 0x7F, 0xFE, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0,
- 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00,
- 0xFE, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x87,
- 0xC7, 0xE3, 0xF1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC1,
- 0xE0, 0xF0, 0xF9, 0xF8, 0xF0, 0x7E, 0x0F, 0x83, 0xC1, 0xE0, 0xF0, 0x78,
- 0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xFC, 0x7E, 0x1F, 0x07, 0x80,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xE0, 0xF0, 0x7C, 0x3E, 0x1F, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E,
- 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x7C, 0x1F, 0x83, 0xC7, 0xE7, 0xC3,
- 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC7, 0xE3, 0xE1,
- 0xF0, 0xF0, 0x00, 0x3C, 0x00, 0xFE, 0x0F, 0xFE, 0x1E, 0x1F, 0xFC, 0x0F,
- 0xC0, 0x0F, 0x00 };
-
-const GFXglyph FreeSansBold18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 10, 0, 1 }, // 0x20 ' '
- { 0, 5, 25, 12, 4, -24 }, // 0x21 '!'
- { 16, 13, 9, 17, 2, -25 }, // 0x22 '"'
- { 31, 20, 24, 19, 0, -23 }, // 0x23 '#'
- { 91, 19, 29, 19, 0, -25 }, // 0x24 '$'
- { 160, 29, 25, 31, 1, -24 }, // 0x25 '%'
- { 251, 22, 25, 25, 2, -24 }, // 0x26 '&'
- { 320, 5, 9, 9, 2, -25 }, // 0x27 '''
- { 326, 9, 33, 12, 1, -25 }, // 0x28 '('
- { 364, 9, 33, 12, 1, -25 }, // 0x29 ')'
- { 402, 12, 11, 14, 0, -25 }, // 0x2A '*'
- { 419, 16, 16, 20, 2, -15 }, // 0x2B '+'
- { 451, 5, 11, 9, 2, -4 }, // 0x2C ','
- { 458, 9, 4, 12, 1, -10 }, // 0x2D '-'
- { 463, 5, 5, 9, 2, -4 }, // 0x2E '.'
- { 467, 9, 25, 10, 0, -24 }, // 0x2F '/'
- { 496, 17, 25, 19, 1, -24 }, // 0x30 '0'
- { 550, 10, 25, 19, 3, -24 }, // 0x31 '1'
- { 582, 17, 25, 19, 1, -24 }, // 0x32 '2'
- { 636, 17, 25, 19, 1, -24 }, // 0x33 '3'
- { 690, 16, 25, 19, 2, -24 }, // 0x34 '4'
- { 740, 17, 25, 19, 1, -24 }, // 0x35 '5'
- { 794, 18, 25, 19, 1, -24 }, // 0x36 '6'
- { 851, 17, 25, 19, 1, -24 }, // 0x37 '7'
- { 905, 17, 25, 19, 1, -24 }, // 0x38 '8'
- { 959, 17, 25, 19, 1, -24 }, // 0x39 '9'
- { 1013, 5, 18, 9, 2, -17 }, // 0x3A ':'
- { 1025, 5, 24, 9, 2, -17 }, // 0x3B ';'
- { 1040, 18, 17, 20, 1, -16 }, // 0x3C '<'
- { 1079, 17, 12, 20, 2, -13 }, // 0x3D '='
- { 1105, 18, 17, 20, 1, -16 }, // 0x3E '>'
- { 1144, 18, 26, 21, 2, -25 }, // 0x3F '?'
- { 1203, 32, 31, 34, 1, -25 }, // 0x40 '@'
- { 1327, 24, 26, 24, 0, -25 }, // 0x41 'A'
- { 1405, 20, 26, 25, 3, -25 }, // 0x42 'B'
- { 1470, 23, 26, 25, 1, -25 }, // 0x43 'C'
- { 1545, 21, 26, 25, 3, -25 }, // 0x44 'D'
- { 1614, 19, 26, 23, 3, -25 }, // 0x45 'E'
- { 1676, 17, 26, 22, 3, -25 }, // 0x46 'F'
- { 1732, 24, 26, 27, 1, -25 }, // 0x47 'G'
- { 1810, 20, 26, 26, 3, -25 }, // 0x48 'H'
- { 1875, 5, 26, 11, 3, -25 }, // 0x49 'I'
- { 1892, 16, 26, 20, 1, -25 }, // 0x4A 'J'
- { 1944, 22, 26, 25, 3, -25 }, // 0x4B 'K'
- { 2016, 17, 26, 22, 3, -25 }, // 0x4C 'L'
- { 2072, 24, 26, 30, 3, -25 }, // 0x4D 'M'
- { 2150, 20, 26, 26, 3, -25 }, // 0x4E 'N'
- { 2215, 25, 26, 27, 1, -25 }, // 0x4F 'O'
- { 2297, 19, 26, 24, 3, -25 }, // 0x50 'P'
- { 2359, 25, 27, 27, 1, -25 }, // 0x51 'Q'
- { 2444, 21, 26, 25, 3, -25 }, // 0x52 'R'
- { 2513, 20, 26, 24, 2, -25 }, // 0x53 'S'
- { 2578, 19, 26, 23, 2, -25 }, // 0x54 'T'
- { 2640, 20, 26, 26, 3, -25 }, // 0x55 'U'
- { 2705, 22, 26, 23, 1, -25 }, // 0x56 'V'
- { 2777, 32, 26, 34, 1, -25 }, // 0x57 'W'
- { 2881, 22, 26, 24, 1, -25 }, // 0x58 'X'
- { 2953, 21, 26, 22, 1, -25 }, // 0x59 'Y'
- { 3022, 19, 26, 21, 1, -25 }, // 0x5A 'Z'
- { 3084, 8, 33, 12, 2, -25 }, // 0x5B '['
- { 3117, 10, 25, 10, 0, -24 }, // 0x5C '\'
- { 3149, 8, 33, 12, 1, -25 }, // 0x5D ']'
- { 3182, 16, 15, 20, 2, -23 }, // 0x5E '^'
- { 3212, 21, 3, 19, -1, 5 }, // 0x5F '_'
- { 3220, 7, 5, 9, 1, -25 }, // 0x60 '`'
- { 3225, 18, 19, 20, 1, -18 }, // 0x61 'a'
- { 3268, 18, 26, 22, 2, -25 }, // 0x62 'b'
- { 3327, 17, 19, 20, 1, -18 }, // 0x63 'c'
- { 3368, 19, 26, 22, 1, -25 }, // 0x64 'd'
- { 3430, 18, 19, 20, 1, -18 }, // 0x65 'e'
- { 3473, 10, 26, 12, 1, -25 }, // 0x66 'f'
- { 3506, 18, 26, 21, 1, -18 }, // 0x67 'g'
- { 3565, 17, 26, 21, 2, -25 }, // 0x68 'h'
- { 3621, 5, 26, 10, 2, -25 }, // 0x69 'i'
- { 3638, 7, 33, 10, 0, -25 }, // 0x6A 'j'
- { 3667, 17, 26, 20, 2, -25 }, // 0x6B 'k'
- { 3723, 5, 26, 9, 2, -25 }, // 0x6C 'l'
- { 3740, 27, 19, 31, 2, -18 }, // 0x6D 'm'
- { 3805, 17, 19, 21, 2, -18 }, // 0x6E 'n'
- { 3846, 19, 19, 21, 1, -18 }, // 0x6F 'o'
- { 3892, 18, 26, 22, 2, -18 }, // 0x70 'p'
- { 3951, 19, 26, 22, 1, -18 }, // 0x71 'q'
- { 4013, 11, 19, 14, 2, -18 }, // 0x72 'r'
- { 4040, 17, 19, 19, 1, -18 }, // 0x73 's'
- { 4081, 9, 23, 12, 1, -22 }, // 0x74 't'
- { 4107, 17, 19, 21, 2, -18 }, // 0x75 'u'
- { 4148, 19, 19, 19, 0, -18 }, // 0x76 'v'
- { 4194, 27, 19, 27, 0, -18 }, // 0x77 'w'
- { 4259, 18, 19, 19, 1, -18 }, // 0x78 'x'
- { 4302, 19, 26, 19, 0, -18 }, // 0x79 'y'
- { 4364, 16, 19, 18, 1, -18 }, // 0x7A 'z'
- { 4402, 9, 33, 14, 1, -25 }, // 0x7B '{'
- { 4440, 3, 33, 10, 4, -25 }, // 0x7C '|'
- { 4453, 9, 33, 14, 3, -25 }, // 0x7D '}'
- { 4491, 15, 6, 18, 1, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSansBold18pt7b PROGMEM = {
- (uint8_t *)FreeSansBold18pt7bBitmaps,
- (GFXglyph *)FreeSansBold18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 5175 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold24pt7b.h
deleted file mode 100644
index aadc9a1..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold24pt7b.h
+++ /dev/null
@@ -1,784 +0,0 @@
-const uint8_t FreeSansBold24pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xDF, 0x3E, 0x7C, 0xF9, 0xF3, 0xE7, 0xC7, 0x0E, 0x1C, 0x00, 0x00, 0x07,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0x1F, 0xFF, 0x87, 0xFF, 0xE1,
- 0xFF, 0xF8, 0x7F, 0xFE, 0x1F, 0xFF, 0x87, 0xFF, 0xE1, 0xFD, 0xF0, 0x3E,
- 0x7C, 0x0F, 0x9F, 0x03, 0xE3, 0x80, 0x70, 0xE0, 0x1C, 0x00, 0xF8, 0x3E,
- 0x00, 0x3E, 0x0F, 0x80, 0x0F, 0x83, 0xE0, 0x03, 0xE0, 0xF8, 0x00, 0xF8,
- 0x7C, 0x00, 0x7C, 0x1F, 0x00, 0x1F, 0x07, 0xC1, 0xFF, 0xFF, 0xFF, 0x7F,
- 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,
- 0x03, 0xE0, 0xF8, 0x00, 0xF8, 0x3E, 0x00, 0x3E, 0x1F, 0x00, 0x1F, 0x07,
- 0xC0, 0x07, 0xC1, 0xF0, 0x01, 0xF0, 0x7C, 0x00, 0x7C, 0x1F, 0x03, 0xFF,
- 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xF3,
- 0xFF, 0xFF, 0xFC, 0x0F, 0x87, 0xC0, 0x07, 0xC1, 0xF0, 0x01, 0xF0, 0x7C,
- 0x00, 0x7C, 0x1F, 0x00, 0x1F, 0x07, 0xC0, 0x07, 0xC3, 0xE0, 0x03, 0xE0,
- 0xF8, 0x00, 0xF8, 0x3E, 0x00, 0x3E, 0x0F, 0x80, 0x00, 0x00, 0x38, 0x00,
- 0x00, 0x1C, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0xFF, 0xFC, 0x00, 0xFF, 0xFF,
- 0x80, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0x73, 0xFE, 0x7F, 0x38,
- 0xFF, 0x3F, 0x1C, 0x3F, 0xDF, 0x8E, 0x0F, 0xEF, 0xC7, 0x07, 0xF7, 0xE3,
- 0x80, 0x03, 0xF9, 0xC0, 0x01, 0xFE, 0xE0, 0x00, 0x7F, 0xF0, 0x00, 0x3F,
- 0xFC, 0x00, 0x0F, 0xFF, 0xC0, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0x80,
- 0x0F, 0xFF, 0xE0, 0x01, 0xFF, 0xF8, 0x00, 0xE7, 0xFC, 0x00, 0x71, 0xFF,
- 0x00, 0x38, 0x7F, 0xFF, 0x1C, 0x1F, 0xFF, 0x8E, 0x0F, 0xFF, 0xC7, 0x07,
- 0xFF, 0xE3, 0x87, 0xFB, 0xF9, 0xC3, 0xF9, 0xFE, 0xE7, 0xFC, 0x7F, 0xFF,
- 0xFC, 0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x00, 0x3F,
- 0xE0, 0x00, 0x03, 0x80, 0x00, 0x01, 0xC0, 0x00, 0x00, 0xE0, 0x00, 0x00,
- 0x70, 0x00, 0x03, 0xE0, 0x00, 0x3C, 0x00, 0x1F, 0xF0, 0x00, 0x78, 0x00,
- 0x7F, 0xF8, 0x01, 0xE0, 0x01, 0xFF, 0xF0, 0x03, 0xC0, 0x07, 0xFF, 0xF0,
- 0x0F, 0x00, 0x0F, 0x83, 0xE0, 0x1E, 0x00, 0x3E, 0x03, 0xE0, 0x78, 0x00,
- 0x78, 0x03, 0xC0, 0xF0, 0x00, 0xF0, 0x07, 0x83, 0xC0, 0x01, 0xE0, 0x0F,
- 0x07, 0x80, 0x03, 0xE0, 0x3E, 0x1E, 0x00, 0x03, 0xE0, 0xF8, 0x3C, 0x00,
- 0x07, 0xFF, 0xF0, 0xF0, 0x00, 0x07, 0xFF, 0xC1, 0xE0, 0x00, 0x07, 0xFF,
- 0x07, 0x80, 0x00, 0x07, 0xFC, 0x1F, 0x00, 0x00, 0x03, 0xE0, 0x3C, 0x00,
- 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x01, 0xE0, 0xFF, 0x80, 0x00,
- 0x07, 0x87, 0xFF, 0xC0, 0x00, 0x0F, 0x0F, 0xFF, 0x80, 0x00, 0x3C, 0x3F,
- 0xFF, 0x80, 0x00, 0x78, 0xFC, 0x1F, 0x00, 0x01, 0xE1, 0xF0, 0x1F, 0x00,
- 0x03, 0xC3, 0xC0, 0x1E, 0x00, 0x0F, 0x07, 0x80, 0x3C, 0x00, 0x1E, 0x0F,
- 0x00, 0x78, 0x00, 0x78, 0x1F, 0x01, 0xF0, 0x00, 0xF0, 0x1F, 0x07, 0xC0,
- 0x03, 0xC0, 0x3F, 0xFF, 0x80, 0x07, 0x80, 0x3F, 0xFE, 0x00, 0x1E, 0x00,
- 0x7F, 0xF8, 0x00, 0x7C, 0x00, 0x3F, 0xE0, 0x00, 0xF0, 0x00, 0x1F, 0x00,
- 0x00, 0x3F, 0x00, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00,
- 0xFF, 0xF8, 0x00, 0x07, 0xFF, 0xF0, 0x00, 0x3F, 0xCF, 0xC0, 0x00, 0xFE,
- 0x1F, 0x00, 0x03, 0xF8, 0x7C, 0x00, 0x0F, 0xE1, 0xF0, 0x00, 0x3F, 0xC7,
- 0xC0, 0x00, 0x7F, 0x3E, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x03, 0xFF, 0xC0,
- 0x00, 0x07, 0xFE, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x7F, 0x80, 0x00,
- 0x07, 0xFF, 0x03, 0xE0, 0x3F, 0xFE, 0x0F, 0x83, 0xFF, 0xF8, 0x3E, 0x1F,
- 0xF3, 0xF1, 0xF8, 0x7F, 0x07, 0xE7, 0xE3, 0xFC, 0x1F, 0xFF, 0x0F, 0xE0,
- 0x3F, 0xFC, 0x3F, 0x80, 0x7F, 0xF0, 0xFE, 0x01, 0xFF, 0x83, 0xF8, 0x03,
- 0xFE, 0x0F, 0xF0, 0x0F, 0xF0, 0x3F, 0xE0, 0x7F, 0xE0, 0x7F, 0xC3, 0xFF,
- 0xC1, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xFE, 0x07, 0xFF, 0xFB, 0xFC,
- 0x0F, 0xFF, 0xC7, 0xF8, 0x1F, 0xFE, 0x0F, 0xE0, 0x0F, 0xE0, 0x00, 0x00,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBE, 0x7C, 0xF8, 0xE1, 0xC0, 0x00,
- 0xF0, 0x0F, 0x80, 0xF8, 0x07, 0xC0, 0x7C, 0x07, 0xE0, 0x3E, 0x03, 0xF0,
- 0x1F, 0x80, 0xF8, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F,
- 0xC0, 0xFC, 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xF0,
- 0x1F, 0x80, 0xFC, 0x07, 0xE0, 0x3F, 0x00, 0xF8, 0x07, 0xE0, 0x3F, 0x01,
- 0xF8, 0x07, 0xC0, 0x3F, 0x01, 0xF8, 0x07, 0xC0, 0x3F, 0x00, 0xF8, 0x07,
- 0xE0, 0x1F, 0x00, 0xF8, 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xE0, 0x78,
- 0x03, 0xE0, 0x0F, 0x80, 0x7C, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x01, 0xF0,
- 0x0F, 0xC0, 0x3E, 0x01, 0xF8, 0x0F, 0xC0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0,
- 0x7E, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x1F, 0x80, 0xFC, 0x07,
- 0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xE0, 0x3F, 0x01, 0xF8,
- 0x0F, 0xC0, 0x7C, 0x07, 0xE0, 0x3F, 0x01, 0xF0, 0x1F, 0x80, 0xF8, 0x0F,
- 0xC0, 0x7C, 0x07, 0xE0, 0x3E, 0x03, 0xF0, 0x1F, 0x01, 0xF0, 0x00, 0x03,
- 0x80, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x06, 0x38, 0xDF, 0xFF, 0xFF, 0xFF,
- 0x9F, 0xFE, 0x07, 0xC0, 0x1F, 0xC0, 0x3F, 0x80, 0xF7, 0x83, 0xC7, 0x87,
- 0x8F, 0x02, 0x08, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0,
- 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00,
- 0x00, 0x3E, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x1F, 0x00, 0x00,
- 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03,
- 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x87, 0x0E, 0x1C, 0x78, 0xEF, 0xDF, 0x38, 0x00, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x80, 0x00, 0x38, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x07, 0x00,
- 0x70, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x38,
- 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x38, 0x03, 0xC0, 0x1C, 0x00,
- 0xE0, 0x07, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0E, 0x00, 0x70,
- 0x03, 0x80, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00,
- 0xFF, 0x00, 0x03, 0xFF, 0xC0, 0x0F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF8, 0x1F,
- 0xFF, 0xF8, 0x3F, 0xFF, 0xFC, 0x3F, 0xC3, 0xFC, 0x7F, 0x81, 0xFE, 0x7F,
- 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0xFE, 0x00, 0x7F, 0xFE,
- 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE,
- 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE,
- 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0x7F,
- 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x81, 0xFE, 0x3F,
- 0xC3, 0xFC, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xF8, 0x1F, 0xFF, 0xF8, 0x0F,
- 0xFF, 0xF0, 0x03, 0xFF, 0xC0, 0x00, 0xFF, 0x00, 0x00, 0x3C, 0x01, 0xF0,
- 0x07, 0xC0, 0x3F, 0x01, 0xFC, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0x1F, 0x80, 0x7E,
- 0x0F, 0xE7, 0xFE, 0x1F, 0xF8, 0xFE, 0xFF, 0xF3, 0xFF, 0xCF, 0xFF, 0xFF,
- 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x83, 0xFF, 0x0F, 0xFF, 0xF0, 0x1F, 0xE0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,
- 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F,
- 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE,
- 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,
- 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F,
- 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE,
- 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,
- 0xF0, 0xFE, 0x1F, 0xC1, 0xFC, 0xFF, 0xE3, 0xFB, 0xFF, 0xE7, 0xFF, 0xFF,
- 0xEF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0xFF,
- 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07, 0xFF,
- 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F, 0xFE,
- 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07, 0xFF, 0xE0,
- 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F, 0xFE, 0x00,
- 0xFE, 0x00, 0x7F, 0x80, 0x01, 0xFF, 0xF0, 0x01, 0xFF, 0xFE, 0x01, 0xFF,
- 0xFF, 0x81, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xF1, 0xFF, 0x07, 0xFC, 0xFF,
- 0x01, 0xFE, 0x7F, 0x00, 0x7F, 0x7F, 0x80, 0x3F, 0xFF, 0x80, 0x0F, 0xFF,
- 0xC0, 0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF,
- 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xBF, 0x80, 0x3F, 0x9F, 0xE0, 0x3F,
- 0xCF, 0xF8, 0x3F, 0xE3, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF,
- 0xF0, 0x0F, 0xFF, 0xF0, 0x03, 0xFF, 0xE0, 0x00, 0x3F, 0xC0, 0x00, 0xFE,
- 0x1F, 0x80, 0x7F, 0x3F, 0xF0, 0x3F, 0xBF, 0xFE, 0x1F, 0xDF, 0xFF, 0x8F,
- 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0xF3, 0xFF, 0x07, 0xFD, 0xFF, 0x01, 0xFE,
- 0xFF, 0x00, 0x7F, 0x7F, 0x80, 0x3F, 0xFF, 0x80, 0x0F, 0xFF, 0xC0, 0x07,
- 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF, 0xFC, 0x00,
- 0x7F, 0xFF, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xBF, 0xE0, 0x3F, 0xDF, 0xF8,
- 0x3F, 0xCF, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0xE3, 0xFB, 0xFF, 0xE1, 0xFD,
- 0xFF, 0xF0, 0xFE, 0x7F, 0xE0, 0x7F, 0x0F, 0xC0, 0x3F, 0x80, 0x00, 0x1F,
- 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x01,
- 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80, 0x00,
- 0x1F, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x81, 0xFF, 0x9F, 0xC3, 0xFF,
- 0xEF, 0xE1, 0xFF, 0xF7, 0xF1, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xFD, 0xFF,
- 0x07, 0xFE, 0xFF, 0x01, 0xFF, 0x7F, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xFF,
- 0x80, 0x0F, 0xFF, 0xC0, 0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF,
- 0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xBF, 0x80, 0x3F,
- 0xDF, 0xE0, 0x3F, 0xEF, 0xF8, 0x3F, 0xF3, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF,
- 0xFC, 0x7F, 0xFE, 0xFE, 0x1F, 0xFF, 0x7F, 0x03, 0xFF, 0x3F, 0x80, 0x7E,
- 0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00,
- 0x01, 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80,
- 0x00, 0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0xFE, 0x1F, 0xFC,
- 0x7F, 0xFB, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x7F, 0x80,
- 0xFF, 0x01, 0xFC, 0x03, 0xF8, 0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0xC0, 0x3F,
- 0x80, 0x7F, 0x00, 0xFE, 0x01, 0xFC, 0x03, 0xF8, 0x07, 0xF0, 0x0F, 0xE0,
- 0x1F, 0xC0, 0x3F, 0x80, 0x7F, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x07,
- 0xFF, 0xE0, 0x0F, 0xFF, 0xF8, 0x1F, 0xFF, 0xFC, 0x3F, 0xFF, 0xFC, 0x7F,
- 0x81, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0xC0, 0x00, 0x7F,
- 0xFC, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xFF, 0xF0, 0x1F, 0xFF, 0xFC, 0x07,
- 0xFF, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x0F, 0xFF, 0x00, 0x01, 0xFF, 0x00,
- 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0x7F, 0x00, 0x7F, 0x7F, 0x81, 0xFE, 0x7F,
- 0xFF, 0xFE, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xF8, 0x0F, 0xFF, 0xF0, 0x01,
- 0xFF, 0x80, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,
- 0x8F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF3, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,
- 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,
- 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xFF, 0x3F, 0xF1, 0xFF, 0x0F,
- 0xF0, 0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0,
- 0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00,
- 0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07,
- 0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F,
- 0xFE, 0x00, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x07, 0xFF, 0xFC, 0x3F, 0xFF,
- 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xDF, 0xFF, 0xBF, 0x9F, 0xFF, 0x7F, 0x1F,
- 0xFC, 0xFE, 0x0F, 0xE0, 0x00, 0x7F, 0x00, 0x3F, 0xBF, 0x80, 0x1F, 0x9F,
- 0xC0, 0x1F, 0xC7, 0xE0, 0x0F, 0xE3, 0xF8, 0x07, 0xE1, 0xFC, 0x07, 0xF0,
- 0x7E, 0x03, 0xF8, 0x3F, 0x81, 0xF8, 0x1F, 0xC0, 0xFC, 0x07, 0xE0, 0xFE,
- 0x03, 0xF8, 0x7E, 0x00, 0xFC, 0x3F, 0x00, 0x7E, 0x1F, 0x80, 0x3F, 0x1F,
- 0x80, 0x0F, 0xCF, 0xC0, 0x07, 0xE7, 0xE0, 0x03, 0xF7, 0xE0, 0x00, 0xFF,
- 0xF0, 0x00, 0x7F, 0xF8, 0x00, 0x3F, 0xF8, 0x00, 0x0F, 0xFC, 0x00, 0x07,
- 0xFE, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F, 0x00, 0x00,
- 0xFC, 0x03, 0xF8, 0x0F, 0xFF, 0xC0, 0x7F, 0x01, 0xFF, 0xF8, 0x0F, 0xE0,
- 0x3F, 0x3F, 0x03, 0xFE, 0x07, 0xE7, 0xE0, 0x7F, 0xC1, 0xFC, 0xFE, 0x0F,
- 0xF8, 0x3F, 0x9F, 0xC1, 0xFF, 0x07, 0xE1, 0xF8, 0x3D, 0xE0, 0xFC, 0x3F,
- 0x0F, 0xBE, 0x3F, 0x87, 0xF1, 0xF7, 0xC7, 0xE0, 0x7E, 0x3E, 0xF8, 0xFC,
- 0x0F, 0xC7, 0xDF, 0x1F, 0x81, 0xF9, 0xF1, 0xE3, 0xF0, 0x3F, 0x3E, 0x3E,
- 0xFC, 0x03, 0xF7, 0xC7, 0xDF, 0x80, 0x7E, 0xF8, 0xFB, 0xF0, 0x0F, 0xDE,
- 0x1F, 0x7C, 0x00, 0xFF, 0xC1, 0xFF, 0x80, 0x1F, 0xF8, 0x3F, 0xF0, 0x03,
- 0xFF, 0x07, 0xFE, 0x00, 0x7F, 0xC0, 0xFF, 0x80, 0x07, 0xF8, 0x1F, 0xF0,
- 0x00, 0xFF, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x3F, 0x80, 0x01, 0xFC, 0x07,
- 0xF0, 0x00, 0xFF, 0x00, 0xFF, 0x7F, 0x81, 0xFE, 0x3F, 0x81, 0xFC, 0x3F,
- 0xC3, 0xFC, 0x1F, 0xC3, 0xF8, 0x0F, 0xE7, 0xF0, 0x0F, 0xEF, 0xF0, 0x07,
- 0xFF, 0xE0, 0x03, 0xFF, 0xC0, 0x03, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x00,
- 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x01, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x03,
- 0xFF, 0xC0, 0x07, 0xFF, 0xC0, 0x07, 0xFF, 0xE0, 0x0F, 0xE7, 0xF0, 0x1F,
- 0xE7, 0xF0, 0x1F, 0xC3, 0xF8, 0x3F, 0xC3, 0xFC, 0x7F, 0x81, 0xFC, 0x7F,
- 0x01, 0xFE, 0xFF, 0x00, 0xFF, 0x7F, 0x00, 0x3F, 0xBF, 0x80, 0x1F, 0xDF,
- 0xC0, 0x0F, 0xC7, 0xF0, 0x07, 0xE3, 0xF8, 0x07, 0xF1, 0xFC, 0x03, 0xF0,
- 0x7F, 0x01, 0xF8, 0x3F, 0x81, 0xFC, 0x0F, 0xC0, 0xFC, 0x07, 0xF0, 0x7E,
- 0x03, 0xF8, 0x3F, 0x00, 0xFC, 0x3F, 0x00, 0x7E, 0x1F, 0x80, 0x3F, 0x8F,
- 0xC0, 0x0F, 0xCF, 0xC0, 0x07, 0xE7, 0xE0, 0x03, 0xFB, 0xF0, 0x00, 0xFD,
- 0xF0, 0x00, 0x7F, 0xF8, 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xFC, 0x00, 0x07,
- 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F, 0x80, 0x00,
- 0x1F, 0xC0, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00,
- 0x03, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x1F, 0xF8, 0x00, 0x0F, 0xFC, 0x00,
- 0x07, 0xFC, 0x00, 0x03, 0xFC, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x7F, 0xFF,
- 0xFB, 0xFF, 0xFF, 0xDF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xBF,
- 0xFF, 0xFC, 0x00, 0x3F, 0xE0, 0x03, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE,
- 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F,
- 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xF8, 0x01, 0xF8, 0x1F, 0xC1, 0xFE, 0x0F, 0xF0, 0xFF,
- 0x87, 0xE0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00,
- 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x3F,
- 0x0F, 0xF0, 0x7F, 0x03, 0xF8, 0x1F, 0xE0, 0x1F, 0x80, 0x7C, 0x03, 0xE0,
- 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03,
- 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xE0, 0x3F, 0xE0, 0xFF, 0x07, 0xF8, 0x1F,
- 0xC0, 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFC, 0x07, 0xF0, 0x3F, 0xC1, 0xFE, 0x0F, 0xF8, 0x0F, 0xC0, 0x3E, 0x01,
- 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E,
- 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x80, 0x7F, 0x81, 0xFC,
- 0x0F, 0xE0, 0xFF, 0x0F, 0xC0, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07,
- 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8,
- 0x0F, 0xC3, 0xFE, 0x1F, 0xE0, 0xFF, 0x07, 0xF0, 0x3F, 0x00, 0x1F, 0x00,
- 0x03, 0xFE, 0x00, 0x1F, 0xF8, 0x0F, 0xFF, 0xF0, 0xFF, 0x0F, 0xFF, 0xF0,
- 0x1F, 0xF8, 0x00, 0x7F, 0x80, 0x00, 0xF8 };
-
-const GFXglyph FreeSansBold24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 13, 0, 1 }, // 0x20 ' '
- { 0, 7, 34, 16, 5, -33 }, // 0x21 '!'
- { 30, 18, 12, 22, 2, -33 }, // 0x22 '"'
- { 57, 26, 33, 26, 0, -31 }, // 0x23 '#'
- { 165, 25, 40, 26, 1, -34 }, // 0x24 '$'
- { 290, 39, 34, 42, 1, -32 }, // 0x25 '%'
- { 456, 30, 35, 34, 3, -33 }, // 0x26 '&'
- { 588, 7, 12, 12, 3, -33 }, // 0x27 '''
- { 599, 13, 44, 16, 2, -33 }, // 0x28 '('
- { 671, 13, 44, 16, 1, -33 }, // 0x29 ')'
- { 743, 15, 15, 18, 1, -33 }, // 0x2A '*'
- { 772, 23, 22, 27, 2, -21 }, // 0x2B '+'
- { 836, 7, 15, 12, 2, -6 }, // 0x2C ','
- { 850, 13, 6, 16, 1, -15 }, // 0x2D '-'
- { 860, 7, 7, 12, 2, -6 }, // 0x2E '.'
- { 867, 13, 34, 13, 0, -32 }, // 0x2F '/'
- { 923, 24, 35, 26, 1, -33 }, // 0x30 '0'
- { 1028, 14, 33, 26, 4, -32 }, // 0x31 '1'
- { 1086, 23, 34, 26, 2, -33 }, // 0x32 '2'
- { 1184, 23, 35, 26, 2, -33 }, // 0x33 '3'
- { 1285, 22, 33, 26, 2, -32 }, // 0x34 '4'
- { 1376, 23, 34, 26, 2, -32 }, // 0x35 '5'
- { 1474, 23, 35, 26, 2, -33 }, // 0x36 '6'
- { 1575, 23, 33, 26, 1, -32 }, // 0x37 '7'
- { 1670, 24, 35, 26, 1, -33 }, // 0x38 '8'
- { 1775, 24, 35, 26, 1, -33 }, // 0x39 '9'
- { 1880, 7, 25, 12, 2, -24 }, // 0x3A ':'
- { 1902, 7, 33, 12, 2, -24 }, // 0x3B ';'
- { 1931, 23, 23, 27, 2, -22 }, // 0x3C '<'
- { 1998, 23, 18, 27, 2, -19 }, // 0x3D '='
- { 2050, 23, 23, 27, 2, -22 }, // 0x3E '>'
- { 2117, 24, 35, 29, 3, -34 }, // 0x3F '?'
- { 2222, 43, 41, 46, 1, -34 }, // 0x40 '@'
- { 2443, 32, 34, 33, 0, -33 }, // 0x41 'A'
- { 2579, 27, 34, 33, 4, -33 }, // 0x42 'B'
- { 2694, 30, 36, 34, 2, -34 }, // 0x43 'C'
- { 2829, 28, 34, 34, 4, -33 }, // 0x44 'D'
- { 2948, 25, 34, 31, 4, -33 }, // 0x45 'E'
- { 3055, 24, 34, 30, 4, -33 }, // 0x46 'F'
- { 3157, 31, 36, 36, 2, -34 }, // 0x47 'G'
- { 3297, 27, 34, 35, 4, -33 }, // 0x48 'H'
- { 3412, 7, 34, 15, 4, -33 }, // 0x49 'I'
- { 3442, 22, 35, 27, 1, -33 }, // 0x4A 'J'
- { 3539, 30, 34, 34, 4, -33 }, // 0x4B 'K'
- { 3667, 23, 34, 29, 4, -33 }, // 0x4C 'L'
- { 3765, 33, 34, 41, 4, -33 }, // 0x4D 'M'
- { 3906, 28, 34, 35, 4, -33 }, // 0x4E 'N'
- { 4025, 33, 36, 37, 2, -34 }, // 0x4F 'O'
- { 4174, 26, 34, 32, 4, -33 }, // 0x50 'P'
- { 4285, 33, 37, 37, 2, -34 }, // 0x51 'Q'
- { 4438, 28, 34, 34, 4, -33 }, // 0x52 'R'
- { 4557, 28, 36, 32, 2, -34 }, // 0x53 'S'
- { 4683, 27, 34, 30, 2, -33 }, // 0x54 'T'
- { 4798, 27, 35, 35, 4, -33 }, // 0x55 'U'
- { 4917, 29, 34, 31, 1, -33 }, // 0x56 'V'
- { 5041, 43, 34, 45, 1, -33 }, // 0x57 'W'
- { 5224, 30, 34, 32, 1, -33 }, // 0x58 'X'
- { 5352, 29, 34, 30, 1, -33 }, // 0x59 'Y'
- { 5476, 26, 34, 29, 1, -33 }, // 0x5A 'Z'
- { 5587, 11, 43, 16, 3, -33 }, // 0x5B '['
- { 5647, 14, 34, 13, -1, -32 }, // 0x5C '\'
- { 5707, 11, 43, 16, 1, -33 }, // 0x5D ']'
- { 5767, 22, 20, 27, 3, -32 }, // 0x5E '^'
- { 5822, 28, 4, 26, -1, 6 }, // 0x5F '_'
- { 5836, 9, 7, 12, 1, -35 }, // 0x60 '`'
- { 5844, 24, 26, 27, 2, -24 }, // 0x61 'a'
- { 5922, 25, 35, 29, 3, -33 }, // 0x62 'b'
- { 6032, 23, 26, 26, 2, -24 }, // 0x63 'c'
- { 6107, 25, 35, 29, 2, -33 }, // 0x64 'd'
- { 6217, 24, 26, 27, 2, -24 }, // 0x65 'e'
- { 6295, 14, 34, 16, 1, -33 }, // 0x66 'f'
- { 6355, 24, 36, 29, 2, -24 }, // 0x67 'g'
- { 6463, 23, 34, 28, 3, -33 }, // 0x68 'h'
- { 6561, 7, 34, 13, 3, -33 }, // 0x69 'i'
- { 6591, 10, 45, 13, 0, -33 }, // 0x6A 'j'
- { 6648, 23, 34, 27, 3, -33 }, // 0x6B 'k'
- { 6746, 7, 34, 13, 3, -33 }, // 0x6C 'l'
- { 6776, 36, 25, 42, 3, -24 }, // 0x6D 'm'
- { 6889, 23, 25, 29, 3, -24 }, // 0x6E 'n'
- { 6961, 25, 26, 29, 2, -24 }, // 0x6F 'o'
- { 7043, 25, 36, 29, 3, -24 }, // 0x70 'p'
- { 7156, 25, 36, 29, 2, -24 }, // 0x71 'q'
- { 7269, 15, 25, 18, 3, -24 }, // 0x72 'r'
- { 7316, 24, 26, 26, 1, -24 }, // 0x73 's'
- { 7394, 12, 32, 16, 2, -30 }, // 0x74 't'
- { 7442, 23, 26, 29, 3, -24 }, // 0x75 'u'
- { 7517, 25, 25, 25, 0, -24 }, // 0x76 'v'
- { 7596, 35, 25, 37, 1, -24 }, // 0x77 'w'
- { 7706, 24, 25, 26, 1, -24 }, // 0x78 'x'
- { 7781, 25, 36, 26, 0, -24 }, // 0x79 'y'
- { 7894, 21, 25, 24, 1, -24 }, // 0x7A 'z'
- { 7960, 13, 43, 18, 2, -33 }, // 0x7B '{'
- { 8030, 4, 44, 13, 5, -33 }, // 0x7C '|'
- { 8052, 13, 43, 18, 3, -33 }, // 0x7D '}'
- { 8122, 21, 8, 23, 1, -14 } }; // 0x7E '~'
-
-const GFXfont FreeSansBold24pt7b PROGMEM = {
- (uint8_t *)FreeSansBold24pt7bBitmaps,
- (GFXglyph *)FreeSansBold24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 8815 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold9pt7b.h
deleted file mode 100644
index aeea463..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBold9pt7b.h
+++ /dev/null
@@ -1,208 +0,0 @@
-const uint8_t FreeSansBold9pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFF, 0xFE, 0x48, 0x7E, 0xEF, 0xDF, 0xBF, 0x74, 0x40, 0x19, 0x86,
- 0x67, 0xFD, 0xFF, 0x33, 0x0C, 0xC3, 0x33, 0xFE, 0xFF, 0x99, 0x86, 0x61,
- 0x90, 0x10, 0x1F, 0x1F, 0xDE, 0xFF, 0x3F, 0x83, 0xC0, 0xFC, 0x1F, 0x09,
- 0xFC, 0xFE, 0xF7, 0xF1, 0xE0, 0x40, 0x38, 0x10, 0x7C, 0x30, 0xC6, 0x20,
- 0xC6, 0x40, 0xC6, 0x40, 0x7C, 0x80, 0x39, 0x9C, 0x01, 0x3E, 0x03, 0x63,
- 0x02, 0x63, 0x04, 0x63, 0x0C, 0x3E, 0x08, 0x1C, 0x0E, 0x01, 0xF8, 0x3B,
- 0x83, 0xB8, 0x3F, 0x01, 0xE0, 0x3E, 0x67, 0x76, 0xE3, 0xEE, 0x1C, 0xF3,
- 0xC7, 0xFE, 0x3F, 0x70, 0xFF, 0xF4, 0x18, 0x63, 0x1C, 0x73, 0x8E, 0x38,
- 0xE3, 0x8E, 0x18, 0x70, 0xC3, 0x06, 0x08, 0x61, 0x83, 0x0E, 0x38, 0x71,
- 0xC7, 0x1C, 0x71, 0xC6, 0x38, 0xE3, 0x18, 0x40, 0x21, 0x3E, 0x45, 0x28,
- 0x38, 0x70, 0xE7, 0xFF, 0xE7, 0x0E, 0x1C, 0xFC, 0x9C, 0xFF, 0xC0, 0xFC,
- 0x08, 0xC4, 0x23, 0x10, 0x84, 0x62, 0x11, 0x88, 0x00, 0x3E, 0x3F, 0x9D,
- 0xDC, 0x7E, 0x3F, 0x1F, 0x8F, 0xC7, 0xE3, 0xF1, 0xDD, 0xCF, 0xE3, 0xE0,
- 0x08, 0xFF, 0xF3, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x80, 0x3E, 0x3F, 0xB8,
- 0xFC, 0x70, 0x38, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x0F, 0xF7, 0xF8,
- 0x3C, 0x7F, 0xE7, 0xE7, 0x07, 0x0C, 0x0E, 0x07, 0x07, 0xE7, 0xE7, 0x7E,
- 0x3C, 0x0E, 0x1E, 0x1E, 0x2E, 0x2E, 0x4E, 0x4E, 0x8E, 0xFF, 0xFF, 0x0E,
- 0x0E, 0x0E, 0x7F, 0x3F, 0x90, 0x18, 0x0D, 0xE7, 0xFB, 0x9E, 0x07, 0x03,
- 0x81, 0xF1, 0xFF, 0xE7, 0xC0, 0x3E, 0x3F, 0x9C, 0xFC, 0x0E, 0xE7, 0xFB,
- 0xDF, 0xC7, 0xE3, 0xF1, 0xDD, 0xEF, 0xE3, 0xE0, 0xFF, 0xFF, 0xC0, 0xE0,
- 0xE0, 0x60, 0x70, 0x30, 0x38, 0x1C, 0x0C, 0x0E, 0x07, 0x03, 0x80, 0x3F,
- 0x1F, 0xEE, 0x3F, 0x87, 0xE3, 0xCF, 0xC7, 0xFB, 0xCF, 0xE1, 0xF8, 0x7F,
- 0x3D, 0xFE, 0x3F, 0x00, 0x3E, 0x3F, 0xBD, 0xDC, 0x7E, 0x3F, 0x1F, 0xDE,
- 0xFF, 0x3B, 0x81, 0xF9, 0xCF, 0xE3, 0xC0, 0xFC, 0x00, 0x07, 0xE0, 0xFC,
- 0x00, 0x07, 0xE5, 0xE0, 0x00, 0x83, 0xC7, 0xDF, 0x0C, 0x07, 0x80, 0xF8,
- 0x1F, 0x01, 0x80, 0xFF, 0xFF, 0xC0, 0x00, 0x0F, 0xFF, 0xFC, 0x00, 0x70,
- 0x3F, 0x03, 0xE0, 0x38, 0x7D, 0xF1, 0xE0, 0x80, 0x00, 0x3E, 0x3F, 0xB8,
- 0xFC, 0x70, 0x38, 0x1C, 0x1C, 0x1C, 0x1C, 0x0E, 0x00, 0x03, 0x81, 0xC0,
- 0x03, 0xF0, 0x0F, 0xFC, 0x1E, 0x0E, 0x38, 0x02, 0x70, 0xE9, 0x63, 0x19,
- 0xC2, 0x19, 0xC6, 0x11, 0xC6, 0x33, 0xC6, 0x32, 0x63, 0xFE, 0x73, 0xDC,
- 0x3C, 0x00, 0x1F, 0xF8, 0x07, 0xF0, 0x07, 0x00, 0xF0, 0x0F, 0x80, 0xF8,
- 0x1D, 0x81, 0x9C, 0x19, 0xC3, 0x8C, 0x3F, 0xE7, 0xFE, 0x70, 0x66, 0x07,
- 0xE0, 0x70, 0xFF, 0x9F, 0xFB, 0x83, 0xF0, 0x7E, 0x0F, 0xFF, 0x3F, 0xF7,
- 0x06, 0xE0, 0xFC, 0x1F, 0x83, 0xFF, 0xEF, 0xF8, 0x1F, 0x83, 0xFE, 0x78,
- 0xE7, 0x07, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x07, 0x07, 0x78,
- 0xF3, 0xFE, 0x1F, 0x80, 0xFF, 0x8F, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0, 0x7E,
- 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x7E, 0x0E, 0xE0, 0xEF, 0xFC, 0xFF, 0x80,
- 0xFF, 0xFF, 0xF8, 0x1C, 0x0E, 0x07, 0xFB, 0xFD, 0xC0, 0xE0, 0x70, 0x38,
- 0x1F, 0xFF, 0xF8, 0xFF, 0xFF, 0xF8, 0x1C, 0x0E, 0x07, 0xFB, 0xFD, 0xC0,
- 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x00, 0x0F, 0x87, 0xF9, 0xE3, 0xB8, 0x3E,
- 0x01, 0xC0, 0x38, 0xFF, 0x1F, 0xE0, 0x6E, 0x0D, 0xE3, 0x9F, 0xD0, 0xF2,
- 0xE0, 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xFF, 0xFF, 0xFF, 0x07, 0xE0,
- 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x07,
- 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xE7, 0xE7, 0xE7, 0x7E, 0x3C,
- 0xE0, 0xEE, 0x1C, 0xE3, 0x8E, 0x70, 0xEE, 0x0F, 0xC0, 0xFE, 0x0F, 0x70,
- 0xE7, 0x0E, 0x38, 0xE1, 0xCE, 0x0E, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
- 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0xE1,
- 0xFF, 0x87, 0xFE, 0x1F, 0xEC, 0x7F, 0xB3, 0x7E, 0xCD, 0xFB, 0x37, 0xEC,
- 0xDF, 0x9E, 0x7E, 0x79, 0xF9, 0xE7, 0xE7, 0x9C, 0xE0, 0xFE, 0x1F, 0xC3,
- 0xFC, 0x7F, 0xCF, 0xD9, 0xFB, 0xBF, 0x37, 0xE7, 0xFC, 0x7F, 0x87, 0xF0,
- 0xFE, 0x0E, 0x0F, 0x81, 0xFF, 0x1E, 0x3C, 0xE0, 0xEE, 0x03, 0xF0, 0x1F,
- 0x80, 0xFC, 0x07, 0xE0, 0x3B, 0x83, 0x9E, 0x3C, 0x7F, 0xC0, 0xF8, 0x00,
- 0xFF, 0x9F, 0xFB, 0x87, 0xF0, 0x7E, 0x0F, 0xC3, 0xFF, 0xF7, 0xFC, 0xE0,
- 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0x0F, 0x81, 0xFF, 0x1E, 0x3C, 0xE0,
- 0xEE, 0x03, 0xF0, 0x1F, 0x80, 0xFC, 0x07, 0xE1, 0xBB, 0x8F, 0x9E, 0x3C,
- 0x7F, 0xE0, 0xFB, 0x80, 0x08, 0xFF, 0x8F, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0,
- 0xEE, 0x0E, 0xFF, 0xCF, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0, 0xEE, 0x0E, 0xE0,
- 0xF0, 0x3F, 0x0F, 0xFB, 0xC7, 0xF0, 0x7E, 0x01, 0xFC, 0x1F, 0xF0, 0x3F,
- 0x00, 0xFC, 0x1D, 0xC7, 0xBF, 0xE1, 0xF8, 0xFF, 0xFF, 0xC7, 0x03, 0x81,
- 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0xFC,
- 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x07, 0xE0, 0xFC, 0x1F,
- 0xC7, 0xBF, 0xE1, 0xF0, 0x60, 0x67, 0x0E, 0x70, 0xE3, 0x0C, 0x30, 0xC3,
- 0x9C, 0x19, 0x81, 0x98, 0x1F, 0x80, 0xF0, 0x0F, 0x00, 0xF0, 0x06, 0x00,
- 0x61, 0xC3, 0xB8, 0xE1, 0x9C, 0x70, 0xCE, 0x3C, 0xE3, 0x36, 0x71, 0x9B,
- 0x30, 0xED, 0x98, 0x36, 0x7C, 0x1B, 0x3C, 0x0F, 0x1E, 0x07, 0x8F, 0x01,
- 0xC3, 0x80, 0xE1, 0x80, 0x70, 0xE7, 0x8E, 0x39, 0xC1, 0xF8, 0x1F, 0x80,
- 0xF0, 0x07, 0x00, 0xF0, 0x1F, 0x81, 0x9C, 0x39, 0xC7, 0x0E, 0x70, 0xE0,
- 0xE0, 0xFC, 0x39, 0xC7, 0x18, 0xC3, 0xB8, 0x36, 0x07, 0xC0, 0x70, 0x0E,
- 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0xFF, 0xFF, 0xC0, 0xE0, 0xE0, 0xF0,
- 0x70, 0x70, 0x70, 0x78, 0x38, 0x38, 0x1F, 0xFF, 0xF8, 0xFF, 0xEE, 0xEE,
- 0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xF0, 0x86, 0x10, 0x86, 0x10, 0x84, 0x30,
- 0x84, 0x30, 0x80, 0xFF, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7F, 0xF0,
- 0x18, 0x1C, 0x3C, 0x3E, 0x36, 0x66, 0x63, 0xC3, 0xFF, 0xC0, 0xCC, 0x3F,
- 0x1F, 0xEE, 0x38, 0x0E, 0x3F, 0x9E, 0xEE, 0x3B, 0x9E, 0xFF, 0x9E, 0xE0,
- 0xE0, 0x38, 0x0E, 0x03, 0xBC, 0xFF, 0xBC, 0xEE, 0x1F, 0x87, 0xE1, 0xF8,
- 0x7F, 0x3B, 0xFE, 0xEF, 0x00, 0x1F, 0x3F, 0xDC, 0x7C, 0x0E, 0x07, 0x03,
- 0x80, 0xE3, 0x7F, 0x8F, 0x00, 0x03, 0x81, 0xC0, 0xE7, 0x77, 0xFB, 0xBF,
- 0x8F, 0xC7, 0xE3, 0xF1, 0xFD, 0xEF, 0xF3, 0xB8, 0x3E, 0x3F, 0x9C, 0xDC,
- 0x3F, 0xFF, 0xFF, 0x81, 0xC3, 0x7F, 0x8F, 0x00, 0x3B, 0xDD, 0xFF, 0xB9,
- 0xCE, 0x73, 0x9C, 0xE7, 0x00, 0x3B, 0xBF, 0xDD, 0xFC, 0x7E, 0x3F, 0x1F,
- 0x8F, 0xEF, 0x7F, 0x9D, 0xC0, 0xFC, 0x77, 0xF1, 0xF0, 0xE0, 0x70, 0x38,
- 0x1D, 0xEF, 0xFF, 0x9F, 0x8F, 0xC7, 0xE3, 0xF1, 0xF8, 0xFC, 0x7E, 0x38,
- 0xFC, 0x7F, 0xFF, 0xFF, 0xFE, 0x77, 0x07, 0x77, 0x77, 0x77, 0x77, 0x77,
- 0x7F, 0xE0, 0xE0, 0x70, 0x38, 0x1C, 0x7E, 0x77, 0x73, 0xF1, 0xF8, 0xFE,
- 0x77, 0x39, 0xDC, 0x6E, 0x38, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xEF, 0x7B,
- 0xFF, 0xFE, 0x39, 0xF8, 0xE7, 0xE3, 0x9F, 0x8E, 0x7E, 0x39, 0xF8, 0xE7,
- 0xE3, 0x9F, 0x8E, 0x70, 0xEF, 0x7F, 0xF8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8F,
- 0xC7, 0xE3, 0xF1, 0xC0, 0x1E, 0x1F, 0xE7, 0x3B, 0x87, 0xE1, 0xF8, 0x7E,
- 0x1D, 0xCE, 0x7F, 0x87, 0x80, 0xEF, 0x3F, 0xEF, 0x3B, 0x87, 0xE1, 0xF8,
- 0x7E, 0x1F, 0xCE, 0xFF, 0xBB, 0xCE, 0x03, 0x80, 0xE0, 0x38, 0x00, 0x3B,
- 0xBF, 0xFD, 0xFC, 0x7E, 0x3F, 0x1F, 0x8F, 0xEF, 0x7F, 0x9D, 0xC0, 0xE0,
- 0x70, 0x38, 0x1C, 0xEF, 0xFF, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x80, 0x3E,
- 0x3F, 0xB8, 0xFC, 0x0F, 0xC3, 0xFC, 0x3F, 0xC7, 0xFF, 0x1F, 0x00, 0x73,
- 0xBF, 0xF7, 0x39, 0xCE, 0x73, 0x9E, 0x70, 0xE3, 0xF1, 0xF8, 0xFC, 0x7E,
- 0x3F, 0x1F, 0x8F, 0xC7, 0xFF, 0xBD, 0xC0, 0xE1, 0x98, 0x67, 0x39, 0xCC,
- 0x33, 0x0D, 0xC3, 0xE0, 0x78, 0x1E, 0x07, 0x00, 0xE3, 0x1D, 0x9E, 0x66,
- 0x79, 0x99, 0xE6, 0x77, 0xB8, 0xD2, 0xC3, 0xCF, 0x0F, 0x3C, 0x3C, 0xF0,
- 0x73, 0x80, 0x73, 0x9C, 0xE3, 0xF0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0xFC,
- 0x73, 0x9C, 0xE0, 0xE1, 0xD8, 0x67, 0x39, 0xCE, 0x33, 0x0E, 0xC3, 0xE0,
- 0x78, 0x1E, 0x03, 0x00, 0xC0, 0x70, 0x38, 0x0E, 0x00, 0xFE, 0xFE, 0x0E,
- 0x1C, 0x38, 0x38, 0x70, 0xE0, 0xFF, 0xFF, 0x37, 0x66, 0x66, 0x6E, 0xE6,
- 0x66, 0x66, 0x67, 0x30, 0xFF, 0xFF, 0x80, 0xCE, 0x66, 0x66, 0x67, 0x76,
- 0x66, 0x66, 0x6E, 0xC0, 0x71, 0x8E };
-
-const GFXglyph FreeSansBold9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 3, 13, 6, 2, -12 }, // 0x21 '!'
- { 5, 7, 5, 9, 1, -12 }, // 0x22 '"'
- { 10, 10, 12, 10, 0, -11 }, // 0x23 '#'
- { 25, 9, 15, 10, 1, -13 }, // 0x24 '$'
- { 42, 16, 13, 16, 0, -12 }, // 0x25 '%'
- { 68, 12, 13, 13, 1, -12 }, // 0x26 '&'
- { 88, 3, 5, 5, 1, -12 }, // 0x27 '''
- { 90, 6, 17, 6, 1, -12 }, // 0x28 '('
- { 103, 6, 17, 6, 0, -12 }, // 0x29 ')'
- { 116, 5, 6, 7, 1, -12 }, // 0x2A '*'
- { 120, 7, 8, 11, 2, -7 }, // 0x2B '+'
- { 127, 3, 5, 4, 1, -1 }, // 0x2C ','
- { 129, 5, 2, 6, 0, -5 }, // 0x2D '-'
- { 131, 3, 2, 4, 1, -1 }, // 0x2E '.'
- { 132, 5, 13, 5, 0, -12 }, // 0x2F '/'
- { 141, 9, 13, 10, 1, -12 }, // 0x30 '0'
- { 156, 5, 13, 10, 2, -12 }, // 0x31 '1'
- { 165, 9, 13, 10, 1, -12 }, // 0x32 '2'
- { 180, 8, 13, 10, 1, -12 }, // 0x33 '3'
- { 193, 8, 13, 10, 2, -12 }, // 0x34 '4'
- { 206, 9, 13, 10, 1, -12 }, // 0x35 '5'
- { 221, 9, 13, 10, 1, -12 }, // 0x36 '6'
- { 236, 9, 13, 10, 0, -12 }, // 0x37 '7'
- { 251, 10, 13, 10, 0, -12 }, // 0x38 '8'
- { 268, 9, 13, 10, 1, -12 }, // 0x39 '9'
- { 283, 3, 9, 4, 1, -8 }, // 0x3A ':'
- { 287, 3, 12, 4, 1, -8 }, // 0x3B ';'
- { 292, 9, 9, 11, 1, -8 }, // 0x3C '<'
- { 303, 9, 6, 11, 1, -6 }, // 0x3D '='
- { 310, 9, 9, 11, 1, -8 }, // 0x3E '>'
- { 321, 9, 13, 11, 1, -12 }, // 0x3F '?'
- { 336, 16, 15, 18, 0, -12 }, // 0x40 '@'
- { 366, 12, 13, 13, 0, -12 }, // 0x41 'A'
- { 386, 11, 13, 13, 1, -12 }, // 0x42 'B'
- { 404, 12, 13, 13, 1, -12 }, // 0x43 'C'
- { 424, 12, 13, 13, 1, -12 }, // 0x44 'D'
- { 444, 9, 13, 12, 1, -12 }, // 0x45 'E'
- { 459, 9, 13, 11, 1, -12 }, // 0x46 'F'
- { 474, 11, 13, 14, 1, -12 }, // 0x47 'G'
- { 492, 11, 13, 13, 1, -12 }, // 0x48 'H'
- { 510, 3, 13, 6, 1, -12 }, // 0x49 'I'
- { 515, 8, 13, 10, 1, -12 }, // 0x4A 'J'
- { 528, 12, 13, 13, 1, -12 }, // 0x4B 'K'
- { 548, 8, 13, 11, 1, -12 }, // 0x4C 'L'
- { 561, 14, 13, 16, 1, -12 }, // 0x4D 'M'
- { 584, 11, 13, 14, 1, -12 }, // 0x4E 'N'
- { 602, 13, 13, 14, 1, -12 }, // 0x4F 'O'
- { 624, 11, 13, 12, 1, -12 }, // 0x50 'P'
- { 642, 13, 14, 14, 1, -12 }, // 0x51 'Q'
- { 665, 12, 13, 13, 1, -12 }, // 0x52 'R'
- { 685, 11, 13, 12, 1, -12 }, // 0x53 'S'
- { 703, 9, 13, 12, 2, -12 }, // 0x54 'T'
- { 718, 11, 13, 13, 1, -12 }, // 0x55 'U'
- { 736, 12, 13, 12, 0, -12 }, // 0x56 'V'
- { 756, 17, 13, 17, 0, -12 }, // 0x57 'W'
- { 784, 12, 13, 12, 0, -12 }, // 0x58 'X'
- { 804, 11, 13, 12, 1, -12 }, // 0x59 'Y'
- { 822, 9, 13, 11, 1, -12 }, // 0x5A 'Z'
- { 837, 4, 17, 6, 1, -12 }, // 0x5B '['
- { 846, 5, 13, 5, 0, -12 }, // 0x5C '\'
- { 855, 4, 17, 6, 0, -12 }, // 0x5D ']'
- { 864, 8, 8, 11, 1, -12 }, // 0x5E '^'
- { 872, 10, 1, 10, 0, 4 }, // 0x5F '_'
- { 874, 3, 2, 5, 0, -12 }, // 0x60 '`'
- { 875, 10, 10, 10, 1, -9 }, // 0x61 'a'
- { 888, 10, 13, 11, 1, -12 }, // 0x62 'b'
- { 905, 9, 10, 10, 1, -9 }, // 0x63 'c'
- { 917, 9, 13, 11, 1, -12 }, // 0x64 'd'
- { 932, 9, 10, 10, 1, -9 }, // 0x65 'e'
- { 944, 5, 13, 6, 1, -12 }, // 0x66 'f'
- { 953, 9, 14, 11, 1, -9 }, // 0x67 'g'
- { 969, 9, 13, 11, 1, -12 }, // 0x68 'h'
- { 984, 3, 13, 5, 1, -12 }, // 0x69 'i'
- { 989, 4, 17, 5, 0, -12 }, // 0x6A 'j'
- { 998, 9, 13, 10, 1, -12 }, // 0x6B 'k'
- { 1013, 3, 13, 5, 1, -12 }, // 0x6C 'l'
- { 1018, 14, 10, 16, 1, -9 }, // 0x6D 'm'
- { 1036, 9, 10, 11, 1, -9 }, // 0x6E 'n'
- { 1048, 10, 10, 11, 1, -9 }, // 0x6F 'o'
- { 1061, 10, 14, 11, 1, -9 }, // 0x70 'p'
- { 1079, 9, 14, 11, 1, -9 }, // 0x71 'q'
- { 1095, 6, 10, 7, 1, -9 }, // 0x72 'r'
- { 1103, 9, 10, 10, 1, -9 }, // 0x73 's'
- { 1115, 5, 12, 6, 1, -11 }, // 0x74 't'
- { 1123, 9, 10, 11, 1, -9 }, // 0x75 'u'
- { 1135, 10, 10, 10, 0, -9 }, // 0x76 'v'
- { 1148, 14, 10, 14, 0, -9 }, // 0x77 'w'
- { 1166, 10, 10, 10, 0, -9 }, // 0x78 'x'
- { 1179, 10, 14, 10, 0, -9 }, // 0x79 'y'
- { 1197, 8, 10, 9, 1, -9 }, // 0x7A 'z'
- { 1207, 4, 17, 7, 1, -12 }, // 0x7B '{'
- { 1216, 1, 17, 5, 2, -12 }, // 0x7C '|'
- { 1219, 4, 17, 7, 2, -12 }, // 0x7D '}'
- { 1228, 8, 2, 9, 0, -4 } }; // 0x7E '~'
-
-const GFXfont FreeSansBold9pt7b PROGMEM = {
- (uint8_t *)FreeSansBold9pt7bBitmaps,
- (GFXglyph *)FreeSansBold9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1902 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique12pt7b.h
deleted file mode 100644
index fabbad3..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique12pt7b.h
+++ /dev/null
@@ -1,317 +0,0 @@
-const uint8_t FreeSansBoldOblique12pt7bBitmaps[] PROGMEM = {
- 0x1C, 0x3C, 0x78, 0xE1, 0xC3, 0x8F, 0x1C, 0x38, 0x70, 0xC1, 0x83, 0x00,
- 0x1C, 0x78, 0xF0, 0x71, 0xFC, 0xFE, 0x3B, 0x8E, 0xC3, 0x30, 0xC0, 0x01,
- 0x8C, 0x07, 0x38, 0x0C, 0x61, 0xFF, 0xF3, 0xFF, 0xE7, 0xFF, 0x83, 0x9C,
- 0x0E, 0x70, 0x1C, 0xE1, 0xFF, 0xF3, 0xFF, 0xC7, 0xFF, 0x83, 0x18, 0x0E,
- 0x70, 0x18, 0xC0, 0x73, 0x80, 0x00, 0x40, 0x07, 0xF0, 0x3F, 0xF0, 0xFF,
- 0xF3, 0xC9, 0xE7, 0xB3, 0xCF, 0x60, 0x1F, 0xC0, 0x3F, 0xC0, 0x3F, 0xE0,
- 0x1F, 0xE0, 0x1B, 0xE0, 0x33, 0xDE, 0x47, 0xBC, 0x8F, 0x7F, 0x7C, 0x7F,
- 0xF0, 0x7F, 0x80, 0x18, 0x00, 0x20, 0x00, 0xC0, 0x00, 0x00, 0x01, 0x87,
- 0x80, 0xC3, 0xF0, 0x61, 0xFE, 0x10, 0xE1, 0x8C, 0x30, 0x66, 0x0C, 0x3B,
- 0x03, 0xFC, 0x80, 0x7E, 0x60, 0x0F, 0x30, 0x00, 0x18, 0x70, 0x0C, 0x7E,
- 0x03, 0x1F, 0xC1, 0x8E, 0x30, 0xC3, 0x1C, 0x60, 0xFE, 0x18, 0x1F, 0x8C,
- 0x07, 0x80, 0x01, 0xE0, 0x07, 0xF0, 0x1F, 0xE0, 0x79, 0xC0, 0xF3, 0x81,
- 0xEE, 0x01, 0xF8, 0x01, 0xE0, 0x1F, 0xC6, 0x7B, 0xDD, 0xE3, 0xF7, 0x87,
- 0xEF, 0x07, 0x9F, 0x1F, 0x3F, 0xFF, 0x3F, 0xDE, 0x3F, 0x1C, 0x7F, 0xEE,
- 0xCC, 0x03, 0x83, 0x81, 0x81, 0xC1, 0xC0, 0xE0, 0xE0, 0x70, 0x70, 0x38,
- 0x3C, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x18, 0x0E, 0x07,
- 0x01, 0x80, 0x06, 0x03, 0x81, 0xC0, 0x60, 0x38, 0x1C, 0x0E, 0x07, 0x03,
- 0x81, 0xC0, 0xE0, 0xE0, 0x70, 0x38, 0x38, 0x1C, 0x1C, 0x0E, 0x0E, 0x06,
- 0x07, 0x07, 0x00, 0x0C, 0x0C, 0x4F, 0xFF, 0x1C, 0x3C, 0x6C, 0x44, 0x03,
- 0x80, 0x38, 0x07, 0x00, 0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0xF0, 0xE0, 0x0E,
- 0x00, 0xE0, 0x0C, 0x00, 0x7B, 0xDC, 0x23, 0x33, 0x00, 0x7F, 0xFF, 0xF0,
- 0x7F, 0xE0, 0x00, 0xC0, 0x30, 0x18, 0x04, 0x03, 0x00, 0x80, 0x60, 0x10,
- 0x0C, 0x02, 0x01, 0x80, 0x40, 0x30, 0x08, 0x06, 0x01, 0x00, 0xC0, 0x00,
- 0x03, 0xC0, 0x7F, 0x87, 0xFC, 0x78, 0xF3, 0xC7, 0xBC, 0x3D, 0xE1, 0xEF,
- 0x0F, 0xF0, 0x7F, 0x87, 0xBC, 0x3D, 0xE1, 0xEF, 0x1E, 0x78, 0xF3, 0xFF,
- 0x0F, 0xF0, 0x3E, 0x00, 0x03, 0x83, 0x83, 0xCF, 0xEF, 0xF0, 0x78, 0x38,
- 0x1C, 0x0E, 0x0F, 0x07, 0x03, 0x81, 0xC1, 0xE0, 0xF0, 0x70, 0x38, 0x00,
- 0x03, 0xF0, 0x0F, 0xF8, 0x7F, 0xF8, 0xF1, 0xF3, 0xC1, 0xE7, 0x83, 0xC0,
- 0x07, 0x80, 0x1E, 0x00, 0x78, 0x03, 0xE0, 0x0F, 0x00, 0x7C, 0x01, 0xE0,
- 0x07, 0x00, 0x1F, 0xFC, 0x3F, 0xF8, 0xFF, 0xF0, 0x07, 0xE0, 0xFF, 0x8F,
- 0xFE, 0xF8, 0xF7, 0x87, 0x80, 0x78, 0x0F, 0x80, 0xFC, 0x07, 0xE0, 0x0F,
- 0x80, 0x3C, 0x01, 0xEF, 0x0F, 0x78, 0xF3, 0xFF, 0x8F, 0xF8, 0x3F, 0x00,
- 0x00, 0x78, 0x07, 0xC0, 0x7E, 0x03, 0xF0, 0x37, 0x03, 0x38, 0x31, 0xC3,
- 0x9E, 0x38, 0xF1, 0x87, 0x1F, 0xFE, 0xFF, 0xF7, 0xFF, 0x80, 0xF0, 0x07,
- 0x00, 0x38, 0x03, 0xC0, 0x07, 0xFC, 0x1F, 0xF0, 0xFF, 0xC3, 0x00, 0x1C,
- 0x00, 0x7F, 0x81, 0xFF, 0x0F, 0xFE, 0x38, 0xF8, 0x01, 0xE0, 0x07, 0x80,
- 0x1E, 0xF0, 0xF3, 0xC7, 0xCF, 0xFE, 0x1F, 0xF0, 0x3F, 0x00, 0x03, 0xE0,
- 0x7F, 0x87, 0xFE, 0x78, 0xF3, 0xC0, 0x3D, 0xE1, 0xFF, 0x8F, 0xFE, 0xF8,
- 0xF7, 0xC7, 0xBC, 0x3D, 0xE1, 0xEF, 0x1E, 0x7C, 0xF3, 0xFF, 0x0F, 0xF0,
- 0x1F, 0x00, 0x7F, 0xFB, 0xFF, 0xDF, 0xFE, 0x00, 0xE0, 0x0E, 0x00, 0xE0,
- 0x0E, 0x00, 0xE0, 0x0F, 0x00, 0x70, 0x07, 0x00, 0x78, 0x03, 0x80, 0x3C,
- 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x00, 0x03, 0xF0, 0x1F, 0xE0, 0xFF, 0xC7,
- 0x8F, 0x1C, 0x3C, 0x71, 0xE0, 0xFF, 0x03, 0xF8, 0x3F, 0xF1, 0xF1, 0xE7,
- 0x87, 0xBC, 0x1E, 0xF0, 0x7B, 0xE3, 0xCF, 0xFF, 0x1F, 0xF8, 0x1F, 0x80,
- 0x03, 0xE0, 0x3F, 0xE1, 0xFF, 0x8F, 0x9F, 0x3C, 0x3D, 0xE0, 0xF7, 0x83,
- 0xDE, 0x1F, 0x78, 0xFD, 0xFF, 0xE3, 0xFF, 0x87, 0xDE, 0x00, 0xF3, 0xC7,
- 0x8F, 0xFE, 0x1F, 0xF0, 0x3F, 0x00, 0x1C, 0xF3, 0x80, 0x00, 0x00, 0x00,
- 0x01, 0xCF, 0x38, 0x0E, 0x3C, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF1,
- 0xE3, 0x81, 0x06, 0x18, 0x60, 0x00, 0x00, 0x01, 0xC0, 0x7E, 0x1F, 0xE7,
- 0xF8, 0x7E, 0x03, 0xE0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x00, 0x78, 0x00,
- 0xC0, 0x3F, 0xFC, 0xFF, 0xF3, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x07,
- 0xFF, 0x9F, 0xFC, 0x7F, 0xF0, 0x30, 0x01, 0xE0, 0x0F, 0xE0, 0x3F, 0xC0,
- 0x7F, 0x80, 0x7C, 0x07, 0xE1, 0xFE, 0x7F, 0x87, 0xE0, 0x38, 0x00, 0x00,
- 0x00, 0x0F, 0xC1, 0xFF, 0x8F, 0xFC, 0xF1, 0xFF, 0x07, 0xF0, 0x3C, 0x01,
- 0xE0, 0x1E, 0x01, 0xE0, 0x3E, 0x03, 0xE0, 0x1C, 0x01, 0xC0, 0x0E, 0x00,
- 0x00, 0x07, 0x80, 0x3C, 0x01, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x03, 0xFF,
- 0x80, 0x3C, 0x0F, 0x01, 0xC0, 0x0E, 0x0E, 0x00, 0x1C, 0x70, 0xF7, 0x73,
- 0x87, 0xF8, 0xCC, 0x31, 0xE3, 0x61, 0x87, 0x0D, 0x8C, 0x1C, 0x3C, 0x30,
- 0x61, 0xB1, 0x81, 0x86, 0xC6, 0x0C, 0x3B, 0x18, 0x71, 0xCC, 0x63, 0xCE,
- 0x31, 0xFB, 0xF0, 0xE3, 0xCF, 0x01, 0xC0, 0x00, 0x03, 0xC0, 0xC0, 0x07,
- 0xFF, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x3F, 0x00, 0x1F, 0x80,
- 0x1F, 0xC0, 0x0F, 0xE0, 0x0F, 0xF0, 0x07, 0x7C, 0x07, 0x1E, 0x03, 0x8F,
- 0x03, 0x87, 0x83, 0xC3, 0xC1, 0xFF, 0xE1, 0xFF, 0xF0, 0xFF, 0xFC, 0xF0,
- 0x1E, 0x70, 0x0F, 0x78, 0x07, 0xB8, 0x03, 0xC0, 0x0F, 0xFE, 0x0F, 0xFF,
- 0x87, 0xFF, 0xE3, 0xC0, 0xF1, 0xC0, 0x78, 0xE0, 0x3C, 0xF0, 0x3C, 0x7F,
- 0xFC, 0x3F, 0xFC, 0x1F, 0xFF, 0x0E, 0x07, 0xCF, 0x01, 0xE7, 0x80, 0xF3,
- 0x80, 0x79, 0xC0, 0x79, 0xFF, 0xF8, 0xFF, 0xFC, 0x7F, 0xF8, 0x00, 0x01,
- 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE1, 0xF3, 0xC0, 0x79, 0xE0, 0x3D,
- 0xE0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E, 0x00,
- 0x0F, 0x00, 0xE7, 0x80, 0xF3, 0xE0, 0xF0, 0xFF, 0xF8, 0x3F, 0xF0, 0x07,
- 0xE0, 0x00, 0x1F, 0xFC, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0x81, 0xF1, 0xC0,
- 0x79, 0xE0, 0x3C, 0xF0, 0x1E, 0x78, 0x0F, 0x38, 0x07, 0x9C, 0x03, 0xDE,
- 0x03, 0xCF, 0x01, 0xE7, 0x81, 0xF3, 0x80, 0xF1, 0xC1, 0xF1, 0xFF, 0xF0,
- 0xFF, 0xF0, 0x7F, 0xE0, 0x00, 0x0F, 0xFF, 0x1F, 0xFF, 0x1F, 0xFF, 0x1C,
- 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F,
- 0xFC, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0xFF,
- 0xF8, 0xFF, 0xF8, 0xFF, 0xF8, 0x1F, 0xFF, 0x1F, 0xFE, 0x1F, 0xFE, 0x1C,
- 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0xF8, 0x3F, 0xF8, 0x3F,
- 0xF8, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xF0,
- 0x00, 0xF0, 0x00, 0xE0, 0x00, 0x01, 0xFC, 0x03, 0xFF, 0x03, 0xFF, 0xC3,
- 0xE0, 0xF3, 0xC0, 0x39, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0xF0, 0x7F,
- 0x78, 0x3F, 0xBC, 0x1F, 0xDE, 0x01, 0xCF, 0x00, 0xE7, 0xC0, 0xF1, 0xF0,
- 0xF8, 0xFF, 0xFC, 0x3F, 0xEC, 0x07, 0xE6, 0x00, 0x1E, 0x03, 0x8F, 0x01,
- 0xC7, 0x01, 0xE3, 0x80, 0xF3, 0xC0, 0x79, 0xE0, 0x38, 0xF0, 0x1C, 0x7F,
- 0xFE, 0x3F, 0xFF, 0x3F, 0xFF, 0x9E, 0x03, 0x8F, 0x01, 0xC7, 0x01, 0xE3,
- 0x80, 0xF3, 0xC0, 0x71, 0xE0, 0x38, 0xF0, 0x3C, 0x70, 0x1E, 0x00, 0x1E,
- 0x3C, 0x78, 0xE1, 0xC7, 0x8F, 0x1E, 0x38, 0x71, 0xE3, 0xC7, 0x8E, 0x1C,
- 0x78, 0xF1, 0xE0, 0x00, 0x1C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x38,
- 0x00, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xC0, 0x07, 0x3C, 0x3C,
- 0xF0, 0xF3, 0xC3, 0x8F, 0x1E, 0x3F, 0xF8, 0x7F, 0xC0, 0xFC, 0x00, 0x1E,
- 0x07, 0xC7, 0x83, 0xE1, 0xE1, 0xE0, 0x70, 0xF0, 0x1C, 0x78, 0x0F, 0x3C,
- 0x03, 0xDE, 0x00, 0xFF, 0x00, 0x3F, 0xC0, 0x0F, 0xF0, 0x07, 0xDE, 0x01,
- 0xE7, 0xC0, 0x78, 0xF0, 0x1C, 0x3E, 0x0F, 0x07, 0x83, 0xC0, 0xF0, 0xF0,
- 0x3C, 0x38, 0x07, 0x80, 0x0E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xC0,
- 0x0E, 0x00, 0xF0, 0x07, 0x80, 0x38, 0x01, 0xC0, 0x1E, 0x00, 0xF0, 0x07,
- 0x80, 0x38, 0x01, 0xC0, 0x1F, 0xFE, 0xFF, 0xF7, 0xFF, 0x80, 0x1F, 0x03,
- 0xF1, 0xF0, 0x3F, 0x1F, 0x07, 0xF1, 0xF0, 0x7F, 0x3F, 0x0F, 0xE3, 0xF0,
- 0xEE, 0x3B, 0x1E, 0xE3, 0xB1, 0xDE, 0x3B, 0x1D, 0xE7, 0xB3, 0x9C, 0x7B,
- 0x39, 0xC7, 0x37, 0x9C, 0x73, 0x73, 0xCF, 0x3F, 0x3C, 0xF3, 0xE3, 0x8F,
- 0x3E, 0x38, 0xE3, 0xC3, 0x8E, 0x3C, 0x78, 0x1E, 0x03, 0x87, 0xC0, 0xE1,
- 0xF0, 0x38, 0x7C, 0x1E, 0x1F, 0x87, 0x8F, 0xE1, 0xC3, 0xB8, 0x70, 0xEF,
- 0x1C, 0x39, 0xCF, 0x1E, 0x73, 0xC7, 0x8E, 0xE1, 0xC3, 0xB8, 0x70, 0xEE,
- 0x1C, 0x1F, 0x8F, 0x07, 0xE3, 0xC1, 0xF0, 0xE0, 0x3C, 0x38, 0x0F, 0x00,
- 0x01, 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE3, 0xE3, 0xC0, 0xF9, 0xE0,
- 0x3D, 0xE0, 0x1E, 0xF0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x03, 0xDE,
- 0x01, 0xEF, 0x00, 0xF7, 0xC0, 0xF1, 0xF0, 0xF0, 0xFF, 0xF0, 0x3F, 0xF0,
- 0x07, 0xE0, 0x00, 0x1F, 0xFC, 0x1F, 0xFE, 0x1F, 0xFF, 0x1C, 0x1F, 0x1C,
- 0x0F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C, 0x1E, 0x3F, 0xFC, 0x3F, 0xFC, 0x7F,
- 0xF0, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xF0,
- 0x00, 0xF0, 0x00, 0x01, 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE3, 0xE3,
- 0xC0, 0xF9, 0xC0, 0x3D, 0xE0, 0x1E, 0xF0, 0x0F, 0xF0, 0x07, 0xF8, 0x03,
- 0xFC, 0x03, 0xDE, 0x09, 0xEF, 0x0E, 0xE7, 0xC7, 0xF1, 0xF1, 0xF0, 0xFF,
- 0xF8, 0x3F, 0xFE, 0x07, 0xE6, 0x00, 0x02, 0x00, 0x0F, 0xFE, 0x0F, 0xFF,
- 0x87, 0xFF, 0xE3, 0x81, 0xF1, 0xC0, 0x78, 0xE0, 0x3C, 0xF0, 0x1C, 0x78,
- 0x1E, 0x3F, 0xFC, 0x1F, 0xFC, 0x1F, 0xFF, 0x8F, 0x03, 0xC7, 0x81, 0xE3,
- 0x80, 0xF1, 0xC0, 0xF1, 0xE0, 0x78, 0xF0, 0x3C, 0x78, 0x1F, 0x00, 0x03,
- 0xF8, 0x0F, 0xFE, 0x1F, 0xFF, 0x1E, 0x1F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C,
- 0x00, 0x3F, 0x00, 0x1F, 0xF0, 0x0F, 0xFC, 0x01, 0xFE, 0x00, 0x3E, 0xF0,
- 0x1E, 0xF0, 0x1E, 0xF8, 0x3C, 0x7F, 0xF8, 0x7F, 0xF0, 0x1F, 0xC0, 0x7F,
- 0xFE, 0xFF, 0xFD, 0xFF, 0xF8, 0x1C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0,
- 0x03, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xE0, 0x01,
- 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38, 0x00, 0x1E, 0x07, 0x1C,
- 0x0F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C, 0x0E, 0x38, 0x0E, 0x78, 0x1E, 0x78,
- 0x1E, 0x78, 0x1E, 0x78, 0x1C, 0x70, 0x1C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0,
- 0x38, 0xF8, 0x78, 0xFF, 0xF0, 0x7F, 0xE0, 0x1F, 0x80, 0xF0, 0x1F, 0xE0,
- 0x39, 0xC0, 0xF3, 0x81, 0xC7, 0x07, 0x8E, 0x0E, 0x1C, 0x3C, 0x3C, 0x70,
- 0x79, 0xE0, 0xF3, 0x80, 0xEF, 0x01, 0xDC, 0x03, 0xB8, 0x07, 0xE0, 0x0F,
- 0x80, 0x1F, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x70, 0x7F, 0x87, 0x83,
- 0xFC, 0x3C, 0x3D, 0xE1, 0xE1, 0xEF, 0x1F, 0x0E, 0x78, 0xD8, 0xF3, 0xC6,
- 0xC7, 0x0E, 0x76, 0x78, 0x73, 0x33, 0x83, 0xB9, 0x9C, 0x1D, 0xCD, 0xC0,
- 0xEC, 0x6E, 0x07, 0xE3, 0xE0, 0x3E, 0x1F, 0x01, 0xF0, 0xF0, 0x0F, 0x87,
- 0x80, 0x78, 0x38, 0x03, 0xC1, 0xC0, 0x00, 0x0F, 0x03, 0xC3, 0xC1, 0xE0,
- 0xF8, 0xF0, 0x1E, 0x78, 0x07, 0x9E, 0x00, 0xFF, 0x00, 0x3F, 0x80, 0x0F,
- 0xC0, 0x01, 0xE0, 0x00, 0xF8, 0x00, 0x3F, 0x00, 0x1F, 0xC0, 0x0F, 0xF0,
- 0x07, 0x9E, 0x03, 0xC7, 0x80, 0xF0, 0xF0, 0x78, 0x3C, 0x3C, 0x0F, 0x80,
- 0x78, 0x1E, 0xF0, 0x79, 0xE0, 0xF3, 0xC3, 0xC3, 0xCF, 0x07, 0x9E, 0x0F,
- 0x78, 0x0F, 0xE0, 0x1F, 0x80, 0x3F, 0x00, 0x3C, 0x00, 0x70, 0x00, 0xE0,
- 0x03, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x1F, 0xFF,
- 0x0F, 0xFF, 0x87, 0xFF, 0xC0, 0x03, 0xC0, 0x03, 0xE0, 0x03, 0xE0, 0x03,
- 0xE0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01,
- 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xFF, 0xF0, 0xFF, 0xF8, 0x7F, 0xFC,
- 0x00, 0x0F, 0xC3, 0xF0, 0xFC, 0x38, 0x1E, 0x07, 0x01, 0xC0, 0x70, 0x1C,
- 0x0F, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F,
- 0x03, 0x80, 0xFC, 0x3F, 0x0F, 0xC0, 0x08, 0x88, 0xC4, 0x44, 0x66, 0x66,
- 0x66, 0x62, 0x22, 0x33, 0x33, 0x30, 0x0F, 0xC3, 0xF0, 0xFC, 0x07, 0x03,
- 0xC0, 0xE0, 0x38, 0x0E, 0x03, 0x81, 0xC0, 0x70, 0x1C, 0x07, 0x03, 0xC0,
- 0xE0, 0x38, 0x0E, 0x03, 0x81, 0xE0, 0x70, 0xFC, 0x3F, 0x0F, 0xC0, 0x03,
- 0x80, 0xF0, 0x1E, 0x07, 0xE1, 0xDC, 0x3B, 0x8E, 0x71, 0x86, 0x70, 0xFC,
- 0x1F, 0x83, 0x80, 0x7F, 0xFE, 0xFF, 0xFC, 0xE6, 0x30, 0x07, 0xE0, 0xFF,
- 0x8F, 0xFE, 0x70, 0xE0, 0x07, 0x03, 0xF8, 0xFF, 0xCF, 0x9E, 0xF0, 0xF7,
- 0x8F, 0x3F, 0xF8, 0xFF, 0xC3, 0xDF, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38,
- 0x00, 0xF0, 0x01, 0xE0, 0x03, 0x9F, 0x07, 0xFF, 0x0F, 0xFF, 0x3E, 0x3E,
- 0x78, 0x3C, 0xF0, 0x79, 0xC0, 0xF3, 0x81, 0xEF, 0x07, 0x9F, 0x1F, 0x3F,
- 0xFC, 0x7F, 0xF0, 0xEF, 0x80, 0x07, 0xC0, 0xFF, 0x8F, 0xFE, 0xF8, 0xF7,
- 0x87, 0xB8, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0xF7, 0x8F, 0x1F, 0xF8, 0xFF,
- 0x81, 0xF0, 0x00, 0x00, 0x1E, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x03,
- 0xC0, 0xF7, 0x87, 0xFE, 0x1F, 0xFC, 0x7C, 0x78, 0xF0, 0x73, 0xC0, 0xE7,
- 0x81, 0x8F, 0x07, 0x1E, 0x0E, 0x3E, 0x3C, 0x7F, 0xF8, 0x7F, 0xE0, 0x7D,
- 0xC0, 0x07, 0xC0, 0xFF, 0x8F, 0xFE, 0xF0, 0xF7, 0x87, 0xFF, 0xFF, 0xFF,
- 0xFE, 0x00, 0xF0, 0x07, 0xC7, 0x9F, 0xF8, 0xFF, 0x81, 0xF0, 0x00, 0x07,
- 0x87, 0xC7, 0xE3, 0xC1, 0xC3, 0xF9, 0xFC, 0x78, 0x3C, 0x1C, 0x0E, 0x07,
- 0x07, 0x83, 0x81, 0xC0, 0xE0, 0xF0, 0x78, 0x00, 0x03, 0xDE, 0x1F, 0xF8,
- 0x7F, 0xF1, 0xF1, 0xE3, 0xC1, 0xCF, 0x03, 0x9E, 0x06, 0x3C, 0x0C, 0x78,
- 0x38, 0xF8, 0xF1, 0xFF, 0xC1, 0xFF, 0x81, 0xF7, 0x00, 0x0E, 0x3C, 0x3C,
- 0x78, 0xF0, 0x7F, 0xC0, 0x7E, 0x00, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x07,
- 0x00, 0x3C, 0x00, 0xF7, 0xC3, 0xBF, 0x8F, 0xFF, 0x3C, 0x3D, 0xE0, 0xE7,
- 0x83, 0x9C, 0x0E, 0x70, 0x79, 0xC1, 0xEF, 0x07, 0x3C, 0x1C, 0xE0, 0x73,
- 0x83, 0xC0, 0x0E, 0x3C, 0x70, 0x00, 0x03, 0x8F, 0x1E, 0x38, 0x71, 0xE3,
- 0xC7, 0x0E, 0x1C, 0x78, 0xF1, 0xC0, 0x03, 0xC0, 0xE0, 0x38, 0x00, 0x00,
- 0x01, 0xE0, 0x70, 0x1C, 0x07, 0x03, 0xC0, 0xF0, 0x38, 0x0E, 0x03, 0x81,
- 0xE0, 0x70, 0x1C, 0x07, 0x03, 0xC0, 0xF0, 0xF8, 0x3E, 0x0F, 0x00, 0x0E,
- 0x00, 0x1C, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0x87, 0x87, 0x1E,
- 0x0E, 0x78, 0x3D, 0xE0, 0x7F, 0x80, 0xFE, 0x01, 0xFE, 0x03, 0xFC, 0x0F,
- 0x38, 0x1E, 0x78, 0x38, 0xF0, 0x70, 0xF0, 0xE1, 0xE0, 0x0E, 0x3C, 0x78,
- 0xE1, 0xC3, 0x8F, 0x1E, 0x38, 0x71, 0xE3, 0xC7, 0x0E, 0x1C, 0x78, 0xF1,
- 0xC0, 0x1C, 0xF1, 0xE0, 0xEF, 0xDF, 0x87, 0xFF, 0xFE, 0x7C, 0x78, 0xF3,
- 0xC3, 0x87, 0x9C, 0x1C, 0x38, 0xE1, 0xE1, 0xC7, 0x0E, 0x0E, 0x78, 0x70,
- 0xF3, 0xC3, 0x87, 0x9C, 0x3C, 0x38, 0xE1, 0xE1, 0xC7, 0x0E, 0x0E, 0x00,
- 0x3D, 0xF0, 0xEF, 0xE3, 0xFF, 0xCF, 0x0F, 0x78, 0x39, 0xC0, 0xE7, 0x03,
- 0x9C, 0x1E, 0xF0, 0x7B, 0xC1, 0xCE, 0x07, 0x38, 0x1C, 0xE0, 0xF0, 0x07,
- 0xE0, 0x7F, 0xE3, 0xFF, 0x9F, 0x1F, 0x78, 0x3F, 0xC0, 0xFF, 0x03, 0xFC,
- 0x1F, 0xF0, 0x7B, 0xE3, 0xE7, 0xFF, 0x1F, 0xF8, 0x1F, 0x80, 0x0E, 0x7C,
- 0x0F, 0xFE, 0x0F, 0xFF, 0x1F, 0x1F, 0x1E, 0x0F, 0x1E, 0x0F, 0x1C, 0x0F,
- 0x1C, 0x0F, 0x3C, 0x1E, 0x3E, 0x3E, 0x3F, 0xFC, 0x3F, 0xF8, 0x7B, 0xE0,
- 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0x70, 0x00, 0xF0, 0x00, 0x07, 0xBC,
- 0x7F, 0xF3, 0xFF, 0x9F, 0x1E, 0x78, 0x3B, 0xC0, 0xEF, 0x03, 0x3C, 0x0C,
- 0xF0, 0x73, 0xE3, 0xCF, 0xFF, 0x1F, 0xF8, 0x3C, 0xE0, 0x03, 0x80, 0x1E,
- 0x00, 0x78, 0x01, 0xC0, 0x07, 0x00, 0x3D, 0xCE, 0xE3, 0xF8, 0xF0, 0x78,
- 0x1E, 0x07, 0x01, 0xC0, 0xF0, 0x3C, 0x0E, 0x03, 0x80, 0xE0, 0x00, 0x1F,
- 0xC3, 0xFE, 0x7F, 0xFF, 0x0F, 0xF0, 0x0F, 0xE0, 0x7F, 0xC1, 0xFE, 0x03,
- 0xEE, 0x1E, 0xFF, 0xC7, 0xFC, 0x3F, 0x00, 0x1E, 0x1E, 0x1C, 0x7F, 0xFF,
- 0x3C, 0x38, 0x38, 0x38, 0x78, 0x78, 0x70, 0x7C, 0xF8, 0x78, 0x38, 0x3C,
- 0xE0, 0xE3, 0x83, 0x9E, 0x0E, 0x70, 0x79, 0xC1, 0xE7, 0x07, 0x3C, 0x1C,
- 0xF0, 0xF3, 0xE7, 0xCF, 0xFF, 0x1F, 0xF8, 0x3C, 0xE0, 0xF0, 0x77, 0x87,
- 0xBC, 0x38, 0xE3, 0xC7, 0x1C, 0x39, 0xE1, 0xCE, 0x0E, 0xE0, 0x77, 0x03,
- 0xF0, 0x0F, 0x80, 0x78, 0x03, 0xC0, 0x00, 0xF1, 0xC3, 0xF8, 0xE3, 0xFC,
- 0xF1, 0xDE, 0x79, 0xEF, 0x3C, 0xE7, 0xB6, 0x73, 0xDB, 0x70, 0xED, 0xB8,
- 0x7C, 0xF8, 0x3E, 0x7C, 0x1F, 0x3C, 0x0F, 0x1E, 0x07, 0x8E, 0x00, 0x0F,
- 0x1E, 0x0F, 0x3C, 0x0F, 0x38, 0x07, 0x70, 0x07, 0xF0, 0x03, 0xE0, 0x03,
- 0xC0, 0x07, 0xC0, 0x0F, 0xE0, 0x1E, 0xE0, 0x3C, 0xF0, 0x3C, 0xF0, 0x78,
- 0x78, 0x3C, 0x1C, 0x78, 0x78, 0xF0, 0xE1, 0xE3, 0xC1, 0xC7, 0x03, 0x9E,
- 0x07, 0x38, 0x0E, 0xE0, 0x1D, 0xC0, 0x3F, 0x00, 0x7E, 0x00, 0x78, 0x00,
- 0xF0, 0x01, 0xC0, 0x07, 0x00, 0x7E, 0x00, 0xF8, 0x01, 0xE0, 0x00, 0x1F,
- 0xF9, 0xFF, 0xCF, 0xFC, 0x01, 0xE0, 0x3E, 0x03, 0xC0, 0x3C, 0x03, 0xC0,
- 0x3C, 0x03, 0xC0, 0x3F, 0xF9, 0xFF, 0xCF, 0xFC, 0x00, 0x07, 0x87, 0xC3,
- 0xE3, 0xC1, 0xC0, 0xE0, 0x70, 0x38, 0x3C, 0x1C, 0x0E, 0x1E, 0x0F, 0x03,
- 0x81, 0xC0, 0xE0, 0x70, 0x78, 0x38, 0x1C, 0x0F, 0x87, 0xC1, 0xC0, 0x0C,
- 0x30, 0x86, 0x18, 0x61, 0x8C, 0x30, 0xC3, 0x0C, 0x61, 0x86, 0x18, 0x63,
- 0x0C, 0x30, 0xC2, 0x00, 0x00, 0x07, 0x07, 0xC3, 0xE0, 0x70, 0x38, 0x3C,
- 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xE0, 0xF0, 0xE0, 0x70, 0x78, 0x38, 0x1C,
- 0x0E, 0x07, 0x07, 0x8F, 0x87, 0xC3, 0xC0, 0x3C, 0x07, 0xE0, 0xC7, 0x30,
- 0x7E, 0x01, 0xC0 };
-
-const GFXglyph FreeSansBoldOblique12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 7, 0, 1 }, // 0x20 ' '
- { 0, 7, 17, 8, 3, -16 }, // 0x21 '!'
- { 15, 10, 6, 11, 4, -17 }, // 0x22 '"'
- { 23, 15, 16, 13, 1, -15 }, // 0x23 '#'
- { 53, 15, 21, 13, 1, -17 }, // 0x24 '$'
- { 93, 18, 18, 21, 3, -17 }, // 0x25 '%'
- { 134, 15, 17, 17, 2, -16 }, // 0x26 '&'
- { 166, 4, 6, 6, 4, -17 }, // 0x27 '''
- { 169, 9, 22, 8, 2, -17 }, // 0x28 '('
- { 194, 9, 22, 8, -1, -16 }, // 0x29 ')'
- { 219, 8, 8, 9, 3, -17 }, // 0x2A '*'
- { 227, 12, 11, 14, 2, -10 }, // 0x2B '+'
- { 244, 5, 7, 7, 1, -2 }, // 0x2C ','
- { 249, 7, 3, 8, 2, -7 }, // 0x2D '-'
- { 252, 4, 3, 7, 2, -2 }, // 0x2E '.'
- { 254, 10, 17, 7, 0, -16 }, // 0x2F '/'
- { 276, 13, 17, 13, 2, -16 }, // 0x30 '0'
- { 304, 9, 17, 13, 4, -16 }, // 0x31 '1'
- { 324, 15, 17, 13, 1, -16 }, // 0x32 '2'
- { 356, 13, 17, 13, 2, -16 }, // 0x33 '3'
- { 384, 13, 17, 13, 1, -16 }, // 0x34 '4'
- { 412, 14, 17, 13, 1, -16 }, // 0x35 '5'
- { 442, 13, 17, 13, 2, -16 }, // 0x36 '6'
- { 470, 13, 17, 13, 3, -16 }, // 0x37 '7'
- { 498, 14, 17, 13, 1, -16 }, // 0x38 '8'
- { 528, 14, 17, 13, 2, -16 }, // 0x39 '9'
- { 558, 6, 12, 8, 3, -11 }, // 0x3A ':'
- { 567, 7, 16, 8, 2, -11 }, // 0x3B ';'
- { 581, 13, 12, 14, 2, -11 }, // 0x3C '<'
- { 601, 14, 9, 14, 1, -9 }, // 0x3D '='
- { 617, 13, 12, 14, 1, -10 }, // 0x3E '>'
- { 637, 13, 18, 15, 4, -17 }, // 0x3F '?'
- { 667, 22, 21, 23, 2, -17 }, // 0x40 '@'
- { 725, 17, 18, 17, 0, -17 }, // 0x41 'A'
- { 764, 17, 18, 17, 2, -17 }, // 0x42 'B'
- { 803, 17, 18, 17, 3, -17 }, // 0x43 'C'
- { 842, 17, 18, 17, 2, -17 }, // 0x44 'D'
- { 881, 16, 18, 16, 2, -17 }, // 0x45 'E'
- { 917, 16, 18, 15, 2, -17 }, // 0x46 'F'
- { 953, 17, 18, 19, 3, -17 }, // 0x47 'G'
- { 992, 17, 18, 17, 2, -17 }, // 0x48 'H'
- { 1031, 7, 18, 7, 2, -17 }, // 0x49 'I'
- { 1047, 14, 18, 13, 1, -17 }, // 0x4A 'J'
- { 1079, 18, 18, 17, 2, -17 }, // 0x4B 'K'
- { 1120, 13, 18, 15, 2, -17 }, // 0x4C 'L'
- { 1150, 20, 18, 20, 2, -17 }, // 0x4D 'M'
- { 1195, 18, 18, 17, 2, -17 }, // 0x4E 'N'
- { 1236, 17, 18, 19, 3, -17 }, // 0x4F 'O'
- { 1275, 16, 18, 16, 2, -17 }, // 0x50 'P'
- { 1311, 17, 19, 19, 3, -17 }, // 0x51 'Q'
- { 1352, 17, 18, 17, 2, -17 }, // 0x52 'R'
- { 1391, 16, 18, 16, 2, -17 }, // 0x53 'S'
- { 1427, 15, 18, 15, 3, -17 }, // 0x54 'T'
- { 1461, 16, 18, 17, 3, -17 }, // 0x55 'U'
- { 1497, 15, 18, 16, 4, -17 }, // 0x56 'V'
- { 1531, 21, 18, 23, 4, -17 }, // 0x57 'W'
- { 1579, 18, 18, 16, 1, -17 }, // 0x58 'X'
- { 1620, 15, 18, 16, 4, -17 }, // 0x59 'Y'
- { 1654, 17, 18, 15, 1, -17 }, // 0x5A 'Z'
- { 1693, 10, 23, 8, 1, -17 }, // 0x5B '['
- { 1722, 4, 23, 7, 3, -22 }, // 0x5C '\'
- { 1734, 10, 23, 8, 0, -17 }, // 0x5D ']'
- { 1763, 11, 11, 14, 3, -16 }, // 0x5E '^'
- { 1779, 15, 2, 13, -2, 4 }, // 0x5F '_'
- { 1783, 4, 3, 8, 4, -17 }, // 0x60 '`'
- { 1785, 13, 13, 13, 1, -12 }, // 0x61 'a'
- { 1807, 15, 18, 15, 1, -17 }, // 0x62 'b'
- { 1841, 13, 13, 13, 2, -12 }, // 0x63 'c'
- { 1863, 15, 18, 15, 2, -17 }, // 0x64 'd'
- { 1897, 13, 13, 13, 2, -12 }, // 0x65 'e'
- { 1919, 9, 18, 8, 2, -17 }, // 0x66 'f'
- { 1940, 15, 18, 15, 1, -12 }, // 0x67 'g'
- { 1974, 14, 18, 15, 2, -17 }, // 0x68 'h'
- { 2006, 7, 18, 7, 2, -17 }, // 0x69 'i'
- { 2022, 10, 23, 7, -1, -17 }, // 0x6A 'j'
- { 2051, 15, 18, 13, 1, -17 }, // 0x6B 'k'
- { 2085, 7, 18, 7, 2, -17 }, // 0x6C 'l'
- { 2101, 21, 13, 21, 1, -12 }, // 0x6D 'm'
- { 2136, 14, 13, 15, 2, -12 }, // 0x6E 'n'
- { 2159, 14, 13, 15, 2, -12 }, // 0x6F 'o'
- { 2182, 16, 18, 15, 0, -12 }, // 0x70 'p'
- { 2218, 14, 18, 15, 2, -12 }, // 0x71 'q'
- { 2250, 10, 13, 9, 2, -12 }, // 0x72 'r'
- { 2267, 12, 13, 13, 3, -12 }, // 0x73 's'
- { 2287, 8, 15, 8, 2, -14 }, // 0x74 't'
- { 2302, 14, 13, 15, 2, -12 }, // 0x75 'u'
- { 2325, 13, 13, 13, 3, -12 }, // 0x76 'v'
- { 2347, 17, 13, 19, 3, -12 }, // 0x77 'w'
- { 2375, 16, 13, 13, 0, -12 }, // 0x78 'x'
- { 2401, 15, 18, 13, 1, -12 }, // 0x79 'y'
- { 2435, 13, 13, 12, 1, -12 }, // 0x7A 'z'
- { 2457, 9, 23, 9, 3, -17 }, // 0x7B '{'
- { 2483, 6, 23, 7, 1, -17 }, // 0x7C '|'
- { 2501, 9, 23, 9, 0, -17 }, // 0x7D '}'
- { 2527, 12, 5, 14, 2, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSansBoldOblique12pt7b PROGMEM = {
- (uint8_t *)FreeSansBoldOblique12pt7bBitmaps,
- (GFXglyph *)FreeSansBoldOblique12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 3207 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique18pt7b.h
deleted file mode 100644
index 79c748c..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique18pt7b.h
+++ /dev/null
@@ -1,545 +0,0 @@
-const uint8_t FreeSansBoldOblique18pt7bBitmaps[] PROGMEM = {
- 0x06, 0x01, 0xC0, 0x7C, 0x1F, 0x0F, 0xC3, 0xE0, 0xF8, 0x3E, 0x0F, 0x83,
- 0xC0, 0xF0, 0x7C, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1C, 0x07, 0x01, 0xC0,
- 0x60, 0x7C, 0x1F, 0x07, 0xC3, 0xF0, 0xF8, 0x00, 0x78, 0x7B, 0xC3, 0xFE,
- 0x3F, 0xE1, 0xEF, 0x0F, 0x78, 0x7B, 0x83, 0x9C, 0x1C, 0xC0, 0xC0, 0x00,
- 0x3C, 0x38, 0x00, 0xF1, 0xE0, 0x07, 0x87, 0x00, 0x1E, 0x3C, 0x00, 0xF0,
- 0xE0, 0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0x1F, 0xFF, 0xF8,
- 0x0F, 0x0E, 0x00, 0x3C, 0x78, 0x00, 0xE1, 0xE0, 0x07, 0x8F, 0x00, 0x1C,
- 0x3C, 0x07, 0xFF, 0xFE, 0x1F, 0xFF, 0xF8, 0x7F, 0xFF, 0xE3, 0xFF, 0xFF,
- 0x01, 0xE3, 0xC0, 0x0F, 0x0E, 0x00, 0x3C, 0x78, 0x01, 0xE1, 0xC0, 0x07,
- 0x8F, 0x00, 0x3C, 0x38, 0x00, 0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0xFC,
- 0x00, 0xFF, 0xC0, 0x3F, 0xFC, 0x0F, 0xFF, 0xC3, 0xE6, 0x78, 0x78, 0xCF,
- 0x1E, 0x39, 0xE3, 0xC7, 0x3C, 0x78, 0xC0, 0x0F, 0x98, 0x01, 0xFF, 0x00,
- 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x00, 0x7F, 0x80, 0x0F, 0xF0,
- 0x03, 0xBE, 0x00, 0x67, 0xCF, 0x8C, 0xF9, 0xF1, 0x9F, 0x3E, 0x77, 0xC7,
- 0xEF, 0xF8, 0x7F, 0xFE, 0x0F, 0xFF, 0x80, 0xFF, 0xE0, 0x03, 0xE0, 0x00,
- 0x38, 0x00, 0x06, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x07, 0x01, 0xE0,
- 0x03, 0x81, 0xFE, 0x00, 0xC0, 0xFF, 0x80, 0x70, 0x7F, 0xF0, 0x38, 0x1E,
- 0x3C, 0x1C, 0x0F, 0x07, 0x06, 0x03, 0x81, 0xC3, 0x80, 0xE0, 0xF1, 0xC0,
- 0x3C, 0x78, 0xE0, 0x0F, 0xFE, 0x30, 0x01, 0xFF, 0x1C, 0x00, 0x7F, 0x8E,
- 0x00, 0x07, 0x83, 0x00, 0x00, 0x01, 0x83, 0xE0, 0x00, 0xE3, 0xFE, 0x00,
- 0x71, 0xFF, 0x80, 0x18, 0xFF, 0xF0, 0x0C, 0x3C, 0x3C, 0x07, 0x1C, 0x07,
- 0x03, 0x87, 0x01, 0xC0, 0xC1, 0xE1, 0xE0, 0x60, 0x7F, 0xF8, 0x38, 0x0F,
- 0xFC, 0x1C, 0x03, 0xFE, 0x06, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x03,
- 0xFC, 0x00, 0x3F, 0xF0, 0x03, 0xFF, 0x80, 0x3F, 0x3C, 0x01, 0xF1, 0xE0,
- 0x0F, 0x8F, 0x00, 0x7C, 0xF0, 0x03, 0xFF, 0x80, 0x0F, 0xF8, 0x00, 0x3F,
- 0x00, 0x03, 0xF0, 0x00, 0x7F, 0xC7, 0x8F, 0xFE, 0x3C, 0xFC, 0xFB, 0xCF,
- 0x83, 0xFE, 0xF8, 0x1F, 0xE7, 0xC0, 0x7E, 0x3E, 0x03, 0xE1, 0xF0, 0x1F,
- 0x0F, 0xE3, 0xFC, 0x7F, 0xFF, 0xE1, 0xFF, 0xFF, 0x87, 0xFE, 0x7C, 0x0F,
- 0xE1, 0xF0, 0x7B, 0xFF, 0xEF, 0x7B, 0x9C, 0xC0, 0x00, 0x78, 0x07, 0x80,
- 0x78, 0x03, 0x80, 0x3C, 0x03, 0xC0, 0x1E, 0x01, 0xE0, 0x1E, 0x00, 0xF0,
- 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0xF0, 0x07,
- 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0,
- 0x07, 0x80, 0x1C, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x00, 0xE0, 0x07, 0x80,
- 0x1C, 0x00, 0x01, 0xC0, 0x0F, 0x00, 0x38, 0x01, 0xE0, 0x0F, 0x00, 0x78,
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- 0xF0, 0x3F, 0xF7, 0x81, 0xFF, 0xFE, 0x0F, 0xE3, 0xF8, 0x3E, 0x07, 0xE1,
- 0xF8, 0x0F, 0x87, 0xC0, 0x3C, 0x1E, 0x00, 0xF0, 0xF8, 0x03, 0xC3, 0xE0,
- 0x1F, 0x0F, 0x80, 0x78, 0x3E, 0x03, 0xE0, 0xF8, 0x1F, 0x83, 0xF0, 0xFE,
- 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xC0, 0x3F, 0xEF, 0x00, 0x3E, 0x7C, 0x00,
- 0x01, 0xF0, 0x00, 0x07, 0xC3, 0xE0, 0x3E, 0x0F, 0x80, 0xF8, 0x3F, 0x0F,
- 0xC0, 0x7F, 0xFE, 0x00, 0xFF, 0xF0, 0x00, 0xFE, 0x00, 0x00, 0x03, 0xE0,
- 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C,
- 0x00, 0x0F, 0x80, 0x00, 0xF8, 0xF8, 0x0F, 0xBF, 0xE0, 0xFF, 0xFF, 0x0F,
- 0xFF, 0xF1, 0xFC, 0x3F, 0x1F, 0x81, 0xF1, 0xF0, 0x1F, 0x1F, 0x01, 0xF1,
- 0xE0, 0x1F, 0x3E, 0x03, 0xE3, 0xE0, 0x3E, 0x3E, 0x03, 0xE3, 0xE0, 0x3E,
- 0x7C, 0x03, 0xE7, 0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0xC0, 0x7C, 0x7C, 0x07,
- 0xCF, 0x80, 0x78, 0x07, 0xC1, 0xF0, 0x7C, 0x3E, 0x00, 0x00, 0x00, 0x00,
- 0x3E, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E,
- 0x0F, 0x87, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8, 0x3E, 0x00,
- 0x00, 0x3E, 0x00, 0x78, 0x01, 0xF0, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x0F, 0x80, 0x1F,
- 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF8, 0x03, 0xE0, 0x07, 0xC0, 0x0F, 0x80,
- 0x1F, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0xC0, 0x1F,
- 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF8, 0x03, 0xF0, 0x1F, 0xC0, 0x3F, 0x80,
- 0x7E, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00,
- 0x0F, 0x80, 0x00, 0x78, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0,
- 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x07, 0xC7, 0xE0, 0x3E, 0x7E, 0x01,
- 0xF7, 0xE0, 0x0F, 0xFE, 0x00, 0xFF, 0xE0, 0x07, 0xFF, 0x00, 0x3F, 0xFC,
- 0x01, 0xFF, 0xE0, 0x0F, 0xDF, 0x00, 0xFC, 0xFC, 0x07, 0xC3, 0xE0, 0x3E,
- 0x1F, 0x01, 0xF0, 0xFC, 0x0F, 0x83, 0xE0, 0xF8, 0x1F, 0x87, 0xC0, 0xFC,
- 0x00, 0x07, 0xC1, 0xF0, 0x7C, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x1F,
- 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x87,
- 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8, 0x3E, 0x00, 0x0F, 0x8F,
- 0x83, 0xF0, 0x3E, 0xFF, 0x3F, 0xE0, 0xF7, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF,
- 0xFF, 0x1F, 0xC7, 0xF8, 0x7C, 0x7C, 0x0F, 0x81, 0xF1, 0xF0, 0x3E, 0x07,
- 0xCF, 0x81, 0xF0, 0x3E, 0x3E, 0x07, 0xC0, 0xF8, 0xF8, 0x1F, 0x03, 0xE3,
- 0xE0, 0x7C, 0x0F, 0x8F, 0x81, 0xF0, 0x3E, 0x7C, 0x0F, 0x81, 0xF1, 0xF0,
- 0x3E, 0x07, 0xC7, 0xC0, 0xF8, 0x1F, 0x1F, 0x03, 0xE0, 0x7C, 0x7C, 0x0F,
- 0x81, 0xE3, 0xE0, 0x7C, 0x0F, 0x8F, 0x81, 0xF0, 0x3E, 0x00, 0x0F, 0x8F,
- 0x80, 0xFB, 0xFE, 0x0F, 0xFF, 0xF1, 0xFF, 0xFF, 0x1F, 0xC3, 0xF1, 0xF8,
- 0x1F, 0x1F, 0x01, 0xF1, 0xF0, 0x1F, 0x3E, 0x01, 0xF3, 0xE0, 0x3E, 0x3E,
- 0x03, 0xE3, 0xE0, 0x3E, 0x3C, 0x03, 0xE7, 0xC0, 0x3E, 0x7C, 0x07, 0xC7,
- 0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0x80, 0x7C, 0xF8, 0x07, 0x80, 0x00, 0xFE,
- 0x00, 0x7F, 0xF0, 0x3F, 0xFF, 0x0F, 0xFF, 0xE3, 0xF8, 0xFE, 0x7C, 0x0F,
- 0xDF, 0x00, 0xFB, 0xE0, 0x1F, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xE0, 0x1F,
- 0xFC, 0x03, 0xEF, 0x80, 0x7D, 0xF8, 0x1F, 0x3F, 0x07, 0xE3, 0xFF, 0xF8,
- 0x7F, 0xFE, 0x07, 0xFF, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xE7, 0xE0, 0x0F,
- 0xBF, 0xC0, 0x7D, 0xFF, 0x81, 0xFF, 0xFE, 0x07, 0xF0, 0xFC, 0x1F, 0x81,
- 0xF0, 0x7C, 0x07, 0xC3, 0xE0, 0x1F, 0x0F, 0x80, 0x7C, 0x3E, 0x01, 0xF0,
- 0xF0, 0x07, 0xC3, 0xC0, 0x3E, 0x1F, 0x00, 0xF8, 0x7E, 0x07, 0xC1, 0xFC,
- 0x7F, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xC0, 0xFB, 0xFE, 0x03, 0xE7, 0xE0,
- 0x0F, 0x80, 0x00, 0x3E, 0x00, 0x00, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x1F,
- 0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x00, 0x01,
- 0xF1, 0xF0, 0x7F, 0xDF, 0x0F, 0xFD, 0xF1, 0xFF, 0xFE, 0x3F, 0x8F, 0xE3,
- 0xE0, 0x7E, 0x7C, 0x03, 0xE7, 0xC0, 0x3E, 0xF8, 0x03, 0xCF, 0x80, 0x3C,
- 0xF8, 0x07, 0xCF, 0x80, 0x7C, 0xF8, 0x0F, 0x8F, 0x81, 0xF8, 0xFC, 0x3F,
- 0x87, 0xFF, 0xF8, 0x7F, 0xFF, 0x83, 0xFF, 0xF0, 0x1F, 0x9F, 0x00, 0x01,
- 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00,
- 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x0F, 0x8E, 0x1F, 0x7C, 0x3F,
- 0xF0, 0xFF, 0xE1, 0xFC, 0x03, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x3E, 0x00,
- 0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x0F, 0x80, 0x1F, 0x00, 0x3E,
- 0x00, 0x7C, 0x00, 0xF0, 0x03, 0xE0, 0x00, 0x01, 0xFC, 0x01, 0xFF, 0xC0,
- 0xFF, 0xF8, 0x7F, 0xFF, 0x3F, 0x0F, 0xCF, 0x81, 0xF3, 0xF0, 0x00, 0xFF,
- 0x80, 0x3F, 0xFC, 0x07, 0xFF, 0xC0, 0x7F, 0xF8, 0x03, 0xFE, 0x00, 0x1F,
- 0xBE, 0x03, 0xEF, 0xC1, 0xFB, 0xFF, 0xFC, 0x7F, 0xFE, 0x0F, 0xFF, 0x00,
- 0xFE, 0x00, 0x0F, 0x81, 0xF0, 0x7C, 0x0F, 0x81, 0xF0, 0xFF, 0xBF, 0xF7,
- 0xFE, 0x3E, 0x07, 0xC0, 0xF8, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0,
- 0xF8, 0x1F, 0x03, 0xE0, 0x7F, 0x0F, 0xE1, 0xFC, 0x1F, 0x80, 0x1F, 0x01,
- 0xF1, 0xF0, 0x1F, 0x3E, 0x03, 0xE3, 0xE0, 0x3E, 0x3E, 0x03, 0xE3, 0xE0,
- 0x3E, 0x3E, 0x03, 0xE7, 0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0xC0, 0x7C, 0x7C,
- 0x07, 0xC7, 0xC0, 0x7C, 0xF8, 0x0F, 0x8F, 0x81, 0xF8, 0xF8, 0x3F, 0x8F,
- 0xFF, 0xF8, 0xFF, 0xFF, 0x07, 0xFD, 0xF0, 0x3F, 0x1F, 0x00, 0xF8, 0x0F,
- 0xFE, 0x03, 0xEF, 0x81, 0xF3, 0xE0, 0x7C, 0xF8, 0x3E, 0x3E, 0x0F, 0x8F,
- 0x87, 0xC1, 0xE1, 0xF0, 0x78, 0xF8, 0x1E, 0x3E, 0x07, 0x9F, 0x01, 0xF7,
- 0x80, 0x7F, 0xE0, 0x1F, 0xF0, 0x03, 0xFC, 0x00, 0xFE, 0x00, 0x3F, 0x80,
- 0x0F, 0xC0, 0x03, 0xF0, 0x00, 0xF8, 0x1F, 0x07, 0xFF, 0x03, 0xE0, 0xFB,
- 0xE0, 0xFC, 0x1F, 0x7C, 0x1F, 0x87, 0xCF, 0x87, 0xF0, 0xF9, 0xF0, 0xFE,
- 0x3E, 0x3E, 0x3D, 0xC7, 0xC3, 0xC7, 0xB9, 0xF0, 0x79, 0xE7, 0x3E, 0x0F,
- 0x3C, 0xE7, 0x81, 0xEF, 0x1D, 0xF0, 0x3D, 0xE3, 0xBC, 0x07, 0xBC, 0x7F,
- 0x80, 0xFF, 0x0F, 0xE0, 0x1F, 0xE1, 0xFC, 0x03, 0xF8, 0x3F, 0x00, 0x7F,
- 0x07, 0xE0, 0x0F, 0xC0, 0xF8, 0x01, 0xF8, 0x1F, 0x00, 0x00, 0x0F, 0xC1,
- 0xF8, 0x3F, 0x07, 0xC0, 0x7C, 0x3E, 0x01, 0xF9, 0xF8, 0x03, 0xEF, 0xC0,
- 0x0F, 0xBE, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0x80, 0x01, 0xFC, 0x00, 0x03,
- 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0xFF, 0x00, 0x07, 0xFE, 0x00, 0x3E, 0xF8,
- 0x01, 0xFB, 0xF0, 0x07, 0xC7, 0xC0, 0x3E, 0x1F, 0x81, 0xF8, 0x7E, 0x0F,
- 0xC0, 0xF8, 0x00, 0x1F, 0x80, 0x7C, 0x3E, 0x03, 0xE0, 0xF8, 0x0F, 0x03,
- 0xE0, 0x7C, 0x0F, 0x81, 0xE0, 0x3E, 0x0F, 0x80, 0xF8, 0x3C, 0x03, 0xE1,
- 0xF0, 0x07, 0x87, 0x80, 0x1F, 0x3E, 0x00, 0x7C, 0xF0, 0x01, 0xF7, 0xC0,
- 0x07, 0xDE, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0xC0, 0x01, 0xFE, 0x00, 0x03,
- 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0,
- 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00, 0x01,
- 0xF8, 0x00, 0x0F, 0x80, 0x00, 0x00, 0x0F, 0xFF, 0xE1, 0xFF, 0xFC, 0x3F,
- 0xFF, 0x87, 0xFF, 0xE0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F, 0xC0, 0x03,
- 0xF0, 0x01, 0xFC, 0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x01, 0xF8,
- 0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xFF, 0xF8, 0xFF, 0xFF, 0x1F, 0xFF,
- 0xE3, 0xFF, 0xFC, 0x00, 0x00, 0x7C, 0x03, 0xF0, 0x1F, 0xC0, 0xFE, 0x03,
- 0xE0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01,
- 0xE0, 0x0F, 0x80, 0x3C, 0x01, 0xF0, 0x1F, 0x80, 0x70, 0x01, 0xF8, 0x01,
- 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00,
- 0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xFC, 0x07, 0xE0, 0x0F, 0x80,
- 0x1E, 0x00, 0x03, 0x81, 0xC0, 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0C, 0x0E,
- 0x07, 0x03, 0x81, 0xC0, 0xC0, 0xE0, 0x70, 0x38, 0x18, 0x1C, 0x0E, 0x07,
- 0x03, 0x81, 0x81, 0xC0, 0xE0, 0x70, 0x38, 0x18, 0x1C, 0x0E, 0x07, 0x01,
- 0x80, 0x80, 0x00, 0x00, 0x01, 0xE0, 0x07, 0xC0, 0x1F, 0x80, 0xFE, 0x00,
- 0x78, 0x01, 0xE0, 0x07, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00,
- 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x7E, 0x00, 0x38, 0x07, 0xE0,
- 0x3E, 0x00, 0xF0, 0x07, 0xC0, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80,
- 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1F, 0x01, 0xF8, 0x0F, 0xE0, 0x3F, 0x00,
- 0xF8, 0x00, 0x0F, 0x00, 0x1F, 0xC1, 0xDF, 0xF0, 0xEE, 0x3F, 0xE6, 0x07,
- 0xF0, 0x01, 0xE0 };
-
-const GFXglyph FreeSansBoldOblique18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 10, 0, 1 }, // 0x20 ' '
- { 0, 10, 25, 12, 4, -24 }, // 0x21 '!'
- { 32, 13, 9, 17, 6, -25 }, // 0x22 '"'
- { 47, 22, 24, 19, 1, -23 }, // 0x23 '#'
- { 113, 19, 31, 19, 2, -26 }, // 0x24 '$'
- { 187, 26, 26, 31, 5, -25 }, // 0x25 '%'
- { 272, 21, 25, 25, 3, -24 }, // 0x26 '&'
- { 338, 5, 9, 8, 6, -25 }, // 0x27 '''
- { 344, 13, 33, 12, 3, -25 }, // 0x28 '('
- { 398, 13, 33, 12, -1, -25 }, // 0x29 ')'
- { 452, 12, 11, 14, 5, -25 }, // 0x2A '*'
- { 469, 18, 16, 20, 3, -15 }, // 0x2B '+'
- { 505, 7, 11, 10, 1, -4 }, // 0x2C ','
- { 515, 10, 4, 12, 2, -10 }, // 0x2D '-'
- { 520, 6, 5, 10, 2, -4 }, // 0x2E '.'
- { 524, 15, 25, 10, 0, -24 }, // 0x2F '/'
- { 571, 18, 25, 19, 3, -24 }, // 0x30 '0'
- { 628, 13, 25, 19, 6, -24 }, // 0x31 '1'
- { 669, 21, 25, 19, 1, -24 }, // 0x32 '2'
- { 735, 20, 25, 19, 2, -24 }, // 0x33 '3'
- { 798, 19, 25, 19, 2, -24 }, // 0x34 '4'
- { 858, 20, 24, 19, 2, -23 }, // 0x35 '5'
- { 918, 19, 25, 19, 3, -24 }, // 0x36 '6'
- { 978, 19, 24, 19, 5, -23 }, // 0x37 '7'
- { 1035, 20, 25, 19, 2, -24 }, // 0x38 '8'
- { 1098, 19, 25, 19, 2, -24 }, // 0x39 '9'
- { 1158, 9, 18, 12, 4, -17 }, // 0x3A ':'
- { 1179, 10, 24, 12, 3, -17 }, // 0x3B ';'
- { 1209, 19, 17, 20, 3, -16 }, // 0x3C '<'
- { 1250, 20, 12, 20, 2, -13 }, // 0x3D '='
- { 1280, 19, 17, 20, 1, -15 }, // 0x3E '>'
- { 1321, 18, 26, 21, 6, -25 }, // 0x3F '?'
- { 1380, 33, 31, 34, 3, -25 }, // 0x40 '@'
- { 1508, 23, 26, 25, 1, -25 }, // 0x41 'A'
- { 1583, 24, 26, 25, 3, -25 }, // 0x42 'B'
- { 1661, 24, 26, 25, 4, -25 }, // 0x43 'C'
- { 1739, 24, 26, 25, 3, -25 }, // 0x44 'D'
- { 1817, 24, 26, 23, 3, -25 }, // 0x45 'E'
- { 1895, 23, 26, 21, 3, -25 }, // 0x46 'F'
- { 1970, 24, 26, 27, 4, -25 }, // 0x47 'G'
- { 2048, 26, 26, 25, 2, -25 }, // 0x48 'H'
- { 2133, 10, 26, 10, 2, -25 }, // 0x49 'I'
- { 2166, 20, 26, 19, 2, -25 }, // 0x4A 'J'
- { 2231, 26, 26, 25, 3, -25 }, // 0x4B 'K'
- { 2316, 18, 26, 21, 3, -25 }, // 0x4C 'L'
- { 2375, 31, 26, 29, 2, -25 }, // 0x4D 'M'
- { 2476, 27, 26, 25, 2, -25 }, // 0x4E 'N'
- { 2564, 25, 26, 27, 4, -25 }, // 0x4F 'O'
- { 2646, 23, 26, 23, 3, -25 }, // 0x50 'P'
- { 2721, 25, 27, 27, 4, -25 }, // 0x51 'Q'
- { 2806, 24, 26, 25, 3, -25 }, // 0x52 'R'
- { 2884, 22, 26, 23, 3, -25 }, // 0x53 'S'
- { 2956, 21, 26, 21, 5, -25 }, // 0x54 'T'
- { 3025, 24, 26, 25, 4, -25 }, // 0x55 'U'
- { 3103, 22, 26, 23, 6, -25 }, // 0x56 'V'
- { 3175, 32, 26, 33, 6, -25 }, // 0x57 'W'
- { 3279, 27, 26, 23, 1, -25 }, // 0x58 'X'
- { 3367, 22, 26, 23, 6, -25 }, // 0x59 'Y'
- { 3439, 25, 26, 21, 1, -25 }, // 0x5A 'Z'
- { 3521, 15, 33, 12, 1, -25 }, // 0x5B '['
- { 3583, 5, 25, 10, 5, -24 }, // 0x5C '\'
- { 3599, 15, 33, 12, -1, -25 }, // 0x5D ']'
- { 3661, 16, 15, 20, 4, -23 }, // 0x5E '^'
- { 3691, 21, 3, 19, -2, 5 }, // 0x5F '_'
- { 3699, 5, 5, 12, 6, -25 }, // 0x60 '`'
- { 3703, 18, 19, 19, 2, -18 }, // 0x61 'a'
- { 3746, 20, 26, 21, 2, -25 }, // 0x62 'b'
- { 3811, 18, 19, 19, 3, -18 }, // 0x63 'c'
- { 3854, 22, 26, 21, 3, -25 }, // 0x64 'd'
- { 3926, 19, 19, 19, 2, -18 }, // 0x65 'e'
- { 3972, 13, 26, 12, 3, -25 }, // 0x66 'f'
- { 4015, 22, 27, 21, 1, -18 }, // 0x67 'g'
- { 4090, 20, 26, 21, 2, -25 }, // 0x68 'h'
- { 4155, 10, 26, 10, 2, -25 }, // 0x69 'i'
- { 4188, 15, 34, 10, -2, -25 }, // 0x6A 'j'
- { 4252, 21, 26, 19, 2, -25 }, // 0x6B 'k'
- { 4321, 10, 26, 10, 2, -25 }, // 0x6C 'l'
- { 4354, 30, 19, 31, 2, -18 }, // 0x6D 'm'
- { 4426, 20, 19, 21, 2, -18 }, // 0x6E 'n'
- { 4474, 19, 19, 21, 3, -18 }, // 0x6F 'o'
- { 4520, 22, 27, 21, 0, -18 }, // 0x70 'p'
- { 4595, 20, 27, 21, 3, -18 }, // 0x71 'q'
- { 4663, 15, 19, 14, 2, -18 }, // 0x72 'r'
- { 4699, 18, 19, 19, 2, -18 }, // 0x73 's'
- { 4742, 11, 23, 12, 4, -22 }, // 0x74 't'
- { 4774, 20, 19, 21, 3, -18 }, // 0x75 'u'
- { 4822, 18, 19, 19, 5, -18 }, // 0x76 'v'
- { 4865, 27, 19, 27, 4, -18 }, // 0x77 'w'
- { 4930, 22, 19, 19, 1, -18 }, // 0x78 'x'
- { 4983, 22, 27, 19, 1, -18 }, // 0x79 'y'
- { 5058, 19, 19, 17, 1, -18 }, // 0x7A 'z'
- { 5104, 14, 33, 14, 2, -25 }, // 0x7B '{'
- { 5162, 9, 33, 10, 2, -25 }, // 0x7C '|'
- { 5200, 14, 33, 14, 2, -25 }, // 0x7D '}'
- { 5258, 17, 6, 20, 3, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSansBoldOblique18pt7b PROGMEM = {
- (uint8_t *)FreeSansBoldOblique18pt7bBitmaps,
- (GFXglyph *)FreeSansBoldOblique18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 5943 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique24pt7b.h
deleted file mode 100644
index ea65f9b..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique24pt7b.h
+++ /dev/null
@@ -1,893 +0,0 @@
-const uint8_t FreeSansBoldOblique24pt7bBitmaps[] PROGMEM = {
- 0x01, 0xE0, 0x07, 0xF0, 0x1F, 0xC0, 0xFF, 0x03, 0xF8, 0x0F, 0xE0, 0x3F,
- 0x80, 0xFE, 0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xE0, 0x1F,
- 0x80, 0x7E, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0xF8, 0x03, 0xE0, 0x0F,
- 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x1F,
- 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0xFE, 0x03, 0xF8, 0x00,
- 0x7E, 0x0F, 0xDF, 0x83, 0xF7, 0xE0, 0xFF, 0xF0, 0x7E, 0xFC, 0x1F, 0xBF,
- 0x07, 0xEF, 0xC1, 0xFB, 0xE0, 0x7C, 0xF8, 0x1F, 0x3C, 0x07, 0x8F, 0x01,
- 0xE3, 0x80, 0x70, 0x00, 0x07, 0xC1, 0xF0, 0x00, 0x3E, 0x0F, 0x80, 0x03,
- 0xE0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x01, 0xF0, 0x7C, 0x00, 0x0F, 0x83,
- 0xE0, 0x00, 0xF8, 0x3E, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF8,
- 0x7F, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0x0F,
- 0x83, 0xE0, 0x00, 0x7C, 0x3E, 0x00, 0x07, 0xC1, 0xF0, 0x00, 0x3E, 0x0F,
- 0x80, 0x03, 0xE0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x00, 0xF8, 0x7C, 0x00,
- 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF, 0xFF, 0x83, 0xFF,
- 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0x1F, 0x07, 0xC0, 0x00, 0xF8, 0x3E,
- 0x00, 0x0F, 0x83, 0xE0, 0x00, 0x7C, 0x1F, 0x00, 0x07, 0xC1, 0xF0, 0x00,
- 0x3E, 0x0F, 0x80, 0x01, 0xF0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x00, 0xF8,
- 0x3C, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E,
- 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x7F, 0xFF, 0x00, 0x3F, 0xFF, 0xE0, 0x1F,
- 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0x07, 0xF3, 0x9F, 0xC1, 0xF8, 0xE3, 0xF0,
- 0x7C, 0x38, 0xFC, 0x3F, 0x0E, 0x3F, 0x0F, 0xC7, 0x8F, 0xC3, 0xF1, 0xC0,
- 0x00, 0xFE, 0x70, 0x00, 0x3F, 0xDC, 0x00, 0x0F, 0xFF, 0x00, 0x01, 0xFF,
- 0xE0, 0x00, 0x3F, 0xFE, 0x00, 0x0F, 0xFF, 0xE0, 0x00, 0xFF, 0xFC, 0x00,
- 0x0F, 0xFF, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0x77, 0xF8, 0x00, 0x1C, 0xFE,
- 0x00, 0x07, 0x3F, 0x8F, 0xE3, 0xCF, 0xE3, 0xF8, 0xE3, 0xF8, 0xFE, 0x38,
- 0xFC, 0x3F, 0x8E, 0x7F, 0x0F, 0xF3, 0x9F, 0xC3, 0xFD, 0xFF, 0xE0, 0x7F,
- 0xFF, 0xF0, 0x1F, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00,
- 0x03, 0xFC, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x03, 0x80,
- 0x00, 0x01, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x01, 0xF8, 0x00, 0x07,
- 0x80, 0x7F, 0xE0, 0x00, 0xF0, 0x0F, 0xFF, 0x00, 0x1E, 0x01, 0xFF, 0xF0,
- 0x01, 0xC0, 0x3F, 0xFF, 0x80, 0x3C, 0x07, 0xE1, 0xF8, 0x07, 0x80, 0x78,
- 0x07, 0x80, 0xF0, 0x0F, 0x80, 0x78, 0x0E, 0x00, 0xF0, 0x07, 0x81, 0xC0,
- 0x0F, 0x00, 0xF8, 0x3C, 0x00, 0xF0, 0x0F, 0x07, 0x80, 0x0F, 0xC3, 0xF0,
- 0xF0, 0x00, 0xFF, 0xFE, 0x0E, 0x00, 0x07, 0xFF, 0xC1, 0xE0, 0x00, 0x7F,
- 0xF8, 0x3C, 0x00, 0x03, 0xFF, 0x07, 0x80, 0x00, 0x0F, 0xC0, 0x70, 0x00,
- 0x00, 0x00, 0x0E, 0x03, 0xF0, 0x00, 0x01, 0xE0, 0xFF, 0xC0, 0x00, 0x3C,
- 0x1F, 0xFE, 0x00, 0x03, 0x83, 0xFF, 0xE0, 0x00, 0x70, 0x7F, 0xFF, 0x00,
- 0x0F, 0x0F, 0xC3, 0xF0, 0x01, 0xE0, 0xF0, 0x0F, 0x00, 0x3C, 0x1F, 0x00,
- 0xF0, 0x03, 0x81, 0xE0, 0x0F, 0x00, 0x78, 0x1E, 0x01, 0xF0, 0x0F, 0x01,
- 0xE0, 0x1E, 0x01, 0xE0, 0x1F, 0x87, 0xE0, 0x1C, 0x01, 0xFF, 0xFC, 0x03,
- 0x80, 0x0F, 0xFF, 0x80, 0x78, 0x00, 0xFF, 0xF0, 0x0F, 0x00, 0x07, 0xFE,
- 0x01, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3F, 0xF0,
- 0x00, 0x07, 0xFF, 0xC0, 0x00, 0x7F, 0xFF, 0x00, 0x03, 0xFF, 0xF8, 0x00,
- 0x3F, 0x9F, 0xC0, 0x03, 0xF8, 0x7E, 0x00, 0x1F, 0xC3, 0xF0, 0x00, 0xFE,
- 0x1F, 0x00, 0x07, 0xF1, 0xF8, 0x00, 0x3F, 0xCF, 0xC0, 0x01, 0xFE, 0xFC,
- 0x00, 0x07, 0xFF, 0xC0, 0x00, 0x3F, 0xFC, 0x00, 0x00, 0xFF, 0xC0, 0x00,
- 0x07, 0xF8, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xFF, 0x07, 0xC1, 0xFF,
- 0xF8, 0x3E, 0x3F, 0xFF, 0xE3, 0xE3, 0xFE, 0x3F, 0x1F, 0x1F, 0xC1, 0xFD,
- 0xF1, 0xFC, 0x07, 0xFF, 0x8F, 0xC0, 0x3F, 0xF8, 0xFE, 0x00, 0xFF, 0xC7,
- 0xF0, 0x07, 0xFC, 0x3F, 0x80, 0x1F, 0xC1, 0xFC, 0x00, 0xFE, 0x0F, 0xF0,
- 0x1F, 0xF8, 0x7F, 0xC1, 0xFF, 0xC1, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF,
- 0xFC, 0x3F, 0xFF, 0xCF, 0xE0, 0x7F, 0xF8, 0x7F, 0x80, 0xFF, 0x00, 0x00,
- 0x7E, 0xFD, 0xFF, 0xEF, 0xDF, 0xBF, 0x7C, 0xF9, 0xE3, 0xC7, 0x00, 0x00,
- 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0xC0, 0x07, 0xC0, 0x07, 0xC0,
- 0x07, 0xE0, 0x03, 0xE0, 0x03, 0xE0, 0x03, 0xF0, 0x01, 0xF0, 0x01, 0xF8,
- 0x00, 0xF8, 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x7E, 0x00, 0x3E, 0x00, 0x1F,
- 0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x03, 0xF0, 0x01,
- 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80,
- 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x1E,
- 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0x7C, 0x00,
- 0x3E, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00,
- 0x1E, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x00, 0xF0, 0x00, 0x7C,
- 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x03, 0xE0, 0x01, 0xF0, 0x00,
- 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0,
- 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E,
- 0x00, 0x1F, 0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x03,
- 0xE0, 0x03, 0xF0, 0x01, 0xF0, 0x01, 0xF8, 0x00, 0xF8, 0x00, 0xFC, 0x00,
- 0x7C, 0x00, 0x7C, 0x00, 0x7E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3F, 0x00,
- 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xE0, 0x03, 0x80, 0x07,
- 0x00, 0x0E, 0x07, 0x3C, 0x6F, 0xFF, 0xFF, 0xFF, 0xBF, 0xFE, 0x0F, 0xE0,
- 0x1F, 0xC0, 0x7F, 0x81, 0xEF, 0x87, 0x8F, 0x0E, 0x1E, 0x08, 0x10, 0x00,
- 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x00,
- 0x00, 0x1F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00,
- 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE,
- 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00,
- 0x00, 0xFC, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF8, 0x00,
- 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x1F, 0xC7, 0xF1, 0xF8, 0xFE, 0x3F,
- 0x8F, 0xE0, 0x38, 0x1C, 0x07, 0x03, 0xC0, 0xE0, 0xF0, 0xFC, 0x3C, 0x0C,
- 0x00, 0x7F, 0xFD, 0xFF, 0xF7, 0xFF, 0x9F, 0xFE, 0xFF, 0xFB, 0xFF, 0xE0,
- 0x7F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFE, 0x00, 0x00, 0x70, 0x00, 0x0E,
- 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x03,
- 0x80, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x01,
- 0xC0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00,
- 0x70, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00,
- 0x38, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00,
- 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00,
- 0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x00,
- 0x1F, 0xFC, 0x00, 0x3F, 0xFF, 0x80, 0x3F, 0xFF, 0xC0, 0x3F, 0xFF, 0xF0,
- 0x1F, 0xC7, 0xF8, 0x1F, 0xC1, 0xFE, 0x1F, 0xC0, 0x7F, 0x0F, 0xC0, 0x3F,
- 0x8F, 0xE0, 0x1F, 0xC7, 0xF0, 0x0F, 0xE3, 0xF0, 0x07, 0xF3, 0xF8, 0x03,
- 0xF9, 0xFC, 0x01, 0xFC, 0xFC, 0x01, 0xFE, 0xFE, 0x00, 0xFE, 0x7F, 0x00,
- 0x7F, 0x3F, 0x80, 0x3F, 0x9F, 0xC0, 0x1F, 0xCF, 0xE0, 0x1F, 0xEF, 0xE0,
- 0x0F, 0xE7, 0xF0, 0x07, 0xF3, 0xF8, 0x03, 0xF9, 0xFC, 0x03, 0xF8, 0xFE,
- 0x01, 0xFC, 0x7F, 0x00, 0xFE, 0x3F, 0x80, 0xFE, 0x1F, 0xE0, 0x7F, 0x0F,
- 0xF8, 0xFF, 0x03, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0x80,
- 0x1F, 0xFF, 0x00, 0x07, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x0F,
- 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x0F, 0xF0, 0x3F, 0xF9, 0xFF,
- 0xF8, 0xFF, 0xFC, 0xFF, 0xFE, 0x7F, 0xFF, 0x00, 0x3F, 0x80, 0x1F, 0x80,
- 0x0F, 0xC0, 0x0F, 0xE0, 0x07, 0xF0, 0x03, 0xF8, 0x01, 0xF8, 0x01, 0xFC,
- 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x3F, 0x00, 0x1F, 0x80, 0x1F, 0xC0, 0x0F,
- 0xE0, 0x07, 0xF0, 0x03, 0xF0, 0x01, 0xF8, 0x01, 0xFC, 0x00, 0xFE, 0x00,
- 0x7F, 0x00, 0x3F, 0x00, 0x3F, 0x80, 0x1F, 0xC0, 0x00, 0x00, 0x01, 0xFE,
- 0x00, 0x00, 0x7F, 0xFC, 0x00, 0x0F, 0xFF, 0xF8, 0x00, 0xFF, 0xFF, 0xE0,
- 0x0F, 0xFF, 0xFF, 0x00, 0xFF, 0x07, 0xFC, 0x07, 0xF0, 0x1F, 0xE0, 0x7F,
- 0x00, 0x7F, 0x03, 0xF0, 0x03, 0xF8, 0x1F, 0x80, 0x1F, 0xC1, 0xF8, 0x00,
- 0xFE, 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07, 0xF0,
- 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x7F, 0x80, 0x00,
- 0x07, 0xF8, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x1F, 0xF8, 0x00, 0x01, 0xFF,
- 0x00, 0x00, 0x3F, 0xE0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0x7F, 0xC0, 0x00,
- 0x07, 0xFC, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x7F,
- 0x80, 0x00, 0x03, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF, 0xFF, 0x81, 0xFF, 0xFF,
- 0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xF0,
- 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x0F, 0xFF, 0x80, 0x0F, 0xFF, 0xF0, 0x07,
- 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xC0, 0xFE, 0x1F, 0xF0, 0x7F, 0x01, 0xFC,
- 0x1F, 0x80, 0x7F, 0x07, 0xE0, 0x1F, 0xC3, 0xF0, 0x07, 0xF0, 0xFC, 0x01,
- 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x80, 0x01,
- 0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xFC, 0x00, 0x07, 0xFF, 0x80,
- 0x01, 0xFF, 0xE0, 0x00, 0x07, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x1F,
- 0xC0, 0x00, 0x07, 0xF0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x7F, 0x3F, 0x80,
- 0x3F, 0xCF, 0xE0, 0x0F, 0xE3, 0xF8, 0x07, 0xF8, 0xFF, 0x83, 0xFC, 0x3F,
- 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xE0,
- 0x03, 0xFF, 0xE0, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x00,
- 0x7F, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00,
- 0x3F, 0xF8, 0x00, 0x3D, 0xFC, 0x00, 0x3C, 0xFE, 0x00, 0x3E, 0x7E, 0x00,
- 0x3E, 0x7F, 0x00, 0x1E, 0x3F, 0x80, 0x1E, 0x1F, 0xC0, 0x1E, 0x0F, 0xC0,
- 0x1F, 0x07, 0xE0, 0x1F, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x1F, 0x01, 0xFC,
- 0x0F, 0x80, 0xFC, 0x0F, 0x80, 0xFE, 0x0F, 0x80, 0x7F, 0x07, 0xFF, 0xFF,
- 0xF7, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF,
- 0xFE, 0x00, 0x03, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xFC, 0x00, 0x00,
- 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F, 0x80, 0x00,
- 0x7F, 0xFF, 0xE0, 0x0F, 0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0x80, 0x7F, 0xFF,
- 0xF0, 0x0F, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x80, 0x7C, 0x00, 0x00, 0x0F,
- 0x80, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0F, 0x80, 0x00,
- 0x03, 0xE3, 0xF0, 0x00, 0x7F, 0xFF, 0x80, 0x1F, 0xFF, 0xF8, 0x03, 0xFF,
- 0xFF, 0x80, 0x7F, 0xFF, 0xF0, 0x1F, 0xE1, 0xFF, 0x03, 0xF0, 0x1F, 0xE0,
- 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00,
- 0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xF0, 0xFE, 0x00, 0xFE, 0x1F,
- 0xC0, 0x3F, 0x83, 0xF8, 0x07, 0xF0, 0x7F, 0x83, 0xFC, 0x0F, 0xFF, 0xFF,
- 0x80, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x01, 0xFF, 0xFE, 0x00, 0x0F,
- 0xFF, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x1F, 0xFE,
- 0x00, 0x1F, 0xFF, 0x80, 0x1F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x1F, 0xC3,
- 0xFC, 0x1F, 0x80, 0xFE, 0x0F, 0xC0, 0x3F, 0x0F, 0xC0, 0x00, 0x07, 0xE0,
- 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF8, 0xFC, 0x01, 0xF9,
- 0xFF, 0x80, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF, 0xFC, 0x3F,
- 0xE1, 0xFF, 0x1F, 0xE0, 0x7F, 0x8F, 0xE0, 0x1F, 0xCF, 0xE0, 0x0F, 0xE7,
- 0xF0, 0x07, 0xF3, 0xF0, 0x03, 0xF9, 0xF8, 0x01, 0xF8, 0xFC, 0x01, 0xFC,
- 0x7E, 0x00, 0xFE, 0x3F, 0x00, 0xFE, 0x1F, 0xC0, 0xFF, 0x0F, 0xF0, 0xFF,
- 0x03, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0x80, 0x1F, 0xFF,
- 0x80, 0x07, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0xFF, 0xFF, 0xCF,
- 0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xFF,
- 0x9F, 0xFF, 0xFF, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x01,
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- 0x80, 0x0F, 0xE0, 0x01, 0xF8, 0x00, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x01,
- 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x01, 0xE0, 0x0F, 0x00, 0x78,
- 0x03, 0xC0, 0x1C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3C, 0x01,
- 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78,
- 0x03, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x01,
- 0xE0, 0x0F, 0x00, 0x70, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x70,
- 0x07, 0x80, 0x3C, 0x00, 0x00, 0x7E, 0x00, 0x1F, 0xC0, 0x07, 0xF0, 0x01,
- 0xFE, 0x00, 0x7F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x1F,
- 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x0F, 0x80,
- 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xF0, 0x00,
- 0xFF, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x07, 0xF8, 0x03, 0xF0, 0x00, 0xF8,
- 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00,
- 0x1F, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x1F,
- 0x80, 0x07, 0xC0, 0x01, 0xF0, 0x07, 0xFC, 0x01, 0xFE, 0x00, 0xFF, 0x80,
- 0x3F, 0xC0, 0x0F, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0x80, 0x07, 0xFF,
- 0x03, 0xDF, 0xFE, 0x0F, 0xF0, 0x7F, 0xFB, 0x80, 0xFF, 0xE0, 0x01, 0xFF,
- 0x00, 0x03, 0xF0 };
-
-const GFXglyph FreeSansBoldOblique24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 13, 0, 1 }, // 0x20 ' '
- { 0, 14, 34, 16, 5, -33 }, // 0x21 '!'
- { 60, 18, 12, 22, 8, -33 }, // 0x22 '"'
- { 87, 29, 33, 26, 2, -31 }, // 0x23 '#'
- { 207, 26, 42, 26, 3, -35 }, // 0x24 '$'
- { 344, 36, 34, 42, 6, -32 }, // 0x25 '%'
- { 497, 29, 35, 34, 4, -33 }, // 0x26 '&'
- { 624, 7, 12, 11, 8, -33 }, // 0x27 '''
- { 635, 17, 44, 16, 4, -33 }, // 0x28 '('
- { 729, 17, 44, 16, 0, -34 }, // 0x29 ')'
- { 823, 15, 15, 18, 7, -33 }, // 0x2A '*'
- { 852, 24, 22, 27, 4, -21 }, // 0x2B '+'
- { 918, 10, 15, 13, 1, -6 }, // 0x2C ','
- { 937, 14, 6, 16, 3, -15 }, // 0x2D '-'
- { 948, 8, 7, 13, 3, -6 }, // 0x2E '.'
- { 955, 20, 34, 13, 0, -32 }, // 0x2F '/'
- { 1040, 25, 35, 26, 4, -33 }, // 0x30 '0'
- { 1150, 17, 33, 26, 8, -32 }, // 0x31 '1'
- { 1221, 29, 34, 26, 1, -33 }, // 0x32 '2'
- { 1345, 26, 35, 26, 3, -33 }, // 0x33 '3'
- { 1459, 25, 32, 26, 3, -31 }, // 0x34 '4'
- { 1559, 27, 34, 26, 3, -32 }, // 0x35 '5'
- { 1674, 25, 35, 26, 4, -33 }, // 0x36 '6'
- { 1784, 26, 33, 26, 6, -32 }, // 0x37 '7'
- { 1892, 26, 35, 26, 3, -33 }, // 0x38 '8'
- { 2006, 25, 35, 26, 4, -33 }, // 0x39 '9'
- { 2116, 12, 25, 16, 5, -24 }, // 0x3A ':'
- { 2154, 14, 33, 16, 3, -24 }, // 0x3B ';'
- { 2212, 26, 23, 27, 4, -22 }, // 0x3C '<'
- { 2287, 26, 18, 27, 3, -19 }, // 0x3D '='
- { 2346, 26, 23, 27, 1, -21 }, // 0x3E '>'
- { 2421, 24, 35, 29, 8, -34 }, // 0x3F '?'
- { 2526, 45, 41, 46, 3, -34 }, // 0x40 '@'
- { 2757, 32, 34, 34, 1, -33 }, // 0x41 'A'
- { 2893, 32, 34, 34, 4, -33 }, // 0x42 'B'
- { 3029, 32, 36, 34, 5, -34 }, // 0x43 'C'
- { 3173, 32, 34, 34, 4, -33 }, // 0x44 'D'
- { 3309, 32, 34, 31, 4, -33 }, // 0x45 'E'
- { 3445, 32, 34, 29, 3, -33 }, // 0x46 'F'
- { 3581, 33, 36, 37, 5, -34 }, // 0x47 'G'
- { 3730, 35, 34, 34, 3, -33 }, // 0x48 'H'
- { 3879, 14, 34, 13, 3, -33 }, // 0x49 'I'
- { 3939, 27, 35, 26, 3, -33 }, // 0x4A 'J'
- { 4058, 37, 34, 34, 3, -33 }, // 0x4B 'K'
- { 4216, 24, 34, 29, 4, -33 }, // 0x4C 'L'
- { 4318, 41, 34, 39, 3, -33 }, // 0x4D 'M'
- { 4493, 35, 34, 34, 3, -33 }, // 0x4E 'N'
- { 4642, 34, 36, 37, 5, -34 }, // 0x4F 'O'
- { 4795, 31, 34, 31, 4, -33 }, // 0x50 'P'
- { 4927, 34, 37, 37, 5, -34 }, // 0x51 'Q'
- { 5085, 33, 34, 34, 4, -33 }, // 0x52 'R'
- { 5226, 30, 36, 31, 4, -34 }, // 0x53 'S'
- { 5361, 28, 34, 29, 7, -33 }, // 0x54 'T'
- { 5480, 32, 35, 34, 6, -33 }, // 0x55 'U'
- { 5620, 30, 34, 31, 8, -33 }, // 0x56 'V'
- { 5748, 43, 34, 44, 8, -33 }, // 0x57 'W'
- { 5931, 37, 34, 31, 1, -33 }, // 0x58 'X'
- { 6089, 29, 34, 31, 9, -33 }, // 0x59 'Y'
- { 6213, 33, 34, 29, 1, -33 }, // 0x5A 'Z'
- { 6354, 21, 43, 16, 1, -33 }, // 0x5B '['
- { 6467, 7, 36, 13, 6, -34 }, // 0x5C '\'
- { 6499, 21, 43, 16, -1, -33 }, // 0x5D ']'
- { 6612, 21, 20, 27, 6, -32 }, // 0x5E '^'
- { 6665, 29, 4, 26, -3, 6 }, // 0x5F '_'
- { 6680, 7, 7, 16, 8, -35 }, // 0x60 '`'
- { 6687, 25, 26, 26, 2, -24 }, // 0x61 'a'
- { 6769, 27, 35, 29, 3, -33 }, // 0x62 'b'
- { 6888, 25, 26, 26, 4, -24 }, // 0x63 'c'
- { 6970, 29, 35, 29, 4, -33 }, // 0x64 'd'
- { 7097, 25, 26, 26, 3, -24 }, // 0x65 'e'
- { 7179, 18, 34, 16, 4, -33 }, // 0x66 'f'
- { 7256, 29, 35, 29, 2, -24 }, // 0x67 'g'
- { 7383, 27, 34, 29, 3, -33 }, // 0x68 'h'
- { 7498, 14, 34, 13, 3, -33 }, // 0x69 'i'
- { 7558, 19, 44, 13, -2, -33 }, // 0x6A 'j'
- { 7663, 28, 34, 26, 3, -33 }, // 0x6B 'k'
- { 7782, 14, 34, 13, 3, -33 }, // 0x6C 'l'
- { 7842, 40, 25, 42, 3, -24 }, // 0x6D 'm'
- { 7967, 27, 25, 29, 3, -24 }, // 0x6E 'n'
- { 8052, 26, 26, 29, 4, -24 }, // 0x6F 'o'
- { 8137, 29, 35, 29, 1, -24 }, // 0x70 'p'
- { 8264, 28, 35, 29, 3, -24 }, // 0x71 'q'
- { 8387, 20, 25, 18, 3, -24 }, // 0x72 'r'
- { 8450, 24, 26, 26, 3, -24 }, // 0x73 's'
- { 8528, 14, 32, 16, 5, -30 }, // 0x74 't'
- { 8584, 27, 26, 29, 4, -24 }, // 0x75 'u'
- { 8672, 25, 25, 26, 6, -24 }, // 0x76 'v'
- { 8751, 35, 25, 37, 6, -24 }, // 0x77 'w'
- { 8861, 29, 25, 26, 1, -24 }, // 0x78 'x'
- { 8952, 29, 35, 26, 2, -24 }, // 0x79 'y'
- { 9079, 26, 25, 23, 1, -24 }, // 0x7A 'z'
- { 9161, 18, 43, 18, 4, -33 }, // 0x7B '{'
- { 9258, 13, 43, 13, 3, -33 }, // 0x7C '|'
- { 9328, 18, 43, 18, 2, -33 }, // 0x7D '}'
- { 9425, 22, 8, 27, 5, -14 } }; // 0x7E '~'
-
-const GFXfont FreeSansBoldOblique24pt7b PROGMEM = {
- (uint8_t *)FreeSansBoldOblique24pt7bBitmaps,
- (GFXglyph *)FreeSansBoldOblique24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 10119 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique9pt7b.h
deleted file mode 100644
index 6250aca..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansBoldOblique9pt7b.h
+++ /dev/null
@@ -1,227 +0,0 @@
-const uint8_t FreeSansBoldOblique9pt7bBitmaps[] PROGMEM = {
- 0x21, 0x8E, 0x73, 0x18, 0xC6, 0x21, 0x19, 0xCE, 0x00, 0xEF, 0xDF, 0xBE,
- 0x68, 0x80, 0x06, 0xC1, 0x99, 0xFF, 0xBF, 0xF1, 0xB0, 0x66, 0x0C, 0xC7,
- 0xFC, 0xFF, 0x8C, 0x83, 0x30, 0x64, 0x00, 0x02, 0x00, 0xF0, 0x7F, 0x1D,
- 0x73, 0xEE, 0x78, 0x0F, 0x00, 0xF8, 0x0F, 0xC1, 0xBB, 0xA7, 0x74, 0xEF,
- 0xF8, 0xFE, 0x04, 0x00, 0x80, 0x3C, 0x11, 0xF8, 0x8E, 0x66, 0x31, 0x90,
- 0xCE, 0x83, 0xF4, 0x07, 0xB0, 0x00, 0x9E, 0x04, 0xFC, 0x26, 0x31, 0x98,
- 0xC4, 0x7E, 0x20, 0xF0, 0x07, 0x80, 0xFC, 0x1D, 0xC1, 0xDC, 0x1F, 0x80,
- 0xE0, 0x3E, 0x37, 0x77, 0xE3, 0xEE, 0x3C, 0xE3, 0xCF, 0xFE, 0x3C, 0xE0,
- 0xFF, 0xE8, 0x06, 0x06, 0x0C, 0x18, 0x38, 0x30, 0x70, 0x60, 0xE0, 0xE0,
- 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x70, 0x30, 0x0C, 0x0E, 0x06, 0x07, 0x07,
- 0x07, 0x07, 0x07, 0x07, 0x06, 0x0E, 0x0C, 0x1C, 0x18, 0x30, 0x60, 0x60,
- 0x32, 0xBF, 0x9C, 0xD2, 0x40, 0x0C, 0x06, 0x07, 0x1F, 0xFF, 0xF0, 0xC0,
- 0xE0, 0x60, 0x77, 0x72, 0x6C, 0xFF, 0xC0, 0xFC, 0x02, 0x02, 0x04, 0x04,
- 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x40, 0x40, 0x80, 0x0F, 0x07, 0xE3,
- 0x9D, 0xC7, 0x71, 0xDC, 0x7E, 0x1F, 0x8E, 0xE3, 0xB8, 0xEE, 0x73, 0xF8,
- 0x3C, 0x00, 0x04, 0x3B, 0xF7, 0xE1, 0xC3, 0x06, 0x1C, 0x38, 0x70, 0xC1,
- 0x87, 0x00, 0x0F, 0x87, 0xFC, 0xE3, 0xB8, 0x70, 0x0E, 0x03, 0x80, 0xF0,
- 0x38, 0x1E, 0x07, 0x01, 0xC0, 0x7F, 0xCF, 0xF8, 0x0F, 0xC7, 0xFC, 0xE3,
- 0xB8, 0x70, 0x1C, 0x0F, 0x03, 0xF0, 0x0E, 0x01, 0xDC, 0x3B, 0x8E, 0x7F,
- 0x83, 0xE0, 0x03, 0xC0, 0xE0, 0x58, 0x2E, 0x13, 0x8C, 0xE6, 0x33, 0xFE,
- 0xFF, 0x81, 0xC0, 0x60, 0x18, 0x0F, 0xE3, 0xFC, 0x60, 0x0C, 0x03, 0x78,
- 0x7F, 0x9C, 0x70, 0x0E, 0x01, 0xDC, 0x33, 0x8E, 0x7F, 0x83, 0xE0, 0x0F,
- 0x07, 0xE3, 0x9D, 0xC0, 0x7F, 0x1F, 0xEF, 0x3B, 0x8E, 0xE3, 0xB8, 0xCE,
- 0x71, 0xF8, 0x3C, 0x00, 0x7F, 0xDF, 0xF0, 0x18, 0x0C, 0x06, 0x03, 0x81,
- 0xC0, 0x60, 0x38, 0x0C, 0x07, 0x01, 0x80, 0x60, 0x00, 0x0F, 0x83, 0xFC,
- 0xE3, 0x9C, 0x73, 0x9C, 0x3F, 0x0F, 0xE3, 0x8E, 0xE1, 0xDC, 0x3B, 0x8E,
- 0x7F, 0xC3, 0xE0, 0x0F, 0x83, 0xF8, 0xE3, 0xB8, 0x77, 0x0E, 0xE1, 0xDC,
- 0x7B, 0xFE, 0x3D, 0xC0, 0x33, 0x8E, 0x7F, 0x87, 0xC0, 0x77, 0x00, 0x00,
- 0x0E, 0xE0, 0x39, 0xC0, 0x00, 0x01, 0xCE, 0x71, 0x19, 0x80, 0x00, 0x00,
- 0x70, 0xFD, 0xF8, 0x70, 0x3F, 0x03, 0xF8, 0x1E, 0x01, 0x80, 0x7F, 0xDF,
- 0xF0, 0x00, 0x00, 0xFF, 0xBF, 0xE0, 0x60, 0x1E, 0x07, 0xF0, 0x3F, 0x03,
- 0x87, 0xEF, 0xC3, 0x80, 0x00, 0x00, 0x1F, 0x1F, 0xFE, 0x1F, 0x87, 0x01,
- 0xC0, 0xE0, 0x70, 0x78, 0x3C, 0x0E, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00,
- 0xFC, 0x00, 0xFF, 0xC0, 0xF0, 0x78, 0x70, 0x07, 0x38, 0x01, 0xCC, 0x3F,
- 0x36, 0x31, 0x8D, 0x98, 0x63, 0xC4, 0x11, 0xF3, 0x0C, 0x6C, 0xC6, 0x73,
- 0x3E, 0xF8, 0xE7, 0x3C, 0x1E, 0x00, 0x03, 0xFE, 0x00, 0x3F, 0x00, 0x01,
- 0xE0, 0x0F, 0x00, 0xF8, 0x07, 0xC0, 0x6F, 0x03, 0x38, 0x31, 0xC3, 0x8E,
- 0x1F, 0xF1, 0xFF, 0x8C, 0x1E, 0xE0, 0x76, 0x03, 0x80, 0x1F, 0xF0, 0xFF,
- 0xC6, 0x0E, 0x70, 0x73, 0x87, 0x1F, 0xF0, 0xFF, 0x86, 0x0E, 0x70, 0x73,
- 0x83, 0x9C, 0x38, 0xFF, 0xC7, 0xF8, 0x00, 0x07, 0xE0, 0xFF, 0x8F, 0x1E,
- 0x70, 0x77, 0x00, 0x30, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x03, 0xBC,
- 0x38, 0xFF, 0x83, 0xF0, 0x00, 0x1F, 0xE0, 0xFF, 0x86, 0x1E, 0x70, 0x73,
- 0x83, 0x9C, 0x1C, 0xC0, 0xE6, 0x07, 0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF,
- 0x8F, 0xF0, 0x00, 0x1F, 0xF8, 0xFF, 0x86, 0x00, 0x70, 0x03, 0x80, 0x1F,
- 0xF0, 0xFF, 0x86, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xFF, 0xC7, 0xFC,
- 0x00, 0x1F, 0xF1, 0xFF, 0x18, 0x03, 0x80, 0x38, 0x03, 0xFC, 0x3F, 0xC7,
- 0x00, 0x70, 0x07, 0x00, 0x70, 0x06, 0x00, 0xE0, 0x00, 0x07, 0xC1, 0xFE,
- 0x38, 0x77, 0x03, 0x70, 0x0E, 0x00, 0xE1, 0xEE, 0x1E, 0xE0, 0x6E, 0x0E,
- 0x70, 0xE7, 0xFC, 0x1F, 0x40, 0x1C, 0x1C, 0x60, 0x63, 0x83, 0x8E, 0x0E,
- 0x38, 0x38, 0xFF, 0xC3, 0xFF, 0x1C, 0x1C, 0x70, 0x71, 0xC1, 0xC6, 0x06,
- 0x18, 0x38, 0xE0, 0xE0, 0x39, 0xCE, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE,
- 0x00, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x00, 0xE0, 0x1C,
- 0xE3, 0x9C, 0x73, 0x9C, 0x7F, 0x87, 0xC0, 0x1C, 0x3C, 0x71, 0xC1, 0x8E,
- 0x0E, 0x70, 0x3B, 0x80, 0xFC, 0x03, 0xF0, 0x0E, 0xE0, 0x73, 0x81, 0xC7,
- 0x07, 0x1C, 0x18, 0x38, 0xE0, 0xF0, 0x1C, 0x07, 0x01, 0x80, 0xE0, 0x38,
- 0x0E, 0x03, 0x80, 0xC0, 0x70, 0x1C, 0x07, 0x01, 0xFF, 0x7F, 0x80, 0x1E,
- 0x1F, 0x1E, 0x1E, 0x3E, 0x1E, 0x3E, 0x3E, 0x36, 0x3E, 0x36, 0x6E, 0x36,
- 0x6C, 0x76, 0xCC, 0x76, 0xDC, 0x67, 0x9C, 0x67, 0x98, 0xE7, 0x18, 0xE7,
- 0x18, 0x1C, 0x1C, 0x70, 0x63, 0xE1, 0x8F, 0x8E, 0x3E, 0x38, 0xDC, 0xC3,
- 0x33, 0x1C, 0xEC, 0x71, 0xF1, 0xC7, 0xC6, 0x1E, 0x18, 0x38, 0xE0, 0xE0,
- 0x07, 0xC0, 0xFF, 0x8E, 0x1E, 0xE0, 0x77, 0x03, 0xF0, 0x1F, 0x80, 0xFC,
- 0x07, 0xE0, 0x77, 0x03, 0xBC, 0x38, 0xFF, 0x81, 0xF0, 0x00, 0x1F, 0xF0,
- 0xFF, 0xC6, 0x0E, 0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF, 0x87, 0xF8, 0x70,
- 0x03, 0x80, 0x1C, 0x00, 0xC0, 0x0E, 0x00, 0x00, 0x07, 0xC0, 0xFF, 0x8F,
- 0x1C, 0xE0, 0x77, 0x03, 0xB0, 0x1F, 0x80, 0xFC, 0x06, 0xE1, 0x77, 0x1F,
- 0x3C, 0x78, 0xFF, 0xC1, 0xF6, 0x00, 0x20, 0x1F, 0xF0, 0xFF, 0xC6, 0x0E,
- 0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF, 0x87, 0xFC, 0x70, 0x73, 0x83, 0x9C,
- 0x38, 0xC1, 0xC6, 0x0F, 0x00, 0x07, 0xE0, 0xFF, 0xC7, 0x0E, 0x70, 0x73,
- 0x80, 0x1F, 0x80, 0x7F, 0x80, 0x7E, 0x00, 0x77, 0x03, 0xBC, 0x38, 0xFF,
- 0xC3, 0xF8, 0x00, 0xFF, 0xDF, 0xF8, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x06,
- 0x01, 0xC0, 0x38, 0x07, 0x00, 0xC0, 0x18, 0x07, 0x00, 0x38, 0x31, 0xC1,
- 0x8C, 0x1C, 0xE0, 0xE7, 0x07, 0x38, 0x31, 0xC3, 0x9C, 0x1C, 0xE0, 0xE7,
- 0x06, 0x38, 0x70, 0xFF, 0x03, 0xE0, 0x00, 0xE0, 0xFC, 0x1D, 0x87, 0x30,
- 0xC6, 0x38, 0xC6, 0x19, 0xC3, 0xB0, 0x7E, 0x0F, 0x80, 0xF0, 0x1C, 0x03,
- 0x00, 0xE1, 0xC3, 0xF1, 0xE3, 0xB8, 0xF1, 0xDC, 0x78, 0xCE, 0x6C, 0xE7,
- 0x36, 0x63, 0xB3, 0x70, 0xD9, 0xB0, 0x7C, 0xD8, 0x3C, 0x78, 0x1E, 0x3C,
- 0x0E, 0x1C, 0x07, 0x0E, 0x00, 0x0E, 0x1C, 0x38, 0xE0, 0xE7, 0x01, 0xD8,
- 0x07, 0xE0, 0x0F, 0x00, 0x38, 0x01, 0xE0, 0x0F, 0xC0, 0x77, 0x01, 0x8E,
- 0x0E, 0x38, 0x70, 0xF0, 0xE0, 0xEE, 0x39, 0xC7, 0x39, 0xC3, 0x70, 0x7C,
- 0x0F, 0x80, 0xE0, 0x1C, 0x03, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x3F, 0xF3,
- 0xFF, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x3C, 0x07,
- 0x80, 0x70, 0x0F, 0xFC, 0xFF, 0xC0, 0x0F, 0x0F, 0x0C, 0x1C, 0x18, 0x18,
- 0x18, 0x18, 0x30, 0x30, 0x30, 0x30, 0x60, 0x60, 0x60, 0x78, 0x78, 0x12,
- 0x4C, 0x92, 0x49, 0x26, 0xD9, 0x20, 0x1E, 0x1E, 0x06, 0x06, 0x06, 0x0C,
- 0x0C, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x38, 0x30, 0xF0, 0xF0, 0x06,
- 0x0E, 0x0E, 0x1B, 0x33, 0x33, 0x63, 0x63, 0xFF, 0xE0, 0xCC, 0x1F, 0x8F,
- 0xF3, 0x1C, 0x06, 0x1F, 0x9F, 0xEE, 0x3B, 0x9C, 0xFF, 0x1D, 0xC0, 0x18,
- 0x03, 0x00, 0xE0, 0x1D, 0xC3, 0xFC, 0x71, 0xDC, 0x3B, 0x87, 0x70, 0xEE,
- 0x39, 0xCF, 0x7F, 0xCF, 0xE0, 0x0F, 0x0F, 0xF7, 0x1D, 0xC0, 0xE0, 0x38,
- 0x0E, 0x03, 0x8E, 0x7F, 0x0F, 0x80, 0x00, 0x60, 0x06, 0x00, 0x61, 0xEE,
- 0x3F, 0xE7, 0x9C, 0x71, 0xCE, 0x1C, 0xE1, 0xCE, 0x1C, 0xE3, 0x87, 0xF8,
- 0x7F, 0x80, 0x1F, 0x0F, 0xE7, 0x1D, 0xC7, 0xFF, 0xFF, 0xFE, 0x03, 0x8E,
- 0x7F, 0x0F, 0x80, 0x1C, 0xF3, 0x3F, 0xFD, 0xC7, 0x18, 0x63, 0x8E, 0x30,
- 0xC0, 0x0F, 0x71, 0xFE, 0x3C, 0xE3, 0x8E, 0x70, 0xE7, 0x0E, 0x70, 0xC7,
- 0x1C, 0x3F, 0xC3, 0xFC, 0x01, 0xCE, 0x38, 0x7F, 0x03, 0xE0, 0x18, 0x03,
- 0x00, 0xE0, 0x1D, 0xE3, 0xFE, 0x71, 0xCC, 0x3B, 0x86, 0x70, 0xCC, 0x39,
- 0x87, 0x30, 0xEE, 0x18, 0x39, 0xC0, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE,
- 0x00, 0x06, 0x06, 0x00, 0x0E, 0x0E, 0x0C, 0x0C, 0x1C, 0x1C, 0x1C, 0x18,
- 0x18, 0x38, 0x38, 0x30, 0x70, 0xE0, 0x18, 0x03, 0x00, 0xE0, 0x1C, 0xE3,
- 0x38, 0x6E, 0x1F, 0x83, 0xF0, 0x7E, 0x0E, 0xE1, 0x9C, 0x73, 0x8E, 0x38,
- 0x39, 0xCE, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE, 0x00, 0x3B, 0x9E, 0x3F,
- 0xFF, 0x39, 0xC7, 0x71, 0xC6, 0x71, 0x86, 0x71, 0x8E, 0x63, 0x8E, 0x63,
- 0x8C, 0xE3, 0x8C, 0xE3, 0x1C, 0x3B, 0xC7, 0xFC, 0xE3, 0xB8, 0x77, 0x0C,
- 0xE1, 0x98, 0x73, 0x0E, 0xE1, 0xDC, 0x30, 0x0F, 0x87, 0xF9, 0xE7, 0xB8,
- 0x7E, 0x0F, 0xC1, 0xF8, 0x77, 0x9E, 0x7F, 0x87, 0xC0, 0x1D, 0xE1, 0xFE,
- 0x1C, 0x73, 0x87, 0x38, 0x73, 0x87, 0x38, 0xE3, 0x8E, 0x7F, 0xC7, 0xF8,
- 0x60, 0x06, 0x00, 0x60, 0x0E, 0x00, 0x1E, 0xE7, 0xFD, 0xE7, 0x38, 0xEE,
- 0x1D, 0xC3, 0xB8, 0x77, 0x1C, 0x7F, 0x8F, 0xF0, 0x0E, 0x01, 0x80, 0x30,
- 0x06, 0x00, 0x3B, 0x36, 0x38, 0x70, 0x70, 0x70, 0x60, 0x60, 0xE0, 0xE0,
- 0x3E, 0x3F, 0xF8, 0xFC, 0x0F, 0xC3, 0xF8, 0x3D, 0x8E, 0xFE, 0x3E, 0x00,
- 0x38, 0xCF, 0xFE, 0x71, 0x86, 0x38, 0xE3, 0x8F, 0x3C, 0x31, 0xDC, 0x77,
- 0x19, 0x86, 0x63, 0xB8, 0xEE, 0x33, 0x9C, 0xFF, 0x1F, 0xC0, 0xE1, 0x98,
- 0xE6, 0x31, 0x9C, 0x66, 0x1B, 0x86, 0xC1, 0xF0, 0x78, 0x0E, 0x00, 0xE7,
- 0x1B, 0x9C, 0xEE, 0x73, 0x3B, 0xDC, 0xEB, 0x63, 0xAD, 0x8F, 0xBC, 0x1C,
- 0xF0, 0x73, 0xC1, 0xCE, 0x00, 0x1C, 0xE1, 0xCC, 0x0D, 0x80, 0xF8, 0x0F,
- 0x00, 0xF0, 0x1F, 0x03, 0xB8, 0x33, 0x87, 0x38, 0x70, 0xCE, 0x38, 0xC6,
- 0x19, 0xC3, 0x30, 0x66, 0x0F, 0x81, 0xF0, 0x3C, 0x03, 0x80, 0x60, 0x18,
- 0x0F, 0x01, 0xC0, 0x00, 0x1F, 0xCF, 0xF0, 0x38, 0x1C, 0x0E, 0x07, 0x03,
- 0x81, 0xC0, 0x7F, 0xBF, 0xE0, 0x0E, 0x38, 0x61, 0x83, 0x06, 0x0C, 0x78,
- 0xF0, 0xC1, 0x83, 0x0E, 0x1C, 0x38, 0x78, 0x70, 0x18, 0xC4, 0x21, 0x18,
- 0xC4, 0x21, 0x18, 0xC4, 0x23, 0x18, 0x80, 0x1C, 0x3C, 0x38, 0x70, 0xE1,
- 0x83, 0x06, 0x1E, 0x5C, 0x60, 0xC1, 0x83, 0x0C, 0x38, 0xE0, 0x71, 0x8E };
-
-const GFXglyph FreeSansBoldOblique9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 5, 13, 6, 2, -12 }, // 0x21 '!'
- { 9, 7, 5, 9, 3, -12 }, // 0x22 '"'
- { 14, 11, 12, 10, 1, -11 }, // 0x23 '#'
- { 31, 11, 16, 10, 1, -13 }, // 0x24 '$'
- { 53, 14, 13, 16, 2, -12 }, // 0x25 '%'
- { 76, 12, 13, 13, 2, -12 }, // 0x26 '&'
- { 96, 3, 5, 4, 3, -12 }, // 0x27 '''
- { 98, 8, 17, 6, 2, -12 }, // 0x28 '('
- { 115, 8, 17, 6, -2, -13 }, // 0x29 ')'
- { 132, 6, 6, 7, 3, -12 }, // 0x2A '*'
- { 137, 9, 8, 11, 2, -7 }, // 0x2B '+'
- { 146, 4, 6, 5, 0, -2 }, // 0x2C ','
- { 149, 5, 2, 6, 1, -5 }, // 0x2D '-'
- { 151, 3, 2, 5, 1, -1 }, // 0x2E '.'
- { 152, 8, 13, 5, 0, -12 }, // 0x2F '/'
- { 165, 10, 13, 10, 1, -12 }, // 0x30 '0'
- { 182, 7, 13, 10, 3, -12 }, // 0x31 '1'
- { 194, 11, 13, 10, 1, -12 }, // 0x32 '2'
- { 212, 11, 13, 10, 1, -12 }, // 0x33 '3'
- { 230, 10, 12, 10, 1, -11 }, // 0x34 '4'
- { 245, 11, 13, 10, 1, -12 }, // 0x35 '5'
- { 263, 10, 13, 10, 2, -12 }, // 0x36 '6'
- { 280, 10, 13, 10, 2, -12 }, // 0x37 '7'
- { 297, 11, 13, 10, 1, -12 }, // 0x38 '8'
- { 315, 11, 13, 10, 1, -12 }, // 0x39 '9'
- { 333, 4, 9, 6, 2, -8 }, // 0x3A ':'
- { 338, 5, 12, 6, 1, -8 }, // 0x3B ';'
- { 346, 10, 9, 11, 1, -8 }, // 0x3C '<'
- { 358, 10, 6, 11, 1, -6 }, // 0x3D '='
- { 366, 10, 9, 11, 1, -7 }, // 0x3E '>'
- { 378, 10, 13, 11, 3, -12 }, // 0x3F '?'
- { 395, 18, 16, 18, 1, -13 }, // 0x40 '@'
- { 431, 13, 13, 13, 0, -12 }, // 0x41 'A'
- { 453, 13, 13, 13, 1, -12 }, // 0x42 'B'
- { 475, 13, 13, 13, 2, -12 }, // 0x43 'C'
- { 497, 13, 13, 13, 1, -12 }, // 0x44 'D'
- { 519, 13, 13, 12, 1, -12 }, // 0x45 'E'
- { 541, 12, 13, 11, 1, -12 }, // 0x46 'F'
- { 561, 12, 13, 14, 2, -12 }, // 0x47 'G'
- { 581, 14, 13, 13, 1, -12 }, // 0x48 'H'
- { 604, 5, 13, 5, 1, -12 }, // 0x49 'I'
- { 613, 11, 13, 10, 1, -12 }, // 0x4A 'J'
- { 631, 14, 13, 13, 1, -12 }, // 0x4B 'K'
- { 654, 10, 13, 11, 1, -12 }, // 0x4C 'L'
- { 671, 16, 13, 15, 1, -12 }, // 0x4D 'M'
- { 697, 14, 13, 13, 1, -12 }, // 0x4E 'N'
- { 720, 13, 13, 14, 2, -12 }, // 0x4F 'O'
- { 742, 13, 13, 12, 1, -12 }, // 0x50 'P'
- { 764, 13, 14, 14, 2, -12 }, // 0x51 'Q'
- { 787, 13, 13, 13, 1, -12 }, // 0x52 'R'
- { 809, 13, 13, 12, 1, -12 }, // 0x53 'S'
- { 831, 11, 13, 11, 3, -12 }, // 0x54 'T'
- { 849, 13, 13, 13, 2, -12 }, // 0x55 'U'
- { 871, 11, 13, 12, 3, -12 }, // 0x56 'V'
- { 889, 17, 13, 17, 3, -12 }, // 0x57 'W'
- { 917, 14, 13, 12, 0, -12 }, // 0x58 'X'
- { 940, 11, 13, 12, 3, -12 }, // 0x59 'Y'
- { 958, 12, 13, 11, 1, -12 }, // 0x5A 'Z'
- { 978, 8, 17, 6, 0, -12 }, // 0x5B '['
- { 995, 3, 17, 5, 2, -16 }, // 0x5C '\'
- { 1002, 8, 17, 6, 0, -13 }, // 0x5D ']'
- { 1019, 8, 8, 11, 2, -12 }, // 0x5E '^'
- { 1027, 11, 1, 10, -1, 4 }, // 0x5F '_'
- { 1029, 3, 2, 6, 3, -12 }, // 0x60 '`'
- { 1030, 10, 10, 10, 1, -9 }, // 0x61 'a'
- { 1043, 11, 13, 11, 1, -12 }, // 0x62 'b'
- { 1061, 10, 10, 10, 1, -9 }, // 0x63 'c'
- { 1074, 12, 13, 11, 1, -12 }, // 0x64 'd'
- { 1094, 10, 10, 10, 1, -9 }, // 0x65 'e'
- { 1107, 6, 13, 6, 2, -12 }, // 0x66 'f'
- { 1117, 12, 14, 11, 0, -9 }, // 0x67 'g'
- { 1138, 11, 13, 11, 1, -12 }, // 0x68 'h'
- { 1156, 5, 13, 5, 1, -12 }, // 0x69 'i'
- { 1165, 8, 17, 5, -1, -12 }, // 0x6A 'j'
- { 1182, 11, 13, 10, 1, -12 }, // 0x6B 'k'
- { 1200, 5, 13, 5, 1, -12 }, // 0x6C 'l'
- { 1209, 16, 10, 16, 1, -9 }, // 0x6D 'm'
- { 1229, 11, 10, 11, 1, -9 }, // 0x6E 'n'
- { 1243, 11, 10, 11, 1, -9 }, // 0x6F 'o'
- { 1257, 12, 14, 11, 0, -9 }, // 0x70 'p'
- { 1278, 11, 14, 11, 1, -9 }, // 0x71 'q'
- { 1298, 8, 10, 7, 1, -9 }, // 0x72 'r'
- { 1308, 9, 10, 10, 2, -9 }, // 0x73 's'
- { 1320, 6, 12, 6, 2, -11 }, // 0x74 't'
- { 1329, 10, 10, 11, 2, -9 }, // 0x75 'u'
- { 1342, 10, 10, 10, 2, -9 }, // 0x76 'v'
- { 1355, 14, 10, 14, 2, -9 }, // 0x77 'w'
- { 1373, 12, 10, 10, 0, -9 }, // 0x78 'x'
- { 1388, 11, 14, 10, 1, -9 }, // 0x79 'y'
- { 1408, 10, 10, 9, 0, -9 }, // 0x7A 'z'
- { 1421, 7, 17, 7, 2, -12 }, // 0x7B '{'
- { 1436, 5, 17, 5, 1, -12 }, // 0x7C '|'
- { 1447, 7, 17, 7, 0, -13 }, // 0x7D '}'
- { 1462, 8, 2, 11, 2, -4 } }; // 0x7E '~'
-
-const GFXfont FreeSansBoldOblique9pt7b PROGMEM = {
- (uint8_t *)FreeSansBoldOblique9pt7bBitmaps,
- (GFXglyph *)FreeSansBoldOblique9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 2136 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique12pt7b.h
deleted file mode 100644
index efdbd8d..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique12pt7b.h
+++ /dev/null
@@ -1,302 +0,0 @@
-const uint8_t FreeSansOblique12pt7bBitmaps[] PROGMEM = {
- 0x0C, 0x61, 0x86, 0x18, 0x63, 0x0C, 0x30, 0xC2, 0x18, 0x61, 0x00, 0x00,
- 0xC3, 0x00, 0xCF, 0x3C, 0xE2, 0x8A, 0x20, 0x01, 0x8C, 0x03, 0x18, 0x06,
- 0x60, 0x18, 0xC0, 0x31, 0x83, 0xFF, 0x87, 0xFF, 0x03, 0x18, 0x0C, 0x60,
- 0x18, 0xC0, 0x23, 0x03, 0xFF, 0x8F, 0xFF, 0x02, 0x30, 0x0C, 0x60, 0x18,
- 0x80, 0x63, 0x00, 0xC6, 0x00, 0x00, 0x80, 0x3F, 0x03, 0xFC, 0x32, 0x73,
- 0x91, 0x99, 0x8C, 0xCC, 0x06, 0x60, 0x3E, 0x00, 0x7E, 0x01, 0xFC, 0x0C,
- 0xEC, 0x43, 0x62, 0x1B, 0x11, 0x9D, 0x9C, 0x7F, 0xC1, 0xF8, 0x02, 0x00,
- 0x10, 0x01, 0x80, 0x00, 0x00, 0x01, 0x83, 0xC0, 0x60, 0xFC, 0x18, 0x30,
- 0xC2, 0x0C, 0x18, 0xC1, 0x83, 0x30, 0x38, 0xCC, 0x03, 0xF1, 0x00, 0x3C,
- 0x40, 0x00, 0x18, 0xF0, 0x06, 0x3F, 0x01, 0x8C, 0x30, 0x23, 0x06, 0x0C,
- 0x60, 0xC3, 0x0E, 0x30, 0xC0, 0xFC, 0x10, 0x0F, 0x00, 0x01, 0xE0, 0x3F,
- 0x81, 0x8C, 0x18, 0x60, 0xC3, 0x06, 0x30, 0x1F, 0x00, 0xE0, 0x1F, 0x01,
- 0xDC, 0xD8, 0x6D, 0x81, 0xEC, 0x0E, 0x60, 0x73, 0x87, 0xCF, 0xE6, 0x3E,
- 0x38, 0xFE, 0xA0, 0x03, 0x06, 0x04, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60,
- 0x60, 0x60, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x40, 0x60,
- 0x60, 0x20, 0x04, 0x06, 0x06, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x06, 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x20, 0x60,
- 0xC0, 0x0C, 0x0C, 0x49, 0x7F, 0x3C, 0x3C, 0x6C, 0x00, 0x03, 0x00, 0x30,
- 0x03, 0x00, 0x30, 0xFF, 0xFF, 0xFF, 0x06, 0x00, 0x60, 0x06, 0x00, 0xC0,
- 0x0C, 0x00, 0x77, 0x22, 0x6C, 0xFF, 0xF0, 0xFC, 0x00, 0x40, 0x30, 0x08,
- 0x06, 0x01, 0x00, 0xC0, 0x20, 0x18, 0x04, 0x02, 0x00, 0x80, 0x40, 0x10,
- 0x08, 0x02, 0x01, 0x00, 0xC0, 0x20, 0x00, 0x07, 0xC0, 0xFE, 0x1C, 0x73,
- 0x83, 0x30, 0x36, 0x03, 0x60, 0x36, 0x03, 0xC0, 0x7C, 0x07, 0xC0, 0x6C,
- 0x06, 0xC0, 0xEC, 0x0C, 0xE3, 0x87, 0xF0, 0x3E, 0x00, 0x02, 0x0C, 0x77,
- 0xEF, 0xC1, 0x83, 0x0C, 0x18, 0x30, 0x61, 0xC3, 0x06, 0x0C, 0x18, 0x60,
- 0x03, 0xF0, 0x1F, 0xE0, 0xE1, 0xC7, 0x03, 0x18, 0x0C, 0x00, 0x30, 0x01,
- 0x80, 0x0E, 0x00, 0x70, 0x07, 0x80, 0x78, 0x07, 0x80, 0x38, 0x01, 0xC0,
- 0x06, 0x00, 0x1F, 0xFC, 0xFF, 0xE0, 0x07, 0xC0, 0xFE, 0x1C, 0x73, 0x03,
- 0x30, 0x30, 0x03, 0x00, 0xE0, 0x7C, 0x07, 0xC0, 0x0E, 0x00, 0x60, 0x06,
- 0xC0, 0x6C, 0x0C, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x00, 0x60, 0x06, 0x00,
- 0xE0, 0x1E, 0x03, 0xE0, 0x6C, 0x0C, 0xC1, 0x8C, 0x30, 0xC6, 0x1C, 0xC1,
- 0x8F, 0xFF, 0xFF, 0xE0, 0x18, 0x03, 0x00, 0x30, 0x03, 0x00, 0x0F, 0xF8,
- 0x7F, 0xC6, 0x00, 0x30, 0x01, 0x00, 0x1B, 0xC0, 0xFF, 0x06, 0x1C, 0x60,
- 0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x0C, 0x60, 0x63, 0x86, 0x0F, 0xE0,
- 0x3E, 0x00, 0x03, 0xC0, 0xFE, 0x1C, 0x73, 0x83, 0x30, 0x06, 0x00, 0x67,
- 0x87, 0xFC, 0xF0, 0xEE, 0x06, 0xC0, 0x6C, 0x06, 0xC0, 0x4C, 0x0C, 0xE1,
- 0x87, 0xF8, 0x3E, 0x00, 0x3F, 0xFB, 0xFF, 0xC0, 0x0C, 0x00, 0xC0, 0x0C,
- 0x00, 0xC0, 0x06, 0x00, 0x60, 0x06, 0x00, 0x70, 0x03, 0x00, 0x30, 0x03,
- 0x80, 0x18, 0x01, 0xC0, 0x0C, 0x00, 0xE0, 0x00, 0x07, 0xC0, 0xFE, 0x1C,
- 0x73, 0x03, 0x30, 0x33, 0x03, 0x38, 0x61, 0xFC, 0x3F, 0xC7, 0x0E, 0x60,
- 0x6C, 0x06, 0xC0, 0x6C, 0x0C, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x07, 0xC1,
- 0xFE, 0x38, 0x73, 0x03, 0x60, 0x36, 0x03, 0x60, 0x36, 0x07, 0x70, 0xF3,
- 0xFE, 0x1E, 0x60, 0x0E, 0x00, 0xCC, 0x1C, 0xE3, 0x87, 0xF0, 0x3C, 0x00,
- 0x39, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x39, 0xC0, 0x1C, 0x70, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x07, 0x1C, 0x20, 0x86, 0x30, 0x00, 0x00, 0x01, 0xC0,
- 0x3C, 0x0F, 0x81, 0xE0, 0x7C, 0x03, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x3E,
- 0x00, 0x38, 0x00, 0x40, 0x7F, 0xFB, 0xFF, 0x80, 0x00, 0x00, 0x0F, 0xFF,
- 0x7F, 0xF0, 0x20, 0x01, 0xC0, 0x07, 0xC0, 0x0F, 0x80, 0x0F, 0x00, 0x1C,
- 0x03, 0xE0, 0x78, 0x1F, 0x03, 0xC0, 0x38, 0x00, 0x00, 0x00, 0x0F, 0x87,
- 0xF9, 0xC3, 0xB0, 0x3C, 0x06, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x01, 0xC0,
- 0x30, 0x0C, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x30, 0x06, 0x00, 0x00,
- 0x3F, 0x80, 0x01, 0xFF, 0xE0, 0x0F, 0x01, 0xE0, 0x38, 0x00, 0xE0, 0xE0,
- 0x00, 0xC3, 0x87, 0x81, 0xCE, 0x1F, 0xB1, 0x98, 0x71, 0xC3, 0x61, 0x83,
- 0x86, 0xC6, 0x06, 0x0F, 0x0C, 0x0C, 0x3E, 0x30, 0x30, 0x6C, 0x60, 0x61,
- 0xD8, 0xC1, 0x87, 0x31, 0xC7, 0x1C, 0x61, 0xF7, 0xF0, 0x63, 0xCF, 0x80,
- 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xFF, 0xE0, 0x00, 0x7F, 0x00, 0x00,
- 0x00, 0x38, 0x00, 0x78, 0x00, 0x7C, 0x00, 0xFC, 0x00, 0xDC, 0x01, 0xCC,
- 0x01, 0x8C, 0x03, 0x8C, 0x03, 0x0C, 0x06, 0x0C, 0x0E, 0x0E, 0x0F, 0xFE,
- 0x1F, 0xFE, 0x18, 0x06, 0x38, 0x06, 0x30, 0x06, 0x70, 0x06, 0x60, 0x07,
- 0x0F, 0xF8, 0x1F, 0xF8, 0x60, 0x38, 0xC0, 0x31, 0x80, 0x63, 0x00, 0xCE,
- 0x03, 0x18, 0x0C, 0x3F, 0xF0, 0x7F, 0xF0, 0xC0, 0x73, 0x00, 0x66, 0x00,
- 0xCC, 0x01, 0x98, 0x06, 0x70, 0x1C, 0xFF, 0xF1, 0xFF, 0x80, 0x01, 0xF8,
- 0x07, 0xFE, 0x0E, 0x0E, 0x1C, 0x03, 0x38, 0x03, 0x30, 0x00, 0x60, 0x00,
- 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x06,
- 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x78, 0x3F, 0xF0, 0x1F, 0x80, 0x0F, 0xF8,
- 0x1F, 0xFC, 0x18, 0x0E, 0x18, 0x07, 0x18, 0x03, 0x18, 0x03, 0x38, 0x03,
- 0x30, 0x03, 0x30, 0x03, 0x30, 0x03, 0x70, 0x06, 0x70, 0x06, 0x60, 0x0C,
- 0x60, 0x0C, 0x60, 0x18, 0xE0, 0x78, 0xFF, 0xE0, 0xFF, 0x80, 0x0F, 0xFF,
- 0x1F, 0xFE, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x38, 0x00,
- 0x30, 0x00, 0x3F, 0xFC, 0x3F, 0xF8, 0x70, 0x00, 0x70, 0x00, 0x60, 0x00,
- 0x60, 0x00, 0x60, 0x00, 0xE0, 0x00, 0xFF, 0xF8, 0xFF, 0xF8, 0x0F, 0xFE,
- 0x3F, 0xFC, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x18,
- 0x00, 0x3F, 0xF0, 0x7F, 0xE1, 0xC0, 0x03, 0x80, 0x06, 0x00, 0x0C, 0x00,
- 0x18, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x80, 0x00, 0x01, 0xF8, 0x07, 0xFE,
- 0x0E, 0x0F, 0x18, 0x03, 0x30, 0x03, 0x70, 0x00, 0x60, 0x00, 0x60, 0x00,
- 0xC0, 0x7F, 0xC0, 0x7E, 0xC0, 0x02, 0xC0, 0x06, 0xC0, 0x06, 0xE0, 0x0E,
- 0x60, 0x1E, 0x78, 0x3C, 0x3F, 0xE4, 0x0F, 0x84, 0x0C, 0x01, 0x8E, 0x00,
- 0xC6, 0x00, 0xE3, 0x00, 0x61, 0x80, 0x30, 0xC0, 0x18, 0xE0, 0x0C, 0x60,
- 0x0E, 0x3F, 0xFE, 0x1F, 0xFF, 0x1C, 0x01, 0x8E, 0x01, 0xC6, 0x00, 0xE3,
- 0x00, 0x61, 0x80, 0x31, 0xC0, 0x18, 0xC0, 0x1C, 0x60, 0x0C, 0x00, 0x0C,
- 0x71, 0x86, 0x18, 0x63, 0x8C, 0x30, 0xC3, 0x1C, 0x61, 0x86, 0x18, 0xE3,
- 0x00, 0x00, 0x18, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x01,
- 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x01, 0x8C, 0x0C, 0x60, 0x63,
- 0x07, 0x1C, 0x70, 0x7F, 0x01, 0xF0, 0x00, 0x0C, 0x03, 0x87, 0x01, 0xC1,
- 0x80, 0xE0, 0x60, 0x60, 0x18, 0x70, 0x06, 0x38, 0x03, 0x9C, 0x00, 0xCE,
- 0x00, 0x37, 0x80, 0x0F, 0x70, 0x07, 0x8C, 0x01, 0xC3, 0x80, 0x60, 0x60,
- 0x18, 0x1C, 0x06, 0x03, 0x03, 0x80, 0xE0, 0xC0, 0x18, 0x30, 0x07, 0x00,
- 0x0C, 0x03, 0x80, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x0E, 0x01, 0x80, 0x30,
- 0x06, 0x01, 0xC0, 0x38, 0x06, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xFF, 0xFF,
- 0xFC, 0x0E, 0x00, 0x71, 0xE0, 0x0F, 0x1E, 0x00, 0xF1, 0xE0, 0x1E, 0x1E,
- 0x01, 0xE1, 0xE0, 0x36, 0x3B, 0x03, 0x63, 0x30, 0x6E, 0x33, 0x0E, 0xC3,
- 0x30, 0xCC, 0x33, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x31, 0xC6, 0x33, 0x18,
- 0x61, 0xE1, 0x8E, 0x1E, 0x18, 0xC1, 0xC1, 0x8C, 0x1C, 0x38, 0x0C, 0x01,
- 0x8F, 0x00, 0xC7, 0x80, 0x63, 0xE0, 0x71, 0xF0, 0x30, 0xD8, 0x18, 0xEE,
- 0x0C, 0x63, 0x06, 0x31, 0xC7, 0x18, 0xE3, 0x0C, 0x31, 0x8C, 0x1C, 0xC6,
- 0x06, 0x63, 0x03, 0xF1, 0x80, 0xF1, 0xC0, 0x78, 0xC0, 0x3C, 0x60, 0x0E,
- 0x00, 0x01, 0xF8, 0x03, 0xFF, 0x03, 0x83, 0xC3, 0x80, 0x63, 0x00, 0x3B,
- 0x80, 0x0D, 0x80, 0x06, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00,
- 0xF8, 0x00, 0x6C, 0x00, 0x36, 0x00, 0x31, 0x80, 0x30, 0xF0, 0x78, 0x3F,
- 0xF0, 0x07, 0xE0, 0x00, 0x0F, 0xF8, 0x3F, 0xF8, 0x60, 0x38, 0xC0, 0x31,
- 0x80, 0x63, 0x00, 0xCE, 0x03, 0x18, 0x0E, 0x3F, 0xF8, 0x7F, 0xE1, 0xC0,
- 0x03, 0x80, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x70, 0x00, 0xC0, 0x01,
- 0x80, 0x00, 0x00, 0xFC, 0x01, 0xFF, 0xC0, 0xF0, 0x78, 0x70, 0x06, 0x38,
- 0x01, 0xCC, 0x00, 0x36, 0x00, 0x0D, 0x80, 0x03, 0xC0, 0x00, 0xF0, 0x00,
- 0x3C, 0x00, 0x1B, 0x00, 0x06, 0xC0, 0x03, 0x38, 0x1D, 0xC6, 0x03, 0xE1,
- 0xE0, 0xF0, 0x3F, 0xFE, 0x03, 0xF1, 0xC0, 0x00, 0x20, 0x0F, 0xFC, 0x1F,
- 0xFE, 0x18, 0x07, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x38, 0x06, 0x30,
- 0x0C, 0x3F, 0xF8, 0x3F, 0xF8, 0x70, 0x1C, 0x70, 0x0C, 0x60, 0x0C, 0x60,
- 0x0C, 0x60, 0x18, 0xE0, 0x18, 0xC0, 0x18, 0xC0, 0x1C, 0x03, 0xF8, 0x1F,
- 0xF8, 0x70, 0x38, 0xC0, 0x33, 0x00, 0x66, 0x00, 0x0C, 0x00, 0x1E, 0x00,
- 0x1F, 0xC0, 0x0F, 0xF0, 0x01, 0xF0, 0x00, 0xEC, 0x00, 0xD8, 0x01, 0xB0,
- 0x06, 0x70, 0x38, 0x7F, 0xE0, 0x3F, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0x70,
- 0x01, 0xC0, 0x06, 0x00, 0x18, 0x00, 0x60, 0x03, 0x80, 0x0C, 0x00, 0x30,
- 0x00, 0xC0, 0x03, 0x00, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x18,
- 0x00, 0xE0, 0x00, 0x18, 0x03, 0x38, 0x03, 0x30, 0x07, 0x30, 0x06, 0x30,
- 0x06, 0x70, 0x06, 0x70, 0x0E, 0x60, 0x0C, 0x60, 0x0C, 0x60, 0x0C, 0xE0,
- 0x0C, 0xC0, 0x1C, 0xC0, 0x18, 0xC0, 0x18, 0xC0, 0x38, 0xE0, 0x70, 0x7F,
- 0xE0, 0x1F, 0x80, 0xC0, 0x0F, 0xC0, 0x1B, 0x80, 0x73, 0x00, 0xC6, 0x03,
- 0x0C, 0x06, 0x18, 0x18, 0x30, 0x70, 0x60, 0xC0, 0xE3, 0x81, 0xC6, 0x01,
- 0x9C, 0x03, 0x30, 0x06, 0xE0, 0x0D, 0x80, 0x1E, 0x00, 0x3C, 0x00, 0x70,
- 0x00, 0xC0, 0x70, 0x1F, 0x01, 0xC0, 0x6C, 0x0F, 0x03, 0xB0, 0x3C, 0x0C,
- 0xC1, 0xF0, 0x73, 0x06, 0xC1, 0x8C, 0x3B, 0x06, 0x30, 0xC6, 0x30, 0xC7,
- 0x18, 0xC3, 0x18, 0x67, 0x0C, 0xE1, 0x98, 0x33, 0x06, 0xE0, 0xDC, 0x1B,
- 0x03, 0x60, 0x6C, 0x07, 0x81, 0xE0, 0x1C, 0x07, 0x80, 0x70, 0x1C, 0x01,
- 0x80, 0x70, 0x00, 0x07, 0x00, 0xE0, 0xE0, 0x38, 0x0C, 0x0E, 0x01, 0xC3,
- 0x80, 0x18, 0xE0, 0x03, 0x98, 0x00, 0x36, 0x00, 0x07, 0x80, 0x00, 0xF0,
- 0x00, 0x1E, 0x00, 0x07, 0xC0, 0x01, 0xDC, 0x00, 0x73, 0x80, 0x1C, 0x30,
- 0x03, 0x07, 0x00, 0xC0, 0x60, 0x38, 0x0E, 0x0E, 0x00, 0xC0, 0xE0, 0x06,
- 0x60, 0x0C, 0x70, 0x1C, 0x70, 0x38, 0x30, 0x70, 0x38, 0x60, 0x18, 0xC0,
- 0x1D, 0xC0, 0x1F, 0x80, 0x0F, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00,
- 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x0F, 0xFF,
- 0x87, 0xFF, 0x80, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01,
- 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01,
- 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xF8, 0x7F, 0xFC,
- 0x00, 0x07, 0xC1, 0xE0, 0x60, 0x18, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x1C,
- 0x06, 0x01, 0x80, 0x60, 0x18, 0x0E, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x06,
- 0x01, 0x80, 0x60, 0x1E, 0x07, 0x80, 0x93, 0x6C, 0x92, 0x49, 0x24, 0xDB,
- 0x24, 0x07, 0x81, 0xE0, 0x18, 0x06, 0x01, 0x80, 0xC0, 0x30, 0x0C, 0x03,
- 0x01, 0xC0, 0x60, 0x18, 0x06, 0x01, 0x80, 0xE0, 0x30, 0x0C, 0x03, 0x00,
- 0xC0, 0x60, 0x18, 0x1E, 0x0F, 0x80, 0x03, 0x01, 0xC0, 0xD8, 0x36, 0x19,
- 0x84, 0x63, 0x19, 0x83, 0x60, 0xC0, 0xFF, 0xFC, 0xE6, 0x23, 0x07, 0xC3,
- 0xFC, 0xE3, 0x98, 0x30, 0x06, 0x01, 0x87, 0xF3, 0xC6, 0xC0, 0xD8, 0x3B,
- 0x0E, 0x7F, 0x77, 0xCC, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x30, 0x01, 0x80,
- 0x0C, 0xF0, 0x7F, 0xC3, 0x87, 0x38, 0x19, 0x80, 0xCC, 0x06, 0x60, 0x32,
- 0x03, 0xB0, 0x19, 0xC1, 0xCE, 0x1C, 0x7F, 0xC3, 0x7C, 0x00, 0x0F, 0x83,
- 0xF8, 0xE3, 0xB8, 0x36, 0x07, 0xC0, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x1B,
- 0x86, 0x3F, 0xC3, 0xE0, 0x00, 0x0C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00,
- 0x18, 0x3E, 0x61, 0xFF, 0x0E, 0x3C, 0x70, 0x71, 0x80, 0xCE, 0x07, 0x30,
- 0x18, 0xC0, 0x63, 0x01, 0x8C, 0x0E, 0x38, 0x78, 0x7F, 0xC0, 0xFB, 0x00,
- 0x07, 0xC1, 0xFE, 0x38, 0x77, 0x03, 0x60, 0x37, 0xFF, 0xFF, 0xFC, 0x00,
- 0xC0, 0x0C, 0x06, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x07, 0x0F, 0x1C, 0x18,
- 0x18, 0x7E, 0x7E, 0x30, 0x30, 0x30, 0x30, 0x60, 0x60, 0x60, 0x60, 0x60,
- 0xC0, 0xC0, 0x03, 0xCC, 0x3F, 0xA1, 0xC7, 0x8E, 0x0E, 0x30, 0x38, 0xC0,
- 0xC6, 0x03, 0x18, 0x0C, 0x60, 0x71, 0x81, 0xC7, 0x0E, 0x0F, 0xF8, 0x1E,
- 0x60, 0x03, 0x80, 0x0C, 0x30, 0x70, 0x7F, 0x80, 0xF8, 0x00, 0x0C, 0x00,
- 0xC0, 0x0C, 0x01, 0x80, 0x18, 0x01, 0x9E, 0x1F, 0xF1, 0xC7, 0x38, 0x33,
- 0x03, 0x30, 0x33, 0x07, 0x30, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60, 0xC6,
- 0x0C, 0x18, 0xC0, 0x00, 0x18, 0xC6, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xC6,
- 0x00, 0x01, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x18, 0x1C, 0x0C, 0x06, 0x03,
- 0x01, 0x81, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x18, 0x0C, 0x06, 0x03, 0x03,
- 0x87, 0x83, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x30, 0x01, 0x80, 0x0C,
- 0x18, 0x61, 0x83, 0x38, 0x33, 0x81, 0xB8, 0x0F, 0xC0, 0x77, 0x03, 0x18,
- 0x30, 0xC1, 0x87, 0x0C, 0x18, 0x60, 0xE3, 0x03, 0x00, 0x18, 0xC6, 0x63,
- 0x18, 0xC6, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xC6, 0x00, 0x1B, 0xE3, 0xC3,
- 0xFD, 0xFC, 0xF1, 0xE1, 0x9C, 0x18, 0x33, 0x03, 0x06, 0x60, 0xC0, 0xCC,
- 0x18, 0x3B, 0x83, 0x06, 0x60, 0x60, 0xCC, 0x0C, 0x19, 0x83, 0x03, 0x30,
- 0x60, 0xE6, 0x0C, 0x18, 0x1B, 0xE1, 0xFF, 0x3C, 0x73, 0x83, 0x30, 0x33,
- 0x03, 0x30, 0x77, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x0C, 0x60, 0xC0,
- 0x07, 0xC1, 0xFE, 0x38, 0x77, 0x03, 0x60, 0x3E, 0x03, 0xC0, 0x3C, 0x06,
- 0xC0, 0x6C, 0x0E, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x0C, 0xF0, 0x3F, 0xE0,
- 0xE1, 0xC7, 0x03, 0x1C, 0x0C, 0x60, 0x31, 0x80, 0xCE, 0x07, 0x38, 0x18,
- 0xE0, 0xE3, 0xC7, 0x0F, 0xF8, 0x77, 0xC1, 0x80, 0x06, 0x00, 0x18, 0x00,
- 0x60, 0x03, 0x80, 0x00, 0x0F, 0x98, 0xFF, 0xCE, 0x3C, 0xE0, 0xE6, 0x03,
- 0x70, 0x1B, 0x01, 0x98, 0x0C, 0xC0, 0x66, 0x07, 0x38, 0x78, 0xFF, 0x83,
- 0xCC, 0x00, 0x60, 0x07, 0x00, 0x38, 0x01, 0x80, 0x0C, 0x00, 0x1B, 0x8F,
- 0xCF, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xE0, 0x60, 0x30, 0x18, 0x0C, 0x06,
- 0x00, 0x0F, 0xC1, 0xFF, 0x30, 0x76, 0x03, 0x60, 0x07, 0x80, 0x3F, 0x80,
- 0x7E, 0x00, 0x6C, 0x06, 0xE0, 0xCF, 0xF8, 0x3E, 0x00, 0x18, 0x30, 0x67,
- 0xEF, 0xC6, 0x0C, 0x30, 0x60, 0xC1, 0x83, 0x0C, 0x18, 0x3C, 0x38, 0x30,
- 0x33, 0x03, 0x30, 0x37, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0xC0,
- 0xEC, 0x0C, 0xC3, 0xCF, 0xFC, 0x7C, 0xC0, 0xC0, 0x78, 0x1B, 0x03, 0x60,
- 0xC6, 0x18, 0xC6, 0x19, 0xC3, 0x30, 0x6C, 0x0D, 0x81, 0xE0, 0x3C, 0x03,
- 0x00, 0xC1, 0xC3, 0xE1, 0xE1, 0xB0, 0xF0, 0xD8, 0x78, 0xCC, 0x6C, 0x66,
- 0x36, 0x63, 0x33, 0x30, 0x99, 0xB0, 0x58, 0xD8, 0x2C, 0x78, 0x1C, 0x3C,
- 0x0E, 0x1C, 0x06, 0x0E, 0x00, 0x0C, 0x1C, 0x30, 0xE0, 0xE3, 0x01, 0x98,
- 0x07, 0xC0, 0x0E, 0x00, 0x30, 0x01, 0xE0, 0x0F, 0x80, 0x73, 0x01, 0x8C,
- 0x0C, 0x38, 0x60, 0x60, 0x18, 0x0C, 0x60, 0x61, 0x83, 0x86, 0x0C, 0x1C,
- 0x60, 0x31, 0x80, 0xCC, 0x03, 0x30, 0x0D, 0x80, 0x36, 0x00, 0xF0, 0x03,
- 0x80, 0x06, 0x00, 0x30, 0x00, 0xC0, 0x06, 0x00, 0xF0, 0x03, 0x80, 0x00,
- 0x1F, 0xF1, 0xFF, 0x00, 0x70, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0,
- 0x18, 0x03, 0x00, 0x60, 0x0F, 0xFC, 0xFF, 0xC0, 0x07, 0x0E, 0x18, 0x18,
- 0x18, 0x18, 0x30, 0x30, 0x30, 0x30, 0x60, 0xE0, 0xE0, 0x60, 0x60, 0x60,
- 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xF0, 0x60, 0x0C, 0x30, 0x82, 0x08, 0x61,
- 0x84, 0x10, 0x43, 0x0C, 0x20, 0x86, 0x18, 0x41, 0x04, 0x30, 0xC2, 0x00,
- 0x00, 0x06, 0x07, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03,
- 0x01, 0xC0, 0xE0, 0x60, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03, 0x01,
- 0x83, 0x83, 0x80, 0x38, 0x0F, 0x82, 0x38, 0x83, 0xE0, 0x38 };
-
-const GFXglyph FreeSansOblique12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 7, 0, 1 }, // 0x20 ' '
- { 0, 6, 18, 7, 3, -17 }, // 0x21 '!'
- { 14, 6, 6, 9, 4, -16 }, // 0x22 '"'
- { 19, 15, 18, 13, 1, -17 }, // 0x23 '#'
- { 53, 13, 21, 13, 2, -17 }, // 0x24 '$'
- { 88, 19, 17, 21, 3, -16 }, // 0x25 '%'
- { 129, 13, 17, 16, 2, -16 }, // 0x26 '&'
- { 157, 2, 6, 5, 4, -16 }, // 0x27 '''
- { 159, 8, 23, 8, 3, -17 }, // 0x28 '('
- { 182, 8, 23, 8, 0, -16 }, // 0x29 ')'
- { 205, 8, 8, 9, 4, -17 }, // 0x2A '*'
- { 213, 12, 11, 14, 2, -10 }, // 0x2B '+'
- { 230, 4, 6, 7, 1, -1 }, // 0x2C ','
- { 233, 6, 2, 8, 2, -7 }, // 0x2D '-'
- { 235, 3, 2, 7, 2, -1 }, // 0x2E '.'
- { 236, 10, 18, 7, 0, -17 }, // 0x2F '/'
- { 259, 12, 17, 13, 2, -16 }, // 0x30 '0'
- { 285, 7, 17, 13, 5, -16 }, // 0x31 '1'
- { 300, 14, 17, 13, 1, -16 }, // 0x32 '2'
- { 330, 12, 17, 13, 2, -16 }, // 0x33 '3'
- { 356, 12, 17, 13, 2, -16 }, // 0x34 '4'
- { 382, 13, 17, 13, 2, -16 }, // 0x35 '5'
- { 410, 12, 17, 13, 2, -16 }, // 0x36 '6'
- { 436, 13, 17, 13, 3, -16 }, // 0x37 '7'
- { 464, 12, 17, 13, 2, -16 }, // 0x38 '8'
- { 490, 12, 17, 13, 2, -16 }, // 0x39 '9'
- { 516, 5, 12, 7, 3, -11 }, // 0x3A ':'
- { 524, 6, 16, 7, 2, -11 }, // 0x3B ';'
- { 536, 13, 12, 14, 2, -11 }, // 0x3C '<'
- { 556, 13, 6, 14, 2, -8 }, // 0x3D '='
- { 566, 13, 12, 14, 1, -10 }, // 0x3E '>'
- { 586, 11, 18, 13, 4, -17 }, // 0x3F '?'
- { 611, 23, 21, 24, 2, -17 }, // 0x40 '@'
- { 672, 16, 18, 16, 0, -17 }, // 0x41 'A'
- { 708, 15, 18, 16, 2, -17 }, // 0x42 'B'
- { 742, 16, 18, 17, 2, -17 }, // 0x43 'C'
- { 778, 16, 18, 17, 2, -17 }, // 0x44 'D'
- { 814, 16, 18, 16, 2, -17 }, // 0x45 'E'
- { 850, 15, 18, 14, 2, -17 }, // 0x46 'F'
- { 884, 16, 18, 19, 3, -17 }, // 0x47 'G'
- { 920, 17, 18, 17, 2, -17 }, // 0x48 'H'
- { 959, 6, 18, 7, 2, -17 }, // 0x49 'I'
- { 973, 13, 18, 12, 1, -17 }, // 0x4A 'J'
- { 1003, 18, 18, 16, 2, -17 }, // 0x4B 'K'
- { 1044, 11, 18, 13, 2, -17 }, // 0x4C 'L'
- { 1069, 20, 18, 20, 2, -17 }, // 0x4D 'M'
- { 1114, 17, 18, 18, 2, -17 }, // 0x4E 'N'
- { 1153, 17, 18, 18, 2, -17 }, // 0x4F 'O'
- { 1192, 15, 18, 15, 2, -17 }, // 0x50 'P'
- { 1226, 18, 19, 19, 2, -17 }, // 0x51 'Q'
- { 1269, 16, 18, 17, 2, -17 }, // 0x52 'R'
- { 1305, 15, 18, 16, 2, -17 }, // 0x53 'S'
- { 1339, 14, 18, 15, 4, -17 }, // 0x54 'T'
- { 1371, 16, 18, 17, 3, -17 }, // 0x55 'U'
- { 1407, 15, 18, 15, 4, -17 }, // 0x56 'V'
- { 1441, 22, 18, 22, 4, -17 }, // 0x57 'W'
- { 1491, 19, 18, 16, 0, -17 }, // 0x58 'X'
- { 1534, 16, 18, 16, 4, -17 }, // 0x59 'Y'
- { 1570, 17, 18, 15, 1, -17 }, // 0x5A 'Z'
- { 1609, 10, 23, 7, 0, -17 }, // 0x5B '['
- { 1638, 3, 18, 7, 4, -17 }, // 0x5C '\'
- { 1645, 10, 23, 7, -1, -16 }, // 0x5D ']'
- { 1674, 10, 9, 11, 2, -16 }, // 0x5E '^'
- { 1686, 14, 1, 13, -1, 4 }, // 0x5F '_'
- { 1688, 4, 4, 8, 4, -17 }, // 0x60 '`'
- { 1690, 11, 13, 13, 2, -12 }, // 0x61 'a'
- { 1708, 13, 18, 13, 1, -17 }, // 0x62 'b'
- { 1738, 11, 13, 12, 2, -12 }, // 0x63 'c'
- { 1756, 14, 18, 13, 2, -17 }, // 0x64 'd'
- { 1788, 12, 13, 13, 2, -12 }, // 0x65 'e'
- { 1808, 8, 18, 6, 2, -17 }, // 0x66 'f'
- { 1826, 14, 18, 13, 1, -12 }, // 0x67 'g'
- { 1858, 12, 18, 13, 1, -17 }, // 0x68 'h'
- { 1885, 5, 18, 5, 2, -17 }, // 0x69 'i'
- { 1897, 9, 23, 6, -1, -17 }, // 0x6A 'j'
- { 1923, 13, 18, 12, 1, -17 }, // 0x6B 'k'
- { 1953, 5, 18, 5, 2, -17 }, // 0x6C 'l'
- { 1965, 19, 13, 20, 1, -12 }, // 0x6D 'm'
- { 1996, 12, 13, 13, 1, -12 }, // 0x6E 'n'
- { 2016, 12, 13, 13, 2, -12 }, // 0x6F 'o'
- { 2036, 14, 18, 14, 0, -12 }, // 0x70 'p'
- { 2068, 13, 18, 13, 2, -12 }, // 0x71 'q'
- { 2098, 9, 13, 8, 1, -12 }, // 0x72 'r'
- { 2113, 12, 13, 12, 1, -12 }, // 0x73 's'
- { 2133, 7, 16, 6, 2, -15 }, // 0x74 't'
- { 2147, 12, 13, 13, 2, -12 }, // 0x75 'u'
- { 2167, 11, 13, 12, 3, -12 }, // 0x76 'v'
- { 2185, 17, 13, 17, 3, -12 }, // 0x77 'w'
- { 2213, 14, 13, 12, 0, -12 }, // 0x78 'x'
- { 2236, 14, 18, 11, 0, -12 }, // 0x79 'y'
- { 2268, 12, 13, 12, 1, -12 }, // 0x7A 'z'
- { 2288, 8, 23, 8, 3, -17 }, // 0x7B '{'
- { 2311, 6, 23, 6, 1, -17 }, // 0x7C '|'
- { 2329, 9, 23, 8, -1, -16 }, // 0x7D '}'
- { 2355, 11, 5, 14, 3, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSansOblique12pt7b PROGMEM = {
- (uint8_t *)FreeSansOblique12pt7bBitmaps,
- (GFXglyph *)FreeSansOblique12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 3034 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique18pt7b.h
deleted file mode 100644
index 2a18a3f..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique18pt7b.h
+++ /dev/null
@@ -1,518 +0,0 @@
-const uint8_t FreeSansOblique18pt7bBitmaps[] PROGMEM = {
- 0x03, 0x83, 0x81, 0xC0, 0xE0, 0x70, 0x78, 0x38, 0x1C, 0x0E, 0x07, 0x07,
- 0x83, 0x81, 0xC0, 0xE0, 0x60, 0x30, 0x30, 0x18, 0x0C, 0x04, 0x00, 0x00,
- 0x01, 0xC0, 0xE0, 0x70, 0x78, 0x00, 0x71, 0xDC, 0x7F, 0x3F, 0x8E, 0xE3,
- 0xB8, 0xEC, 0x33, 0x0C, 0xC3, 0x00, 0x00, 0x38, 0x70, 0x01, 0xC3, 0x80,
- 0x0C, 0x18, 0x00, 0xE1, 0xC0, 0x06, 0x0C, 0x00, 0x70, 0xE0, 0x03, 0x87,
- 0x03, 0xFF, 0xFF, 0x1F, 0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0x60, 0xC0, 0x07,
- 0x0E, 0x00, 0x30, 0x60, 0x03, 0x87, 0x00, 0x18, 0x30, 0x1F, 0xFF, 0xF8,
- 0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x07, 0x0E, 0x00, 0x30, 0x70, 0x03, 0x87,
- 0x00, 0x1C, 0x38, 0x00, 0xC1, 0x80, 0x0E, 0x1C, 0x00, 0x60, 0xC0, 0x00,
- 0x00, 0x0C, 0x00, 0x07, 0xF8, 0x01, 0xFF, 0xC0, 0x3F, 0xFE, 0x07, 0x99,
- 0xF0, 0xF1, 0x87, 0x0E, 0x18, 0x71, 0xC1, 0x87, 0x1C, 0x38, 0x01, 0xC3,
- 0x00, 0x1C, 0x30, 0x01, 0xE3, 0x00, 0x0F, 0xB0, 0x00, 0xFF, 0x80, 0x03,
- 0xFF, 0x00, 0x0F, 0xF8, 0x00, 0x6F, 0xC0, 0x06, 0x3C, 0x00, 0xC1, 0xCE,
- 0x0C, 0x1C, 0xE0, 0xC1, 0xCE, 0x0C, 0x38, 0xF1, 0xC3, 0x8F, 0x98, 0xF0,
- 0x7F, 0xFE, 0x03, 0xFF, 0xC0, 0x0F, 0xF0, 0x00, 0x30, 0x00, 0x03, 0x00,
- 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0xE0, 0x03,
- 0x81, 0xFC, 0x00, 0xC0, 0xFF, 0x00, 0x60, 0x70, 0xE0, 0x38, 0x38, 0x18,
- 0x1C, 0x0C, 0x06, 0x0E, 0x03, 0x01, 0x83, 0x00, 0xC0, 0xE1, 0x80, 0x38,
- 0x70, 0xE0, 0x0F, 0xF8, 0x70, 0x01, 0xFC, 0x18, 0x00, 0x3E, 0x0C, 0x00,
- 0x00, 0x06, 0x07, 0x80, 0x03, 0x87, 0xF8, 0x00, 0xC3, 0xFE, 0x00, 0x61,
- 0xE1, 0xC0, 0x30, 0x60, 0x30, 0x1C, 0x30, 0x0C, 0x0E, 0x0C, 0x03, 0x03,
- 0x03, 0x01, 0x81, 0x80, 0xE1, 0xE0, 0xC0, 0x1F, 0xF0, 0x70, 0x07, 0xF8,
- 0x18, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x07, 0xF8, 0x00, 0xFF, 0xC0,
- 0x1E, 0x3C, 0x03, 0xC1, 0xC0, 0x38, 0x1C, 0x03, 0x81, 0xC0, 0x38, 0x38,
- 0x03, 0xC7, 0x00, 0x1D, 0xE0, 0x01, 0xFC, 0x00, 0x1F, 0x00, 0x07, 0xF0,
- 0x01, 0xF7, 0x87, 0x3C, 0x3C, 0xE7, 0x81, 0xCE, 0x70, 0x1F, 0xCE, 0x00,
- 0xFC, 0xE0, 0x07, 0x8E, 0x00, 0x78, 0xF0, 0x1F, 0x8F, 0x87, 0xFC, 0x7F,
- 0xF9, 0xC3, 0xFE, 0x1E, 0x1F, 0x80, 0xE0, 0x77, 0xFE, 0xEE, 0xCC, 0xC0,
- 0x00, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x80, 0x30, 0x06, 0x00, 0xE0,
- 0x0C, 0x01, 0xC0, 0x18, 0x03, 0x80, 0x38, 0x07, 0x00, 0x70, 0x07, 0x00,
- 0x70, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00,
- 0xE0, 0x0E, 0x00, 0xE0, 0x06, 0x00, 0x70, 0x07, 0x00, 0x30, 0x03, 0x00,
- 0x18, 0x00, 0x01, 0x80, 0x0C, 0x00, 0xC0, 0x0E, 0x00, 0xE0, 0x06, 0x00,
- 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00,
- 0x70, 0x07, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x03,
- 0x80, 0x38, 0x03, 0x00, 0x70, 0x06, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x30,
- 0x06, 0x00, 0xC0, 0x00, 0x06, 0x01, 0x84, 0x47, 0xF7, 0xFF, 0xCF, 0xC1,
- 0xE0, 0xD8, 0x67, 0x18, 0xC0, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x0F, 0x00,
- 0x03, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xC0, 0x70, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0xE0,
- 0x00, 0x38, 0x00, 0x0E, 0x00, 0x3B, 0xDC, 0x21, 0x18, 0x98, 0xFF, 0xFF,
- 0xFF, 0xE0, 0x7F, 0xFE, 0x00, 0x06, 0x00, 0x18, 0x00, 0x30, 0x00, 0xC0,
- 0x01, 0x80, 0x06, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x60, 0x01, 0x80, 0x03,
- 0x00, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x00, 0x06, 0x00,
- 0x18, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x00, 0x06, 0x00, 0x18, 0x00, 0x30,
- 0x00, 0xC0, 0x01, 0x80, 0x00, 0x00, 0x7C, 0x00, 0x7F, 0xC0, 0x7F, 0xF8,
- 0x3E, 0x1E, 0x0F, 0x03, 0xC7, 0x80, 0x71, 0xC0, 0x1C, 0xE0, 0x07, 0x38,
- 0x01, 0xDE, 0x00, 0x77, 0x00, 0x1D, 0xC0, 0x0F, 0x70, 0x03, 0xFC, 0x00,
- 0xEE, 0x00, 0x3B, 0x80, 0x0E, 0xE0, 0x07, 0xB8, 0x01, 0xCE, 0x00, 0xF3,
- 0x80, 0x38, 0xF0, 0x1E, 0x1E, 0x1F, 0x07, 0xFF, 0x80, 0xFF, 0xC0, 0x0F,
- 0x80, 0x00, 0x00, 0xC0, 0x70, 0x3C, 0x3E, 0xFF, 0xBF, 0xEF, 0xF8, 0x1E,
- 0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x07,
- 0x81, 0xC0, 0x70, 0x1C, 0x07, 0x01, 0xC0, 0xE0, 0x38, 0x00, 0x00, 0x3F,
- 0x00, 0x0F, 0xFC, 0x03, 0xFF, 0xE0, 0x7C, 0x1E, 0x07, 0x80, 0xF0, 0xF0,
- 0x07, 0x0E, 0x00, 0x70, 0xE0, 0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00,
- 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x0F, 0x80, 0x03, 0xF0, 0x00, 0xFC, 0x00,
- 0x1F, 0x00, 0x07, 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0x80, 0x00,
- 0x70, 0x00, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x8F, 0xFF, 0xF0, 0xFF, 0xFF,
- 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x03, 0xC1, 0xF0, 0x70,
- 0x0E, 0x1C, 0x01, 0xC3, 0x80, 0x38, 0xE0, 0x07, 0x00, 0x01, 0xC0, 0x00,
- 0xF0, 0x03, 0xFC, 0x00, 0x7F, 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0x00, 0x00,
- 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x1E, 0x70, 0x03,
- 0x8F, 0x00, 0xF1, 0xF0, 0x7C, 0x1F, 0xFF, 0x01, 0xFF, 0xC0, 0x0F, 0xC0,
- 0x00, 0x00, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x3E, 0x00, 0x1F,
- 0x80, 0x0F, 0xE0, 0x07, 0xF0, 0x03, 0xDC, 0x01, 0xE7, 0x00, 0x71, 0xC0,
- 0x38, 0xF0, 0x1C, 0x38, 0x0E, 0x0E, 0x07, 0x03, 0x83, 0x80, 0xE1, 0xC0,
- 0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x70, 0x00, 0x38,
- 0x00, 0x0E, 0x00, 0x03, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x01, 0xFF,
- 0xF0, 0x3F, 0xFF, 0x03, 0xFF, 0xE0, 0x78, 0x00, 0x07, 0x00, 0x00, 0x70,
- 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0xFC, 0x01, 0xFF, 0xF0, 0x1F,
- 0xFF, 0x83, 0xE0, 0x78, 0x3C, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0,
- 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x03, 0x8E, 0x00, 0x78,
- 0xE0, 0x0F, 0x0F, 0x81, 0xE0, 0x7F, 0xFC, 0x03, 0xFF, 0x80, 0x0F, 0xE0,
- 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x03, 0xE1, 0xF0, 0xF0,
- 0x0E, 0x1C, 0x01, 0xC7, 0x00, 0x01, 0xE0, 0x00, 0x38, 0x00, 0x07, 0x1F,
- 0x01, 0xCF, 0xF8, 0x3B, 0xFF, 0x87, 0xE0, 0xF8, 0xF0, 0x0F, 0x3C, 0x00,
- 0xE7, 0x80, 0x1C, 0xE0, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x1C, 0x70, 0x03,
- 0x8F, 0x00, 0xE0, 0xF0, 0x78, 0x1F, 0xFF, 0x01, 0xFF, 0x80, 0x0F, 0xC0,
- 0x00, 0x3F, 0xFF, 0xCF, 0xFF, 0xF7, 0xFF, 0xFC, 0x00, 0x0E, 0x00, 0x07,
- 0x00, 0x03, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00,
- 0x0E, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x1C,
- 0x00, 0x0E, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xF0, 0x00, 0x38, 0x00,
- 0x1E, 0x00, 0x07, 0x00, 0x03, 0xC0, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x7E,
- 0x00, 0x3F, 0xF0, 0x1F, 0xFF, 0x07, 0xC1, 0xF0, 0xE0, 0x0E, 0x38, 0x01,
- 0xC7, 0x00, 0x38, 0xE0, 0x0E, 0x1C, 0x01, 0xC3, 0xC0, 0xF0, 0x3F, 0xFC,
- 0x03, 0xFE, 0x01, 0xFF, 0xF0, 0x7C, 0x1E, 0x1E, 0x01, 0xE3, 0x80, 0x1C,
- 0xE0, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x0E, 0x70, 0x03, 0x8F, 0x00, 0xF1,
- 0xF0, 0x7C, 0x1F, 0xFF, 0x01, 0xFF, 0xC0, 0x0F, 0xC0, 0x00, 0x00, 0x7E,
- 0x00, 0x3F, 0xF0, 0x1F, 0xFF, 0x07, 0xC1, 0xE0, 0xE0, 0x1E, 0x38, 0x01,
- 0xC7, 0x00, 0x39, 0xC0, 0x07, 0x38, 0x00, 0xE7, 0x00, 0x3C, 0xE0, 0x07,
- 0x9E, 0x01, 0xE3, 0xE0, 0xFC, 0x3F, 0xFB, 0x83, 0xFE, 0xF0, 0x3F, 0x1C,
- 0x00, 0x03, 0x80, 0x00, 0xF0, 0x00, 0x1C, 0x70, 0x07, 0x8E, 0x01, 0xE1,
- 0xE0, 0xF8, 0x1F, 0xFE, 0x01, 0xFF, 0x80, 0x0F, 0xC0, 0x00, 0x0E, 0x3C,
- 0x78, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
- 0xF1, 0xE3, 0x80, 0x07, 0x0F, 0x0F, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x78, 0x70, 0x10, 0x10,
- 0x30, 0x20, 0xC0, 0x00, 0x00, 0x20, 0x00, 0x1C, 0x00, 0x1F, 0x80, 0x1F,
- 0xC0, 0x0F, 0xC0, 0x0F, 0xE0, 0x07, 0xE0, 0x03, 0xF0, 0x00, 0xF0, 0x00,
- 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8,
- 0x00, 0x0F, 0xC0, 0x00, 0x78, 0x00, 0x01, 0x00, 0x7F, 0xFF, 0xDF, 0xFF,
- 0xF7, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0xFB,
- 0xFF, 0xFE, 0xFF, 0xFF, 0x80, 0x10, 0x00, 0x03, 0xC0, 0x00, 0x7E, 0x00,
- 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F,
- 0x00, 0x01, 0xE0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0x7E, 0x00,
- 0x7F, 0x00, 0x3F, 0x00, 0x07, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 0xF8,
- 0x0F, 0xFC, 0x1F, 0xFE, 0x3C, 0x1F, 0x78, 0x07, 0x70, 0x07, 0xE0, 0x07,
- 0xE0, 0x07, 0x00, 0x0E, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0,
- 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x0E, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00,
- 0x3C, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x07,
- 0xFF, 0xFE, 0x00, 0x0F, 0xE0, 0x3F, 0x80, 0x0F, 0x80, 0x03, 0xE0, 0x0F,
- 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x3C, 0x0F, 0x01, 0xF0, 0x0F, 0x0F,
- 0x03, 0xFD, 0xC7, 0x8F, 0x03, 0xFE, 0xE1, 0xC7, 0x03, 0xC3, 0x60, 0xE7,
- 0x03, 0xC0, 0xF0, 0x77, 0x83, 0xC0, 0x70, 0x3B, 0x83, 0xC0, 0x78, 0x1D,
- 0xC1, 0xC0, 0x38, 0x1F, 0xC1, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x1C, 0x0F,
- 0x70, 0x70, 0x0E, 0x07, 0x38, 0x38, 0x0E, 0x07, 0x9C, 0x1C, 0x0F, 0x07,
- 0x8E, 0x0F, 0x0F, 0x8F, 0x87, 0x03, 0xFD, 0xFF, 0x83, 0xC1, 0xFC, 0xFF,
- 0x80, 0xE0, 0x7C, 0x3F, 0x00, 0x78, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00,
- 0x00, 0x07, 0x80, 0x00, 0x00, 0x01, 0xF8, 0x07, 0x00, 0x00, 0x7F, 0xFF,
- 0x80, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x01,
- 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x80, 0x00, 0xFF,
- 0x00, 0x01, 0xDE, 0x00, 0x07, 0x9C, 0x00, 0x0E, 0x38, 0x00, 0x3C, 0x70,
- 0x00, 0x70, 0xF0, 0x01, 0xC1, 0xE0, 0x07, 0x83, 0xC0, 0x0E, 0x07, 0x80,
- 0x38, 0x07, 0x00, 0x70, 0x0E, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x0F,
- 0xFF, 0xF8, 0x1C, 0x00, 0xF0, 0x70, 0x01, 0xE1, 0xE0, 0x01, 0xC3, 0x80,
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- 0x00, 0x01, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x00, 0xFF, 0xFF, 0xE0, 0xFF,
- 0xFF, 0xF0, 0x7F, 0xFF, 0xF8, 0x00, 0x01, 0xF8, 0x1F, 0xC0, 0xFE, 0x07,
- 0x00, 0x38, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x03, 0xC0,
- 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07,
- 0x00, 0x38, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x78, 0x03, 0x80,
- 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x70, 0x03, 0xF8, 0x1F, 0xC0, 0xFE, 0x00,
- 0xCC, 0xCC, 0xCC, 0x46, 0x66, 0x66, 0x66, 0x66, 0x66, 0x62, 0x33, 0x33,
- 0x33, 0x03, 0xF8, 0x1F, 0xC0, 0xFE, 0x00, 0x70, 0x07, 0x00, 0x38, 0x01,
- 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0xE0,
- 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01,
- 0xC0, 0x1E, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x1E, 0x00, 0xE0,
- 0x07, 0x03, 0xF8, 0x1F, 0xC0, 0xFC, 0x00, 0x00, 0xF0, 0x03, 0xC0, 0x1F,
- 0x00, 0x7C, 0x03, 0xB8, 0x1C, 0xE0, 0x63, 0x83, 0x8E, 0x1C, 0x38, 0x60,
- 0x73, 0x81, 0xCC, 0x07, 0x70, 0x1F, 0x80, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xC0, 0xF1, 0xC3, 0x86, 0x0C, 0x00, 0xFE, 0x01, 0xFF, 0xE0, 0xFF,
- 0xFC, 0x3C, 0x0F, 0x1C, 0x01, 0xC0, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x0E,
- 0x00, 0x1F, 0x83, 0xFF, 0xE3, 0xFE, 0x39, 0xF0, 0x1E, 0xF0, 0x07, 0x38,
- 0x01, 0xCE, 0x00, 0xF3, 0xC0, 0xFC, 0xFF, 0xF7, 0x9F, 0xF1, 0xE1, 0xF0,
- 0x38, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0xF0,
- 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x71, 0xF0, 0x0E, 0xFF, 0x83, 0xFF,
- 0xF8, 0x7F, 0x0F, 0x0F, 0x80, 0xF1, 0xE0, 0x0E, 0x38, 0x01, 0xCF, 0x00,
- 0x39, 0xE0, 0x07, 0x38, 0x00, 0xE7, 0x00, 0x38, 0xE0, 0x07, 0x3C, 0x00,
- 0xE7, 0x80, 0x38, 0xF8, 0x0F, 0x1F, 0x87, 0xC3, 0xFF, 0xF0, 0xE7, 0xFC,
- 0x1C, 0x7E, 0x00, 0x01, 0xF8, 0x07, 0xFC, 0x0F, 0xFE, 0x1E, 0x0F, 0x3C,
- 0x07, 0x78, 0x07, 0x70, 0x07, 0x70, 0x00, 0xF0, 0x00, 0xE0, 0x00, 0xE0,
- 0x00, 0xE0, 0x00, 0xE0, 0x0E, 0xE0, 0x1C, 0xF0, 0x3C, 0x78, 0x78, 0x7F,
- 0xF0, 0x3F, 0xE0, 0x0F, 0x80, 0x00, 0x00, 0x70, 0x00, 0x0F, 0x00, 0x00,
- 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x01, 0xE0, 0x1F,
- 0x1C, 0x07, 0xFD, 0xC0, 0xFF, 0xDC, 0x1E, 0x0F, 0xC3, 0xC0, 0x7C, 0x38,
- 0x07, 0x87, 0x00, 0x38, 0x70, 0x03, 0x8F, 0x00, 0x38, 0xE0, 0x07, 0x8E,
- 0x00, 0x70, 0xE0, 0x07, 0x0E, 0x00, 0xF0, 0xE0, 0x0F, 0x0F, 0x01, 0xF0,
- 0x78, 0x7E, 0x07, 0xFF, 0xE0, 0x3F, 0xEE, 0x01, 0xF8, 0xE0, 0x01, 0xF8,
- 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xC1, 0xF3, 0xC0, 0x79, 0xC0, 0x1D, 0xC0,
- 0x0E, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0E,
- 0x00, 0x07, 0x00, 0x73, 0xC0, 0x78, 0xF0, 0x78, 0x7F, 0xF8, 0x1F, 0xF8,
- 0x03, 0xF0, 0x00, 0x01, 0xE0, 0x7C, 0x1F, 0x83, 0x80, 0x70, 0x1C, 0x03,
- 0x83, 0xFC, 0x7F, 0x8F, 0xF0, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x0F, 0x01,
- 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80,
- 0xE0, 0x1C, 0x00, 0x00, 0xFC, 0x60, 0x7F, 0xCC, 0x1F, 0xFF, 0x87, 0xC3,
- 0xF1, 0xE0, 0x3E, 0x38, 0x03, 0x8E, 0x00, 0x71, 0xC0, 0x0E, 0x38, 0x01,
- 0xCE, 0x00, 0x79, 0xC0, 0x0E, 0x38, 0x01, 0xC7, 0x00, 0x78, 0xE0, 0x0F,
- 0x1E, 0x03, 0xC1, 0xE1, 0xF8, 0x3F, 0xFF, 0x03, 0xFE, 0xE0, 0x1F, 0x1C,
- 0x00, 0x03, 0x00, 0x00, 0xE0, 0x00, 0x18, 0x38, 0x07, 0x07, 0x83, 0xC0,
- 0x7F, 0xF8, 0x0F, 0xFC, 0x00, 0x7E, 0x00, 0x00, 0x07, 0x00, 0x01, 0xC0,
- 0x00, 0x70, 0x00, 0x1C, 0x00, 0x0F, 0x00, 0x03, 0x80, 0x00, 0xE0, 0x00,
- 0x38, 0xFC, 0x0E, 0xFF, 0x87, 0xFF, 0xF1, 0xF8, 0x3C, 0x7C, 0x07, 0x1E,
- 0x01, 0xC7, 0x00, 0x73, 0xC0, 0x1C, 0xE0, 0x0F, 0x38, 0x03, 0x8E, 0x00,
- 0xE3, 0x80, 0x39, 0xE0, 0x0E, 0x70, 0x07, 0x9C, 0x01, 0xC7, 0x00, 0x71,
- 0xC0, 0x1C, 0xE0, 0x07, 0x38, 0x03, 0x80, 0x07, 0x07, 0x0F, 0x0E, 0x00,
- 0x00, 0x00, 0x1E, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x38, 0x38, 0x38, 0x38,
- 0x38, 0x78, 0x70, 0x70, 0x70, 0x70, 0xF0, 0xE0, 0xE0, 0x00, 0x3C, 0x00,
- 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00,
- 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x00, 0xE0, 0x03, 0x80, 0x1E, 0x00,
- 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0xE0, 0x03, 0x80, 0x0E, 0x00,
- 0x38, 0x00, 0xE0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xC0, 0x0F, 0x00,
- 0x38, 0x00, 0xE0, 0x1F, 0x80, 0x7C, 0x03, 0xE0, 0x00, 0x07, 0x00, 0x00,
- 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0xF0, 0x00, 0x1C, 0x00, 0x03,
- 0x80, 0x00, 0x70, 0x1E, 0x0E, 0x07, 0x83, 0xC1, 0xE0, 0x70, 0x70, 0x0E,
- 0x1C, 0x01, 0xCF, 0x00, 0x3B, 0xC0, 0x0F, 0xF8, 0x01, 0xFF, 0x80, 0x3E,
- 0x70, 0x07, 0x8E, 0x00, 0xE0, 0xE0, 0x38, 0x1C, 0x07, 0x03, 0xC0, 0xE0,
- 0x38, 0x1C, 0x07, 0x03, 0x80, 0xF0, 0xE0, 0x0E, 0x1C, 0x01, 0xE0, 0x07,
- 0x07, 0x0F, 0x0E, 0x0E, 0x0E, 0x0E, 0x1E, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x38, 0x38, 0x38, 0x38, 0x38, 0x78, 0x70, 0x70, 0x70, 0x70, 0xF0, 0xE0,
- 0xE0, 0x1E, 0x7C, 0x0F, 0x83, 0xBF, 0xE7, 0xF8, 0x7F, 0xFD, 0xFF, 0x8F,
- 0xC3, 0xF0, 0xF1, 0xE0, 0x3C, 0x0E, 0x38, 0x07, 0x01, 0xCF, 0x01, 0xE0,
- 0x39, 0xC0, 0x38, 0x07, 0x38, 0x07, 0x00, 0xE7, 0x00, 0xE0, 0x1C, 0xE0,
- 0x1C, 0x07, 0x3C, 0x07, 0x00, 0xE7, 0x00, 0xE0, 0x1C, 0xE0, 0x1C, 0x03,
- 0x9C, 0x03, 0x80, 0xF3, 0x80, 0x70, 0x1C, 0x70, 0x1C, 0x03, 0x9C, 0x03,
- 0x80, 0x73, 0x80, 0x70, 0x0E, 0x00, 0x1E, 0x3E, 0x07, 0x7F, 0xE1, 0xFF,
- 0xF8, 0x7E, 0x0F, 0x1F, 0x01, 0xC7, 0x80, 0x73, 0xC0, 0x1C, 0xE0, 0x07,
- 0x38, 0x03, 0xCE, 0x00, 0xE3, 0x80, 0x39, 0xE0, 0x0E, 0x70, 0x03, 0x9C,
- 0x01, 0xC7, 0x00, 0x71, 0xC0, 0x1C, 0x70, 0x07, 0x38, 0x01, 0xCE, 0x00,
- 0xE0, 0x01, 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE1, 0xE3, 0xC0, 0x79,
- 0xC0, 0x1D, 0xC0, 0x0E, 0xE0, 0x07, 0x70, 0x03, 0xF0, 0x01, 0xF8, 0x01,
- 0xDC, 0x00, 0xEE, 0x00, 0x77, 0x00, 0x73, 0xC0, 0x78, 0xF0, 0xF8, 0x7F,
- 0xF8, 0x1F, 0xF8, 0x03, 0xF0, 0x00, 0x03, 0x8F, 0x80, 0x1D, 0xFF, 0x01,
- 0xFF, 0xFC, 0x0F, 0xC1, 0xE0, 0x7C, 0x07, 0x83, 0xC0, 0x1C, 0x1C, 0x00,
- 0xE1, 0xE0, 0x07, 0x0E, 0x00, 0x38, 0x70, 0x01, 0xC3, 0x80, 0x1E, 0x1C,
- 0x00, 0xE1, 0xE0, 0x07, 0x0F, 0x00, 0x70, 0x78, 0x07, 0x83, 0xF0, 0xF8,
- 0x3F, 0xFF, 0x81, 0xDF, 0xF8, 0x0E, 0x3F, 0x00, 0x70, 0x00, 0x03, 0x80,
- 0x00, 0x3C, 0x00, 0x01, 0xC0, 0x00, 0x0E, 0x00, 0x00, 0x70, 0x00, 0x03,
- 0x80, 0x00, 0x00, 0x00, 0xF8, 0xF0, 0x7F, 0xEE, 0x0F, 0xFF, 0xE1, 0xF0,
- 0xFE, 0x3C, 0x07, 0xE3, 0x80, 0x3E, 0x70, 0x03, 0xC7, 0x00, 0x3C, 0x70,
- 0x03, 0xCE, 0x00, 0x3C, 0xE0, 0x07, 0x8E, 0x00, 0x78, 0xE0, 0x07, 0x8E,
- 0x00, 0xF8, 0xF0, 0x1F, 0x87, 0x87, 0xF0, 0x7F, 0xF7, 0x03, 0xFE, 0x70,
- 0x0F, 0x8F, 0x00, 0x00, 0xF0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E,
- 0x00, 0x01, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x04, 0x00, 0x1E,
- 0x78, 0xE7, 0xC7, 0x7C, 0x3F, 0x01, 0xF0, 0x0F, 0x00, 0xF0, 0x07, 0x00,
- 0x38, 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E,
- 0x00, 0x70, 0x07, 0x00, 0x38, 0x00, 0x01, 0xF8, 0x07, 0xFE, 0x0F, 0xFF,
- 0x1E, 0x0F, 0x3C, 0x07, 0x38, 0x07, 0x38, 0x00, 0x3C, 0x00, 0x3F, 0x80,
- 0x1F, 0xF8, 0x07, 0xFC, 0x00, 0x7E, 0x00, 0x0E, 0xE0, 0x0E, 0xE0, 0x1E,
- 0xF0, 0x3C, 0x7F, 0xF8, 0x7F, 0xF0, 0x1F, 0xC0, 0x0E, 0x03, 0x80, 0xE0,
- 0x38, 0x7F, 0xDF, 0xEF, 0xF8, 0x70, 0x1C, 0x0E, 0x03, 0x80, 0xE0, 0x38,
- 0x1E, 0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F, 0x03, 0x80, 0xFC, 0x3F, 0x07,
- 0x80, 0x1C, 0x03, 0xC7, 0x00, 0xE1, 0xC0, 0x38, 0xF0, 0x0E, 0x38, 0x03,
- 0x8E, 0x00, 0xE3, 0x80, 0x70, 0xE0, 0x1C, 0x78, 0x07, 0x1C, 0x01, 0xC7,
- 0x00, 0x71, 0xC0, 0x3C, 0x70, 0x0E, 0x38, 0x07, 0x8E, 0x03, 0xE3, 0x81,
- 0xF8, 0xFF, 0xFE, 0x1F, 0xFF, 0x03, 0xF1, 0xC0, 0xE0, 0x07, 0xE0, 0x0F,
- 0xE0, 0x0E, 0xE0, 0x1C, 0x70, 0x1C, 0x70, 0x38, 0x70, 0x38, 0x70, 0x70,
- 0x70, 0xF0, 0x70, 0xE0, 0x71, 0xC0, 0x71, 0xC0, 0x33, 0x80, 0x3B, 0x80,
- 0x3F, 0x00, 0x3F, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0xE0, 0x1C,
- 0x07, 0xE0, 0x3C, 0x0E, 0xE0, 0x3C, 0x0E, 0xE0, 0x7C, 0x1C, 0xE0, 0x7C,
- 0x1C, 0xE0, 0xEC, 0x38, 0xE0, 0xEC, 0x38, 0x61, 0xCC, 0x70, 0x61, 0xCC,
- 0x70, 0x63, 0x8C, 0xE0, 0x73, 0x8C, 0xE0, 0x77, 0x0C, 0xC0, 0x77, 0x0D,
- 0xC0, 0x7E, 0x0D, 0x80, 0x7E, 0x0F, 0x80, 0x7C, 0x0F, 0x80, 0x7C, 0x0F,
- 0x00, 0x78, 0x0F, 0x00, 0x78, 0x0E, 0x00, 0x0E, 0x00, 0xE1, 0xE0, 0x38,
- 0x1C, 0x0E, 0x03, 0xC3, 0x80, 0x38, 0xE0, 0x07, 0xBC, 0x00, 0x77, 0x00,
- 0x0F, 0xC0, 0x00, 0xF0, 0x00, 0x1C, 0x00, 0x07, 0xC0, 0x01, 0xF8, 0x00,
- 0x77, 0x80, 0x1E, 0x70, 0x07, 0x8F, 0x00, 0xE0, 0xE0, 0x38, 0x1C, 0x0E,
- 0x01, 0xC3, 0x80, 0x38, 0x00, 0x0E, 0x00, 0x70, 0xF0, 0x0F, 0x07, 0x00,
- 0xE0, 0x70, 0x1C, 0x07, 0x01, 0xC0, 0x70, 0x38, 0x07, 0x03, 0x80, 0x70,
- 0x70, 0x07, 0x07, 0x00, 0x70, 0xE0, 0x03, 0x9E, 0x00, 0x39, 0xC0, 0x03,
- 0xB8, 0x00, 0x3B, 0x80, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00,
- 0x1E, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00,
- 0x07, 0x00, 0x00, 0xE0, 0x00, 0xFE, 0x00, 0x0F, 0xC0, 0x00, 0xF0, 0x00,
- 0x00, 0x07, 0xFF, 0xC0, 0xFF, 0xF8, 0x3F, 0xFF, 0x00, 0x01, 0xC0, 0x00,
- 0x70, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0x70, 0x00, 0x1C,
- 0x00, 0x07, 0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00,
- 0x03, 0xC0, 0x00, 0x7F, 0xFE, 0x1F, 0xFF, 0xC3, 0xFF, 0xF8, 0x00, 0x00,
- 0x70, 0x1F, 0x01, 0xF0, 0x3C, 0x03, 0x80, 0x38, 0x07, 0x00, 0x70, 0x07,
- 0x00, 0x70, 0x07, 0x00, 0xE0, 0x0E, 0x01, 0xE0, 0x3C, 0x0F, 0x80, 0xE0,
- 0x0F, 0x00, 0x78, 0x03, 0x80, 0x38, 0x03, 0x80, 0x38, 0x03, 0x80, 0x38,
- 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x0E, 0x00, 0xF8, 0x0F, 0x80, 0x78,
- 0x00, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03,
- 0x01, 0x81, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x18, 0x0C, 0x06, 0x03, 0x01,
- 0x81, 0x80, 0xC0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x06, 0x03, 0x03, 0x01,
- 0x80, 0xC0, 0x00, 0x01, 0xE0, 0x1F, 0x01, 0xF0, 0x07, 0x00, 0xE0, 0x0E,
- 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x1C,
- 0x01, 0xE0, 0x0F, 0x00, 0x70, 0x1F, 0x03, 0xC0, 0x78, 0x07, 0x00, 0x70,
- 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x03, 0xC0,
- 0xF8, 0x0F, 0x80, 0xE0, 0x00, 0x1C, 0x00, 0x3F, 0x00, 0x7F, 0x83, 0x63,
- 0xC7, 0xC1, 0xFE, 0x00, 0xFC, 0x00, 0x78 };
-
-const GFXglyph FreeSansOblique18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 10, 0, 1 }, // 0x20 ' '
- { 0, 9, 26, 10, 4, -25 }, // 0x21 '!'
- { 30, 10, 9, 12, 6, -24 }, // 0x22 '"'
- { 42, 21, 25, 19, 2, -24 }, // 0x23 '#'
- { 108, 20, 31, 19, 2, -26 }, // 0x24 '$'
- { 186, 26, 25, 31, 5, -24 }, // 0x25 '%'
- { 268, 20, 25, 23, 3, -24 }, // 0x26 '&'
- { 331, 4, 9, 7, 6, -24 }, // 0x27 '''
- { 336, 12, 33, 12, 4, -25 }, // 0x28 '('
- { 386, 12, 33, 12, -1, -24 }, // 0x29 ')'
- { 436, 10, 10, 14, 6, -25 }, // 0x2A '*'
- { 449, 18, 16, 20, 3, -15 }, // 0x2B '+'
- { 485, 5, 8, 10, 2, -2 }, // 0x2C ','
- { 490, 9, 3, 12, 3, -10 }, // 0x2D '-'
- { 494, 4, 4, 10, 3, -3 }, // 0x2E '.'
- { 496, 15, 26, 10, 0, -25 }, // 0x2F '/'
- { 545, 18, 25, 19, 3, -24 }, // 0x30 '0'
- { 602, 10, 25, 19, 7, -24 }, // 0x31 '1'
- { 634, 20, 25, 19, 2, -24 }, // 0x32 '2'
- { 697, 19, 25, 19, 2, -24 }, // 0x33 '3'
- { 757, 18, 25, 19, 2, -24 }, // 0x34 '4'
- { 814, 20, 25, 19, 2, -24 }, // 0x35 '5'
- { 877, 19, 25, 19, 3, -24 }, // 0x36 '6'
- { 937, 18, 25, 19, 5, -24 }, // 0x37 '7'
- { 994, 19, 25, 19, 3, -24 }, // 0x38 '8'
- { 1054, 19, 25, 19, 2, -24 }, // 0x39 '9'
- { 1114, 7, 19, 10, 4, -18 }, // 0x3A ':'
- { 1131, 8, 24, 10, 3, -18 }, // 0x3B ';'
- { 1155, 19, 17, 20, 3, -16 }, // 0x3C '<'
- { 1196, 18, 9, 20, 3, -12 }, // 0x3D '='
- { 1217, 19, 17, 20, 2, -15 }, // 0x3E '>'
- { 1258, 16, 26, 19, 6, -25 }, // 0x3F '?'
- { 1310, 33, 31, 36, 3, -25 }, // 0x40 '@'
- { 1438, 23, 26, 23, 0, -25 }, // 0x41 'A'
- { 1513, 21, 26, 23, 3, -25 }, // 0x42 'B'
- { 1582, 22, 26, 25, 4, -25 }, // 0x43 'C'
- { 1654, 23, 26, 25, 3, -25 }, // 0x44 'D'
- { 1729, 23, 26, 23, 3, -25 }, // 0x45 'E'
- { 1804, 22, 26, 21, 3, -25 }, // 0x46 'F'
- { 1876, 24, 26, 27, 4, -25 }, // 0x47 'G'
- { 1954, 25, 26, 25, 3, -25 }, // 0x48 'H'
- { 2036, 8, 26, 10, 4, -25 }, // 0x49 'I'
- { 2062, 18, 26, 18, 2, -25 }, // 0x4A 'J'
- { 2121, 25, 26, 23, 3, -25 }, // 0x4B 'K'
- { 2203, 16, 26, 19, 3, -25 }, // 0x4C 'L'
- { 2255, 29, 26, 30, 3, -25 }, // 0x4D 'M'
- { 2350, 25, 26, 26, 3, -25 }, // 0x4E 'N'
- { 2432, 24, 26, 27, 4, -25 }, // 0x4F 'O'
- { 2510, 22, 26, 23, 3, -25 }, // 0x50 'P'
- { 2582, 25, 28, 27, 4, -25 }, // 0x51 'Q'
- { 2670, 23, 26, 25, 3, -25 }, // 0x52 'R'
- { 2745, 22, 26, 23, 3, -25 }, // 0x53 'S'
- { 2817, 20, 26, 21, 6, -25 }, // 0x54 'T'
- { 2882, 24, 26, 25, 4, -25 }, // 0x55 'U'
- { 2960, 21, 26, 23, 6, -25 }, // 0x56 'V'
- { 3029, 32, 26, 33, 6, -25 }, // 0x57 'W'
- { 3133, 27, 26, 23, 1, -25 }, // 0x58 'X'
- { 3221, 23, 26, 24, 6, -25 }, // 0x59 'Y'
- { 3296, 25, 26, 21, 1, -25 }, // 0x5A 'Z'
- { 3378, 13, 33, 10, 1, -25 }, // 0x5B '['
- { 3432, 4, 26, 10, 5, -25 }, // 0x5C '\'
- { 3445, 13, 33, 10, -1, -24 }, // 0x5D ']'
- { 3499, 14, 14, 16, 3, -24 }, // 0x5E '^'
- { 3524, 21, 2, 19, -2, 5 }, // 0x5F '_'
- { 3530, 6, 5, 12, 6, -25 }, // 0x60 '`'
- { 3534, 18, 19, 19, 2, -18 }, // 0x61 'a'
- { 3577, 19, 26, 20, 2, -25 }, // 0x62 'b'
- { 3639, 16, 19, 18, 3, -18 }, // 0x63 'c'
- { 3677, 20, 26, 20, 3, -25 }, // 0x64 'd'
- { 3742, 17, 19, 19, 3, -18 }, // 0x65 'e'
- { 3783, 11, 26, 9, 2, -25 }, // 0x66 'f'
- { 3819, 19, 27, 19, 2, -18 }, // 0x67 'g'
- { 3884, 18, 26, 19, 2, -25 }, // 0x68 'h'
- { 3943, 8, 26, 8, 2, -25 }, // 0x69 'i'
- { 3969, 14, 34, 8, -2, -25 }, // 0x6A 'j'
- { 4029, 19, 26, 18, 2, -25 }, // 0x6B 'k'
- { 4091, 8, 26, 8, 2, -25 }, // 0x6C 'l'
- { 4117, 27, 19, 29, 2, -18 }, // 0x6D 'm'
- { 4182, 18, 19, 19, 2, -18 }, // 0x6E 'n'
- { 4225, 17, 19, 19, 3, -18 }, // 0x6F 'o'
- { 4266, 21, 26, 20, 0, -18 }, // 0x70 'p'
- { 4335, 20, 27, 19, 2, -18 }, // 0x71 'q'
- { 4403, 13, 19, 11, 2, -18 }, // 0x72 'r'
- { 4434, 16, 19, 18, 2, -18 }, // 0x73 's'
- { 4472, 10, 23, 9, 3, -22 }, // 0x74 't'
- { 4501, 18, 19, 19, 3, -18 }, // 0x75 'u'
- { 4544, 16, 19, 17, 4, -18 }, // 0x76 'v'
- { 4582, 24, 19, 25, 4, -18 }, // 0x77 'w'
- { 4639, 19, 19, 17, 1, -18 }, // 0x78 'x'
- { 4685, 20, 27, 17, 0, -18 }, // 0x79 'y'
- { 4753, 19, 19, 17, 1, -18 }, // 0x7A 'z'
- { 4799, 12, 33, 12, 3, -25 }, // 0x7B '{'
- { 4849, 9, 33, 9, 2, -25 }, // 0x7C '|'
- { 4887, 12, 33, 12, 0, -24 }, // 0x7D '}'
- { 4937, 16, 7, 20, 5, -15 } }; // 0x7E '~'
-
-const GFXfont FreeSansOblique18pt7b PROGMEM = {
- (uint8_t *)FreeSansOblique18pt7bBitmaps,
- (GFXglyph *)FreeSansOblique18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 5623 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique24pt7b.h
deleted file mode 100644
index 4c8c8ab..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique24pt7b.h
+++ /dev/null
@@ -1,840 +0,0 @@
-const uint8_t FreeSansOblique24pt7bBitmaps[] PROGMEM = {
- 0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x3C, 0x07,
- 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x03,
- 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x38, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1E, 0x07, 0x80, 0xF0, 0x1E, 0x00, 0x78,
- 0x7B, 0xC3, 0xDE, 0x1F, 0xE1, 0xEF, 0x0F, 0x78, 0x7B, 0xC3, 0xDC, 0x1C,
- 0xE0, 0xE7, 0x07, 0x30, 0x31, 0x81, 0x80, 0x00, 0x07, 0x81, 0xC0, 0x00,
- 0x78, 0x3C, 0x00, 0x07, 0x03, 0xC0, 0x00, 0xF0, 0x38, 0x00, 0x0E, 0x07,
- 0x80, 0x01, 0xE0, 0x70, 0x00, 0x1E, 0x0F, 0x00, 0x01, 0xC0, 0xF0, 0x00,
- 0x3C, 0x0E, 0x00, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF,
- 0xFE, 0x00, 0x70, 0x3C, 0x00, 0x0F, 0x03, 0x80, 0x00, 0xF0, 0x78, 0x00,
- 0x0E, 0x07, 0x80, 0x01, 0xE0, 0x70, 0x00, 0x1C, 0x0F, 0x00, 0x03, 0xC0,
- 0xE0, 0x00, 0x3C, 0x1E, 0x00, 0x03, 0x81, 0xE0, 0x0F, 0xFF, 0xFF, 0xE0,
- 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xE0, 0x0F, 0x03, 0x80, 0x00, 0xE0,
- 0x78, 0x00, 0x1E, 0x07, 0x00, 0x01, 0xC0, 0xF0, 0x00, 0x1C, 0x0F, 0x00,
- 0x03, 0xC0, 0xE0, 0x00, 0x38, 0x1E, 0x00, 0x07, 0x81, 0xC0, 0x00, 0x78,
- 0x3C, 0x00, 0x07, 0x03, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x30,
- 0x00, 0x00, 0x7F, 0x80, 0x00, 0xFF, 0xF8, 0x00, 0x7F, 0xFF, 0x00, 0x7F,
- 0xFF, 0xE0, 0x1F, 0x18, 0xF8, 0x0F, 0x8E, 0x1F, 0x07, 0xC3, 0x83, 0xC1,
- 0xE0, 0xE0, 0xF0, 0x70, 0x38, 0x3C, 0x3C, 0x0C, 0x0F, 0x0F, 0x07, 0x00,
- 0x03, 0xC1, 0xC0, 0x00, 0xF0, 0x70, 0x00, 0x3E, 0x1C, 0x00, 0x0F, 0xE6,
- 0x00, 0x01, 0xFF, 0xC0, 0x00, 0x3F, 0xFE, 0x00, 0x03, 0xFF, 0xE0, 0x00,
- 0x3F, 0xFC, 0x00, 0x03, 0xFF, 0x80, 0x01, 0xC7, 0xF0, 0x00, 0x70, 0x7C,
- 0x00, 0x1C, 0x0F, 0x00, 0x06, 0x03, 0xCF, 0x03, 0x80, 0xF3, 0xC0, 0xE0,
- 0x3C, 0xF0, 0x38, 0x0E, 0x3C, 0x0E, 0x07, 0x8F, 0x03, 0x01, 0xE3, 0xE1,
- 0xC0, 0xF0, 0xF8, 0x70, 0x78, 0x1F, 0x9C, 0xFC, 0x03, 0xFF, 0xFE, 0x00,
- 0x7F, 0xFF, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00,
- 0x00, 0x03, 0x00, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x07, 0x80, 0x1F, 0x00, 0x00, 0x70, 0x07, 0xFC, 0x00, 0x0E,
- 0x00, 0xFF, 0xE0, 0x01, 0xC0, 0x1E, 0x1E, 0x00, 0x3C, 0x03, 0x80, 0xF0,
- 0x03, 0x80, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x0E, 0x00, 0xE0,
- 0x07, 0x01, 0xC0, 0x0E, 0x00, 0x70, 0x3C, 0x00, 0xE0, 0x0E, 0x03, 0x80,
- 0x0E, 0x00, 0xE0, 0x70, 0x00, 0xF0, 0x1C, 0x0E, 0x00, 0x07, 0x87, 0xC1,
- 0xE0, 0x00, 0x7F, 0xF8, 0x1C, 0x00, 0x03, 0xFE, 0x03, 0x80, 0x00, 0x0F,
- 0x80, 0x70, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x1F,
- 0x00, 0x00, 0x1C, 0x07, 0xFC, 0x00, 0x03, 0x80, 0xFF, 0xE0, 0x00, 0x70,
- 0x1E, 0x1E, 0x00, 0x0F, 0x03, 0x80, 0xF0, 0x00, 0xE0, 0x70, 0x07, 0x00,
- 0x1C, 0x07, 0x00, 0x70, 0x03, 0x80, 0xE0, 0x07, 0x00, 0x70, 0x0E, 0x00,
- 0x70, 0x0F, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x1C, 0x00,
- 0xF0, 0x1C, 0x03, 0x80, 0x07, 0x87, 0xC0, 0x70, 0x00, 0x7F, 0xF8, 0x07,
- 0x00, 0x03, 0xFE, 0x00, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0x01, 0xF8, 0x00,
- 0x03, 0xFF, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0xF8, 0x7C, 0x00, 0x78, 0x0F,
- 0x00, 0x1E, 0x03, 0xC0, 0x0F, 0x00, 0xF0, 0x03, 0xC0, 0x3C, 0x00, 0xF0,
- 0x1E, 0x00, 0x3C, 0x07, 0x80, 0x0F, 0x87, 0xC0, 0x01, 0xE3, 0xE0, 0x00,
- 0x7F, 0xF0, 0x00, 0x0F, 0xF8, 0x00, 0x03, 0xF8, 0x00, 0x03, 0xFC, 0x00,
- 0x03, 0xFF, 0x00, 0x01, 0xFB, 0xE0, 0x70, 0xF8, 0x7C, 0x1C, 0x7C, 0x1F,
- 0x0E, 0x3C, 0x03, 0xE3, 0x9E, 0x00, 0x79, 0xE7, 0x80, 0x1F, 0xF3, 0xC0,
- 0x03, 0xF8, 0xF0, 0x00, 0xFE, 0x3C, 0x00, 0x1F, 0x0F, 0x00, 0x07, 0xC3,
- 0xE0, 0x03, 0xF8, 0xF8, 0x03, 0xFE, 0x3F, 0x83, 0xF7, 0xC7, 0xFF, 0xF8,
- 0xF0, 0xFF, 0xFC, 0x3E, 0x1F, 0xFC, 0x07, 0x81, 0xFC, 0x00, 0x00, 0x7B,
- 0xDF, 0xEF, 0x7B, 0xDC, 0xE7, 0x31, 0x80, 0x00, 0x0E, 0x00, 0x38, 0x00,
- 0xE0, 0x03, 0x80, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xE0, 0x03, 0x80,
- 0x0F, 0x00, 0x1C, 0x00, 0x78, 0x00, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E,
- 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,
- 0x1C, 0x00, 0x78, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E,
- 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80,
- 0x07, 0x00, 0x06, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00,
- 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0x00, 0x30, 0x00, 0x70, 0x00, 0xE0,
- 0x00, 0xC0, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0E, 0x00,
- 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80, 0x07,
- 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x01, 0xE0, 0x03, 0x80,
- 0x07, 0x00, 0x0E, 0x00, 0x3C, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x07,
- 0x00, 0x0E, 0x00, 0x3C, 0x00, 0x70, 0x01, 0xE0, 0x03, 0x80, 0x0F, 0x00,
- 0x1C, 0x00, 0x78, 0x00, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x1C, 0x00, 0x70,
- 0x01, 0xC0, 0x07, 0x00, 0x00, 0x01, 0xC0, 0x07, 0x00, 0x38, 0x18, 0xE3,
- 0x7B, 0xBF, 0xFF, 0xF3, 0xFF, 0x01, 0xE0, 0x1F, 0xC0, 0xF7, 0x07, 0x9E,
- 0x1C, 0x38, 0x20, 0xC0, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x78,
- 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00,
- 0x00, 0x1C, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xE0, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07,
- 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x3E, 0x7C, 0xF9, 0xE7,
- 0xC1, 0x83, 0x0C, 0x18, 0x63, 0xC6, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFE, 0x7D, 0xF7, 0xBE, 0xF8, 0x00, 0x00, 0x18, 0x00, 0x01, 0xC0, 0x00,
- 0x1C, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0x70, 0x00, 0x07, 0x00,
- 0x00, 0x30, 0x00, 0x03, 0x80, 0x00, 0x18, 0x00, 0x01, 0xC0, 0x00, 0x0C,
- 0x00, 0x00, 0xE0, 0x00, 0x06, 0x00, 0x00, 0x70, 0x00, 0x03, 0x00, 0x00,
- 0x38, 0x00, 0x01, 0x80, 0x00, 0x1C, 0x00, 0x00, 0xC0, 0x00, 0x0E, 0x00,
- 0x00, 0x60, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x03, 0x80, 0x00, 0x38,
- 0x00, 0x01, 0x80, 0x00, 0x1C, 0x00, 0x00, 0xC0, 0x00, 0x0E, 0x00, 0x00,
- 0x60, 0x00, 0x07, 0x00, 0x00, 0x30, 0x00, 0x03, 0x80, 0x00, 0x18, 0x00,
- 0x00, 0x00, 0x0F, 0xC0, 0x00, 0xFF, 0xE0, 0x03, 0xFF, 0xE0, 0x0F, 0xFF,
- 0xE0, 0x3F, 0x0F, 0xC0, 0xF8, 0x07, 0x81, 0xE0, 0x0F, 0x87, 0x80, 0x0F,
- 0x1F, 0x00, 0x1E, 0x3C, 0x00, 0x3C, 0x78, 0x00, 0x79, 0xE0, 0x00, 0xF3,
- 0xC0, 0x01, 0xE7, 0x80, 0x07, 0xDE, 0x00, 0x0F, 0xBC, 0x00, 0x1E, 0x78,
- 0x00, 0x3C, 0xF0, 0x00, 0x79, 0xE0, 0x00, 0xF7, 0x80, 0x03, 0xEF, 0x00,
- 0x07, 0xDE, 0x00, 0x0F, 0x3C, 0x00, 0x1E, 0x78, 0x00, 0x7C, 0xF0, 0x00,
- 0xF1, 0xE0, 0x03, 0xE3, 0xC0, 0x07, 0x87, 0xC0, 0x1F, 0x0F, 0x80, 0x7C,
- 0x0F, 0xC3, 0xF0, 0x1F, 0xFF, 0xC0, 0x1F, 0xFF, 0x00, 0x1F, 0xFC, 0x00,
- 0x0F, 0xC0, 0x00, 0x00, 0x18, 0x01, 0xC0, 0x1C, 0x01, 0xE0, 0x1F, 0x0F,
- 0xFB, 0xFF, 0xDF, 0xFC, 0xFF, 0xE0, 0x0F, 0x00, 0x78, 0x07, 0xC0, 0x3C,
- 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x07, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00,
- 0x78, 0x07, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x07, 0xC0, 0x3C,
- 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x07, 0xC0, 0x3C, 0x00, 0x00, 0x03, 0xFC,
- 0x00, 0x03, 0xFF, 0xE0, 0x00, 0xFF, 0xFE, 0x00, 0x3F, 0xFF, 0xE0, 0x0F,
- 0xC0, 0xFC, 0x03, 0xE0, 0x07, 0xC0, 0xF8, 0x00, 0xF8, 0x1F, 0x00, 0x0F,
- 0x03, 0xC0, 0x01, 0xE0, 0xF8, 0x00, 0x3C, 0x1E, 0x00, 0x07, 0x80, 0x00,
- 0x01, 0xE0, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x03, 0xE0,
- 0x00, 0x00, 0xF8, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x1F,
- 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x00,
- 0xFC, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x03, 0xE0, 0x00,
- 0x00, 0xF8, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0xFF,
- 0xFF, 0xFC, 0x3F, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFC,
- 0x00, 0x00, 0x07, 0xF0, 0x00, 0x1F, 0xFE, 0x00, 0x3F, 0xFF, 0x80, 0x3F,
- 0xFF, 0xE0, 0x1F, 0x81, 0xF8, 0x1F, 0x00, 0x7C, 0x1F, 0x00, 0x1E, 0x0F,
- 0x00, 0x0F, 0x0F, 0x80, 0x07, 0x87, 0x80, 0x03, 0xC0, 0x00, 0x03, 0xC0,
- 0x00, 0x01, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0xE0,
- 0x00, 0x3F, 0xE0, 0x00, 0x1F, 0xF8, 0x00, 0x1F, 0xFE, 0x00, 0x00, 0x3F,
- 0x00, 0x00, 0x07, 0xC0, 0x00, 0x01, 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00,
- 0x79, 0xE0, 0x00, 0x3C, 0xF0, 0x00, 0x1E, 0x78, 0x00, 0x1E, 0x3C, 0x00,
- 0x0F, 0x1E, 0x00, 0x0F, 0x0F, 0x80, 0x1F, 0x83, 0xF0, 0x3F, 0x81, 0xFF,
- 0xFF, 0x80, 0x7F, 0xFF, 0x80, 0x1F, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x00,
- 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7E,
- 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xBC,
- 0x00, 0x0F, 0xBC, 0x00, 0x1F, 0x7C, 0x00, 0x3E, 0x78, 0x00, 0x7C, 0x78,
- 0x00, 0xF8, 0x78, 0x00, 0xF0, 0x78, 0x01, 0xE0, 0xF0, 0x03, 0xC0, 0xF0,
- 0x07, 0x80, 0xF0, 0x0F, 0x00, 0xF0, 0x1E, 0x01, 0xF0, 0x3C, 0x01, 0xE0,
- 0x78, 0x01, 0xE0, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
- 0xFF, 0xFF, 0xFE, 0x00, 0x03, 0xC0, 0x00, 0x03, 0xC0, 0x00, 0x03, 0xC0,
- 0x00, 0x07, 0x80, 0x00, 0x07, 0x80, 0x00, 0x07, 0x80, 0x00, 0x07, 0x80,
- 0x00, 0x0F, 0x80, 0x00, 0x7F, 0xFF, 0xC0, 0x1F, 0xFF, 0xF8, 0x03, 0xFF,
- 0xFF, 0x00, 0x7F, 0xFF, 0xE0, 0x1E, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x00,
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- 0x00, 0x1E, 0x00 };
-
-const GFXglyph FreeSansOblique24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 13, 0, 1 }, // 0x20 ' '
- { 0, 11, 34, 13, 6, -33 }, // 0x21 '!'
- { 47, 13, 12, 17, 8, -32 }, // 0x22 '"'
- { 67, 28, 34, 26, 3, -32 }, // 0x23 '#'
- { 186, 26, 42, 26, 3, -35 }, // 0x24 '$'
- { 323, 36, 34, 42, 6, -32 }, // 0x25 '%'
- { 476, 26, 34, 31, 4, -32 }, // 0x26 '&'
- { 587, 5, 12, 9, 8, -32 }, // 0x27 '''
- { 595, 15, 44, 16, 5, -33 }, // 0x28 '('
- { 678, 15, 44, 16, 1, -33 }, // 0x29 ')'
- { 761, 14, 13, 18, 8, -33 }, // 0x2A '*'
- { 784, 23, 22, 27, 5, -20 }, // 0x2B '+'
- { 848, 7, 12, 13, 3, -4 }, // 0x2C ','
- { 859, 12, 4, 16, 5, -14 }, // 0x2D '-'
- { 865, 6, 5, 13, 4, -4 }, // 0x2E '.'
- { 869, 21, 35, 13, -1, -33 }, // 0x2F '/'
- { 961, 23, 34, 26, 5, -32 }, // 0x30 '0'
- { 1059, 13, 33, 26, 10, -32 }, // 0x31 '1'
- { 1113, 27, 33, 26, 2, -32 }, // 0x32 '2'
- { 1225, 25, 34, 26, 3, -32 }, // 0x33 '3'
- { 1332, 24, 33, 26, 3, -32 }, // 0x34 '4'
- { 1431, 27, 34, 26, 3, -32 }, // 0x35 '5'
- { 1546, 24, 34, 26, 4, -32 }, // 0x36 '6'
- { 1648, 26, 33, 26, 6, -32 }, // 0x37 '7'
- { 1756, 25, 34, 26, 3, -32 }, // 0x38 '8'
- { 1863, 24, 34, 26, 4, -32 }, // 0x39 '9'
- { 1965, 10, 25, 13, 5, -24 }, // 0x3A ':'
- { 1997, 11, 32, 13, 4, -24 }, // 0x3B ';'
- { 2041, 26, 23, 27, 4, -22 }, // 0x3C '<'
- { 2116, 26, 12, 27, 3, -16 }, // 0x3D '='
- { 2155, 26, 23, 27, 2, -21 }, // 0x3E '>'
- { 2230, 20, 35, 26, 9, -34 }, // 0x3F '?'
- { 2318, 45, 42, 48, 4, -34 }, // 0x40 '@'
- { 2555, 30, 34, 31, 1, -33 }, // 0x41 'A'
- { 2683, 29, 34, 31, 4, -33 }, // 0x42 'B'
- { 2807, 30, 36, 33, 5, -34 }, // 0x43 'C'
- { 2942, 31, 34, 33, 4, -33 }, // 0x44 'D'
- { 3074, 31, 34, 31, 4, -33 }, // 0x45 'E'
- { 3206, 30, 34, 28, 4, -33 }, // 0x46 'F'
- { 3334, 33, 36, 37, 5, -34 }, // 0x47 'G'
- { 3483, 33, 34, 34, 4, -33 }, // 0x48 'H'
- { 3624, 11, 34, 13, 5, -33 }, // 0x49 'I'
- { 3671, 25, 35, 24, 2, -33 }, // 0x4A 'J'
- { 3781, 34, 34, 31, 4, -33 }, // 0x4B 'K'
- { 3926, 22, 34, 26, 4, -33 }, // 0x4C 'L'
- { 4020, 39, 34, 40, 4, -33 }, // 0x4D 'M'
- { 4186, 34, 34, 34, 4, -33 }, // 0x4E 'N'
- { 4331, 33, 36, 36, 5, -34 }, // 0x4F 'O'
- { 4480, 29, 34, 30, 4, -33 }, // 0x50 'P'
- { 4604, 33, 38, 36, 5, -34 }, // 0x51 'Q'
- { 4761, 30, 34, 33, 4, -33 }, // 0x52 'R'
- { 4889, 29, 36, 31, 4, -34 }, // 0x53 'S'
- { 5020, 28, 34, 29, 7, -33 }, // 0x54 'T'
- { 5139, 31, 35, 34, 6, -33 }, // 0x55 'U'
- { 5275, 29, 34, 30, 8, -33 }, // 0x56 'V'
- { 5399, 43, 34, 44, 8, -33 }, // 0x57 'W'
- { 5582, 36, 34, 31, 1, -33 }, // 0x58 'X'
- { 5735, 30, 34, 32, 8, -33 }, // 0x59 'Y'
- { 5863, 34, 34, 29, 1, -33 }, // 0x5A 'Z'
- { 6008, 18, 44, 13, 1, -33 }, // 0x5B '['
- { 6107, 6, 35, 13, 7, -33 }, // 0x5C '\'
- { 6134, 18, 44, 13, -1, -33 }, // 0x5D ']'
- { 6233, 17, 18, 22, 6, -32 }, // 0x5E '^'
- { 6272, 29, 2, 26, -3, 7 }, // 0x5F '_'
- { 6280, 8, 7, 16, 8, -34 }, // 0x60 '`'
- { 6287, 23, 27, 26, 3, -25 }, // 0x61 'a'
- { 6365, 25, 35, 26, 3, -33 }, // 0x62 'b'
- { 6475, 22, 27, 24, 4, -25 }, // 0x63 'c'
- { 6550, 27, 35, 26, 4, -33 }, // 0x64 'd'
- { 6669, 23, 27, 26, 4, -25 }, // 0x65 'e'
- { 6747, 15, 34, 12, 3, -33 }, // 0x66 'f'
- { 6811, 27, 36, 26, 2, -25 }, // 0x67 'g'
- { 6933, 23, 34, 25, 3, -33 }, // 0x68 'h'
- { 7031, 11, 34, 10, 3, -33 }, // 0x69 'i'
- { 7078, 18, 44, 11, -2, -33 }, // 0x6A 'j'
- { 7177, 25, 34, 24, 3, -33 }, // 0x6B 'k'
- { 7284, 11, 34, 10, 3, -33 }, // 0x6C 'l'
- { 7331, 36, 26, 38, 3, -25 }, // 0x6D 'm'
- { 7448, 23, 26, 25, 3, -25 }, // 0x6E 'n'
- { 7523, 23, 27, 26, 4, -25 }, // 0x6F 'o'
- { 7601, 27, 36, 26, 1, -25 }, // 0x70 'p'
- { 7723, 26, 36, 26, 3, -25 }, // 0x71 'q'
- { 7840, 17, 26, 15, 3, -25 }, // 0x72 'r'
- { 7896, 21, 27, 24, 3, -25 }, // 0x73 's'
- { 7967, 13, 32, 12, 4, -30 }, // 0x74 't'
- { 8019, 24, 26, 25, 4, -24 }, // 0x75 'u'
- { 8097, 22, 25, 23, 6, -24 }, // 0x76 'v'
- { 8166, 33, 25, 34, 6, -24 }, // 0x77 'w'
- { 8270, 26, 25, 23, 1, -24 }, // 0x78 'x'
- { 8352, 27, 35, 23, 0, -24 }, // 0x79 'y'
- { 8471, 25, 25, 23, 1, -24 }, // 0x7A 'z'
- { 8550, 16, 44, 16, 5, -33 }, // 0x7B '{'
- { 8638, 12, 44, 12, 3, -33 }, // 0x7C '|'
- { 8704, 16, 44, 16, -1, -33 }, // 0x7D '}'
- { 8792, 21, 7, 27, 6, -19 } }; // 0x7E '~'
-
-const GFXfont FreeSansOblique24pt7b PROGMEM = {
- (uint8_t *)FreeSansOblique24pt7bBitmaps,
- (GFXglyph *)FreeSansOblique24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 9483 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique9pt7b.h
deleted file mode 100644
index 18a6cbe..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSansOblique9pt7b.h
+++ /dev/null
@@ -1,220 +0,0 @@
-const uint8_t FreeSansOblique9pt7bBitmaps[] PROGMEM = {
- 0x10, 0x84, 0x22, 0x10, 0x84, 0x42, 0x10, 0x08, 0x00, 0xDE, 0xE5, 0x20,
- 0x06, 0x40, 0x88, 0x13, 0x06, 0x43, 0xFE, 0x32, 0x04, 0x40, 0x98, 0x32,
- 0x1F, 0xF0, 0x98, 0x22, 0x04, 0xC0, 0x02, 0x01, 0xF8, 0x6B, 0x99, 0x33,
- 0x40, 0x68, 0x0F, 0x00, 0xF8, 0x07, 0xC1, 0x1B, 0x23, 0x64, 0x4E, 0x98,
- 0xFC, 0x04, 0x00, 0x80, 0x3C, 0x08, 0xCC, 0x23, 0x18, 0x86, 0x32, 0x0C,
- 0x64, 0x19, 0x90, 0x1E, 0x40, 0x01, 0x1E, 0x02, 0x66, 0x09, 0x8C, 0x23,
- 0x18, 0x86, 0x62, 0x07, 0x80, 0x0F, 0x06, 0x63, 0x18, 0xC6, 0x3F, 0x07,
- 0x03, 0xC1, 0xB3, 0xC7, 0xB0, 0xCC, 0x33, 0x3E, 0x79, 0x80, 0xFA, 0x04,
- 0x10, 0x60, 0x83, 0x04, 0x18, 0x30, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x10,
- 0x30, 0x20, 0x08, 0x18, 0x10, 0x30, 0x60, 0xC1, 0x83, 0x06, 0x18, 0x30,
- 0x41, 0x82, 0x0C, 0x10, 0x40, 0x19, 0x73, 0x16, 0x48, 0x04, 0x04, 0x02,
- 0x1F, 0xF0, 0x80, 0x80, 0x40, 0x20, 0x6D, 0x28, 0xF0, 0xC0, 0x01, 0x02,
- 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x40, 0x40, 0x80, 0x0F,
- 0x19, 0xC8, 0x6C, 0x36, 0x1A, 0x0F, 0x05, 0x86, 0xC3, 0x61, 0xB1, 0x9C,
- 0x87, 0x80, 0x08, 0xCD, 0xE3, 0x18, 0xC4, 0x23, 0x18, 0xC4, 0x00, 0x07,
- 0x83, 0x1C, 0x41, 0x98, 0x30, 0x06, 0x01, 0x80, 0x60, 0x38, 0x1C, 0x06,
- 0x01, 0x80, 0x20, 0x0F, 0xF8, 0x0F, 0x86, 0x73, 0x0C, 0x83, 0x00, 0xC0,
- 0x60, 0xE0, 0x06, 0x01, 0xB0, 0x6C, 0x13, 0x8C, 0x7C, 0x00, 0x00, 0x80,
- 0xC0, 0xE0, 0xA0, 0x90, 0x98, 0x8C, 0x86, 0xFF, 0x81, 0x01, 0x80, 0xC0,
- 0x60, 0x0F, 0xC3, 0x00, 0x40, 0x08, 0x03, 0x00, 0x7F, 0x1C, 0x70, 0x06,
- 0x00, 0xC0, 0x1B, 0x06, 0x71, 0x87, 0xE0, 0x0F, 0x86, 0x73, 0x0D, 0x80,
- 0x60, 0x1F, 0xCF, 0x3B, 0x86, 0xC1, 0xB0, 0x6C, 0x33, 0x98, 0x3C, 0x00,
- 0x7F, 0xC0, 0x20, 0x10, 0x0C, 0x06, 0x01, 0x00, 0x80, 0x60, 0x10, 0x0C,
- 0x02, 0x01, 0x80, 0x40, 0x00, 0x0F, 0x86, 0x73, 0x0C, 0xC3, 0x30, 0xCC,
- 0x61, 0xE1, 0x86, 0x41, 0xB0, 0x6C, 0x13, 0x8C, 0x3E, 0x00, 0x0F, 0x06,
- 0x73, 0x0D, 0x83, 0x60, 0xD8, 0x77, 0x3C, 0xFE, 0x01, 0x80, 0x6C, 0x33,
- 0x98, 0x7C, 0x00, 0x30, 0x00, 0x00, 0x00, 0xC0, 0x18, 0x00, 0x00, 0x00,
- 0x0C, 0x62, 0x11, 0x00, 0x00, 0x01, 0xC3, 0x8F, 0x0C, 0x07, 0x00, 0xE0,
- 0x1E, 0x01, 0x00, 0x7F, 0xC0, 0x00, 0x03, 0xFE, 0x40, 0x3C, 0x03, 0x80,
- 0x70, 0x18, 0x78, 0xE1, 0xC0, 0x00, 0x00, 0x1F, 0x30, 0xD0, 0x78, 0x30,
- 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xFE,
- 0x00, 0xC0, 0xE0, 0xC0, 0x18, 0x61, 0xD3, 0x31, 0x9C, 0xD8, 0xC2, 0x36,
- 0x31, 0x8F, 0x18, 0x67, 0xC6, 0x11, 0xB1, 0x8C, 0xCC, 0x67, 0x63, 0x0E,
- 0xF0, 0x60, 0x00, 0x1C, 0x00, 0x01, 0x81, 0x00, 0x1F, 0xC0, 0x01, 0xC0,
- 0x1C, 0x03, 0xC0, 0x24, 0x06, 0x60, 0x46, 0x0C, 0x61, 0x86, 0x1F, 0xE3,
- 0x06, 0x20, 0x26, 0x03, 0x40, 0x30, 0x1F, 0xE1, 0x87, 0x30, 0x33, 0x03,
- 0x30, 0x23, 0x06, 0x3F, 0xC6, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x0C,
- 0x7F, 0x80, 0x07, 0xC1, 0x86, 0x30, 0x32, 0x03, 0x60, 0x04, 0x00, 0xC0,
- 0x0C, 0x00, 0xC0, 0x6C, 0x06, 0xC0, 0xC6, 0x18, 0x3E, 0x00, 0x1F, 0xE0,
- 0xC1, 0x84, 0x06, 0x60, 0x33, 0x01, 0x98, 0x0C, 0x80, 0x64, 0x02, 0x60,
- 0x33, 0x01, 0x98, 0x18, 0x81, 0x87, 0xF0, 0x00, 0x1F, 0xF1, 0x80, 0x10,
- 0x03, 0x00, 0x30, 0x03, 0x00, 0x3F, 0xE2, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x04, 0x00, 0x7F, 0xC0, 0x1F, 0xF1, 0x80, 0x10, 0x03, 0x00, 0x30, 0x03,
- 0x00, 0x3F, 0xC2, 0x00, 0x60, 0x06, 0x00, 0x60, 0x04, 0x00, 0x40, 0x00,
- 0x07, 0xE0, 0xE1, 0x8C, 0x06, 0xC0, 0x36, 0x00, 0x60, 0x03, 0x07, 0xF8,
- 0x02, 0xC0, 0x36, 0x01, 0x98, 0x1C, 0xE1, 0xC1, 0xF2, 0x00, 0x18, 0x08,
- 0xC0, 0xC4, 0x06, 0x60, 0x33, 0x01, 0x18, 0x18, 0xFF, 0xC4, 0x06, 0x60,
- 0x23, 0x01, 0x18, 0x18, 0x80, 0xC4, 0x06, 0x00, 0x33, 0x32, 0x26, 0x66,
- 0x44, 0xCC, 0xC0, 0x00, 0xC0, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x30,
- 0x0C, 0x03, 0x30, 0xCC, 0x63, 0x18, 0x7C, 0x00, 0x18, 0x18, 0x60, 0xC1,
- 0x0E, 0x0C, 0x60, 0x33, 0x00, 0xD8, 0x03, 0xF0, 0x0C, 0xC0, 0x61, 0x81,
- 0x86, 0x06, 0x0C, 0x10, 0x30, 0x40, 0x60, 0x18, 0x0C, 0x04, 0x06, 0x03,
- 0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x18, 0x08, 0x07, 0xF8, 0x18, 0x06,
- 0x18, 0x0E, 0x18, 0x0E, 0x34, 0x1E, 0x34, 0x36, 0x34, 0x34, 0x24, 0x64,
- 0x24, 0x6C, 0x64, 0xCC, 0x64, 0x8C, 0x65, 0x88, 0x43, 0x08, 0x43, 0x18,
- 0x18, 0x08, 0xE0, 0x47, 0x06, 0x6C, 0x33, 0x61, 0x99, 0x08, 0x8C, 0xC4,
- 0x66, 0x61, 0xB3, 0x0D, 0x18, 0x38, 0x81, 0xC4, 0x06, 0x00, 0x07, 0xC0,
- 0xC3, 0x8C, 0x0E, 0xC0, 0x36, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0,
- 0x36, 0x01, 0xB8, 0x18, 0xE1, 0x81, 0xF0, 0x00, 0x1F, 0xE1, 0x83, 0x10,
- 0x33, 0x03, 0x30, 0x33, 0x06, 0x3F, 0xC2, 0x00, 0x60, 0x06, 0x00, 0x60,
- 0x04, 0x00, 0x40, 0x00, 0x07, 0xC0, 0xC3, 0x8C, 0x0E, 0xC0, 0x36, 0x01,
- 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x36, 0x09, 0xB8, 0x78, 0xE3, 0x81,
- 0xF6, 0x00, 0x10, 0x1F, 0xF0, 0xC0, 0xC4, 0x06, 0x60, 0x33, 0x01, 0x18,
- 0x18, 0xFF, 0x04, 0x0C, 0x60, 0x63, 0x03, 0x18, 0x18, 0x80, 0xC4, 0x06,
- 0x00, 0x07, 0xC1, 0x87, 0x30, 0x33, 0x03, 0x30, 0x03, 0xC0, 0x0F, 0xC0,
- 0x1E, 0x00, 0x6C, 0x06, 0xC0, 0x46, 0x0C, 0x3F, 0x00, 0xFF, 0xC3, 0x00,
- 0xC0, 0x20, 0x18, 0x06, 0x01, 0x80, 0x60, 0x10, 0x0C, 0x03, 0x00, 0xC0,
- 0x20, 0x00, 0x30, 0x13, 0x03, 0x20, 0x36, 0x03, 0x60, 0x26, 0x06, 0x60,
- 0x64, 0x06, 0xC0, 0x6C, 0x04, 0xC0, 0xCE, 0x18, 0x3E, 0x00, 0xC0, 0x78,
- 0x0B, 0x03, 0x20, 0xC4, 0x18, 0xC6, 0x18, 0x83, 0x30, 0x64, 0x0D, 0x80,
- 0xA0, 0x1C, 0x03, 0x00, 0xC1, 0x83, 0xC1, 0x83, 0xC3, 0x86, 0xC2, 0x86,
- 0xC6, 0x84, 0xC4, 0x8C, 0xCC, 0xC8, 0xC8, 0xD8, 0xD8, 0xD0, 0xD0, 0xF0,
- 0x70, 0xE0, 0x60, 0xE0, 0x60, 0xE0, 0x0C, 0x0C, 0x30, 0x60, 0x63, 0x01,
- 0x98, 0x02, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xE0, 0x0C, 0x80, 0x33, 0x01,
- 0x8C, 0x0C, 0x18, 0x60, 0x60, 0xC0, 0x66, 0x0C, 0x60, 0xC2, 0x18, 0x33,
- 0x03, 0x60, 0x1C, 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x01, 0x00, 0x30,
- 0x00, 0x1F, 0xF0, 0x07, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00,
- 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x00, 0xFF, 0xC0, 0x0E, 0x10, 0x20,
- 0x41, 0x02, 0x04, 0x08, 0x20, 0x40, 0x81, 0x04, 0x08, 0x10, 0x20, 0xE0,
- 0xAA, 0xA9, 0x55, 0x40, 0x0E, 0x08, 0x10, 0x20, 0x41, 0x02, 0x04, 0x08,
- 0x20, 0x40, 0x81, 0x04, 0x08, 0x10, 0xE0, 0x0C, 0x18, 0x51, 0xA2, 0x4C,
- 0x50, 0x80, 0xFF, 0xE0, 0xC8, 0x80, 0x0F, 0x86, 0x33, 0x0C, 0x03, 0x03,
- 0xDF, 0xEE, 0x0B, 0x02, 0xC1, 0x9F, 0xE0, 0x10, 0x04, 0x01, 0x00, 0xDC,
- 0x39, 0x88, 0x32, 0x0D, 0x83, 0x40, 0xD0, 0x64, 0x1B, 0x8C, 0xBC, 0x00,
- 0x1F, 0x18, 0xD8, 0x6C, 0x0C, 0x06, 0x03, 0x01, 0x86, 0x66, 0x3E, 0x00,
- 0x00, 0x20, 0x08, 0x01, 0x0F, 0x23, 0x14, 0xC1, 0x18, 0x26, 0x04, 0xC0,
- 0x98, 0x23, 0x04, 0x71, 0x87, 0xD0, 0x0F, 0x0C, 0x76, 0x0D, 0x83, 0xFF,
- 0xF0, 0x0C, 0x03, 0x06, 0x63, 0x0F, 0x80, 0x1C, 0xC2, 0x1E, 0x20, 0x84,
- 0x10, 0x41, 0x04, 0x20, 0x80, 0x0F, 0x46, 0x33, 0x0C, 0xC1, 0x60, 0xD8,
- 0x26, 0x09, 0x86, 0x71, 0x8F, 0xE0, 0x10, 0x04, 0xC2, 0x1F, 0x00, 0x10,
- 0x04, 0x01, 0x00, 0x9F, 0x39, 0x88, 0x22, 0x09, 0x02, 0x40, 0x90, 0x44,
- 0x12, 0x04, 0x81, 0x00, 0x10, 0x02, 0x22, 0x64, 0x44, 0x48, 0x80, 0x04,
- 0x00, 0x01, 0x08, 0x20, 0x82, 0x08, 0x41, 0x04, 0x10, 0x42, 0x08, 0xE0,
- 0x10, 0x08, 0x04, 0x04, 0x32, 0x31, 0x20, 0xA0, 0xB8, 0x6C, 0x22, 0x11,
- 0x90, 0xC8, 0x30, 0x11, 0x22, 0x22, 0x64, 0x44, 0x48, 0x80, 0x2F, 0x3C,
- 0x63, 0x8C, 0x86, 0x19, 0x08, 0x44, 0x10, 0x88, 0x21, 0x10, 0x82, 0x21,
- 0x04, 0x82, 0x11, 0x04, 0x20, 0x00, 0x0B, 0xF3, 0x18, 0x82, 0x20, 0x90,
- 0x24, 0x09, 0x04, 0x41, 0x20, 0x48, 0x10, 0x0F, 0x0C, 0x76, 0x0D, 0x83,
- 0xC0, 0xF0, 0x3C, 0x1B, 0x06, 0xE3, 0x0F, 0x00, 0x17, 0xC3, 0x1C, 0x41,
- 0x98, 0x32, 0x06, 0x40, 0xC8, 0x33, 0x06, 0x71, 0x8B, 0xC1, 0x00, 0x20,
- 0x08, 0x01, 0x00, 0x00, 0x1E, 0xCC, 0x66, 0x09, 0x82, 0xC0, 0xB0, 0x4C,
- 0x13, 0x04, 0x63, 0x0F, 0xC0, 0x20, 0x08, 0x02, 0x00, 0x80, 0x2C, 0x60,
- 0x81, 0x04, 0x08, 0x10, 0x20, 0x81, 0x00, 0x1E, 0x33, 0x63, 0x60, 0x70,
- 0x1E, 0x03, 0xC3, 0xC6, 0x7C, 0x22, 0xF2, 0x44, 0x44, 0xCC, 0xCE, 0x21,
- 0x20, 0x90, 0x48, 0x24, 0x12, 0x13, 0x09, 0x84, 0xE6, 0x3E, 0x00, 0xC1,
- 0xE1, 0xB0, 0xC8, 0xC4, 0x43, 0x61, 0xA0, 0xF0, 0x70, 0x18, 0x00, 0xC7,
- 0x1E, 0x38, 0xB3, 0xCD, 0x96, 0x4C, 0xB6, 0x6D, 0xB1, 0x4D, 0x0E, 0x78,
- 0x63, 0x83, 0x1C, 0x00, 0x10, 0xC3, 0x10, 0x24, 0x07, 0x80, 0xE0, 0x1C,
- 0x07, 0x81, 0x90, 0x23, 0x08, 0x20, 0x30, 0x46, 0x18, 0x42, 0x08, 0xC1,
- 0x10, 0x24, 0x07, 0x80, 0xE0, 0x1C, 0x03, 0x00, 0x60, 0x08, 0x03, 0x01,
- 0xC0, 0x00, 0x3F, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
- 0x7F, 0x00, 0x18, 0x88, 0x42, 0x10, 0x88, 0xC3, 0x18, 0x88, 0x42, 0x18,
- 0xE0, 0x11, 0x22, 0x22, 0x24, 0x44, 0x4C, 0x88, 0x88, 0x00, 0x38, 0xC2,
- 0x10, 0x88, 0xC6, 0x18, 0x88, 0x42, 0x10, 0x88, 0xC0, 0x70, 0x4E, 0x41,
- 0xC0 };
-
-const GFXglyph FreeSansOblique9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 5, 13, 5, 2, -12 }, // 0x21 '!'
- { 9, 5, 4, 6, 3, -12 }, // 0x22 '"'
- { 12, 11, 13, 10, 1, -12 }, // 0x23 '#'
- { 30, 11, 16, 10, 1, -13 }, // 0x24 '$'
- { 52, 15, 13, 16, 2, -12 }, // 0x25 '%'
- { 77, 10, 13, 12, 2, -12 }, // 0x26 '&'
- { 94, 2, 4, 3, 3, -12 }, // 0x27 '''
- { 95, 7, 17, 6, 2, -12 }, // 0x28 '('
- { 110, 7, 17, 6, -1, -12 }, // 0x29 ')'
- { 125, 6, 5, 7, 3, -12 }, // 0x2A '*'
- { 129, 9, 8, 11, 2, -7 }, // 0x2B '+'
- { 138, 3, 5, 5, 1, -1 }, // 0x2C ','
- { 140, 4, 1, 6, 2, -4 }, // 0x2D '-'
- { 141, 2, 1, 5, 2, 0 }, // 0x2E '.'
- { 142, 8, 13, 5, 0, -12 }, // 0x2F '/'
- { 155, 9, 13, 10, 2, -12 }, // 0x30 '0'
- { 170, 5, 13, 10, 4, -12 }, // 0x31 '1'
- { 179, 11, 13, 10, 1, -12 }, // 0x32 '2'
- { 197, 10, 13, 10, 1, -12 }, // 0x33 '3'
- { 214, 9, 13, 10, 1, -12 }, // 0x34 '4'
- { 229, 11, 13, 10, 1, -12 }, // 0x35 '5'
- { 247, 10, 13, 10, 2, -12 }, // 0x36 '6'
- { 264, 10, 13, 10, 2, -12 }, // 0x37 '7'
- { 281, 10, 13, 10, 1, -12 }, // 0x38 '8'
- { 298, 10, 13, 10, 1, -12 }, // 0x39 '9'
- { 315, 4, 9, 5, 2, -8 }, // 0x3A ':'
- { 320, 5, 12, 5, 1, -8 }, // 0x3B ';'
- { 328, 9, 9, 11, 2, -8 }, // 0x3C '<'
- { 339, 10, 4, 11, 1, -5 }, // 0x3D '='
- { 344, 9, 9, 11, 1, -7 }, // 0x3E '>'
- { 355, 9, 13, 10, 3, -12 }, // 0x3F '?'
- { 370, 18, 16, 18, 1, -12 }, // 0x40 '@'
- { 406, 12, 13, 12, 0, -12 }, // 0x41 'A'
- { 426, 12, 13, 12, 1, -12 }, // 0x42 'B'
- { 446, 12, 13, 13, 2, -12 }, // 0x43 'C'
- { 466, 13, 13, 13, 1, -12 }, // 0x44 'D'
- { 488, 12, 13, 12, 1, -12 }, // 0x45 'E'
- { 508, 12, 13, 11, 1, -12 }, // 0x46 'F'
- { 528, 13, 13, 14, 2, -12 }, // 0x47 'G'
- { 550, 13, 13, 13, 1, -12 }, // 0x48 'H'
- { 572, 4, 13, 5, 2, -12 }, // 0x49 'I'
- { 579, 10, 13, 9, 1, -12 }, // 0x4A 'J'
- { 596, 14, 13, 12, 1, -12 }, // 0x4B 'K'
- { 619, 9, 13, 10, 1, -12 }, // 0x4C 'L'
- { 634, 16, 13, 15, 1, -12 }, // 0x4D 'M'
- { 660, 13, 13, 13, 1, -12 }, // 0x4E 'N'
- { 682, 13, 13, 14, 2, -12 }, // 0x4F 'O'
- { 704, 12, 13, 12, 1, -12 }, // 0x50 'P'
- { 724, 13, 14, 14, 2, -12 }, // 0x51 'Q'
- { 747, 13, 13, 13, 1, -12 }, // 0x52 'R'
- { 769, 12, 13, 12, 1, -12 }, // 0x53 'S'
- { 789, 10, 13, 11, 3, -12 }, // 0x54 'T'
- { 806, 12, 13, 13, 2, -12 }, // 0x55 'U'
- { 826, 11, 13, 12, 3, -12 }, // 0x56 'V'
- { 844, 16, 13, 17, 3, -12 }, // 0x57 'W'
- { 870, 14, 13, 12, 0, -12 }, // 0x58 'X'
- { 893, 12, 13, 12, 3, -12 }, // 0x59 'Y'
- { 913, 12, 13, 11, 1, -12 }, // 0x5A 'Z'
- { 933, 7, 17, 5, 0, -12 }, // 0x5B '['
- { 948, 2, 13, 5, 3, -12 }, // 0x5C '\'
- { 952, 7, 17, 5, 0, -12 }, // 0x5D ']'
- { 967, 7, 7, 8, 2, -12 }, // 0x5E '^'
- { 974, 11, 1, 10, -1, 3 }, // 0x5F '_'
- { 976, 3, 3, 6, 3, -12 }, // 0x60 '`'
- { 978, 10, 10, 10, 1, -9 }, // 0x61 'a'
- { 991, 10, 13, 10, 1, -12 }, // 0x62 'b'
- { 1008, 9, 10, 9, 1, -9 }, // 0x63 'c'
- { 1020, 11, 13, 10, 1, -12 }, // 0x64 'd'
- { 1038, 10, 10, 10, 1, -9 }, // 0x65 'e'
- { 1051, 6, 13, 5, 1, -12 }, // 0x66 'f'
- { 1061, 10, 14, 10, 0, -9 }, // 0x67 'g'
- { 1079, 10, 13, 10, 1, -12 }, // 0x68 'h'
- { 1096, 4, 13, 4, 1, -12 }, // 0x69 'i'
- { 1103, 6, 17, 4, -1, -12 }, // 0x6A 'j'
- { 1116, 9, 13, 9, 1, -12 }, // 0x6B 'k'
- { 1131, 4, 13, 4, 1, -12 }, // 0x6C 'l'
- { 1138, 15, 10, 15, 1, -9 }, // 0x6D 'm'
- { 1157, 10, 11, 10, 1, -10 }, // 0x6E 'n'
- { 1171, 10, 10, 10, 1, -9 }, // 0x6F 'o'
- { 1184, 11, 14, 10, 0, -9 }, // 0x70 'p'
- { 1204, 10, 14, 10, 1, -9 }, // 0x71 'q'
- { 1222, 7, 10, 6, 1, -9 }, // 0x72 'r'
- { 1231, 8, 10, 9, 1, -9 }, // 0x73 's'
- { 1241, 4, 12, 5, 2, -11 }, // 0x74 't'
- { 1247, 9, 10, 10, 2, -9 }, // 0x75 'u'
- { 1259, 9, 10, 9, 2, -9 }, // 0x76 'v'
- { 1271, 13, 10, 13, 2, -9 }, // 0x77 'w'
- { 1288, 11, 10, 9, 0, -9 }, // 0x78 'x'
- { 1302, 11, 14, 9, 0, -9 }, // 0x79 'y'
- { 1322, 9, 10, 9, 1, -9 }, // 0x7A 'z'
- { 1334, 5, 17, 6, 2, -12 }, // 0x7B '{'
- { 1345, 4, 17, 5, 1, -12 }, // 0x7C '|'
- { 1354, 5, 17, 6, 0, -12 }, // 0x7D '}'
- { 1365, 9, 3, 11, 2, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSansOblique9pt7b PROGMEM = {
- (uint8_t *)FreeSansOblique9pt7bBitmaps,
- (GFXglyph *)FreeSansOblique9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 2041 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif12pt7b.h
deleted file mode 100644
index 48ad3da..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif12pt7b.h
+++ /dev/null
@@ -1,259 +0,0 @@
-const uint8_t FreeSerif12pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xFE, 0xA8, 0x3F, 0xCF, 0x3C, 0xF3, 0x8A, 0x20, 0x0C, 0x40, 0xC4,
- 0x08, 0x40, 0x8C, 0x08, 0xC7, 0xFF, 0x18, 0x81, 0x88, 0x10, 0x81, 0x08,
- 0xFF, 0xE1, 0x18, 0x31, 0x03, 0x10, 0x31, 0x02, 0x10, 0x04, 0x07, 0xC6,
- 0x5B, 0x12, 0xC4, 0xB1, 0x0F, 0x41, 0xF0, 0x1E, 0x01, 0xE0, 0x58, 0x13,
- 0x84, 0xE1, 0x3C, 0x4F, 0x96, 0x3F, 0x01, 0x00, 0x00, 0x04, 0x03, 0x83,
- 0x03, 0x9F, 0x81, 0xC2, 0x20, 0x60, 0x90, 0x38, 0x24, 0x0C, 0x12, 0x03,
- 0x0D, 0x00, 0xC6, 0x47, 0x9E, 0x23, 0x10, 0x09, 0x84, 0x04, 0xE1, 0x03,
- 0x30, 0x40, 0x8C, 0x20, 0x43, 0x08, 0x10, 0xC4, 0x08, 0x1E, 0x00, 0x03,
- 0xC0, 0x02, 0x30, 0x03, 0x08, 0x01, 0x84, 0x00, 0xC4, 0x00, 0x7C, 0xF8,
- 0x1C, 0x38, 0x1E, 0x08, 0x33, 0x0C, 0x31, 0xC4, 0x10, 0x74, 0x18, 0x3A,
- 0x0C, 0x0E, 0x07, 0x03, 0x83, 0xC3, 0xE2, 0x7E, 0x3E, 0xFF, 0xA0, 0x04,
- 0x21, 0x08, 0x61, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC1, 0x04, 0x18, 0x20,
- 0x40, 0x81, 0x81, 0x02, 0x04, 0x18, 0x20, 0x83, 0x0C, 0x30, 0xC3, 0x0C,
- 0x30, 0x86, 0x10, 0x84, 0x20, 0x30, 0xB3, 0xD7, 0x54, 0x38, 0x7C, 0xD3,
- 0x30, 0x30, 0x10, 0x04, 0x00, 0x80, 0x10, 0x02, 0x00, 0x41, 0xFF, 0xC1,
- 0x00, 0x20, 0x04, 0x00, 0x80, 0x10, 0x00, 0xDF, 0x95, 0x00, 0xFC, 0xFC,
- 0x06, 0x0C, 0x10, 0x60, 0xC1, 0x06, 0x0C, 0x10, 0x60, 0xC1, 0x06, 0x0C,
- 0x10, 0x60, 0xC0, 0x1E, 0x0C, 0xC6, 0x19, 0x86, 0xC0, 0xB0, 0x3C, 0x0F,
- 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xD8, 0x66, 0x18, 0xCC, 0x1E,
- 0x00, 0x11, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3,
- 0x0C, 0xFC, 0x1E, 0x18, 0xC4, 0x1A, 0x06, 0x01, 0x80, 0x60, 0x10, 0x0C,
- 0x02, 0x01, 0x00, 0xC0, 0x60, 0x30, 0x18, 0x1F, 0xF8, 0x1E, 0x18, 0xE8,
- 0x18, 0x06, 0x01, 0x00, 0x80, 0xF0, 0x7E, 0x03, 0xC0, 0x70, 0x0C, 0x03,
- 0x00, 0xC0, 0x6E, 0x11, 0xF8, 0x01, 0x00, 0xC0, 0x70, 0x2C, 0x0B, 0x04,
- 0xC2, 0x30, 0x8C, 0x43, 0x20, 0xC8, 0x33, 0xFF, 0x03, 0x00, 0xC0, 0x30,
- 0x0C, 0x00, 0x03, 0xF1, 0x00, 0x40, 0x18, 0x0F, 0x80, 0xF8, 0x0E, 0x01,
- 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x20, 0x1B, 0x8C, 0x7C, 0x00, 0x01,
- 0xC3, 0xC1, 0xC0, 0xC0, 0x70, 0x18, 0x0E, 0xF3, 0xCE, 0xC1, 0xF0, 0x3C,
- 0x0F, 0x03, 0xC0, 0xD8, 0x36, 0x08, 0xC6, 0x1E, 0x00, 0x3F, 0xD0, 0x38,
- 0x08, 0x06, 0x01, 0x80, 0x40, 0x10, 0x0C, 0x02, 0x00, 0x80, 0x20, 0x10,
- 0x04, 0x01, 0x00, 0x80, 0x20, 0x1F, 0x18, 0x6C, 0x0F, 0x03, 0xC0, 0xF8,
- 0x67, 0x30, 0xF0, 0x1E, 0x09, 0xE6, 0x3B, 0x07, 0xC0, 0xF0, 0x3C, 0x0D,
- 0x86, 0x1F, 0x00, 0x1E, 0x08, 0xC6, 0x1B, 0x02, 0xC0, 0xF0, 0x3C, 0x0F,
- 0x03, 0xE0, 0xDC, 0x73, 0xEC, 0x06, 0x01, 0x80, 0xC0, 0x70, 0x38, 0x38,
- 0x18, 0x00, 0xFC, 0x00, 0x3F, 0xCC, 0xC0, 0x00, 0x00, 0x06, 0x77, 0x12,
- 0x40, 0x00, 0x00, 0x07, 0x01, 0xE0, 0x78, 0x1E, 0x07, 0x00, 0xC0, 0x0F,
- 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x07, 0x00, 0x10, 0xFF, 0xF0, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x0E, 0x00, 0x3C, 0x00, 0xF0,
- 0x03, 0xC0, 0x0F, 0x00, 0x30, 0x0E, 0x07, 0x81, 0xE0, 0x78, 0x0E, 0x00,
- 0x00, 0x00, 0x7C, 0x86, 0x83, 0xC3, 0x03, 0x03, 0x06, 0x0C, 0x08, 0x08,
- 0x10, 0x10, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xF0, 0x06, 0x06, 0x06,
- 0x00, 0x86, 0x00, 0x26, 0x0E, 0xD3, 0x0C, 0xC7, 0x0C, 0x63, 0x84, 0x31,
- 0xC6, 0x18, 0xE3, 0x08, 0x71, 0x8C, 0x4C, 0xC6, 0x46, 0x3D, 0xC1, 0x80,
- 0x00, 0x30, 0x10, 0x07, 0xF0, 0x00, 0x80, 0x00, 0x60, 0x00, 0x70, 0x00,
- 0x38, 0x00, 0x2E, 0x00, 0x13, 0x00, 0x19, 0xC0, 0x08, 0x60, 0x04, 0x38,
- 0x04, 0x0C, 0x03, 0xFF, 0x03, 0x03, 0x81, 0x00, 0xE1, 0x80, 0x70, 0xC0,
- 0x3D, 0xF0, 0x3F, 0xFF, 0x83, 0x0C, 0x30, 0x63, 0x06, 0x30, 0x63, 0x06,
- 0x30, 0xC3, 0xF0, 0x30, 0xE3, 0x06, 0x30, 0x33, 0x03, 0x30, 0x33, 0x07,
- 0x30, 0xEF, 0xFC, 0x07, 0xE2, 0x38, 0x3C, 0xC0, 0x3B, 0x00, 0x36, 0x00,
- 0x38, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x03,
- 0x00, 0x06, 0x00, 0x06, 0x00, 0x47, 0x03, 0x03, 0xF8, 0xFF, 0xC0, 0x30,
- 0x78, 0x30, 0x1C, 0x30, 0x0E, 0x30, 0x06, 0x30, 0x03, 0x30, 0x03, 0x30,
- 0x03, 0x30, 0x03, 0x30, 0x03, 0x30, 0x03, 0x30, 0x06, 0x30, 0x06, 0x30,
- 0x0C, 0x30, 0x78, 0xFF, 0xC0, 0xFF, 0xFC, 0xC0, 0x33, 0x00, 0x4C, 0x00,
- 0x30, 0x00, 0xC0, 0x43, 0x03, 0x0F, 0xFC, 0x30, 0x30, 0xC0, 0x43, 0x00,
- 0x0C, 0x00, 0x30, 0x08, 0xC0, 0x23, 0x03, 0xBF, 0xFE, 0xFF, 0xFC, 0xC0,
- 0x33, 0x00, 0x4C, 0x00, 0x30, 0x00, 0xC0, 0x43, 0x03, 0x0F, 0xFC, 0x30,
- 0x30, 0xC0, 0x43, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x3F,
- 0x00, 0x07, 0xE4, 0x1C, 0x3C, 0x30, 0x0C, 0x60, 0x0C, 0x60, 0x04, 0xC0,
- 0x00, 0xC0, 0x00, 0xC0, 0x3F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x60,
- 0x0C, 0x60, 0x0C, 0x30, 0x0C, 0x1C, 0x1C, 0x07, 0xE0, 0xFC, 0x3F, 0x30,
- 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x3F,
- 0xFC, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,
- 0x0C, 0x30, 0x0C, 0xFC, 0x3F, 0xFC, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30,
- 0xC3, 0x0C, 0x30, 0xC3, 0x3F, 0x3F, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
- 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0xC8, 0xF0, 0xFC, 0xFE, 0x30,
- 0x38, 0x30, 0x20, 0x30, 0x40, 0x30, 0x80, 0x33, 0x00, 0x36, 0x00, 0x3E,
- 0x00, 0x37, 0x00, 0x33, 0x80, 0x31, 0xC0, 0x30, 0xE0, 0x30, 0x70, 0x30,
- 0x38, 0x30, 0x3C, 0xFC, 0x7F, 0xFC, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80,
- 0x03, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00,
- 0xC0, 0x01, 0x80, 0x03, 0x00, 0x26, 0x00, 0x8C, 0x07, 0x7F, 0xFE, 0xF8,
- 0x01, 0xE7, 0x00, 0x70, 0xE0, 0x0E, 0x1E, 0x03, 0xC2, 0xC0, 0x58, 0x5C,
- 0x1B, 0x09, 0x82, 0x61, 0x38, 0x4C, 0x27, 0x11, 0x84, 0x72, 0x30, 0x8E,
- 0xC6, 0x10, 0xD0, 0xC2, 0x1E, 0x18, 0x41, 0x83, 0x1C, 0x30, 0x67, 0xC4,
- 0x3F, 0xF0, 0x1F, 0x78, 0x0E, 0x3C, 0x04, 0x3E, 0x04, 0x2E, 0x04, 0x27,
- 0x04, 0x23, 0x84, 0x23, 0xC4, 0x21, 0xE4, 0x20, 0xE4, 0x20, 0x74, 0x20,
- 0x3C, 0x20, 0x1C, 0x20, 0x0C, 0x70, 0x0C, 0xF8, 0x04, 0x07, 0xC0, 0x30,
- 0x60, 0xC0, 0x63, 0x00, 0x66, 0x00, 0xD8, 0x00, 0xF0, 0x01, 0xE0, 0x03,
- 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1B, 0x00, 0x66, 0x00, 0xC6, 0x03, 0x06,
- 0x0C, 0x03, 0xE0, 0xFF, 0x83, 0x0E, 0x30, 0x73, 0x03, 0x30, 0x33, 0x03,
- 0x30, 0x63, 0x0E, 0x3F, 0x83, 0x00, 0x30, 0x03, 0x00, 0x30, 0x03, 0x00,
- 0x30, 0x0F, 0xC0, 0x0F, 0xE0, 0x18, 0x30, 0x30, 0x18, 0x60, 0x0C, 0x60,
- 0x0C, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0,
- 0x06, 0x60, 0x0C, 0x60, 0x0C, 0x30, 0x18, 0x18, 0x30, 0x07, 0xC0, 0x03,
- 0xC0, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1F, 0xFF, 0x80, 0x61, 0xC0, 0xC1,
- 0xC1, 0x81, 0x83, 0x03, 0x06, 0x06, 0x0C, 0x1C, 0x18, 0x70, 0x3F, 0x80,
- 0x67, 0x00, 0xC7, 0x01, 0x8F, 0x03, 0x0F, 0x06, 0x0E, 0x0C, 0x0E, 0x7E,
- 0x0F, 0x1F, 0x46, 0x19, 0x81, 0x30, 0x27, 0x02, 0xF0, 0x0F, 0x00, 0xF8,
- 0x07, 0xC0, 0x38, 0x03, 0xC0, 0x34, 0x06, 0x80, 0xDC, 0x32, 0x7C, 0xFF,
- 0xFF, 0x86, 0x0E, 0x0C, 0x1C, 0x18, 0x10, 0x30, 0x00, 0x60, 0x00, 0xC0,
- 0x01, 0x80, 0x03, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00,
- 0x60, 0x00, 0xC0, 0x07, 0xE0, 0xFC, 0x1F, 0x30, 0x0E, 0x30, 0x04, 0x30,
- 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30,
- 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x18, 0x08, 0x1C, 0x18, 0x07,
- 0xE0, 0xFE, 0x0F, 0x9C, 0x03, 0x0E, 0x01, 0x83, 0x00, 0x81, 0xC0, 0x40,
- 0x60, 0x40, 0x38, 0x20, 0x0C, 0x30, 0x07, 0x10, 0x01, 0x98, 0x00, 0xE8,
- 0x00, 0x34, 0x00, 0x1E, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x00, 0xFC,
- 0xFC, 0x3D, 0xE1, 0xC0, 0x63, 0x83, 0x01, 0x86, 0x0E, 0x04, 0x1C, 0x18,
- 0x10, 0x70, 0x70, 0x80, 0xC3, 0xC2, 0x03, 0x8B, 0x08, 0x06, 0x6E, 0x40,
- 0x1D, 0x19, 0x00, 0x74, 0x78, 0x00, 0xE1, 0xE0, 0x03, 0x83, 0x80, 0x0E,
- 0x0C, 0x00, 0x10, 0x10, 0x00, 0x40, 0x40, 0x7F, 0x1F, 0x9E, 0x03, 0x07,
- 0x03, 0x01, 0xC3, 0x00, 0x71, 0x00, 0x19, 0x00, 0x0F, 0x00, 0x03, 0x80,
- 0x01, 0xE0, 0x01, 0xB0, 0x01, 0x9C, 0x00, 0x87, 0x00, 0x81, 0xC0, 0x80,
- 0xE0, 0xC0, 0x79, 0xF8, 0x7F, 0xFE, 0x1F, 0x78, 0x0C, 0x38, 0x08, 0x1C,
- 0x18, 0x0E, 0x10, 0x06, 0x20, 0x07, 0x60, 0x03, 0xC0, 0x01, 0x80, 0x01,
- 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x07,
- 0xE0, 0x7F, 0xFB, 0x00, 0xC8, 0x07, 0x20, 0x38, 0x01, 0xC0, 0x07, 0x00,
- 0x38, 0x01, 0xC0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x05,
- 0xC0, 0x3E, 0x01, 0xBF, 0xFE, 0xFE, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31,
- 0x8C, 0x63, 0x18, 0xC6, 0x31, 0xF0, 0xC1, 0x81, 0x03, 0x06, 0x04, 0x0C,
- 0x18, 0x10, 0x30, 0x60, 0x40, 0xC1, 0x81, 0x03, 0x06, 0xF8, 0xC6, 0x31,
- 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC7, 0xF0, 0x0C, 0x07,
- 0x01, 0x60, 0xD8, 0x23, 0x18, 0xC4, 0x1B, 0x06, 0x80, 0xC0, 0xFF, 0xF0,
- 0xC7, 0x0C, 0x30, 0x3E, 0x31, 0x8C, 0x30, 0x0C, 0x03, 0x07, 0xC6, 0x33,
- 0x0C, 0xC3, 0x31, 0xC7, 0xB8, 0x20, 0x38, 0x06, 0x01, 0x80, 0x60, 0x18,
- 0x06, 0xF1, 0xC6, 0x61, 0xD8, 0x36, 0x0D, 0x83, 0x60, 0xD8, 0x26, 0x19,
- 0x84, 0x3E, 0x00, 0x1E, 0x23, 0x63, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xE1,
- 0x72, 0x3C, 0x00, 0x80, 0xE0, 0x18, 0x06, 0x01, 0x80, 0x61, 0xD8, 0x8E,
- 0x61, 0xB0, 0x6C, 0x1B, 0x06, 0xC1, 0xB0, 0x6E, 0x19, 0xCE, 0x3D, 0xC0,
- 0x1E, 0x08, 0xE4, 0x1B, 0xFE, 0xC0, 0x30, 0x0C, 0x03, 0x81, 0x60, 0x9C,
- 0x41, 0xE0, 0x0F, 0x08, 0xC4, 0x06, 0x03, 0x01, 0x81, 0xF0, 0x60, 0x30,
- 0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x60, 0xFC, 0x00, 0x1F, 0x03,
- 0x1F, 0x60, 0xC6, 0x0C, 0x60, 0xC3, 0x18, 0x1F, 0x02, 0x00, 0x40, 0x07,
- 0xFC, 0x40, 0x24, 0x02, 0xC0, 0x2C, 0x04, 0xE0, 0x83, 0xF0, 0x30, 0x1E,
- 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0D, 0xE1, 0xCE, 0x30, 0xC6, 0x18,
- 0xC3, 0x18, 0x63, 0x0C, 0x61, 0x8C, 0x31, 0x86, 0x79, 0xE0, 0x31, 0x80,
- 0x00, 0x09, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xDF, 0x0C, 0x30, 0x00, 0x00,
- 0x31, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xF2, 0xF0,
- 0x20, 0x1C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0xFB, 0x08, 0x62,
- 0x0C, 0x81, 0xE0, 0x3E, 0x06, 0xE0, 0xCE, 0x18, 0xC3, 0x0E, 0xF3, 0xE0,
- 0x13, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0xF8, 0xF7,
- 0x8F, 0x0E, 0x3C, 0xE3, 0x0C, 0x18, 0xC3, 0x06, 0x30, 0xC1, 0x8C, 0x30,
- 0x63, 0x0C, 0x18, 0xC3, 0x06, 0x30, 0xC1, 0x8C, 0x30, 0x67, 0x9E, 0x3C,
- 0xF7, 0x87, 0x18, 0xC3, 0x18, 0x63, 0x0C, 0x61, 0x8C, 0x31, 0x86, 0x30,
- 0xC6, 0x19, 0xE7, 0x80, 0x1E, 0x18, 0xE4, 0x1B, 0x03, 0xC0, 0xF0, 0x3C,
- 0x0F, 0x03, 0x60, 0x9C, 0x41, 0xE0, 0x77, 0x87, 0x18, 0xC3, 0x98, 0x33,
- 0x06, 0x60, 0xCC, 0x19, 0x83, 0x30, 0xC7, 0x10, 0xDC, 0x18, 0x03, 0x00,
- 0x60, 0x0C, 0x07, 0xE0, 0x1E, 0x8C, 0xE6, 0x1B, 0x06, 0xC1, 0xB0, 0x6C,
- 0x1B, 0x06, 0xE1, 0x98, 0xE3, 0xD8, 0x06, 0x01, 0x80, 0x60, 0x18, 0x1F,
- 0x37, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x7C, 0x7B,
- 0x0E, 0x1C, 0x1E, 0x0F, 0x07, 0xC3, 0x87, 0x8A, 0xE0, 0x21, 0x8F, 0x98,
- 0x61, 0x86, 0x18, 0x61, 0x86, 0x19, 0x38, 0xE3, 0x98, 0x66, 0x19, 0x86,
- 0x61, 0x98, 0x66, 0x19, 0x86, 0x61, 0x9C, 0xE3, 0xDC, 0xF8, 0xEE, 0x08,
- 0xC1, 0x18, 0x41, 0x88, 0x32, 0x03, 0x40, 0x68, 0x06, 0x00, 0xC0, 0x10,
- 0x00, 0xF3, 0xE7, 0x61, 0x83, 0x70, 0xC2, 0x30, 0xC2, 0x30, 0xC4, 0x19,
- 0x64, 0x19, 0x68, 0x0E, 0x38, 0x0E, 0x38, 0x0C, 0x30, 0x04, 0x10, 0xFB,
- 0xC6, 0x30, 0x64, 0x0F, 0x00, 0xC0, 0x0C, 0x03, 0xC0, 0x98, 0x21, 0x8C,
- 0x3B, 0xCF, 0x80, 0xF8, 0xEE, 0x08, 0xC1, 0x18, 0x41, 0x88, 0x31, 0x03,
- 0x40, 0x68, 0x06, 0x00, 0xC0, 0x08, 0x02, 0x00, 0x40, 0x10, 0x1E, 0x03,
- 0x80, 0x7F, 0x90, 0xE0, 0x30, 0x18, 0x0E, 0x03, 0x01, 0xC0, 0xE0, 0x30,
- 0x5C, 0x3F, 0xF8, 0x19, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0xB0, 0x63, 0x18,
- 0xC6, 0x31, 0x8C, 0x61, 0x80, 0xFF, 0xFF, 0x80, 0xC3, 0x18, 0xC6, 0x31,
- 0x8C, 0x63, 0x06, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xCC, 0x00, 0x38, 0x06,
- 0x62, 0x41, 0xC0 };
-
-const GFXglyph FreeSerif12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 2, 16, 8, 3, -15 }, // 0x21 '!'
- { 4, 6, 6, 10, 1, -15 }, // 0x22 '"'
- { 9, 12, 16, 12, 0, -15 }, // 0x23 '#'
- { 33, 10, 18, 12, 1, -16 }, // 0x24 '$'
- { 56, 18, 17, 20, 1, -16 }, // 0x25 '%'
- { 95, 17, 16, 19, 1, -15 }, // 0x26 '&'
- { 129, 2, 6, 5, 1, -15 }, // 0x27 '''
- { 131, 6, 20, 8, 1, -15 }, // 0x28 '('
- { 146, 6, 20, 8, 1, -15 }, // 0x29 ')'
- { 161, 8, 10, 12, 3, -14 }, // 0x2A '*'
- { 171, 11, 11, 14, 1, -10 }, // 0x2B '+'
- { 187, 3, 6, 6, 2, -2 }, // 0x2C ','
- { 190, 6, 1, 8, 1, -5 }, // 0x2D '-'
- { 191, 2, 3, 6, 2, -2 }, // 0x2E '.'
- { 192, 7, 17, 7, 0, -16 }, // 0x2F '/'
- { 207, 10, 17, 12, 1, -16 }, // 0x30 '0'
- { 229, 6, 17, 12, 3, -16 }, // 0x31 '1'
- { 242, 10, 15, 12, 1, -14 }, // 0x32 '2'
- { 261, 10, 16, 12, 1, -15 }, // 0x33 '3'
- { 281, 10, 16, 12, 1, -15 }, // 0x34 '4'
- { 301, 10, 17, 12, 1, -16 }, // 0x35 '5'
- { 323, 10, 17, 12, 1, -16 }, // 0x36 '6'
- { 345, 10, 16, 12, 0, -15 }, // 0x37 '7'
- { 365, 10, 17, 12, 1, -16 }, // 0x38 '8'
- { 387, 10, 18, 12, 1, -16 }, // 0x39 '9'
- { 410, 2, 12, 6, 2, -11 }, // 0x3A ':'
- { 413, 4, 15, 6, 2, -11 }, // 0x3B ';'
- { 421, 12, 13, 14, 1, -12 }, // 0x3C '<'
- { 441, 12, 6, 14, 1, -8 }, // 0x3D '='
- { 450, 12, 13, 14, 1, -11 }, // 0x3E '>'
- { 470, 8, 17, 11, 2, -16 }, // 0x3F '?'
- { 487, 17, 16, 21, 2, -15 }, // 0x40 '@'
- { 521, 17, 16, 17, 0, -15 }, // 0x41 'A'
- { 555, 12, 16, 15, 1, -15 }, // 0x42 'B'
- { 579, 15, 16, 16, 1, -15 }, // 0x43 'C'
- { 609, 16, 16, 17, 0, -15 }, // 0x44 'D'
- { 641, 14, 16, 15, 0, -15 }, // 0x45 'E'
- { 669, 14, 16, 14, 0, -15 }, // 0x46 'F'
- { 697, 16, 16, 17, 1, -15 }, // 0x47 'G'
- { 729, 16, 16, 17, 0, -15 }, // 0x48 'H'
- { 761, 6, 16, 8, 1, -15 }, // 0x49 'I'
- { 773, 8, 16, 9, 0, -15 }, // 0x4A 'J'
- { 789, 16, 16, 17, 1, -15 }, // 0x4B 'K'
- { 821, 15, 16, 15, 0, -15 }, // 0x4C 'L'
- { 851, 19, 16, 21, 1, -15 }, // 0x4D 'M'
- { 889, 16, 16, 17, 1, -15 }, // 0x4E 'N'
- { 921, 15, 16, 17, 1, -15 }, // 0x4F 'O'
- { 951, 12, 16, 14, 0, -15 }, // 0x50 'P'
- { 975, 16, 20, 17, 1, -15 }, // 0x51 'Q'
- { 1015, 15, 16, 16, 0, -15 }, // 0x52 'R'
- { 1045, 11, 16, 13, 0, -15 }, // 0x53 'S'
- { 1067, 15, 16, 15, 0, -15 }, // 0x54 'T'
- { 1097, 16, 16, 17, 1, -15 }, // 0x55 'U'
- { 1129, 17, 16, 17, 0, -15 }, // 0x56 'V'
- { 1163, 22, 16, 23, 0, -15 }, // 0x57 'W'
- { 1207, 17, 16, 17, 0, -15 }, // 0x58 'X'
- { 1241, 16, 16, 17, 0, -15 }, // 0x59 'Y'
- { 1273, 14, 16, 15, 1, -15 }, // 0x5A 'Z'
- { 1301, 5, 20, 8, 2, -15 }, // 0x5B '['
- { 1314, 7, 17, 7, 0, -16 }, // 0x5C '\'
- { 1329, 5, 20, 8, 1, -15 }, // 0x5D ']'
- { 1342, 10, 9, 11, 1, -15 }, // 0x5E '^'
- { 1354, 12, 1, 12, 0, 3 }, // 0x5F '_'
- { 1356, 5, 4, 6, 0, -15 }, // 0x60 '`'
- { 1359, 10, 11, 10, 1, -10 }, // 0x61 'a'
- { 1373, 10, 17, 12, 1, -16 }, // 0x62 'b'
- { 1395, 8, 11, 11, 1, -10 }, // 0x63 'c'
- { 1406, 10, 17, 12, 1, -16 }, // 0x64 'd'
- { 1428, 10, 11, 11, 1, -10 }, // 0x65 'e'
- { 1442, 9, 17, 9, 0, -16 }, // 0x66 'f'
- { 1462, 12, 16, 11, 0, -10 }, // 0x67 'g'
- { 1486, 11, 17, 12, 0, -16 }, // 0x68 'h'
- { 1510, 5, 16, 7, 0, -15 }, // 0x69 'i'
- { 1520, 6, 21, 8, 0, -15 }, // 0x6A 'j'
- { 1536, 11, 17, 12, 1, -16 }, // 0x6B 'k'
- { 1560, 5, 17, 6, 0, -16 }, // 0x6C 'l'
- { 1571, 18, 11, 19, 0, -10 }, // 0x6D 'm'
- { 1596, 11, 11, 12, 0, -10 }, // 0x6E 'n'
- { 1612, 10, 11, 12, 1, -10 }, // 0x6F 'o'
- { 1626, 11, 16, 12, 0, -10 }, // 0x70 'p'
- { 1648, 10, 16, 12, 1, -10 }, // 0x71 'q'
- { 1668, 8, 11, 8, 0, -10 }, // 0x72 'r'
- { 1679, 7, 11, 9, 1, -10 }, // 0x73 's'
- { 1689, 6, 13, 7, 1, -12 }, // 0x74 't'
- { 1699, 10, 11, 12, 1, -10 }, // 0x75 'u'
- { 1713, 11, 11, 11, 0, -10 }, // 0x76 'v'
- { 1729, 16, 11, 16, 0, -10 }, // 0x77 'w'
- { 1751, 11, 11, 12, 0, -10 }, // 0x78 'x'
- { 1767, 11, 16, 11, 0, -10 }, // 0x79 'y'
- { 1789, 10, 11, 10, 0, -10 }, // 0x7A 'z'
- { 1803, 5, 21, 12, 2, -16 }, // 0x7B '{'
- { 1817, 1, 17, 5, 2, -16 }, // 0x7C '|'
- { 1820, 5, 21, 12, 5, -15 }, // 0x7D '}'
- { 1834, 12, 3, 12, 0, -6 } }; // 0x7E '~'
-
-const GFXfont FreeSerif12pt7b PROGMEM = {
- (uint8_t *)FreeSerif12pt7bBitmaps,
- (GFXglyph *)FreeSerif12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2511 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif18pt7b.h
deleted file mode 100644
index 7d19dd1..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif18pt7b.h
+++ /dev/null
@@ -1,429 +0,0 @@
-const uint8_t FreeSerif18pt7bBitmaps[] PROGMEM = {
- 0x6F, 0xFF, 0xFF, 0xFE, 0x66, 0x66, 0x66, 0x64, 0x40, 0x00, 0x6F, 0xF6,
- 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0x46, 0x42, 0x42, 0x42, 0x03, 0x06, 0x01,
- 0x83, 0x00, 0xC1, 0x80, 0x61, 0xC0, 0x30, 0xC0, 0x38, 0x60, 0x18, 0x30,
- 0xFF, 0xFF, 0x7F, 0xFF, 0x83, 0x06, 0x01, 0x86, 0x00, 0xC3, 0x00, 0xC1,
- 0x87, 0xFF, 0xFF, 0xFF, 0xFE, 0x18, 0x30, 0x0C, 0x18, 0x06, 0x18, 0x06,
- 0x0C, 0x03, 0x06, 0x01, 0x83, 0x00, 0xC1, 0x80, 0x60, 0xC0, 0x02, 0x00,
- 0x10, 0x03, 0xE0, 0x64, 0xE6, 0x23, 0x61, 0x1B, 0x08, 0x58, 0x42, 0xE2,
- 0x03, 0x90, 0x1F, 0x80, 0x7E, 0x00, 0xFC, 0x01, 0xF0, 0x0F, 0xC0, 0x4E,
- 0x02, 0x38, 0x10, 0xE0, 0x87, 0x04, 0x3C, 0x21, 0xE1, 0x1B, 0xC9, 0xCF,
- 0xFC, 0x1F, 0x80, 0x10, 0x00, 0x80, 0x07, 0x80, 0x20, 0x0F, 0xF0, 0x70,
- 0x0F, 0x07, 0xD0, 0x0F, 0x02, 0x18, 0x07, 0x01, 0x18, 0x07, 0x00, 0x8C,
- 0x03, 0x80, 0x4C, 0x01, 0x80, 0x44, 0x00, 0xC0, 0x26, 0x00, 0x60, 0x22,
- 0x0F, 0x30, 0x33, 0x1F, 0xCC, 0x73, 0x1E, 0x37, 0xF1, 0x8E, 0x19, 0xE1,
- 0x8E, 0x04, 0x00, 0x86, 0x02, 0x00, 0xC7, 0x01, 0x00, 0xC3, 0x80, 0x80,
- 0x61, 0x80, 0x80, 0x60, 0xC0, 0x40, 0x30, 0x60, 0x40, 0x30, 0x38, 0xE0,
- 0x30, 0x0F, 0xE0, 0x18, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x00, 0x7E, 0x00,
- 0x00, 0x61, 0x80, 0x00, 0x60, 0x60, 0x00, 0x30, 0x30, 0x00, 0x18, 0x18,
- 0x00, 0x0C, 0x0C, 0x00, 0x06, 0x0C, 0x00, 0x03, 0x8E, 0x00, 0x01, 0xCE,
- 0x00, 0x00, 0x7C, 0x3F, 0xC0, 0x38, 0x07, 0x80, 0x3E, 0x03, 0x80, 0x77,
- 0x01, 0x80, 0x73, 0xC0, 0x80, 0xF0, 0xF0, 0xC0, 0x70, 0x7C, 0xC0, 0x78,
- 0x1E, 0x40, 0x3C, 0x07, 0xC0, 0x1E, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x0F,
- 0xC0, 0xFF, 0x0D, 0xF0, 0xC7, 0xFC, 0x7F, 0xC1, 0xFC, 0x1F, 0x80, 0x3C,
- 0x00, 0xFF, 0xFE, 0x92, 0x40, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0,
- 0xC0, 0x60, 0x70, 0x30, 0x18, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0,
- 0x70, 0x38, 0x0C, 0x06, 0x03, 0x80, 0xC0, 0x60, 0x18, 0x0C, 0x03, 0x00,
- 0xC0, 0x30, 0x0C, 0x80, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x60, 0x18, 0x0C,
- 0x07, 0x01, 0x80, 0xC0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0,
- 0xE0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x0C, 0x04, 0x04, 0x04, 0x04, 0x04,
- 0x00, 0x0C, 0x00, 0xC0, 0x0C, 0x0C, 0x46, 0xE4, 0xF7, 0x5E, 0x1F, 0x00,
- 0xC0, 0x17, 0x8E, 0x4E, 0xE4, 0xFC, 0xC6, 0x0C, 0x00, 0xC0, 0x01, 0x80,
- 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,
- 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,
- 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x6F, 0xFF,
- 0x11, 0x24, 0x80, 0xFF, 0xFF, 0x6F, 0xF6, 0x00, 0xC0, 0x60, 0x18, 0x06,
- 0x03, 0x80, 0xC0, 0x30, 0x1C, 0x06, 0x01, 0x80, 0xE0, 0x30, 0x0C, 0x07,
- 0x01, 0x80, 0x60, 0x38, 0x0C, 0x03, 0x01, 0xC0, 0x60, 0x18, 0x0E, 0x03,
- 0x00, 0x03, 0xE0, 0x0E, 0x70, 0x1C, 0x38, 0x38, 0x1C, 0x38, 0x1C, 0x78,
- 0x1E, 0x70, 0x0E, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0,
- 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0x70, 0x0E, 0x70,
- 0x0E, 0x78, 0x1E, 0x38, 0x1C, 0x38, 0x1C, 0x1C, 0x38, 0x0C, 0x30, 0x03,
- 0xC0, 0x06, 0x03, 0x83, 0xE3, 0x38, 0x0E, 0x03, 0x80, 0xE0, 0x38, 0x0E,
- 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x03, 0x80,
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- 0x00, 0x00, 0xF0, 0x00, 0x1F, 0x80, 0x03, 0xFC, 0x00, 0xFF, 0x01, 0xFD,
- 0xF8, 0x01, 0xC3, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0,
- 0x00, 0x83, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00,
- 0x83, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00, 0x83,
- 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00, 0x81, 0xE0,
- 0x04, 0x07, 0x80, 0x30, 0x0F, 0x81, 0x80, 0x1F, 0xFC, 0x00, 0x1F, 0xC0,
- 0x00, 0xFF, 0xC0, 0x7F, 0x3E, 0x00, 0x1E, 0x1E, 0x00, 0x0C, 0x0E, 0x00,
- 0x18, 0x0F, 0x00, 0x18, 0x07, 0x00, 0x10, 0x07, 0x80, 0x30, 0x07, 0x80,
- 0x30, 0x03, 0xC0, 0x60, 0x03, 0xC0, 0x60, 0x01, 0xE0, 0x40, 0x01, 0xE0,
- 0xC0, 0x00, 0xF0, 0xC0, 0x00, 0xF1, 0x80, 0x00, 0x71, 0x80, 0x00, 0x7B,
- 0x00, 0x00, 0x3B, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E,
- 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x08, 0x00, 0xFF, 0x9F,
- 0xF0, 0x3F, 0x9F, 0x03, 0xE0, 0x07, 0x07, 0x80, 0xF0, 0x03, 0x03, 0xC0,
- 0x78, 0x01, 0x80, 0xE0, 0x1E, 0x00, 0x80, 0x78, 0x0F, 0x00, 0xC0, 0x1C,
- 0x03, 0x80, 0x60, 0x0F, 0x01, 0xE0, 0x20, 0x07, 0x81, 0xF0, 0x30, 0x01,
- 0xC0, 0xBC, 0x18, 0x00, 0xF0, 0xDE, 0x08, 0x00, 0x78, 0x67, 0x0C, 0x00,
- 0x1E, 0x23, 0xC4, 0x00, 0x0F, 0x31, 0xE6, 0x00, 0x03, 0x90, 0x7B, 0x00,
- 0x01, 0xF8, 0x3D, 0x00, 0x00, 0xFC, 0x0F, 0x80, 0x00, 0x3C, 0x07, 0xC0,
- 0x00, 0x1E, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0xE0, 0x00, 0x03, 0x00, 0x70,
- 0x00, 0x01, 0x80, 0x10, 0x00, 0x00, 0x80, 0x08, 0x00, 0x7F, 0xE0, 0xFF,
- 0x0F, 0xC0, 0x1E, 0x03, 0xE0, 0x0E, 0x00, 0xF0, 0x06, 0x00, 0x3C, 0x06,
- 0x00, 0x0F, 0x06, 0x00, 0x07, 0x86, 0x00, 0x01, 0xE6, 0x00, 0x00, 0x7B,
- 0x00, 0x00, 0x3F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x03,
- 0xF0, 0x00, 0x03, 0x78, 0x00, 0x01, 0x9E, 0x00, 0x01, 0x87, 0x80, 0x01,
- 0x83, 0xE0, 0x01, 0x80, 0xF0, 0x01, 0x80, 0x3C, 0x01, 0x80, 0x1F, 0x01,
- 0xC0, 0x07, 0xC1, 0xE0, 0x03, 0xF3, 0xFE, 0x0F, 0xFE, 0xFF, 0xC0, 0xFF,
- 0x7E, 0x00, 0x1C, 0x1E, 0x00, 0x18, 0x1F, 0x00, 0x30, 0x0F, 0x00, 0x60,
- 0x07, 0x80, 0x60, 0x03, 0xC0, 0xC0, 0x03, 0xE1, 0x80, 0x01, 0xE1, 0x80,
- 0x00, 0xF3, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3C, 0x00,
- 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00,
- 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00,
- 0x00, 0x7E, 0x00, 0x01, 0xFF, 0x80, 0x3F, 0xFF, 0xF1, 0xFF, 0xFF, 0x9C,
- 0x00, 0x78, 0xC0, 0x07, 0x84, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x3C,
- 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x1E, 0x00, 0x01,
- 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00,
- 0x07, 0x00, 0x00, 0x78, 0x00, 0x47, 0x80, 0x06, 0x78, 0x00, 0x33, 0x80,
- 0x07, 0x3F, 0xFF, 0xFB, 0xFF, 0xFF, 0xC0, 0xFF, 0x83, 0x06, 0x0C, 0x18,
- 0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06,
- 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x07, 0xF0, 0xC0, 0x18, 0x06, 0x01,
- 0x80, 0x70, 0x0C, 0x03, 0x00, 0xE0, 0x18, 0x06, 0x01, 0xC0, 0x30, 0x0C,
- 0x03, 0x80, 0x60, 0x18, 0x07, 0x00, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x60,
- 0x1C, 0x03, 0xFE, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18,
- 0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06,
- 0x0C, 0x1F, 0xF0, 0x03, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x76, 0x00, 0xCE,
- 0x03, 0x8C, 0x06, 0x1C, 0x1C, 0x18, 0x30, 0x30, 0xE0, 0x31, 0x80, 0x67,
- 0x00, 0x6C, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xC0, 0xE0, 0x70,
- 0x18, 0x0C, 0x03, 0x1F, 0x03, 0x8C, 0x38, 0x31, 0xC1, 0x8E, 0x0C, 0x00,
- 0x60, 0x0F, 0x01, 0x98, 0x30, 0xC3, 0x86, 0x38, 0x31, 0xC1, 0x8E, 0x0C,
- 0x78, 0xE5, 0xFB, 0xCF, 0x0C, 0x00, 0x00, 0x38, 0x00, 0xF8, 0x00, 0x38,
- 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x39,
- 0xF0, 0x3B, 0xFC, 0x3C, 0x3E, 0x38, 0x0E, 0x38, 0x0F, 0x38, 0x07, 0x38,
- 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x06, 0x38, 0x0E, 0x38,
- 0x0C, 0x3C, 0x1C, 0x1F, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x7F, 0xE3, 0x87,
- 0xD8, 0x0F, 0x60, 0x1B, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00,
- 0x0E, 0x00, 0x3C, 0x01, 0x78, 0x19, 0xFF, 0xC3, 0xFE, 0x03, 0xE0, 0x00,
- 0x00, 0x00, 0x1C, 0x00, 0x7C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00,
- 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x07, 0x9C, 0x1F, 0xDC, 0x38, 0x7C, 0x70,
- 0x3C, 0x70, 0x1C, 0x60, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0,
- 0x1C, 0xE0, 0x1C, 0xF0, 0x1C, 0x70, 0x1C, 0x7C, 0x3E, 0x3F, 0xDF, 0x0F,
- 0x90, 0x0F, 0x81, 0xFF, 0x08, 0x3C, 0x80, 0xE7, 0xFF, 0x7F, 0xFF, 0x00,
- 0x18, 0x00, 0xC0, 0x07, 0x00, 0x38, 0x03, 0xE0, 0x37, 0x83, 0x3F, 0xF0,
- 0xFF, 0x03, 0xF0, 0x01, 0xF0, 0x3F, 0xC3, 0x8E, 0x18, 0x00, 0xC0, 0x0E,
- 0x00, 0x70, 0x03, 0x80, 0x1C, 0x03, 0xFE, 0x1F, 0xF0, 0x38, 0x01, 0xC0,
- 0x0E, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01,
- 0xC0, 0x0E, 0x00, 0x70, 0x07, 0xC0, 0xFF, 0x80, 0x0F, 0xC0, 0x1F, 0xFF,
- 0x38, 0xFF, 0x70, 0x70, 0x70, 0x70, 0x70, 0x30, 0x70, 0x30, 0x70, 0x30,
- 0x38, 0x20, 0x1C, 0x60, 0x0F, 0x80, 0x10, 0x00, 0x20, 0x00, 0x60, 0x00,
- 0x7F, 0xE0, 0x3F, 0xFC, 0x1F, 0xFE, 0x20, 0x06, 0x40, 0x02, 0xC0, 0x02,
- 0xC0, 0x04, 0xF0, 0x18, 0x7F, 0xF0, 0x1F, 0x80, 0x00, 0x00, 0x38, 0x00,
- 0xF8, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00,
- 0x38, 0x00, 0x38, 0xF0, 0x3B, 0xF8, 0x3E, 0x3C, 0x3C, 0x1C, 0x38, 0x1C,
- 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,
- 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x7C, 0x3E, 0xFE, 0x7F, 0x18, 0x3C,
- 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x04, 0x3C, 0x7C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x3C, 0xFF, 0x03, 0x03,
- 0xC1, 0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0xC3, 0xE0, 0x70,
- 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E,
- 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x37, 0x3B, 0xF8, 0xF8, 0x00, 0x00,
- 0x1C, 0x00, 0x3E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0,
- 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x3F, 0x8E, 0x0F, 0x07, 0x06, 0x03,
- 0x86, 0x01, 0xC4, 0x00, 0xE4, 0x00, 0x7E, 0x00, 0x3F, 0x80, 0x1D, 0xC0,
- 0x0E, 0x70, 0x07, 0x1C, 0x03, 0x8F, 0x01, 0xC3, 0xC0, 0xE0, 0xF0, 0xF8,
- 0x3C, 0xFE, 0x7F, 0x80, 0x00, 0x1C, 0x7C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x3C, 0xFF, 0x38, 0xF0, 0x7C, 0x3E, 0xFE, 0x7F, 0x83,
- 0xE3, 0xF0, 0xE0, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E, 0x07, 0x01,
- 0xC3, 0x81, 0xC0, 0x70, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E, 0x07,
- 0x01, 0xC3, 0x81, 0xC0, 0x70, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E,
- 0x07, 0x01, 0xC3, 0x81, 0xE0, 0x73, 0xF9, 0xFC, 0x7F, 0x38, 0xF0, 0xFB,
- 0xF8, 0x3E, 0x3C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38,
- 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38,
- 0x1C, 0x78, 0x3C, 0xFE, 0x7F, 0x07, 0xE0, 0x1F, 0xF8, 0x3C, 0x7C, 0x78,
- 0x3E, 0x70, 0x1E, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0,
- 0x0F, 0xF8, 0x0F, 0x78, 0x0E, 0x7C, 0x1C, 0x3E, 0x3C, 0x0F, 0xF0, 0x07,
- 0xC0, 0x18, 0xF0, 0xFB, 0xFC, 0x3E, 0x1E, 0x38, 0x0E, 0x38, 0x0F, 0x38,
- 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x06, 0x38,
- 0x0E, 0x38, 0x0C, 0x3E, 0x1C, 0x3B, 0xF8, 0x39, 0xE0, 0x38, 0x00, 0x38,
- 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x7C, 0x00, 0xFF,
- 0x00, 0x07, 0xC4, 0x1F, 0xEC, 0x3C, 0x3C, 0x70, 0x1C, 0x70, 0x1C, 0x60,
- 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xF0,
- 0x1C, 0x70, 0x1C, 0x78, 0x3C, 0x3F, 0xDC, 0x1F, 0x1C, 0x00, 0x1C, 0x00,
- 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3E, 0x00,
- 0xFF, 0x19, 0xFF, 0x7C, 0xF3, 0x9C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0,
- 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x1F, 0x07, 0xF0, 0x3E,
- 0x58, 0x7C, 0x0F, 0x03, 0xC0, 0x7C, 0x07, 0x80, 0xF8, 0x1F, 0x81, 0xF8,
- 0x1E, 0x03, 0xC0, 0xF0, 0x3E, 0x1A, 0x7C, 0x10, 0x30, 0x70, 0xFE, 0xFE,
- 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x79,
- 0x7E, 0x3C, 0xF8, 0x7C, 0x38, 0x3C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,
- 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,
- 0x38, 0x1C, 0x38, 0x1C, 0x3C, 0x7C, 0x1F, 0xDF, 0x0F, 0x18, 0xFE, 0x1F,
- 0x7C, 0x06, 0x38, 0x04, 0x1C, 0x04, 0x1C, 0x0C, 0x0E, 0x08, 0x0E, 0x18,
- 0x07, 0x10, 0x07, 0x10, 0x07, 0x20, 0x03, 0xA0, 0x03, 0xE0, 0x01, 0xC0,
- 0x01, 0xC0, 0x00, 0x80, 0x00, 0x80, 0xFC, 0x7F, 0x1F, 0x78, 0x3C, 0x06,
- 0x38, 0x1C, 0x04, 0x38, 0x1C, 0x04, 0x1C, 0x1C, 0x0C, 0x1C, 0x0E, 0x08,
- 0x1C, 0x1E, 0x18, 0x0E, 0x17, 0x10, 0x0E, 0x37, 0x10, 0x07, 0x23, 0x30,
- 0x07, 0x63, 0xA0, 0x07, 0x43, 0xE0, 0x03, 0xC1, 0xC0, 0x03, 0x81, 0xC0,
- 0x01, 0x80, 0x80, 0x01, 0x00, 0x80, 0x7F, 0x7E, 0x1E, 0x0C, 0x07, 0x8C,
- 0x01, 0xC4, 0x00, 0x76, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x03,
- 0xE0, 0x01, 0x70, 0x01, 0x1C, 0x01, 0x8F, 0x01, 0x83, 0x80, 0x80, 0xE0,
- 0xC0, 0x79, 0xF0, 0xFF, 0xFE, 0x0F, 0x7C, 0x06, 0x38, 0x06, 0x1C, 0x04,
- 0x1C, 0x0C, 0x0E, 0x0C, 0x0E, 0x08, 0x0F, 0x18, 0x07, 0x10, 0x07, 0x90,
- 0x03, 0xB0, 0x03, 0xA0, 0x01, 0xE0, 0x01, 0xE0, 0x00, 0xC0, 0x00, 0xC0,
- 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x03, 0x00, 0x7E, 0x00,
- 0x7C, 0x00, 0x78, 0x00, 0x7F, 0xF9, 0xFF, 0xE6, 0x07, 0x10, 0x38, 0x00,
- 0xE0, 0x07, 0x00, 0x38, 0x01, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xE0, 0x07,
- 0x01, 0x38, 0x0D, 0xC0, 0x3F, 0xFF, 0xBF, 0xFE, 0x07, 0x0E, 0x1C, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x60, 0x60,
- 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1C,
- 0x0E, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x70, 0x38, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x08, 0x06, 0x06,
- 0x08, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38,
- 0x70, 0xE0, 0x3E, 0x00, 0x7F, 0x87, 0xE3, 0xFE, 0x00, 0x7C };
-
-const GFXglyph FreeSerif18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 9, 0, 1 }, // 0x20 ' '
- { 0, 4, 24, 12, 5, -23 }, // 0x21 '!'
- { 12, 8, 9, 14, 3, -23 }, // 0x22 '"'
- { 21, 17, 23, 17, 0, -22 }, // 0x23 '#'
- { 70, 13, 27, 17, 2, -24 }, // 0x24 '$'
- { 114, 25, 23, 29, 2, -22 }, // 0x25 '%'
- { 186, 25, 25, 27, 1, -24 }, // 0x26 '&'
- { 265, 3, 9, 7, 2, -23 }, // 0x27 '''
- { 269, 9, 30, 12, 2, -23 }, // 0x28 '('
- { 303, 9, 30, 12, 1, -22 }, // 0x29 ')'
- { 337, 12, 14, 18, 3, -23 }, // 0x2A '*'
- { 358, 16, 18, 20, 2, -17 }, // 0x2B '+'
- { 394, 4, 9, 9, 2, -3 }, // 0x2C ','
- { 399, 8, 2, 12, 1, -8 }, // 0x2D '-'
- { 401, 4, 4, 9, 2, -3 }, // 0x2E '.'
- { 403, 10, 24, 10, 0, -23 }, // 0x2F '/'
- { 433, 16, 24, 18, 1, -23 }, // 0x30 '0'
- { 481, 10, 24, 18, 3, -23 }, // 0x31 '1'
- { 511, 16, 24, 17, 1, -23 }, // 0x32 '2'
- { 559, 13, 24, 17, 2, -23 }, // 0x33 '3'
- { 598, 16, 23, 18, 0, -22 }, // 0x34 '4'
- { 644, 13, 24, 17, 2, -23 }, // 0x35 '5'
- { 683, 16, 24, 18, 1, -23 }, // 0x36 '6'
- { 731, 14, 23, 18, 1, -22 }, // 0x37 '7'
- { 772, 12, 25, 18, 2, -24 }, // 0x38 '8'
- { 810, 16, 26, 17, 1, -24 }, // 0x39 '9'
- { 862, 4, 17, 9, 2, -16 }, // 0x3A ':'
- { 871, 5, 22, 9, 2, -16 }, // 0x3B ';'
- { 885, 18, 18, 20, 1, -17 }, // 0x3C '<'
- { 926, 18, 9, 20, 1, -12 }, // 0x3D '='
- { 947, 18, 18, 20, 1, -17 }, // 0x3E '>'
- { 988, 13, 25, 16, 2, -24 }, // 0x3F '?'
- { 1029, 24, 25, 30, 3, -24 }, // 0x40 '@'
- { 1104, 24, 23, 25, 1, -22 }, // 0x41 'A'
- { 1173, 20, 23, 22, 1, -22 }, // 0x42 'B'
- { 1231, 22, 24, 23, 1, -23 }, // 0x43 'C'
- { 1297, 23, 23, 25, 1, -22 }, // 0x44 'D'
- { 1364, 20, 23, 21, 2, -22 }, // 0x45 'E'
- { 1422, 17, 23, 20, 2, -22 }, // 0x46 'F'
- { 1471, 23, 24, 25, 1, -23 }, // 0x47 'G'
- { 1540, 22, 23, 25, 2, -22 }, // 0x48 'H'
- { 1604, 9, 23, 11, 2, -22 }, // 0x49 'I'
- { 1630, 12, 23, 13, 0, -22 }, // 0x4A 'J'
- { 1665, 23, 23, 25, 2, -22 }, // 0x4B 'K'
- { 1732, 19, 23, 21, 2, -22 }, // 0x4C 'L'
- { 1787, 29, 23, 31, 1, -22 }, // 0x4D 'M'
- { 1871, 23, 23, 25, 1, -22 }, // 0x4E 'N'
- { 1938, 23, 24, 25, 1, -23 }, // 0x4F 'O'
- { 2007, 18, 23, 20, 1, -22 }, // 0x50 'P'
- { 2059, 23, 30, 25, 1, -23 }, // 0x51 'Q'
- { 2146, 21, 23, 23, 2, -22 }, // 0x52 'R'
- { 2207, 16, 24, 19, 1, -23 }, // 0x53 'S'
- { 2255, 20, 23, 21, 1, -22 }, // 0x54 'T'
- { 2313, 22, 23, 25, 2, -22 }, // 0x55 'U'
- { 2377, 24, 23, 25, 0, -22 }, // 0x56 'V'
- { 2446, 33, 23, 33, 0, -22 }, // 0x57 'W'
- { 2541, 25, 23, 25, 0, -22 }, // 0x58 'X'
- { 2613, 24, 23, 25, 1, -22 }, // 0x59 'Y'
- { 2682, 21, 23, 21, 0, -22 }, // 0x5A 'Z'
- { 2743, 7, 28, 12, 3, -22 }, // 0x5B '['
- { 2768, 10, 24, 10, 0, -23 }, // 0x5C '\'
- { 2798, 7, 28, 12, 2, -22 }, // 0x5D ']'
- { 2823, 15, 13, 16, 1, -22 }, // 0x5E '^'
- { 2848, 18, 2, 17, 0, 3 }, // 0x5F '_'
- { 2853, 8, 6, 9, 1, -23 }, // 0x60 '`'
- { 2859, 13, 16, 15, 2, -15 }, // 0x61 'a'
- { 2885, 16, 25, 17, 1, -24 }, // 0x62 'b'
- { 2935, 14, 16, 16, 1, -15 }, // 0x63 'c'
- { 2963, 16, 25, 17, 1, -24 }, // 0x64 'd'
- { 3013, 13, 16, 16, 1, -15 }, // 0x65 'e'
- { 3039, 13, 25, 13, 0, -24 }, // 0x66 'f'
- { 3080, 16, 24, 16, 1, -15 }, // 0x67 'g'
- { 3128, 16, 25, 17, 1, -24 }, // 0x68 'h'
- { 3178, 8, 24, 10, 0, -23 }, // 0x69 'i'
- { 3202, 9, 32, 12, 0, -23 }, // 0x6A 'j'
- { 3238, 17, 25, 18, 1, -24 }, // 0x6B 'k'
- { 3292, 8, 25, 9, 0, -24 }, // 0x6C 'l'
- { 3317, 26, 16, 27, 1, -15 }, // 0x6D 'm'
- { 3369, 16, 16, 17, 1, -15 }, // 0x6E 'n'
- { 3401, 16, 16, 17, 1, -15 }, // 0x6F 'o'
- { 3433, 16, 24, 17, 1, -15 }, // 0x70 'p'
- { 3481, 16, 24, 17, 1, -15 }, // 0x71 'q'
- { 3529, 11, 16, 12, 1, -15 }, // 0x72 'r'
- { 3551, 10, 16, 13, 1, -15 }, // 0x73 's'
- { 3571, 8, 19, 10, 2, -18 }, // 0x74 't'
- { 3590, 16, 16, 17, 1, -15 }, // 0x75 'u'
- { 3622, 16, 16, 16, 0, -15 }, // 0x76 'v'
- { 3654, 24, 16, 24, 0, -15 }, // 0x77 'w'
- { 3702, 17, 16, 17, 0, -15 }, // 0x78 'x'
- { 3736, 16, 24, 16, 0, -15 }, // 0x79 'y'
- { 3784, 14, 16, 15, 0, -15 }, // 0x7A 'z'
- { 3812, 8, 30, 17, 3, -23 }, // 0x7B '{'
- { 3842, 2, 24, 7, 2, -23 }, // 0x7C '|'
- { 3848, 8, 30, 17, 6, -22 }, // 0x7D '}'
- { 3878, 16, 4, 17, 1, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSerif18pt7b PROGMEM = {
- (uint8_t *)FreeSerif18pt7bBitmaps,
- (GFXglyph *)FreeSerif18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 4558 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif24pt7b.h
deleted file mode 100644
index 99ff3f4..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif24pt7b.h
+++ /dev/null
@@ -1,690 +0,0 @@
-const uint8_t FreeSerif24pt7bBitmaps[] PROGMEM = {
- 0x77, 0xBF, 0xFF, 0xFF, 0xFF, 0xFB, 0x9C, 0xE7, 0x39, 0xCE, 0x61, 0x08,
- 0x42, 0x10, 0x84, 0x00, 0x00, 0xEF, 0xFF, 0xEE, 0x60, 0x6F, 0x0F, 0xF0,
- 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60,
- 0x66, 0x06, 0x00, 0xE0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x07,
- 0x03, 0x80, 0x0E, 0x06, 0x00, 0x18, 0x0C, 0x00, 0x30, 0x38, 0x00, 0xE0,
- 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC1, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF,
- 0xF0, 0x18, 0x0C, 0x00, 0x70, 0x38, 0x00, 0xE0, 0x70, 0x01, 0xC0, 0xE0,
- 0x03, 0x81, 0xC0, 0x07, 0x03, 0x80, 0x0C, 0x06, 0x07, 0xFF, 0xFF, 0xEF,
- 0xFF, 0xFF, 0xC0, 0xE0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x06,
- 0x03, 0x80, 0x0C, 0x06, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x38, 0x00, 0xE0,
- 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x08,
- 0x00, 0x01, 0x00, 0x01, 0xFC, 0x01, 0xE4, 0xF8, 0x70, 0x87, 0x9C, 0x10,
- 0x77, 0x02, 0x06, 0xE0, 0x40, 0xDC, 0x08, 0x0B, 0x81, 0x00, 0x78, 0x20,
- 0x07, 0x84, 0x00, 0xFC, 0x80, 0x0F, 0xF0, 0x00, 0xFE, 0x00, 0x07, 0xF0,
- 0x00, 0x7F, 0x80, 0x03, 0xFC, 0x00, 0x3F, 0xC0, 0x05, 0xFC, 0x00, 0x8F,
- 0x80, 0x10, 0xF8, 0x02, 0x0F, 0x00, 0x40, 0xF0, 0x08, 0x1E, 0x01, 0x03,
- 0xE0, 0x20, 0x7C, 0x04, 0x0F, 0xC0, 0x83, 0xBC, 0x10, 0xE3, 0xE2, 0x78,
- 0x3F, 0xFE, 0x00, 0xFE, 0x00, 0x01, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00,
- 0x01, 0xF0, 0x00, 0xC0, 0x03, 0xFC, 0x01, 0xE0, 0x03, 0xC7, 0x81, 0xE0,
- 0x03, 0xC0, 0x7F, 0x60, 0x03, 0xC0, 0x20, 0x70, 0x01, 0xE0, 0x10, 0x30,
- 0x01, 0xE0, 0x08, 0x38, 0x00, 0xE0, 0x04, 0x18, 0x00, 0xF0, 0x02, 0x1C,
- 0x00, 0x78, 0x02, 0x0C, 0x00, 0x38, 0x01, 0x0E, 0x00, 0x1C, 0x01, 0x86,
- 0x00, 0x0E, 0x00, 0x86, 0x00, 0x07, 0x00, 0x87, 0x03, 0xE1, 0x80, 0xC3,
- 0x07, 0xFC, 0xE1, 0xC3, 0x87, 0xC6, 0x3F, 0xC1, 0x87, 0x81, 0x8F, 0x81,
- 0xC7, 0x80, 0x40, 0x00, 0xC3, 0xC0, 0x20, 0x00, 0xE3, 0xC0, 0x10, 0x00,
- 0x61, 0xC0, 0x08, 0x00, 0x61, 0xE0, 0x04, 0x00, 0x70, 0xF0, 0x06, 0x00,
- 0x30, 0x70, 0x02, 0x00, 0x38, 0x38, 0x03, 0x00, 0x18, 0x1C, 0x01, 0x00,
- 0x1C, 0x0E, 0x01, 0x80, 0x0C, 0x07, 0x01, 0x80, 0x0E, 0x01, 0xC3, 0x80,
- 0x06, 0x00, 0x7F, 0x80, 0x06, 0x00, 0x1F, 0x00, 0x07, 0x00, 0x00, 0x00,
- 0x00, 0x1F, 0x00, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0x70, 0xE0, 0x00,
- 0x00, 0xE0, 0x60, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x30, 0x00,
- 0x01, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x70, 0x00,
- 0x01, 0xE0, 0xE0, 0x00, 0x01, 0xE1, 0xC0, 0x00, 0x00, 0xF3, 0x80, 0x00,
- 0x00, 0xFF, 0x0F, 0xFC, 0x00, 0xFC, 0x03, 0xF0, 0x00, 0xF8, 0x01, 0xE0,
- 0x01, 0xFC, 0x01, 0xC0, 0x07, 0x7C, 0x01, 0xC0, 0x0F, 0x3E, 0x01, 0x80,
- 0x1E, 0x3E, 0x03, 0x00, 0x3C, 0x1F, 0x03, 0x00, 0x7C, 0x1F, 0x06, 0x00,
- 0x78, 0x0F, 0x86, 0x00, 0x78, 0x07, 0xCC, 0x00, 0xF8, 0x07, 0xE8, 0x00,
- 0xF8, 0x03, 0xF8, 0x00, 0xF8, 0x01, 0xF0, 0x00, 0xF8, 0x01, 0xF8, 0x00,
- 0xFC, 0x00, 0xFC, 0x01, 0xFC, 0x01, 0xFE, 0x01, 0x7E, 0x03, 0xBF, 0x86,
- 0x7F, 0x0F, 0x1F, 0xFE, 0x3F, 0xFC, 0x0F, 0xF8, 0x0F, 0xE0, 0x03, 0xF0,
- 0x6F, 0xFF, 0xFF, 0x66, 0x66, 0x66, 0x00, 0x10, 0x02, 0x00, 0xC0, 0x18,
- 0x03, 0x00, 0x60, 0x0E, 0x00, 0xC0, 0x1C, 0x03, 0x80, 0x38, 0x03, 0x80,
- 0x78, 0x07, 0x00, 0x70, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00,
- 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x07, 0x00, 0x70, 0x07, 0x80,
- 0x38, 0x03, 0x80, 0x38, 0x01, 0xC0, 0x0C, 0x00, 0xC0, 0x06, 0x00, 0x30,
- 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0xC0, 0x06, 0x00, 0x30, 0x01, 0x80,
- 0x0C, 0x00, 0x60, 0x07, 0x00, 0x30, 0x03, 0x80, 0x1C, 0x01, 0xC0, 0x1C,
- 0x01, 0xE0, 0x0E, 0x00, 0xE0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0E, 0x00, 0xE0, 0x1E,
- 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x38, 0x03, 0x00, 0x70, 0x0E, 0x00, 0xC0,
- 0x18, 0x03, 0x00, 0x40, 0x08, 0x00, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80,
- 0x43, 0x86, 0xE1, 0x0F, 0xF1, 0x1F, 0xF9, 0x3E, 0x3D, 0x78, 0x07, 0xC0,
- 0x01, 0x00, 0x07, 0xC0, 0x19, 0x30, 0xF9, 0x1E, 0xF1, 0x0F, 0xE1, 0x07,
- 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x00, 0x38, 0x00, 0x00,
- 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07,
- 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70,
- 0x00, 0x00, 0xE0, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x07, 0x00,
- 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00,
- 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00,
- 0x0E, 0x00, 0x00, 0x73, 0xEF, 0xFF, 0x7C, 0x10, 0x42, 0x08, 0xC6, 0x00,
- 0xFF, 0xFF, 0xFC, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x1C, 0x00, 0xE0, 0x03,
- 0x80, 0x0E, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x38, 0x00, 0xE0, 0x03,
- 0x80, 0x1C, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xE0, 0x07,
- 0x00, 0x1C, 0x00, 0xF0, 0x03, 0x80, 0x0E, 0x00, 0x78, 0x01, 0xC0, 0x07,
- 0x00, 0x3C, 0x00, 0xE0, 0x03, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0F,
- 0x00, 0x38, 0x00, 0x00, 0xFC, 0x00, 0x0E, 0x1C, 0x00, 0x70, 0x38, 0x03,
- 0x80, 0x70, 0x1E, 0x01, 0xE0, 0xF0, 0x03, 0x83, 0xC0, 0x0F, 0x0F, 0x00,
- 0x3C, 0x7C, 0x00, 0xF9, 0xE0, 0x01, 0xE7, 0x80, 0x07, 0xBE, 0x00, 0x1F,
- 0xF8, 0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x1F, 0xF8,
- 0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x1F, 0xF8, 0x00,
- 0x7F, 0xE0, 0x01, 0xF7, 0x80, 0x07, 0x9E, 0x00, 0x1E, 0x7C, 0x00, 0xF8,
- 0xF0, 0x03, 0xC3, 0xC0, 0x0F, 0x07, 0x00, 0x38, 0x1E, 0x01, 0xE0, 0x38,
- 0x07, 0x00, 0x70, 0x38, 0x00, 0xE1, 0xC0, 0x00, 0xFC, 0x00, 0x00, 0x80,
- 0x1C, 0x03, 0xE0, 0x7F, 0x0C, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07,
- 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0,
- 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00,
- 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3F,
- 0x0F, 0xFF, 0x01, 0xF8, 0x00, 0x3F, 0xF0, 0x07, 0xFF, 0xE0, 0x70, 0x3F,
- 0x83, 0x00, 0x7C, 0x30, 0x01, 0xF1, 0x00, 0x0F, 0x98, 0x00, 0x3C, 0x80,
- 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0x80, 0x00, 0x1C,
- 0x00, 0x01, 0xC0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00,
- 0x70, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00,
- 0x03, 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x43, 0x00,
- 0x02, 0x30, 0x00, 0x23, 0xFF, 0xFF, 0x3F, 0xFF, 0xF3, 0xFF, 0xFF, 0x80,
- 0x03, 0xF8, 0x03, 0xFF, 0x01, 0x83, 0xE0, 0x80, 0x3C, 0x40, 0x0F, 0x10,
- 0x01, 0xC8, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x06, 0x00, 0x03, 0x00, 0x00,
- 0x80, 0x00, 0xC0, 0x00, 0x78, 0x00, 0x7F, 0x80, 0x7F, 0xF0, 0x01, 0xFE,
- 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x01, 0xC0,
- 0x00, 0x70, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00,
- 0x30, 0x00, 0x0C, 0x70, 0x06, 0x3F, 0x07, 0x0F, 0xFF, 0x00, 0xFF, 0x00,
- 0x00, 0x03, 0x00, 0x00, 0x38, 0x00, 0x01, 0xC0, 0x00, 0x1E, 0x00, 0x01,
- 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xDC, 0x00, 0x0C, 0xE0, 0x00, 0x47, 0x00,
- 0x06, 0x38, 0x00, 0x61, 0xC0, 0x06, 0x0E, 0x00, 0x30, 0x70, 0x03, 0x03,
- 0x80, 0x30, 0x1C, 0x01, 0x80, 0xE0, 0x18, 0x07, 0x01, 0x80, 0x38, 0x08,
- 0x01, 0xC0, 0xC0, 0x0E, 0x0C, 0x00, 0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xE0, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0x38, 0x00, 0x01, 0xC0, 0x00,
- 0x0E, 0x00, 0x00, 0x70, 0x00, 0x03, 0x80, 0x00, 0x1C, 0x00, 0x00, 0x00,
- 0x40, 0x7F, 0xF8, 0x1F, 0xFE, 0x03, 0xFF, 0xC0, 0xC0, 0x00, 0x18, 0x00,
- 0x06, 0x00, 0x00, 0xC0, 0x00, 0x1C, 0x00, 0x07, 0xF8, 0x00, 0xFF, 0xC0,
- 0x3F, 0xFE, 0x00, 0xFF, 0xE0, 0x01, 0xFE, 0x00, 0x0F, 0xE0, 0x00, 0x7C,
- 0x00, 0x07, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x1C,
- 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x30,
- 0x00, 0x0E, 0x00, 0x01, 0x80, 0x00, 0x71, 0xE0, 0x1C, 0x3F, 0x07, 0x07,
- 0xFF, 0x80, 0x3F, 0x80, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x3E, 0x00, 0x0F,
- 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01,
- 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00,
- 0x07, 0xC7, 0xE0, 0x3E, 0xFF, 0xC3, 0xF8, 0x3F, 0x1F, 0x80, 0x7C, 0xF8,
- 0x03, 0xF7, 0xC0, 0x0F, 0xBE, 0x00, 0x7F, 0xF0, 0x01, 0xFF, 0x80, 0x0F,
- 0xFC, 0x00, 0x7F, 0xE0, 0x03, 0xFF, 0x00, 0x1F, 0x78, 0x00, 0xFB, 0xE0,
- 0x07, 0x9F, 0x00, 0x3C, 0x78, 0x03, 0xE3, 0xE0, 0x1E, 0x0F, 0x81, 0xE0,
- 0x3E, 0x1E, 0x00, 0xFF, 0xE0, 0x00, 0xFC, 0x00, 0x3F, 0xFF, 0xF3, 0xFF,
- 0xFF, 0x3F, 0xFF, 0xE7, 0x00, 0x0E, 0x40, 0x00, 0xEC, 0x00, 0x1C, 0x80,
- 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x03, 0x80,
- 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x00, 0xE0,
- 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x38,
- 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x07,
- 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x00, 0x01,
- 0xC0, 0x00, 0x03, 0xF0, 0x03, 0xFF, 0x03, 0xC1, 0xE0, 0xC0, 0x1C, 0x70,
- 0x07, 0x18, 0x00, 0xEE, 0x00, 0x3B, 0x80, 0x0E, 0xF0, 0x03, 0xBC, 0x00,
- 0xE7, 0x80, 0x71, 0xF0, 0x38, 0x3E, 0x1C, 0x07, 0xEE, 0x00, 0xFE, 0x00,
- 0x1F, 0xC0, 0x03, 0xF8, 0x03, 0xFF, 0x01, 0xC7, 0xE0, 0xE0, 0xFC, 0x70,
- 0x0F, 0x98, 0x01, 0xEE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x01, 0xF8, 0x00,
- 0x7E, 0x00, 0x1F, 0xC0, 0x07, 0x70, 0x03, 0x9E, 0x00, 0xE3, 0xE0, 0xF0,
- 0x7F, 0xF0, 0x07, 0xF0, 0x00, 0x01, 0xF8, 0x00, 0x3F, 0xF0, 0x03, 0xC3,
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- 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80,
- 0x70, 0x0E, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x0E, 0x07, 0x01, 0xC0, 0x70,
- 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E,
- 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x3C, 0x07, 0x03, 0xC0, 0xF0, 0x00,
- 0x1F, 0x80, 0x00, 0xFF, 0x80, 0xC7, 0x0F, 0x87, 0xB8, 0x0F, 0xFC, 0x00,
- 0x07, 0xC0 };
-
-const GFXglyph FreeSerif24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 12, 0, 1 }, // 0x20 ' '
- { 0, 5, 32, 16, 6, -31 }, // 0x21 '!'
- { 20, 12, 12, 19, 4, -31 }, // 0x22 '"'
- { 38, 23, 31, 23, 0, -30 }, // 0x23 '#'
- { 128, 19, 37, 24, 2, -33 }, // 0x24 '$'
- { 216, 33, 32, 39, 3, -30 }, // 0x25 '%'
- { 348, 32, 33, 37, 2, -31 }, // 0x26 '&'
- { 480, 4, 12, 9, 3, -31 }, // 0x27 '''
- { 486, 12, 40, 16, 2, -31 }, // 0x28 '('
- { 546, 12, 40, 16, 2, -30 }, // 0x29 ')'
- { 606, 16, 19, 24, 4, -30 }, // 0x2A '*'
- { 644, 23, 23, 27, 2, -22 }, // 0x2B '+'
- { 711, 6, 11, 12, 2, -4 }, // 0x2C ','
- { 720, 11, 2, 16, 2, -10 }, // 0x2D '-'
- { 723, 5, 5, 12, 3, -3 }, // 0x2E '.'
- { 727, 14, 32, 14, 0, -30 }, // 0x2F '/'
- { 783, 22, 33, 23, 1, -31 }, // 0x30 '0'
- { 874, 13, 32, 24, 5, -31 }, // 0x31 '1'
- { 926, 21, 31, 23, 1, -30 }, // 0x32 '2'
- { 1008, 18, 32, 23, 2, -30 }, // 0x33 '3'
- { 1080, 21, 31, 24, 1, -30 }, // 0x34 '4'
- { 1162, 19, 33, 24, 2, -31 }, // 0x35 '5'
- { 1241, 21, 33, 23, 2, -31 }, // 0x36 '6'
- { 1328, 20, 31, 24, 1, -30 }, // 0x37 '7'
- { 1406, 18, 33, 23, 3, -31 }, // 0x38 '8'
- { 1481, 21, 33, 24, 1, -31 }, // 0x39 '9'
- { 1568, 5, 22, 12, 4, -20 }, // 0x3A ':'
- { 1582, 6, 27, 12, 3, -20 }, // 0x3B ';'
- { 1603, 24, 25, 27, 1, -24 }, // 0x3C '<'
- { 1678, 24, 11, 27, 1, -16 }, // 0x3D '='
- { 1711, 24, 25, 27, 2, -23 }, // 0x3E '>'
- { 1786, 17, 32, 21, 3, -31 }, // 0x3F '?'
- { 1854, 32, 33, 41, 4, -31 }, // 0x40 '@'
- { 1986, 32, 32, 34, 1, -31 }, // 0x41 'A'
- { 2114, 27, 31, 30, 0, -30 }, // 0x42 'B'
- { 2219, 28, 33, 31, 2, -31 }, // 0x43 'C'
- { 2335, 31, 31, 34, 1, -30 }, // 0x44 'D'
- { 2456, 27, 31, 29, 2, -30 }, // 0x45 'E'
- { 2561, 24, 31, 27, 2, -30 }, // 0x46 'F'
- { 2654, 31, 33, 35, 2, -31 }, // 0x47 'G'
- { 2782, 30, 31, 34, 2, -30 }, // 0x48 'H'
- { 2899, 13, 31, 15, 1, -30 }, // 0x49 'I'
- { 2950, 17, 32, 18, 0, -30 }, // 0x4A 'J'
- { 3018, 32, 31, 33, 1, -30 }, // 0x4B 'K'
- { 3142, 26, 31, 29, 2, -30 }, // 0x4C 'L'
- { 3243, 39, 31, 41, 1, -30 }, // 0x4D 'M'
- { 3395, 32, 32, 34, 1, -30 }, // 0x4E 'N'
- { 3523, 30, 33, 34, 2, -31 }, // 0x4F 'O'
- { 3647, 23, 31, 27, 2, -30 }, // 0x50 'P'
- { 3737, 31, 40, 34, 2, -31 }, // 0x51 'Q'
- { 3892, 28, 31, 31, 2, -30 }, // 0x52 'R'
- { 4001, 21, 33, 25, 2, -31 }, // 0x53 'S'
- { 4088, 27, 31, 28, 1, -30 }, // 0x54 'T'
- { 4193, 32, 32, 34, 1, -30 }, // 0x55 'U'
- { 4321, 32, 32, 33, 0, -30 }, // 0x56 'V'
- { 4449, 44, 32, 45, 0, -30 }, // 0x57 'W'
- { 4625, 33, 31, 34, 0, -30 }, // 0x58 'X'
- { 4753, 32, 31, 33, 0, -30 }, // 0x59 'Y'
- { 4877, 27, 31, 29, 1, -30 }, // 0x5A 'Z'
- { 4982, 9, 38, 16, 4, -30 }, // 0x5B '['
- { 5025, 14, 32, 14, 0, -30 }, // 0x5C '\'
- { 5081, 9, 38, 16, 3, -30 }, // 0x5D ']'
- { 5124, 20, 17, 22, 1, -30 }, // 0x5E '^'
- { 5167, 24, 2, 23, 0, 5 }, // 0x5F '_'
- { 5173, 10, 8, 12, 1, -31 }, // 0x60 '`'
- { 5183, 18, 21, 20, 1, -20 }, // 0x61 'a'
- { 5231, 21, 32, 24, 1, -31 }, // 0x62 'b'
- { 5315, 19, 21, 21, 1, -20 }, // 0x63 'c'
- { 5365, 22, 32, 23, 1, -31 }, // 0x64 'd'
- { 5453, 18, 21, 21, 1, -20 }, // 0x65 'e'
- { 5501, 17, 33, 18, 0, -32 }, // 0x66 'f'
- { 5572, 21, 31, 22, 1, -20 }, // 0x67 'g'
- { 5654, 22, 32, 23, 0, -31 }, // 0x68 'h'
- { 5742, 11, 32, 13, 0, -31 }, // 0x69 'i'
- { 5786, 12, 42, 16, 0, -31 }, // 0x6A 'j'
- { 5849, 23, 32, 24, 1, -31 }, // 0x6B 'k'
- { 5941, 11, 32, 12, 0, -31 }, // 0x6C 'l'
- { 5985, 35, 21, 37, 1, -20 }, // 0x6D 'm'
- { 6077, 22, 21, 23, 0, -20 }, // 0x6E 'n'
- { 6135, 22, 21, 23, 1, -20 }, // 0x6F 'o'
- { 6193, 21, 31, 24, 1, -20 }, // 0x70 'p'
- { 6275, 21, 31, 23, 1, -20 }, // 0x71 'q'
- { 6357, 15, 21, 16, 1, -20 }, // 0x72 'r'
- { 6397, 13, 21, 17, 2, -20 }, // 0x73 's'
- { 6432, 12, 26, 13, 1, -25 }, // 0x74 't'
- { 6471, 22, 21, 23, 1, -20 }, // 0x75 'u'
- { 6529, 22, 22, 22, 0, -20 }, // 0x76 'v'
- { 6590, 32, 22, 32, 0, -20 }, // 0x77 'w'
- { 6678, 22, 21, 23, 0, -20 }, // 0x78 'x'
- { 6736, 22, 31, 22, 0, -20 }, // 0x79 'y'
- { 6822, 18, 21, 20, 1, -20 }, // 0x7A 'z'
- { 6870, 11, 41, 23, 5, -31 }, // 0x7B '{'
- { 6927, 3, 32, 9, 3, -30 }, // 0x7C '|'
- { 6939, 11, 41, 23, 7, -31 }, // 0x7D '}'
- { 6996, 22, 5, 23, 1, -13 } }; // 0x7E '~'
-
-const GFXfont FreeSerif24pt7b PROGMEM = {
- (uint8_t *)FreeSerif24pt7bBitmaps,
- (GFXglyph *)FreeSerif24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 7682 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif9pt7b.h
deleted file mode 100644
index cdb20c7..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerif9pt7b.h
+++ /dev/null
@@ -1,195 +0,0 @@
-const uint8_t FreeSerif9pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xEA, 0x03, 0xDE, 0xF7, 0x20, 0x11, 0x09, 0x04, 0x82, 0x4F, 0xF9,
- 0x10, 0x89, 0xFF, 0x24, 0x12, 0x09, 0x0C, 0x80, 0x10, 0x7C, 0xD6, 0xD2,
- 0xD0, 0xF0, 0x38, 0x1E, 0x17, 0x93, 0x93, 0xD6, 0x7C, 0x10, 0x38, 0x43,
- 0x3C, 0x39, 0x21, 0x8A, 0x0C, 0x50, 0x65, 0x39, 0xCB, 0x20, 0xB9, 0x05,
- 0x88, 0x4C, 0x44, 0x64, 0x21, 0xC0, 0x0E, 0x00, 0xC8, 0x06, 0x40, 0x32,
- 0x01, 0xA0, 0x07, 0x78, 0x31, 0x87, 0x88, 0x46, 0x86, 0x34, 0x30, 0xC1,
- 0xC7, 0x17, 0xCF, 0x00, 0xFE, 0x08, 0x88, 0x84, 0x63, 0x18, 0xC6, 0x10,
- 0x82, 0x08, 0x20, 0x82, 0x08, 0x21, 0x0C, 0x63, 0x18, 0xC4, 0x22, 0x22,
- 0x00, 0x63, 0x9A, 0xDC, 0x72, 0xB6, 0x08, 0x08, 0x04, 0x02, 0x01, 0x0F,
- 0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0xD8, 0xF0, 0xF0, 0x08, 0x84, 0x22,
- 0x10, 0x8C, 0x42, 0x31, 0x00, 0x1C, 0x31, 0x98, 0xD8, 0x3C, 0x1E, 0x0F,
- 0x07, 0x83, 0xC1, 0xE0, 0xD8, 0xC4, 0x61, 0xC0, 0x13, 0x8C, 0x63, 0x18,
- 0xC6, 0x31, 0x8C, 0x67, 0x80, 0x3C, 0x4E, 0x86, 0x06, 0x06, 0x04, 0x0C,
- 0x08, 0x10, 0x20, 0x41, 0xFE, 0x3C, 0xC6, 0x06, 0x04, 0x1C, 0x3E, 0x07,
- 0x03, 0x03, 0x03, 0x06, 0xF8, 0x04, 0x18, 0x71, 0x64, 0xC9, 0xA3, 0x46,
- 0xFE, 0x18, 0x30, 0x60, 0x0F, 0x10, 0x20, 0x3C, 0x0E, 0x07, 0x03, 0x03,
- 0x03, 0x02, 0x04, 0xF8, 0x07, 0x1C, 0x30, 0x60, 0x60, 0xDC, 0xE6, 0xC3,
- 0xC3, 0xC3, 0x43, 0x66, 0x3C, 0x7F, 0x82, 0x02, 0x02, 0x04, 0x04, 0x04,
- 0x08, 0x08, 0x08, 0x10, 0x10, 0x3C, 0x8F, 0x1E, 0x3E, 0x4F, 0x06, 0x36,
- 0xC7, 0x8F, 0x1B, 0x33, 0xC0, 0x3C, 0x66, 0xC2, 0xC3, 0xC3, 0xC3, 0xC3,
- 0x63, 0x3F, 0x06, 0x06, 0x0C, 0x38, 0x60, 0xF0, 0x0F, 0xD8, 0x00, 0x03,
- 0x28, 0x01, 0x87, 0x0E, 0x1C, 0x0C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0x80,
- 0xFF, 0x80, 0x00, 0x00, 0x0F, 0xF8, 0x80, 0x1C, 0x01, 0xC0, 0x1C, 0x01,
- 0xC0, 0xE0, 0xE0, 0xE0, 0xC0, 0x00, 0x79, 0x1A, 0x18, 0x30, 0x60, 0x83,
- 0x04, 0x10, 0x20, 0x40, 0x03, 0x00, 0x0F, 0x83, 0x8C, 0x60, 0x26, 0x02,
- 0xC7, 0x9C, 0xC9, 0xD8, 0x9D, 0x99, 0xD9, 0x26, 0xEC, 0x60, 0x03, 0x04,
- 0x0F, 0x80, 0x02, 0x00, 0x10, 0x01, 0xC0, 0x16, 0x00, 0x98, 0x04, 0xC0,
- 0x43, 0x03, 0xF8, 0x20, 0x61, 0x03, 0x18, 0x1D, 0xE1, 0xF0, 0xFF, 0x86,
- 0x1C, 0xC1, 0x98, 0x33, 0x0C, 0x7E, 0x0C, 0x31, 0x83, 0x30, 0x66, 0x0C,
- 0xC3, 0x7F, 0xC0, 0x1F, 0x26, 0x1D, 0x81, 0xE0, 0x1C, 0x01, 0x80, 0x30,
- 0x06, 0x00, 0xC0, 0x0C, 0x00, 0xC1, 0x8F, 0xC0, 0xFF, 0x03, 0x1C, 0x30,
- 0x63, 0x07, 0x30, 0x33, 0x03, 0x30, 0x33, 0x03, 0x30, 0x33, 0x06, 0x30,
- 0xCF, 0xF0, 0xFF, 0x98, 0x26, 0x01, 0x80, 0x61, 0x1F, 0xC6, 0x11, 0x80,
- 0x60, 0x18, 0x16, 0x0F, 0xFE, 0xFF, 0xB0, 0x58, 0x0C, 0x06, 0x13, 0xF9,
- 0x84, 0xC0, 0x60, 0x30, 0x18, 0x1E, 0x00, 0x1F, 0x23, 0x0E, 0x60, 0x26,
- 0x00, 0xC0, 0x0C, 0x0F, 0xC0, 0x6C, 0x06, 0xC0, 0x66, 0x06, 0x30, 0x60,
- 0xF8, 0xF1, 0xEC, 0x19, 0x83, 0x30, 0x66, 0x0C, 0xFF, 0x98, 0x33, 0x06,
- 0x60, 0xCC, 0x19, 0x83, 0x78, 0xF0, 0xF6, 0x66, 0x66, 0x66, 0x66, 0x6F,
- 0x3C, 0x61, 0x86, 0x18, 0x61, 0x86, 0x18, 0x6D, 0xBC, 0xF3, 0xE6, 0x08,
- 0x61, 0x06, 0x20, 0x64, 0x07, 0x80, 0x6C, 0x06, 0x60, 0x63, 0x06, 0x18,
- 0x60, 0xCF, 0x3F, 0xF0, 0x18, 0x06, 0x01, 0x80, 0x60, 0x18, 0x06, 0x01,
- 0x80, 0x60, 0x18, 0x16, 0x0B, 0xFE, 0xF0, 0x0E, 0x70, 0x38, 0xE0, 0x71,
- 0xE1, 0x62, 0xC2, 0xC5, 0xC9, 0x89, 0x93, 0x13, 0x26, 0x23, 0x8C, 0x47,
- 0x18, 0x84, 0x33, 0x88, 0xF0, 0xE0, 0xEE, 0x09, 0xC1, 0x2C, 0x25, 0xC4,
- 0x9C, 0x91, 0x92, 0x1A, 0x41, 0xC8, 0x19, 0x03, 0x70, 0x20, 0x1F, 0x06,
- 0x31, 0x83, 0x20, 0x2C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x68, 0x09,
- 0x83, 0x18, 0xC1, 0xF0, 0xFE, 0x31, 0x98, 0x6C, 0x36, 0x1B, 0x19, 0xF8,
- 0xC0, 0x60, 0x30, 0x18, 0x1E, 0x00, 0x1F, 0x06, 0x31, 0x83, 0x20, 0x2C,
- 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x68, 0x19, 0x83, 0x18, 0xC0, 0xE0,
- 0x0E, 0x00, 0xE0, 0x07, 0xFE, 0x0C, 0x61, 0x86, 0x30, 0xC6, 0x18, 0xC6,
- 0x1F, 0x83, 0x70, 0x67, 0x0C, 0x71, 0x87, 0x78, 0x70, 0x1D, 0x31, 0x98,
- 0x4C, 0x07, 0x80, 0xE0, 0x1C, 0x07, 0x01, 0xA0, 0xD8, 0xCB, 0xC0, 0xFF,
- 0xF8, 0xCE, 0x18, 0x83, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00,
- 0xC0, 0x18, 0x07, 0x80, 0xF0, 0xEC, 0x09, 0x81, 0x30, 0x26, 0x04, 0xC0,
- 0x98, 0x13, 0x02, 0x60, 0x4C, 0x08, 0xC2, 0x0F, 0x80, 0xF8, 0x77, 0x02,
- 0x30, 0x23, 0x04, 0x18, 0x41, 0x84, 0x0C, 0x80, 0xC8, 0x07, 0x00, 0x70,
- 0x02, 0x00, 0x20, 0xFB, 0xE7, 0xB0, 0xC0, 0x8C, 0x20, 0x86, 0x18, 0x41,
- 0x8C, 0x40, 0xCB, 0x20, 0x65, 0x90, 0x1A, 0x70, 0x0E, 0x38, 0x03, 0x1C,
- 0x01, 0x04, 0x00, 0x82, 0x00, 0xFC, 0xF9, 0x83, 0x06, 0x10, 0x19, 0x00,
- 0xD0, 0x03, 0x00, 0x1C, 0x01, 0x30, 0x11, 0xC1, 0x86, 0x08, 0x19, 0xE3,
- 0xF0, 0xF8, 0xF6, 0x06, 0x30, 0x41, 0x88, 0x1D, 0x00, 0xD0, 0x06, 0x00,
- 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0xF0, 0x3F, 0xCC, 0x11, 0x06, 0x01,
- 0x80, 0x70, 0x0C, 0x03, 0x00, 0xE0, 0x38, 0x06, 0x05, 0xC1, 0x7F, 0xE0,
- 0xFB, 0x6D, 0xB6, 0xDB, 0x6D, 0xB8, 0x82, 0x10, 0x82, 0x10, 0x86, 0x10,
- 0x86, 0x10, 0xED, 0xB6, 0xDB, 0x6D, 0xB6, 0xF8, 0x18, 0x1C, 0x34, 0x26,
- 0x62, 0x42, 0xC1, 0xFF, 0x80, 0x84, 0x20, 0x79, 0x98, 0x30, 0xE6, 0xD9,
- 0xB3, 0x3F, 0x20, 0x70, 0x18, 0x0C, 0x06, 0x03, 0x71, 0xCC, 0xC3, 0x61,
- 0xB0, 0xD8, 0x6C, 0x63, 0xE0, 0x3C, 0xCF, 0x06, 0x0C, 0x18, 0x18, 0x9E,
- 0x01, 0x03, 0x80, 0xC0, 0x60, 0x31, 0xD9, 0x9D, 0x86, 0xC3, 0x61, 0xB0,
- 0xCC, 0x63, 0xF0, 0x3C, 0x46, 0xFE, 0xC0, 0xC0, 0xE1, 0x62, 0x3C, 0x1E,
- 0x41, 0x83, 0x06, 0x1E, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x0F, 0x00, 0x3C,
- 0x19, 0xF6, 0x31, 0x8C, 0x1E, 0x08, 0x04, 0x01, 0xFC, 0x40, 0xB0, 0x2E,
- 0x11, 0xF8, 0x20, 0x70, 0x18, 0x0C, 0x06, 0x03, 0x71, 0xCC, 0xC6, 0x63,
- 0x31, 0x98, 0xCC, 0x6F, 0x78, 0x60, 0x02, 0xE6, 0x66, 0x66, 0xF0, 0x18,
- 0x00, 0x33, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8B, 0x80, 0x20, 0x70, 0x18,
- 0x0C, 0x06, 0x03, 0x3D, 0x88, 0xD8, 0x78, 0x36, 0x19, 0x8C, 0x6F, 0x78,
- 0x2E, 0x66, 0x66, 0x66, 0x66, 0x66, 0xF0, 0xEE, 0x71, 0xCE, 0x66, 0x31,
- 0x98, 0xC6, 0x63, 0x19, 0x8C, 0x66, 0x31, 0xBD, 0xEF, 0xEE, 0x39, 0x98,
- 0xCC, 0x66, 0x33, 0x19, 0x8D, 0xEF, 0x3E, 0x31, 0xB0, 0x78, 0x3C, 0x1E,
- 0x0D, 0x8C, 0x7C, 0xEE, 0x39, 0x98, 0x6C, 0x36, 0x1B, 0x0D, 0x8C, 0xFC,
- 0x60, 0x30, 0x18, 0x1E, 0x00, 0x3D, 0x31, 0xB0, 0xD8, 0x6C, 0x36, 0x1B,
- 0x8C, 0xFE, 0x03, 0x01, 0x80, 0xC0, 0xF0, 0x6D, 0xC6, 0x18, 0x61, 0x86,
- 0x3C, 0x76, 0x38, 0x58, 0x3E, 0x38, 0xFE, 0x27, 0x98, 0xC6, 0x31, 0x8C,
- 0x38, 0xE7, 0x31, 0x98, 0xCC, 0x66, 0x33, 0x19, 0x8C, 0x7F, 0xF3, 0x61,
- 0x22, 0x32, 0x14, 0x1C, 0x08, 0x08, 0xEF, 0x36, 0x61, 0x62, 0x22, 0x32,
- 0x35, 0x41, 0x9C, 0x18, 0x81, 0x08, 0xF7, 0x12, 0x0E, 0x03, 0x01, 0xC1,
- 0x21, 0x09, 0xCF, 0xF3, 0x61, 0x62, 0x32, 0x34, 0x14, 0x1C, 0x08, 0x08,
- 0x08, 0x10, 0xE0, 0xFD, 0x18, 0x60, 0x83, 0x0C, 0x70, 0xFE, 0x19, 0x8C,
- 0x63, 0x18, 0xC4, 0x61, 0x8C, 0x63, 0x18, 0xC3, 0xFF, 0xF0, 0xC3, 0x18,
- 0xC6, 0x31, 0x84, 0x33, 0x18, 0xC6, 0x31, 0x98, 0x70, 0x24, 0xC1, 0xC0 };
-
-const GFXglyph FreeSerif9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 2, 12, 6, 2, -11 }, // 0x21 '!'
- { 3, 5, 4, 7, 1, -11 }, // 0x22 '"'
- { 6, 9, 12, 9, 0, -11 }, // 0x23 '#'
- { 20, 8, 14, 9, 1, -12 }, // 0x24 '$'
- { 34, 13, 12, 15, 1, -11 }, // 0x25 '%'
- { 54, 13, 13, 14, 1, -12 }, // 0x26 '&'
- { 76, 2, 4, 4, 1, -11 }, // 0x27 '''
- { 77, 5, 15, 6, 1, -11 }, // 0x28 '('
- { 87, 5, 15, 6, 0, -11 }, // 0x29 ')'
- { 97, 6, 8, 9, 3, -11 }, // 0x2A '*'
- { 103, 9, 9, 10, 0, -8 }, // 0x2B '+'
- { 114, 2, 3, 4, 2, 0 }, // 0x2C ','
- { 115, 4, 1, 6, 1, -3 }, // 0x2D '-'
- { 116, 2, 2, 5, 1, -1 }, // 0x2E '.'
- { 117, 5, 12, 5, 0, -11 }, // 0x2F '/'
- { 125, 9, 13, 9, 0, -12 }, // 0x30 '0'
- { 140, 5, 13, 9, 2, -12 }, // 0x31 '1'
- { 149, 8, 12, 9, 1, -11 }, // 0x32 '2'
- { 161, 8, 12, 9, 0, -11 }, // 0x33 '3'
- { 173, 7, 12, 9, 1, -11 }, // 0x34 '4'
- { 184, 8, 12, 9, 0, -11 }, // 0x35 '5'
- { 196, 8, 13, 9, 1, -12 }, // 0x36 '6'
- { 209, 8, 12, 9, 0, -11 }, // 0x37 '7'
- { 221, 7, 13, 9, 1, -12 }, // 0x38 '8'
- { 233, 8, 14, 9, 1, -12 }, // 0x39 '9'
- { 247, 2, 8, 5, 1, -7 }, // 0x3A ':'
- { 249, 3, 10, 5, 1, -7 }, // 0x3B ';'
- { 253, 9, 9, 10, 1, -8 }, // 0x3C '<'
- { 264, 9, 5, 10, 1, -6 }, // 0x3D '='
- { 270, 10, 9, 10, 0, -8 }, // 0x3E '>'
- { 282, 7, 13, 8, 1, -12 }, // 0x3F '?'
- { 294, 12, 13, 16, 2, -12 }, // 0x40 '@'
- { 314, 13, 12, 13, 0, -11 }, // 0x41 'A'
- { 334, 11, 12, 11, 0, -11 }, // 0x42 'B'
- { 351, 11, 12, 12, 1, -11 }, // 0x43 'C'
- { 368, 12, 12, 13, 0, -11 }, // 0x44 'D'
- { 386, 10, 12, 11, 1, -11 }, // 0x45 'E'
- { 401, 9, 12, 10, 1, -11 }, // 0x46 'F'
- { 415, 12, 12, 13, 1, -11 }, // 0x47 'G'
- { 433, 11, 12, 13, 1, -11 }, // 0x48 'H'
- { 450, 4, 12, 6, 1, -11 }, // 0x49 'I'
- { 456, 6, 12, 7, 0, -11 }, // 0x4A 'J'
- { 465, 12, 12, 13, 1, -11 }, // 0x4B 'K'
- { 483, 10, 12, 11, 1, -11 }, // 0x4C 'L'
- { 498, 15, 12, 16, 0, -11 }, // 0x4D 'M'
- { 521, 11, 12, 13, 1, -11 }, // 0x4E 'N'
- { 538, 11, 13, 13, 1, -12 }, // 0x4F 'O'
- { 556, 9, 12, 10, 1, -11 }, // 0x50 'P'
- { 570, 11, 16, 13, 1, -12 }, // 0x51 'Q'
- { 592, 11, 12, 12, 1, -11 }, // 0x52 'R'
- { 609, 9, 12, 10, 0, -11 }, // 0x53 'S'
- { 623, 11, 12, 11, 0, -11 }, // 0x54 'T'
- { 640, 11, 12, 13, 1, -11 }, // 0x55 'U'
- { 657, 12, 12, 13, 0, -11 }, // 0x56 'V'
- { 675, 17, 12, 17, 0, -11 }, // 0x57 'W'
- { 701, 13, 12, 13, 0, -11 }, // 0x58 'X'
- { 721, 12, 12, 13, 0, -11 }, // 0x59 'Y'
- { 739, 11, 12, 11, 0, -11 }, // 0x5A 'Z'
- { 756, 3, 15, 6, 2, -11 }, // 0x5B '['
- { 762, 5, 12, 5, 0, -11 }, // 0x5C '\'
- { 770, 3, 15, 6, 1, -11 }, // 0x5D ']'
- { 776, 8, 7, 8, 0, -11 }, // 0x5E '^'
- { 783, 9, 1, 9, 0, 2 }, // 0x5F '_'
- { 785, 4, 3, 5, 0, -11 }, // 0x60 '`'
- { 787, 7, 8, 8, 1, -7 }, // 0x61 'a'
- { 794, 9, 13, 9, 0, -12 }, // 0x62 'b'
- { 809, 7, 8, 8, 0, -7 }, // 0x63 'c'
- { 816, 9, 13, 9, 0, -12 }, // 0x64 'd'
- { 831, 8, 8, 8, 0, -7 }, // 0x65 'e'
- { 839, 7, 13, 7, 1, -12 }, // 0x66 'f'
- { 851, 10, 12, 8, 0, -7 }, // 0x67 'g'
- { 866, 9, 13, 9, 0, -12 }, // 0x68 'h'
- { 881, 4, 11, 5, 1, -10 }, // 0x69 'i'
- { 887, 5, 15, 6, 0, -10 }, // 0x6A 'j'
- { 897, 9, 13, 9, 1, -12 }, // 0x6B 'k'
- { 912, 4, 13, 5, 1, -12 }, // 0x6C 'l'
- { 919, 14, 8, 14, 0, -7 }, // 0x6D 'm'
- { 933, 9, 8, 9, 0, -7 }, // 0x6E 'n'
- { 942, 9, 8, 9, 0, -7 }, // 0x6F 'o'
- { 951, 9, 12, 9, 0, -7 }, // 0x70 'p'
- { 965, 9, 12, 9, 0, -7 }, // 0x71 'q'
- { 979, 6, 8, 6, 0, -7 }, // 0x72 'r'
- { 985, 6, 8, 7, 1, -7 }, // 0x73 's'
- { 991, 5, 9, 5, 0, -8 }, // 0x74 't'
- { 997, 9, 8, 9, 0, -7 }, // 0x75 'u'
- { 1006, 8, 8, 8, 0, -7 }, // 0x76 'v'
- { 1014, 12, 8, 12, 0, -7 }, // 0x77 'w'
- { 1026, 9, 8, 9, 0, -7 }, // 0x78 'x'
- { 1035, 8, 12, 8, 0, -7 }, // 0x79 'y'
- { 1047, 7, 8, 7, 1, -7 }, // 0x7A 'z'
- { 1054, 5, 16, 9, 1, -12 }, // 0x7B '{'
- { 1064, 1, 12, 4, 1, -11 }, // 0x7C '|'
- { 1066, 5, 16, 9, 3, -11 }, // 0x7D '}'
- { 1076, 9, 3, 9, 0, -5 } }; // 0x7E '~'
-
-const GFXfont FreeSerif9pt7b PROGMEM = {
- (uint8_t *)FreeSerif9pt7bBitmaps,
- (GFXglyph *)FreeSerif9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1752 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold12pt7b.h
deleted file mode 100644
index 1d49981..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold12pt7b.h
+++ /dev/null
@@ -1,271 +0,0 @@
-const uint8_t FreeSerifBold12pt7bBitmaps[] PROGMEM = {
- 0x7F, 0xFF, 0x77, 0x66, 0x22, 0x00, 0x6F, 0xF7, 0xE3, 0xF1, 0xF8, 0xFC,
- 0x7E, 0x3A, 0x09, 0x04, 0x0C, 0x40, 0xCC, 0x0C, 0xC0, 0x8C, 0x18, 0xC7,
- 0xFF, 0x18, 0xC1, 0x88, 0x19, 0x81, 0x98, 0xFF, 0xE3, 0x18, 0x31, 0x83,
- 0x18, 0x33, 0x03, 0x30, 0x08, 0x01, 0x00, 0xFC, 0x24, 0xEC, 0x8D, 0x90,
- 0xBA, 0x07, 0xC0, 0x7E, 0x07, 0xF0, 0x7F, 0x07, 0xF0, 0x9F, 0x11, 0xE2,
- 0x3E, 0x46, 0xE9, 0xC7, 0xC0, 0x20, 0x04, 0x00, 0x1E, 0x0C, 0x0E, 0x7F,
- 0x07, 0x10, 0x83, 0xC4, 0x40, 0xE1, 0x30, 0x38, 0x88, 0x0E, 0x26, 0x03,
- 0x91, 0x1E, 0x78, 0x8E, 0x40, 0x27, 0x10, 0x11, 0xC4, 0x0C, 0xE1, 0x02,
- 0x38, 0x81, 0x0E, 0x20, 0x43, 0x90, 0x20, 0x78, 0x03, 0xE0, 0x01, 0x9E,
- 0x00, 0xE3, 0x80, 0x38, 0xE0, 0x0F, 0x30, 0x03, 0xF0, 0x00, 0x78, 0x7C,
- 0x1F, 0x06, 0x1B, 0xE1, 0x1C, 0x7C, 0x8F, 0x1F, 0x23, 0xC3, 0xF0, 0xF8,
- 0x7C, 0x3E, 0x0F, 0x97, 0xC7, 0xFC, 0xFE, 0x3E, 0xFF, 0xFE, 0x90, 0x00,
- 0x31, 0x0C, 0x31, 0x86, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x86, 0x18, 0x60,
- 0xC1, 0x02, 0x04, 0x03, 0x06, 0x0C, 0x30, 0x61, 0x87, 0x1C, 0x71, 0xC7,
- 0x1C, 0x71, 0x86, 0x38, 0xC2, 0x10, 0x80, 0x1C, 0x6E, 0xFA, 0xEF, 0xF1,
- 0xC7, 0xFF, 0xAF, 0xBB, 0x1C, 0x04, 0x00, 0x06, 0x00, 0x60, 0x06, 0x00,
- 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00,
- 0x60, 0x6F, 0xF7, 0x11, 0x24, 0xFF, 0xFF, 0xC0, 0x6F, 0xF6, 0x03, 0x07,
- 0x06, 0x06, 0x0C, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x30, 0x30, 0x30, 0x60,
- 0x60, 0x60, 0xC0, 0x0E, 0x07, 0x71, 0xC7, 0x38, 0xEF, 0x1D, 0xE3, 0xFC,
- 0x7F, 0x8F, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xF7, 0x1C, 0xE3, 0x8E, 0xE0,
- 0xF8, 0x06, 0x0F, 0x1F, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F,
- 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0xF9, 0xFF, 0x0F, 0x03, 0xFC, 0x7F, 0xC4,
- 0x3E, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x1C, 0x03, 0x80, 0x30, 0x06, 0x00,
- 0xC1, 0x18, 0x13, 0xFE, 0x7F, 0xEF, 0xFE, 0x1F, 0x0C, 0xFA, 0x0F, 0x01,
- 0xE0, 0x38, 0x0E, 0x03, 0xE0, 0x3E, 0x03, 0xE0, 0x3C, 0x03, 0x80, 0x70,
- 0x0D, 0xC1, 0xBC, 0x43, 0xF0, 0x03, 0x80, 0xE0, 0x78, 0x3E, 0x17, 0x89,
- 0xE2, 0x79, 0x1E, 0x87, 0xA1, 0xEF, 0xFF, 0xFF, 0xFF, 0xC1, 0xE0, 0x78,
- 0x1E, 0x3F, 0xE7, 0xF8, 0xFF, 0x10, 0x04, 0x00, 0xF8, 0x1F, 0xC7, 0xFC,
- 0x1F, 0xC0, 0x78, 0x07, 0x00, 0x60, 0x0D, 0xC1, 0x3C, 0x43, 0xF0, 0x00,
- 0xE0, 0xF0, 0x38, 0x1E, 0x07, 0x80, 0xF0, 0x3F, 0xE7, 0x9E, 0xF1, 0xFE,
- 0x3F, 0xC7, 0xF8, 0xF7, 0x1E, 0xE3, 0x8E, 0x60, 0xF8, 0x7F, 0xEF, 0xFD,
- 0xFF, 0xA0, 0x68, 0x0C, 0x03, 0x80, 0x60, 0x0C, 0x03, 0x00, 0x60, 0x0C,
- 0x03, 0x00, 0x60, 0x1C, 0x03, 0x00, 0x60, 0x1F, 0x0E, 0x73, 0x87, 0x70,
- 0xEF, 0x1D, 0xF3, 0x1F, 0x81, 0xF8, 0x1F, 0xCC, 0xFB, 0x8F, 0xF0, 0xFE,
- 0x1F, 0xC3, 0x9C, 0xF1, 0xF8, 0x1F, 0x06, 0x71, 0xC7, 0x78, 0xEF, 0x1F,
- 0xE3, 0xFC, 0x7F, 0x8F, 0x79, 0xE7, 0xFC, 0x0F, 0x01, 0xC0, 0x78, 0x1C,
- 0x0F, 0x07, 0x00, 0x6F, 0xF6, 0x00, 0x06, 0xFF, 0x60, 0x6F, 0xF6, 0x00,
- 0x06, 0xFF, 0x71, 0x22, 0xC0, 0x00, 0x04, 0x00, 0x70, 0x07, 0xC0, 0xFC,
- 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F,
- 0x00, 0x1F, 0x00, 0x1C, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0x00, 0x03, 0x80, 0x0F,
- 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x1F, 0x01, 0xF0,
- 0x1F, 0x03, 0xF0, 0x3E, 0x00, 0xE0, 0x02, 0x00, 0x00, 0x3E, 0x11, 0xEC,
- 0x3F, 0x8F, 0xE3, 0xC0, 0xF0, 0x78, 0x18, 0x08, 0x02, 0x00, 0x00, 0x00,
- 0x1C, 0x07, 0x81, 0xE0, 0x30, 0x03, 0xF0, 0x0E, 0x18, 0x18, 0x04, 0x30,
- 0x66, 0x70, 0xDB, 0x61, 0x99, 0xE3, 0x19, 0xE3, 0x31, 0xE6, 0x31, 0xE6,
- 0x31, 0xE6, 0xF2, 0x66, 0xB2, 0x73, 0x3C, 0x38, 0x00, 0x1E, 0x04, 0x03,
- 0xF8, 0x00, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x3E, 0x00,
- 0x1F, 0x00, 0x1B, 0xC0, 0x09, 0xE0, 0x0C, 0xF8, 0x04, 0x3C, 0x02, 0x1F,
- 0x03, 0xFF, 0x81, 0x03, 0xC1, 0x80, 0xF0, 0x80, 0x7D, 0xF0, 0xFF, 0xFF,
- 0xC0, 0xF3, 0xC3, 0xC7, 0x8F, 0x1E, 0x3C, 0x78, 0xF1, 0xE3, 0xCE, 0x0F,
- 0xF0, 0x3C, 0x70, 0xF0, 0xE3, 0xC3, 0xCF, 0x0F, 0x3C, 0x3C, 0xF0, 0xE3,
- 0xC7, 0xBF, 0xF8, 0x07, 0xE2, 0x38, 0x7C, 0xE0, 0x3B, 0xC0, 0x37, 0x00,
- 0x7E, 0x00, 0x7C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x03,
- 0x80, 0x07, 0x80, 0x27, 0x00, 0xC7, 0x86, 0x03, 0xF0, 0xFF, 0xE0, 0x1E,
- 0x1E, 0x0F, 0x07, 0x87, 0x81, 0xE3, 0xC0, 0xF1, 0xE0, 0x3C, 0xF0, 0x1E,
- 0x78, 0x0F, 0x3C, 0x07, 0x9E, 0x03, 0xCF, 0x01, 0xE7, 0x80, 0xE3, 0xC0,
- 0xF1, 0xE0, 0xF0, 0xF0, 0xE1, 0xFF, 0xC0, 0xFF, 0xFC, 0x78, 0x38, 0xF0,
- 0x31, 0xE0, 0x23, 0xC4, 0x07, 0x88, 0x0F, 0x30, 0x1F, 0xE0, 0x3C, 0xC0,
- 0x78, 0x80, 0xF1, 0x01, 0xE0, 0x23, 0xC0, 0x47, 0x81, 0x8F, 0x07, 0x7F,
- 0xFE, 0xFF, 0xFC, 0xF0, 0x73, 0xC0, 0xCF, 0x01, 0x3C, 0x40, 0xF1, 0x03,
- 0xCC, 0x0F, 0xF0, 0x3C, 0xC0, 0xF1, 0x03, 0xC4, 0x0F, 0x00, 0x3C, 0x00,
- 0xF0, 0x03, 0xC0, 0x3F, 0xC0, 0x07, 0xE2, 0x1C, 0x3E, 0x38, 0x0E, 0x78,
- 0x06, 0x70, 0x06, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0,
- 0x7F, 0xF0, 0x1E, 0x70, 0x1E, 0x78, 0x1E, 0x38, 0x1E, 0x1E, 0x1E, 0x07,
- 0xF0, 0xFE, 0xFF, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78,
- 0x3C, 0x78, 0x3C, 0x7F, 0xFC, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78,
- 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0xFE, 0xFF, 0xFF, 0x3C, 0x3C,
- 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C,
- 0xFF, 0x0F, 0xF0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0,
- 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0xE3, 0xCE,
- 0x38, 0xE3, 0x83, 0xE0, 0xFE, 0x7F, 0x3C, 0x0E, 0x1E, 0x04, 0x0F, 0x04,
- 0x07, 0x84, 0x03, 0xCC, 0x01, 0xEE, 0x00, 0xFF, 0x00, 0x7F, 0xC0, 0x3C,
- 0xF0, 0x1E, 0x7C, 0x0F, 0x1F, 0x07, 0x87, 0xC3, 0xC1, 0xF1, 0xE0, 0x7D,
- 0xFC, 0xFF, 0xFE, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0,
- 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x01, 0x78,
- 0x0D, 0xE0, 0x67, 0x83, 0xBF, 0xFE, 0xFC, 0x01, 0xF3, 0xC0, 0x3E, 0x3E,
- 0x03, 0xE2, 0xE0, 0x5E, 0x2F, 0x05, 0xE2, 0xF0, 0x5E, 0x27, 0x09, 0xE2,
- 0x78, 0x9E, 0x23, 0x91, 0xE2, 0x3D, 0x1E, 0x23, 0xF1, 0xE2, 0x1E, 0x1E,
- 0x21, 0xE1, 0xE2, 0x0C, 0x1E, 0x20, 0xC1, 0xEF, 0x88, 0x3F, 0xF8, 0x1E,
- 0xF8, 0x18, 0xF8, 0x11, 0xF8, 0x22, 0xF8, 0x45, 0xF0, 0x89, 0xF1, 0x11,
- 0xF2, 0x21, 0xF4, 0x41, 0xF8, 0x81, 0xF1, 0x01, 0xE2, 0x03, 0xC4, 0x03,
- 0x8C, 0x03, 0x7C, 0x02, 0x07, 0xF0, 0x0F, 0x1E, 0x0E, 0x03, 0x8F, 0x01,
- 0xE7, 0x00, 0x77, 0x80, 0x3F, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8,
- 0x03, 0xFC, 0x01, 0xEE, 0x00, 0xE7, 0x80, 0xF1, 0xC0, 0x70, 0x70, 0x70,
- 0x0F, 0xE0, 0xFF, 0x87, 0x9E, 0x78, 0xF7, 0x8F, 0x78, 0xF7, 0x8F, 0x78,
- 0xF7, 0x9E, 0x7F, 0x87, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0x80, 0x78,
- 0x0F, 0xE0, 0x07, 0xF0, 0x0F, 0x1E, 0x0E, 0x07, 0x8F, 0x01, 0xE7, 0x00,
- 0xF7, 0x80, 0x3F, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC,
- 0x01, 0xEE, 0x00, 0xE7, 0x00, 0xF1, 0xC0, 0x70, 0x70, 0x70, 0x1C, 0xF0,
- 0x03, 0xE0, 0x01, 0xF8, 0x00, 0x3E, 0x00, 0x07, 0xE0, 0xFF, 0xE0, 0x3C,
- 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x38, 0x3C,
- 0x70, 0x3F, 0xC0, 0x3D, 0xE0, 0x3C, 0xF0, 0x3C, 0xF8, 0x3C, 0x78, 0x3C,
- 0x3C, 0x3C, 0x3E, 0xFF, 0x1F, 0x1F, 0x27, 0x0E, 0x60, 0x6E, 0x06, 0xF0,
- 0x2F, 0x80, 0x7F, 0x07, 0xFC, 0x1F, 0xE0, 0x7E, 0x01, 0xF8, 0x07, 0xC0,
- 0x7C, 0x06, 0xF0, 0xC9, 0xF8, 0xFF, 0xFF, 0xC7, 0x9F, 0x0F, 0x1C, 0x1E,
- 0x10, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80,
- 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x07, 0xF8, 0xFE,
- 0x1E, 0xF0, 0x09, 0xE0, 0x13, 0xC0, 0x27, 0x80, 0x4F, 0x00, 0x9E, 0x01,
- 0x3C, 0x02, 0x78, 0x04, 0xF0, 0x09, 0xE0, 0x13, 0xC0, 0x27, 0x80, 0x47,
- 0x81, 0x07, 0x84, 0x07, 0xF0, 0xFF, 0x0F, 0x9E, 0x03, 0x0F, 0x00, 0x83,
- 0xC0, 0x81, 0xE0, 0x40, 0xF8, 0x60, 0x3C, 0x20, 0x1E, 0x10, 0x07, 0x90,
- 0x03, 0xC8, 0x00, 0xF4, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x07,
- 0x00, 0x01, 0x80, 0x00, 0x80, 0x00, 0xFE, 0x7F, 0x9E, 0xF8, 0x3C, 0x08,
- 0xF0, 0x78, 0x31, 0xE0, 0xF0, 0x41, 0xE0, 0xF0, 0x83, 0xC3, 0xE3, 0x07,
- 0x85, 0xC4, 0x07, 0x93, 0xC8, 0x0F, 0x27, 0xB0, 0x0E, 0x47, 0x40, 0x1F,
- 0x0F, 0x80, 0x3E, 0x1F, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x38, 0x00, 0xE0,
- 0x30, 0x00, 0x80, 0x40, 0xFF, 0x9F, 0x9F, 0x07, 0x07, 0x83, 0x03, 0xE3,
- 0x00, 0xF9, 0x00, 0x3D, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xE0, 0x00,
- 0xF8, 0x00, 0xBE, 0x00, 0x8F, 0x00, 0x83, 0xC0, 0xC1, 0xF0, 0xE0, 0xFD,
- 0xF8, 0xFF, 0xFF, 0x1F, 0x7C, 0x06, 0x3C, 0x04, 0x3E, 0x0C, 0x1E, 0x08,
- 0x0F, 0x10, 0x0F, 0x30, 0x07, 0xA0, 0x07, 0xC0, 0x03, 0xC0, 0x03, 0xC0,
- 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x0F, 0xF0, 0x7F, 0xFC,
- 0xE0, 0xF1, 0x83, 0xE2, 0x07, 0x84, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x03,
- 0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x7C, 0x08, 0xF0, 0x13, 0xC0, 0x6F, 0x81,
- 0x9E, 0x07, 0x7F, 0xFE, 0xFF, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE,
- 0x73, 0x9C, 0xE7, 0x39, 0xF0, 0xC0, 0x60, 0x60, 0x60, 0x30, 0x30, 0x30,
- 0x18, 0x18, 0x18, 0x0C, 0x0C, 0x0C, 0x06, 0x06, 0x06, 0x03, 0xF9, 0xCE,
- 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCF, 0xF0, 0x0C,
- 0x07, 0x81, 0xE0, 0xCC, 0x33, 0x18, 0x66, 0x1B, 0x87, 0xC0, 0xC0, 0xFF,
- 0xF0, 0xC7, 0x1C, 0x30, 0x1F, 0x0E, 0x71, 0xCF, 0x39, 0xE0, 0x3C, 0x1F,
- 0x8E, 0xF3, 0x9E, 0xF3, 0xDE, 0x79, 0xFF, 0x80, 0xF8, 0x07, 0x80, 0x78,
- 0x07, 0x80, 0x78, 0x07, 0xB8, 0x7D, 0xE7, 0x8E, 0x78, 0xF7, 0x8F, 0x78,
- 0xF7, 0x8F, 0x78, 0xF7, 0x8E, 0x79, 0xC4, 0x78, 0x1F, 0x1D, 0xDC, 0xFE,
- 0x7F, 0x07, 0x83, 0xC1, 0xE0, 0x78, 0x3C, 0x47, 0xC0, 0x03, 0xE0, 0x1E,
- 0x01, 0xE0, 0x1E, 0x01, 0xE1, 0xDE, 0x7B, 0xE7, 0x1E, 0xF1, 0xEF, 0x1E,
- 0xF1, 0xEF, 0x1E, 0xF1, 0xE7, 0x1E, 0x7B, 0xE1, 0xDF, 0x1F, 0x0C, 0x67,
- 0x1B, 0xC7, 0xFF, 0xFC, 0x0F, 0x03, 0xC0, 0x78, 0x4E, 0x21, 0xF0, 0x1E,
- 0x3B, 0x7B, 0x78, 0x78, 0xFC, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
- 0x78, 0x78, 0xFC, 0x3E, 0x0E, 0x7F, 0xCE, 0x79, 0xEF, 0x3C, 0xE7, 0x0F,
- 0xC1, 0x00, 0x60, 0x1C, 0x03, 0xFE, 0x7F, 0xE3, 0xFF, 0x80, 0xF0, 0x33,
- 0xFC, 0xF8, 0x07, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0xB8, 0x7D, 0xE7,
- 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xEF,
- 0xFF, 0x31, 0xE7, 0x8C, 0x03, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7,
- 0xBF, 0x06, 0x0F, 0x0F, 0x06, 0x00, 0x1F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0xCF, 0xCE, 0x7C, 0xF8, 0x03,
- 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0xF9, 0xE1, 0x8F, 0x10, 0x79,
- 0x03, 0xD8, 0x1F, 0xE0, 0xF7, 0x87, 0x9E, 0x3C, 0x71, 0xE3, 0xDF, 0xBF,
- 0xF9, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0xBF,
- 0xFB, 0xCF, 0x0F, 0xBE, 0x79, 0xE7, 0x8F, 0x3C, 0xF1, 0xE7, 0x9E, 0x3C,
- 0xF3, 0xC7, 0x9E, 0x78, 0xF3, 0xCF, 0x1E, 0x79, 0xE3, 0xCF, 0x3C, 0x7B,
- 0xFF, 0xDF, 0x80, 0xFB, 0x87, 0xDE, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E,
- 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0xFF, 0xF0, 0x1F, 0x07, 0x71, 0xC7,
- 0x78, 0xFF, 0x1F, 0xE3, 0xFC, 0x7F, 0x8F, 0x71, 0xC7, 0x70, 0x7C, 0x00,
- 0xFB, 0x87, 0xDE, 0x78, 0xE7, 0x8F, 0x78, 0xF7, 0x8F, 0x78, 0xF7, 0x8F,
- 0x78, 0xE7, 0x9E, 0x7F, 0x87, 0x80, 0x78, 0x07, 0x80, 0x78, 0x0F, 0xC0,
- 0x1E, 0x23, 0x9E, 0x71, 0xEF, 0x1E, 0xF1, 0xEF, 0x1E, 0xF1, 0xEF, 0x1E,
- 0x71, 0xE7, 0x9E, 0x1F, 0xE0, 0x1E, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x3F,
- 0xF9, 0xDF, 0xF7, 0xDD, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E,
- 0x0F, 0xC0, 0x3D, 0x43, 0xC3, 0xE0, 0xFC, 0x7E, 0x1F, 0x87, 0x83, 0xC2,
- 0xBC, 0x08, 0x18, 0x38, 0x78, 0xFC, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
- 0x78, 0x78, 0x79, 0x3E, 0xFB, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7,
- 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x3F, 0xF0, 0xFC, 0xEF, 0x08,
- 0xE1, 0x1E, 0x41, 0xC8, 0x3D, 0x03, 0xC0, 0x78, 0x0E, 0x00, 0xC0, 0x10,
- 0x00, 0xFD, 0xF7, 0xBC, 0x71, 0x9E, 0x38, 0x87, 0x1E, 0x43, 0xCF, 0x40,
- 0xEB, 0xA0, 0x7C, 0xF0, 0x1C, 0x70, 0x0E, 0x38, 0x06, 0x08, 0x01, 0x04,
- 0x00, 0xFC, 0xF7, 0x84, 0x3C, 0x81, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x80,
- 0xBC, 0x13, 0xC2, 0x1E, 0xFB, 0xF0, 0xFC, 0xEF, 0x08, 0xE1, 0x1E, 0x43,
- 0xC8, 0x3A, 0x07, 0xC0, 0x78, 0x0E, 0x01, 0xC0, 0x18, 0x02, 0x00, 0x41,
- 0xC8, 0x3A, 0x03, 0x80, 0xFF, 0xB1, 0xE8, 0x70, 0x3C, 0x1E, 0x07, 0x83,
- 0xC1, 0xE0, 0x78, 0xBC, 0x2F, 0xF8, 0x07, 0x0E, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1C, 0x1C, 0x1C, 0xE0, 0x18, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
- 0x1C, 0x1E, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xE0, 0x70, 0x38, 0x38,
- 0x38, 0x38, 0x38, 0x38, 0x38, 0x18, 0x07, 0x38, 0x38, 0x38, 0x38, 0x38,
- 0x38, 0x38, 0x38, 0x70, 0xE0, 0x70, 0x1F, 0x8B, 0x3F, 0x01, 0xC0 };
-
-const GFXglyph FreeSerifBold12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 4, 16, 8, 2, -15 }, // 0x21 '!'
- { 8, 9, 7, 13, 2, -15 }, // 0x22 '"'
- { 16, 12, 16, 12, 0, -15 }, // 0x23 '#'
- { 40, 11, 20, 12, 1, -17 }, // 0x24 '$'
- { 68, 18, 16, 24, 3, -15 }, // 0x25 '%'
- { 104, 18, 16, 20, 1, -15 }, // 0x26 '&'
- { 140, 3, 7, 7, 2, -15 }, // 0x27 '''
- { 143, 6, 21, 8, 1, -16 }, // 0x28 '('
- { 159, 6, 21, 8, 1, -16 }, // 0x29 ')'
- { 175, 9, 10, 12, 2, -15 }, // 0x2A '*'
- { 187, 12, 12, 16, 2, -11 }, // 0x2B '+'
- { 205, 4, 8, 6, 1, -3 }, // 0x2C ','
- { 209, 6, 3, 8, 1, -6 }, // 0x2D '-'
- { 212, 4, 4, 6, 1, -3 }, // 0x2E '.'
- { 214, 8, 17, 7, -1, -15 }, // 0x2F '/'
- { 231, 11, 16, 12, 1, -15 }, // 0x30 '0'
- { 253, 9, 16, 12, 1, -15 }, // 0x31 '1'
- { 271, 12, 16, 12, 0, -15 }, // 0x32 '2'
- { 295, 11, 16, 12, 1, -15 }, // 0x33 '3'
- { 317, 10, 16, 12, 1, -15 }, // 0x34 '4'
- { 337, 11, 16, 12, 1, -15 }, // 0x35 '5'
- { 359, 11, 16, 12, 1, -15 }, // 0x36 '6'
- { 381, 11, 16, 12, 0, -15 }, // 0x37 '7'
- { 403, 11, 16, 12, 1, -15 }, // 0x38 '8'
- { 425, 11, 16, 12, 1, -15 }, // 0x39 '9'
- { 447, 4, 11, 8, 2, -10 }, // 0x3A ':'
- { 453, 4, 15, 8, 2, -10 }, // 0x3B ';'
- { 461, 14, 14, 16, 1, -12 }, // 0x3C '<'
- { 486, 14, 8, 16, 1, -9 }, // 0x3D '='
- { 500, 14, 14, 16, 1, -12 }, // 0x3E '>'
- { 525, 10, 16, 12, 1, -15 }, // 0x3F '?'
- { 545, 16, 16, 22, 3, -15 }, // 0x40 '@'
- { 577, 17, 16, 17, 0, -15 }, // 0x41 'A'
- { 611, 14, 16, 16, 1, -15 }, // 0x42 'B'
- { 639, 15, 16, 17, 1, -15 }, // 0x43 'C'
- { 669, 17, 16, 18, 0, -15 }, // 0x44 'D'
- { 703, 15, 16, 16, 1, -15 }, // 0x45 'E'
- { 733, 14, 16, 15, 1, -15 }, // 0x46 'F'
- { 761, 16, 16, 19, 1, -15 }, // 0x47 'G'
- { 793, 16, 16, 19, 2, -15 }, // 0x48 'H'
- { 825, 8, 16, 9, 1, -15 }, // 0x49 'I'
- { 841, 12, 18, 12, 0, -15 }, // 0x4A 'J'
- { 868, 17, 16, 19, 2, -15 }, // 0x4B 'K'
- { 902, 14, 16, 16, 2, -15 }, // 0x4C 'L'
- { 930, 20, 16, 23, 1, -15 }, // 0x4D 'M'
- { 970, 15, 16, 17, 1, -15 }, // 0x4E 'N'
- { 1000, 17, 16, 19, 1, -15 }, // 0x4F 'O'
- { 1034, 12, 16, 15, 2, -15 }, // 0x50 'P'
- { 1058, 17, 20, 19, 1, -15 }, // 0x51 'Q'
- { 1101, 16, 16, 17, 1, -15 }, // 0x52 'R'
- { 1133, 12, 16, 14, 1, -15 }, // 0x53 'S'
- { 1157, 15, 16, 15, 0, -15 }, // 0x54 'T'
- { 1187, 15, 16, 17, 1, -15 }, // 0x55 'U'
- { 1217, 17, 17, 17, 0, -15 }, // 0x56 'V'
- { 1254, 23, 16, 24, 0, -15 }, // 0x57 'W'
- { 1300, 17, 16, 17, 0, -15 }, // 0x58 'X'
- { 1334, 16, 16, 17, 1, -15 }, // 0x59 'Y'
- { 1366, 15, 16, 16, 0, -15 }, // 0x5A 'Z'
- { 1396, 5, 20, 8, 2, -15 }, // 0x5B '['
- { 1409, 8, 17, 7, -1, -15 }, // 0x5C '\'
- { 1426, 5, 20, 8, 2, -15 }, // 0x5D ']'
- { 1439, 10, 9, 14, 2, -15 }, // 0x5E '^'
- { 1451, 12, 1, 12, 0, 4 }, // 0x5F '_'
- { 1453, 5, 4, 8, 0, -16 }, // 0x60 '`'
- { 1456, 11, 11, 12, 1, -10 }, // 0x61 'a'
- { 1472, 12, 16, 13, 1, -15 }, // 0x62 'b'
- { 1496, 9, 11, 10, 1, -10 }, // 0x63 'c'
- { 1509, 12, 16, 13, 1, -15 }, // 0x64 'd'
- { 1533, 10, 11, 11, 1, -10 }, // 0x65 'e'
- { 1547, 8, 16, 9, 1, -15 }, // 0x66 'f'
- { 1563, 11, 16, 12, 1, -10 }, // 0x67 'g'
- { 1585, 12, 16, 13, 1, -15 }, // 0x68 'h'
- { 1609, 6, 16, 7, 1, -15 }, // 0x69 'i'
- { 1621, 8, 21, 10, 0, -15 }, // 0x6A 'j'
- { 1642, 13, 16, 13, 1, -15 }, // 0x6B 'k'
- { 1668, 6, 16, 7, 1, -15 }, // 0x6C 'l'
- { 1680, 19, 11, 20, 1, -10 }, // 0x6D 'm'
- { 1707, 12, 11, 13, 1, -10 }, // 0x6E 'n'
- { 1724, 11, 11, 12, 1, -10 }, // 0x6F 'o'
- { 1740, 12, 16, 13, 1, -10 }, // 0x70 'p'
- { 1764, 12, 16, 13, 1, -10 }, // 0x71 'q'
- { 1788, 10, 11, 10, 1, -10 }, // 0x72 'r'
- { 1802, 8, 11, 10, 1, -10 }, // 0x73 's'
- { 1813, 8, 15, 8, 1, -14 }, // 0x74 't'
- { 1828, 12, 11, 14, 1, -10 }, // 0x75 'u'
- { 1845, 11, 11, 12, 0, -10 }, // 0x76 'v'
- { 1861, 17, 11, 17, 0, -10 }, // 0x77 'w'
- { 1885, 12, 11, 12, 0, -10 }, // 0x78 'x'
- { 1902, 11, 16, 12, 0, -10 }, // 0x79 'y'
- { 1924, 10, 11, 11, 1, -10 }, // 0x7A 'z'
- { 1938, 8, 21, 9, 0, -16 }, // 0x7B '{'
- { 1959, 2, 17, 5, 2, -15 }, // 0x7C '|'
- { 1964, 8, 21, 9, 2, -16 }, // 0x7D '}'
- { 1985, 11, 4, 12, 1, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBold12pt7b PROGMEM = {
- (uint8_t *)FreeSerifBold12pt7bBitmaps,
- (GFXglyph *)FreeSerifBold12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2663 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold18pt7b.h
deleted file mode 100644
index 11d3c7e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold18pt7b.h
+++ /dev/null
@@ -1,462 +0,0 @@
-const uint8_t FreeSerifBold18pt7bBitmaps[] PROGMEM = {
- 0x7B, 0xEF, 0xFF, 0xFF, 0xF7, 0x9E, 0x71, 0xC7, 0x0C, 0x20, 0x82, 0x00,
- 0x00, 0x07, 0x3E, 0xFF, 0xFF, 0xDC, 0x60, 0x37, 0x83, 0xFC, 0x1F, 0xE0,
- 0xFF, 0x07, 0xB8, 0x3D, 0xC0, 0xCC, 0x06, 0x20, 0x31, 0x01, 0x80, 0x03,
- 0x8E, 0x00, 0xC3, 0x80, 0x30, 0xE0, 0x1C, 0x38, 0x07, 0x0E, 0x01, 0xC3,
- 0x87, 0xFF, 0xFD, 0xFF, 0xFF, 0x7F, 0xFF, 0xC1, 0x87, 0x00, 0xE1, 0xC0,
- 0x38, 0x70, 0x0E, 0x1C, 0x03, 0x86, 0x0F, 0xFF, 0xF3, 0xFF, 0xFC, 0xFF,
- 0xFF, 0x07, 0x0E, 0x01, 0xC3, 0x80, 0x70, 0xE0, 0x1C, 0x30, 0x07, 0x0C,
- 0x01, 0x87, 0x00, 0x61, 0xC0, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0xFF,
- 0x03, 0x27, 0x8C, 0x47, 0x38, 0x86, 0x71, 0x0C, 0xF2, 0x09, 0xF4, 0x03,
- 0xF8, 0x03, 0xF8, 0x07, 0xFC, 0x03, 0xFC, 0x03, 0xFE, 0x01, 0xFE, 0x03,
- 0xFC, 0x04, 0xFC, 0x08, 0xFA, 0x10, 0xF4, 0x21, 0xEC, 0x43, 0xD8, 0x8F,
- 0x3D, 0x3C, 0x3F, 0xF0, 0x1F, 0x00, 0x08, 0x00, 0x10, 0x00, 0x03, 0xC0,
- 0x18, 0x01, 0xFE, 0x0F, 0x00, 0x7C, 0xFF, 0xC0, 0x1F, 0x0F, 0x90, 0x07,
- 0xC1, 0x06, 0x00, 0xF0, 0x21, 0x80, 0x3E, 0x04, 0x30, 0x07, 0x81, 0x8C,
- 0x00, 0xF0, 0x21, 0x80, 0x1E, 0x0C, 0x60, 0x03, 0xC1, 0x18, 0x1E, 0x3C,
- 0xE3, 0x0F, 0xE7, 0xF8, 0xC3, 0xE6, 0x3C, 0x18, 0xF8, 0x40, 0x06, 0x3E,
- 0x08, 0x01, 0x87, 0x81, 0x00, 0x31, 0xF0, 0x20, 0x0C, 0x3E, 0x04, 0x01,
- 0x87, 0x81, 0x00, 0x60, 0xF0, 0x60, 0x18, 0x1E, 0x08, 0x03, 0x03, 0xC7,
- 0x00, 0xC0, 0x3F, 0xC0, 0x18, 0x03, 0xE0, 0x00, 0x7E, 0x00, 0x00, 0x7F,
- 0xE0, 0x00, 0x38, 0xF8, 0x00, 0x1E, 0x1F, 0x00, 0x07, 0x83, 0xC0, 0x01,
- 0xF0, 0xF0, 0x00, 0x7C, 0x38, 0x00, 0x1F, 0x9C, 0x00, 0x03, 0xFC, 0x00,
- 0x00, 0xFE, 0x0F, 0xF0, 0x3F, 0x80, 0xF0, 0x1F, 0xF0, 0x18, 0x1C, 0xFE,
- 0x0C, 0x0E, 0x1F, 0xC3, 0x07, 0x87, 0xF1, 0x81, 0xE0, 0xFE, 0x40, 0xF8,
- 0x1F, 0xF0, 0x3F, 0x07, 0xF8, 0x0F, 0xC0, 0xFE, 0x03, 0xF8, 0x1F, 0xC0,
- 0xFE, 0x07, 0xF8, 0x9F, 0xE3, 0xFF, 0xE7, 0xFF, 0x9F, 0xF0, 0xFF, 0xC3,
- 0xF8, 0x0F, 0x80, 0x3C, 0x00, 0x6F, 0xFF, 0xFF, 0x66, 0x66, 0x00, 0x81,
- 0x81, 0x81, 0x81, 0x80, 0xC0, 0xE0, 0x70, 0x70, 0x38, 0x3C, 0x1E, 0x0F,
- 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x0E, 0x07, 0x03, 0x80, 0xE0,
- 0x70, 0x18, 0x06, 0x01, 0x00, 0x40, 0x10, 0x04, 0x80, 0x30, 0x0C, 0x03,
- 0x00, 0xC0, 0x60, 0x38, 0x1C, 0x07, 0x03, 0x81, 0xC0, 0xF0, 0x78, 0x3C,
- 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xE0, 0x70, 0x38, 0x38, 0x1C, 0x0C,
- 0x0C, 0x06, 0x04, 0x04, 0x04, 0x00, 0x03, 0x00, 0x1E, 0x00, 0x78, 0x1D,
- 0xE6, 0xFB, 0x3D, 0xED, 0xF3, 0xFF, 0x01, 0xC0, 0x7F, 0xF3, 0xED, 0xFF,
- 0x33, 0xD9, 0xE6, 0x07, 0x80, 0x1E, 0x00, 0x30, 0x00, 0x00, 0xE0, 0x00,
- 0x1C, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00,
- 0x38, 0x00, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80,
- 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00,
- 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x73, 0xEF, 0xFF, 0xFD, 0xF0,
- 0xC2, 0x18, 0xC6, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0x7B, 0xFF, 0xFF, 0xFD,
- 0xE0, 0x00, 0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C,
- 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C,
- 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x00,
- 0x03, 0xC0, 0x0E, 0x70, 0x1E, 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x7C, 0x3E,
- 0x7C, 0x3E, 0x7C, 0x3E, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F,
- 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3E, 0x7C, 0x3E,
- 0x7C, 0x3E, 0x3C, 0x3C, 0x3C, 0x3C, 0x1E, 0x78, 0x0E, 0x70, 0x03, 0xC0,
- 0x00, 0xC0, 0x3C, 0x0F, 0xC3, 0xFC, 0x4F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC,
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- 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xF8, 0x3E, 0x07, 0x80, 0xF0, 0x1E, 0x03,
- 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x07, 0x87,
- 0x80, 0x1E, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78,
- 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF8, 0x0F, 0x80, 0x78, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0xF0, 0x0F, 0x80, 0xF0,
- 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F,
- 0x01, 0xE0, 0x3C, 0x03, 0xC0, 0x0F, 0x0F, 0x03, 0xC0, 0x78, 0x0F, 0x01,
- 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x03, 0xE0,
- 0xF8, 0x3C, 0x00, 0x3E, 0x00, 0x7F, 0xC6, 0xFF, 0xFF, 0x61, 0xFE, 0x00,
- 0x7C };
-
-const GFXglyph FreeSerifBold18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 9, 0, 1 }, // 0x20 ' '
- { 0, 6, 24, 12, 3, -23 }, // 0x21 '!'
- { 18, 13, 10, 19, 3, -23 }, // 0x22 '"'
- { 35, 18, 24, 17, 0, -23 }, // 0x23 '#'
- { 89, 15, 28, 17, 1, -25 }, // 0x24 '$'
- { 142, 27, 24, 35, 4, -23 }, // 0x25 '%'
- { 223, 26, 25, 29, 2, -23 }, // 0x26 '&'
- { 305, 4, 10, 10, 3, -23 }, // 0x27 '''
- { 310, 9, 30, 12, 2, -23 }, // 0x28 '('
- { 344, 9, 30, 12, 1, -23 }, // 0x29 ')'
- { 378, 14, 15, 18, 2, -23 }, // 0x2A '*'
- { 405, 19, 19, 24, 2, -17 }, // 0x2B '+'
- { 451, 6, 12, 9, 1, -5 }, // 0x2C ','
- { 460, 8, 4, 12, 2, -9 }, // 0x2D '-'
- { 464, 6, 6, 9, 1, -5 }, // 0x2E '.'
- { 469, 11, 25, 10, -1, -23 }, // 0x2F '/'
- { 504, 16, 24, 18, 1, -23 }, // 0x30 '0'
- { 552, 12, 24, 18, 3, -23 }, // 0x31 '1'
- { 588, 16, 24, 17, 1, -23 }, // 0x32 '2'
- { 636, 16, 24, 18, 0, -23 }, // 0x33 '3'
- { 684, 15, 24, 18, 1, -23 }, // 0x34 '4'
- { 729, 15, 24, 18, 1, -23 }, // 0x35 '5'
- { 774, 16, 24, 18, 1, -23 }, // 0x36 '6'
- { 822, 16, 24, 17, 1, -23 }, // 0x37 '7'
- { 870, 16, 24, 17, 1, -23 }, // 0x38 '8'
- { 918, 16, 24, 18, 1, -23 }, // 0x39 '9'
- { 966, 6, 16, 12, 3, -15 }, // 0x3A ':'
- { 978, 7, 22, 12, 2, -15 }, // 0x3B ';'
- { 998, 19, 20, 24, 2, -18 }, // 0x3C '<'
- { 1046, 19, 12, 24, 2, -14 }, // 0x3D '='
- { 1075, 19, 20, 24, 3, -18 }, // 0x3E '>'
- { 1123, 14, 24, 18, 2, -23 }, // 0x3F '?'
- { 1165, 24, 25, 33, 4, -23 }, // 0x40 '@'
- { 1240, 24, 24, 25, 1, -23 }, // 0x41 'A'
- { 1312, 21, 24, 23, 1, -23 }, // 0x42 'B'
- { 1375, 23, 25, 25, 1, -23 }, // 0x43 'C'
- { 1447, 23, 24, 26, 1, -23 }, // 0x44 'D'
- { 1516, 21, 24, 23, 2, -23 }, // 0x45 'E'
- { 1579, 19, 24, 22, 2, -23 }, // 0x46 'F'
- { 1636, 25, 25, 27, 1, -23 }, // 0x47 'G'
- { 1715, 24, 24, 27, 2, -23 }, // 0x48 'H'
- { 1787, 11, 24, 14, 2, -23 }, // 0x49 'I'
- { 1820, 16, 27, 18, 0, -23 }, // 0x4A 'J'
- { 1874, 25, 24, 27, 2, -23 }, // 0x4B 'K'
- { 1949, 21, 24, 23, 2, -23 }, // 0x4C 'L'
- { 2012, 31, 24, 33, 1, -23 }, // 0x4D 'M'
- { 2105, 23, 24, 25, 1, -23 }, // 0x4E 'N'
- { 2174, 25, 25, 27, 1, -23 }, // 0x4F 'O'
- { 2253, 19, 24, 22, 2, -23 }, // 0x50 'P'
- { 2310, 25, 30, 27, 1, -23 }, // 0x51 'Q'
- { 2404, 23, 24, 25, 2, -23 }, // 0x52 'R'
- { 2473, 16, 25, 20, 2, -23 }, // 0x53 'S'
- { 2523, 21, 24, 23, 1, -23 }, // 0x54 'T'
- { 2586, 22, 25, 25, 2, -23 }, // 0x55 'U'
- { 2655, 24, 24, 25, 0, -23 }, // 0x56 'V'
- { 2727, 34, 25, 34, 0, -23 }, // 0x57 'W'
- { 2834, 24, 24, 25, 1, -23 }, // 0x58 'X'
- { 2906, 24, 24, 25, 1, -23 }, // 0x59 'Y'
- { 2978, 21, 24, 23, 1, -23 }, // 0x5A 'Z'
- { 3041, 8, 29, 12, 2, -23 }, // 0x5B '['
- { 3070, 11, 25, 10, -1, -23 }, // 0x5C '\'
- { 3105, 8, 29, 12, 2, -23 }, // 0x5D ']'
- { 3134, 15, 13, 20, 3, -23 }, // 0x5E '^'
- { 3159, 18, 3, 17, 0, 3 }, // 0x5F '_'
- { 3166, 8, 6, 12, 0, -23 }, // 0x60 '`'
- { 3172, 16, 16, 18, 1, -15 }, // 0x61 'a'
- { 3204, 18, 24, 19, 1, -23 }, // 0x62 'b'
- { 3258, 14, 16, 15, 1, -15 }, // 0x63 'c'
- { 3286, 18, 24, 19, 1, -23 }, // 0x64 'd'
- { 3340, 14, 16, 16, 1, -15 }, // 0x65 'e'
- { 3368, 11, 24, 14, 2, -23 }, // 0x66 'f'
- { 3401, 17, 23, 17, 1, -15 }, // 0x67 'g'
- { 3450, 17, 24, 19, 1, -23 }, // 0x68 'h'
- { 3501, 7, 24, 10, 2, -23 }, // 0x69 'i'
- { 3522, 11, 31, 14, 0, -23 }, // 0x6A 'j'
- { 3565, 18, 24, 19, 1, -23 }, // 0x6B 'k'
- { 3619, 7, 24, 10, 1, -23 }, // 0x6C 'l'
- { 3640, 27, 16, 29, 1, -15 }, // 0x6D 'm'
- { 3694, 17, 16, 19, 1, -15 }, // 0x6E 'n'
- { 3728, 17, 16, 18, 1, -15 }, // 0x6F 'o'
- { 3762, 19, 23, 19, 0, -15 }, // 0x70 'p'
- { 3817, 17, 23, 19, 1, -15 }, // 0x71 'q'
- { 3866, 13, 16, 15, 1, -15 }, // 0x72 'r'
- { 3892, 12, 16, 14, 1, -15 }, // 0x73 's'
- { 3916, 10, 21, 12, 1, -20 }, // 0x74 't'
- { 3943, 18, 16, 20, 1, -15 }, // 0x75 'u'
- { 3979, 17, 16, 17, 0, -15 }, // 0x76 'v'
- { 4013, 24, 16, 25, 0, -15 }, // 0x77 'w'
- { 4061, 16, 16, 18, 1, -15 }, // 0x78 'x'
- { 4093, 16, 23, 17, 0, -15 }, // 0x79 'y'
- { 4139, 14, 16, 16, 0, -15 }, // 0x7A 'z'
- { 4167, 11, 31, 14, 1, -24 }, // 0x7B '{'
- { 4210, 3, 25, 8, 2, -23 }, // 0x7C '|'
- { 4220, 11, 31, 14, 3, -24 }, // 0x7D '}'
- { 4263, 16, 5, 18, 1, -11 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBold18pt7b PROGMEM = {
- (uint8_t *)FreeSerifBold18pt7bBitmaps,
- (GFXglyph *)FreeSerifBold18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 4945 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold24pt7b.h
deleted file mode 100644
index 0eb2d0b..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold24pt7b.h
+++ /dev/null
@@ -1,759 +0,0 @@
-const uint8_t FreeSerifBold24pt7bBitmaps[] PROGMEM = {
- 0x3C, 0x7E, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x7E, 0x7C, 0x7C,
- 0x3C, 0x3C, 0x38, 0x38, 0x38, 0x38, 0x18, 0x10, 0x10, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x3C, 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x3C, 0x70, 0x07,
- 0x7C, 0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xC0,
- 0x3E, 0xE0, 0x0E, 0x70, 0x07, 0x38, 0x03, 0x9C, 0x01, 0xC4, 0x00, 0xE2,
- 0x00, 0x20, 0x00, 0xF0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x0F,
- 0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x00, 0x78, 0x3C, 0x00, 0xF0,
- 0x78, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF,
- 0xF3, 0xFF, 0xFF, 0xE0, 0x78, 0x3C, 0x00, 0xF0, 0x78, 0x01, 0xC0, 0xE0,
- 0x03, 0x81, 0xC0, 0x0F, 0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x0F,
- 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0x03, 0x81, 0xC0, 0x0F,
- 0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x00, 0x78, 0x3C, 0x00, 0xF0,
- 0x78, 0x01, 0xE0, 0xE0, 0x03, 0x81, 0xC0, 0x07, 0x07, 0x80, 0x1E, 0x0F,
- 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00,
- 0x7F, 0xF0, 0x0F, 0x37, 0xE0, 0xE1, 0x8F, 0x8E, 0x0C, 0x3C, 0x70, 0x60,
- 0xE7, 0x83, 0x03, 0x3C, 0x18, 0x19, 0xF0, 0xC0, 0x4F, 0xC6, 0x02, 0x7F,
- 0xF0, 0x03, 0xFF, 0x80, 0x0F, 0xFE, 0x00, 0x3F, 0xFC, 0x00, 0xFF, 0xF0,
- 0x03, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x1F, 0xFE, 0x00, 0x3F, 0xF8, 0x01,
- 0xFF, 0xC0, 0x0C, 0xFF, 0x00, 0x63, 0xFA, 0x03, 0x0F, 0xD0, 0x18, 0x3E,
- 0x80, 0xC1, 0xF6, 0x06, 0x0F, 0xB8, 0x30, 0x79, 0xC1, 0x87, 0xCF, 0x0C,
- 0x3C, 0x7E, 0x67, 0xC0, 0xFF, 0xF8, 0x00, 0xFE, 0x00, 0x00, 0xC0, 0x00,
- 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x30,
- 0x00, 0x3E, 0x00, 0x0C, 0x00, 0x0F, 0xF0, 0x03, 0x80, 0x07, 0xE7, 0x03,
- 0xE0, 0x01, 0xF8, 0x7F, 0xFC, 0x00, 0x3E, 0x07, 0xF7, 0x00, 0x0F, 0xC0,
- 0x80, 0xE0, 0x03, 0xF0, 0x10, 0x38, 0x00, 0x7E, 0x02, 0x07, 0x00, 0x0F,
- 0x80, 0x41, 0xC0, 0x03, 0xF0, 0x10, 0x30, 0x00, 0x7E, 0x02, 0x0E, 0x00,
- 0x0F, 0x80, 0xC1, 0x80, 0x01, 0xF0, 0x10, 0x70, 0x00, 0x3E, 0x06, 0x1C,
- 0x00, 0x07, 0xC1, 0x83, 0x80, 0x00, 0x7C, 0x60, 0xE0, 0x1F, 0x07, 0xF8,
- 0x18, 0x0F, 0xF8, 0x7C, 0x07, 0x07, 0xF1, 0x00, 0x00, 0xC1, 0xF8, 0x10,
- 0x00, 0x38, 0x3F, 0x02, 0x00, 0x06, 0x0F, 0xC0, 0x40, 0x01, 0xC3, 0xF0,
- 0x08, 0x00, 0x30, 0x7E, 0x01, 0x00, 0x0E, 0x1F, 0x80, 0x40, 0x03, 0x83,
- 0xF0, 0x08, 0x00, 0x60, 0x7E, 0x01, 0x00, 0x1C, 0x0F, 0x80, 0x40, 0x03,
- 0x01, 0xF0, 0x18, 0x00, 0xE0, 0x3E, 0x02, 0x00, 0x18, 0x03, 0xC0, 0xC0,
- 0x07, 0x00, 0x7C, 0x70, 0x00, 0xC0, 0x07, 0xFC, 0x00, 0x38, 0x00, 0x7E,
- 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x0F, 0xFE, 0x00, 0x00, 0x07, 0x8F,
- 0xE0, 0x00, 0x03, 0xC1, 0xF8, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x7C,
- 0x07, 0xC0, 0x00, 0x1F, 0x01, 0xF0, 0x00, 0x07, 0xE0, 0x7C, 0x00, 0x01,
- 0xF8, 0x1E, 0x00, 0x00, 0x7F, 0x07, 0x80, 0x00, 0x1F, 0xE3, 0x80, 0x00,
- 0x03, 0xFF, 0xC0, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x00, 0x1F, 0xE0, 0x3F,
- 0xF0, 0x07, 0xFC, 0x01, 0xF0, 0x07, 0xFF, 0x00, 0x78, 0x07, 0xBF, 0xE0,
- 0x1C, 0x03, 0x87, 0xFC, 0x07, 0x01, 0xE0, 0xFF, 0x81, 0x80, 0xF0, 0x3F,
- 0xE0, 0xC0, 0x7C, 0x07, 0xFC, 0x30, 0x1F, 0x00, 0xFF, 0x98, 0x0F, 0xC0,
- 0x3F, 0xFC, 0x03, 0xF0, 0x07, 0xFF, 0x00, 0xFE, 0x00, 0xFF, 0x80, 0x3F,
- 0x80, 0x3F, 0xF0, 0x0F, 0xF0, 0x07, 0xFE, 0x03, 0xFC, 0x00, 0xFF, 0x81,
- 0x7F, 0x80, 0x3F, 0xF8, 0xDF, 0xF0, 0x1F, 0xFF, 0xE3, 0xFF, 0x0E, 0xFF,
- 0xF8, 0xFF, 0xFE, 0x1F, 0xFC, 0x0F, 0xFE, 0x03, 0xFE, 0x00, 0xFE, 0x00,
- 0x3E, 0x00, 0x77, 0xFF, 0xFF, 0xFF, 0xEE, 0x73, 0x9C, 0xE2, 0x00, 0x00,
- 0x00, 0x03, 0x00, 0x60, 0x1C, 0x03, 0x80, 0x70, 0x06, 0x00, 0xE0, 0x1C,
- 0x01, 0xC0, 0x3C, 0x03, 0xC0, 0x78, 0x07, 0x80, 0x78, 0x07, 0x80, 0xF8,
- 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8,
- 0x0F, 0x80, 0x78, 0x07, 0x80, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xC0, 0x1C,
- 0x00, 0xE0, 0x0E, 0x00, 0x70, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x03, 0x00,
- 0x10, 0x00, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x06, 0x00,
- 0x70, 0x03, 0x80, 0x38, 0x03, 0xC0, 0x3C, 0x03, 0xE0, 0x1E, 0x01, 0xE0,
- 0x1E, 0x01, 0xF0, 0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xF0,
- 0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x3C, 0x03, 0xC0,
- 0x38, 0x03, 0x80, 0x70, 0x07, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x0C,
- 0x00, 0x80, 0x00, 0x01, 0xC0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80,
- 0x03, 0xE0, 0x3C, 0x78, 0xEF, 0x9C, 0x7B, 0xF7, 0x3F, 0xFE, 0xDF, 0x8F,
- 0xFF, 0xC0, 0x7F, 0x00, 0x3F, 0xC0, 0x7E, 0xBF, 0x3F, 0x77, 0xEF, 0x9C,
- 0xFF, 0xC7, 0x1E, 0x63, 0xE3, 0x80, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80,
- 0x01, 0xC0, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x01, 0xE0,
- 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x01,
- 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x0F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07,
- 0x80, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00,
- 0x07, 0x80, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00,
- 0x00, 0x3C, 0x7E, 0xFE, 0xFF, 0xFF, 0xFF, 0x7F, 0x07, 0x06, 0x06, 0x0C,
- 0x18, 0x30, 0x60, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x3C,
- 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x3C, 0x00, 0x1E, 0x00, 0x7C, 0x00,
- 0xF0, 0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0,
- 0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x01,
- 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x01, 0xE0,
- 0x03, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xE0, 0x03,
- 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0x00, 0xFC, 0x00,
- 0x0F, 0x3C, 0x00, 0x78, 0x78, 0x03, 0xE1, 0xF0, 0x1F, 0x03, 0xE0, 0x7C,
- 0x0F, 0x83, 0xF0, 0x3F, 0x0F, 0xC0, 0xFC, 0x7F, 0x03, 0xF9, 0xFC, 0x0F,
- 0xE7, 0xF0, 0x3F, 0xBF, 0xC0, 0xFE, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF,
- 0xF0, 0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0,
- 0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0, 0x3F,
- 0x9F, 0xC0, 0xFE, 0x7F, 0x03, 0xF9, 0xFC, 0x0F, 0xE3, 0xF0, 0x3F, 0x0F,
- 0xC0, 0xFC, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x80, 0xF8, 0x7C, 0x01, 0xE1,
- 0xE0, 0x03, 0xCF, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x18, 0x00, 0x1E, 0x00,
- 0x1F, 0x80, 0x1F, 0xE0, 0x1F, 0xF8, 0x1D, 0xFE, 0x00, 0x3F, 0x80, 0x0F,
- 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8,
- 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00,
- 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F,
- 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8,
- 0x00, 0xFE, 0x00, 0x7F, 0x80, 0x3F, 0xF8, 0xFF, 0xFF, 0xC0, 0x00, 0xFC,
- 0x00, 0x1F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x81, 0xFF, 0xFC, 0x1C,
- 0x1F, 0xF1, 0xC0, 0x7F, 0x8C, 0x01, 0xFC, 0x40, 0x0F, 0xE0, 0x00, 0x3F,
- 0x00, 0x01, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00,
- 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x00,
- 0x00, 0x70, 0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x38,
- 0x01, 0x03, 0x80, 0x18, 0x38, 0x00, 0x81, 0x80, 0x1C, 0x1F, 0xFF, 0xE1,
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- 0xFE, 0x7F, 0xF0, 0x3F, 0xC3, 0xFF, 0x1F, 0x81, 0xFC, 0x0F, 0xE0, 0x7E,
- 0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x7E, 0x03, 0xF0, 0x1F, 0x83, 0xF0, 0x1F,
- 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x07, 0xE0, 0xFC, 0x07, 0xE0, 0x3F, 0x07,
- 0xE0, 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x0F, 0xC1, 0xF8, 0x0F, 0xC0,
- 0x7E, 0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x7E, 0x03, 0xF0, 0x1F, 0x83, 0xF0,
- 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x07, 0xE0, 0xFC, 0x07, 0xE0, 0x3F,
- 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x0F, 0xC1, 0xF8, 0x0F,
- 0xC0, 0x7E, 0x1F, 0xE0, 0xFF, 0x07, 0xFB, 0xFF, 0x8F, 0xFC, 0x7F, 0xE0,
- 0x00, 0x07, 0xE0, 0xFF, 0x9F, 0xF0, 0x3F, 0xBF, 0xF8, 0x1F, 0xF1, 0xF8,
- 0x1F, 0xC0, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,
- 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,
- 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,
- 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,
- 0x1F, 0x80, 0xFC, 0x3F, 0xC1, 0xFE, 0xFF, 0xE3, 0xFF, 0x01, 0xFC, 0x00,
- 0x3F, 0xF8, 0x03, 0xE3, 0xE0, 0x3E, 0x0F, 0x83, 0xF0, 0x7E, 0x1F, 0x01,
- 0xF1, 0xF8, 0x0F, 0xCF, 0xC0, 0x7E, 0xFE, 0x03, 0xFF, 0xF0, 0x1F, 0xFF,
- 0x80, 0xFF, 0xFC, 0x07, 0xFF, 0xE0, 0x3F, 0xFF, 0x01, 0xFF, 0xF8, 0x0F,
- 0xFF, 0xC0, 0x7F, 0x7E, 0x03, 0xF3, 0xF0, 0x1F, 0x8F, 0x80, 0xF8, 0x7E,
- 0x0F, 0xC1, 0xF0, 0x7C, 0x07, 0xC7, 0xC0, 0x1F, 0xFC, 0x00, 0x3F, 0x80,
- 0x00, 0x0F, 0xC0, 0xFF, 0xBF, 0xF0, 0x3F, 0xF1, 0xF8, 0x1F, 0xC0, 0xFC,
- 0x1F, 0xC0, 0xFC, 0x1F, 0x80, 0xFE, 0x1F, 0x80, 0x7E, 0x1F, 0x80, 0x7F,
- 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F,
- 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F,
- 0x1F, 0x80, 0x7E, 0x1F, 0x80, 0x7E, 0x1F, 0x80, 0xFE, 0x1F, 0x80, 0xFC,
- 0x1F, 0xC1, 0xF8, 0x1F, 0xE3, 0xF8, 0x1F, 0xBF, 0xE0, 0x1F, 0x8F, 0xC0,
- 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00,
- 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0xF8, 0x00,
- 0x00, 0xF8, 0x08, 0x07, 0xFE, 0x18, 0x0F, 0xC7, 0x38, 0x1F, 0x83, 0xF8,
- 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0x7E, 0x01, 0xF8,
- 0x7E, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8,
- 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8,
- 0xFE, 0x01, 0xF8, 0x7E, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0x7F, 0x01, 0xF8,
- 0x3F, 0x83, 0xF8, 0x1F, 0xC7, 0xF8, 0x0F, 0xFD, 0xF8, 0x03, 0xF1, 0xF8,
- 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8,
- 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xFF,
- 0x00, 0x07, 0x9F, 0xF3, 0xF8, 0xFE, 0xFF, 0x8F, 0xFF, 0xF1, 0xFE, 0x7E,
- 0x3F, 0x87, 0x87, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00,
- 0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xE0, 0x00,
- 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01,
- 0xF8, 0x00, 0x7F, 0x80, 0x3F, 0xFC, 0x00, 0x0F, 0x84, 0x3F, 0xF8, 0xE1,
- 0xF3, 0x80, 0xEF, 0x00, 0xDE, 0x01, 0xBE, 0x01, 0x7E, 0x00, 0xFF, 0x01,
- 0xFF, 0x81, 0xFF, 0xC3, 0xFF, 0xC3, 0xFF, 0xC1, 0xFF, 0x80, 0xFF, 0x80,
- 0x7F, 0x80, 0x7F, 0x80, 0x7F, 0x00, 0x7E, 0x00, 0xFE, 0x01, 0xDF, 0x0F,
- 0x37, 0xFC, 0x43, 0xF0, 0x01, 0x00, 0x0C, 0x00, 0x70, 0x01, 0xC0, 0x0F,
- 0x00, 0x7C, 0x03, 0xF0, 0x1F, 0xC0, 0xFF, 0xF3, 0xFF, 0xC3, 0xF0, 0x0F,
- 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03,
- 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00,
- 0xFC, 0x23, 0xF0, 0x8F, 0xE6, 0x1F, 0xF0, 0x7F, 0x80, 0xF8, 0x00, 0xFF,
- 0x87, 0xFC, 0x1F, 0xC0, 0xFE, 0x07, 0xE0, 0x3F, 0x03, 0xF0, 0x1F, 0x81,
- 0xF8, 0x0F, 0xC0, 0xFC, 0x07, 0xE0, 0x7E, 0x03, 0xF0, 0x3F, 0x01, 0xF8,
- 0x1F, 0x80, 0xFC, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x3F, 0x03, 0xF0, 0x1F,
- 0x81, 0xF8, 0x0F, 0xC0, 0xFC, 0x07, 0xE0, 0x7E, 0x03, 0xF0, 0x3F, 0x01,
- 0xF8, 0x1F, 0x80, 0xFC, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x7F, 0x03, 0xF8,
- 0x7F, 0xC0, 0xFF, 0xEF, 0xF8, 0x3F, 0xE7, 0xC0, 0x0F, 0xC2, 0x00, 0xFF,
- 0xF1, 0xFC, 0xFF, 0x01, 0xE3, 0xFC, 0x03, 0x07, 0xF0, 0x0C, 0x1F, 0xC0,
- 0x60, 0x3F, 0x81, 0x80, 0xFE, 0x04, 0x01, 0xF8, 0x30, 0x07, 0xF0, 0xC0,
- 0x1F, 0xC6, 0x00, 0x3F, 0x98, 0x00, 0xFE, 0x40, 0x01, 0xFB, 0x00, 0x07,
- 0xFC, 0x00, 0x1F, 0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFE, 0x00, 0x01, 0xF0,
- 0x00, 0x07, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00,
- 0x01, 0x00, 0x00, 0xFF, 0xE7, 0xFF, 0x3F, 0xBF, 0xE0, 0xFE, 0x07, 0x0F,
- 0xE0, 0x7F, 0x03, 0x83, 0xF0, 0x1F, 0x81, 0x81, 0xFC, 0x0F, 0xC0, 0xC0,
- 0xFE, 0x07, 0xF0, 0x40, 0x3F, 0x03, 0xF8, 0x60, 0x1F, 0xC3, 0xFC, 0x30,
- 0x07, 0xE1, 0xFE, 0x10, 0x03, 0xF0, 0x9F, 0x98, 0x01, 0xFC, 0xCF, 0xCC,
- 0x00, 0x7E, 0x67, 0xEC, 0x00, 0x3F, 0xE1, 0xFE, 0x00, 0x1F, 0xF0, 0xFE,
- 0x00, 0x07, 0xF0, 0x7F, 0x00, 0x03, 0xF8, 0x3F, 0x80, 0x00, 0xFC, 0x0F,
- 0x80, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x3E, 0x03, 0xE0, 0x00, 0x0F, 0x00,
- 0xE0, 0x00, 0x07, 0x00, 0x70, 0x00, 0x03, 0x80, 0x38, 0x00, 0x00, 0x80,
- 0x08, 0x00, 0xFF, 0xF3, 0xFD, 0xFF, 0x03, 0xC3, 0xFC, 0x0E, 0x07, 0xF0,
- 0x30, 0x1F, 0xE1, 0x80, 0x3F, 0x8C, 0x00, 0x7F, 0x70, 0x01, 0xFF, 0x80,
- 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0xE0, 0x00, 0x3F, 0x80, 0x00,
- 0xFF, 0x00, 0x07, 0xFE, 0x00, 0x1B, 0xF8, 0x00, 0xCF, 0xF0, 0x06, 0x1F,
- 0xC0, 0x38, 0x3F, 0x80, 0xC0, 0xFF, 0x07, 0x01, 0xFC, 0x3C, 0x07, 0xFB,
- 0xFC, 0x7F, 0xF0, 0xFF, 0xE3, 0xFB, 0xFC, 0x07, 0x8F, 0xE0, 0x18, 0x7F,
- 0x01, 0x81, 0xF8, 0x0C, 0x0F, 0xE0, 0x60, 0x7F, 0x06, 0x01, 0xF8, 0x30,
- 0x0F, 0xE1, 0x80, 0x7F, 0x18, 0x01, 0xF8, 0xC0, 0x0F, 0xE6, 0x00, 0x3F,
- 0x60, 0x01, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xFC, 0x00,
- 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0x00, 0x00, 0x38,
- 0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x03, 0x82, 0x00, 0x3E,
- 0x30, 0x01, 0xF1, 0x00, 0x0F, 0x98, 0x00, 0x3F, 0x80, 0x00, 0xF0, 0x00,
- 0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xFD, 0xE0, 0x7F, 0x30, 0x1F, 0xC6, 0x07,
- 0xF8, 0x80, 0xFE, 0x00, 0x3F, 0xC0, 0x07, 0xF0, 0x01, 0xFC, 0x00, 0x3F,
- 0x80, 0x0F, 0xE0, 0x03, 0xFC, 0x00, 0x7F, 0x00, 0x1F, 0xE0, 0x03, 0xF8,
- 0x00, 0xFE, 0x03, 0x3F, 0xC0, 0x67, 0xF0, 0x19, 0xFE, 0x07, 0x3F, 0x83,
- 0xEF, 0xFF, 0xFD, 0xFF, 0xFF, 0x80, 0x00, 0x7C, 0x07, 0xE0, 0x3E, 0x00,
- 0xF8, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00,
- 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0,
- 0x1F, 0x00, 0xF8, 0x03, 0xC0, 0x3C, 0x01, 0xF0, 0x00, 0xF0, 0x03, 0xE0,
- 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C,
- 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F,
- 0x00, 0x3E, 0x00, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF0, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x3E, 0x00,
- 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80,
- 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0x7C, 0x00, 0xF0,
- 0x00, 0xF0, 0x03, 0xE0, 0x3C, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x00, 0xF8,
- 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,
- 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x01, 0xF0, 0x07, 0xC0, 0x7E,
- 0x03, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0xC0, 0x47, 0xFF, 0xC3, 0x9F,
- 0xFF, 0xFF, 0x70, 0x7F, 0xF8, 0x80, 0x7F, 0xC0, 0x00, 0x3E, 0x00 };
-
-const GFXglyph FreeSerifBold24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 12, 0, 1 }, // 0x20 ' '
- { 0, 8, 34, 16, 4, -32 }, // 0x21 '!'
- { 34, 17, 13, 26, 4, -32 }, // 0x22 '"'
- { 62, 23, 33, 23, 0, -32 }, // 0x23 '#'
- { 157, 21, 39, 24, 1, -34 }, // 0x24 '$'
- { 260, 35, 34, 47, 6, -32 }, // 0x25 '%'
- { 409, 34, 34, 39, 3, -32 }, // 0x26 '&'
- { 554, 5, 13, 13, 4, -32 }, // 0x27 '''
- { 563, 12, 41, 16, 2, -32 }, // 0x28 '('
- { 625, 12, 41, 16, 1, -32 }, // 0x29 ')'
- { 687, 18, 21, 24, 3, -32 }, // 0x2A '*'
- { 735, 26, 25, 32, 3, -24 }, // 0x2B '+'
- { 817, 8, 15, 12, 2, -6 }, // 0x2C ','
- { 832, 11, 5, 16, 2, -12 }, // 0x2D '-'
- { 839, 8, 8, 12, 2, -6 }, // 0x2E '.'
- { 847, 15, 33, 13, -1, -32 }, // 0x2F '/'
- { 909, 22, 34, 23, 1, -32 }, // 0x30 '0'
- { 1003, 18, 33, 23, 3, -32 }, // 0x31 '1'
- { 1078, 21, 33, 24, 1, -32 }, // 0x32 '2'
- { 1165, 21, 34, 24, 1, -32 }, // 0x33 '3'
- { 1255, 21, 33, 24, 1, -32 }, // 0x34 '4'
- { 1342, 20, 32, 23, 2, -31 }, // 0x35 '5'
- { 1422, 21, 34, 24, 1, -32 }, // 0x36 '6'
- { 1512, 21, 32, 23, 1, -31 }, // 0x37 '7'
- { 1596, 21, 34, 23, 1, -32 }, // 0x38 '8'
- { 1686, 22, 34, 23, 1, -32 }, // 0x39 '9'
- { 1780, 8, 24, 16, 4, -22 }, // 0x3A ':'
- { 1804, 9, 31, 16, 3, -22 }, // 0x3B ';'
- { 1839, 26, 26, 32, 3, -24 }, // 0x3C '<'
- { 1924, 26, 17, 32, 3, -20 }, // 0x3D '='
- { 1980, 26, 26, 32, 3, -24 }, // 0x3E '>'
- { 2065, 18, 34, 24, 3, -32 }, // 0x3F '?'
- { 2142, 33, 34, 44, 5, -32 }, // 0x40 '@'
- { 2283, 32, 33, 34, 1, -32 }, // 0x41 'A'
- { 2415, 28, 32, 31, 1, -31 }, // 0x42 'B'
- { 2527, 30, 34, 33, 2, -32 }, // 0x43 'C'
- { 2655, 32, 32, 34, 1, -31 }, // 0x44 'D'
- { 2783, 28, 32, 32, 2, -31 }, // 0x45 'E'
- { 2895, 25, 32, 29, 2, -31 }, // 0x46 'F'
- { 2995, 33, 34, 36, 2, -32 }, // 0x47 'G'
- { 3136, 33, 32, 37, 2, -31 }, // 0x48 'H'
- { 3268, 15, 32, 18, 2, -31 }, // 0x49 'I'
- { 3328, 22, 37, 24, 0, -31 }, // 0x4A 'J'
- { 3430, 34, 32, 36, 2, -31 }, // 0x4B 'K'
- { 3566, 28, 32, 31, 2, -31 }, // 0x4C 'L'
- { 3678, 43, 32, 45, 0, -31 }, // 0x4D 'M'
- { 3850, 31, 32, 34, 1, -31 }, // 0x4E 'N'
- { 3974, 33, 34, 37, 2, -32 }, // 0x4F 'O'
- { 4115, 26, 32, 30, 2, -31 }, // 0x50 'P'
- { 4219, 33, 41, 37, 2, -32 }, // 0x51 'Q'
- { 4389, 31, 32, 34, 2, -31 }, // 0x52 'R'
- { 4513, 21, 34, 27, 3, -32 }, // 0x53 'S'
- { 4603, 28, 32, 30, 1, -31 }, // 0x54 'T'
- { 4715, 30, 33, 34, 2, -31 }, // 0x55 'U'
- { 4839, 33, 32, 33, 0, -31 }, // 0x56 'V'
- { 4971, 45, 33, 46, 1, -31 }, // 0x57 'W'
- { 5157, 32, 32, 34, 1, -31 }, // 0x58 'X'
- { 5285, 32, 32, 33, 1, -31 }, // 0x59 'Y'
- { 5413, 28, 32, 30, 1, -31 }, // 0x5A 'Z'
- { 5525, 11, 39, 16, 3, -31 }, // 0x5B '['
- { 5579, 15, 33, 13, -1, -32 }, // 0x5C '\'
- { 5641, 11, 39, 16, 2, -31 }, // 0x5D ']'
- { 5695, 21, 17, 27, 3, -31 }, // 0x5E '^'
- { 5740, 24, 3, 23, 0, 5 }, // 0x5F '_'
- { 5749, 11, 9, 16, 0, -33 }, // 0x60 '`'
- { 5762, 22, 24, 23, 1, -22 }, // 0x61 'a'
- { 5828, 25, 33, 26, 0, -31 }, // 0x62 'b'
- { 5932, 19, 24, 20, 1, -22 }, // 0x63 'c'
- { 5989, 24, 33, 26, 1, -31 }, // 0x64 'd'
- { 6088, 18, 24, 21, 1, -22 }, // 0x65 'e'
- { 6142, 17, 33, 18, 1, -32 }, // 0x66 'f'
- { 6213, 19, 32, 24, 2, -22 }, // 0x67 'g'
- { 6289, 24, 32, 26, 0, -31 }, // 0x68 'h'
- { 6385, 11, 33, 14, 1, -32 }, // 0x69 'i'
- { 6431, 14, 42, 18, 0, -32 }, // 0x6A 'j'
- { 6505, 25, 32, 26, 0, -31 }, // 0x6B 'k'
- { 6605, 11, 32, 13, 0, -31 }, // 0x6C 'l'
- { 6649, 37, 23, 39, 0, -22 }, // 0x6D 'm'
- { 6756, 24, 23, 26, 0, -22 }, // 0x6E 'n'
- { 6825, 21, 24, 24, 1, -22 }, // 0x6F 'o'
- { 6888, 24, 32, 26, 0, -22 }, // 0x70 'p'
- { 6984, 24, 32, 26, 1, -22 }, // 0x71 'q'
- { 7080, 19, 23, 20, 0, -22 }, // 0x72 'r'
- { 7135, 15, 24, 19, 2, -22 }, // 0x73 's'
- { 7180, 14, 31, 16, 1, -29 }, // 0x74 't'
- { 7235, 25, 23, 27, 0, -21 }, // 0x75 'u'
- { 7307, 22, 23, 23, 0, -21 }, // 0x76 'v'
- { 7371, 33, 23, 33, 0, -21 }, // 0x77 'w'
- { 7466, 22, 22, 24, 1, -21 }, // 0x78 'x'
- { 7527, 21, 31, 23, 0, -21 }, // 0x79 'y'
- { 7609, 19, 22, 21, 1, -21 }, // 0x7A 'z'
- { 7662, 14, 42, 19, 1, -33 }, // 0x7B '{'
- { 7736, 4, 33, 10, 3, -32 }, // 0x7C '|'
- { 7753, 14, 42, 19, 4, -33 }, // 0x7D '}'
- { 7827, 22, 7, 24, 1, -14 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBold24pt7b PROGMEM = {
- (uint8_t *)FreeSerifBold24pt7bBitmaps,
- (GFXglyph *)FreeSerifBold24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 8519 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold9pt7b.h
deleted file mode 100644
index 52dbe36..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBold9pt7b.h
+++ /dev/null
@@ -1,202 +0,0 @@
-const uint8_t FreeSerifBold9pt7bBitmaps[] PROGMEM = {
- 0xFF, 0xF4, 0x92, 0x1F, 0xF0, 0xCF, 0x3C, 0xE3, 0x88, 0x13, 0x09, 0x84,
- 0xC2, 0x47, 0xF9, 0x90, 0xC8, 0x4C, 0xFF, 0x13, 0x09, 0x0C, 0x86, 0x40,
- 0x10, 0x38, 0xD6, 0x92, 0xD2, 0xF0, 0x7C, 0x3E, 0x17, 0x93, 0x93, 0xD6,
- 0x7C, 0x10, 0x3C, 0x21, 0xCF, 0x0E, 0x24, 0x30, 0xA0, 0xC5, 0x03, 0x34,
- 0xE7, 0x26, 0x40, 0xB9, 0x04, 0xC4, 0x23, 0x30, 0x8C, 0x84, 0x1C, 0x0F,
- 0x00, 0xCC, 0x06, 0x60, 0x3E, 0x00, 0xE7, 0x8F, 0x18, 0x9C, 0x8C, 0xE4,
- 0xE3, 0xC7, 0x9E, 0x3C, 0x72, 0xFD, 0xE0, 0xFF, 0x80, 0x32, 0x44, 0xCC,
- 0xCC, 0xCC, 0xC4, 0x62, 0x10, 0x84, 0x22, 0x33, 0x33, 0x33, 0x32, 0x64,
- 0x80, 0x31, 0x6B, 0xB1, 0x8E, 0xD6, 0x8C, 0x00, 0x08, 0x04, 0x02, 0x01,
- 0x0F, 0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0xDF, 0x95, 0x00, 0xFF, 0xFF,
- 0x80, 0x0C, 0x21, 0x86, 0x10, 0xC3, 0x08, 0x61, 0x84, 0x30, 0xC0, 0x1C,
- 0x33, 0x98, 0xDC, 0x7E, 0x3F, 0x1F, 0x8F, 0xC7, 0xE3, 0xB1, 0x98, 0xC3,
- 0x80, 0x08, 0xE3, 0x8E, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0xBF, 0x3C, 0x3F,
- 0x23, 0xC0, 0xE0, 0x70, 0x30, 0x38, 0x18, 0x18, 0x18, 0x5F, 0xDF, 0xE0,
- 0x7C, 0x8E, 0x0E, 0x0E, 0x0C, 0x1E, 0x07, 0x03, 0x03, 0x02, 0xE6, 0xF8,
- 0x06, 0x0E, 0x0E, 0x3E, 0x2E, 0x4E, 0x8E, 0x8E, 0xFF, 0xFF, 0x0E, 0x0E,
- 0x3F, 0x7E, 0x40, 0x40, 0xF8, 0xFC, 0x1E, 0x06, 0x02, 0x02, 0xE4, 0xF8,
- 0x07, 0x1C, 0x30, 0x70, 0xFC, 0xE6, 0xE7, 0xE7, 0xE7, 0x67, 0x66, 0x3C,
- 0x7F, 0x3F, 0xA0, 0xD0, 0x40, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x04, 0x06,
- 0x03, 0x00, 0x3C, 0xC6, 0xC6, 0xC6, 0xFC, 0x7C, 0x3E, 0xCF, 0xC7, 0xC7,
- 0xC6, 0x7C, 0x3E, 0x33, 0xB8, 0xDC, 0x7E, 0x3F, 0x1D, 0xCE, 0x7F, 0x07,
- 0x07, 0x0F, 0x1C, 0x00, 0xFF, 0x80, 0x3F, 0xE0, 0xFF, 0x80, 0x37, 0xE5,
- 0x40, 0x00, 0x00, 0x70, 0x78, 0x78, 0x78, 0x38, 0x03, 0x80, 0x3C, 0x03,
- 0xC0, 0x30, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xC0, 0x3C, 0x03,
- 0xC0, 0x1C, 0x01, 0xC1, 0xE1, 0xE1, 0xE0, 0xE0, 0x00, 0x00, 0x3D, 0x9F,
- 0x3E, 0x70, 0xE1, 0x04, 0x08, 0x00, 0x70, 0xE1, 0xC0, 0x0F, 0x81, 0x83,
- 0x18, 0xC4, 0x89, 0x9C, 0x4C, 0xE4, 0x67, 0x22, 0x39, 0x22, 0x4F, 0xE3,
- 0x00, 0x0C, 0x10, 0x1F, 0x00, 0x02, 0x00, 0x30, 0x01, 0xC0, 0x0E, 0x00,
- 0xB8, 0x05, 0xC0, 0x4F, 0x02, 0x38, 0x3F, 0xE1, 0x07, 0x18, 0x3D, 0xE3,
- 0xF0, 0xFF, 0x87, 0x1C, 0xE3, 0x9C, 0x73, 0x9C, 0x7F, 0x0E, 0x71, 0xC7,
- 0x38, 0xE7, 0x1C, 0xE7, 0x7F, 0xC0, 0x1F, 0x26, 0x1D, 0xC1, 0xB0, 0x1E,
- 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x0E, 0x04, 0xE1, 0x0F, 0xC0, 0xFF,
- 0x0E, 0x71, 0xC7, 0x38, 0x77, 0x0E, 0xE1, 0xDC, 0x3B, 0x87, 0x70, 0xCE,
- 0x39, 0xC6, 0x7F, 0x80, 0xFF, 0xCE, 0x19, 0xC1, 0x38, 0x87, 0x30, 0xFE,
- 0x1C, 0xC3, 0x88, 0x70, 0x2E, 0x0D, 0xC3, 0x7F, 0xE0, 0xFF, 0xDC, 0x37,
- 0x05, 0xC4, 0x73, 0x1F, 0xC7, 0x31, 0xC4, 0x70, 0x1C, 0x07, 0x03, 0xE0,
- 0x1F, 0x23, 0x0E, 0x70, 0x6E, 0x02, 0xE0, 0x0E, 0x00, 0xE1, 0xFE, 0x0E,
- 0x60, 0xE7, 0x0E, 0x38, 0xE0, 0xF8, 0xF9, 0xF7, 0x0E, 0x70, 0xE7, 0x0E,
- 0x70, 0xE7, 0xFE, 0x70, 0xE7, 0x0E, 0x70, 0xE7, 0x0E, 0x70, 0xEF, 0x9F,
- 0xFB, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0, 0x1F, 0x0E, 0x0E, 0x0E,
- 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0xCE, 0xCC, 0x78, 0xF9, 0xF3,
- 0x82, 0x1C, 0x20, 0xE2, 0x07, 0x20, 0x3F, 0x01, 0xDC, 0x0E, 0x70, 0x73,
- 0xC3, 0x8F, 0x1C, 0x3D, 0xF3, 0xF0, 0xF8, 0x0E, 0x01, 0xC0, 0x38, 0x07,
- 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x2E, 0x09, 0xC3, 0x7F, 0xE0, 0xF8,
- 0x0F, 0x3C, 0x1E, 0x3C, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x26, 0x4E, 0x27,
- 0x4E, 0x27, 0x4E, 0x23, 0x8E, 0x23, 0x8E, 0x21, 0x0E, 0x71, 0x1F, 0xF0,
- 0xEE, 0x09, 0xE1, 0x3E, 0x25, 0xE4, 0x9E, 0x91, 0xD2, 0x1E, 0x43, 0xC8,
- 0x39, 0x03, 0x70, 0x20, 0x1F, 0x83, 0x0C, 0x70, 0xEE, 0x07, 0xE0, 0x7E,
- 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x77, 0x0E, 0x30, 0xC1, 0xF8, 0xFF, 0x1C,
- 0xE7, 0x1D, 0xC7, 0x71, 0xDC, 0xE7, 0xF1, 0xC0, 0x70, 0x1C, 0x07, 0x03,
- 0xE0, 0x0F, 0x83, 0x9C, 0x70, 0xE6, 0x06, 0xE0, 0x7E, 0x07, 0xE0, 0x7E,
- 0x07, 0xE0, 0x76, 0x06, 0x30, 0xC1, 0x98, 0x0F, 0x00, 0x78, 0x03, 0xE0,
- 0xFF, 0x07, 0x38, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x38, 0x7E, 0x07, 0x70,
- 0x77, 0x87, 0x3C, 0x71, 0xEF, 0x8F, 0x39, 0x47, 0xC1, 0xC0, 0xF0, 0x7C,
- 0x3E, 0x0F, 0x83, 0xC3, 0xC6, 0xBC, 0xFF, 0xFC, 0xE3, 0x8E, 0x10, 0xE0,
- 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xF0,
- 0xF8, 0xEE, 0x09, 0xC1, 0x38, 0x27, 0x04, 0xE0, 0x9C, 0x13, 0x82, 0x70,
- 0x4E, 0x08, 0xE2, 0x0F, 0x80, 0xFC, 0x7B, 0xC1, 0x0E, 0x08, 0x70, 0x81,
- 0xC4, 0x0E, 0x20, 0x7A, 0x01, 0xD0, 0x0E, 0x80, 0x38, 0x01, 0xC0, 0x04,
- 0x00, 0x20, 0x00, 0xFD, 0xFB, 0xDC, 0x38, 0x43, 0x87, 0x10, 0xE1, 0xC4,
- 0x38, 0xF2, 0x07, 0x2E, 0x81, 0xD3, 0xA0, 0x34, 0x70, 0x0E, 0x1C, 0x03,
- 0x87, 0x00, 0x60, 0x80, 0x10, 0x20, 0xFE, 0xF3, 0xC3, 0x0F, 0x10, 0x39,
- 0x00, 0xF0, 0x03, 0x80, 0x1E, 0x01, 0x70, 0x09, 0xC0, 0x8F, 0x08, 0x3D,
- 0xF3, 0xF0, 0xFC, 0x7B, 0xC1, 0x8E, 0x08, 0x38, 0x81, 0xE8, 0x07, 0x40,
- 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x1F, 0x00, 0xFF, 0xD8,
- 0x72, 0x1E, 0x43, 0x80, 0xE0, 0x1C, 0x07, 0x01, 0xC0, 0x38, 0x2E, 0x0F,
- 0x83, 0x7F, 0xE0, 0xFC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xF0, 0xC1,
- 0x06, 0x18, 0x20, 0xC3, 0x04, 0x18, 0x60, 0x83, 0x0C, 0xF3, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33, 0xF0, 0x18, 0x1C, 0x34, 0x26, 0x62, 0x43, 0xC1,
- 0xFF, 0x80, 0xC6, 0x30, 0x7C, 0x63, 0xB1, 0xC0, 0xE1, 0xF3, 0x3B, 0x9D,
- 0xCE, 0xFF, 0x80, 0xF0, 0x1C, 0x07, 0x01, 0xDC, 0x7B, 0x9C, 0x77, 0x1D,
- 0xC7, 0x71, 0xDC, 0x77, 0x39, 0x3C, 0x3C, 0xED, 0x9F, 0x0E, 0x1C, 0x38,
- 0x39, 0x3C, 0x07, 0x80, 0xE0, 0x38, 0xEE, 0x77, 0xB8, 0xEE, 0x3B, 0x8E,
- 0xE3, 0xB8, 0xE7, 0x78, 0xEF, 0x3C, 0x66, 0xE6, 0xFE, 0xE0, 0xE0, 0xE0,
- 0x72, 0x3C, 0x3E, 0xED, 0xC7, 0xC7, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC7,
- 0xC0, 0x31, 0xDF, 0xBF, 0x7E, 0xE7, 0x90, 0x60, 0xFC, 0xFE, 0x0C, 0x17,
- 0xC0, 0xF0, 0x1C, 0x07, 0x01, 0xDC, 0x7B, 0x9C, 0xE7, 0x39, 0xCE, 0x73,
- 0x9C, 0xE7, 0x3B, 0xFF, 0x73, 0x9D, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0,
- 0x1C, 0x71, 0xCF, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x7D, 0xBE,
- 0xF0, 0x1C, 0x07, 0x01, 0xCE, 0x71, 0x1C, 0x87, 0x41, 0xF8, 0x77, 0x1C,
- 0xE7, 0x1B, 0xEF, 0xF3, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0, 0xF7,
- 0x38, 0xF7, 0xB9, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7,
- 0x39, 0xCE, 0xFF, 0xFE, 0xF7, 0x1E, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7,
- 0x39, 0xCE, 0xFF, 0xC0, 0x3E, 0x31, 0xB8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8E,
- 0xC6, 0x3E, 0x00, 0xF7, 0x1E, 0xE7, 0x1D, 0xC7, 0x71, 0xDC, 0x77, 0x1D,
- 0xCE, 0x7F, 0x1C, 0x07, 0x01, 0xC0, 0xF8, 0x00, 0x3C, 0x9C, 0xEE, 0x3B,
- 0x8E, 0xE3, 0xB8, 0xEE, 0x39, 0xCE, 0x3F, 0x80, 0xE0, 0x38, 0x0E, 0x07,
- 0xC0, 0xF7, 0x7B, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0xF8, 0x7E, 0x73,
- 0xC7, 0x8E, 0x39, 0xB0, 0x10, 0xCF, 0x9C, 0x71, 0xC7, 0x1C, 0x71, 0xD3,
- 0x80, 0xF7, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x3F,
- 0xC0, 0xFB, 0xB8, 0x8C, 0x87, 0x43, 0xC0, 0xE0, 0x70, 0x10, 0x08, 0x00,
- 0xF7, 0xB6, 0x31, 0x73, 0xA3, 0x3A, 0x3D, 0xA3, 0xDC, 0x18, 0xC1, 0x88,
- 0x10, 0x80, 0xFB, 0xB8, 0x8E, 0x83, 0x81, 0xC0, 0xF0, 0x98, 0xCE, 0xEF,
- 0x80, 0xF7, 0x62, 0x72, 0x34, 0x34, 0x3C, 0x18, 0x18, 0x10, 0x10, 0x10,
- 0xE0, 0xE0, 0xFF, 0x1C, 0x70, 0xE3, 0x87, 0x1C, 0x71, 0xFE, 0x19, 0x8C,
- 0x63, 0x18, 0xCC, 0x61, 0x8C, 0x63, 0x18, 0xC3, 0xFF, 0xF8, 0xC3, 0x18,
- 0xC6, 0x31, 0x86, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xF0, 0x8E };
-
-const GFXglyph FreeSerifBold9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 3, 12, 6, 1, -11 }, // 0x21 '!'
- { 5, 6, 5, 10, 2, -11 }, // 0x22 '"'
- { 9, 9, 13, 9, 0, -12 }, // 0x23 '#'
- { 24, 8, 14, 9, 1, -12 }, // 0x24 '$'
- { 38, 14, 12, 18, 2, -11 }, // 0x25 '%'
- { 59, 13, 12, 15, 1, -11 }, // 0x26 '&'
- { 79, 2, 5, 5, 1, -11 }, // 0x27 '''
- { 81, 4, 15, 6, 1, -11 }, // 0x28 '('
- { 89, 4, 15, 6, 1, -11 }, // 0x29 ')'
- { 97, 7, 7, 9, 2, -11 }, // 0x2A '*'
- { 104, 9, 9, 12, 1, -8 }, // 0x2B '+'
- { 115, 3, 6, 4, 1, -2 }, // 0x2C ','
- { 118, 4, 2, 6, 1, -4 }, // 0x2D '-'
- { 119, 3, 3, 4, 1, -2 }, // 0x2E '.'
- { 121, 6, 13, 5, 0, -11 }, // 0x2F '/'
- { 131, 9, 12, 9, 0, -11 }, // 0x30 '0'
- { 145, 6, 12, 9, 1, -11 }, // 0x31 '1'
- { 154, 9, 12, 9, 0, -11 }, // 0x32 '2'
- { 168, 8, 12, 9, 0, -11 }, // 0x33 '3'
- { 180, 8, 12, 9, 1, -11 }, // 0x34 '4'
- { 192, 8, 12, 9, 1, -11 }, // 0x35 '5'
- { 204, 8, 12, 9, 1, -11 }, // 0x36 '6'
- { 216, 9, 12, 9, 0, -11 }, // 0x37 '7'
- { 230, 8, 12, 9, 1, -11 }, // 0x38 '8'
- { 242, 9, 12, 9, 0, -11 }, // 0x39 '9'
- { 256, 3, 9, 6, 1, -8 }, // 0x3A ':'
- { 260, 3, 12, 6, 2, -8 }, // 0x3B ';'
- { 265, 10, 10, 12, 1, -9 }, // 0x3C '<'
- { 278, 10, 5, 12, 1, -6 }, // 0x3D '='
- { 285, 10, 10, 12, 1, -8 }, // 0x3E '>'
- { 298, 7, 12, 9, 1, -11 }, // 0x3F '?'
- { 309, 13, 12, 17, 2, -11 }, // 0x40 '@'
- { 329, 13, 12, 13, 0, -11 }, // 0x41 'A'
- { 349, 11, 12, 12, 0, -11 }, // 0x42 'B'
- { 366, 11, 12, 13, 1, -11 }, // 0x43 'C'
- { 383, 11, 12, 13, 1, -11 }, // 0x44 'D'
- { 400, 11, 12, 12, 1, -11 }, // 0x45 'E'
- { 417, 10, 12, 11, 1, -11 }, // 0x46 'F'
- { 432, 12, 12, 14, 1, -11 }, // 0x47 'G'
- { 450, 12, 12, 14, 1, -11 }, // 0x48 'H'
- { 468, 5, 12, 7, 1, -11 }, // 0x49 'I'
- { 476, 8, 14, 9, 0, -11 }, // 0x4A 'J'
- { 490, 13, 12, 14, 1, -11 }, // 0x4B 'K'
- { 510, 11, 12, 12, 1, -11 }, // 0x4C 'L'
- { 527, 16, 12, 17, 0, -11 }, // 0x4D 'M'
- { 551, 11, 12, 13, 1, -11 }, // 0x4E 'N'
- { 568, 12, 12, 14, 1, -11 }, // 0x4F 'O'
- { 586, 10, 12, 11, 1, -11 }, // 0x50 'P'
- { 601, 12, 15, 14, 1, -11 }, // 0x51 'Q'
- { 624, 12, 12, 13, 1, -11 }, // 0x52 'R'
- { 642, 8, 12, 10, 1, -11 }, // 0x53 'S'
- { 654, 12, 12, 12, 0, -11 }, // 0x54 'T'
- { 672, 11, 12, 13, 1, -11 }, // 0x55 'U'
- { 689, 13, 13, 13, 0, -11 }, // 0x56 'V'
- { 711, 18, 12, 18, 0, -11 }, // 0x57 'W'
- { 738, 13, 12, 13, 0, -11 }, // 0x58 'X'
- { 758, 13, 12, 13, 0, -11 }, // 0x59 'Y'
- { 778, 11, 12, 12, 1, -11 }, // 0x5A 'Z'
- { 795, 4, 15, 6, 1, -11 }, // 0x5B '['
- { 803, 6, 13, 5, 0, -11 }, // 0x5C '\'
- { 813, 4, 15, 6, 1, -11 }, // 0x5D ']'
- { 821, 8, 7, 10, 1, -11 }, // 0x5E '^'
- { 828, 9, 1, 9, 0, 3 }, // 0x5F '_'
- { 830, 4, 3, 6, 0, -12 }, // 0x60 '`'
- { 832, 9, 9, 9, 0, -8 }, // 0x61 'a'
- { 843, 10, 12, 10, 0, -11 }, // 0x62 'b'
- { 858, 7, 9, 8, 0, -8 }, // 0x63 'c'
- { 866, 10, 12, 10, 0, -11 }, // 0x64 'd'
- { 881, 8, 9, 8, 0, -8 }, // 0x65 'e'
- { 890, 7, 12, 7, 0, -11 }, // 0x66 'f'
- { 901, 7, 13, 9, 1, -8 }, // 0x67 'g'
- { 913, 10, 12, 10, 0, -11 }, // 0x68 'h'
- { 928, 5, 12, 5, 0, -11 }, // 0x69 'i'
- { 936, 6, 16, 7, 0, -11 }, // 0x6A 'j'
- { 948, 10, 12, 10, 0, -11 }, // 0x6B 'k'
- { 963, 5, 12, 5, 0, -11 }, // 0x6C 'l'
- { 971, 15, 9, 15, 0, -8 }, // 0x6D 'm'
- { 988, 10, 9, 10, 0, -8 }, // 0x6E 'n'
- { 1000, 9, 9, 9, 0, -8 }, // 0x6F 'o'
- { 1011, 10, 13, 10, 0, -8 }, // 0x70 'p'
- { 1028, 10, 13, 10, 0, -8 }, // 0x71 'q'
- { 1045, 8, 9, 8, 0, -8 }, // 0x72 'r'
- { 1054, 5, 9, 7, 1, -8 }, // 0x73 's'
- { 1060, 6, 11, 6, 0, -10 }, // 0x74 't'
- { 1069, 10, 9, 10, 0, -8 }, // 0x75 'u'
- { 1081, 9, 9, 9, 0, -8 }, // 0x76 'v'
- { 1092, 12, 9, 13, 0, -8 }, // 0x77 'w'
- { 1106, 9, 9, 9, 0, -8 }, // 0x78 'x'
- { 1117, 8, 13, 9, 0, -8 }, // 0x79 'y'
- { 1130, 7, 9, 8, 1, -8 }, // 0x7A 'z'
- { 1138, 5, 16, 7, 0, -12 }, // 0x7B '{'
- { 1148, 1, 13, 4, 1, -11 }, // 0x7C '|'
- { 1150, 5, 16, 7, 2, -12 }, // 0x7D '}'
- { 1160, 8, 2, 9, 1, -4 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBold9pt7b PROGMEM = {
- (uint8_t *)FreeSerifBold9pt7bBitmaps,
- (GFXglyph *)FreeSerifBold9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1834 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic12pt7b.h
deleted file mode 100644
index 1f674e9..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic12pt7b.h
+++ /dev/null
@@ -1,292 +0,0 @@
-const uint8_t FreeSerifBoldItalic12pt7bBitmaps[] PROGMEM = {
- 0x07, 0x07, 0x07, 0x0F, 0x0E, 0x0E, 0x0C, 0x0C, 0x08, 0x18, 0x10, 0x00,
- 0x00, 0x60, 0xF0, 0xF0, 0x60, 0x61, 0xF1, 0xF8, 0xF8, 0x6C, 0x34, 0x12,
- 0x08, 0x01, 0x8C, 0x06, 0x60, 0x31, 0x80, 0xCC, 0x06, 0x30, 0xFF, 0xF0,
- 0xC6, 0x03, 0x18, 0x0C, 0xC0, 0x63, 0x0F, 0xFF, 0x0C, 0x60, 0x33, 0x01,
- 0x8C, 0x06, 0x30, 0x19, 0x80, 0x00, 0x80, 0x08, 0x07, 0xC1, 0x96, 0x31,
- 0x33, 0x13, 0x3A, 0x23, 0xE0, 0x1E, 0x01, 0xF0, 0x07, 0x80, 0x7C, 0x05,
- 0xC4, 0xCC, 0x48, 0xCC, 0x8C, 0xF8, 0x83, 0x30, 0x1E, 0x01, 0x00, 0x00,
- 0x02, 0x07, 0x83, 0x03, 0x9F, 0x81, 0xC4, 0x20, 0x71, 0x10, 0x3C, 0x44,
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- 0x8C, 0x1C, 0xC0, 0xE4, 0x06, 0x40, 0x7E, 0x03, 0xF0, 0x1D, 0x81, 0xCE,
- 0x0E, 0x72, 0x71, 0xA3, 0x8E, 0x00, 0x06, 0x7C, 0x70, 0xE1, 0xC3, 0x0E,
- 0x1C, 0x38, 0x61, 0xC3, 0x87, 0x0C, 0x38, 0x72, 0xE9, 0xE0, 0x3C, 0x73,
- 0xC7, 0x7D, 0x71, 0xE7, 0x9C, 0xF1, 0xCE, 0x3C, 0xF3, 0x8E, 0x39, 0xC3,
- 0x8E, 0x71, 0xC3, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xD7, 0x1C, 0x7B, 0x8E,
- 0x1C, 0x3C, 0xF1, 0xD7, 0x1E, 0x73, 0xCE, 0x3C, 0xE3, 0x8E, 0x39, 0xC7,
- 0x9C, 0x71, 0xC7, 0x1D, 0x71, 0xEE, 0x1C, 0x0F, 0x06, 0x63, 0x9D, 0xC7,
- 0x71, 0xF8, 0x7E, 0x3F, 0x8E, 0xE3, 0xB9, 0xC6, 0x60, 0xF0, 0x0F, 0x38,
- 0x1F, 0x70, 0x71, 0xC1, 0xC7, 0x0E, 0x1C, 0x38, 0xF0, 0xE3, 0x83, 0x8E,
- 0x1C, 0x70, 0x71, 0xC1, 0xCE, 0x07, 0xE0, 0x38, 0x00, 0xE0, 0x03, 0x80,
- 0x3F, 0x00, 0x07, 0x70, 0xCE, 0x18, 0xE3, 0x8E, 0x70, 0xE7, 0x1C, 0xF1,
- 0xCE, 0x1C, 0xE3, 0x8E, 0x38, 0xE7, 0x87, 0xB0, 0x07, 0x00, 0x70, 0x0F,
- 0x03, 0xF8, 0x0D, 0xDF, 0x71, 0xAC, 0xF0, 0x38, 0x0E, 0x03, 0x81, 0xC0,
- 0x70, 0x1C, 0x0E, 0x00, 0x1D, 0x99, 0x8C, 0x46, 0x23, 0x80, 0xE0, 0x70,
- 0x1C, 0x06, 0x23, 0x19, 0x17, 0x00, 0x0C, 0x10, 0xE3, 0xF3, 0x86, 0x1C,
- 0x38, 0x71, 0xC3, 0x87, 0x0E, 0x9E, 0x38, 0x00, 0xF8, 0xE3, 0x8E, 0x38,
- 0xC3, 0x9C, 0x71, 0xC7, 0x18, 0x71, 0x87, 0x38, 0xE3, 0x8E, 0xFA, 0xF3,
- 0xAE, 0x3C, 0xF0, 0xDC, 0x33, 0x0C, 0xC2, 0x31, 0x8C, 0xC3, 0x60, 0xF0,
- 0x38, 0x0C, 0x02, 0x00, 0xE0, 0x86, 0xE3, 0x0C, 0xC6, 0x19, 0x9C, 0x23,
- 0x78, 0xC7, 0xF9, 0x0E, 0x74, 0x1C, 0xF0, 0x31, 0xC0, 0x43, 0x00, 0x84,
- 0x00, 0x0E, 0x31, 0xF3, 0x83, 0xA0, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x1C,
- 0x00, 0xE0, 0x0B, 0x02, 0x5D, 0x3C, 0xF1, 0xC3, 0x00, 0x04, 0x67, 0x8C,
- 0x79, 0x87, 0x10, 0xE2, 0x1C, 0x81, 0x90, 0x3A, 0x07, 0x80, 0xF0, 0x1C,
- 0x03, 0x00, 0x40, 0x08, 0x32, 0x07, 0x80, 0x3F, 0xCF, 0xE6, 0x30, 0x08,
- 0x04, 0x02, 0x01, 0x00, 0xC0, 0x30, 0x1E, 0x0F, 0x98, 0x76, 0x07, 0x00,
- 0x01, 0xE0, 0x70, 0x1C, 0x03, 0x80, 0x60, 0x1C, 0x03, 0x80, 0x60, 0x0C,
- 0x03, 0x80, 0xF0, 0x3C, 0x07, 0x00, 0x40, 0x0C, 0x01, 0x80, 0x70, 0x0E,
- 0x01, 0xC0, 0x30, 0x03, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0xE0,
- 0x18, 0x06, 0x01, 0x80, 0xE0, 0x38, 0x0C, 0x03, 0x00, 0xC0, 0x10, 0x1F,
- 0x07, 0x03, 0x80, 0xE0, 0x30, 0x0C, 0x07, 0x01, 0x80, 0xE0, 0xE0, 0x00,
- 0x38, 0x0F, 0xCD, 0x1F, 0x80, 0xE0 };
-
-const GFXglyph FreeSerifBoldItalic12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 8, 17, 9, 2, -15 }, // 0x21 '!'
- { 17, 9, 7, 13, 4, -15 }, // 0x22 '"'
- { 25, 14, 16, 12, -1, -15 }, // 0x23 '#'
- { 53, 12, 20, 12, 0, -17 }, // 0x24 '$'
- { 83, 18, 18, 20, 1, -16 }, // 0x25 '%'
- { 124, 16, 17, 19, 0, -15 }, // 0x26 '&'
- { 158, 3, 7, 7, 3, -15 }, // 0x27 '''
- { 161, 7, 21, 8, 1, -15 }, // 0x28 '('
- { 180, 7, 21, 8, -1, -15 }, // 0x29 ')'
- { 199, 10, 10, 12, 1, -15 }, // 0x2A '*'
- { 212, 12, 12, 14, 1, -11 }, // 0x2B '+'
- { 230, 5, 8, 6, -2, -3 }, // 0x2C ','
- { 235, 6, 3, 8, 0, -6 }, // 0x2D '-'
- { 238, 4, 4, 6, 0, -2 }, // 0x2E '.'
- { 240, 10, 16, 8, 0, -15 }, // 0x2F '/'
- { 260, 11, 17, 12, 0, -15 }, // 0x30 '0'
- { 284, 10, 17, 12, 0, -15 }, // 0x31 '1'
- { 306, 11, 17, 12, 0, -15 }, // 0x32 '2'
- { 330, 11, 17, 12, 0, -15 }, // 0x33 '3'
- { 354, 13, 16, 12, 0, -15 }, // 0x34 '4'
- { 380, 12, 17, 12, 0, -15 }, // 0x35 '5'
- { 406, 11, 17, 12, 1, -15 }, // 0x36 '6'
- { 430, 11, 16, 12, 2, -15 }, // 0x37 '7'
- { 452, 11, 17, 12, 0, -15 }, // 0x38 '8'
- { 476, 11, 17, 12, 0, -15 }, // 0x39 '9'
- { 500, 7, 12, 6, 0, -10 }, // 0x3A ':'
- { 511, 8, 15, 6, -1, -10 }, // 0x3B ';'
- { 526, 12, 13, 14, 1, -12 }, // 0x3C '<'
- { 546, 12, 6, 14, 2, -8 }, // 0x3D '='
- { 555, 13, 13, 14, 1, -12 }, // 0x3E '>'
- { 577, 9, 17, 12, 2, -15 }, // 0x3F '?'
- { 597, 17, 16, 20, 1, -15 }, // 0x40 '@'
- { 631, 16, 17, 17, 0, -15 }, // 0x41 'A'
- { 665, 16, 17, 15, 0, -15 }, // 0x42 'B'
- { 699, 15, 17, 15, 1, -15 }, // 0x43 'C'
- { 731, 18, 17, 17, 0, -15 }, // 0x44 'D'
- { 770, 17, 17, 15, 0, -15 }, // 0x45 'E'
- { 807, 16, 17, 15, 0, -15 }, // 0x46 'F'
- { 841, 17, 17, 17, 1, -15 }, // 0x47 'G'
- { 878, 20, 17, 18, 0, -15 }, // 0x48 'H'
- { 921, 10, 17, 9, 0, -15 }, // 0x49 'I'
- { 943, 14, 18, 12, 0, -15 }, // 0x4A 'J'
- { 975, 17, 17, 16, 0, -15 }, // 0x4B 'K'
- { 1012, 15, 17, 15, 0, -15 }, // 0x4C 'L'
- { 1044, 23, 17, 21, 0, -15 }, // 0x4D 'M'
- { 1093, 19, 17, 17, 0, -15 }, // 0x4E 'N'
- { 1134, 16, 17, 16, 1, -15 }, // 0x4F 'O'
- { 1168, 16, 17, 14, 0, -15 }, // 0x50 'P'
- { 1202, 16, 21, 16, 1, -15 }, // 0x51 'Q'
- { 1244, 16, 17, 16, 0, -15 }, // 0x52 'R'
- { 1278, 12, 17, 12, 0, -15 }, // 0x53 'S'
- { 1304, 15, 17, 14, 2, -15 }, // 0x54 'T'
- { 1336, 16, 17, 17, 3, -15 }, // 0x55 'U'
- { 1370, 16, 16, 17, 3, -15 }, // 0x56 'V'
- { 1402, 21, 16, 22, 3, -15 }, // 0x57 'W'
- { 1444, 17, 17, 17, 0, -15 }, // 0x58 'X'
- { 1481, 14, 17, 15, 3, -15 }, // 0x59 'Y'
- { 1511, 15, 17, 13, 0, -15 }, // 0x5A 'Z'
- { 1543, 10, 20, 8, -1, -15 }, // 0x5B '['
- { 1568, 6, 16, 10, 3, -15 }, // 0x5C '\'
- { 1580, 9, 20, 8, -1, -15 }, // 0x5D ']'
- { 1603, 10, 9, 14, 2, -15 }, // 0x5E '^'
- { 1615, 12, 1, 12, 0, 4 }, // 0x5F '_'
- { 1617, 5, 4, 8, 2, -15 }, // 0x60 '`'
- { 1620, 12, 12, 12, 0, -10 }, // 0x61 'a'
- { 1638, 11, 18, 12, 1, -16 }, // 0x62 'b'
- { 1663, 9, 12, 10, 1, -10 }, // 0x63 'c'
- { 1677, 14, 18, 12, 0, -16 }, // 0x64 'd'
- { 1709, 9, 12, 10, 1, -10 }, // 0x65 'e'
- { 1723, 14, 22, 12, -2, -16 }, // 0x66 'f'
- { 1762, 13, 16, 12, -1, -10 }, // 0x67 'g'
- { 1788, 13, 18, 13, 0, -16 }, // 0x68 'h'
- { 1818, 6, 17, 7, 1, -15 }, // 0x69 'i'
- { 1831, 11, 21, 8, -2, -15 }, // 0x6A 'j'
- { 1860, 13, 18, 12, 0, -16 }, // 0x6B 'k'
- { 1890, 7, 18, 7, 1, -16 }, // 0x6C 'l'
- { 1906, 18, 12, 18, 0, -10 }, // 0x6D 'm'
- { 1933, 12, 12, 13, 0, -10 }, // 0x6E 'n'
- { 1951, 10, 12, 11, 1, -10 }, // 0x6F 'o'
- { 1966, 14, 16, 12, -2, -10 }, // 0x70 'p'
- { 1994, 12, 16, 12, 0, -10 }, // 0x71 'q'
- { 2018, 10, 11, 10, 0, -10 }, // 0x72 'r'
- { 2032, 9, 12, 9, 0, -10 }, // 0x73 's'
- { 2046, 7, 15, 7, 1, -13 }, // 0x74 't'
- { 2060, 12, 12, 13, 1, -10 }, // 0x75 'u'
- { 2078, 10, 11, 11, 1, -10 }, // 0x76 'v'
- { 2092, 15, 11, 16, 1, -10 }, // 0x77 'w'
- { 2113, 13, 12, 11, -1, -10 }, // 0x78 'x'
- { 2133, 11, 16, 10, -1, -10 }, // 0x79 'y'
- { 2155, 10, 13, 10, 0, -10 }, // 0x7A 'z'
- { 2172, 11, 21, 8, 0, -16 }, // 0x7B '{'
- { 2201, 2, 16, 6, 3, -15 }, // 0x7C '|'
- { 2205, 10, 21, 8, -3, -16 }, // 0x7D '}'
- { 2232, 11, 4, 14, 1, -7 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBoldItalic12pt7b PROGMEM = {
- (uint8_t *)FreeSerifBoldItalic12pt7bBitmaps,
- (GFXglyph *)FreeSerifBoldItalic12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2910 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic18pt7b.h
deleted file mode 100644
index e24eea6..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic18pt7b.h
+++ /dev/null
@@ -1,500 +0,0 @@
-const uint8_t FreeSerifBoldItalic18pt7bBitmaps[] PROGMEM = {
- 0x01, 0xC0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0x80, 0xF0, 0x3C, 0x07,
- 0x80, 0xE0, 0x1C, 0x03, 0x00, 0x60, 0x0C, 0x03, 0x00, 0x60, 0x08, 0x00,
- 0x00, 0x00, 0x00, 0x07, 0x81, 0xF8, 0x3F, 0x07, 0xE0, 0x78, 0x00, 0x38,
- 0x1D, 0xE0, 0xF7, 0x83, 0xDC, 0x0E, 0x70, 0x39, 0xC0, 0xE6, 0x03, 0x18,
- 0x0C, 0x40, 0x23, 0x01, 0x80, 0x00, 0x38, 0x60, 0x07, 0x0E, 0x00, 0x70,
- 0xC0, 0x06, 0x1C, 0x00, 0xE1, 0xC0, 0x0E, 0x38, 0x01, 0xC3, 0x81, 0xFF,
- 0xFF, 0x1F, 0xFF, 0xE1, 0xFF, 0xFE, 0x03, 0x86, 0x00, 0x30, 0xE0, 0x07,
- 0x0E, 0x00, 0x71, 0xC0, 0x0E, 0x1C, 0x0F, 0xFF, 0xF8, 0xFF, 0xFF, 0x0F,
- 0xFF, 0xF0, 0x1C, 0x30, 0x01, 0x87, 0x00, 0x38, 0x70, 0x03, 0x0E, 0x00,
- 0x70, 0xE0, 0x07, 0x0C, 0x00, 0xE1, 0xC0, 0x00, 0x00, 0x08, 0x00, 0x0C,
- 0x00, 0x7E, 0x00, 0xFF, 0xC0, 0xF3, 0x70, 0x71, 0x9C, 0x70, 0xC6, 0x38,
- 0x43, 0x1C, 0x61, 0x0F, 0x30, 0x87, 0xD8, 0x03, 0xF8, 0x00, 0xFE, 0x00,
- 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x01, 0xFC, 0x00, 0xDF, 0x10, 0x47,
- 0x88, 0x63, 0xCC, 0x31, 0xE6, 0x10, 0xF3, 0x98, 0x71, 0xCC, 0x78, 0x7E,
- 0x78, 0x07, 0xF8, 0x03, 0xF0, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x03, 0xC0,
- 0x18, 0x01, 0xFE, 0x0F, 0x00, 0x7C, 0xFF, 0xC0, 0x1F, 0x0F, 0x98, 0x07,
- 0xC1, 0x06, 0x00, 0xF8, 0x21, 0x80, 0x3E, 0x04, 0x30, 0x07, 0xC1, 0x8C,
- 0x00, 0xF0, 0x21, 0x80, 0x1E, 0x0C, 0x60, 0x03, 0xC1, 0x0C, 0x00, 0x78,
- 0xC3, 0x03, 0xC7, 0xF8, 0x61, 0xFC, 0x7C, 0x18, 0x7C, 0xC0, 0x06, 0x1F,
- 0x08, 0x00, 0xC7, 0xC1, 0x00, 0x30, 0xF0, 0x20, 0x06, 0x3E, 0x04, 0x01,
- 0x87, 0xC1, 0x00, 0x30, 0xF0, 0x20, 0x0C, 0x1E, 0x0C, 0x03, 0x03, 0xC1,
- 0x00, 0x60, 0x3C, 0xC0, 0x18, 0x07, 0xF8, 0x03, 0x00, 0x7C, 0x00, 0x00,
- 0x0F, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x1E, 0x38, 0x00, 0x0E, 0x0E, 0x00,
- 0x0F, 0x07, 0x00, 0x07, 0x83, 0x80, 0x03, 0xC3, 0x80, 0x01, 0xE3, 0x80,
- 0x00, 0xF7, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7F, 0x0F,
- 0xF0, 0xE7, 0x81, 0xE0, 0xE3, 0xE0, 0xE0, 0xE1, 0xF0, 0x60, 0xE0, 0x7C,
- 0x60, 0xF0, 0x3E, 0x20, 0x78, 0x1F, 0xB0, 0x3C, 0x07, 0xF0, 0x1F, 0x03,
- 0xF0, 0x0F, 0x80, 0xFC, 0x03, 0xF0, 0x7F, 0x8D, 0xFF, 0xEF, 0xFC, 0x7F,
- 0xE3, 0xFC, 0x0F, 0xC0, 0x78, 0x00, 0x3B, 0xDE, 0xE7, 0x39, 0x8C, 0x46,
- 0x00, 0x00, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x1C, 0x07, 0x01, 0xE0,
- 0x38, 0x0F, 0x01, 0xC0, 0x38, 0x0F, 0x01, 0xE0, 0x38, 0x07, 0x00, 0xE0,
- 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x06,
- 0x00, 0xC0, 0x08, 0x00, 0x80, 0x10, 0x00, 0x06, 0x00, 0x40, 0x04, 0x00,
- 0x80, 0x18, 0x01, 0x00, 0x30, 0x06, 0x00, 0xC0, 0x1C, 0x03, 0x80, 0x70,
- 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x01, 0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x3C,
- 0x07, 0x00, 0xE0, 0x38, 0x06, 0x01, 0xC0, 0x70, 0x18, 0x06, 0x01, 0x80,
- 0x00, 0x07, 0x00, 0x38, 0x01, 0xC1, 0x8E, 0x3E, 0x23, 0xF9, 0x3F, 0xEB,
- 0xE0, 0xE0, 0xFF, 0xF7, 0x93, 0xF8, 0x9F, 0x8E, 0x60, 0x70, 0x03, 0x80,
- 0x08, 0x00, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
- 0x00, 0x0E, 0x00, 0x07, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
- 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80,
- 0x01, 0xC0, 0x00, 0x1C, 0x7C, 0xF9, 0xF1, 0xE1, 0xC3, 0x0C, 0x30, 0xC2,
- 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xE0, 0x7B, 0xFF, 0xFF, 0x78, 0x00, 0x1C,
- 0x00, 0xE0, 0x03, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38,
- 0x01, 0xC0, 0x07, 0x00, 0x38, 0x00, 0xE0, 0x07, 0x80, 0x1C, 0x00, 0x70,
- 0x03, 0x80, 0x0E, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xC0,
- 0x07, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x07, 0x30, 0x1C, 0x30,
- 0x78, 0x60, 0xE0, 0xE3, 0xC1, 0xCF, 0x83, 0x9E, 0x0F, 0x3C, 0x1E, 0xF8,
- 0x3D, 0xE0, 0x7B, 0xC1, 0xFF, 0x83, 0xFF, 0x07, 0xBC, 0x0F, 0x78, 0x3E,
- 0xF0, 0x7D, 0xE0, 0xF3, 0x81, 0xE7, 0x07, 0x8E, 0x0F, 0x0C, 0x3C, 0x18,
- 0x70, 0x19, 0xC0, 0x1E, 0x00, 0x00, 0x06, 0x01, 0xF8, 0x1F, 0xF0, 0x03,
- 0xE0, 0x07, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF0, 0x03, 0xE0,
- 0x07, 0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x7C, 0x00, 0xF8, 0x01, 0xE0, 0x07,
- 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0,
- 0x0F, 0xC0, 0xFF, 0xF0, 0x00, 0xF8, 0x01, 0xFC, 0x03, 0xFE, 0x06, 0x3F,
- 0x08, 0x1F, 0x18, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0E,
- 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00, 0x70, 0x00, 0xC0,
- 0x01, 0x80, 0x03, 0x00, 0x06, 0x02, 0x0C, 0x06, 0x08, 0x0C, 0x1F, 0xFC,
- 0x3F, 0xFC, 0x7F, 0xF8, 0xFF, 0xF8, 0x00, 0xF0, 0x07, 0xF8, 0x1F, 0xF0,
- 0x61, 0xF0, 0x81, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0E, 0x00, 0x3C, 0x00,
- 0xE0, 0x07, 0xC0, 0x3F, 0xC0, 0x1F, 0x80, 0x0F, 0x80, 0x1F, 0x00, 0x1E,
- 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xC0, 0x07, 0x9C, 0x0E, 0x3C,
- 0x38, 0x7F, 0xE0, 0x7E, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x3C,
- 0x00, 0x1E, 0x00, 0x0F, 0x80, 0x07, 0xE0, 0x02, 0xF8, 0x01, 0x3C, 0x00,
- 0x9F, 0x00, 0x47, 0xC0, 0x31, 0xE0, 0x18, 0x78, 0x0C, 0x3E, 0x06, 0x0F,
- 0x83, 0x03, 0xC1, 0x80, 0xF0, 0x7F, 0xFF, 0x1F, 0xFF, 0xCF, 0xFF, 0xF0,
- 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x07, 0xC0, 0x01,
- 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x60, 0x00, 0x30, 0x00,
- 0x10, 0x00, 0x1F, 0x00, 0x0F, 0xE0, 0x0F, 0xF8, 0x07, 0xFE, 0x00, 0x3F,
- 0x00, 0x07, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x1C, 0x00,
- 0x0E, 0x00, 0x06, 0x00, 0x03, 0x00, 0x03, 0x87, 0x83, 0x83, 0xE3, 0x81,
- 0xFF, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x03, 0x80, 0x0F, 0x80, 0x1F, 0x00,
- 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x1F, 0x00,
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- 0x03, 0x87, 0x80, 0x70, 0xF0, 0x0C, 0x0C, 0x01, 0x01, 0x00, 0x03, 0x83,
- 0x87, 0xF1, 0xF0, 0x3C, 0xF8, 0x0F, 0x60, 0x03, 0xD0, 0x00, 0xF8, 0x00,
- 0x1E, 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1F, 0x00, 0x0F,
- 0xC0, 0x02, 0xF1, 0x39, 0x3C, 0xCF, 0xCF, 0xE3, 0xE1, 0xF0, 0x70, 0x38,
- 0x00, 0x01, 0x83, 0x07, 0xE3, 0xC1, 0xF1, 0xE0, 0x78, 0xF0, 0x3E, 0x18,
- 0x1F, 0x08, 0x07, 0x84, 0x03, 0xC6, 0x01, 0xE2, 0x00, 0xFB, 0x00, 0x3D,
- 0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00,
- 0xE0, 0x00, 0x60, 0x00, 0x60, 0x0E, 0x60, 0x0F, 0xE0, 0x07, 0xE0, 0x01,
- 0xC0, 0x00, 0x1F, 0xFC, 0x3F, 0xF8, 0x7F, 0xE1, 0x81, 0x82, 0x06, 0x00,
- 0x08, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x10, 0x00, 0x40,
- 0x01, 0x80, 0x07, 0xC0, 0x1F, 0x86, 0x3F, 0x8E, 0xCF, 0x9C, 0x07, 0x30,
- 0x03, 0xC0, 0x00, 0x1E, 0x00, 0xF8, 0x03, 0xC0, 0x0F, 0x00, 0x1E, 0x00,
- 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x1E, 0x00, 0x3C,
- 0x00, 0x78, 0x01, 0xE0, 0x03, 0xC0, 0x1F, 0x00, 0x7E, 0x00, 0x30, 0x00,
- 0x60, 0x00, 0xE0, 0x01, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38,
- 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,
- 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0,
- 0x00, 0xF0, 0x00, 0x70, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80,
- 0x07, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xE0, 0x03, 0xC0, 0x07,
- 0x80, 0x0F, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x10, 0x00, 0xF0, 0x03, 0xF0,
- 0x0F, 0x00, 0x1E, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07,
- 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x70, 0x01, 0xE0, 0x0F, 0x80, 0x7C, 0x00,
- 0x3E, 0x00, 0x7F, 0xC6, 0xFF, 0xFF, 0x61, 0xFE, 0x00, 0x7C };
-
-const GFXglyph FreeSerifBoldItalic18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 9, 0, 1 }, // 0x20 ' '
- { 0, 11, 25, 14, 2, -23 }, // 0x21 '!'
- { 35, 14, 10, 19, 4, -23 }, // 0x22 '"'
- { 53, 20, 25, 17, -1, -24 }, // 0x23 '#'
- { 116, 17, 29, 18, 0, -25 }, // 0x24 '$'
- { 178, 27, 25, 29, 1, -23 }, // 0x25 '%'
- { 263, 25, 25, 27, 0, -23 }, // 0x26 '&'
- { 342, 5, 10, 10, 4, -23 }, // 0x27 '''
- { 349, 11, 30, 12, 1, -23 }, // 0x28 '('
- { 391, 11, 30, 12, -2, -23 }, // 0x29 ')'
- { 433, 13, 15, 18, 2, -23 }, // 0x2A '*'
- { 458, 17, 17, 20, 1, -16 }, // 0x2B '+'
- { 495, 7, 11, 9, -2, -4 }, // 0x2C ','
- { 505, 9, 4, 12, 0, -9 }, // 0x2D '-'
- { 510, 6, 5, 9, 0, -3 }, // 0x2E '.'
- { 514, 14, 25, 12, 0, -23 }, // 0x2F '/'
- { 558, 15, 25, 18, 1, -23 }, // 0x30 '0'
- { 605, 15, 25, 17, 0, -23 }, // 0x31 '1'
- { 652, 16, 25, 18, 0, -23 }, // 0x32 '2'
- { 702, 15, 25, 17, 1, -23 }, // 0x33 '3'
- { 749, 18, 24, 17, 0, -23 }, // 0x34 '4'
- { 803, 17, 25, 18, 0, -23 }, // 0x35 '5'
- { 857, 17, 25, 18, 1, -23 }, // 0x36 '6'
- { 911, 16, 24, 17, 3, -23 }, // 0x37 '7'
- { 959, 17, 25, 18, 0, -23 }, // 0x38 '8'
- { 1013, 17, 25, 18, 0, -23 }, // 0x39 '9'
- { 1067, 10, 17, 9, 0, -15 }, // 0x3A ':'
- { 1089, 11, 22, 9, -1, -15 }, // 0x3B ';'
- { 1120, 18, 19, 20, 1, -18 }, // 0x3C '<'
- { 1163, 18, 10, 20, 2, -13 }, // 0x3D '='
- { 1186, 18, 19, 20, 2, -18 }, // 0x3E '>'
- { 1229, 13, 25, 17, 3, -23 }, // 0x3F '?'
- { 1270, 25, 25, 29, 2, -23 }, // 0x40 '@'
- { 1349, 23, 25, 24, 0, -23 }, // 0x41 'A'
- { 1421, 24, 25, 22, 0, -23 }, // 0x42 'B'
- { 1496, 23, 25, 22, 1, -23 }, // 0x43 'C'
- { 1568, 26, 25, 25, 0, -23 }, // 0x44 'D'
- { 1650, 23, 25, 22, 0, -23 }, // 0x45 'E'
- { 1722, 23, 25, 21, 0, -23 }, // 0x46 'F'
- { 1794, 24, 25, 25, 2, -23 }, // 0x47 'G'
- { 1869, 29, 25, 26, 0, -23 }, // 0x48 'H'
- { 1960, 15, 25, 13, 0, -23 }, // 0x49 'I'
- { 2007, 20, 27, 17, 0, -23 }, // 0x4A 'J'
- { 2075, 25, 25, 23, 0, -23 }, // 0x4B 'K'
- { 2154, 22, 25, 21, 0, -23 }, // 0x4C 'L'
- { 2223, 33, 25, 31, 0, -23 }, // 0x4D 'M'
- { 2327, 27, 25, 25, 0, -23 }, // 0x4E 'N'
- { 2412, 23, 25, 24, 1, -23 }, // 0x4F 'O'
- { 2484, 23, 25, 21, 0, -23 }, // 0x50 'P'
- { 2556, 23, 31, 24, 1, -23 }, // 0x51 'Q'
- { 2646, 24, 25, 23, 0, -23 }, // 0x52 'R'
- { 2721, 18, 25, 18, 0, -23 }, // 0x53 'S'
- { 2778, 21, 25, 21, 3, -23 }, // 0x54 'T'
- { 2844, 24, 25, 25, 4, -23 }, // 0x55 'U'
- { 2919, 24, 25, 25, 4, -23 }, // 0x56 'V'
- { 2994, 31, 25, 32, 4, -23 }, // 0x57 'W'
- { 3091, 25, 25, 24, 0, -23 }, // 0x58 'X'
- { 3170, 21, 25, 22, 4, -23 }, // 0x59 'Y'
- { 3236, 21, 25, 20, 0, -23 }, // 0x5A 'Z'
- { 3302, 14, 30, 12, -1, -23 }, // 0x5B '['
- { 3355, 10, 25, 14, 4, -23 }, // 0x5C '\'
- { 3387, 14, 30, 12, -2, -23 }, // 0x5D ']'
- { 3440, 16, 13, 20, 2, -23 }, // 0x5E '^'
- { 3466, 18, 3, 17, 0, 3 }, // 0x5F '_'
- { 3473, 7, 6, 12, 3, -23 }, // 0x60 '`'
- { 3479, 18, 17, 18, 0, -15 }, // 0x61 'a'
- { 3518, 16, 26, 17, 1, -24 }, // 0x62 'b'
- { 3570, 13, 17, 15, 1, -15 }, // 0x63 'c'
- { 3598, 19, 25, 18, 1, -23 }, // 0x64 'd'
- { 3658, 13, 17, 15, 1, -15 }, // 0x65 'e'
- { 3686, 21, 32, 17, -3, -24 }, // 0x66 'f'
- { 3770, 19, 23, 17, -1, -15 }, // 0x67 'g'
- { 3825, 17, 25, 19, 1, -23 }, // 0x68 'h'
- { 3879, 9, 25, 10, 1, -23 }, // 0x69 'i'
- { 3908, 16, 31, 12, -3, -23 }, // 0x6A 'j'
- { 3970, 17, 25, 18, 1, -23 }, // 0x6B 'k'
- { 4024, 11, 25, 10, 1, -23 }, // 0x6C 'l'
- { 4059, 26, 17, 27, 0, -15 }, // 0x6D 'm'
- { 4115, 18, 17, 18, 0, -15 }, // 0x6E 'n'
- { 4154, 15, 17, 17, 1, -15 }, // 0x6F 'o'
- { 4186, 19, 23, 17, -2, -15 }, // 0x70 'p'
- { 4241, 16, 23, 17, 1, -15 }, // 0x71 'q'
- { 4287, 15, 16, 14, 0, -15 }, // 0x72 'r'
- { 4317, 13, 17, 12, 0, -15 }, // 0x73 's'
- { 4345, 10, 22, 10, 1, -20 }, // 0x74 't'
- { 4373, 17, 17, 19, 1, -15 }, // 0x75 'u'
- { 4410, 13, 16, 15, 2, -15 }, // 0x76 'v'
- { 4436, 19, 16, 23, 3, -15 }, // 0x77 'w'
- { 4474, 18, 17, 17, -1, -15 }, // 0x78 'x'
- { 4513, 17, 23, 15, -2, -15 }, // 0x79 'y'
- { 4562, 15, 19, 14, 0, -15 }, // 0x7A 'z'
- { 4598, 15, 32, 12, 0, -24 }, // 0x7B '{'
- { 4658, 3, 25, 9, 4, -23 }, // 0x7C '|'
- { 4668, 15, 32, 12, -5, -24 }, // 0x7D '}'
- { 4728, 16, 5, 20, 2, -11 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBoldItalic18pt7b PROGMEM = {
- (uint8_t *)FreeSerifBoldItalic18pt7bBitmaps,
- (GFXglyph *)FreeSerifBoldItalic18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 5410 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic24pt7b.h
deleted file mode 100644
index fcb857e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic24pt7b.h
+++ /dev/null
@@ -1,793 +0,0 @@
-const uint8_t FreeSerifBoldItalic24pt7bBitmaps[] PROGMEM = {
- 0x00, 0x3C, 0x00, 0xFC, 0x01, 0xF8, 0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0xC0,
- 0x3F, 0x00, 0x7E, 0x00, 0xF8, 0x01, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x1E,
- 0x00, 0x3C, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x00, 0x0E, 0x00,
- 0x18, 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xF0, 0x03, 0xF0, 0x0F, 0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x3F, 0x00,
- 0x3C, 0x00, 0x1C, 0x01, 0xC7, 0xC0, 0x7D, 0xF8, 0x1F, 0xBF, 0x03, 0xF7,
- 0xC0, 0x7C, 0xF8, 0x0F, 0x9E, 0x01, 0xE3, 0xC0, 0x3C, 0x70, 0x07, 0x1E,
- 0x00, 0xE3, 0x80, 0x38, 0x70, 0x07, 0x0C, 0x00, 0xC0, 0x00, 0x03, 0xC1,
- 0xE0, 0x00, 0x70, 0x38, 0x00, 0x1E, 0x0F, 0x00, 0x03, 0xC1, 0xE0, 0x00,
- 0x70, 0x38, 0x00, 0x1E, 0x0F, 0x00, 0x03, 0x81, 0xC0, 0x00, 0xF0, 0x78,
- 0x00, 0x1E, 0x0F, 0x00, 0x07, 0x83, 0xC0, 0x1F, 0xFF, 0xFF, 0x83, 0xFF,
- 0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x00, 0xE0, 0x70, 0x00, 0x3C, 0x1E, 0x00,
- 0x07, 0x83, 0xC0, 0x00, 0xE0, 0x70, 0x00, 0x3C, 0x1E, 0x00, 0x07, 0x83,
- 0xC0, 0x00, 0xE0, 0x70, 0x07, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFC, 0x1F,
- 0xFF, 0xFF, 0x00, 0x38, 0x1C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xE0, 0xF0,
- 0x00, 0x38, 0x1C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xC0, 0xE0, 0x00, 0x78,
- 0x3C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xC0, 0xE0, 0x00, 0x78, 0x3C, 0x00,
- 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x1F,
- 0xE0, 0x00, 0x7F, 0xF8, 0x01, 0xF1, 0x9E, 0x01, 0xC1, 0x8F, 0x03, 0x83,
- 0x8F, 0x03, 0x83, 0x06, 0x07, 0x83, 0x06, 0x07, 0x87, 0x06, 0x07, 0xC7,
- 0x04, 0x07, 0xE6, 0x04, 0x07, 0xFE, 0x00, 0x03, 0xFE, 0x00, 0x03, 0xFF,
- 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x1F,
- 0xE0, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xF0, 0x00, 0x3B, 0xF8, 0x20, 0x31,
- 0xF8, 0x20, 0x30, 0xF8, 0x60, 0x70, 0xF8, 0x60, 0x60, 0xF8, 0x60, 0x60,
- 0xF8, 0xF0, 0xE0, 0xF0, 0xF0, 0xE1, 0xE0, 0x78, 0xC3, 0xE0, 0x3C, 0xC7,
- 0xC0, 0x0F, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x01, 0x80, 0x00, 0x03, 0x80,
- 0x00, 0x03, 0x80, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0xF0,
- 0x00, 0x70, 0x00, 0xFF, 0x80, 0x1C, 0x00, 0x3F, 0x38, 0x1F, 0x00, 0x0F,
- 0xC7, 0xFF, 0xE0, 0x03, 0xF0, 0x3F, 0xB8, 0x00, 0x7E, 0x04, 0x07, 0x00,
- 0x1F, 0x80, 0x81, 0xC0, 0x03, 0xF0, 0x10, 0x38, 0x00, 0xFC, 0x02, 0x0E,
- 0x00, 0x1F, 0x80, 0x81, 0x80, 0x03, 0xF0, 0x10, 0x70, 0x00, 0x7C, 0x06,
- 0x1C, 0x00, 0x0F, 0x80, 0x83, 0x80, 0x01, 0xF0, 0x30, 0xE0, 0x00, 0x1E,
- 0x0C, 0x1C, 0x07, 0xC3, 0xE3, 0x07, 0x03, 0xFC, 0x3F, 0xC0, 0xC0, 0xFC,
- 0x43, 0xE0, 0x38, 0x3E, 0x0C, 0x00, 0x0E, 0x0F, 0xC0, 0x80, 0x01, 0xC3,
- 0xF0, 0x10, 0x00, 0x70, 0xFC, 0x02, 0x00, 0x0C, 0x1F, 0x80, 0x40, 0x03,
- 0x83, 0xE0, 0x08, 0x00, 0x60, 0xFC, 0x02, 0x00, 0x1C, 0x1F, 0x80, 0x40,
- 0x07, 0x03, 0xE0, 0x10, 0x00, 0xE0, 0x7C, 0x02, 0x00, 0x38, 0x0F, 0x80,
- 0xC0, 0x06, 0x01, 0xF0, 0x30, 0x01, 0xC0, 0x1F, 0x0C, 0x00, 0x30, 0x01,
- 0xFF, 0x00, 0x0E, 0x00, 0x1F, 0x80, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00,
- 0xFF, 0x80, 0x00, 0x01, 0xF1, 0xE0, 0x00, 0x00, 0xF0, 0x78, 0x00, 0x00,
- 0xF0, 0x3C, 0x00, 0x00, 0x78, 0x1E, 0x00, 0x00, 0x7C, 0x0F, 0x00, 0x00,
- 0x3E, 0x0F, 0x80, 0x00, 0x1F, 0x07, 0x80, 0x00, 0x0F, 0x87, 0x80, 0x00,
- 0x07, 0xC7, 0x80, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x01, 0xFE, 0x00, 0x00,
- 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x01, 0xFF, 0x07, 0xFE,
- 0x03, 0xCF, 0xC0, 0xFE, 0x03, 0xC7, 0xE0, 0x3C, 0x07, 0xC3, 0xF0, 0x1C,
- 0x07, 0xC0, 0xFC, 0x0C, 0x03, 0xC0, 0x7E, 0x0E, 0x03, 0xE0, 0x3F, 0x0E,
- 0x01, 0xF0, 0x1F, 0xC6, 0x01, 0xF8, 0x07, 0xF6, 0x00, 0xFC, 0x03, 0xFF,
- 0x00, 0x7E, 0x00, 0xFF, 0x00, 0x3F, 0x80, 0x7F, 0x80, 0x1F, 0xC0, 0x1F,
- 0xC0, 0x07, 0xF0, 0x0F, 0xF0, 0x13, 0xFE, 0x0F, 0xFE, 0x18, 0xFF, 0xFE,
- 0xFF, 0xF8, 0x3F, 0xFE, 0x3F, 0xF8, 0x07, 0xF8, 0x03, 0xF0, 0x00, 0x1C,
- 0x7D, 0xFB, 0xF7, 0xCF, 0x9E, 0x3C, 0x71, 0xE3, 0x87, 0x0C, 0x00, 0x00,
- 0x04, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x3C, 0x01,
- 0xE0, 0x0F, 0x00, 0x3C, 0x01, 0xE0, 0x0F, 0x80, 0x3C, 0x00, 0xF0, 0x07,
- 0xC0, 0x1E, 0x00, 0x78, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF0, 0x03,
- 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00,
- 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0x30, 0x00, 0xE0, 0x01, 0x80,
- 0x06, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x60, 0x01, 0x80, 0x00, 0x00, 0x01,
- 0x00, 0x06, 0x00, 0x08, 0x00, 0x30, 0x00, 0x40, 0x01, 0x80, 0x06, 0x00,
- 0x1C, 0x00, 0x30, 0x00, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x38, 0x00, 0xF0,
- 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x7C,
- 0x01, 0xF0, 0x07, 0xC0, 0x1E, 0x00, 0x78, 0x03, 0xE0, 0x0F, 0x80, 0x3C,
- 0x01, 0xF0, 0x07, 0x80, 0x1E, 0x00, 0xF0, 0x03, 0x80, 0x1E, 0x00, 0xF0,
- 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x06, 0x00, 0x30, 0x00, 0x80, 0x00, 0x00,
- 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x07, 0x0E, 0x1D, 0xF1,
- 0xC7, 0xFF, 0x11, 0xFF, 0xE2, 0x3F, 0x7E, 0x4F, 0xC0, 0x3E, 0x00, 0x07,
- 0xC0, 0x3F, 0x27, 0xEF, 0xC4, 0x7F, 0xF8, 0x8F, 0xFE, 0x38, 0xFB, 0x87,
- 0x0E, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0x70, 0x00, 0x00,
- 0x78, 0x00, 0x01, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78,
- 0x00, 0x01, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x03,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x01,
- 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0,
- 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00,
- 0x07, 0x80, 0x00, 0x0F, 0x07, 0xE1, 0xFC, 0x7F, 0x1F, 0xC3, 0xF0, 0x7C,
- 0x0E, 0x03, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x1C, 0x04, 0x00, 0x7F, 0xF7,
- 0xFF, 0x7F, 0xEF, 0xFE, 0xFF, 0xE0, 0x3C, 0x7E, 0xFF, 0xFF, 0xFF, 0x7E,
- 0x3C, 0x00, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00,
- 0x78, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x07,
- 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x07, 0x80, 0x00, 0xF0, 0x00, 0x3C,
- 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x01, 0xE0,
- 0x00, 0x7C, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x0F, 0x00,
- 0x03, 0xC0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00, 0xF8, 0x00,
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- 0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00, 0xF8, 0x00, 0x00,
- 0x0F, 0x80, 0x00, 0x01, 0xF0, 0x00, 0x06, 0x1F, 0x00, 0x00, 0xF1, 0xE0,
- 0x00, 0x0F, 0x3E, 0x00, 0x00, 0xF3, 0xC0, 0x00, 0x07, 0xF8, 0x00, 0x00,
- 0x3E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x7F, 0xF0, 0x00, 0x7E,
- 0x3F, 0xE0, 0x7C, 0x0F, 0xF0, 0x7E, 0x07, 0xC0, 0x7E, 0x03, 0xE0, 0x3F,
- 0x01, 0xF0, 0x1F, 0x01, 0xF8, 0x0F, 0x80, 0xFC, 0x07, 0xC0, 0xFC, 0x01,
- 0xE0, 0xFC, 0x00, 0x78, 0xFC, 0x00, 0x1F, 0xFC, 0x00, 0x0F, 0xF0, 0x00,
- 0x1C, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x0F, 0xF8, 0x00,
- 0x07, 0xFF, 0x80, 0x01, 0xFF, 0xF8, 0x00, 0x7F, 0xFE, 0x00, 0x77, 0xFF,
- 0x80, 0xF0, 0x7F, 0xC0, 0xF0, 0x07, 0xE0, 0xF0, 0x01, 0xF0, 0x78, 0x00,
- 0xF8, 0x3C, 0x00, 0x78, 0x1F, 0x00, 0x7C, 0x07, 0xC0, 0x78, 0x01, 0xFF,
- 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0x04, 0x00, 0x01, 0xF8, 0x00, 0x1F,
- 0xF0, 0x00, 0x07, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x7E,
- 0x00, 0x00, 0xFC, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0xC0,
- 0x00, 0x1F, 0x87, 0xC0, 0x3E, 0x1F, 0xC0, 0xFC, 0x7F, 0x81, 0xF9, 0x9F,
- 0x03, 0xE6, 0x3E, 0x07, 0xD8, 0x7C, 0x1F, 0xA0, 0xF8, 0x3F, 0x83, 0xF0,
- 0x7F, 0x07, 0xE0, 0xFC, 0x0F, 0xC3, 0xF8, 0x3F, 0x07, 0xE0, 0x7E, 0x0F,
- 0xC0, 0xFC, 0x3F, 0x03, 0xF0, 0x7E, 0x07, 0xE0, 0xFC, 0x0F, 0xC1, 0xF0,
- 0x3F, 0x17, 0xE0, 0x7E, 0x6F, 0xC0, 0xF9, 0x9F, 0x01, 0xF6, 0x3E, 0x03,
- 0xF8, 0xFC, 0x07, 0xF1, 0xC0, 0x07, 0x80, 0x01, 0xE0, 0x3F, 0x03, 0xF0,
- 0x3F, 0x03, 0xF0, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC7,
- 0xFC, 0x1F, 0xC0, 0xF8, 0x0F, 0x81, 0xF8, 0x1F, 0x81, 0xF0, 0x1F, 0x03,
- 0xF0, 0x3E, 0x03, 0xE0, 0x3E, 0x07, 0xE0, 0x7C, 0x07, 0xC0, 0xFC, 0x2F,
- 0x84, 0xF8, 0xCF, 0x98, 0xFF, 0x0F, 0xE0, 0x78, 0x00, 0x00, 0x00, 0x78,
- 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00,
- 0x01, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x00, 0xFC, 0x00, 0x1F, 0xF0, 0x00, 0x1F, 0xC0,
- 0x00, 0x3E, 0x00, 0x01, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00,
- 0x7C, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8,
- 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7E, 0x00, 0x01, 0xF0, 0x00,
- 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xE0, 0x00, 0x1F,
- 0x80, 0x00, 0x7E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3F, 0x00,
- 0x60, 0xF8, 0x03, 0xC3, 0xC0, 0x0F, 0x1F, 0x00, 0x3C, 0xF8, 0x00, 0x7F,
- 0xC0, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xFC, 0x00, 0x07,
- 0xFC, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x01,
- 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x03,
- 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xE3, 0xFF, 0x03, 0xE0, 0xFC, 0x07,
- 0xE0, 0xF0, 0x07, 0xE0, 0xE0, 0x07, 0xC1, 0xC0, 0x0F, 0xC3, 0x80, 0x0F,
- 0xC7, 0x00, 0x0F, 0x8E, 0x00, 0x0F, 0xBE, 0x00, 0x1F, 0xFE, 0x00, 0x1F,
- 0xFE, 0x00, 0x1F, 0xFE, 0x00, 0x1F, 0x3E, 0x00, 0x3F, 0x3F, 0x00, 0x3F,
- 0x1F, 0x00, 0x3E, 0x1F, 0x00, 0x7E, 0x1F, 0x04, 0x7E, 0x1F, 0x8C, 0x7E,
- 0x0F, 0x98, 0x7C, 0x0F, 0xF0, 0xFC, 0x07, 0xE0, 0xE0, 0x03, 0xC0, 0x00,
- 0x08, 0x0F, 0xC7, 0xFE, 0x07, 0xF0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7C,
- 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0x80, 0x7C, 0x07, 0xE0, 0x3E, 0x01,
- 0xF0, 0x1F, 0x80, 0xFC, 0x07, 0xC0, 0x3E, 0x03, 0xF0, 0x1F, 0x80, 0xF8,
- 0x0F, 0xC0, 0x7E, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x8F, 0x8C, 0x7C, 0x43,
- 0xE4, 0x1F, 0xE0, 0xFE, 0x03, 0xC0, 0x00, 0x00, 0x70, 0x78, 0x0F, 0x83,
- 0xFE, 0x3F, 0x87, 0xF8, 0x1F, 0xCF, 0xF1, 0xFF, 0x03, 0xF1, 0x3E, 0x73,
- 0xE0, 0x7E, 0x47, 0xD8, 0x7C, 0x0F, 0xD0, 0xFB, 0x1F, 0x81, 0xF4, 0x3E,
- 0xC3, 0xF0, 0x3E, 0x87, 0xF0, 0x7C, 0x0F, 0xE0, 0xFE, 0x1F, 0x81, 0xF4,
- 0x1F, 0x83, 0xF0, 0x3F, 0x07, 0xE0, 0x7C, 0x07, 0xE0, 0xFC, 0x1F, 0x81,
- 0xF8, 0x1F, 0x83, 0xF0, 0x3F, 0x07, 0xE0, 0x7C, 0x07, 0xE0, 0xFC, 0x0F,
- 0x80, 0xF8, 0x1F, 0x03, 0xF0, 0x3F, 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0xFC,
- 0x0F, 0x88, 0xF8, 0x1F, 0x81, 0xF3, 0x3F, 0x03, 0xE0, 0x3E, 0x47, 0xE0,
- 0xFC, 0x07, 0xF0, 0xFC, 0x1F, 0x80, 0xFE, 0x18, 0x00, 0x00, 0x0F, 0x00,
- 0x00, 0x70, 0xF8, 0x7F, 0xC3, 0xF8, 0x1F, 0x8F, 0xF0, 0x3F, 0x33, 0xE0,
- 0x7C, 0x87, 0xC1, 0xF9, 0x0F, 0x83, 0xF4, 0x1F, 0x07, 0xD0, 0x3E, 0x0F,
- 0xE0, 0xFC, 0x3F, 0x81, 0xF8, 0x7F, 0x03, 0xE0, 0xFC, 0x0F, 0xC1, 0xF8,
- 0x1F, 0x87, 0xE0, 0x3E, 0x0F, 0xC0, 0xFC, 0x1F, 0x81, 0xF0, 0x3E, 0x03,
- 0xE0, 0xFC, 0x0F, 0xC9, 0xF8, 0x1F, 0x33, 0xE0, 0x3E, 0x47, 0xC0, 0x7F,
- 0x1F, 0x80, 0xFE, 0x38, 0x00, 0xF0, 0x00, 0x00, 0x3F, 0x00, 0x0E, 0x38,
- 0x03, 0xC1, 0xC0, 0x78, 0x1E, 0x0F, 0x81, 0xF0, 0xF0, 0x1F, 0x1F, 0x01,
- 0xF3, 0xE0, 0x1F, 0x3E, 0x03, 0xF7, 0xC0, 0x3F, 0x7C, 0x03, 0xF7, 0xC0,
- 0x3E, 0xFC, 0x03, 0xEF, 0xC0, 0x7E, 0xF8, 0x07, 0xCF, 0x80, 0x7C, 0xF8,
- 0x0F, 0x8F, 0x80, 0xF8, 0xF8, 0x1F, 0x07, 0x81, 0xE0, 0x78, 0x3C, 0x03,
- 0xC7, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0x0F, 0x1F, 0x00, 0x3F, 0xE7, 0xF8,
- 0x01, 0xF9, 0xFF, 0x00, 0x1F, 0x47, 0xF0, 0x07, 0xF0, 0x7E, 0x00, 0xFE,
- 0x0F, 0xC0, 0x1F, 0x81, 0xF8, 0x03, 0xF0, 0x3F, 0x00, 0xFC, 0x07, 0xE0,
- 0x1F, 0x81, 0xFC, 0x03, 0xE0, 0x3F, 0x00, 0x7C, 0x07, 0xE0, 0x1F, 0x81,
- 0xFC, 0x03, 0xF0, 0x3F, 0x00, 0x7C, 0x07, 0xE0, 0x0F, 0x81, 0xF8, 0x03,
- 0xF0, 0x3E, 0x00, 0x7E, 0x0F, 0xC0, 0x0F, 0x81, 0xF0, 0x01, 0xF0, 0x7C,
- 0x00, 0x7F, 0x1F, 0x00, 0x0F, 0xFF, 0xC0, 0x01, 0xF3, 0xE0, 0x00, 0x3E,
- 0x00, 0x00, 0x0F, 0xC0, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3E, 0x00, 0x00,
- 0x0F, 0xC0, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0xFC,
- 0x00, 0x00, 0x00, 0x3E, 0x00, 0x03, 0xF9, 0xF0, 0x1F, 0x1F, 0xC0, 0xF8,
- 0x7E, 0x07, 0xC1, 0xF8, 0x3F, 0x07, 0xE0, 0xF8, 0x1F, 0x87, 0xE0, 0x7C,
- 0x3F, 0x01, 0xF0, 0xFC, 0x0F, 0xC7, 0xE0, 0x3E, 0x1F, 0x80, 0xF8, 0x7E,
- 0x07, 0xE3, 0xF0, 0x1F, 0x8F, 0xC0, 0x7C, 0x3F, 0x03, 0xF0, 0xFC, 0x0F,
- 0xC3, 0xF0, 0x7E, 0x0F, 0xC3, 0xF8, 0x3F, 0x9B, 0xE0, 0x7F, 0xDF, 0x01,
- 0xFE, 0x7C, 0x01, 0xF1, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3E, 0x00, 0x00,
- 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xF8,
- 0x00, 0x7F, 0xF8, 0x00, 0x00, 0x71, 0xE1, 0xFF, 0x3E, 0x07, 0xE7, 0xF0,
- 0x7E, 0xFF, 0x07, 0xE9, 0xE0, 0x7D, 0x0E, 0x07, 0xD0, 0x00, 0xFE, 0x00,
- 0x0F, 0xE0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0x80,
- 0x01, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xF0,
- 0x00, 0x7E, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07, 0xC0, 0x00, 0x01,
- 0xF1, 0x07, 0xFF, 0x0F, 0x0F, 0x0E, 0x07, 0x1E, 0x06, 0x1E, 0x06, 0x1F,
- 0x02, 0x1F, 0x02, 0x1F, 0x80, 0x0F, 0xC0, 0x0F, 0xE0, 0x0F, 0xF0, 0x07,
- 0xF8, 0x03, 0xF8, 0x01, 0xFC, 0x00, 0xFC, 0x40, 0x7C, 0x40, 0x7C, 0x60,
- 0x3C, 0xE0, 0x38, 0xF0, 0x38, 0xF8, 0xF0, 0xDF, 0xC0, 0x00, 0x20, 0x03,
- 0x00, 0x38, 0x03, 0x80, 0x3C, 0x03, 0xE0, 0x7F, 0x07, 0xFF, 0x3F, 0xF8,
- 0x7C, 0x07, 0xE0, 0x3F, 0x01, 0xF0, 0x0F, 0x80, 0xFC, 0x07, 0xC0, 0x3E,
- 0x03, 0xF0, 0x1F, 0x80, 0xF8, 0x07, 0xC0, 0x7E, 0x03, 0xF1, 0x1F, 0x08,
- 0xF8, 0x87, 0xC8, 0x3F, 0xC1, 0xFC, 0x07, 0x80, 0x00, 0x00, 0x40, 0x00,
- 0x1F, 0x03, 0xF7, 0xF8, 0x0F, 0x87, 0xE0, 0x3E, 0x1F, 0x81, 0xF8, 0x7E,
- 0x07, 0xC1, 0xF0, 0x1F, 0x07, 0xC0, 0xFC, 0x3F, 0x03, 0xE0, 0xF8, 0x0F,
- 0x83, 0xE0, 0x7E, 0x0F, 0x81, 0xF8, 0x7E, 0x0F, 0xC1, 0xF0, 0x3F, 0x07,
- 0xC1, 0xFC, 0x1F, 0x07, 0xE0, 0xF8, 0x2F, 0x83, 0xE1, 0x3C, 0x6F, 0x8D,
- 0xF1, 0x3E, 0x67, 0xC8, 0xFF, 0x1F, 0xE3, 0xF8, 0x7F, 0x07, 0xC0, 0xF0,
- 0x00, 0x06, 0x07, 0x1F, 0x07, 0xBF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF9,
- 0xF8, 0x3C, 0x7C, 0x0C, 0x3E, 0x06, 0x1F, 0x03, 0x0F, 0x83, 0x07, 0xC1,
- 0x83, 0xE1, 0x81, 0xF1, 0x80, 0xF9, 0x80, 0x7C, 0xC0, 0x3E, 0xC0, 0x1F,
- 0xC0, 0x0F, 0xC0, 0x07, 0xC0, 0x03, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x00,
- 0x40, 0x00, 0x06, 0x01, 0x81, 0xC7, 0xC0, 0x30, 0x7F, 0xF8, 0x0E, 0x0F,
- 0x9F, 0x01, 0xC1, 0xF3, 0xE0, 0x78, 0x3E, 0x7C, 0x1F, 0x03, 0xCF, 0xC3,
- 0xE0, 0x30, 0xF8, 0xFC, 0x06, 0x1F, 0x1F, 0xC0, 0x83, 0xE7, 0xF8, 0x30,
- 0x7C, 0xFF, 0x04, 0x0F, 0xB7, 0xE1, 0x81, 0xF6, 0xFC, 0x60, 0x3F, 0x8F,
- 0x98, 0x07, 0xE1, 0xF3, 0x00, 0xFC, 0x3E, 0xC0, 0x1F, 0x07, 0xF0, 0x03,
- 0xE0, 0xFC, 0x00, 0x78, 0x1F, 0x80, 0x0F, 0x03, 0xE0, 0x01, 0xC0, 0x78,
- 0x00, 0x30, 0x0E, 0x00, 0x06, 0x01, 0x80, 0x00, 0x00, 0xF0, 0x1E, 0x0F,
- 0xF0, 0x3E, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0xFF, 0x00, 0xF9, 0x8E, 0x00,
- 0xFB, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7C, 0x00, 0x00,
- 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7E, 0x00, 0x00,
- 0x7E, 0x00, 0x00, 0x7E, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xBF, 0x00, 0x01,
- 0xBF, 0x08, 0x73, 0x1F, 0x18, 0xFF, 0x1F, 0x30, 0xFE, 0x1F, 0xE0, 0xFC,
- 0x0F, 0xC0, 0x78, 0x07, 0x80, 0x00, 0x30, 0x1C, 0x0F, 0xF0, 0x7C, 0x07,
- 0xE0, 0xF8, 0x0F, 0xC1, 0xF0, 0x0F, 0xC1, 0xE0, 0x1F, 0x81, 0xC0, 0x3F,
- 0x03, 0x00, 0x3E, 0x06, 0x00, 0x7E, 0x08, 0x00, 0xFC, 0x30, 0x01, 0xF8,
- 0x60, 0x01, 0xF1, 0x80, 0x03, 0xE3, 0x00, 0x07, 0xCC, 0x00, 0x0F, 0xD8,
- 0x00, 0x1F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00,
- 0x00, 0xF8, 0x00, 0x01, 0xE0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x00, 0x00,
- 0x0C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x01, 0xC1, 0x80, 0x07, 0xE6,
- 0x00, 0x0F, 0xF8, 0x00, 0x1F, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x07,
- 0xFF, 0xE1, 0xFF, 0xF8, 0x3F, 0xFF, 0x07, 0xFF, 0xC0, 0x80, 0x70, 0x30,
- 0x1C, 0x04, 0x07, 0x00, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03,
- 0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x06, 0x00, 0x01, 0xC0, 0x00, 0x30,
- 0x00, 0x0C, 0x00, 0x03, 0xE0, 0x00, 0xFE, 0x00, 0x1F, 0xE0, 0xC7, 0xFC,
- 0x3D, 0xCF, 0xC7, 0x90, 0xF8, 0xF0, 0x07, 0x9C, 0x00, 0x3E, 0x00, 0x00,
- 0x01, 0xF0, 0x00, 0xFC, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00,
- 0x07, 0xC0, 0x00, 0x78, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80,
- 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xE0,
- 0x00, 0x3E, 0x00, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x0F, 0xC0,
- 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F,
- 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03,
- 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00,
- 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00,
- 0x03, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00,
- 0x3E, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0,
- 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C,
- 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F,
- 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x00,
- 0xF8, 0x00, 0x03, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x03, 0xE0, 0x00,
- 0x7C, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00,
- 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00,
- 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0x80,
- 0x03, 0xF0, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x03, 0xFF, 0x01, 0x3F,
- 0xFE, 0x1D, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0x00, 0x1F, 0xF0, 0x00, 0x1F,
- 0x00 };
-
-const GFXglyph FreeSerifBoldItalic24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 12, 0, 1 }, // 0x20 ' '
- { 0, 15, 33, 18, 3, -31 }, // 0x21 '!'
- { 62, 19, 13, 26, 6, -31 }, // 0x22 '"'
- { 93, 27, 33, 23, -2, -32 }, // 0x23 '#'
- { 205, 24, 39, 24, -1, -33 }, // 0x24 '$'
- { 322, 35, 32, 39, 2, -30 }, // 0x25 '%'
- { 462, 33, 33, 37, 0, -31 }, // 0x26 '&'
- { 599, 7, 13, 13, 6, -31 }, // 0x27 '''
- { 611, 14, 41, 16, 1, -31 }, // 0x28 '('
- { 683, 14, 41, 16, -2, -31 }, // 0x29 ')'
- { 755, 19, 20, 23, 3, -31 }, // 0x2A '*'
- { 803, 22, 23, 27, 2, -22 }, // 0x2B '+'
- { 867, 10, 15, 12, -3, -5 }, // 0x2C ','
- { 886, 12, 5, 16, 0, -12 }, // 0x2D '-'
- { 894, 8, 7, 12, 0, -5 }, // 0x2E '.'
- { 901, 19, 33, 16, 0, -31 }, // 0x2F '/'
- { 980, 22, 33, 23, 1, -31 }, // 0x30 '0'
- { 1071, 20, 32, 23, 0, -31 }, // 0x31 '1'
- { 1151, 22, 32, 23, 1, -31 }, // 0x32 '2'
- { 1239, 22, 33, 24, 0, -31 }, // 0x33 '3'
- { 1330, 25, 32, 23, 0, -31 }, // 0x34 '4'
- { 1430, 24, 32, 24, 0, -30 }, // 0x35 '5'
- { 1526, 23, 32, 24, 1, -30 }, // 0x36 '6'
- { 1618, 23, 31, 23, 3, -30 }, // 0x37 '7'
- { 1708, 21, 33, 23, 1, -31 }, // 0x38 '8'
- { 1795, 23, 33, 23, 0, -31 }, // 0x39 '9'
- { 1890, 13, 22, 12, 0, -20 }, // 0x3A ':'
- { 1926, 15, 30, 12, -2, -20 }, // 0x3B ';'
- { 1983, 24, 25, 27, 1, -23 }, // 0x3C '<'
- { 2058, 24, 14, 27, 3, -18 }, // 0x3D '='
- { 2100, 24, 25, 27, 3, -23 }, // 0x3E '>'
- { 2175, 18, 33, 24, 4, -31 }, // 0x3F '?'
- { 2250, 33, 33, 39, 3, -31 }, // 0x40 '@'
- { 2387, 31, 32, 33, 0, -31 }, // 0x41 'A'
- { 2511, 31, 31, 30, 0, -30 }, // 0x42 'B'
- { 2632, 29, 33, 29, 2, -31 }, // 0x43 'C'
- { 2752, 35, 31, 34, 0, -30 }, // 0x44 'D'
- { 2888, 32, 31, 30, 0, -30 }, // 0x45 'E'
- { 3012, 31, 31, 29, 0, -30 }, // 0x46 'F'
- { 3133, 32, 33, 33, 2, -31 }, // 0x47 'G'
- { 3265, 39, 31, 35, 0, -30 }, // 0x48 'H'
- { 3417, 21, 31, 18, 0, -30 }, // 0x49 'I'
- { 3499, 27, 36, 23, 0, -30 }, // 0x4A 'J'
- { 3621, 34, 31, 31, 0, -30 }, // 0x4B 'K'
- { 3753, 29, 31, 29, 0, -30 }, // 0x4C 'L'
- { 3866, 44, 32, 41, 0, -30 }, // 0x4D 'M'
- { 4042, 37, 32, 33, 0, -30 }, // 0x4E 'N'
- { 4190, 31, 33, 32, 2, -31 }, // 0x4F 'O'
- { 4318, 31, 31, 28, 0, -30 }, // 0x50 'P'
- { 4439, 31, 42, 32, 2, -31 }, // 0x51 'Q'
- { 4602, 32, 31, 31, 0, -30 }, // 0x52 'R'
- { 4726, 24, 33, 24, 0, -31 }, // 0x53 'S'
- { 4825, 27, 31, 28, 4, -30 }, // 0x54 'T'
- { 4930, 32, 32, 34, 5, -30 }, // 0x55 'U'
- { 5058, 31, 32, 33, 6, -30 }, // 0x56 'V'
- { 5182, 41, 32, 44, 6, -30 }, // 0x57 'W'
- { 5346, 34, 31, 33, 0, -30 }, // 0x58 'X'
- { 5478, 28, 31, 30, 6, -30 }, // 0x59 'Y'
- { 5587, 28, 31, 26, 0, -30 }, // 0x5A 'Z'
- { 5696, 19, 38, 16, -2, -30 }, // 0x5B '['
- { 5787, 13, 33, 19, 6, -31 }, // 0x5C '\'
- { 5841, 19, 38, 16, -3, -30 }, // 0x5D ']'
- { 5932, 21, 17, 27, 3, -30 }, // 0x5E '^'
- { 5977, 24, 3, 23, 0, 5 }, // 0x5F '_'
- { 5986, 10, 9, 16, 4, -32 }, // 0x60 '`'
- { 5998, 22, 23, 24, 1, -21 }, // 0x61 'a'
- { 6062, 22, 33, 23, 1, -31 }, // 0x62 'b'
- { 6153, 18, 23, 20, 1, -21 }, // 0x63 'c'
- { 6205, 25, 34, 24, 1, -32 }, // 0x64 'd'
- { 6312, 18, 23, 20, 1, -21 }, // 0x65 'e'
- { 6364, 28, 41, 23, -4, -31 }, // 0x66 'f'
- { 6508, 25, 31, 23, -1, -21 }, // 0x67 'g'
- { 6605, 23, 34, 26, 1, -32 }, // 0x68 'h'
- { 6703, 12, 33, 14, 2, -31 }, // 0x69 'i'
- { 6753, 22, 42, 16, -4, -31 }, // 0x6A 'j'
- { 6869, 24, 34, 24, 1, -32 }, // 0x6B 'k'
- { 6971, 13, 34, 14, 2, -32 }, // 0x6C 'l'
- { 7027, 35, 23, 36, 0, -21 }, // 0x6D 'm'
- { 7128, 23, 23, 25, 0, -21 }, // 0x6E 'n'
- { 7195, 20, 23, 22, 1, -21 }, // 0x6F 'o'
- { 7253, 27, 31, 23, -4, -21 }, // 0x70 'p'
- { 7358, 22, 31, 23, 1, -21 }, // 0x71 'q'
- { 7444, 20, 22, 19, 0, -21 }, // 0x72 'r'
- { 7499, 16, 23, 17, 0, -21 }, // 0x73 's'
- { 7545, 13, 29, 13, 2, -27 }, // 0x74 't'
- { 7593, 22, 23, 25, 2, -21 }, // 0x75 'u'
- { 7657, 17, 23, 21, 3, -21 }, // 0x76 'v'
- { 7706, 27, 23, 31, 3, -21 }, // 0x77 'w'
- { 7784, 24, 23, 22, -1, -21 }, // 0x78 'x'
- { 7853, 23, 31, 20, -3, -21 }, // 0x79 'y'
- { 7943, 19, 25, 19, 0, -20 }, // 0x7A 'z'
- { 8003, 20, 41, 16, 0, -31 }, // 0x7B '{'
- { 8106, 4, 33, 13, 5, -31 }, // 0x7C '|'
- { 8123, 20, 41, 16, -6, -31 }, // 0x7D '}'
- { 8226, 21, 7, 27, 3, -14 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBoldItalic24pt7b PROGMEM = {
- (uint8_t *)FreeSerifBoldItalic24pt7bBitmaps,
- (GFXglyph *)FreeSerifBoldItalic24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 8917 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic9pt7b.h
deleted file mode 100644
index 47711ee..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifBoldItalic9pt7b.h
+++ /dev/null
@@ -1,215 +0,0 @@
-const uint8_t FreeSerifBoldItalic9pt7bBitmaps[] PROGMEM = {
- 0x0C, 0x31, 0xC6, 0x18, 0x41, 0x08, 0x20, 0x0E, 0x38, 0xE0, 0xCF, 0x38,
- 0xA2, 0x88, 0x02, 0x40, 0xC8, 0x13, 0x06, 0x43, 0xFC, 0x32, 0x06, 0x40,
- 0x98, 0x7F, 0x84, 0xC0, 0x90, 0x32, 0x04, 0xC0, 0x01, 0x01, 0xF0, 0x4B,
- 0x99, 0x33, 0x24, 0x78, 0x07, 0x80, 0x38, 0x0B, 0x89, 0x31, 0x26, 0x64,
- 0xC7, 0x30, 0x3C, 0x04, 0x00, 0x38, 0x41, 0x9F, 0x06, 0x48, 0x31, 0x60,
- 0xCD, 0x03, 0x2C, 0x07, 0x27, 0x81, 0x39, 0x05, 0xC4, 0x26, 0x10, 0x98,
- 0x84, 0x66, 0x10, 0xE0, 0x03, 0x80, 0x22, 0x03, 0x10, 0x19, 0x00, 0xF0,
- 0x0F, 0x3C, 0xF8, 0xCC, 0xC4, 0xE7, 0x47, 0x3E, 0x38, 0xE1, 0xE7, 0x97,
- 0xCF, 0x00, 0xFA, 0x80, 0x08, 0x88, 0x84, 0x62, 0x10, 0x84, 0x21, 0x08,
- 0x41, 0x00, 0x20, 0x84, 0x10, 0x84, 0x21, 0x08, 0xC6, 0x23, 0x11, 0x00,
- 0x18, 0x18, 0xD6, 0x38, 0x18, 0xF7, 0x18, 0x18, 0x08, 0x04, 0x02, 0x01,
- 0x0F, 0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0x6D, 0x95, 0x00, 0xFF, 0xC0,
- 0xFF, 0x80, 0x06, 0x0C, 0x30, 0x60, 0x83, 0x04, 0x18, 0x20, 0xC1, 0x06,
- 0x00, 0x0F, 0x0C, 0x8C, 0x6E, 0x37, 0x1B, 0x1F, 0x8F, 0xC7, 0xC7, 0x63,
- 0xB1, 0x89, 0x83, 0x80, 0x06, 0x1E, 0x0E, 0x0E, 0x0C, 0x0C, 0x1C, 0x18,
- 0x18, 0x18, 0x38, 0x38, 0xFC, 0x1F, 0x13, 0xD0, 0xE0, 0x70, 0x38, 0x38,
- 0x18, 0x18, 0x18, 0x08, 0x08, 0x4F, 0xCF, 0xE0, 0x1F, 0x11, 0xC0, 0xE0,
- 0x60, 0xC1, 0xF0, 0x38, 0x0C, 0x06, 0x03, 0x01, 0x19, 0x8F, 0x00, 0x00,
- 0x80, 0xC0, 0xE1, 0xE0, 0xB0, 0x98, 0x9C, 0x8C, 0xFF, 0x07, 0x03, 0x01,
- 0x80, 0x0F, 0x88, 0x08, 0x07, 0x83, 0xE0, 0x78, 0x1C, 0x06, 0x03, 0x01,
- 0x80, 0x9C, 0x87, 0x80, 0x03, 0x87, 0x07, 0x07, 0x07, 0x03, 0xE3, 0x99,
- 0xCC, 0xC6, 0x63, 0x33, 0x89, 0x87, 0x80, 0x3F, 0xBF, 0x90, 0x80, 0xC0,
- 0x40, 0x60, 0x20, 0x30, 0x30, 0x10, 0x18, 0x08, 0x00, 0x1E, 0x13, 0x31,
- 0x31, 0x3A, 0x1C, 0x1C, 0x6E, 0xC6, 0xC6, 0xC6, 0x44, 0x38, 0x0E, 0x1C,
- 0x8C, 0x6C, 0x36, 0x3B, 0x1D, 0x8E, 0x7E, 0x0E, 0x07, 0x07, 0x0E, 0x0C,
- 0x00, 0x39, 0xCE, 0x00, 0x03, 0x9C, 0xE0, 0x39, 0xCE, 0x00, 0x01, 0x8C,
- 0x22, 0x20, 0x00, 0x01, 0xC3, 0xC7, 0x8E, 0x06, 0x01, 0xE0, 0x3C, 0x07,
- 0x80, 0x40, 0xFF, 0x80, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x60, 0x1E, 0x03,
- 0xC0, 0x78, 0x1C, 0x3C, 0x78, 0xF0, 0x40, 0x00, 0x1C, 0x27, 0x37, 0x07,
- 0x0E, 0x1C, 0x30, 0x60, 0x40, 0x00, 0xE0, 0xE0, 0xE0, 0x0F, 0x80, 0xC3,
- 0x08, 0x04, 0xC3, 0x3C, 0x24, 0xE2, 0x27, 0x33, 0x39, 0x11, 0xC9, 0x93,
- 0x77, 0x18, 0x00, 0x70, 0x40, 0xFC, 0x00, 0x00, 0x80, 0x18, 0x01, 0x80,
- 0x38, 0x05, 0x80, 0x5C, 0x09, 0xC1, 0x1C, 0x1F, 0xC2, 0x0C, 0x20, 0xC4,
- 0x0E, 0xF3, 0xF0, 0x3F, 0xE0, 0xC7, 0x0C, 0x71, 0xC7, 0x1C, 0xE1, 0xF0,
- 0x39, 0xC3, 0x8E, 0x38, 0xE3, 0x0E, 0x71, 0xE7, 0x1C, 0xFF, 0x00, 0x07,
- 0xD1, 0xC7, 0x38, 0x27, 0x02, 0x70, 0x0F, 0x00, 0xE0, 0x0E, 0x00, 0xE0,
- 0x0E, 0x00, 0x60, 0x87, 0x18, 0x1E, 0x00, 0x3F, 0xE0, 0x30, 0xE0, 0xC1,
- 0x87, 0x07, 0x1C, 0x1C, 0x60, 0x73, 0x81, 0xCE, 0x07, 0x38, 0x38, 0xC0,
- 0xE7, 0x07, 0x1C, 0x78, 0xFF, 0x80, 0x1F, 0xF8, 0x61, 0xC3, 0x04, 0x38,
- 0x81, 0xCC, 0x0F, 0xE0, 0xE2, 0x07, 0x10, 0x38, 0x81, 0x81, 0x1C, 0x18,
- 0xE3, 0x8F, 0xFC, 0x00, 0x3F, 0xF8, 0x61, 0xC3, 0x04, 0x38, 0x81, 0xCC,
- 0x0F, 0xE0, 0xE2, 0x07, 0x10, 0x38, 0x81, 0x80, 0x1C, 0x00, 0xE0, 0x0F,
- 0x80, 0x00, 0x07, 0x91, 0xC7, 0x38, 0x27, 0x00, 0x70, 0x0F, 0x00, 0xE1,
- 0xFE, 0x0E, 0xE0, 0xCE, 0x0C, 0x60, 0xC7, 0x1C, 0x1F, 0x00, 0x1F, 0x7E,
- 0x1C, 0x38, 0x30, 0x60, 0xE1, 0xC1, 0xC3, 0x83, 0x06, 0x0F, 0xFC, 0x1C,
- 0x38, 0x38, 0x70, 0x60, 0xC1, 0xC3, 0x83, 0x87, 0x0F, 0x9F, 0x00, 0x3F,
- 0x0C, 0x0C, 0x1C, 0x1C, 0x18, 0x38, 0x38, 0x38, 0x30, 0x70, 0x70, 0xF8,
- 0x07, 0xC0, 0xE0, 0x38, 0x0C, 0x07, 0x01, 0xC0, 0x70, 0x18, 0x0E, 0x03,
- 0x80, 0xC3, 0x30, 0xDC, 0x1E, 0x00, 0x1F, 0x78, 0x71, 0x83, 0x18, 0x39,
- 0x81, 0xD0, 0x0D, 0x00, 0xFC, 0x07, 0x60, 0x3B, 0x81, 0x8C, 0x1C, 0x70,
- 0xE1, 0x8F, 0xBE, 0x00, 0x1F, 0x00, 0xC0, 0x0C, 0x01, 0xC0, 0x1C, 0x01,
- 0x80, 0x38, 0x03, 0x80, 0x38, 0x03, 0x01, 0x70, 0x37, 0x0E, 0xFF, 0xE0,
- 0x1E, 0x07, 0x87, 0x07, 0x83, 0x83, 0x82, 0xC3, 0xC1, 0x62, 0xE0, 0xB1,
- 0x70, 0x99, 0x30, 0x4D, 0xB8, 0x27, 0x9C, 0x13, 0x8C, 0x11, 0xC6, 0x0C,
- 0xC7, 0x0F, 0x47, 0xC0, 0x3C, 0x3C, 0x38, 0x20, 0xE0, 0x85, 0xC4, 0x13,
- 0x10, 0x4E, 0x42, 0x3A, 0x08, 0x78, 0x21, 0xE0, 0x83, 0x84, 0x0C, 0x18,
- 0x10, 0x00, 0x40, 0x07, 0xC1, 0xCE, 0x38, 0x73, 0x87, 0x70, 0x77, 0x07,
- 0xF0, 0xFE, 0x0E, 0xE0, 0xEE, 0x1C, 0xE1, 0xC6, 0x38, 0x3E, 0x00, 0x3F,
- 0xC0, 0xC7, 0x0C, 0x71, 0xC7, 0x1C, 0x71, 0x8E, 0x3F, 0xC3, 0x80, 0x30,
- 0x03, 0x00, 0x70, 0x07, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0xCE, 0x38, 0x73,
- 0x87, 0x70, 0x77, 0x07, 0xF0, 0x7E, 0x0E, 0xE0, 0xEE, 0x0C, 0xE1, 0xC6,
- 0x38, 0x36, 0x01, 0x80, 0x3C, 0x2D, 0xFC, 0x3F, 0xC0, 0xE7, 0x0C, 0x71,
- 0xC7, 0x1C, 0x71, 0x8E, 0x3F, 0x83, 0xB8, 0x3B, 0x83, 0x3C, 0x71, 0xC7,
- 0x1C, 0xF9, 0xF0, 0x0C, 0x89, 0x8C, 0x46, 0x23, 0x80, 0xE0, 0x78, 0x0E,
- 0x03, 0x21, 0x90, 0xCC, 0xC9, 0xC0, 0x7F, 0xE9, 0xDF, 0x31, 0x4E, 0x21,
- 0xC0, 0x38, 0x06, 0x01, 0xC0, 0x38, 0x06, 0x00, 0xC0, 0x38, 0x0F, 0xC0,
- 0x7C, 0xF3, 0x82, 0x30, 0x27, 0x04, 0x70, 0x46, 0x04, 0xE0, 0x4E, 0x08,
- 0xE0, 0x8E, 0x08, 0xE1, 0x0F, 0x30, 0x3C, 0x00, 0xFC, 0x73, 0x82, 0x38,
- 0x23, 0x84, 0x38, 0x83, 0x90, 0x39, 0x01, 0xA0, 0x1C, 0x01, 0xC0, 0x18,
- 0x01, 0x00, 0xF9, 0xF7, 0x30, 0xE2, 0x30, 0xC2, 0x38, 0xC4, 0x3B, 0xC4,
- 0x3A, 0xE8, 0x3C, 0xE8, 0x3C, 0xF0, 0x18, 0xF0, 0x18, 0x60, 0x10, 0x60,
- 0x10, 0x40, 0x3F, 0x78, 0x61, 0x83, 0x98, 0x1D, 0x00, 0x70, 0x03, 0x80,
- 0x1C, 0x01, 0x60, 0x0B, 0x80, 0x9C, 0x08, 0x60, 0xC3, 0x8F, 0x7E, 0x00,
- 0xF9, 0xE6, 0x18, 0xC2, 0x1C, 0x81, 0xA0, 0x34, 0x07, 0x00, 0xC0, 0x18,
- 0x07, 0x00, 0xE0, 0x1C, 0x0F, 0xC0, 0x3F, 0xE6, 0x19, 0x87, 0x21, 0xC0,
- 0x30, 0x0E, 0x03, 0x80, 0x60, 0x1C, 0x07, 0x05, 0xC1, 0x38, 0xEF, 0xFC,
- 0x0E, 0x08, 0x18, 0x18, 0x18, 0x10, 0x30, 0x30, 0x30, 0x20, 0x60, 0x60,
- 0x60, 0x40, 0xF0, 0xC6, 0x10, 0xC6, 0x10, 0x86, 0x30, 0x86, 0x30, 0x1E,
- 0x0C, 0x18, 0x20, 0xC1, 0x83, 0x04, 0x18, 0x30, 0x60, 0x83, 0x06, 0x3C,
- 0x00, 0x18, 0x1C, 0x34, 0x26, 0x66, 0x43, 0xC3, 0xFF, 0x80, 0xC6, 0x30,
- 0x0D, 0x9D, 0x8C, 0xCC, 0x6E, 0x26, 0x33, 0x19, 0xBE, 0x66, 0x00, 0x00,
- 0x78, 0x18, 0x30, 0x30, 0x3E, 0x73, 0x63, 0x63, 0x63, 0xC6, 0xC6, 0xCC,
- 0x70, 0x0F, 0x3B, 0x70, 0x70, 0xE0, 0xE0, 0xE2, 0xE4, 0x78, 0x00, 0x00,
- 0xF0, 0x1C, 0x06, 0x01, 0x83, 0xE3, 0x30, 0xCC, 0x63, 0x19, 0xCC, 0x63,
- 0x38, 0xCF, 0x1D, 0x80, 0x0E, 0x75, 0xCB, 0xBE, 0xDE, 0x38, 0x72, 0x78,
- 0x00, 0xE0, 0x34, 0x0C, 0x01, 0x80, 0x30, 0x1F, 0x01, 0x80, 0x30, 0x06,
- 0x01, 0xC0, 0x30, 0x06, 0x00, 0xC0, 0x30, 0x06, 0x04, 0x80, 0xE0, 0x00,
- 0x1C, 0x19, 0xD8, 0xCC, 0x66, 0x60, 0xE1, 0x80, 0xF0, 0x7E, 0x43, 0x21,
- 0x8F, 0x00, 0x00, 0x1E, 0x07, 0x03, 0x01, 0x80, 0xD8, 0xFC, 0x76, 0x33,
- 0x19, 0x99, 0xCC, 0xD6, 0x77, 0x30, 0x39, 0xC0, 0x0F, 0x31, 0x8C, 0xC6,
- 0x31, 0xAE, 0x00, 0x03, 0x81, 0xC0, 0x00, 0x00, 0xE0, 0x30, 0x18, 0x18,
- 0x0C, 0x06, 0x03, 0x03, 0x01, 0x80, 0xC2, 0xC1, 0xC0, 0x00, 0x0F, 0x00,
- 0xC0, 0x60, 0x18, 0x06, 0xF3, 0x90, 0xC8, 0x34, 0x0F, 0x06, 0xC1, 0x98,
- 0x66, 0xB9, 0xC0, 0x03, 0xCC, 0x63, 0x39, 0x8C, 0x66, 0x31, 0x8E, 0x70,
- 0x7B, 0x99, 0xAF, 0xCE, 0x66, 0x63, 0x67, 0x33, 0x31, 0x99, 0x8C, 0xCC,
- 0xE7, 0xC6, 0x30, 0x73, 0x7F, 0x73, 0x73, 0x63, 0x67, 0xE6, 0xC7, 0xC6,
- 0x1E, 0x33, 0x63, 0x63, 0xC3, 0xC6, 0xC6, 0xCC, 0x78, 0x1D, 0xC3, 0xB1,
- 0xCC, 0x63, 0x19, 0xCE, 0x63, 0x18, 0xCC, 0x3E, 0x1C, 0x06, 0x03, 0xE0,
- 0x0D, 0x99, 0x8C, 0xCC, 0x6E, 0x76, 0x33, 0x19, 0x9C, 0x7C, 0x06, 0x07,
- 0x07, 0xC0, 0x76, 0x3A, 0x30, 0x70, 0x60, 0x60, 0x60, 0xE0, 0x3D, 0x14,
- 0x58, 0x38, 0x60, 0xA2, 0xF0, 0x08, 0xCC, 0xF6, 0x31, 0x98, 0xC6, 0x35,
- 0xC0, 0xE3, 0x63, 0x66, 0x66, 0x66, 0xCC, 0xCC, 0xFE, 0xEC, 0xE6, 0xCD,
- 0x8B, 0x26, 0x8E, 0x18, 0x20, 0xE4, 0xD9, 0x36, 0xE5, 0xDA, 0x77, 0x19,
- 0xC6, 0x61, 0x10, 0x39, 0xC7, 0xB0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xE1,
- 0x5A, 0x67, 0x00, 0x39, 0x8C, 0xC3, 0x21, 0xA0, 0xD0, 0x68, 0x38, 0x0C,
- 0x04, 0x04, 0x14, 0x0C, 0x00, 0x3E, 0x46, 0x0C, 0x08, 0x10, 0x20, 0x70,
- 0x1A, 0x0E, 0x03, 0x0E, 0x0C, 0x0C, 0x08, 0x18, 0x18, 0x10, 0x60, 0x30,
- 0x30, 0x30, 0x60, 0x60, 0x60, 0x30, 0xFF, 0xF0, 0x0C, 0x06, 0x06, 0x06,
- 0x04, 0x0C, 0x0C, 0x0C, 0x06, 0x18, 0x18, 0x18, 0x30, 0x30, 0x30, 0xE0,
- 0x71, 0x8F };
-
-const GFXglyph FreeSerifBoldItalic9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 6, 13, 7, 1, -11 }, // 0x21 '!'
- { 10, 6, 5, 10, 3, -11 }, // 0x22 '"'
- { 14, 11, 13, 9, -1, -12 }, // 0x23 '#'
- { 32, 11, 15, 9, -1, -12 }, // 0x24 '$'
- { 53, 14, 13, 15, 1, -11 }, // 0x25 '%'
- { 76, 13, 13, 14, 0, -11 }, // 0x26 '&'
- { 98, 2, 5, 5, 3, -11 }, // 0x27 '''
- { 100, 5, 16, 6, 1, -11 }, // 0x28 '('
- { 110, 5, 16, 6, -1, -11 }, // 0x29 ')'
- { 120, 8, 8, 9, 1, -11 }, // 0x2A '*'
- { 128, 9, 9, 10, 0, -8 }, // 0x2B '+'
- { 139, 3, 6, 5, -1, -2 }, // 0x2C ','
- { 142, 5, 2, 6, 0, -4 }, // 0x2D '-'
- { 144, 3, 3, 4, 0, -1 }, // 0x2E '.'
- { 146, 7, 12, 6, 0, -11 }, // 0x2F '/'
- { 157, 9, 13, 9, 0, -11 }, // 0x30 '0'
- { 172, 8, 13, 9, 0, -11 }, // 0x31 '1'
- { 185, 9, 13, 9, 0, -11 }, // 0x32 '2'
- { 200, 9, 13, 9, 0, -11 }, // 0x33 '3'
- { 215, 9, 12, 9, 0, -11 }, // 0x34 '4'
- { 229, 9, 13, 9, 0, -11 }, // 0x35 '5'
- { 244, 9, 13, 9, 1, -11 }, // 0x36 '6'
- { 259, 9, 12, 9, 1, -11 }, // 0x37 '7'
- { 273, 8, 13, 9, 0, -11 }, // 0x38 '8'
- { 286, 9, 13, 9, 0, -11 }, // 0x39 '9'
- { 301, 5, 9, 5, 0, -7 }, // 0x3A ':'
- { 307, 5, 11, 5, 0, -7 }, // 0x3B ';'
- { 314, 9, 10, 10, 1, -9 }, // 0x3C '<'
- { 326, 9, 5, 10, 1, -6 }, // 0x3D '='
- { 332, 9, 10, 10, 1, -9 }, // 0x3E '>'
- { 344, 8, 13, 9, 1, -11 }, // 0x3F '?'
- { 357, 13, 13, 15, 1, -12 }, // 0x40 '@'
- { 379, 12, 13, 13, 0, -11 }, // 0x41 'A'
- { 399, 12, 13, 12, 0, -11 }, // 0x42 'B'
- { 419, 12, 13, 11, 1, -11 }, // 0x43 'C'
- { 439, 14, 13, 13, 0, -11 }, // 0x44 'D'
- { 462, 13, 13, 11, 0, -11 }, // 0x45 'E'
- { 484, 13, 13, 11, 0, -11 }, // 0x46 'F'
- { 506, 12, 13, 13, 1, -11 }, // 0x47 'G'
- { 526, 15, 13, 14, 0, -11 }, // 0x48 'H'
- { 551, 8, 13, 7, 0, -11 }, // 0x49 'I'
- { 564, 10, 14, 9, 0, -11 }, // 0x4A 'J'
- { 582, 13, 13, 12, 0, -11 }, // 0x4B 'K'
- { 604, 12, 13, 11, 0, -11 }, // 0x4C 'L'
- { 624, 17, 13, 16, 0, -11 }, // 0x4D 'M'
- { 652, 14, 13, 13, 0, -11 }, // 0x4E 'N'
- { 675, 12, 13, 12, 1, -11 }, // 0x4F 'O'
- { 695, 12, 13, 11, 0, -11 }, // 0x50 'P'
- { 715, 12, 16, 12, 1, -11 }, // 0x51 'Q'
- { 739, 12, 13, 12, 0, -11 }, // 0x52 'R'
- { 759, 9, 13, 9, 0, -11 }, // 0x53 'S'
- { 774, 11, 13, 11, 2, -11 }, // 0x54 'T'
- { 792, 12, 13, 13, 2, -11 }, // 0x55 'U'
- { 812, 12, 12, 13, 2, -11 }, // 0x56 'V'
- { 830, 16, 12, 17, 2, -11 }, // 0x57 'W'
- { 854, 13, 13, 13, 0, -11 }, // 0x58 'X'
- { 876, 11, 13, 11, 2, -11 }, // 0x59 'Y'
- { 894, 11, 13, 10, 0, -11 }, // 0x5A 'Z'
- { 912, 8, 15, 6, -1, -11 }, // 0x5B '['
- { 927, 5, 12, 7, 2, -11 }, // 0x5C '\'
- { 935, 7, 15, 6, -1, -11 }, // 0x5D ']'
- { 949, 8, 7, 10, 1, -11 }, // 0x5E '^'
- { 956, 9, 1, 9, 0, 3 }, // 0x5F '_'
- { 958, 4, 3, 6, 2, -11 }, // 0x60 '`'
- { 960, 9, 9, 9, 0, -7 }, // 0x61 'a'
- { 971, 8, 14, 9, 0, -12 }, // 0x62 'b'
- { 985, 8, 9, 8, 0, -7 }, // 0x63 'c'
- { 994, 10, 14, 9, 0, -12 }, // 0x64 'd'
- { 1012, 7, 9, 7, 0, -7 }, // 0x65 'e'
- { 1020, 11, 17, 9, -2, -12 }, // 0x66 'f'
- { 1044, 9, 12, 9, 0, -7 }, // 0x67 'g'
- { 1058, 9, 14, 10, 0, -12 }, // 0x68 'h'
- { 1074, 5, 13, 5, 1, -11 }, // 0x69 'i'
- { 1083, 9, 16, 6, -1, -11 }, // 0x6A 'j'
- { 1101, 10, 14, 9, 0, -12 }, // 0x6B 'k'
- { 1119, 5, 14, 5, 1, -12 }, // 0x6C 'l'
- { 1128, 13, 9, 14, 0, -7 }, // 0x6D 'm'
- { 1143, 8, 9, 9, 0, -7 }, // 0x6E 'n'
- { 1152, 8, 9, 9, 0, -7 }, // 0x6F 'o'
- { 1161, 10, 12, 9, -2, -7 }, // 0x70 'p'
- { 1176, 9, 12, 9, 0, -7 }, // 0x71 'q'
- { 1190, 8, 8, 7, 0, -7 }, // 0x72 'r'
- { 1198, 6, 9, 6, 0, -7 }, // 0x73 's'
- { 1205, 5, 12, 5, 1, -10 }, // 0x74 't'
- { 1213, 8, 9, 10, 1, -7 }, // 0x75 'u'
- { 1222, 7, 8, 8, 1, -7 }, // 0x76 'v'
- { 1229, 10, 8, 12, 1, -7 }, // 0x77 'w'
- { 1239, 10, 9, 9, -1, -7 }, // 0x78 'x'
- { 1251, 9, 12, 8, -1, -7 }, // 0x79 'y'
- { 1265, 8, 9, 7, 0, -7 }, // 0x7A 'z'
- { 1274, 8, 16, 6, 0, -12 }, // 0x7B '{'
- { 1290, 1, 12, 5, 2, -11 }, // 0x7C '|'
- { 1292, 8, 16, 6, -2, -12 }, // 0x7D '}'
- { 1308, 8, 2, 10, 1, -4 } }; // 0x7E '~'
-
-const GFXfont FreeSerifBoldItalic9pt7b PROGMEM = {
- (uint8_t *)FreeSerifBoldItalic9pt7bBitmaps,
- (GFXglyph *)FreeSerifBoldItalic9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1982 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic12pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic12pt7b.h
deleted file mode 100644
index 52332a7..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic12pt7b.h
+++ /dev/null
@@ -1,271 +0,0 @@
-const uint8_t FreeSerifItalic12pt7bBitmaps[] PROGMEM = {
- 0x0C, 0x31, 0xC6, 0x18, 0x43, 0x0C, 0x20, 0x84, 0x10, 0x03, 0x0C, 0x30,
- 0x66, 0xCD, 0x12, 0x24, 0x51, 0x00, 0x03, 0x10, 0x11, 0x80, 0x8C, 0x0C,
- 0x40, 0x46, 0x1F, 0xFC, 0x21, 0x01, 0x18, 0x18, 0x80, 0x84, 0x3F, 0xF8,
- 0x62, 0x02, 0x30, 0x31, 0x01, 0x08, 0x08, 0xC0, 0x00, 0x40, 0x08, 0x07,
- 0xC0, 0xCA, 0x18, 0xA1, 0x92, 0x19, 0x01, 0xD0, 0x0F, 0x00, 0x78, 0x03,
- 0xC0, 0x2E, 0x02, 0x64, 0x46, 0x44, 0x64, 0x46, 0x64, 0xC1, 0xF0, 0x08,
- 0x00, 0x80, 0x00, 0x08, 0x0F, 0x0C, 0x0C, 0x7C, 0x0C, 0x22, 0x06, 0x12,
- 0x06, 0x09, 0x03, 0x09, 0x01, 0x84, 0x80, 0xC4, 0x8F, 0x3C, 0x4C, 0x40,
- 0x4C, 0x20, 0x4E, 0x10, 0x26, 0x08, 0x23, 0x08, 0x11, 0x84, 0x10, 0xC4,
- 0x08, 0x3C, 0x00, 0x00, 0xE0, 0x02, 0x60, 0x0C, 0xC0, 0x19, 0x80, 0x36,
- 0x00, 0x70, 0x00, 0xC0, 0x07, 0x9F, 0x33, 0x08, 0xC3, 0x13, 0x06, 0x46,
- 0x0D, 0x0C, 0x0C, 0x18, 0x1C, 0x1C, 0x5C, 0x9F, 0x1E, 0xFA, 0xA0, 0x02,
- 0x08, 0x20, 0xC3, 0x06, 0x18, 0x30, 0xE1, 0x83, 0x06, 0x0C, 0x18, 0x30,
- 0x60, 0x40, 0x80, 0x81, 0x00, 0x08, 0x10, 0x10, 0x20, 0x40, 0xC1, 0x83,
- 0x06, 0x0C, 0x18, 0x70, 0xC1, 0x83, 0x0C, 0x10, 0x41, 0x04, 0x00, 0x18,
- 0x18, 0x18, 0x93, 0x74, 0x38, 0xD7, 0x93, 0x18, 0x18, 0x04, 0x00, 0x80,
- 0x10, 0x02, 0x00, 0x41, 0xFF, 0xC1, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10,
- 0x00, 0x6C, 0x95, 0x00, 0xF8, 0xFC, 0x00, 0x40, 0x18, 0x02, 0x00, 0xC0,
- 0x30, 0x06, 0x01, 0x80, 0x20, 0x0C, 0x01, 0x00, 0x60, 0x18, 0x03, 0x00,
- 0xC0, 0x10, 0x06, 0x00, 0x07, 0x81, 0x98, 0x61, 0x18, 0x33, 0x06, 0xC0,
- 0xD8, 0x1B, 0x03, 0xE0, 0xF8, 0x1F, 0x03, 0x60, 0x6C, 0x19, 0x83, 0x10,
- 0xC3, 0x30, 0x3C, 0x00, 0x01, 0x87, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x18,
- 0x0C, 0x06, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30, 0xFE, 0x00,
- 0x0F, 0x0C, 0x64, 0x0C, 0x03, 0x00, 0xC0, 0x20, 0x18, 0x0C, 0x02, 0x01,
- 0x00, 0x80, 0x40, 0x20, 0x10, 0x2F, 0xF0, 0x07, 0x86, 0x30, 0x0C, 0x03,
- 0x01, 0x81, 0x81, 0xF0, 0x1E, 0x03, 0x80, 0x60, 0x18, 0x06, 0x01, 0x00,
- 0xCC, 0x63, 0xE0, 0x00, 0x20, 0x0C, 0x03, 0x80, 0xA0, 0x2C, 0x09, 0x82,
- 0x30, 0x84, 0x31, 0x8C, 0x33, 0x06, 0x7F, 0xE0, 0x30, 0x06, 0x00, 0x80,
- 0x30, 0x03, 0xE1, 0x80, 0x20, 0x06, 0x00, 0xF0, 0x0F, 0x00, 0x60, 0x06,
- 0x00, 0xC0, 0x18, 0x03, 0x00, 0x40, 0x18, 0x02, 0x30, 0x87, 0xE0, 0x00,
- 0x70, 0x3C, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x7F, 0x07, 0x18, 0x60,
- 0xCE, 0x0C, 0xC0, 0xCC, 0x0C, 0xC0, 0xCC, 0x18, 0x41, 0x86, 0x30, 0x3E,
- 0x00, 0x7F, 0xF0, 0x18, 0x03, 0x00, 0xC0, 0x10, 0x06, 0x01, 0x80, 0x30,
- 0x0C, 0x01, 0x00, 0x60, 0x08, 0x03, 0x00, 0xC0, 0x10, 0x06, 0x00, 0x0F,
- 0x83, 0x18, 0xC1, 0x98, 0x33, 0x06, 0x71, 0x87, 0x60, 0x70, 0x17, 0x0C,
- 0x71, 0x07, 0x60, 0x6C, 0x0D, 0x81, 0xB0, 0x63, 0x1C, 0x3E, 0x00, 0x07,
- 0x83, 0x18, 0xC1, 0x18, 0x36, 0x06, 0xC0, 0xD8, 0x1B, 0x07, 0x60, 0xE6,
- 0x38, 0x7F, 0x00, 0xC0, 0x30, 0x0C, 0x07, 0x03, 0xC0, 0xC0, 0x00, 0x33,
- 0x30, 0x00, 0x00, 0xCC, 0xC0, 0x18, 0xC6, 0x00, 0x00, 0x00, 0x03, 0x18,
- 0x44, 0x40, 0x00, 0x00, 0x03, 0x00, 0xF0, 0x38, 0x1E, 0x07, 0x80, 0xE0,
- 0x0F, 0x00, 0x1C, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x00, 0x10, 0xFF, 0xF0,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0x00, 0x0C, 0x00, 0xF0, 0x01,
- 0xC0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x0F, 0x03, 0xC1, 0xE0, 0x78, 0x0E,
- 0x00, 0x80, 0x00, 0x3E, 0x21, 0x90, 0x60, 0x30, 0x38, 0x38, 0x30, 0x30,
- 0x20, 0x20, 0x10, 0x00, 0x00, 0x06, 0x03, 0x01, 0x80, 0x07, 0xE0, 0x1C,
- 0x18, 0x30, 0x04, 0x60, 0x02, 0x61, 0xDA, 0xC3, 0x31, 0xC6, 0x31, 0xC4,
- 0x31, 0xCC, 0x31, 0xCC, 0x21, 0xCC, 0x62, 0x6C, 0xE4, 0x67, 0x38, 0x30,
- 0x00, 0x1C, 0x08, 0x07, 0xF0, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x80, 0x0B,
- 0x00, 0x16, 0x00, 0x4E, 0x00, 0x9C, 0x02, 0x18, 0x08, 0x30, 0x1F, 0xE0,
- 0x40, 0xC1, 0x81, 0xC2, 0x03, 0x8C, 0x07, 0x3C, 0x1F, 0x80, 0x1F, 0xF0,
- 0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x38, 0x60, 0xC3, 0x03, 0xF0,
- 0x1C, 0x30, 0x60, 0x61, 0x81, 0x86, 0x06, 0x38, 0x18, 0xC0, 0xC3, 0x06,
- 0x3F, 0xF0, 0x01, 0xF9, 0x06, 0x0F, 0x1C, 0x06, 0x38, 0x02, 0x30, 0x02,
- 0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
- 0xC0, 0x00, 0xC0, 0x08, 0x60, 0x10, 0x30, 0x60, 0x1F, 0x80, 0x1F, 0xF0,
- 0x07, 0x0C, 0x06, 0x06, 0x06, 0x06, 0x06, 0x03, 0x0E, 0x03, 0x0C, 0x03,
- 0x0C, 0x03, 0x1C, 0x03, 0x1C, 0x07, 0x18, 0x06, 0x18, 0x06, 0x38, 0x0C,
- 0x30, 0x18, 0x30, 0x70, 0xFF, 0x80, 0x1F, 0xFF, 0x07, 0x07, 0x06, 0x02,
- 0x06, 0x02, 0x06, 0x00, 0x0E, 0x10, 0x0C, 0x30, 0x0F, 0xF0, 0x1C, 0x20,
- 0x18, 0x20, 0x18, 0x00, 0x18, 0x00, 0x38, 0x04, 0x30, 0x08, 0x30, 0x38,
- 0xFF, 0xF8, 0x1F, 0xFF, 0x07, 0x07, 0x07, 0x02, 0x06, 0x02, 0x06, 0x00,
- 0x0E, 0x10, 0x0C, 0x30, 0x0F, 0xF0, 0x1C, 0x20, 0x1C, 0x20, 0x18, 0x00,
- 0x18, 0x00, 0x38, 0x00, 0x30, 0x00, 0x30, 0x00, 0xFC, 0x00, 0x01, 0xF1,
- 0x06, 0x0F, 0x18, 0x07, 0x38, 0x02, 0x30, 0x02, 0x60, 0x00, 0x60, 0x00,
- 0xE0, 0x00, 0xC0, 0x7F, 0xC0, 0x1C, 0xC0, 0x1C, 0xC0, 0x18, 0xC0, 0x18,
- 0x60, 0x18, 0x30, 0x38, 0x0F, 0xC0, 0x1F, 0xC7, 0xE0, 0xE0, 0x70, 0x18,
- 0x0E, 0x03, 0x01, 0x80, 0x60, 0x30, 0x1C, 0x0E, 0x03, 0x01, 0x80, 0x7F,
- 0xF0, 0x1C, 0x06, 0x03, 0x01, 0xC0, 0x60, 0x30, 0x0C, 0x06, 0x03, 0x81,
- 0xC0, 0x60, 0x38, 0x0C, 0x06, 0x07, 0xE3, 0xF0, 0x1F, 0x83, 0x81, 0x80,
- 0xC0, 0x60, 0x70, 0x30, 0x18, 0x1C, 0x0C, 0x06, 0x03, 0x03, 0x81, 0x80,
- 0xC1, 0xF8, 0x03, 0xF0, 0x0C, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x18, 0x03,
- 0x80, 0x30, 0x03, 0x00, 0x30, 0x07, 0x00, 0x60, 0x06, 0x0C, 0xE0, 0xCC,
- 0x07, 0x80, 0x1F, 0xCF, 0x83, 0x83, 0x81, 0x81, 0x00, 0xC3, 0x00, 0x62,
- 0x00, 0x72, 0x00, 0x36, 0x00, 0x1E, 0x00, 0x1D, 0x80, 0x0C, 0xE0, 0x06,
- 0x30, 0x03, 0x1C, 0x03, 0x87, 0x01, 0x81, 0x80, 0xC0, 0xE1, 0xF9, 0xFC,
- 0x1F, 0xC0, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x38, 0x00, 0xC0,
- 0x03, 0x00, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x38, 0x0C, 0xC0,
- 0x23, 0x03, 0xBF, 0xFE, 0x0F, 0x00, 0x78, 0x38, 0x07, 0x81, 0xC0, 0x38,
- 0x0E, 0x02, 0xC0, 0x70, 0x3E, 0x05, 0xC1, 0x70, 0x2E, 0x13, 0x01, 0x31,
- 0x98, 0x11, 0x89, 0xC0, 0x8C, 0x8C, 0x04, 0x6C, 0x60, 0x23, 0x43, 0x02,
- 0x1C, 0x38, 0x10, 0xE1, 0x81, 0x86, 0x1C, 0x1F, 0x23, 0xF8, 0x1E, 0x07,
- 0xC1, 0xC0, 0x60, 0x70, 0x10, 0x1C, 0x0C, 0x05, 0x82, 0x02, 0x60, 0x80,
- 0x9C, 0x60, 0x23, 0x10, 0x10, 0xC4, 0x04, 0x19, 0x01, 0x06, 0xC0, 0x40,
- 0xE0, 0x20, 0x38, 0x08, 0x0E, 0x06, 0x01, 0x03, 0xE0, 0x40, 0x01, 0xF0,
- 0x0C, 0x10, 0x30, 0x10, 0xC0, 0x33, 0x00, 0x6E, 0x00, 0xD8, 0x01, 0xF0,
- 0x03, 0xC0, 0x0D, 0x80, 0x1B, 0x00, 0x76, 0x00, 0xCC, 0x03, 0x08, 0x0C,
- 0x18, 0x70, 0x0F, 0x80, 0x1F, 0xF0, 0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06,
- 0x0C, 0x38, 0x30, 0xC1, 0x83, 0x0E, 0x1F, 0xE0, 0x60, 0x01, 0x80, 0x06,
- 0x00, 0x38, 0x00, 0xC0, 0x03, 0x00, 0x3F, 0x00, 0x01, 0xF0, 0x06, 0x10,
- 0x30, 0x30, 0xC0, 0x33, 0x00, 0x66, 0x00, 0xD8, 0x01, 0xB0, 0x03, 0xE0,
- 0x0F, 0x80, 0x1B, 0x00, 0x36, 0x00, 0xCC, 0x03, 0x98, 0x06, 0x18, 0x18,
- 0x18, 0xC0, 0x0E, 0x00, 0x20, 0x01, 0xF8, 0x36, 0x7F, 0x80, 0x1F, 0xF0,
- 0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x38, 0x70, 0xC3, 0x83, 0xF8,
- 0x1D, 0xC0, 0x63, 0x01, 0x8C, 0x06, 0x18, 0x38, 0x60, 0xC1, 0xC3, 0x03,
- 0x3F, 0x0F, 0x07, 0x90, 0xC7, 0x18, 0x21, 0x82, 0x18, 0x01, 0xC0, 0x0E,
- 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xC4, 0x0C, 0x40, 0xC6, 0x08, 0xE1,
- 0x89, 0xE0, 0x7F, 0xFE, 0xC7, 0x1D, 0x0C, 0x14, 0x18, 0x20, 0x70, 0x00,
- 0xE0, 0x01, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60,
- 0x01, 0xC0, 0x03, 0x00, 0x0E, 0x00, 0x7F, 0x80, 0x7E, 0x1F, 0x38, 0x0C,
- 0x38, 0x0C, 0x30, 0x08, 0x30, 0x08, 0x70, 0x08, 0x70, 0x10, 0x60, 0x10,
- 0x60, 0x10, 0xE0, 0x10, 0xC0, 0x20, 0xC0, 0x20, 0xC0, 0x60, 0xC0, 0x40,
- 0x61, 0x80, 0x3F, 0x00, 0xFC, 0x3E, 0xE0, 0x18, 0xC0, 0x21, 0x80, 0xC3,
- 0x81, 0x07, 0x04, 0x0E, 0x08, 0x0C, 0x20, 0x18, 0x80, 0x31, 0x00, 0x64,
- 0x00, 0xF0, 0x01, 0xE0, 0x01, 0x80, 0x02, 0x00, 0x04, 0x00, 0xFD, 0xF8,
- 0xF7, 0x07, 0x06, 0x30, 0x60, 0x63, 0x07, 0x04, 0x30, 0x70, 0x83, 0x8F,
- 0x08, 0x38, 0xB1, 0x03, 0x93, 0x10, 0x19, 0x32, 0x01, 0xA3, 0x20, 0x1A,
- 0x34, 0x01, 0xC3, 0x40, 0x1C, 0x38, 0x01, 0x83, 0x00, 0x18, 0x30, 0x01,
- 0x02, 0x00, 0x1F, 0x9F, 0x0E, 0x06, 0x06, 0x04, 0x07, 0x08, 0x03, 0x10,
- 0x03, 0x20, 0x03, 0xC0, 0x01, 0x80, 0x01, 0xC0, 0x03, 0xC0, 0x06, 0xE0,
- 0x0C, 0x60, 0x18, 0x60, 0x30, 0x70, 0x70, 0x78, 0xF8, 0xFC, 0xFC, 0xFB,
- 0x81, 0x8C, 0x08, 0x60, 0x83, 0x8C, 0x0C, 0xC0, 0x64, 0x03, 0xC0, 0x0C,
- 0x00, 0xE0, 0x07, 0x00, 0x30, 0x01, 0x80, 0x1C, 0x00, 0xC0, 0x1F, 0xC0,
- 0x1F, 0xFE, 0x30, 0x38, 0xC0, 0xF1, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00,
- 0x70, 0x01, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x38, 0x00, 0xE0, 0x01, 0xC0,
- 0x47, 0x01, 0x1C, 0x06, 0x7F, 0xF8, 0x07, 0x04, 0x08, 0x08, 0x08, 0x18,
- 0x10, 0x10, 0x10, 0x20, 0x20, 0x20, 0x20, 0x40, 0x40, 0x40, 0x80, 0x80,
- 0x80, 0xE0, 0xC0, 0xC0, 0x40, 0x60, 0x20, 0x30, 0x30, 0x18, 0x18, 0x08,
- 0x0C, 0x04, 0x06, 0x06, 0x03, 0x03, 0x0E, 0x04, 0x08, 0x10, 0x60, 0x81,
- 0x02, 0x04, 0x18, 0x20, 0x40, 0x81, 0x02, 0x08, 0x10, 0x20, 0x47, 0x80,
- 0x0C, 0x03, 0x81, 0xE0, 0x4C, 0x33, 0x08, 0x66, 0x19, 0x03, 0xC0, 0xC0,
- 0xFF, 0xF0, 0xCE, 0x63, 0x07, 0xA0, 0xCE, 0x18, 0x63, 0x04, 0x60, 0xC6,
- 0x0C, 0xC0, 0xCC, 0x18, 0xC3, 0x8C, 0x5A, 0x79, 0xC0, 0x38, 0x06, 0x01,
- 0x80, 0x40, 0x30, 0x0C, 0xE3, 0xCC, 0xC3, 0x70, 0xD8, 0x36, 0x19, 0x06,
- 0xC3, 0x30, 0x8C, 0xC3, 0xE0, 0x0F, 0x0C, 0xCC, 0x6C, 0x06, 0x06, 0x03,
- 0x01, 0x80, 0xC0, 0x73, 0x1E, 0x00, 0x00, 0x70, 0x01, 0x80, 0x0C, 0x00,
- 0x60, 0x02, 0x03, 0xF0, 0x31, 0x83, 0x08, 0x30, 0xC3, 0x06, 0x18, 0x31,
- 0x81, 0x8C, 0x18, 0x61, 0xCB, 0x16, 0x8F, 0x38, 0x07, 0x19, 0x31, 0x63,
- 0x62, 0xEC, 0xD0, 0xC0, 0xC0, 0xE6, 0x78, 0x00, 0x38, 0x01, 0x30, 0x0C,
- 0x00, 0x20, 0x01, 0x80, 0x06, 0x00, 0xFE, 0x00, 0x40, 0x03, 0x00, 0x0C,
- 0x00, 0x30, 0x00, 0x80, 0x06, 0x00, 0x18, 0x00, 0x60, 0x01, 0x80, 0x04,
- 0x00, 0x30, 0x00, 0xC0, 0x02, 0x00, 0x90, 0x03, 0x80, 0x00, 0x07, 0xC0,
- 0xC7, 0x18, 0x61, 0x86, 0x18, 0xE1, 0x8C, 0x07, 0x80, 0x80, 0x1C, 0x00,
- 0xF0, 0x33, 0x84, 0x18, 0x80, 0x88, 0x08, 0x61, 0x03, 0xE0, 0x1C, 0x00,
- 0xC0, 0x0C, 0x00, 0xC0, 0x18, 0x01, 0x8E, 0x1B, 0x61, 0xC6, 0x38, 0x63,
- 0x8C, 0x30, 0xC3, 0x0C, 0x60, 0xC6, 0x1A, 0x61, 0xA4, 0x1C, 0x18, 0xC6,
- 0x00, 0x0B, 0xC6, 0x23, 0x18, 0x8C, 0x63, 0x5C, 0x01, 0x80, 0xC0, 0x60,
- 0x00, 0x00, 0x0C, 0x1E, 0x02, 0x03, 0x01, 0x80, 0xC0, 0x40, 0x60, 0x30,
- 0x18, 0x08, 0x0C, 0x06, 0x02, 0x1B, 0x0F, 0x00, 0x1C, 0x01, 0x80, 0x30,
- 0x06, 0x01, 0x80, 0x33, 0xC6, 0x30, 0x88, 0x32, 0x06, 0x80, 0xF0, 0x1B,
- 0x06, 0x60, 0xC4, 0x18, 0xD2, 0x0C, 0x3C, 0x61, 0x86, 0x18, 0xC3, 0x0C,
- 0x21, 0x86, 0x18, 0x43, 0x2D, 0x38, 0x78, 0xE7, 0x0D, 0xB5, 0x8D, 0x1C,
- 0xC7, 0x0C, 0x63, 0x8E, 0x31, 0x86, 0x30, 0xC3, 0x18, 0xC1, 0x0C, 0x61,
- 0x84, 0xB0, 0xC6, 0xB0, 0x63, 0x80, 0x78, 0xE1, 0xB6, 0x14, 0x63, 0x84,
- 0x38, 0xC3, 0x0C, 0x70, 0x86, 0x18, 0x61, 0x96, 0x1A, 0xC1, 0xC0, 0x0F,
- 0x06, 0x63, 0x0D, 0x83, 0x60, 0xF0, 0x3C, 0x1B, 0x06, 0xC3, 0x39, 0x87,
- 0x80, 0x1E, 0xF0, 0x39, 0xC1, 0x86, 0x0C, 0x30, 0xC1, 0x86, 0x0C, 0x30,
- 0xC3, 0x06, 0x18, 0x60, 0xC6, 0x07, 0xC0, 0x60, 0x03, 0x00, 0x18, 0x00,
- 0xC0, 0x1F, 0x00, 0x07, 0x81, 0x9C, 0x63, 0x98, 0x76, 0x0C, 0xC1, 0xB0,
- 0x76, 0x0E, 0xC3, 0x98, 0xB1, 0xE6, 0x00, 0x80, 0x30, 0x06, 0x00, 0xC0,
- 0xFC, 0x79, 0x8F, 0xC5, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30,
- 0x10, 0x00, 0x1E, 0x98, 0xCC, 0x27, 0x11, 0x80, 0xE0, 0x39, 0x0C, 0x86,
- 0x62, 0x2E, 0x00, 0x08, 0x67, 0xCC, 0x30, 0xC6, 0x18, 0x61, 0x8C, 0x34,
- 0xE0, 0xF0, 0xCC, 0x19, 0x83, 0x30, 0xC6, 0x18, 0x87, 0x31, 0x66, 0x3C,
- 0xCB, 0x1A, 0x6B, 0x8E, 0x00, 0x70, 0xCC, 0x33, 0x04, 0xC2, 0x18, 0x86,
- 0x41, 0x90, 0x68, 0x1C, 0x06, 0x01, 0x00, 0x61, 0x0F, 0x84, 0x36, 0x30,
- 0xDC, 0xC1, 0x35, 0x08, 0xD4, 0x23, 0x91, 0x0E, 0x48, 0x30, 0xE0, 0xC3,
- 0x02, 0x08, 0x00, 0x0C, 0x63, 0x4A, 0x07, 0x00, 0x70, 0x06, 0x00, 0x20,
- 0x07, 0x00, 0xB0, 0x0B, 0x21, 0x14, 0xE1, 0x80, 0x38, 0x63, 0x0C, 0x30,
- 0x86, 0x10, 0xC4, 0x0C, 0x81, 0xA0, 0x34, 0x07, 0x00, 0x60, 0x08, 0x02,
- 0x00, 0x40, 0x10, 0x04, 0x07, 0x00, 0x1F, 0x90, 0x80, 0x80, 0xC0, 0xC0,
- 0x40, 0x60, 0x60, 0x60, 0x38, 0x3E, 0x03, 0xA0, 0x60, 0x00, 0x83, 0x81,
- 0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x10, 0x10, 0x1C, 0x06, 0x03, 0x03,
- 0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x18, 0x07, 0x00, 0xFF, 0xFF, 0x07,
- 0x00, 0xC0, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x06, 0x06, 0x03, 0x01, 0x80,
- 0x60, 0x40, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x06, 0x06, 0x06, 0x00, 0x78,
- 0x18, 0x8C, 0x0F, 0x00 };
-
-const GFXglyph FreeSerifItalic12pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 6, 16, 8, 1, -15 }, // 0x21 '!'
- { 12, 7, 6, 8, 3, -15 }, // 0x22 '"'
- { 18, 13, 16, 12, 0, -15 }, // 0x23 '#'
- { 44, 12, 20, 12, 0, -17 }, // 0x24 '$'
- { 74, 17, 17, 20, 2, -16 }, // 0x25 '%'
- { 111, 15, 16, 19, 2, -15 }, // 0x26 '&'
- { 141, 2, 6, 5, 4, -15 }, // 0x27 '''
- { 143, 7, 20, 8, 1, -15 }, // 0x28 '('
- { 161, 7, 20, 8, 0, -15 }, // 0x29 ')'
- { 179, 8, 10, 12, 4, -15 }, // 0x2A '*'
- { 189, 11, 11, 16, 2, -10 }, // 0x2B '+'
- { 205, 3, 6, 6, 0, -2 }, // 0x2C ','
- { 208, 5, 1, 8, 1, -5 }, // 0x2D '-'
- { 209, 2, 3, 6, 1, -2 }, // 0x2E '.'
- { 210, 11, 16, 7, 0, -15 }, // 0x2F '/'
- { 232, 11, 17, 12, 1, -16 }, // 0x30 '0'
- { 256, 9, 17, 12, 1, -16 }, // 0x31 '1'
- { 276, 10, 15, 12, 1, -14 }, // 0x32 '2'
- { 295, 10, 16, 12, 1, -15 }, // 0x33 '3'
- { 315, 11, 16, 12, 0, -15 }, // 0x34 '4'
- { 337, 11, 16, 12, 0, -15 }, // 0x35 '5'
- { 359, 12, 17, 12, 1, -16 }, // 0x36 '6'
- { 385, 11, 16, 12, 2, -15 }, // 0x37 '7'
- { 407, 11, 17, 12, 1, -16 }, // 0x38 '8'
- { 431, 11, 17, 12, 1, -16 }, // 0x39 '9'
- { 455, 4, 11, 6, 1, -10 }, // 0x3A ':'
- { 461, 5, 14, 6, 0, -10 }, // 0x3B ';'
- { 470, 12, 13, 14, 1, -12 }, // 0x3C '<'
- { 490, 12, 6, 16, 2, -8 }, // 0x3D '='
- { 499, 12, 13, 14, 2, -12 }, // 0x3E '>'
- { 519, 9, 16, 11, 3, -15 }, // 0x3F '?'
- { 537, 16, 16, 19, 2, -15 }, // 0x40 '@'
- { 569, 15, 15, 16, 0, -14 }, // 0x41 'A'
- { 598, 14, 16, 14, 0, -15 }, // 0x42 'B'
- { 626, 16, 16, 15, 1, -15 }, // 0x43 'C'
- { 658, 16, 16, 17, 0, -15 }, // 0x44 'D'
- { 690, 16, 16, 14, 0, -15 }, // 0x45 'E'
- { 722, 16, 16, 14, 0, -15 }, // 0x46 'F'
- { 754, 16, 16, 17, 1, -15 }, // 0x47 'G'
- { 786, 19, 16, 17, 0, -15 }, // 0x48 'H'
- { 824, 9, 16, 8, 0, -15 }, // 0x49 'I'
- { 842, 12, 16, 10, 0, -15 }, // 0x4A 'J'
- { 866, 17, 16, 15, 0, -15 }, // 0x4B 'K'
- { 900, 14, 16, 14, 0, -15 }, // 0x4C 'L'
- { 928, 21, 16, 20, 0, -15 }, // 0x4D 'M'
- { 970, 18, 16, 16, 0, -15 }, // 0x4E 'N'
- { 1006, 15, 16, 16, 1, -15 }, // 0x4F 'O'
- { 1036, 14, 16, 14, 0, -15 }, // 0x50 'P'
- { 1064, 15, 20, 16, 1, -15 }, // 0x51 'Q'
- { 1102, 14, 16, 15, 0, -15 }, // 0x52 'R'
- { 1130, 12, 16, 11, 0, -15 }, // 0x53 'S'
- { 1154, 15, 16, 14, 2, -15 }, // 0x54 'T'
- { 1184, 16, 16, 17, 3, -15 }, // 0x55 'U'
- { 1216, 15, 16, 16, 3, -15 }, // 0x56 'V'
- { 1246, 20, 16, 21, 3, -15 }, // 0x57 'W'
- { 1286, 16, 16, 16, 0, -15 }, // 0x58 'X'
- { 1318, 13, 16, 14, 3, -15 }, // 0x59 'Y'
- { 1344, 15, 16, 14, 0, -15 }, // 0x5A 'Z'
- { 1374, 8, 20, 9, 1, -15 }, // 0x5B '['
- { 1394, 8, 16, 12, 3, -15 }, // 0x5C '\'
- { 1410, 7, 20, 9, 1, -15 }, // 0x5D ']'
- { 1428, 10, 9, 10, 0, -15 }, // 0x5E '^'
- { 1440, 12, 1, 12, 0, 3 }, // 0x5F '_'
- { 1442, 4, 4, 6, 3, -15 }, // 0x60 '`'
- { 1444, 12, 11, 12, 0, -10 }, // 0x61 'a'
- { 1461, 10, 16, 11, 1, -15 }, // 0x62 'b'
- { 1481, 9, 11, 10, 1, -10 }, // 0x63 'c'
- { 1494, 13, 16, 12, 0, -15 }, // 0x64 'd'
- { 1520, 8, 11, 10, 1, -10 }, // 0x65 'e'
- { 1531, 14, 22, 10, -2, -16 }, // 0x66 'f'
- { 1570, 12, 16, 11, -1, -10 }, // 0x67 'g'
- { 1594, 12, 16, 12, 0, -15 }, // 0x68 'h'
- { 1618, 5, 16, 6, 1, -15 }, // 0x69 'i'
- { 1628, 9, 21, 7, -2, -15 }, // 0x6A 'j'
- { 1652, 11, 16, 11, 0, -15 }, // 0x6B 'k'
- { 1674, 6, 16, 6, 1, -15 }, // 0x6C 'l'
- { 1686, 17, 11, 17, 0, -10 }, // 0x6D 'm'
- { 1710, 12, 11, 12, 0, -10 }, // 0x6E 'n'
- { 1727, 10, 11, 11, 1, -10 }, // 0x6F 'o'
- { 1741, 13, 16, 11, -2, -10 }, // 0x70 'p'
- { 1767, 11, 16, 12, 0, -10 }, // 0x71 'q'
- { 1789, 9, 11, 9, 0, -10 }, // 0x72 'r'
- { 1802, 9, 11, 8, 0, -10 }, // 0x73 's'
- { 1815, 6, 13, 6, 1, -12 }, // 0x74 't'
- { 1825, 11, 11, 12, 1, -10 }, // 0x75 'u'
- { 1841, 10, 11, 11, 1, -10 }, // 0x76 'v'
- { 1855, 14, 11, 16, 2, -10 }, // 0x77 'w'
- { 1875, 12, 11, 10, -1, -10 }, // 0x78 'x'
- { 1892, 11, 16, 11, 0, -10 }, // 0x79 'y'
- { 1914, 9, 13, 9, 0, -10 }, // 0x7A 'z'
- { 1929, 9, 21, 10, 1, -16 }, // 0x7B '{'
- { 1953, 1, 16, 7, 3, -15 }, // 0x7C '|'
- { 1955, 9, 21, 10, 0, -16 }, // 0x7D '}'
- { 1979, 11, 3, 13, 1, -6 } }; // 0x7E '~'
-
-const GFXfont FreeSerifItalic12pt7b PROGMEM = {
- (uint8_t *)FreeSerifItalic12pt7bBitmaps,
- (GFXglyph *)FreeSerifItalic12pt7bGlyphs,
- 0x20, 0x7E, 29 };
-
-// Approx. 2656 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic18pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic18pt7b.h
deleted file mode 100644
index 666ae7e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic18pt7b.h
+++ /dev/null
@@ -1,450 +0,0 @@
-const uint8_t FreeSerifItalic18pt7bBitmaps[] PROGMEM = {
- 0x01, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0x81, 0xE0, 0x70, 0x1C, 0x06, 0x01,
- 0x80, 0xC0, 0x30, 0x0C, 0x02, 0x01, 0x80, 0x40, 0x10, 0x00, 0x00, 0x01,
- 0x80, 0xF0, 0x3C, 0x06, 0x00, 0x38, 0x77, 0x8F, 0x78, 0xF7, 0x0E, 0x60,
- 0xE6, 0x0C, 0xC1, 0x8C, 0x18, 0x81, 0x00, 0x00, 0x60, 0xC0, 0x0C, 0x38,
- 0x03, 0x86, 0x00, 0x60, 0xC0, 0x0C, 0x38, 0x03, 0x06, 0x00, 0x60, 0xC0,
- 0xFF, 0xFF, 0x1F, 0xFF, 0xE0, 0x61, 0xC0, 0x1C, 0x30, 0x03, 0x06, 0x00,
- 0x61, 0xC0, 0x18, 0x30, 0x3F, 0xFF, 0xC7, 0xFF, 0xF8, 0x18, 0x30, 0x03,
- 0x0E, 0x00, 0xE1, 0x80, 0x18, 0x30, 0x03, 0x0C, 0x00, 0xC1, 0x80, 0x18,
- 0x70, 0x00, 0x00, 0x08, 0x00, 0x30, 0x00, 0x40, 0x0F, 0xC0, 0x61, 0xE1,
- 0x86, 0xC6, 0x0D, 0x8C, 0x1A, 0x18, 0x24, 0x38, 0xC0, 0x39, 0x80, 0x7F,
- 0x00, 0x7E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xDC, 0x03, 0x38,
- 0x06, 0x32, 0x0C, 0x64, 0x18, 0xDC, 0x71, 0xB8, 0xC6, 0x39, 0x8C, 0x3F,
- 0x30, 0x1F, 0x80, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0x07, 0x80, 0x60,
- 0x0F, 0xE0, 0xE0, 0x0F, 0x0F, 0xB0, 0x0E, 0x04, 0x30, 0x07, 0x02, 0x18,
- 0x07, 0x01, 0x18, 0x03, 0x00, 0x8C, 0x01, 0x80, 0x8C, 0x00, 0xC0, 0x4C,
- 0x00, 0x60, 0x66, 0x1F, 0x30, 0x66, 0x1F, 0xCC, 0x63, 0x1C, 0x67, 0xE3,
- 0x1C, 0x19, 0xE1, 0x1C, 0x04, 0x01, 0x8C, 0x02, 0x00, 0x8E, 0x01, 0x00,
- 0xC7, 0x00, 0x80, 0xC3, 0x00, 0x80, 0x61, 0x80, 0xC0, 0x60, 0xC0, 0xC0,
- 0x20, 0x70, 0xE0, 0x30, 0x1F, 0xC0, 0x10, 0x07, 0xC0, 0x00, 0x1E, 0x00,
- 0x00, 0xFC, 0x00, 0x07, 0x18, 0x00, 0x18, 0x60, 0x00, 0xE1, 0x80, 0x03,
- 0x8C, 0x00, 0x0E, 0x60, 0x00, 0x3B, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x80,
- 0x00, 0x7F, 0x1F, 0xC3, 0x3C, 0x1C, 0x38, 0x70, 0x61, 0xE1, 0xE3, 0x87,
- 0x07, 0x8C, 0x3C, 0x0F, 0x60, 0xF0, 0x3D, 0x03, 0xC0, 0x78, 0x0F, 0x01,
- 0xE0, 0x3E, 0x07, 0xC0, 0x7C, 0x77, 0x84, 0xFF, 0x8F, 0xE1, 0xF8, 0x0F,
- 0x00, 0x3B, 0xDE, 0xE7, 0x33, 0x18, 0x80, 0x00, 0x80, 0x80, 0x80, 0x80,
- 0xC0, 0xC0, 0xE0, 0x60, 0x70, 0x38, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x01,
- 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x01, 0x00, 0x80, 0x40, 0x30,
- 0x08, 0x04, 0x02, 0x00, 0x04, 0x01, 0x00, 0x80, 0x60, 0x10, 0x08, 0x04,
- 0x03, 0x01, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x81,
- 0x80, 0xC0, 0xE0, 0x60, 0x30, 0x30, 0x18, 0x18, 0x08, 0x08, 0x08, 0x08,
- 0x00, 0x06, 0x00, 0x60, 0x06, 0x0C, 0x43, 0xE4, 0xF1, 0x58, 0x0E, 0x00,
- 0xF0, 0x74, 0xEE, 0x47, 0xC4, 0x30, 0x60, 0x06, 0x00, 0x60, 0x01, 0x80,
- 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,
- 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,
- 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x31, 0xCE,
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- 0x30, 0x07, 0x00, 0x70, 0x06, 0x00, 0x60, 0x0E, 0x00, 0xE0, 0x0C, 0x00,
- 0xC0, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0xC0, 0x06,
- 0x00, 0x30, 0x03, 0x00, 0x30, 0x03, 0x00, 0x70, 0x07, 0x00, 0x70, 0x06,
- 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0C, 0x00, 0x40, 0x04, 0x00, 0xC0, 0x1E,
- 0x03, 0x80, 0x38, 0x03, 0x00, 0x70, 0x07, 0x00, 0x70, 0x06, 0x00, 0xE0,
- 0x0E, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x70, 0x00, 0x1E, 0x00, 0x3F, 0xE1,
- 0xF8, 0x7F, 0xC0, 0x07, 0x80 };
-
-const GFXglyph FreeSerifItalic18pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 9, 0, 1 }, // 0x20 ' '
- { 0, 10, 23, 12, 1, -22 }, // 0x21 '!'
- { 29, 12, 9, 12, 4, -22 }, // 0x22 '"'
- { 43, 19, 23, 17, 0, -22 }, // 0x23 '#'
- { 98, 15, 29, 17, 1, -25 }, // 0x24 '$'
- { 153, 25, 23, 29, 3, -22 }, // 0x25 '%'
- { 225, 22, 23, 27, 3, -22 }, // 0x26 '&'
- { 289, 5, 9, 7, 4, -22 }, // 0x27 '''
- { 295, 9, 29, 12, 1, -22 }, // 0x28 '('
- { 328, 9, 29, 12, 1, -22 }, // 0x29 ')'
- { 361, 12, 14, 18, 5, -22 }, // 0x2A '*'
- { 382, 16, 18, 24, 4, -17 }, // 0x2B '+'
- { 418, 5, 8, 9, -1, -2 }, // 0x2C ','
- { 423, 8, 2, 12, 2, -8 }, // 0x2D '-'
- { 425, 4, 4, 9, 1, -3 }, // 0x2E '.'
- { 427, 16, 23, 10, 0, -22 }, // 0x2F '/'
- { 473, 17, 24, 17, 1, -23 }, // 0x30 '0'
- { 524, 12, 24, 17, 2, -23 }, // 0x31 '1'
- { 560, 16, 23, 17, 1, -22 }, // 0x32 '2'
- { 606, 17, 24, 18, 0, -23 }, // 0x33 '3'
- { 657, 17, 24, 17, 0, -23 }, // 0x34 '4'
- { 708, 16, 23, 18, 0, -22 }, // 0x35 '5'
- { 754, 17, 24, 18, 1, -23 }, // 0x36 '6'
- { 805, 16, 23, 17, 3, -22 }, // 0x37 '7'
- { 851, 16, 24, 18, 1, -23 }, // 0x38 '8'
- { 899, 16, 24, 17, 1, -23 }, // 0x39 '9'
- { 947, 7, 15, 9, 2, -14 }, // 0x3A ':'
- { 961, 9, 20, 9, 1, -14 }, // 0x3B ';'
- { 984, 18, 18, 20, 2, -17 }, // 0x3C '<'
- { 1025, 18, 9, 23, 3, -12 }, // 0x3D '='
- { 1046, 18, 18, 20, 2, -17 }, // 0x3E '>'
- { 1087, 12, 23, 16, 4, -22 }, // 0x3F '?'
- { 1122, 24, 23, 27, 2, -22 }, // 0x40 '@'
- { 1191, 21, 23, 23, 0, -22 }, // 0x41 'A'
- { 1252, 21, 23, 21, 0, -22 }, // 0x42 'B'
- { 1313, 21, 23, 21, 2, -22 }, // 0x43 'C'
- { 1374, 25, 23, 25, 0, -22 }, // 0x44 'D'
- { 1446, 22, 23, 20, 0, -22 }, // 0x45 'E'
- { 1510, 22, 23, 20, 0, -22 }, // 0x46 'F'
- { 1574, 23, 23, 24, 2, -22 }, // 0x47 'G'
- { 1641, 27, 23, 25, 0, -22 }, // 0x48 'H'
- { 1719, 14, 23, 11, 0, -22 }, // 0x49 'I'
- { 1760, 17, 23, 15, 0, -22 }, // 0x4A 'J'
- { 1809, 25, 23, 22, 0, -22 }, // 0x4B 'K'
- { 1881, 20, 23, 20, 0, -22 }, // 0x4C 'L'
- { 1939, 31, 23, 29, 0, -22 }, // 0x4D 'M'
- { 2029, 26, 23, 24, 0, -22 }, // 0x4E 'N'
- { 2104, 23, 23, 23, 1, -22 }, // 0x4F 'O'
- { 2171, 22, 23, 20, 0, -22 }, // 0x50 'P'
- { 2235, 23, 29, 23, 1, -22 }, // 0x51 'Q'
- { 2319, 21, 23, 22, 0, -22 }, // 0x52 'R'
- { 2380, 17, 23, 16, 0, -22 }, // 0x53 'S'
- { 2429, 20, 23, 21, 3, -22 }, // 0x54 'T'
- { 2487, 23, 23, 25, 4, -22 }, // 0x55 'U'
- { 2554, 21, 23, 23, 5, -22 }, // 0x56 'V'
- { 2615, 29, 23, 31, 5, -22 }, // 0x57 'W'
- { 2699, 24, 23, 23, 0, -22 }, // 0x58 'X'
- { 2768, 19, 23, 21, 4, -22 }, // 0x59 'Y'
- { 2823, 22, 23, 20, 0, -22 }, // 0x5A 'Z'
- { 2887, 13, 28, 14, 1, -22 }, // 0x5B '['
- { 2933, 12, 23, 17, 4, -22 }, // 0x5C '\'
- { 2968, 12, 28, 14, 1, -22 }, // 0x5D ']'
- { 3010, 15, 13, 15, 0, -22 }, // 0x5E '^'
- { 3035, 18, 2, 17, 0, 3 }, // 0x5F '_'
- { 3040, 6, 6, 9, 5, -22 }, // 0x60 '`'
- { 3045, 15, 15, 17, 1, -14 }, // 0x61 'a'
- { 3074, 16, 24, 17, 1, -23 }, // 0x62 'b'
- { 3122, 13, 15, 14, 1, -14 }, // 0x63 'c'
- { 3147, 17, 24, 18, 1, -23 }, // 0x64 'd'
- { 3198, 13, 15, 14, 1, -14 }, // 0x65 'e'
- { 3223, 20, 31, 15, -3, -23 }, // 0x66 'f'
- { 3301, 16, 22, 15, -1, -14 }, // 0x67 'g'
- { 3345, 16, 24, 17, 1, -23 }, // 0x68 'h'
- { 3393, 9, 23, 9, 1, -22 }, // 0x69 'i'
- { 3419, 15, 30, 10, -3, -22 }, // 0x6A 'j'
- { 3476, 15, 24, 16, 1, -23 }, // 0x6B 'k'
- { 3521, 8, 25, 9, 1, -23 }, // 0x6C 'l'
- { 3546, 24, 15, 25, 0, -14 }, // 0x6D 'm'
- { 3591, 17, 15, 17, 0, -14 }, // 0x6E 'n'
- { 3623, 15, 15, 17, 1, -14 }, // 0x6F 'o'
- { 3652, 20, 22, 16, -3, -14 }, // 0x70 'p'
- { 3707, 16, 22, 17, 1, -14 }, // 0x71 'q'
- { 3751, 13, 15, 13, 1, -14 }, // 0x72 'r'
- { 3776, 13, 15, 12, 0, -14 }, // 0x73 's'
- { 3801, 9, 18, 8, 1, -17 }, // 0x74 't'
- { 3822, 15, 15, 17, 1, -14 }, // 0x75 'u'
- { 3851, 14, 15, 16, 2, -14 }, // 0x76 'v'
- { 3878, 22, 15, 24, 1, -14 }, // 0x77 'w'
- { 3920, 16, 15, 15, -1, -14 }, // 0x78 'x'
- { 3950, 16, 22, 16, 0, -14 }, // 0x79 'y'
- { 3994, 14, 18, 14, 0, -14 }, // 0x7A 'z'
- { 4026, 12, 30, 14, 2, -23 }, // 0x7B '{'
- { 4071, 2, 23, 10, 4, -22 }, // 0x7C '|'
- { 4077, 12, 31, 14, 0, -24 }, // 0x7D '}'
- { 4124, 17, 4, 19, 1, -10 } }; // 0x7E '~'
-
-const GFXfont FreeSerifItalic18pt7b PROGMEM = {
- (uint8_t *)FreeSerifItalic18pt7bBitmaps,
- (GFXglyph *)FreeSerifItalic18pt7bGlyphs,
- 0x20, 0x7E, 42 };
-
-// Approx. 4805 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic24pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic24pt7b.h
deleted file mode 100644
index 75da1e0..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic24pt7b.h
+++ /dev/null
@@ -1,737 +0,0 @@
-const uint8_t FreeSerifItalic24pt7bBitmaps[] PROGMEM = {
- 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x01, 0xF0, 0x1E, 0x01, 0xE0, 0x1C,
- 0x01, 0xC0, 0x3C, 0x03, 0x80, 0x38, 0x03, 0x80, 0x30, 0x07, 0x00, 0x60,
- 0x06, 0x00, 0x60, 0x04, 0x00, 0x40, 0x0C, 0x00, 0x80, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xF8, 0x0F, 0x80, 0xF8, 0x07, 0x00,
- 0x38, 0x1D, 0xE0, 0x77, 0x83, 0xDC, 0x0E, 0x70, 0x39, 0xC1, 0xEE, 0x07,
- 0x38, 0x1C, 0xC0, 0x63, 0x01, 0x8C, 0x06, 0x20, 0x10, 0x00, 0x06, 0x03,
- 0x00, 0x07, 0x03, 0x80, 0x03, 0x81, 0xC0, 0x03, 0x81, 0xC0, 0x01, 0xC0,
- 0xE0, 0x00, 0xE0, 0x70, 0x00, 0xE0, 0x70, 0x00, 0x70, 0x38, 0x00, 0x30,
- 0x18, 0x00, 0x38, 0x1C, 0x03, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xF0, 0x0E,
- 0x07, 0x00, 0x06, 0x03, 0x00, 0x07, 0x03, 0x80, 0x03, 0x81, 0xC0, 0x03,
- 0x81, 0xC0, 0x01, 0xC0, 0xE0, 0x00, 0xE0, 0x70, 0x1F, 0xFF, 0xFF, 0x8F,
- 0xFF, 0xFF, 0x80, 0x70, 0x38, 0x00, 0x38, 0x1C, 0x00, 0x1C, 0x0C, 0x00,
- 0x1C, 0x0E, 0x00, 0x0E, 0x07, 0x00, 0x0E, 0x07, 0x00, 0x07, 0x03, 0x80,
- 0x03, 0x81, 0xC0, 0x03, 0x81, 0xC0, 0x01, 0xC0, 0xE0, 0x00, 0x00, 0x01,
- 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0xFF, 0x80, 0x1C, 0x2F, 0x01,
- 0x83, 0x3C, 0x1C, 0x18, 0xE1, 0xC0, 0xC3, 0x0E, 0x06, 0x18, 0x70, 0x60,
- 0x83, 0x83, 0x04, 0x1E, 0x18, 0x00, 0xF8, 0xC0, 0x03, 0xEC, 0x00, 0x0F,
- 0xE0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0,
- 0x00, 0x7F, 0x00, 0x03, 0x7C, 0x00, 0x19, 0xE0, 0x01, 0x87, 0x80, 0x0C,
- 0x3C, 0x00, 0x60, 0xE2, 0x03, 0x07, 0x10, 0x30, 0x39, 0x81, 0x81, 0xCE,
- 0x0C, 0x0C, 0x70, 0x60, 0xE3, 0xC6, 0x06, 0x0F, 0x30, 0x60, 0x1F, 0x9E,
- 0x00, 0x3F, 0x80, 0x00, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01,
- 0x80, 0x00, 0x01, 0xF0, 0x00, 0xC0, 0x03, 0xFE, 0x01, 0xE0, 0x03, 0xC7,
- 0x83, 0xE0, 0x03, 0xC0, 0x7F, 0x60, 0x03, 0xC0, 0x20, 0x70, 0x01, 0xC0,
- 0x10, 0x30, 0x01, 0xE0, 0x08, 0x38, 0x00, 0xE0, 0x04, 0x18, 0x00, 0xF0,
- 0x02, 0x1C, 0x00, 0x70, 0x02, 0x0C, 0x00, 0x38, 0x01, 0x0E, 0x00, 0x1C,
- 0x01, 0x8E, 0x00, 0x0E, 0x00, 0x86, 0x00, 0x07, 0x00, 0x87, 0x03, 0xE1,
- 0x80, 0xC3, 0x07, 0xFC, 0xE1, 0xC3, 0x87, 0xC6, 0x3F, 0x81, 0x87, 0x81,
- 0x8F, 0x81, 0xC7, 0x80, 0x40, 0x00, 0xC3, 0xC0, 0x20, 0x00, 0xE3, 0xC0,
- 0x10, 0x00, 0x61, 0xC0, 0x08, 0x00, 0x61, 0xE0, 0x04, 0x00, 0x70, 0xF0,
- 0x06, 0x00, 0x30, 0x70, 0x02, 0x00, 0x38, 0x38, 0x03, 0x00, 0x18, 0x1C,
- 0x01, 0x00, 0x1C, 0x0E, 0x01, 0x80, 0x0C, 0x07, 0x01, 0x80, 0x0E, 0x01,
- 0xC3, 0x80, 0x06, 0x00, 0x7F, 0x80, 0x06, 0x00, 0x1F, 0x00, 0x07, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x71,
- 0xC0, 0x00, 0x01, 0xC3, 0x80, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x38, 0x38,
- 0x00, 0x01, 0xE0, 0xE0, 0x00, 0x07, 0x87, 0x00, 0x00, 0x1E, 0x18, 0x00,
- 0x00, 0x78, 0xC0, 0x00, 0x01, 0xE6, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00,
- 0x1F, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x00, 0x7F,
- 0xC1, 0xFE, 0x03, 0x9F, 0x03, 0xE0, 0x3C, 0x3C, 0x07, 0x01, 0xE0, 0xF8,
- 0x1C, 0x0F, 0x03, 0xE0, 0xE0, 0x7C, 0x07, 0x83, 0x01, 0xE0, 0x1F, 0x1C,
- 0x07, 0x80, 0x7C, 0x60, 0x3E, 0x00, 0xFB, 0x00, 0xF8, 0x03, 0xFC, 0x03,
- 0xE0, 0x07, 0xE0, 0x0F, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x3E, 0x00, 0x7C,
- 0x00, 0xFC, 0x01, 0xF8, 0x0F, 0xF0, 0x03, 0xF0, 0xF3, 0xF0, 0x87, 0xFF,
- 0x07, 0xFC, 0x07, 0xF0, 0x07, 0xC0, 0x39, 0xDE, 0xE7, 0x3B, 0x9C, 0xC6,
- 0x31, 0x00, 0x00, 0x10, 0x01, 0x00, 0x18, 0x01, 0x80, 0x18, 0x01, 0x80,
- 0x1C, 0x00, 0xC0, 0x0E, 0x00, 0xE0, 0x07, 0x00, 0x78, 0x03, 0x80, 0x3C,
- 0x01, 0xE0, 0x0E, 0x00, 0x70, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0E, 0x00,
- 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E,
- 0x00, 0x30, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x01, 0x80, 0x0C, 0x00, 0x60,
- 0x01, 0x00, 0x0C, 0x00, 0x20, 0x00, 0x00, 0x80, 0x06, 0x00, 0x10, 0x00,
- 0x80, 0x06, 0x00, 0x30, 0x00, 0xC0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x0C,
- 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0,
- 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xC0, 0x1E, 0x00, 0xF0, 0x07,
- 0x80, 0x38, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x0E, 0x00, 0x60, 0x07, 0x00,
- 0x30, 0x03, 0x00, 0x30, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00, 0x01, 0x00,
- 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0xE1, 0x07, 0xE1, 0x0F,
- 0xF1, 0x1F, 0x19, 0x30, 0x07, 0xC0, 0x03, 0x80, 0x0D, 0x60, 0x79, 0x3C,
- 0xF1, 0x1F, 0xE1, 0x0F, 0xE1, 0x07, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80,
- 0x03, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01,
- 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C,
- 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xE0, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00,
- 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00,
- 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x7C, 0xF9,
- 0xF1, 0xE1, 0xC3, 0x0C, 0x10, 0xC1, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0x00,
- 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x80, 0x00, 0x3C,
- 0x00, 0x01, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00,
- 0xF0, 0x00, 0x07, 0x00, 0x00, 0x78, 0x00, 0x03, 0x80, 0x00, 0x3C, 0x00,
- 0x01, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x70,
- 0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x3C, 0x00, 0x01,
- 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x70, 0x00,
- 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0,
- 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x03, 0x86,
- 0x00, 0x30, 0x18, 0x03, 0x00, 0xC0, 0x38, 0x03, 0x03, 0x80, 0x18, 0x38,
- 0x00, 0xC1, 0xC0, 0x07, 0x1C, 0x00, 0x38, 0xE0, 0x01, 0xCF, 0x00, 0x0E,
- 0x70, 0x00, 0x77, 0x80, 0x07, 0xBC, 0x00, 0x3D, 0xE0, 0x01, 0xEE, 0x00,
- 0x0F, 0xF0, 0x00, 0x77, 0x80, 0x07, 0xBC, 0x00, 0x3D, 0xC0, 0x01, 0xCE,
- 0x00, 0x1E, 0x70, 0x00, 0xF3, 0x80, 0x07, 0x1C, 0x00, 0x78, 0xE0, 0x03,
- 0x83, 0x00, 0x38, 0x18, 0x03, 0x80, 0xE0, 0x18, 0x03, 0x01, 0x80, 0x0C,
- 0x38, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0xC0, 0x3F, 0xE0,
- 0x01, 0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x1E,
- 0x00, 0x0F, 0x00, 0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,
- 0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x1E, 0x00,
- 0x0F, 0x00, 0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x01, 0xE0,
- 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0x01, 0xFF,
- 0xF0, 0x00, 0x3F, 0x00, 0x07, 0xFE, 0x00, 0x7F, 0xF8, 0x07, 0x07, 0xE0,
- 0x60, 0x1F, 0x06, 0x00, 0x7C, 0x20, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00,
- 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x0E, 0x00,
- 0x00, 0xF0, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0x70,
- 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x03,
- 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x01, 0x03, 0x00, 0x08,
- 0x30, 0x00, 0xC3, 0xFF, 0xFC, 0x3F, 0xFF, 0xE3, 0xFF, 0xFE, 0x00, 0x00,
- 0x0F, 0xC0, 0x00, 0xFF, 0xC0, 0x06, 0x0F, 0x80, 0x30, 0x1E, 0x01, 0x80,
- 0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x78,
- 0x00, 0x01, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x0E, 0x00, 0x01,
- 0xF8, 0x00, 0x3F, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x0F,
- 0x80, 0x00, 0x3E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00, 0x07, 0x80,
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- 0x03, 0x80, 0xF0, 0x38, 0x03, 0xC3, 0x00, 0x07, 0xE0, 0x00, 0x00, 0x3C,
- 0x3F, 0x00, 0x7F, 0x8F, 0xF0, 0x01, 0xF7, 0x3F, 0x00, 0x1D, 0x83, 0xF0,
- 0x07, 0xA0, 0x3E, 0x00, 0xF8, 0x07, 0xC0, 0x1E, 0x00, 0xF8, 0x03, 0xC0,
- 0x1F, 0x00, 0xF0, 0x03, 0xE0, 0x1E, 0x00, 0x7C, 0x03, 0xC0, 0x1F, 0x00,
- 0x70, 0x03, 0xE0, 0x1E, 0x00, 0x78, 0x03, 0xC0, 0x1F, 0x00, 0x70, 0x03,
- 0xC0, 0x0E, 0x00, 0xF8, 0x03, 0xC0, 0x1E, 0x00, 0x78, 0x07, 0x80, 0x0F,
- 0x01, 0xE0, 0x01, 0xE0, 0x70, 0x00, 0x7C, 0x3C, 0x00, 0x0F, 0x7C, 0x00,
- 0x01, 0xC0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xE0,
- 0x00, 0x00, 0x38, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x00,
- 0x7E, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x03, 0x8D,
- 0xC0, 0x38, 0x2E, 0x07, 0x80, 0xF0, 0x78, 0x07, 0x03, 0x80, 0x38, 0x38,
- 0x03, 0xC3, 0xC0, 0x1E, 0x3C, 0x00, 0xE1, 0xE0, 0x07, 0x1E, 0x00, 0x78,
- 0xF0, 0x03, 0x87, 0x80, 0x3C, 0x78, 0x01, 0xE3, 0xC0, 0x1F, 0x1E, 0x01,
- 0x70, 0xF0, 0x17, 0x87, 0x80, 0xBC, 0x3C, 0x09, 0xC0, 0xF1, 0x8E, 0x07,
- 0xF8, 0xF0, 0x1F, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x1E,
- 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00,
- 0x3E, 0x00, 0x0F, 0xFE, 0x00, 0x07, 0x87, 0x3F, 0x87, 0xC3, 0xC7, 0xE1,
- 0xE6, 0xF0, 0xF6, 0x00, 0x72, 0x00, 0x3A, 0x00, 0x1D, 0x00, 0x1F, 0x00,
- 0x0E, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0,
- 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0F,
- 0x00, 0x00, 0x01, 0xF8, 0x81, 0x87, 0xC1, 0x80, 0xE1, 0xC0, 0x60, 0xE0,
- 0x10, 0x70, 0x08, 0x3C, 0x04, 0x1F, 0x00, 0x07, 0xC0, 0x03, 0xE0, 0x00,
- 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x00, 0x03, 0xC1, 0x01, 0xE0, 0x80, 0x70,
- 0x40, 0x38, 0x30, 0x1C, 0x38, 0x0C, 0x1C, 0x0E, 0x0F, 0x0E, 0x04, 0x7C,
- 0x00, 0x00, 0xC0, 0x18, 0x03, 0x80, 0x78, 0x1F, 0x03, 0xFF, 0x7F, 0xF0,
- 0xF0, 0x0E, 0x00, 0xE0, 0x1E, 0x01, 0xE0, 0x1C, 0x01, 0xC0, 0x3C, 0x03,
- 0xC0, 0x38, 0x03, 0x80, 0x78, 0x07, 0x80, 0x70, 0x8F, 0x10, 0xF1, 0x0F,
- 0x20, 0xFC, 0x07, 0x80, 0x00, 0x00, 0x00, 0xF0, 0x0E, 0x7F, 0x00, 0xE0,
- 0xF0, 0x1E, 0x0E, 0x01, 0xE1, 0xE0, 0x3C, 0x1E, 0x03, 0xC1, 0xE0, 0x3C,
- 0x1C, 0x07, 0xC3, 0xC0, 0x78, 0x3C, 0x0F, 0x83, 0xC0, 0xB8, 0x38, 0x1F,
- 0x87, 0x83, 0x70, 0x78, 0x27, 0x07, 0x86, 0x70, 0x70, 0xC7, 0x1F, 0x08,
- 0xE1, 0xE1, 0x0E, 0x2E, 0x60, 0xE4, 0xFC, 0x0F, 0x87, 0x00, 0x70, 0x1C,
- 0x03, 0xBF, 0x00, 0xF1, 0xE0, 0x3C, 0x78, 0x07, 0x1E, 0x00, 0xC3, 0x80,
- 0x30, 0xE0, 0x08, 0x38, 0x06, 0x0E, 0x01, 0x03, 0x80, 0xC0, 0xF0, 0x20,
- 0x3C, 0x10, 0x07, 0x04, 0x01, 0xC2, 0x00, 0x71, 0x00, 0x1C, 0xC0, 0x07,
- 0x60, 0x01, 0xF0, 0x00, 0x78, 0x00, 0x1C, 0x00, 0x06, 0x00, 0x01, 0x00,
- 0x00, 0x0C, 0x00, 0x40, 0x3B, 0xF8, 0x01, 0x00, 0xF1, 0xE0, 0x0C, 0x03,
- 0xC3, 0x80, 0x78, 0x07, 0x0E, 0x01, 0xE0, 0x0C, 0x38, 0x0F, 0x80, 0x20,
- 0xE0, 0x6E, 0x00, 0x83, 0x81, 0x38, 0x04, 0x0F, 0x0C, 0xE0, 0x10, 0x1C,
- 0x23, 0x80, 0x80, 0x71, 0x8E, 0x06, 0x01, 0xCC, 0x38, 0x10, 0x07, 0x20,
- 0xE0, 0x80, 0x1D, 0x83, 0x86, 0x00, 0x7C, 0x07, 0x30, 0x01, 0xF0, 0x1C,
- 0x80, 0x07, 0x80, 0x74, 0x00, 0x1E, 0x01, 0xF0, 0x00, 0x70, 0x07, 0x80,
- 0x01, 0xC0, 0x1C, 0x00, 0x06, 0x00, 0x60, 0x00, 0x10, 0x01, 0x00, 0x00,
- 0x00, 0xE0, 0x38, 0x1F, 0x81, 0xF0, 0x8F, 0x09, 0x80, 0x3C, 0x40, 0x00,
- 0x72, 0x00, 0x01, 0xD0, 0x00, 0x07, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x38,
- 0x00, 0x00, 0xE0, 0x00, 0x03, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x7C, 0x00,
- 0x01, 0x70, 0x00, 0x09, 0xC0, 0x00, 0x67, 0x00, 0x01, 0x1E, 0x10, 0x08,
- 0x38, 0x40, 0x40, 0xE2, 0x39, 0x03, 0xD0, 0xF8, 0x0F, 0x83, 0xC0, 0x1C,
- 0x00, 0x07, 0x80, 0x33, 0xFC, 0x03, 0xC1, 0xE0, 0x1E, 0x07, 0x80, 0x70,
- 0x3C, 0x01, 0x80, 0xE0, 0x0C, 0x07, 0x80, 0x40, 0x3C, 0x02, 0x00, 0xE0,
- 0x20, 0x07, 0x81, 0x00, 0x3C, 0x18, 0x01, 0xE0, 0x80, 0x07, 0x0C, 0x00,
- 0x38, 0x40, 0x01, 0xE4, 0x00, 0x0F, 0x60, 0x00, 0x3A, 0x00, 0x01, 0xF0,
- 0x00, 0x0F, 0x00, 0x00, 0x70, 0x00, 0x03, 0x80, 0x00, 0x18, 0x00, 0x00,
- 0x80, 0x00, 0x0C, 0x00, 0x00, 0x40, 0x00, 0x04, 0x00, 0x00, 0x40, 0x00,
- 0x04, 0x00, 0x0E, 0x40, 0x00, 0x7C, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x0F,
- 0xFF, 0x87, 0xFF, 0x82, 0x00, 0x83, 0x00, 0xC1, 0x00, 0xC0, 0x00, 0xC0,
- 0x00, 0xC0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x20,
- 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x18, 0x00, 0x1E,
- 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xE8, 0xFC, 0x70, 0x1E, 0x38, 0x03, 0x88,
- 0x00, 0x78, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x0F,
- 0x00, 0x07, 0x80, 0x03, 0x80, 0x01, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00,
- 0x70, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x0F, 0x00,
- 0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0xC0, 0x00, 0x80,
- 0x00, 0x60, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x07,
- 0x80, 0x03, 0x80, 0x01, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x70, 0x00,
- 0x38, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x01, 0x80,
- 0x00, 0x70, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0x18, 0x00, 0x0E, 0x00, 0x06, 0x00, 0x07,
- 0x00, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0E,
- 0x00, 0x0E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3C,
- 0x00, 0x3C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x18, 0x00, 0x08, 0x00, 0x1C,
- 0x00, 0x7E, 0x00, 0x78, 0x00, 0xF0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xE0,
- 0x01, 0xC0, 0x01, 0xC0, 0x03, 0xC0, 0x03, 0x80, 0x03, 0x80, 0x07, 0x80,
- 0x07, 0x80, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x1C, 0x00,
- 0xF8, 0x00, 0x1F, 0x80, 0x00, 0xFF, 0x80, 0xC7, 0xFF, 0x87, 0xBC, 0x3F,
- 0xFE, 0x60, 0x3F, 0xF0, 0x00, 0x1F, 0x00 };
-
-const GFXglyph FreeSerifItalic24pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 12, 0, 1 }, // 0x20 ' '
- { 0, 12, 32, 16, 2, -30 }, // 0x21 '!'
- { 48, 14, 12, 16, 6, -31 }, // 0x22 '"'
- { 69, 25, 31, 23, 0, -30 }, // 0x23 '#'
- { 166, 21, 38, 24, 2, -33 }, // 0x24 '$'
- { 266, 33, 32, 39, 4, -30 }, // 0x25 '%'
- { 398, 30, 33, 37, 4, -31 }, // 0x26 '&'
- { 522, 5, 12, 9, 6, -31 }, // 0x27 '''
- { 530, 13, 39, 16, 2, -30 }, // 0x28 '('
- { 594, 13, 39, 16, 0, -30 }, // 0x29 ')'
- { 658, 16, 20, 23, 7, -31 }, // 0x2A '*'
- { 698, 23, 23, 32, 4, -22 }, // 0x2B '+'
- { 765, 7, 11, 12, -1, -4 }, // 0x2C ','
- { 775, 11, 3, 16, 2, -11 }, // 0x2D '-'
- { 780, 5, 5, 12, 1, -3 }, // 0x2E '.'
- { 784, 21, 33, 14, 0, -31 }, // 0x2F '/'
- { 871, 21, 31, 23, 2, -30 }, // 0x30 '0'
- { 953, 17, 32, 23, 2, -31 }, // 0x31 '1'
- { 1021, 21, 31, 24, 0, -30 }, // 0x32 '2'
- { 1103, 22, 32, 23, 0, -31 }, // 0x33 '3'
- { 1191, 22, 32, 23, 0, -31 }, // 0x34 '4'
- { 1279, 22, 32, 24, 0, -31 }, // 0x35 '5'
- { 1367, 23, 32, 23, 1, -31 }, // 0x36 '6'
- { 1459, 21, 32, 23, 4, -31 }, // 0x37 '7'
- { 1543, 22, 32, 23, 1, -31 }, // 0x38 '8'
- { 1631, 22, 33, 23, 1, -31 }, // 0x39 '9'
- { 1722, 9, 22, 12, 2, -20 }, // 0x3A ':'
- { 1747, 11, 27, 12, 1, -20 }, // 0x3B ';'
- { 1785, 23, 25, 27, 3, -24 }, // 0x3C '<'
- { 1857, 24, 12, 31, 4, -17 }, // 0x3D '='
- { 1893, 24, 25, 27, 3, -24 }, // 0x3E '>'
- { 1968, 16, 33, 21, 6, -31 }, // 0x3F '?'
- { 2034, 33, 33, 37, 3, -31 }, // 0x40 '@'
- { 2171, 29, 31, 31, 0, -30 }, // 0x41 'A'
- { 2284, 28, 31, 28, 0, -30 }, // 0x42 'B'
- { 2393, 30, 33, 29, 2, -31 }, // 0x43 'C'
- { 2517, 33, 31, 33, 0, -30 }, // 0x44 'D'
- { 2645, 29, 31, 27, 0, -30 }, // 0x45 'E'
- { 2758, 29, 31, 27, 0, -30 }, // 0x46 'F'
- { 2871, 31, 33, 32, 2, -31 }, // 0x47 'G'
- { 2999, 36, 31, 33, 0, -30 }, // 0x48 'H'
- { 3139, 18, 31, 15, 0, -30 }, // 0x49 'I'
- { 3209, 23, 32, 20, 0, -30 }, // 0x4A 'J'
- { 3301, 33, 31, 30, 0, -30 }, // 0x4B 'K'
- { 3429, 27, 31, 27, 0, -30 }, // 0x4C 'L'
- { 3534, 42, 31, 39, 0, -30 }, // 0x4D 'M'
- { 3697, 35, 32, 32, 0, -30 }, // 0x4E 'N'
- { 3837, 30, 33, 31, 2, -31 }, // 0x4F 'O'
- { 3961, 29, 31, 27, 0, -30 }, // 0x50 'P'
- { 4074, 30, 41, 31, 2, -31 }, // 0x51 'Q'
- { 4228, 28, 31, 29, 0, -30 }, // 0x52 'R'
- { 4337, 23, 33, 21, 0, -31 }, // 0x53 'S'
- { 4432, 27, 31, 28, 4, -30 }, // 0x54 'T'
- { 4537, 31, 32, 33, 5, -30 }, // 0x55 'U'
- { 4661, 29, 32, 31, 6, -30 }, // 0x56 'V'
- { 4777, 39, 32, 42, 6, -30 }, // 0x57 'W'
- { 4933, 32, 31, 31, 0, -30 }, // 0x58 'X'
- { 5057, 26, 31, 28, 5, -30 }, // 0x59 'Y'
- { 5158, 29, 31, 26, 0, -30 }, // 0x5A 'Z'
- { 5271, 17, 39, 18, 1, -31 }, // 0x5B '['
- { 5354, 17, 33, 23, 5, -31 }, // 0x5C '\'
- { 5425, 17, 39, 18, 1, -31 }, // 0x5D ']'
- { 5508, 20, 17, 20, 0, -31 }, // 0x5E '^'
- { 5551, 24, 2, 23, 0, 5 }, // 0x5F '_'
- { 5557, 8, 8, 12, 6, -31 }, // 0x60 '`'
- { 5565, 21, 21, 23, 1, -20 }, // 0x61 'a'
- { 5621, 21, 33, 22, 1, -31 }, // 0x62 'b'
- { 5708, 18, 22, 19, 1, -20 }, // 0x63 'c'
- { 5758, 24, 33, 23, 1, -31 }, // 0x64 'd'
- { 5857, 18, 22, 19, 1, -20 }, // 0x65 'e'
- { 5907, 27, 42, 20, -4, -31 }, // 0x66 'f'
- { 6049, 21, 31, 21, -1, -20 }, // 0x67 'g'
- { 6131, 21, 32, 23, 1, -31 }, // 0x68 'h'
- { 6215, 10, 32, 12, 2, -30 }, // 0x69 'i'
- { 6255, 19, 41, 13, -3, -30 }, // 0x6A 'j'
- { 6353, 21, 33, 21, 1, -31 }, // 0x6B 'k'
- { 6440, 11, 33, 12, 2, -31 }, // 0x6C 'l'
- { 6486, 31, 21, 34, 1, -20 }, // 0x6D 'm'
- { 6568, 21, 21, 23, 1, -20 }, // 0x6E 'n'
- { 6624, 21, 22, 22, 1, -20 }, // 0x6F 'o'
- { 6682, 27, 31, 22, -4, -20 }, // 0x70 'p'
- { 6787, 21, 31, 23, 1, -20 }, // 0x71 'q'
- { 6869, 17, 21, 17, 1, -20 }, // 0x72 'r'
- { 6914, 17, 22, 16, 0, -20 }, // 0x73 's'
- { 6961, 12, 26, 11, 1, -24 }, // 0x74 't'
- { 7000, 20, 22, 23, 1, -20 }, // 0x75 'u'
- { 7055, 18, 22, 21, 3, -20 }, // 0x76 'v'
- { 7105, 30, 22, 32, 2, -20 }, // 0x77 'w'
- { 7188, 22, 22, 20, -1, -20 }, // 0x78 'x'
- { 7249, 21, 31, 22, 1, -20 }, // 0x79 'y'
- { 7331, 17, 24, 18, 0, -19 }, // 0x7A 'z'
- { 7382, 17, 40, 19, 2, -31 }, // 0x7B '{'
- { 7467, 3, 33, 13, 5, -31 }, // 0x7C '|'
- { 7480, 16, 41, 19, 0, -32 }, // 0x7D '}'
- { 7562, 22, 6, 25, 2, -14 } }; // 0x7E '~'
-
-const GFXfont FreeSerifItalic24pt7b PROGMEM = {
- (uint8_t *)FreeSerifItalic24pt7bBitmaps,
- (GFXglyph *)FreeSerifItalic24pt7bGlyphs,
- 0x20, 0x7E, 56 };
-
-// Approx. 8251 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic9pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic9pt7b.h
deleted file mode 100644
index 34e6b8d..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/FreeSerifItalic9pt7b.h
+++ /dev/null
@@ -1,202 +0,0 @@
-const uint8_t FreeSerifItalic9pt7bBitmaps[] PROGMEM = {
- 0x11, 0x12, 0x22, 0x24, 0x40, 0x0C, 0xDE, 0xE5, 0x40, 0x04, 0x82, 0x20,
- 0x98, 0x24, 0x7F, 0xC4, 0x82, 0x23, 0xFC, 0x24, 0x11, 0x04, 0x83, 0x20,
- 0x1C, 0x1B, 0x99, 0x4D, 0x26, 0x81, 0xC0, 0x70, 0x1C, 0x13, 0x49, 0xA4,
- 0xDA, 0xC7, 0xC1, 0x00, 0x80, 0x1C, 0x61, 0xCF, 0x0E, 0x28, 0x30, 0xA0,
- 0xC5, 0x03, 0x34, 0xE7, 0xAE, 0x40, 0xB1, 0x05, 0x84, 0x26, 0x20, 0x99,
- 0x84, 0x3C, 0x03, 0x80, 0x6C, 0x06, 0xC0, 0x78, 0x06, 0x01, 0xEF, 0x66,
- 0x24, 0x24, 0xC3, 0x8C, 0x10, 0xE3, 0x87, 0xCE, 0xFA, 0x08, 0x21, 0x08,
- 0x61, 0x8C, 0x30, 0xC3, 0x0C, 0x30, 0x41, 0x02, 0x00, 0x10, 0x40, 0x82,
- 0x0C, 0x30, 0xC3, 0x0C, 0x61, 0x84, 0x21, 0x08, 0x00, 0x30, 0xCA, 0x5E,
- 0x6A, 0x93, 0x08, 0x08, 0x04, 0x02, 0x01, 0x0F, 0xF8, 0x40, 0x20, 0x10,
- 0x08, 0x00, 0x56, 0xF0, 0xF0, 0x03, 0x02, 0x06, 0x04, 0x08, 0x08, 0x10,
- 0x30, 0x20, 0x60, 0x40, 0xC0, 0x0E, 0x0C, 0x8C, 0x6C, 0x36, 0x1F, 0x0F,
- 0x07, 0x87, 0xC3, 0x61, 0xB1, 0x88, 0x83, 0x80, 0x04, 0x70, 0xC3, 0x08,
- 0x21, 0x86, 0x10, 0x43, 0x08, 0xF8, 0x1C, 0x67, 0x83, 0x03, 0x02, 0x06,
- 0x0C, 0x08, 0x10, 0x20, 0x42, 0xFC, 0x0F, 0x08, 0xC0, 0x60, 0xC1, 0xE0,
- 0x38, 0x0C, 0x06, 0x03, 0x01, 0x01, 0x1F, 0x00, 0x01, 0x01, 0x81, 0x41,
- 0x61, 0x21, 0x11, 0x18, 0x88, 0xFF, 0x02, 0x03, 0x01, 0x00, 0x0F, 0x84,
- 0x04, 0x03, 0x80, 0x60, 0x18, 0x0C, 0x06, 0x03, 0x03, 0x03, 0x1E, 0x00,
- 0x01, 0x83, 0x87, 0x07, 0x03, 0x03, 0x73, 0xCD, 0x86, 0xC3, 0x61, 0xB1,
- 0x88, 0xC3, 0xC0, 0x7F, 0x40, 0x80, 0x80, 0x40, 0x40, 0x60, 0x20, 0x20,
- 0x10, 0x10, 0x18, 0x08, 0x00, 0x1E, 0x19, 0xCC, 0x66, 0x33, 0xB0, 0xE0,
- 0x50, 0xCC, 0xC3, 0x61, 0xB0, 0xCC, 0xC3, 0xC0, 0x0E, 0x19, 0x8C, 0x6C,
- 0x36, 0x1B, 0x0D, 0x86, 0xE6, 0x3F, 0x03, 0x03, 0x06, 0x0C, 0x00, 0x33,
- 0x00, 0x00, 0xCC, 0x33, 0x00, 0x00, 0x44, 0x48, 0x01, 0x83, 0x86, 0x1C,
- 0x0C, 0x03, 0x80, 0x30, 0x07, 0x00, 0x80, 0xFF, 0x80, 0x00, 0x00, 0x0F,
- 0xF8, 0xC0, 0x1C, 0x03, 0x80, 0x70, 0x18, 0x38, 0x70, 0xC0, 0x80, 0x00,
- 0x3C, 0x8C, 0x18, 0x30, 0xC3, 0x0C, 0x20, 0x40, 0x80, 0x06, 0x00, 0x0F,
- 0xC0, 0xC3, 0x0C, 0x04, 0xC7, 0xBC, 0x64, 0xE2, 0x27, 0x31, 0x39, 0x91,
- 0xCC, 0x93, 0x3B, 0x0E, 0x00, 0x1F, 0x80, 0x01, 0x00, 0x60, 0x14, 0x04,
- 0xC0, 0x98, 0x23, 0x07, 0xE1, 0x04, 0x20, 0x88, 0x1B, 0x8F, 0x80, 0x3F,
- 0xC1, 0x8C, 0x21, 0x8C, 0x31, 0x8C, 0x3E, 0x04, 0x61, 0x86, 0x30, 0xC4,
- 0x19, 0x86, 0x7F, 0x80, 0x07, 0x91, 0x86, 0x30, 0x26, 0x02, 0x60, 0x0C,
- 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0x61, 0x83, 0xE0, 0x3F, 0xC0,
- 0x63, 0x82, 0x0C, 0x30, 0x31, 0x81, 0x8C, 0x0C, 0x40, 0x66, 0x07, 0x30,
- 0x31, 0x03, 0x18, 0x71, 0xFE, 0x00, 0x3F, 0xF0, 0xC2, 0x08, 0x21, 0x80,
- 0x19, 0x81, 0xF8, 0x11, 0x03, 0x10, 0x30, 0x02, 0x04, 0x60, 0x8F, 0xF8,
- 0x3F, 0xF0, 0xC2, 0x08, 0x21, 0x80, 0x19, 0x81, 0xF8, 0x11, 0x03, 0x10,
- 0x30, 0x02, 0x00, 0x60, 0x0F, 0x80, 0x07, 0x91, 0x87, 0x30, 0x26, 0x02,
- 0x60, 0x0C, 0x00, 0xC1, 0xFC, 0x0C, 0xC0, 0xCC, 0x0C, 0x60, 0x83, 0xF0,
- 0x3E, 0x3C, 0x30, 0x60, 0x81, 0x06, 0x0C, 0x18, 0x30, 0x7F, 0x81, 0x06,
- 0x0C, 0x18, 0x30, 0x60, 0x81, 0x06, 0x0C, 0x3C, 0x78, 0x1E, 0x18, 0x20,
- 0xC1, 0x83, 0x04, 0x18, 0x30, 0x41, 0x87, 0x80, 0x0F, 0x81, 0x80, 0x80,
- 0xC0, 0x60, 0x20, 0x30, 0x18, 0x0C, 0x04, 0x36, 0x1E, 0x00, 0x3E, 0x78,
- 0x61, 0x82, 0x10, 0x31, 0x01, 0xB0, 0x0E, 0x00, 0x58, 0x06, 0x60, 0x33,
- 0x01, 0x0C, 0x18, 0x61, 0xE7, 0xC0, 0x3E, 0x01, 0x80, 0x20, 0x0C, 0x01,
- 0x80, 0x30, 0x04, 0x01, 0x80, 0x30, 0x04, 0x0D, 0x83, 0x7F, 0xE0, 0x1C,
- 0x07, 0x0C, 0x0E, 0x0C, 0x14, 0x14, 0x1C, 0x14, 0x2C, 0x16, 0x4C, 0x26,
- 0x48, 0x26, 0x98, 0x27, 0x18, 0x27, 0x10, 0x42, 0x30, 0xF4, 0x7C, 0x38,
- 0x78, 0x60, 0x83, 0x04, 0x2C, 0x41, 0x22, 0x09, 0x10, 0x4D, 0x84, 0x28,
- 0x21, 0x41, 0x06, 0x10, 0x21, 0xE1, 0x00, 0x07, 0x83, 0x18, 0xC1, 0xB0,
- 0x36, 0x07, 0xC0, 0xF0, 0x3E, 0x06, 0xC0, 0xD8, 0x31, 0x8C, 0x1E, 0x00,
- 0x3F, 0xC1, 0x9C, 0x21, 0x8C, 0x31, 0x86, 0x31, 0x87, 0xE1, 0x80, 0x30,
- 0x04, 0x01, 0x80, 0x78, 0x00, 0x07, 0x83, 0x18, 0xC1, 0x98, 0x36, 0x07,
- 0xC0, 0xF0, 0x1E, 0x06, 0xC0, 0xD8, 0x31, 0x04, 0x13, 0x01, 0x80, 0x70,
- 0xB7, 0xE0, 0x3F, 0xC1, 0x8C, 0x21, 0x8C, 0x31, 0x8C, 0x3F, 0x04, 0xC1,
- 0x98, 0x31, 0x84, 0x31, 0x86, 0x78, 0x70, 0x1E, 0x4C, 0x63, 0x08, 0xC0,
- 0x38, 0x07, 0x00, 0x60, 0x0C, 0x43, 0x10, 0xC6, 0x62, 0x70, 0x7F, 0xE9,
- 0x8E, 0x31, 0x04, 0x01, 0x80, 0x30, 0x06, 0x00, 0x80, 0x30, 0x06, 0x00,
- 0x80, 0x7E, 0x00, 0x7C, 0xF3, 0x02, 0x30, 0x46, 0x04, 0x60, 0x46, 0x04,
- 0x40, 0x8C, 0x08, 0xC0, 0x8C, 0x10, 0xE3, 0x03, 0xC0, 0xF8, 0xEC, 0x0C,
- 0x81, 0x18, 0x43, 0x08, 0x62, 0x0C, 0x81, 0x90, 0x14, 0x03, 0x00, 0x60,
- 0x08, 0x00, 0xFB, 0xCE, 0x43, 0x0C, 0x86, 0x11, 0x8C, 0x43, 0x38, 0x86,
- 0xB2, 0x0D, 0x24, 0x1C, 0x50, 0x38, 0xA0, 0x21, 0x80, 0x42, 0x01, 0x04,
- 0x00, 0x3E, 0x71, 0x82, 0x0C, 0x40, 0xC8, 0x07, 0x00, 0x60, 0x06, 0x00,
- 0xB0, 0x13, 0x02, 0x18, 0x61, 0x8F, 0x3E, 0xF9, 0xC8, 0x23, 0x10, 0xC8,
- 0x34, 0x05, 0x01, 0x80, 0x40, 0x30, 0x0C, 0x03, 0x03, 0xE0, 0x3F, 0xE4,
- 0x19, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x40, 0x18, 0x06, 0x05,
- 0x81, 0x7F, 0xE0, 0x0E, 0x10, 0x20, 0x81, 0x02, 0x04, 0x10, 0x20, 0x40,
- 0x82, 0x04, 0x08, 0x1C, 0x00, 0x81, 0x04, 0x18, 0x20, 0xC1, 0x04, 0x08,
- 0x20, 0x41, 0x38, 0x20, 0x82, 0x08, 0x41, 0x04, 0x10, 0xC2, 0x08, 0x20,
- 0x8C, 0x00, 0x18, 0x18, 0x2C, 0x24, 0x46, 0x42, 0x83, 0xFF, 0x80, 0xD8,
- 0x80, 0x1F, 0x98, 0x98, 0x4C, 0x2C, 0x36, 0x33, 0x3A, 0xEE, 0x38, 0x08,
- 0x04, 0x02, 0x03, 0x71, 0xCC, 0xC6, 0xC3, 0x63, 0x21, 0x93, 0x8F, 0x00,
- 0x1F, 0x33, 0x60, 0xC0, 0xC0, 0xC0, 0xC4, 0x78, 0x01, 0x80, 0x40, 0x60,
- 0x20, 0xF1, 0x89, 0x8C, 0xC4, 0xC2, 0x63, 0x33, 0xAE, 0xE0, 0x0E, 0x65,
- 0x8B, 0x2F, 0x98, 0x31, 0x3C, 0x01, 0xE0, 0x40, 0x08, 0x02, 0x00, 0x40,
- 0x3E, 0x03, 0x00, 0x40, 0x08, 0x01, 0x00, 0x60, 0x0C, 0x01, 0x00, 0x20,
- 0x04, 0x01, 0x00, 0xC0, 0x00, 0x1E, 0x19, 0xD8, 0xCC, 0xE1, 0xC3, 0x01,
- 0xE0, 0xBC, 0x82, 0x41, 0x31, 0x0F, 0x00, 0x38, 0x08, 0x04, 0x02, 0x03,
- 0x39, 0x6C, 0xC6, 0x46, 0x63, 0x21, 0x11, 0xB8, 0xE0, 0x30, 0x00, 0xE2,
- 0x44, 0xC8, 0xCE, 0x06, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x04, 0x08, 0x10,
- 0x60, 0x81, 0x02, 0x04, 0x70, 0x38, 0x10, 0x10, 0x10, 0x37, 0x22, 0x24,
- 0x38, 0x78, 0x48, 0x4D, 0xC6, 0x73, 0x32, 0x26, 0x64, 0x4C, 0xDE, 0x77,
- 0x39, 0x5E, 0xCC, 0xCC, 0xCE, 0x66, 0x62, 0x22, 0x11, 0x11, 0xB9, 0x8E,
- 0x77, 0x3B, 0x33, 0x62, 0x62, 0x42, 0x4D, 0xCE, 0x0F, 0x18, 0xD8, 0x7C,
- 0x3C, 0x3E, 0x1B, 0x18, 0xF0, 0x3B, 0x87, 0x31, 0x8C, 0x43, 0x31, 0x88,
- 0x62, 0x30, 0xF0, 0x60, 0x10, 0x04, 0x03, 0x80, 0x0F, 0x18, 0x98, 0x4C,
- 0x2C, 0x26, 0x33, 0x38, 0xEC, 0x04, 0x02, 0x03, 0x03, 0xC0, 0x76, 0x50,
- 0xC1, 0x06, 0x08, 0x10, 0x60, 0x1A, 0x6C, 0xC8, 0xC0, 0xD1, 0xB3, 0x5C,
- 0x23, 0xC8, 0xC4, 0x21, 0x18, 0xE0, 0xC3, 0x42, 0x42, 0xC6, 0x86, 0x8C,
- 0x9D, 0xEE, 0x62, 0xC4, 0x89, 0xA3, 0x47, 0x0C, 0x10, 0xE2, 0x2C, 0x44,
- 0xD8, 0x9D, 0x23, 0xA4, 0x65, 0x0C, 0xC1, 0x10, 0x19, 0x95, 0x43, 0x01,
- 0x80, 0xC0, 0xA0, 0x91, 0x8E, 0x70, 0x88, 0x46, 0x23, 0x20, 0x90, 0x50,
- 0x28, 0x18, 0x08, 0x08, 0x08, 0x18, 0x00, 0x3F, 0x42, 0x04, 0x08, 0x10,
- 0x20, 0x40, 0x72, 0x0E, 0x08, 0x61, 0x04, 0x30, 0x86, 0x08, 0x61, 0x04,
- 0x30, 0xC3, 0x8F, 0x00, 0xFF, 0xF0, 0x1E, 0x0C, 0x10, 0x20, 0xC1, 0x82,
- 0x04, 0x1C, 0x30, 0x40, 0x83, 0x04, 0x08, 0x20, 0x60, 0x99, 0x8E };
-
-const GFXglyph FreeSerifItalic9pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 5, 0, 1 }, // 0x20 ' '
- { 0, 4, 12, 6, 1, -11 }, // 0x21 '!'
- { 6, 5, 4, 6, 3, -11 }, // 0x22 '"'
- { 9, 10, 12, 9, 0, -11 }, // 0x23 '#'
- { 24, 9, 15, 9, 1, -12 }, // 0x24 '$'
- { 41, 14, 12, 15, 1, -11 }, // 0x25 '%'
- { 62, 12, 12, 14, 1, -11 }, // 0x26 '&'
- { 80, 2, 4, 4, 3, -11 }, // 0x27 '''
- { 81, 6, 15, 6, 1, -11 }, // 0x28 '('
- { 93, 6, 15, 6, 0, -11 }, // 0x29 ')'
- { 105, 6, 8, 9, 3, -11 }, // 0x2A '*'
- { 111, 9, 9, 12, 1, -8 }, // 0x2B '+'
- { 122, 2, 4, 5, 0, -1 }, // 0x2C ','
- { 123, 4, 1, 6, 1, -3 }, // 0x2D '-'
- { 124, 2, 2, 5, 0, -1 }, // 0x2E '.'
- { 125, 8, 12, 5, 0, -11 }, // 0x2F '/'
- { 137, 9, 13, 9, 1, -12 }, // 0x30 '0'
- { 152, 6, 13, 9, 1, -12 }, // 0x31 '1'
- { 162, 8, 12, 9, 1, -11 }, // 0x32 '2'
- { 174, 9, 12, 9, 0, -11 }, // 0x33 '3'
- { 188, 9, 12, 9, 0, -11 }, // 0x34 '4'
- { 202, 9, 12, 9, 0, -11 }, // 0x35 '5'
- { 216, 9, 13, 9, 1, -12 }, // 0x36 '6'
- { 231, 9, 12, 9, 1, -11 }, // 0x37 '7'
- { 245, 9, 13, 9, 1, -12 }, // 0x38 '8'
- { 260, 9, 13, 9, 0, -12 }, // 0x39 '9'
- { 275, 4, 8, 4, 1, -7 }, // 0x3A ':'
- { 279, 4, 10, 4, 1, -7 }, // 0x3B ';'
- { 284, 9, 9, 10, 1, -8 }, // 0x3C '<'
- { 295, 9, 5, 12, 2, -6 }, // 0x3D '='
- { 301, 9, 9, 10, 1, -8 }, // 0x3E '>'
- { 312, 7, 12, 8, 2, -11 }, // 0x3F '?'
- { 323, 13, 12, 14, 1, -11 }, // 0x40 '@'
- { 343, 11, 11, 12, 0, -10 }, // 0x41 'A'
- { 359, 11, 12, 11, 0, -11 }, // 0x42 'B'
- { 376, 12, 12, 11, 1, -11 }, // 0x43 'C'
- { 394, 13, 12, 13, 0, -11 }, // 0x44 'D'
- { 414, 12, 12, 10, 0, -11 }, // 0x45 'E'
- { 432, 12, 12, 10, 0, -11 }, // 0x46 'F'
- { 450, 12, 12, 12, 1, -11 }, // 0x47 'G'
- { 468, 14, 12, 13, 0, -11 }, // 0x48 'H'
- { 489, 7, 12, 6, 0, -11 }, // 0x49 'I'
- { 500, 9, 12, 8, 0, -11 }, // 0x4A 'J'
- { 514, 13, 12, 12, 0, -11 }, // 0x4B 'K'
- { 534, 11, 12, 10, 0, -11 }, // 0x4C 'L'
- { 551, 16, 12, 15, 0, -11 }, // 0x4D 'M'
- { 575, 13, 12, 12, 0, -11 }, // 0x4E 'N'
- { 595, 11, 12, 12, 1, -11 }, // 0x4F 'O'
- { 612, 11, 12, 10, 0, -11 }, // 0x50 'P'
- { 629, 11, 15, 12, 1, -11 }, // 0x51 'Q'
- { 650, 11, 12, 11, 0, -11 }, // 0x52 'R'
- { 667, 10, 12, 8, 0, -11 }, // 0x53 'S'
- { 682, 11, 12, 11, 2, -11 }, // 0x54 'T'
- { 699, 12, 12, 13, 2, -11 }, // 0x55 'U'
- { 717, 11, 12, 12, 2, -11 }, // 0x56 'V'
- { 734, 15, 12, 16, 2, -11 }, // 0x57 'W'
- { 757, 12, 12, 12, 0, -11 }, // 0x58 'X'
- { 775, 10, 12, 11, 2, -11 }, // 0x59 'Y'
- { 790, 11, 12, 10, 0, -11 }, // 0x5A 'Z'
- { 807, 7, 15, 7, 0, -11 }, // 0x5B '['
- { 821, 6, 12, 9, 2, -11 }, // 0x5C '\'
- { 830, 6, 15, 7, 1, -11 }, // 0x5D ']'
- { 842, 8, 7, 8, 0, -11 }, // 0x5E '^'
- { 849, 9, 1, 9, 0, 2 }, // 0x5F '_'
- { 851, 3, 3, 5, 2, -11 }, // 0x60 '`'
- { 853, 9, 8, 9, 0, -7 }, // 0x61 'a'
- { 862, 9, 12, 9, 0, -11 }, // 0x62 'b'
- { 876, 8, 8, 7, 0, -7 }, // 0x63 'c'
- { 884, 9, 12, 9, 0, -11 }, // 0x64 'd'
- { 898, 7, 8, 7, 0, -7 }, // 0x65 'e'
- { 905, 11, 17, 8, -1, -12 }, // 0x66 'f'
- { 929, 9, 12, 8, 0, -7 }, // 0x67 'g'
- { 943, 9, 12, 9, 0, -11 }, // 0x68 'h'
- { 957, 4, 12, 4, 1, -11 }, // 0x69 'i'
- { 963, 7, 16, 5, -1, -11 }, // 0x6A 'j'
- { 977, 8, 12, 8, 0, -11 }, // 0x6B 'k'
- { 989, 4, 12, 5, 1, -11 }, // 0x6C 'l'
- { 995, 13, 8, 13, 0, -7 }, // 0x6D 'm'
- { 1008, 8, 8, 9, 0, -7 }, // 0x6E 'n'
- { 1016, 9, 8, 9, 0, -7 }, // 0x6F 'o'
- { 1025, 10, 12, 8, -1, -7 }, // 0x70 'p'
- { 1040, 9, 12, 9, 0, -7 }, // 0x71 'q'
- { 1054, 7, 8, 7, 0, -7 }, // 0x72 'r'
- { 1061, 7, 8, 6, 0, -7 }, // 0x73 's'
- { 1068, 5, 9, 4, 0, -8 }, // 0x74 't'
- { 1074, 8, 8, 9, 1, -7 }, // 0x75 'u'
- { 1082, 7, 8, 8, 1, -7 }, // 0x76 'v'
- { 1089, 11, 8, 12, 1, -7 }, // 0x77 'w'
- { 1100, 9, 8, 8, -1, -7 }, // 0x78 'x'
- { 1109, 9, 12, 9, 0, -7 }, // 0x79 'y'
- { 1123, 8, 9, 7, 0, -7 }, // 0x7A 'z'
- { 1132, 6, 15, 7, 1, -11 }, // 0x7B '{'
- { 1144, 1, 12, 5, 2, -11 }, // 0x7C '|'
- { 1146, 7, 16, 7, 0, -12 }, // 0x7D '}'
- { 1160, 8, 3, 10, 1, -5 } }; // 0x7E '~'
-
-const GFXfont FreeSerifItalic9pt7b PROGMEM = {
- (uint8_t *)FreeSerifItalic9pt7bBitmaps,
- (GFXglyph *)FreeSerifItalic9pt7bGlyphs,
- 0x20, 0x7E, 22 };
-
-// Approx. 1835 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/Org_01.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/Org_01.h
deleted file mode 100644
index ac41f31..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/Org_01.h
+++ /dev/null
@@ -1,131 +0,0 @@
-// Org_v01 by Orgdot (www.orgdot.com/aliasfonts). A tiny,
-// stylized font with all characters within a 6 pixel height.
-
-const uint8_t Org_01Bitmaps[] PROGMEM = {
- 0xE8, 0xA0, 0x57, 0xD5, 0xF5, 0x00, 0xFD, 0x3E, 0x5F, 0x80, 0x88, 0x88,
- 0x88, 0x80, 0xF4, 0xBF, 0x2E, 0x80, 0x80, 0x6A, 0x40, 0x95, 0x80, 0xAA,
- 0x80, 0x5D, 0x00, 0xC0, 0xF0, 0x80, 0x08, 0x88, 0x88, 0x00, 0xFC, 0x63,
- 0x1F, 0x80, 0xF8, 0xF8, 0x7F, 0x0F, 0x80, 0xF8, 0x7E, 0x1F, 0x80, 0x8C,
- 0x7E, 0x10, 0x80, 0xFC, 0x3E, 0x1F, 0x80, 0xFC, 0x3F, 0x1F, 0x80, 0xF8,
- 0x42, 0x10, 0x80, 0xFC, 0x7F, 0x1F, 0x80, 0xFC, 0x7E, 0x1F, 0x80, 0x90,
- 0xB0, 0x2A, 0x22, 0xF0, 0xF0, 0x88, 0xA8, 0xF8, 0x4E, 0x02, 0x00, 0xFD,
- 0x6F, 0x0F, 0x80, 0xFC, 0x7F, 0x18, 0x80, 0xF4, 0x7D, 0x1F, 0x00, 0xFC,
- 0x21, 0x0F, 0x80, 0xF4, 0x63, 0x1F, 0x00, 0xFC, 0x3F, 0x0F, 0x80, 0xFC,
- 0x3F, 0x08, 0x00, 0xFC, 0x2F, 0x1F, 0x80, 0x8C, 0x7F, 0x18, 0x80, 0xF9,
- 0x08, 0x4F, 0x80, 0x78, 0x85, 0x2F, 0x80, 0x8D, 0xB1, 0x68, 0x80, 0x84,
- 0x21, 0x0F, 0x80, 0xFD, 0x6B, 0x5A, 0x80, 0xFC, 0x63, 0x18, 0x80, 0xFC,
- 0x63, 0x1F, 0x80, 0xFC, 0x7F, 0x08, 0x00, 0xFC, 0x63, 0x3F, 0x80, 0xFC,
- 0x7F, 0x29, 0x00, 0xFC, 0x3E, 0x1F, 0x80, 0xF9, 0x08, 0x42, 0x00, 0x8C,
- 0x63, 0x1F, 0x80, 0x8C, 0x62, 0xA2, 0x00, 0xAD, 0x6B, 0x5F, 0x80, 0x8A,
- 0x88, 0xA8, 0x80, 0x8C, 0x54, 0x42, 0x00, 0xF8, 0x7F, 0x0F, 0x80, 0xEA,
- 0xC0, 0x82, 0x08, 0x20, 0x80, 0xD5, 0xC0, 0x54, 0xF8, 0x80, 0xF1, 0xFF,
- 0x8F, 0x99, 0xF0, 0xF8, 0x8F, 0x1F, 0x99, 0xF0, 0xFF, 0x8F, 0x6B, 0xA4,
- 0xF9, 0x9F, 0x10, 0x8F, 0x99, 0x90, 0xF0, 0x55, 0xC0, 0x8A, 0xF9, 0x90,
- 0xF8, 0xFD, 0x63, 0x10, 0xF9, 0x99, 0xF9, 0x9F, 0xF9, 0x9F, 0x80, 0xF9,
- 0x9F, 0x20, 0xF8, 0x88, 0x47, 0x1F, 0x27, 0xC8, 0x42, 0x00, 0x99, 0x9F,
- 0x99, 0x97, 0x8C, 0x6B, 0xF0, 0x96, 0x69, 0x99, 0x9F, 0x10, 0x2E, 0x8F,
- 0x2B, 0x22, 0xF8, 0x89, 0xA8, 0x0F, 0xE0 };
-
-const GFXglyph Org_01Glyphs[] PROGMEM = {
- { 0, 0, 0, 6, 0, 1 }, // 0x20 ' '
- { 0, 1, 5, 2, 0, -4 }, // 0x21 '!'
- { 1, 3, 1, 4, 0, -4 }, // 0x22 '"'
- { 2, 5, 5, 6, 0, -4 }, // 0x23 '#'
- { 6, 5, 5, 6, 0, -4 }, // 0x24 '$'
- { 10, 5, 5, 6, 0, -4 }, // 0x25 '%'
- { 14, 5, 5, 6, 0, -4 }, // 0x26 '&'
- { 18, 1, 1, 2, 0, -4 }, // 0x27 '''
- { 19, 2, 5, 3, 0, -4 }, // 0x28 '('
- { 21, 2, 5, 3, 0, -4 }, // 0x29 ')'
- { 23, 3, 3, 4, 0, -3 }, // 0x2A '*'
- { 25, 3, 3, 4, 0, -3 }, // 0x2B '+'
- { 27, 1, 2, 2, 0, 0 }, // 0x2C ','
- { 28, 4, 1, 5, 0, -2 }, // 0x2D '-'
- { 29, 1, 1, 2, 0, 0 }, // 0x2E '.'
- { 30, 5, 5, 6, 0, -4 }, // 0x2F '/'
- { 34, 5, 5, 6, 0, -4 }, // 0x30 '0'
- { 38, 1, 5, 2, 0, -4 }, // 0x31 '1'
- { 39, 5, 5, 6, 0, -4 }, // 0x32 '2'
- { 43, 5, 5, 6, 0, -4 }, // 0x33 '3'
- { 47, 5, 5, 6, 0, -4 }, // 0x34 '4'
- { 51, 5, 5, 6, 0, -4 }, // 0x35 '5'
- { 55, 5, 5, 6, 0, -4 }, // 0x36 '6'
- { 59, 5, 5, 6, 0, -4 }, // 0x37 '7'
- { 63, 5, 5, 6, 0, -4 }, // 0x38 '8'
- { 67, 5, 5, 6, 0, -4 }, // 0x39 '9'
- { 71, 1, 4, 2, 0, -3 }, // 0x3A ':'
- { 72, 1, 4, 2, 0, -3 }, // 0x3B ';'
- { 73, 3, 5, 4, 0, -4 }, // 0x3C '<'
- { 75, 4, 3, 5, 0, -3 }, // 0x3D '='
- { 77, 3, 5, 4, 0, -4 }, // 0x3E '>'
- { 79, 5, 5, 6, 0, -4 }, // 0x3F '?'
- { 83, 5, 5, 6, 0, -4 }, // 0x40 '@'
- { 87, 5, 5, 6, 0, -4 }, // 0x41 'A'
- { 91, 5, 5, 6, 0, -4 }, // 0x42 'B'
- { 95, 5, 5, 6, 0, -4 }, // 0x43 'C'
- { 99, 5, 5, 6, 0, -4 }, // 0x44 'D'
- { 103, 5, 5, 6, 0, -4 }, // 0x45 'E'
- { 107, 5, 5, 6, 0, -4 }, // 0x46 'F'
- { 111, 5, 5, 6, 0, -4 }, // 0x47 'G'
- { 115, 5, 5, 6, 0, -4 }, // 0x48 'H'
- { 119, 5, 5, 6, 0, -4 }, // 0x49 'I'
- { 123, 5, 5, 6, 0, -4 }, // 0x4A 'J'
- { 127, 5, 5, 6, 0, -4 }, // 0x4B 'K'
- { 131, 5, 5, 6, 0, -4 }, // 0x4C 'L'
- { 135, 5, 5, 6, 0, -4 }, // 0x4D 'M'
- { 139, 5, 5, 6, 0, -4 }, // 0x4E 'N'
- { 143, 5, 5, 6, 0, -4 }, // 0x4F 'O'
- { 147, 5, 5, 6, 0, -4 }, // 0x50 'P'
- { 151, 5, 5, 6, 0, -4 }, // 0x51 'Q'
- { 155, 5, 5, 6, 0, -4 }, // 0x52 'R'
- { 159, 5, 5, 6, 0, -4 }, // 0x53 'S'
- { 163, 5, 5, 6, 0, -4 }, // 0x54 'T'
- { 167, 5, 5, 6, 0, -4 }, // 0x55 'U'
- { 171, 5, 5, 6, 0, -4 }, // 0x56 'V'
- { 175, 5, 5, 6, 0, -4 }, // 0x57 'W'
- { 179, 5, 5, 6, 0, -4 }, // 0x58 'X'
- { 183, 5, 5, 6, 0, -4 }, // 0x59 'Y'
- { 187, 5, 5, 6, 0, -4 }, // 0x5A 'Z'
- { 191, 2, 5, 3, 0, -4 }, // 0x5B '['
- { 193, 5, 5, 6, 0, -4 }, // 0x5C '\'
- { 197, 2, 5, 3, 0, -4 }, // 0x5D ']'
- { 199, 3, 2, 4, 0, -4 }, // 0x5E '^'
- { 200, 5, 1, 6, 0, 1 }, // 0x5F '_'
- { 201, 1, 1, 2, 0, -4 }, // 0x60 '`'
- { 202, 4, 4, 5, 0, -3 }, // 0x61 'a'
- { 204, 4, 5, 5, 0, -4 }, // 0x62 'b'
- { 207, 4, 4, 5, 0, -3 }, // 0x63 'c'
- { 209, 4, 5, 5, 0, -4 }, // 0x64 'd'
- { 212, 4, 4, 5, 0, -3 }, // 0x65 'e'
- { 214, 3, 5, 4, 0, -4 }, // 0x66 'f'
- { 216, 4, 5, 5, 0, -3 }, // 0x67 'g'
- { 219, 4, 5, 5, 0, -4 }, // 0x68 'h'
- { 222, 1, 4, 2, 0, -3 }, // 0x69 'i'
- { 223, 2, 5, 3, 0, -3 }, // 0x6A 'j'
- { 225, 4, 5, 5, 0, -4 }, // 0x6B 'k'
- { 228, 1, 5, 2, 0, -4 }, // 0x6C 'l'
- { 229, 5, 4, 6, 0, -3 }, // 0x6D 'm'
- { 232, 4, 4, 5, 0, -3 }, // 0x6E 'n'
- { 234, 4, 4, 5, 0, -3 }, // 0x6F 'o'
- { 236, 4, 5, 5, 0, -3 }, // 0x70 'p'
- { 239, 4, 5, 5, 0, -3 }, // 0x71 'q'
- { 242, 4, 4, 5, 0, -3 }, // 0x72 'r'
- { 244, 4, 4, 5, 0, -3 }, // 0x73 's'
- { 246, 5, 5, 6, 0, -4 }, // 0x74 't'
- { 250, 4, 4, 5, 0, -3 }, // 0x75 'u'
- { 252, 4, 4, 5, 0, -3 }, // 0x76 'v'
- { 254, 5, 4, 6, 0, -3 }, // 0x77 'w'
- { 257, 4, 4, 5, 0, -3 }, // 0x78 'x'
- { 259, 4, 5, 5, 0, -3 }, // 0x79 'y'
- { 262, 4, 4, 5, 0, -3 }, // 0x7A 'z'
- { 264, 3, 5, 4, 0, -4 }, // 0x7B '{'
- { 266, 1, 5, 2, 0, -4 }, // 0x7C '|'
- { 267, 3, 5, 4, 0, -4 }, // 0x7D '}'
- { 269, 5, 3, 6, 0, -3 } }; // 0x7E '~'
-
-const GFXfont Org_01 PROGMEM = {
- (uint8_t *)Org_01Bitmaps,
- (GFXglyph *)Org_01Glyphs,
- 0x20, 0x7E, 7 };
-
-// Approx. 943 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/Picopixel.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/Picopixel.h
deleted file mode 100644
index 0ed6543..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/Picopixel.h
+++ /dev/null
@@ -1,123 +0,0 @@
-// Picopixel by Sebastian Weber. A tiny font
-// with all characters within a 6 pixel height.
-
-const uint8_t PicopixelBitmaps[] PROGMEM = {
- 0xE8, 0xB4, 0x57, 0xD5, 0xF5, 0x00, 0x4E, 0x3E, 0x80, 0xA5, 0x4A, 0x4A,
- 0x5A, 0x50, 0xC0, 0x6A, 0x40, 0x95, 0x80, 0xAA, 0x80, 0x5D, 0x00, 0x60,
- 0xE0, 0x80, 0x25, 0x48, 0x56, 0xD4, 0x75, 0x40, 0xC5, 0x4E, 0xC5, 0x1C,
- 0x97, 0x92, 0xF3, 0x1C, 0x53, 0x54, 0xE5, 0x48, 0x55, 0x54, 0x55, 0x94,
- 0xA0, 0x46, 0x64, 0xE3, 0x80, 0x98, 0xC5, 0x04, 0x56, 0xC6, 0x57, 0xDA,
- 0xD7, 0x5C, 0x72, 0x46, 0xD6, 0xDC, 0xF3, 0xCE, 0xF3, 0x48, 0x72, 0xD4,
- 0xB7, 0xDA, 0xF8, 0x24, 0xD4, 0xBB, 0x5A, 0x92, 0x4E, 0x8E, 0xEB, 0x58,
- 0x80, 0x9D, 0xB9, 0x90, 0x56, 0xD4, 0xD7, 0x48, 0x56, 0xD4, 0x40, 0xD7,
- 0x5A, 0x71, 0x1C, 0xE9, 0x24, 0xB6, 0xD4, 0xB6, 0xA4, 0x8C, 0x6B, 0x55,
- 0x00, 0xB5, 0x5A, 0xB5, 0x24, 0xE5, 0x4E, 0xEA, 0xC0, 0x91, 0x12, 0xD5,
- 0xC0, 0x54, 0xF0, 0x90, 0xC7, 0xF0, 0x93, 0x5E, 0x71, 0x80, 0x25, 0xDE,
- 0x5E, 0x30, 0x6E, 0x80, 0x77, 0x9C, 0x93, 0x5A, 0xB8, 0x45, 0x60, 0x92,
- 0xEA, 0xAA, 0x40, 0xD5, 0x6A, 0xD6, 0x80, 0x55, 0x00, 0xD7, 0x40, 0x75,
- 0x90, 0xE8, 0x71, 0xE0, 0xBA, 0x40, 0xB5, 0x80, 0xB5, 0x00, 0x8D, 0x54,
- 0xAA, 0x80, 0xAC, 0xE0, 0xE5, 0x70, 0x6A, 0x26, 0xFC, 0xC8, 0xAC, 0x5A };
-
-const GFXglyph PicopixelGlyphs[] PROGMEM = {
- { 0, 0, 0, 2, 0, 1 }, // 0x20 ' '
- { 0, 1, 5, 2, 0, -4 }, // 0x21 '!'
- { 1, 3, 2, 4, 0, -4 }, // 0x22 '"'
- { 2, 5, 5, 6, 0, -4 }, // 0x23 '#'
- { 6, 3, 6, 4, 0, -4 }, // 0x24 '$'
- { 9, 3, 5, 4, 0, -4 }, // 0x25 '%'
- { 11, 4, 5, 5, 0, -4 }, // 0x26 '&'
- { 14, 1, 2, 2, 0, -4 }, // 0x27 '''
- { 15, 2, 5, 3, 0, -4 }, // 0x28 '('
- { 17, 2, 5, 3, 0, -4 }, // 0x29 ')'
- { 19, 3, 3, 4, 0, -3 }, // 0x2A '*'
- { 21, 3, 3, 4, 0, -3 }, // 0x2B '+'
- { 23, 2, 2, 3, 0, 0 }, // 0x2C ','
- { 24, 3, 1, 4, 0, -2 }, // 0x2D '-'
- { 25, 1, 1, 2, 0, 0 }, // 0x2E '.'
- { 26, 3, 5, 4, 0, -4 }, // 0x2F '/'
- { 28, 3, 5, 4, 0, -4 }, // 0x30 '0'
- { 30, 2, 5, 3, 0, -4 }, // 0x31 '1'
- { 32, 3, 5, 4, 0, -4 }, // 0x32 '2'
- { 34, 3, 5, 4, 0, -4 }, // 0x33 '3'
- { 36, 3, 5, 4, 0, -4 }, // 0x34 '4'
- { 38, 3, 5, 4, 0, -4 }, // 0x35 '5'
- { 40, 3, 5, 4, 0, -4 }, // 0x36 '6'
- { 42, 3, 5, 4, 0, -4 }, // 0x37 '7'
- { 44, 3, 5, 4, 0, -4 }, // 0x38 '8'
- { 46, 3, 5, 4, 0, -4 }, // 0x39 '9'
- { 48, 1, 3, 2, 0, -3 }, // 0x3A ':'
- { 49, 2, 4, 3, 0, -3 }, // 0x3B ';'
- { 50, 2, 3, 3, 0, -3 }, // 0x3C '<'
- { 51, 3, 3, 4, 0, -3 }, // 0x3D '='
- { 53, 2, 3, 3, 0, -3 }, // 0x3E '>'
- { 54, 3, 5, 4, 0, -4 }, // 0x3F '?'
- { 56, 3, 5, 4, 0, -4 }, // 0x40 '@'
- { 58, 3, 5, 4, 0, -4 }, // 0x41 'A'
- { 60, 3, 5, 4, 0, -4 }, // 0x42 'B'
- { 62, 3, 5, 4, 0, -4 }, // 0x43 'C'
- { 64, 3, 5, 4, 0, -4 }, // 0x44 'D'
- { 66, 3, 5, 4, 0, -4 }, // 0x45 'E'
- { 68, 3, 5, 4, 0, -4 }, // 0x46 'F'
- { 70, 3, 5, 4, 0, -4 }, // 0x47 'G'
- { 72, 3, 5, 4, 0, -4 }, // 0x48 'H'
- { 74, 1, 5, 2, 0, -4 }, // 0x49 'I'
- { 75, 3, 5, 4, 0, -4 }, // 0x4A 'J'
- { 77, 3, 5, 4, 0, -4 }, // 0x4B 'K'
- { 79, 3, 5, 4, 0, -4 }, // 0x4C 'L'
- { 81, 5, 5, 6, 0, -4 }, // 0x4D 'M'
- { 85, 4, 5, 5, 0, -4 }, // 0x4E 'N'
- { 88, 3, 5, 4, 0, -4 }, // 0x4F 'O'
- { 90, 3, 5, 4, 0, -4 }, // 0x50 'P'
- { 92, 3, 6, 4, 0, -4 }, // 0x51 'Q'
- { 95, 3, 5, 4, 0, -4 }, // 0x52 'R'
- { 97, 3, 5, 4, 0, -4 }, // 0x53 'S'
- { 99, 3, 5, 4, 0, -4 }, // 0x54 'T'
- { 101, 3, 5, 4, 0, -4 }, // 0x55 'U'
- { 103, 3, 5, 4, 0, -4 }, // 0x56 'V'
- { 105, 5, 5, 6, 0, -4 }, // 0x57 'W'
- { 109, 3, 5, 4, 0, -4 }, // 0x58 'X'
- { 111, 3, 5, 4, 0, -4 }, // 0x59 'Y'
- { 113, 3, 5, 4, 0, -4 }, // 0x5A 'Z'
- { 115, 2, 5, 3, 0, -4 }, // 0x5B '['
- { 117, 3, 5, 4, 0, -4 }, // 0x5C '\'
- { 119, 2, 5, 3, 0, -4 }, // 0x5D ']'
- { 121, 3, 2, 4, 0, -4 }, // 0x5E '^'
- { 122, 4, 1, 4, 0, 1 }, // 0x5F '_'
- { 123, 2, 2, 3, 0, -4 }, // 0x60 '`'
- { 124, 3, 4, 4, 0, -3 }, // 0x61 'a'
- { 126, 3, 5, 4, 0, -4 }, // 0x62 'b'
- { 128, 3, 3, 4, 0, -2 }, // 0x63 'c'
- { 130, 3, 5, 4, 0, -4 }, // 0x64 'd'
- { 132, 3, 4, 4, 0, -3 }, // 0x65 'e'
- { 134, 2, 5, 3, 0, -4 }, // 0x66 'f'
- { 136, 3, 5, 4, 0, -3 }, // 0x67 'g'
- { 138, 3, 5, 4, 0, -4 }, // 0x68 'h'
- { 140, 1, 5, 2, 0, -4 }, // 0x69 'i'
- { 141, 2, 6, 3, 0, -4 }, // 0x6A 'j'
- { 143, 3, 5, 4, 0, -4 }, // 0x6B 'k'
- { 145, 2, 5, 3, 0, -4 }, // 0x6C 'l'
- { 147, 5, 3, 6, 0, -2 }, // 0x6D 'm'
- { 149, 3, 3, 4, 0, -2 }, // 0x6E 'n'
- { 151, 3, 3, 4, 0, -2 }, // 0x6F 'o'
- { 153, 3, 4, 4, 0, -2 }, // 0x70 'p'
- { 155, 3, 4, 4, 0, -2 }, // 0x71 'q'
- { 157, 2, 3, 3, 0, -2 }, // 0x72 'r'
- { 158, 3, 4, 4, 0, -3 }, // 0x73 's'
- { 160, 2, 5, 3, 0, -4 }, // 0x74 't'
- { 162, 3, 3, 4, 0, -2 }, // 0x75 'u'
- { 164, 3, 3, 4, 0, -2 }, // 0x76 'v'
- { 166, 5, 3, 6, 0, -2 }, // 0x77 'w'
- { 168, 3, 3, 4, 0, -2 }, // 0x78 'x'
- { 170, 3, 4, 4, 0, -2 }, // 0x79 'y'
- { 172, 3, 4, 4, 0, -3 }, // 0x7A 'z'
- { 174, 3, 5, 4, 0, -4 }, // 0x7B '{'
- { 176, 1, 6, 2, 0, -4 }, // 0x7C '|'
- { 177, 3, 5, 4, 0, -4 }, // 0x7D '}'
- { 179, 4, 2, 5, 0, -3 } }; // 0x7E '~'
-
-const GFXfont Picopixel PROGMEM = {
- (uint8_t *)PicopixelBitmaps,
- (GFXglyph *)PicopixelGlyphs,
- 0x20, 0x7E, 7 };
-
-// Approx. 852 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/Tiny3x3a2pt7b.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/Tiny3x3a2pt7b.h
deleted file mode 100644
index d77676c..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/Tiny3x3a2pt7b.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
-** The FontStruction “Tiny3x3aâ€
-** (https://fontstruct.com/fontstructions/show/670512) by “Michaelangel007†is
-** licensed under a Creative Commons Attribution Non-commercial Share Alike license
-** (http://creativecommons.org/licenses/by-nc-sa/3.0/).
-** “Tiny3x3a†was originally cloned (copied) from the FontStruction
-** “CHECKER†(https://fontstruct.com/fontstructions/show/2391) by Wolf grant
-** Grant, which is licensed under a Creative Commons Attribution Non-commercial
-** Share Alike license (http://creativecommons.org/licenses/by-nc-sa/3.0/).
-*
-* Converted by eadmaster with fontconvert
-**/
-
-const uint8_t Tiny3x3a2pt7bBitmaps[] PROGMEM = {
- 0xC0, 0xB4, 0xBF, 0x80, 0x6B, 0x00, 0xDD, 0x80, 0x59, 0x80, 0x80, 0x64,
- 0x98, 0xF0, 0x5D, 0x00, 0xC0, 0xE0, 0x80, 0x2A, 0x00, 0x55, 0x00, 0x94,
- 0xC9, 0x80, 0xEF, 0x80, 0xBC, 0x80, 0x6B, 0x00, 0x9F, 0x80, 0xE4, 0x80,
- 0x7F, 0x00, 0xFC, 0x80, 0xA0, 0x58, 0x64, 0xE3, 0x80, 0x98, 0xD8, 0xD8,
- 0x80, 0x5E, 0x80, 0xDF, 0x80, 0x71, 0x80, 0xD7, 0x00, 0xFB, 0x80, 0xFA,
- 0x00, 0xD7, 0x80, 0xBE, 0x80, 0xE0, 0x27, 0x00, 0xBA, 0x80, 0x93, 0x80,
- 0xFE, 0x80, 0xF6, 0x80, 0xF7, 0x80, 0xFE, 0x00, 0xF7, 0x00, 0xDE, 0x80,
- 0x6B, 0x00, 0xE9, 0x00, 0xB7, 0x80, 0xB5, 0x00, 0xBF, 0x80, 0xAA, 0x80,
- 0xA9, 0x00, 0xEB, 0x80, 0xEC, 0x88, 0x80, 0xDC, 0x54, 0xE0, 0x90, 0x70,
- 0xBC, 0xF0, 0x7C, 0xB0, 0x68, 0xFC, 0xBC, 0xC0, 0x58, 0x9A, 0x80, 0xA4,
- 0xDC, 0xD4, 0xF0, 0xF8, 0xF4, 0xE0, 0x60, 0x59, 0x80, 0xBC, 0xA8, 0xEC,
- 0xF0, 0xAC, 0x80, 0x90, 0x79, 0x80, 0xF0, 0xCF, 0x00, 0x78 };
-
-const GFXglyph Tiny3x3a2pt7bGlyphs[] PROGMEM = {
- { 0, 0, 0, 4, 0, 1 }, // 0x20 ' '
- { 0, 1, 2, 3, 1, -2 }, // 0x21 '!'
- { 1, 3, 2, 4, 0, -2 }, // 0x22 '"'
- { 2, 3, 3, 4, 0, -2 }, // 0x23 '#'
- { 4, 3, 3, 4, 0, -2 }, // 0x24 '$'
- { 6, 3, 3, 4, 0, -2 }, // 0x25 '%'
- { 8, 3, 3, 4, 0, -2 }, // 0x26 '&'
- { 10, 1, 1, 3, 1, -2 }, // 0x27 '''
- { 11, 2, 3, 3, 0, -2 }, // 0x28 '('
- { 12, 2, 3, 4, 1, -2 }, // 0x29 ')'
- { 13, 2, 2, 4, 1, -2 }, // 0x2A '*'
- { 14, 3, 3, 4, 0, -2 }, // 0x2B '+'
- { 16, 1, 2, 2, 0, 0 }, // 0x2C ','
- { 17, 3, 1, 4, 0, -1 }, // 0x2D '-'
- { 18, 1, 1, 2, 0, 0 }, // 0x2E '.'
- { 19, 3, 3, 4, 0, -2 }, // 0x2F '/'
- { 21, 3, 3, 4, 0, -2 }, // 0x30 '0'
- { 23, 2, 3, 3, 0, -2 }, // 0x31 '1'
- { 24, 3, 3, 4, 0, -2 }, // 0x32 '2'
- { 26, 3, 3, 4, 0, -2 }, // 0x33 '3'
- { 28, 3, 3, 4, 0, -2 }, // 0x34 '4'
- { 30, 3, 3, 4, 0, -2 }, // 0x35 '5'
- { 32, 3, 3, 4, 0, -2 }, // 0x36 '6'
- { 34, 3, 3, 4, 0, -2 }, // 0x37 '7'
- { 36, 3, 3, 4, 0, -2 }, // 0x38 '8'
- { 38, 3, 3, 4, 0, -2 }, // 0x39 '9'
- { 40, 1, 3, 3, 1, -2 }, // 0x3A ':'
- { 41, 2, 3, 3, 0, -1 }, // 0x3B ';'
- { 42, 2, 3, 3, 0, -2 }, // 0x3C '<'
- { 43, 3, 3, 4, 0, -2 }, // 0x3D '='
- { 45, 2, 3, 4, 1, -2 }, // 0x3E '>'
- { 46, 2, 3, 4, 1, -2 }, // 0x3F '?'
- { 47, 3, 3, 4, 0, -2 }, // 0x40 '@'
- { 49, 3, 3, 4, 0, -2 }, // 0x41 'A'
- { 51, 3, 3, 4, 0, -2 }, // 0x42 'B'
- { 53, 3, 3, 4, 0, -2 }, // 0x43 'C'
- { 55, 3, 3, 4, 0, -2 }, // 0x44 'D'
- { 57, 3, 3, 4, 0, -2 }, // 0x45 'E'
- { 59, 3, 3, 4, 0, -2 }, // 0x46 'F'
- { 61, 3, 3, 4, 0, -2 }, // 0x47 'G'
- { 63, 3, 3, 4, 0, -2 }, // 0x48 'H'
- { 65, 1, 3, 3, 1, -2 }, // 0x49 'I'
- { 66, 3, 3, 4, 0, -2 }, // 0x4A 'J'
- { 68, 3, 3, 4, 0, -2 }, // 0x4B 'K'
- { 70, 3, 3, 4, 0, -2 }, // 0x4C 'L'
- { 72, 3, 3, 4, 0, -2 }, // 0x4D 'M'
- { 74, 3, 3, 4, 0, -2 }, // 0x4E 'N'
- { 76, 3, 3, 4, 0, -2 }, // 0x4F 'O'
- { 78, 3, 3, 4, 0, -2 }, // 0x50 'P'
- { 80, 3, 3, 4, 0, -2 }, // 0x51 'Q'
- { 82, 3, 3, 4, 0, -2 }, // 0x52 'R'
- { 84, 3, 3, 4, 0, -2 }, // 0x53 'S'
- { 86, 3, 3, 4, 0, -2 }, // 0x54 'T'
- { 88, 3, 3, 4, 0, -2 }, // 0x55 'U'
- { 90, 3, 3, 4, 0, -2 }, // 0x56 'V'
- { 92, 3, 3, 4, 0, -2 }, // 0x57 'W'
- { 94, 3, 3, 4, 0, -2 }, // 0x58 'X'
- { 96, 3, 3, 4, 0, -2 }, // 0x59 'Y'
- { 98, 3, 3, 4, 0, -2 }, // 0x5A 'Z'
- { 100, 2, 3, 3, 0, -2 }, // 0x5B '['
- { 101, 3, 3, 4, 0, -2 }, // 0x5C '\'
- { 103, 2, 3, 4, 1, -2 }, // 0x5D ']'
- { 104, 3, 2, 4, 0, -2 }, // 0x5E '^'
- { 105, 3, 1, 4, 0, 0 }, // 0x5F '_'
- { 106, 2, 2, 3, 0, -2 }, // 0x60 '`'
- { 107, 2, 2, 3, 0, -1 }, // 0x61 'a'
- { 108, 2, 3, 3, 0, -2 }, // 0x62 'b'
- { 109, 2, 2, 3, 0, -1 }, // 0x63 'c'
- { 110, 2, 3, 3, 0, -2 }, // 0x64 'd'
- { 111, 2, 2, 3, 0, -1 }, // 0x65 'e'
- { 112, 2, 3, 3, 0, -2 }, // 0x66 'f'
- { 113, 2, 3, 3, 0, -1 }, // 0x67 'g'
- { 114, 2, 3, 3, 0, -2 }, // 0x68 'h'
- { 115, 1, 2, 2, 0, -1 }, // 0x69 'i'
- { 116, 2, 3, 3, 0, -1 }, // 0x6A 'j'
- { 117, 3, 3, 4, 0, -2 }, // 0x6B 'k'
- { 119, 2, 3, 3, 0, -2 }, // 0x6C 'l'
- { 120, 3, 2, 4, 0, -1 }, // 0x6D 'm'
- { 121, 3, 2, 4, 0, -1 }, // 0x6E 'n'
- { 122, 2, 2, 3, 0, -1 }, // 0x6F 'o'
- { 123, 2, 3, 3, 0, -1 }, // 0x70 'p'
- { 124, 2, 3, 3, 0, -1 }, // 0x71 'q'
- { 125, 2, 2, 3, 0, -1 }, // 0x72 'r'
- { 126, 2, 2, 3, 0, -1 }, // 0x73 's'
- { 127, 3, 3, 4, 0, -2 }, // 0x74 't'
- { 129, 3, 2, 4, 0, -1 }, // 0x75 'u'
- { 130, 3, 2, 4, 0, -1 }, // 0x76 'v'
- { 131, 3, 2, 4, 0, -1 }, // 0x77 'w'
- { 132, 2, 2, 3, 0, -1 }, // 0x78 'x'
- { 133, 3, 3, 4, 0, -1 }, // 0x79 'y'
- { 135, 2, 2, 3, 0, -1 }, // 0x7A 'z'
- { 136, 3, 3, 4, 0, -2 }, // 0x7B '{'
- { 138, 1, 4, 3, 1, -2 }, // 0x7C '|'
- { 139, 3, 3, 4, 0, -2 }, // 0x7D '}'
- { 141, 3, 2, 4, 0, -2 } }; // 0x7E '~'
-
-const GFXfont Tiny3x3a2pt7b PROGMEM = {
- (uint8_t *)Tiny3x3a2pt7bBitmaps,
- (GFXglyph *)Tiny3x3a2pt7bGlyphs,
- 0x20, 0x7E, 4 };
-
-// Approx. 814 bytes
diff --git a/KugleFirmware/Libraries/Devices/LCD/Fonts/TomThumb.h b/KugleFirmware/Libraries/Devices/LCD/Fonts/TomThumb.h
deleted file mode 100644
index dad420d..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Fonts/TomThumb.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/**
-** The original 3x5 font is licensed under the 3-clause BSD license:
-**
-** Copyright 1999 Brian J. Swetland
-** Copyright 1999 Vassilii Khachaturov
-** Portions (of vt100.c/vt100.h) copyright Dan Marks
-**
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without
-** modification, are permitted provided that the following conditions
-** are met:
-** 1. Redistributions of source code must retain the above copyright
-** notice, this list of conditions, and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright
-** notice, this list of conditions, and the following disclaimer in the
-** documentation and/or other materials provided with the distribution.
-** 3. The name of the authors may not be used to endorse or promote products
-** derived from this software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** Modifications to Tom Thumb for improved readability are from Robey Pointer,
-** see:
-** http://robey.lag.net/2010/01/23/tiny-monospace-font.html
-**
-** The original author does not have any objection to relicensing of Robey
-** Pointer's modifications (in this file) in a more permissive license. See
-** the discussion at the above blog, and also here:
-** http://opengameart.org/forumtopic/how-to-submit-art-using-the-3-clause-bsd-license
-**
-** Feb 21, 2016: Conversion from Linux BDF --> Adafruit GFX font,
-** with the help of this Python script:
-** https://gist.github.com/skelliam/322d421f028545f16f6d
-** William Skellenger (williamj@skellenger.net)
-** Twitter: @skelliam
-**
-*/
-
-#define TOMTHUMB_USE_EXTENDED 0
-
-const uint8_t TomThumbBitmaps[] PROGMEM = {
- 0x00, /* 0x20 space */
- 0x80, 0x80, 0x80, 0x00, 0x80, /* 0x21 exclam */
- 0xA0, 0xA0, /* 0x22 quotedbl */
- 0xA0, 0xE0, 0xA0, 0xE0, 0xA0, /* 0x23 numbersign */
- 0x60, 0xC0, 0x60, 0xC0, 0x40, /* 0x24 dollar */
- 0x80, 0x20, 0x40, 0x80, 0x20, /* 0x25 percent */
- 0xC0, 0xC0, 0xE0, 0xA0, 0x60, /* 0x26 ampersand */
- 0x80, 0x80, /* 0x27 quotesingle */
- 0x40, 0x80, 0x80, 0x80, 0x40, /* 0x28 parenleft */
- 0x80, 0x40, 0x40, 0x40, 0x80, /* 0x29 parenright */
- 0xA0, 0x40, 0xA0, /* 0x2A asterisk */
- 0x40, 0xE0, 0x40, /* 0x2B plus */
- 0x40, 0x80, /* 0x2C comma */
- 0xE0, /* 0x2D hyphen */
- 0x80, /* 0x2E period */
- 0x20, 0x20, 0x40, 0x80, 0x80, /* 0x2F slash */
- 0x60, 0xA0, 0xA0, 0xA0, 0xC0, /* 0x30 zero */
- 0x40, 0xC0, 0x40, 0x40, 0x40, /* 0x31 one */
- 0xC0, 0x20, 0x40, 0x80, 0xE0, /* 0x32 two */
- 0xC0, 0x20, 0x40, 0x20, 0xC0, /* 0x33 three */
- 0xA0, 0xA0, 0xE0, 0x20, 0x20, /* 0x34 four */
- 0xE0, 0x80, 0xC0, 0x20, 0xC0, /* 0x35 five */
- 0x60, 0x80, 0xE0, 0xA0, 0xE0, /* 0x36 six */
- 0xE0, 0x20, 0x40, 0x80, 0x80, /* 0x37 seven */
- 0xE0, 0xA0, 0xE0, 0xA0, 0xE0, /* 0x38 eight */
- 0xE0, 0xA0, 0xE0, 0x20, 0xC0, /* 0x39 nine */
- 0x80, 0x00, 0x80, /* 0x3A colon */
- 0x40, 0x00, 0x40, 0x80, /* 0x3B semicolon */
- 0x20, 0x40, 0x80, 0x40, 0x20, /* 0x3C less */
- 0xE0, 0x00, 0xE0, /* 0x3D equal */
- 0x80, 0x40, 0x20, 0x40, 0x80, /* 0x3E greater */
- 0xE0, 0x20, 0x40, 0x00, 0x40, /* 0x3F question */
- 0x40, 0xA0, 0xE0, 0x80, 0x60, /* 0x40 at */
- 0x40, 0xA0, 0xE0, 0xA0, 0xA0, /* 0x41 A */
- 0xC0, 0xA0, 0xC0, 0xA0, 0xC0, /* 0x42 B */
- 0x60, 0x80, 0x80, 0x80, 0x60, /* 0x43 C */
- 0xC0, 0xA0, 0xA0, 0xA0, 0xC0, /* 0x44 D */
- 0xE0, 0x80, 0xE0, 0x80, 0xE0, /* 0x45 E */
- 0xE0, 0x80, 0xE0, 0x80, 0x80, /* 0x46 F */
- 0x60, 0x80, 0xE0, 0xA0, 0x60, /* 0x47 G */
- 0xA0, 0xA0, 0xE0, 0xA0, 0xA0, /* 0x48 H */
- 0xE0, 0x40, 0x40, 0x40, 0xE0, /* 0x49 I */
- 0x20, 0x20, 0x20, 0xA0, 0x40, /* 0x4A J */
- 0xA0, 0xA0, 0xC0, 0xA0, 0xA0, /* 0x4B K */
- 0x80, 0x80, 0x80, 0x80, 0xE0, /* 0x4C L */
- 0xA0, 0xE0, 0xE0, 0xA0, 0xA0, /* 0x4D M */
- 0xA0, 0xE0, 0xE0, 0xE0, 0xA0, /* 0x4E N */
- 0x40, 0xA0, 0xA0, 0xA0, 0x40, /* 0x4F O */
- 0xC0, 0xA0, 0xC0, 0x80, 0x80, /* 0x50 P */
- 0x40, 0xA0, 0xA0, 0xE0, 0x60, /* 0x51 Q */
- 0xC0, 0xA0, 0xE0, 0xC0, 0xA0, /* 0x52 R */
- 0x60, 0x80, 0x40, 0x20, 0xC0, /* 0x53 S */
- 0xE0, 0x40, 0x40, 0x40, 0x40, /* 0x54 T */
- 0xA0, 0xA0, 0xA0, 0xA0, 0x60, /* 0x55 U */
- 0xA0, 0xA0, 0xA0, 0x40, 0x40, /* 0x56 V */
- 0xA0, 0xA0, 0xE0, 0xE0, 0xA0, /* 0x57 W */
- 0xA0, 0xA0, 0x40, 0xA0, 0xA0, /* 0x58 X */
- 0xA0, 0xA0, 0x40, 0x40, 0x40, /* 0x59 Y */
- 0xE0, 0x20, 0x40, 0x80, 0xE0, /* 0x5A Z */
- 0xE0, 0x80, 0x80, 0x80, 0xE0, /* 0x5B bracketleft */
- 0x80, 0x40, 0x20, /* 0x5C backslash */
- 0xE0, 0x20, 0x20, 0x20, 0xE0, /* 0x5D bracketright */
- 0x40, 0xA0, /* 0x5E asciicircum */
- 0xE0, /* 0x5F underscore */
- 0x80, 0x40, /* 0x60 grave */
- 0xC0, 0x60, 0xA0, 0xE0, /* 0x61 a */
- 0x80, 0xC0, 0xA0, 0xA0, 0xC0, /* 0x62 b */
- 0x60, 0x80, 0x80, 0x60, /* 0x63 c */
- 0x20, 0x60, 0xA0, 0xA0, 0x60, /* 0x64 d */
- 0x60, 0xA0, 0xC0, 0x60, /* 0x65 e */
- 0x20, 0x40, 0xE0, 0x40, 0x40, /* 0x66 f */
- 0x60, 0xA0, 0xE0, 0x20, 0x40, /* 0x67 g */
- 0x80, 0xC0, 0xA0, 0xA0, 0xA0, /* 0x68 h */
- 0x80, 0x00, 0x80, 0x80, 0x80, /* 0x69 i */
- 0x20, 0x00, 0x20, 0x20, 0xA0, 0x40, /* 0x6A j */
- 0x80, 0xA0, 0xC0, 0xC0, 0xA0, /* 0x6B k */
- 0xC0, 0x40, 0x40, 0x40, 0xE0, /* 0x6C l */
- 0xE0, 0xE0, 0xE0, 0xA0, /* 0x6D m */
- 0xC0, 0xA0, 0xA0, 0xA0, /* 0x6E n */
- 0x40, 0xA0, 0xA0, 0x40, /* 0x6F o */
- 0xC0, 0xA0, 0xA0, 0xC0, 0x80, /* 0x70 p */
- 0x60, 0xA0, 0xA0, 0x60, 0x20, /* 0x71 q */
- 0x60, 0x80, 0x80, 0x80, /* 0x72 r */
- 0x60, 0xC0, 0x60, 0xC0, /* 0x73 s */
- 0x40, 0xE0, 0x40, 0x40, 0x60, /* 0x74 t */
- 0xA0, 0xA0, 0xA0, 0x60, /* 0x75 u */
- 0xA0, 0xA0, 0xE0, 0x40, /* 0x76 v */
- 0xA0, 0xE0, 0xE0, 0xE0, /* 0x77 w */
- 0xA0, 0x40, 0x40, 0xA0, /* 0x78 x */
- 0xA0, 0xA0, 0x60, 0x20, 0x40, /* 0x79 y */
- 0xE0, 0x60, 0xC0, 0xE0, /* 0x7A z */
- 0x60, 0x40, 0x80, 0x40, 0x60, /* 0x7B braceleft */
- 0x80, 0x80, 0x00, 0x80, 0x80, /* 0x7C bar */
- 0xC0, 0x40, 0x20, 0x40, 0xC0, /* 0x7D braceright */
- 0x60, 0xC0, /* 0x7E asciitilde */
-#if (TOMTHUMB_USE_EXTENDED)
- 0x80, 0x00, 0x80, 0x80, 0x80, /* 0xA1 exclamdown */
- 0x40, 0xE0, 0x80, 0xE0, 0x40, /* 0xA2 cent */
- 0x60, 0x40, 0xE0, 0x40, 0xE0, /* 0xA3 sterling */
- 0xA0, 0x40, 0xE0, 0x40, 0xA0, /* 0xA4 currency */
- 0xA0, 0xA0, 0x40, 0xE0, 0x40, /* 0xA5 yen */
- 0x80, 0x80, 0x00, 0x80, 0x80, /* 0xA6 brokenbar */
- 0x60, 0x40, 0xA0, 0x40, 0xC0, /* 0xA7 section */
- 0xA0, /* 0xA8 dieresis */
- 0x60, 0x80, 0x60, /* 0xA9 copyright */
- 0x60, 0xA0, 0xE0, 0x00, 0xE0, /* 0xAA ordfeminine */
- 0x40, 0x80, 0x40, /* 0xAB guillemotleft */
- 0xE0, 0x20, /* 0xAC logicalnot */
- 0xC0, /* 0xAD softhyphen */
- 0xC0, 0xC0, 0xA0, /* 0xAE registered */
- 0xE0, /* 0xAF macron */
- 0x40, 0xA0, 0x40, /* 0xB0 degree */
- 0x40, 0xE0, 0x40, 0x00, 0xE0, /* 0xB1 plusminus */
- 0xC0, 0x40, 0x60, /* 0xB2 twosuperior */
- 0xE0, 0x60, 0xE0, /* 0xB3 threesuperior */
- 0x40, 0x80, /* 0xB4 acute */
- 0xA0, 0xA0, 0xA0, 0xC0, 0x80, /* 0xB5 mu */
- 0x60, 0xA0, 0x60, 0x60, 0x60, /* 0xB6 paragraph */
- 0xE0, 0xE0, 0xE0, /* 0xB7 periodcentered */
- 0x40, 0x20, 0xC0, /* 0xB8 cedilla */
- 0x80, 0x80, 0x80, /* 0xB9 onesuperior */
- 0x40, 0xA0, 0x40, 0x00, 0xE0, /* 0xBA ordmasculine */
- 0x80, 0x40, 0x80, /* 0xBB guillemotright */
- 0x80, 0x80, 0x00, 0x60, 0x20, /* 0xBC onequarter */
- 0x80, 0x80, 0x00, 0xC0, 0x60, /* 0xBD onehalf */
- 0xC0, 0xC0, 0x00, 0x60, 0x20, /* 0xBE threequarters */
- 0x40, 0x00, 0x40, 0x80, 0xE0, /* 0xBF questiondown */
- 0x40, 0x20, 0x40, 0xE0, 0xA0, /* 0xC0 Agrave */
- 0x40, 0x80, 0x40, 0xE0, 0xA0, /* 0xC1 Aacute */
- 0xE0, 0x00, 0x40, 0xE0, 0xA0, /* 0xC2 Acircumflex */
- 0x60, 0xC0, 0x40, 0xE0, 0xA0, /* 0xC3 Atilde */
- 0xA0, 0x40, 0xA0, 0xE0, 0xA0, /* 0xC4 Adieresis */
- 0xC0, 0xC0, 0xA0, 0xE0, 0xA0, /* 0xC5 Aring */
- 0x60, 0xC0, 0xE0, 0xC0, 0xE0, /* 0xC6 AE */
- 0x60, 0x80, 0x80, 0x60, 0x20, 0x40, /* 0xC7 Ccedilla */
- 0x40, 0x20, 0xE0, 0xC0, 0xE0, /* 0xC8 Egrave */
- 0x40, 0x80, 0xE0, 0xC0, 0xE0, /* 0xC9 Eacute */
- 0xE0, 0x00, 0xE0, 0xC0, 0xE0, /* 0xCA Ecircumflex */
- 0xA0, 0x00, 0xE0, 0xC0, 0xE0, /* 0xCB Edieresis */
- 0x40, 0x20, 0xE0, 0x40, 0xE0, /* 0xCC Igrave */
- 0x40, 0x80, 0xE0, 0x40, 0xE0, /* 0xCD Iacute */
- 0xE0, 0x00, 0xE0, 0x40, 0xE0, /* 0xCE Icircumflex */
- 0xA0, 0x00, 0xE0, 0x40, 0xE0, /* 0xCF Idieresis */
- 0xC0, 0xA0, 0xE0, 0xA0, 0xC0, /* 0xD0 Eth */
- 0xC0, 0x60, 0xA0, 0xE0, 0xA0, /* 0xD1 Ntilde */
- 0x40, 0x20, 0xE0, 0xA0, 0xE0, /* 0xD2 Ograve */
- 0x40, 0x80, 0xE0, 0xA0, 0xE0, /* 0xD3 Oacute */
- 0xE0, 0x00, 0xE0, 0xA0, 0xE0, /* 0xD4 Ocircumflex */
- 0xC0, 0x60, 0xE0, 0xA0, 0xE0, /* 0xD5 Otilde */
- 0xA0, 0x00, 0xE0, 0xA0, 0xE0, /* 0xD6 Odieresis */
- 0xA0, 0x40, 0xA0, /* 0xD7 multiply */
- 0x60, 0xA0, 0xE0, 0xA0, 0xC0, /* 0xD8 Oslash */
- 0x80, 0x40, 0xA0, 0xA0, 0xE0, /* 0xD9 Ugrave */
- 0x20, 0x40, 0xA0, 0xA0, 0xE0, /* 0xDA Uacute */
- 0xE0, 0x00, 0xA0, 0xA0, 0xE0, /* 0xDB Ucircumflex */
- 0xA0, 0x00, 0xA0, 0xA0, 0xE0, /* 0xDC Udieresis */
- 0x20, 0x40, 0xA0, 0xE0, 0x40, /* 0xDD Yacute */
- 0x80, 0xE0, 0xA0, 0xE0, 0x80, /* 0xDE Thorn */
- 0x60, 0xA0, 0xC0, 0xA0, 0xC0, 0x80, /* 0xDF germandbls */
- 0x40, 0x20, 0x60, 0xA0, 0xE0, /* 0xE0 agrave */
- 0x40, 0x80, 0x60, 0xA0, 0xE0, /* 0xE1 aacute */
- 0xE0, 0x00, 0x60, 0xA0, 0xE0, /* 0xE2 acircumflex */
- 0x60, 0xC0, 0x60, 0xA0, 0xE0, /* 0xE3 atilde */
- 0xA0, 0x00, 0x60, 0xA0, 0xE0, /* 0xE4 adieresis */
- 0x60, 0x60, 0x60, 0xA0, 0xE0, /* 0xE5 aring */
- 0x60, 0xE0, 0xE0, 0xC0, /* 0xE6 ae */
- 0x60, 0x80, 0x60, 0x20, 0x40, /* 0xE7 ccedilla */
- 0x40, 0x20, 0x60, 0xE0, 0x60, /* 0xE8 egrave */
- 0x40, 0x80, 0x60, 0xE0, 0x60, /* 0xE9 eacute */
- 0xE0, 0x00, 0x60, 0xE0, 0x60, /* 0xEA ecircumflex */
- 0xA0, 0x00, 0x60, 0xE0, 0x60, /* 0xEB edieresis */
- 0x80, 0x40, 0x80, 0x80, 0x80, /* 0xEC igrave */
- 0x40, 0x80, 0x40, 0x40, 0x40, /* 0xED iacute */
- 0xE0, 0x00, 0x40, 0x40, 0x40, /* 0xEE icircumflex */
- 0xA0, 0x00, 0x40, 0x40, 0x40, /* 0xEF idieresis */
- 0x60, 0xC0, 0x60, 0xA0, 0x60, /* 0xF0 eth */
- 0xC0, 0x60, 0xC0, 0xA0, 0xA0, /* 0xF1 ntilde */
- 0x40, 0x20, 0x40, 0xA0, 0x40, /* 0xF2 ograve */
- 0x40, 0x80, 0x40, 0xA0, 0x40, /* 0xF3 oacute */
- 0xE0, 0x00, 0x40, 0xA0, 0x40, /* 0xF4 ocircumflex */
- 0xC0, 0x60, 0x40, 0xA0, 0x40, /* 0xF5 otilde */
- 0xA0, 0x00, 0x40, 0xA0, 0x40, /* 0xF6 odieresis */
- 0x40, 0x00, 0xE0, 0x00, 0x40, /* 0xF7 divide */
- 0x60, 0xE0, 0xA0, 0xC0, /* 0xF8 oslash */
- 0x80, 0x40, 0xA0, 0xA0, 0x60, /* 0xF9 ugrave */
- 0x20, 0x40, 0xA0, 0xA0, 0x60, /* 0xFA uacute */
- 0xE0, 0x00, 0xA0, 0xA0, 0x60, /* 0xFB ucircumflex */
- 0xA0, 0x00, 0xA0, 0xA0, 0x60, /* 0xFC udieresis */
- 0x20, 0x40, 0xA0, 0x60, 0x20, 0x40, /* 0xFD yacute */
- 0x80, 0xC0, 0xA0, 0xC0, 0x80, /* 0xFE thorn */
- 0xA0, 0x00, 0xA0, 0x60, 0x20, 0x40, /* 0xFF ydieresis */
- 0x00, /* 0x11D gcircumflex */
- 0x60, 0xC0, 0xE0, 0xC0, 0x60, /* 0x152 OE */
- 0x60, 0xE0, 0xC0, 0xE0, /* 0x153 oe */
- 0xA0, 0x60, 0xC0, 0x60, 0xC0, /* 0x160 Scaron */
- 0xA0, 0x60, 0xC0, 0x60, 0xC0, /* 0x161 scaron */
- 0xA0, 0x00, 0xA0, 0x40, 0x40, /* 0x178 Ydieresis */
- 0xA0, 0xE0, 0x60, 0xC0, 0xE0, /* 0x17D Zcaron */
- 0xA0, 0xE0, 0x60, 0xC0, 0xE0, /* 0x17E zcaron */
- 0x00, /* 0xEA4 uni0EA4 */
- 0x00, /* 0x13A0 uni13A0 */
- 0x80, /* 0x2022 bullet */
- 0xA0, /* 0x2026 ellipsis */
- 0x60, 0xE0, 0xE0, 0xC0, 0x60, /* 0x20AC Euro */
- 0xE0, 0xA0, 0xA0, 0xA0, 0xE0, /* 0xFFFD uniFFFD */
-#endif /* (TOMTHUMB_USE_EXTENDED) */
- };
-
-
-/* {offset, width, height, advance cursor, x offset, y offset} */
-const GFXglyph TomThumbGlyphs[] PROGMEM = {
- { 0, 8, 1, 2, 0, -5 }, /* 0x20 space */
- { 1, 8, 5, 2, 0, -5 }, /* 0x21 exclam */
- { 6, 8, 2, 4, 0, -5 }, /* 0x22 quotedbl */
- { 8, 8, 5, 4, 0, -5 }, /* 0x23 numbersign */
- { 13, 8, 5, 4, 0, -5 }, /* 0x24 dollar */
- { 18, 8, 5, 4, 0, -5 }, /* 0x25 percent */
- { 23, 8, 5, 4, 0, -5 }, /* 0x26 ampersand */
- { 28, 8, 2, 2, 0, -5 }, /* 0x27 quotesingle */
- { 30, 8, 5, 3, 0, -5 }, /* 0x28 parenleft */
- { 35, 8, 5, 3, 0, -5 }, /* 0x29 parenright */
- { 40, 8, 3, 4, 0, -5 }, /* 0x2A asterisk */
- { 43, 8, 3, 4, 0, -4 }, /* 0x2B plus */
- { 46, 8, 2, 3, 0, -2 }, /* 0x2C comma */
- { 48, 8, 1, 4, 0, -3 }, /* 0x2D hyphen */
- { 49, 8, 1, 2, 0, -1 }, /* 0x2E period */
- { 50, 8, 5, 4, 0, -5 }, /* 0x2F slash */
- { 55, 8, 5, 4, 0, -5 }, /* 0x30 zero */
- { 60, 8, 5, 3, 0, -5 }, /* 0x31 one */
- { 65, 8, 5, 4, 0, -5 }, /* 0x32 two */
- { 70, 8, 5, 4, 0, -5 }, /* 0x33 three */
- { 75, 8, 5, 4, 0, -5 }, /* 0x34 four */
- { 80, 8, 5, 4, 0, -5 }, /* 0x35 five */
- { 85, 8, 5, 4, 0, -5 }, /* 0x36 six */
- { 90, 8, 5, 4, 0, -5 }, /* 0x37 seven */
- { 95, 8, 5, 4, 0, -5 }, /* 0x38 eight */
- { 100, 8, 5, 4, 0, -5 }, /* 0x39 nine */
- { 105, 8, 3, 2, 0, -4 }, /* 0x3A colon */
- { 108, 8, 4, 3, 0, -4 }, /* 0x3B semicolon */
- { 112, 8, 5, 4, 0, -5 }, /* 0x3C less */
- { 117, 8, 3, 4, 0, -4 }, /* 0x3D equal */
- { 120, 8, 5, 4, 0, -5 }, /* 0x3E greater */
- { 125, 8, 5, 4, 0, -5 }, /* 0x3F question */
- { 130, 8, 5, 4, 0, -5 }, /* 0x40 at */
- { 135, 8, 5, 4, 0, -5 }, /* 0x41 A */
- { 140, 8, 5, 4, 0, -5 }, /* 0x42 B */
- { 145, 8, 5, 4, 0, -5 }, /* 0x43 C */
- { 150, 8, 5, 4, 0, -5 }, /* 0x44 D */
- { 155, 8, 5, 4, 0, -5 }, /* 0x45 E */
- { 160, 8, 5, 4, 0, -5 }, /* 0x46 F */
- { 165, 8, 5, 4, 0, -5 }, /* 0x47 G */
- { 170, 8, 5, 4, 0, -5 }, /* 0x48 H */
- { 175, 8, 5, 4, 0, -5 }, /* 0x49 I */
- { 180, 8, 5, 4, 0, -5 }, /* 0x4A J */
- { 185, 8, 5, 4, 0, -5 }, /* 0x4B K */
- { 190, 8, 5, 4, 0, -5 }, /* 0x4C L */
- { 195, 8, 5, 4, 0, -5 }, /* 0x4D M */
- { 200, 8, 5, 4, 0, -5 }, /* 0x4E N */
- { 205, 8, 5, 4, 0, -5 }, /* 0x4F O */
- { 210, 8, 5, 4, 0, -5 }, /* 0x50 P */
- { 215, 8, 5, 4, 0, -5 }, /* 0x51 Q */
- { 220, 8, 5, 4, 0, -5 }, /* 0x52 R */
- { 225, 8, 5, 4, 0, -5 }, /* 0x53 S */
- { 230, 8, 5, 4, 0, -5 }, /* 0x54 T */
- { 235, 8, 5, 4, 0, -5 }, /* 0x55 U */
- { 240, 8, 5, 4, 0, -5 }, /* 0x56 V */
- { 245, 8, 5, 4, 0, -5 }, /* 0x57 W */
- { 250, 8, 5, 4, 0, -5 }, /* 0x58 X */
- { 255, 8, 5, 4, 0, -5 }, /* 0x59 Y */
- { 260, 8, 5, 4, 0, -5 }, /* 0x5A Z */
- { 265, 8, 5, 4, 0, -5 }, /* 0x5B bracketleft */
- { 270, 8, 3, 4, 0, -4 }, /* 0x5C backslash */
- { 273, 8, 5, 4, 0, -5 }, /* 0x5D bracketright */
- { 278, 8, 2, 4, 0, -5 }, /* 0x5E asciicircum */
- { 280, 8, 1, 4, 0, -1 }, /* 0x5F underscore */
- { 281, 8, 2, 3, 0, -5 }, /* 0x60 grave */
- { 283, 8, 4, 4, 0, -4 }, /* 0x61 a */
- { 287, 8, 5, 4, 0, -5 }, /* 0x62 b */
- { 292, 8, 4, 4, 0, -4 }, /* 0x63 c */
- { 296, 8, 5, 4, 0, -5 }, /* 0x64 d */
- { 301, 8, 4, 4, 0, -4 }, /* 0x65 e */
- { 305, 8, 5, 4, 0, -5 }, /* 0x66 f */
- { 310, 8, 5, 4, 0, -4 }, /* 0x67 g */
- { 315, 8, 5, 4, 0, -5 }, /* 0x68 h */
- { 320, 8, 5, 2, 0, -5 }, /* 0x69 i */
- { 325, 8, 6, 4, 0, -5 }, /* 0x6A j */
- { 331, 8, 5, 4, 0, -5 }, /* 0x6B k */
- { 336, 8, 5, 4, 0, -5 }, /* 0x6C l */
- { 341, 8, 4, 4, 0, -4 }, /* 0x6D m */
- { 345, 8, 4, 4, 0, -4 }, /* 0x6E n */
- { 349, 8, 4, 4, 0, -4 }, /* 0x6F o */
- { 353, 8, 5, 4, 0, -4 }, /* 0x70 p */
- { 358, 8, 5, 4, 0, -4 }, /* 0x71 q */
- { 363, 8, 4, 4, 0, -4 }, /* 0x72 r */
- { 367, 8, 4, 4, 0, -4 }, /* 0x73 s */
- { 371, 8, 5, 4, 0, -5 }, /* 0x74 t */
- { 376, 8, 4, 4, 0, -4 }, /* 0x75 u */
- { 380, 8, 4, 4, 0, -4 }, /* 0x76 v */
- { 384, 8, 4, 4, 0, -4 }, /* 0x77 w */
- { 388, 8, 4, 4, 0, -4 }, /* 0x78 x */
- { 392, 8, 5, 4, 0, -4 }, /* 0x79 y */
- { 397, 8, 4, 4, 0, -4 }, /* 0x7A z */
- { 401, 8, 5, 4, 0, -5 }, /* 0x7B braceleft */
- { 406, 8, 5, 2, 0, -5 }, /* 0x7C bar */
- { 411, 8, 5, 4, 0, -5 }, /* 0x7D braceright */
- { 416, 8, 2, 4, 0, -5 }, /* 0x7E asciitilde */
-#if (TOMTHUMB_USE_EXTENDED)
- { 418, 8, 5, 2, 0, -5 }, /* 0xA1 exclamdown */
- { 423, 8, 5, 4, 0, -5 }, /* 0xA2 cent */
- { 428, 8, 5, 4, 0, -5 }, /* 0xA3 sterling */
- { 433, 8, 5, 4, 0, -5 }, /* 0xA4 currency */
- { 438, 8, 5, 4, 0, -5 }, /* 0xA5 yen */
- { 443, 8, 5, 2, 0, -5 }, /* 0xA6 brokenbar */
- { 448, 8, 5, 4, 0, -5 }, /* 0xA7 section */
- { 453, 8, 1, 4, 0, -5 }, /* 0xA8 dieresis */
- { 454, 8, 3, 4, 0, -5 }, /* 0xA9 copyright */
- { 457, 8, 5, 4, 0, -5 }, /* 0xAA ordfeminine */
- { 462, 8, 3, 3, 0, -5 }, /* 0xAB guillemotleft */
- { 465, 8, 2, 4, 0, -4 }, /* 0xAC logicalnot */
- { 467, 8, 1, 3, 0, -3 }, /* 0xAD softhyphen */
- { 468, 8, 3, 4, 0, -5 }, /* 0xAE registered */
- { 471, 8, 1, 4, 0, -5 }, /* 0xAF macron */
- { 472, 8, 3, 4, 0, -5 }, /* 0xB0 degree */
- { 475, 8, 5, 4, 0, -5 }, /* 0xB1 plusminus */
- { 480, 8, 3, 4, 0, -5 }, /* 0xB2 twosuperior */
- { 483, 8, 3, 4, 0, -5 }, /* 0xB3 threesuperior */
- { 486, 8, 2, 3, 0, -5 }, /* 0xB4 acute */
- { 488, 8, 5, 4, 0, -5 }, /* 0xB5 mu */
- { 493, 8, 5, 4, 0, -5 }, /* 0xB6 paragraph */
- { 498, 8, 3, 4, 0, -4 }, /* 0xB7 periodcentered */
- { 501, 8, 3, 4, 0, -3 }, /* 0xB8 cedilla */
- { 504, 8, 3, 2, 0, -5 }, /* 0xB9 onesuperior */
- { 507, 8, 5, 4, 0, -5 }, /* 0xBA ordmasculine */
- { 512, 8, 3, 3, 0, -5 }, /* 0xBB guillemotright */
- { 515, 8, 5, 4, 0, -5 }, /* 0xBC onequarter */
- { 520, 8, 5, 4, 0, -5 }, /* 0xBD onehalf */
- { 525, 8, 5, 4, 0, -5 }, /* 0xBE threequarters */
- { 530, 8, 5, 4, 0, -5 }, /* 0xBF questiondown */
- { 535, 8, 5, 4, 0, -5 }, /* 0xC0 Agrave */
- { 540, 8, 5, 4, 0, -5 }, /* 0xC1 Aacute */
- { 545, 8, 5, 4, 0, -5 }, /* 0xC2 Acircumflex */
- { 550, 8, 5, 4, 0, -5 }, /* 0xC3 Atilde */
- { 555, 8, 5, 4, 0, -5 }, /* 0xC4 Adieresis */
- { 560, 8, 5, 4, 0, -5 }, /* 0xC5 Aring */
- { 565, 8, 5, 4, 0, -5 }, /* 0xC6 AE */
- { 570, 8, 6, 4, 0, -5 }, /* 0xC7 Ccedilla */
- { 576, 8, 5, 4, 0, -5 }, /* 0xC8 Egrave */
- { 581, 8, 5, 4, 0, -5 }, /* 0xC9 Eacute */
- { 586, 8, 5, 4, 0, -5 }, /* 0xCA Ecircumflex */
- { 591, 8, 5, 4, 0, -5 }, /* 0xCB Edieresis */
- { 596, 8, 5, 4, 0, -5 }, /* 0xCC Igrave */
- { 601, 8, 5, 4, 0, -5 }, /* 0xCD Iacute */
- { 606, 8, 5, 4, 0, -5 }, /* 0xCE Icircumflex */
- { 611, 8, 5, 4, 0, -5 }, /* 0xCF Idieresis */
- { 616, 8, 5, 4, 0, -5 }, /* 0xD0 Eth */
- { 621, 8, 5, 4, 0, -5 }, /* 0xD1 Ntilde */
- { 626, 8, 5, 4, 0, -5 }, /* 0xD2 Ograve */
- { 631, 8, 5, 4, 0, -5 }, /* 0xD3 Oacute */
- { 636, 8, 5, 4, 0, -5 }, /* 0xD4 Ocircumflex */
- { 641, 8, 5, 4, 0, -5 }, /* 0xD5 Otilde */
- { 646, 8, 5, 4, 0, -5 }, /* 0xD6 Odieresis */
- { 651, 8, 3, 4, 0, -4 }, /* 0xD7 multiply */
- { 654, 8, 5, 4, 0, -5 }, /* 0xD8 Oslash */
- { 659, 8, 5, 4, 0, -5 }, /* 0xD9 Ugrave */
- { 664, 8, 5, 4, 0, -5 }, /* 0xDA Uacute */
- { 669, 8, 5, 4, 0, -5 }, /* 0xDB Ucircumflex */
- { 674, 8, 5, 4, 0, -5 }, /* 0xDC Udieresis */
- { 679, 8, 5, 4, 0, -5 }, /* 0xDD Yacute */
- { 684, 8, 5, 4, 0, -5 }, /* 0xDE Thorn */
- { 689, 8, 6, 4, 0, -5 }, /* 0xDF germandbls */
- { 695, 8, 5, 4, 0, -5 }, /* 0xE0 agrave */
- { 700, 8, 5, 4, 0, -5 }, /* 0xE1 aacute */
- { 705, 8, 5, 4, 0, -5 }, /* 0xE2 acircumflex */
- { 710, 8, 5, 4, 0, -5 }, /* 0xE3 atilde */
- { 715, 8, 5, 4, 0, -5 }, /* 0xE4 adieresis */
- { 720, 8, 5, 4, 0, -5 }, /* 0xE5 aring */
- { 725, 8, 4, 4, 0, -4 }, /* 0xE6 ae */
- { 729, 8, 5, 4, 0, -4 }, /* 0xE7 ccedilla */
- { 734, 8, 5, 4, 0, -5 }, /* 0xE8 egrave */
- { 739, 8, 5, 4, 0, -5 }, /* 0xE9 eacute */
- { 744, 8, 5, 4, 0, -5 }, /* 0xEA ecircumflex */
- { 749, 8, 5, 4, 0, -5 }, /* 0xEB edieresis */
- { 754, 8, 5, 3, 0, -5 }, /* 0xEC igrave */
- { 759, 8, 5, 3, 0, -5 }, /* 0xED iacute */
- { 764, 8, 5, 4, 0, -5 }, /* 0xEE icircumflex */
- { 769, 8, 5, 4, 0, -5 }, /* 0xEF idieresis */
- { 774, 8, 5, 4, 0, -5 }, /* 0xF0 eth */
- { 779, 8, 5, 4, 0, -5 }, /* 0xF1 ntilde */
- { 784, 8, 5, 4, 0, -5 }, /* 0xF2 ograve */
- { 789, 8, 5, 4, 0, -5 }, /* 0xF3 oacute */
- { 794, 8, 5, 4, 0, -5 }, /* 0xF4 ocircumflex */
- { 799, 8, 5, 4, 0, -5 }, /* 0xF5 otilde */
- { 804, 8, 5, 4, 0, -5 }, /* 0xF6 odieresis */
- { 809, 8, 5, 4, 0, -5 }, /* 0xF7 divide */
- { 814, 8, 4, 4, 0, -4 }, /* 0xF8 oslash */
- { 818, 8, 5, 4, 0, -5 }, /* 0xF9 ugrave */
- { 823, 8, 5, 4, 0, -5 }, /* 0xFA uacute */
- { 828, 8, 5, 4, 0, -5 }, /* 0xFB ucircumflex */
- { 833, 8, 5, 4, 0, -5 }, /* 0xFC udieresis */
- { 838, 8, 6, 4, 0, -5 }, /* 0xFD yacute */
- { 844, 8, 5, 4, 0, -4 }, /* 0xFE thorn */
- { 849, 8, 6, 4, 0, -5 }, /* 0xFF ydieresis */
- { 855, 8, 1, 2, 0, -1 }, /* 0x11D gcircumflex */
- { 856, 8, 5, 4, 0, -5 }, /* 0x152 OE */
- { 861, 8, 4, 4, 0, -4 }, /* 0x153 oe */
- { 865, 8, 5, 4, 0, -5 }, /* 0x160 Scaron */
- { 870, 8, 5, 4, 0, -5 }, /* 0x161 scaron */
- { 875, 8, 5, 4, 0, -5 }, /* 0x178 Ydieresis */
- { 880, 8, 5, 4, 0, -5 }, /* 0x17D Zcaron */
- { 885, 8, 5, 4, 0, -5 }, /* 0x17E zcaron */
- { 890, 8, 1, 2, 0, -1 }, /* 0xEA4 uni0EA4 */
- { 891, 8, 1, 2, 0, -1 }, /* 0x13A0 uni13A0 */
- { 892, 8, 1, 2, 0, -3 }, /* 0x2022 bullet */
- { 893, 8, 1, 4, 0, -1 }, /* 0x2026 ellipsis */
- { 894, 8, 5, 4, 0, -5 }, /* 0x20AC Euro */
- { 899, 8, 5, 4, 0, -5 }, /* 0xFFFD uniFFFD */
-#endif /* (TOMTHUMB_USE_EXTENDED) */
-};
-
-const GFXfont TomThumb PROGMEM = {
- (uint8_t *)TomThumbBitmaps,
- (GFXglyph *)TomThumbGlyphs,
- 0x20, 0x7E, 6 };
diff --git a/KugleFirmware/Libraries/Devices/LCD/LCD.h b/KugleFirmware/Libraries/Devices/LCD/LCD.h
deleted file mode 100644
index cc85f6b..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/LCD.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-#ifndef DEVICES_LCD_H
-#define DEVICES_LCD_H
-
-#include "Adafruit_SPITFT.h"
-
-#endif
diff --git a/KugleFirmware/Libraries/Devices/LCD/Print.cpp b/KugleFirmware/Libraries/Devices/LCD/Print.cpp
deleted file mode 100644
index 7f8f7d8..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Print.cpp
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- Print.cpp - Base class that provides print() and println()
- Copyright (c) 2008 David A. Mellis. All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-
- Modified 23 November 2006 by David A. Mellis
- */
-#include
-#include
-#include
-#include // for std::string class
-#include
-#include "Print.h"
-// Public Methods //////////////////////////////////////////////////////////////
-/* default implementation: may be overridden */
-void Print::write(const char *str)
-{
- while (*str)
- write(*str++);
-}
-/* default implementation: may be overridden */
-void Print::write(const uint8_t *buffer, size_t size)
-{
- while (size--)
- write(*buffer++);
-}
-void Print::print(const std::string &s)
-{
- for (unsigned int i = 0; i < s.length(); i++) {
- write(s[i]);
- }
-}
-void Print::print(const char str[])
-{
- write(str);
-}
-void Print::print(char c, int base)
-{
- print((long) c, base);
-}
-void Print::print(unsigned char b, int base)
-{
- print((unsigned long) b, base);
-}
-void Print::print(int n, int base)
-{
- print((long) n, base);
-}
-void Print::print(unsigned int n, int base)
-{
- print((unsigned long) n, base);
-}
-void Print::print(long n, int base)
-{
- if (base == 0) {
- write(n);
- } else if (base == 10) {
- if (n < 0) {
- print('-');
- n = -n;
- }
- printNumber(n, 10);
- } else {
- printNumber(n, base);
- }
-}
-void Print::print(unsigned long n, int base)
-{
- if (base == 0) write(n);
- else printNumber(n, base);
-}
-void Print::print(double n, int digits)
-{
- printFloat(n, digits);
-}
-void Print::println(void)
-{
- print('\r');
- print('\n');
-}
-void Print::println(const std::string &s)
-{
- print(s);
- println();
-}
-void Print::println(const char c[])
-{
- print(c);
- println();
-}
-void Print::println(char c, int base)
-{
- print(c, base);
- println();
-}
-void Print::println(unsigned char b, int base)
-{
- print(b, base);
- println();
-}
-void Print::println(int n, int base)
-{
- print(n, base);
- println();
-}
-void Print::println(unsigned int n, int base)
-{
- print(n, base);
- println();
-}
-void Print::println(long n, int base)
-{
- print(n, base);
- println();
-}
-void Print::println(unsigned long n, int base)
-{
- print(n, base);
- println();
-}
-void Print::println(double n, int digits)
-{
- print(n, digits);
- println();
-}
-// Private Methods /////////////////////////////////////////////////////////////
-void Print::printNumber(unsigned long n, uint8_t base)
-{
- unsigned char buf[8 * sizeof(long)]; // Assumes 8-bit chars.
- unsigned long i = 0;
- if (n == 0) {
- print('0');
- return;
- }
- while (n > 0) {
- buf[i++] = n % base;
- n /= base;
- }
- for (; i > 0; i--)
- print((char) (buf[i - 1] < 10 ?
- '0' + buf[i - 1] :
- 'A' + buf[i - 1] - 10));
-}
-void Print::printFloat(double number, uint8_t digits)
-{
- // Handle negative numbers
- if (number < 0.0)
- {
- print('-');
- number = -number;
- }
- // Round correctly so that print(1.999, 2) prints as "2.00"
- double rounding = 0.5;
- for (uint8_t i=0; i 0)
- print(".");
- // Extract digits from the remainder one at a time
- while (digits-- > 0)
- {
- remainder *= 10.0;
- int toPrint = int(remainder);
- print(toPrint);
- remainder -= toPrint;
- }
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/Print.h b/KugleFirmware/Libraries/Devices/LCD/Print.h
deleted file mode 100644
index 9a9b03c..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/Print.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- Print.h - Base class that provides print() and println()
- Copyright (c) 2008 David A. Mellis. All right reserved.
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-#ifndef Print_h
-#define Print_h
-#include
-#include // for size_t
-#include // for std::string
-#define DEC 10
-#define HEX 16
-#define OCT 8
-#define BIN 2
-#define BYTE 0
-class Print
-{
- private:
- void printNumber(unsigned long, uint8_t);
- void printFloat(double, uint8_t);
- public:
- virtual void write(uint8_t) = 0;
- virtual void write(const char *str);
- virtual void write(const uint8_t *buffer, size_t size);
-
- void print(const std::string &);
- void print(const char[]);
- void print(char, int = BYTE);
- void print(unsigned char, int = BYTE);
- void print(int, int = DEC);
- void print(unsigned int, int = DEC);
- void print(long, int = DEC);
- void print(unsigned long, int = DEC);
- void print(double, int = 2);
- void println(const std::string &s);
- void println(const char[]);
- void println(char, int = BYTE);
- void println(unsigned char, int = BYTE);
- void println(int, int = DEC);
- void println(unsigned int, int = DEC);
- void println(long, int = DEC);
- void println(unsigned long, int = DEC);
- void println(double, int = 2);
- void println(void);
-};
-#endif
diff --git a/KugleFirmware/Libraries/Devices/LCD/README.md b/KugleFirmware/Libraries/Devices/LCD/README.md
deleted file mode 100644
index 746c8d5..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/README.md
+++ /dev/null
@@ -1,25 +0,0 @@
-This folder contains a modified version of the HX8357 library from https://github.com/adafruit/Adafruit_HX8357_Library
-
-# Adafruit HX8357 Arduino Library [](https://travis-ci.org/adafruit/Adafruit_HX8357_Library)
-
-This is a library for the Adafruit HX8357 display products
-
-This library works with the Adafruit 3.5" Breakout
- * http://www.adafruit.com/products/2050
-And the 3.5" TFT FeatherWing
- * https://www.adafruit.com/product/3651
-
-Check out the links above for our tutorials and wiring diagrams.
-These displays use SPI to communicate, 4 or 5 pins are required
-to interface (RST is optional).
-
-Adafruit invests time and resources providing this open source code,
-please support Adafruit and open-source hardware by purchasing
-products from Adafruit!
-
-Written by Limor Fried/Ladyada for Adafruit Industries.
-MIT license, all text above must be included in any redistribution
-
-Recent Arduino IDE releases include the Library Manager for easy installation. Otherwise, to download, click the DOWNLOAD ZIP button, uncompress and rename the uncompressed folder Adafruit_HX8357. Confirm that the Adafruit_HX8357 folder contains Adafruit_HX8357.cpp and Adafruit_HX8357.h. Place the Adafruit_HX8357 library folder your ArduinoSketchFolder/Libraries/ folder. You may need to create the Libraries subfolder if its your first library. Restart the IDE.
-
-Also requires the Adafruit_GFX library for Arduino.
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/bitmapdraw_featherwing/.mega2560.test.skip b/KugleFirmware/Libraries/Devices/LCD/examples/bitmapdraw_featherwing/.mega2560.test.skip
deleted file mode 100644
index e69de29..0000000
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/bitmapdraw_featherwing/bitmapdraw_featherwing.ino b/KugleFirmware/Libraries/Devices/LCD/examples/bitmapdraw_featherwing/bitmapdraw_featherwing.ino
deleted file mode 100644
index 5e7205e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/bitmapdraw_featherwing/bitmapdraw_featherwing.ino
+++ /dev/null
@@ -1,282 +0,0 @@
-/***************************************************
- This is our library for the Adafruit HX8357D FeatherWing
- ----> http://www.adafruit.com/products/3651
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-#include
-#include // Core graphics library
-#include
-#include
-#include
-
-
-#ifdef ESP8266
- #define STMPE_CS 16
- #define TFT_CS 0
- #define TFT_DC 15
- #define SD_CS 2
-#endif
-#ifdef ESP32
- #define STMPE_CS 32
- #define TFT_CS 15
- #define TFT_DC 33
- #define SD_CS 14
-#endif
-#ifdef TEENSYDUINO
- #define TFT_DC 10
- #define TFT_CS 4
- #define STMPE_CS 3
- #define SD_CS 8
-#endif
-#ifdef ARDUINO_STM32_FEATHER
- #define TFT_DC PB4
- #define TFT_CS PA15
- #define STMPE_CS PC7
- #define SD_CS PC5
-#endif
-#ifdef ARDUINO_FEATHER52
- #define STMPE_CS 30
- #define TFT_CS 31
- #define TFT_DC 11
- #define SD_CS 27
-#endif
-#if defined(ARDUINO_MAX32620FTHR) || defined(ARDUINO_MAX32630FTHR)
- #define TFT_DC P5_4
- #define TFT_CS P5_3
- #define STMPE_CS P3_3
- #define SD_CS P3_2
-#endif
-
-// Anything else!
-#if defined (__AVR_ATmega32U4__) || defined(ARDUINO_SAMD_FEATHER_M0) || defined (__AVR_ATmega328P__) || defined(ARDUINO_SAMD_ZERO) || defined(__SAMD51__) || defined(__SAM3X8E__)
- #define STMPE_CS 6
- #define TFT_CS 9
- #define TFT_DC 10
- #define SD_CS 5
-#endif
-
-
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC);
-Adafruit_STMPE610 ts = Adafruit_STMPE610(STMPE_CS);
-
-// This is calibration data for the raw touch data to the screen coordinates
-#define TS_MINX 3800
-#define TS_MAXX 100
-#define TS_MINY 100
-#define TS_MAXY 3750
-
-// Size of the color selection boxes and the paintbrush size
-#define BOXSIZE 40
-#define PENRADIUS 3
-int oldcolor, currentcolor;
-
-
-void setup() {
- Serial.begin(115200);
-
- //while (!Serial) delay(10);
-
- Serial.println("HX8357D Featherwing full control test!");
-
- if (!ts.begin()) {
- Serial.println("Couldn't start touchscreen controller");
- while (1);
- }
- Serial.println("Touchscreen started");
-
- // Uncomment these lines to turn off the backlite via STMPE!
- //ts.writeRegister8(STMPE_GPIO_DIR, 1<<2);
- //ts.writeRegister8(STMPE_GPIO_ALT_FUNCT, 1<<2);
- //ts.writeRegister8(STMPE_GPIO_CLR_PIN, 1<<2);
-
- tft.begin();
- tft.fillScreen(HX8357_BLACK);
-
- Serial.print("Initializing SD card...");
- if (!SD.begin(SD_CS)) {
- Serial.println("failed!");
- }
- Serial.println("OK!");
-
- bmpDraw("/adabot.bmp", 0, 0);
-
- // select the current color 'red'
- currentcolor = HX8357_RED;
-
- // turn backlite on via STMPE
- //ts.writeRegister8(STMPE_GPIO_SET_PIN, 1<<2);
-}
-
-
-void loop(void) {
- // Retrieve a point
- TS_Point p = ts.getPoint();
-
- //Serial.print("X = "); Serial.print(p.x); Serial.print("\tY = "); Serial.print(p.y); Serial.print("\tPressure = "); Serial.println(p.z);
-
- // Scale from ~0->4000 to tft.width using the calibration #'s
- p.x = map(p.x, TS_MINX, TS_MAXX, tft.width(), 0);
- p.y = map(p.y, TS_MINY, TS_MAXY, 0, tft.height());
-
- if (((p.y-PENRADIUS) > 0) && ((p.y+PENRADIUS) < tft.height())) {
- tft.fillCircle(p.x, p.y, PENRADIUS, currentcolor);
- }
-}
-
-
-
-// This function opens a Windows Bitmap (BMP) file and
-// displays it at the given coordinates. It's sped up
-// by reading many pixels worth of data at a time
-// (rather than pixel by pixel). Increasing the buffer
-// size takes more of the Arduino's precious RAM but
-// makes loading a little faster. 20 pixels seems a
-// good balance.
-
-#define BUFFPIXEL 20
-
-void bmpDraw(char *filename, uint8_t x, uint16_t y) {
-
- File bmpFile;
- int bmpWidth, bmpHeight; // W+H in pixels
- uint8_t bmpDepth; // Bit depth (currently must be 24)
- uint32_t bmpImageoffset; // Start of image data in file
- uint32_t rowSize; // Not always = bmpWidth; may have padding
- uint8_t sdbuffer[3*BUFFPIXEL]; // pixel buffer (R+G+B per pixel)
- uint8_t buffidx = sizeof(sdbuffer); // Current position in sdbuffer
- boolean goodBmp = false; // Set to true on valid header parse
- boolean flip = true; // BMP is stored bottom-to-top
- int w, h, row, col;
- uint8_t r, g, b;
- uint32_t pos = 0, startTime = millis();
-
- if((x >= tft.width()) || (y >= tft.height())) return;
-
- Serial.println();
- Serial.print(F("Loading image '"));
- Serial.print(filename);
- Serial.println('\'');
-
- // Open requested file on SD card
- if ((bmpFile = SD.open(filename)) == NULL) {
- Serial.print(F("File not found"));
- return;
- }
-
- // Parse BMP header
- if(read16(bmpFile) == 0x4D42) { // BMP signature
- Serial.print(F("File size: ")); Serial.println(read32(bmpFile));
- (void)read32(bmpFile); // Read & ignore creator bytes
- bmpImageoffset = read32(bmpFile); // Start of image data
- Serial.print(F("Image Offset: ")); Serial.println(bmpImageoffset, DEC);
- // Read DIB header
- Serial.print(F("Header size: ")); Serial.println(read32(bmpFile));
- bmpWidth = read32(bmpFile);
- bmpHeight = read32(bmpFile);
- if(read16(bmpFile) == 1) { // # planes -- must be '1'
- bmpDepth = read16(bmpFile); // bits per pixel
- Serial.print(F("Bit Depth: ")); Serial.println(bmpDepth);
- if((bmpDepth == 24) && (read32(bmpFile) == 0)) { // 0 = uncompressed
-
- goodBmp = true; // Supported BMP format -- proceed!
- Serial.print(F("Image size: "));
- Serial.print(bmpWidth);
- Serial.print('x');
- Serial.println(bmpHeight);
-
- // BMP rows are padded (if needed) to 4-byte boundary
- rowSize = (bmpWidth * 3 + 3) & ~3;
-
- // If bmpHeight is negative, image is in top-down order.
- // This is not canon but has been observed in the wild.
- if(bmpHeight < 0) {
- bmpHeight = -bmpHeight;
- flip = false;
- }
-
- // Crop area to be loaded
- w = bmpWidth;
- h = bmpHeight;
- if((x+w-1) >= tft.width()) w = tft.width() - x;
- if((y+h-1) >= tft.height()) h = tft.height() - y;
-
- // Set TFT address window to clipped image bounds
- tft.startWrite(); // Start TFT transaction
- tft.setAddrWindow(x, y, w, h);
-
- for (row=0; row= sizeof(sdbuffer)) { // Indeed
- tft.endWrite(); // End TFT transaction
- bmpFile.read(sdbuffer, sizeof(sdbuffer));
- buffidx = 0; // Set index to beginning
- tft.startWrite(); // Start new TFT transaction
- }
-
- // Convert pixel from BMP to TFT format, push to display
- b = sdbuffer[buffidx++];
- g = sdbuffer[buffidx++];
- r = sdbuffer[buffidx++];
- tft.pushColor(tft.color565(r,g,b));
- } // end pixel
- } // end scanline
- tft.endWrite(); // End last TFT transaction
- Serial.print(F("Loaded in "));
- Serial.print(millis() - startTime);
- Serial.println(" ms");
- } // end goodBmp
- }
- }
-
- bmpFile.close();
- if(!goodBmp) Serial.println(F("BMP format not recognized."));
-}
-
-// These read 16- and 32-bit types from the SD card file.
-// BMP data is stored little-endian, Arduino is little-endian too.
-// May need to reverse subscript order if porting elsewhere.
-
-uint16_t read16(File &f) {
- uint16_t result;
- ((uint8_t *)&result)[0] = f.read(); // LSB
- ((uint8_t *)&result)[1] = f.read(); // MSB
- return result;
-}
-
-uint32_t read32(File &f) {
- uint32_t result;
- ((uint8_t *)&result)[0] = f.read(); // LSB
- ((uint8_t *)&result)[1] = f.read();
- ((uint8_t *)&result)[2] = f.read();
- ((uint8_t *)&result)[3] = f.read(); // MSB
- return result;
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/breakouttouchpaint/.esp8266.test.skip b/KugleFirmware/Libraries/Devices/LCD/examples/breakouttouchpaint/.esp8266.test.skip
deleted file mode 100644
index e69de29..0000000
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/breakouttouchpaint/breakouttouchpaint.ino b/KugleFirmware/Libraries/Devices/LCD/examples/breakouttouchpaint/breakouttouchpaint.ino
deleted file mode 100644
index 5001c27..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/breakouttouchpaint/breakouttouchpaint.ino
+++ /dev/null
@@ -1,157 +0,0 @@
-/***************************************************
- This is our touchscreen painting example for the Adafruit HX8357 Breakout
- ----> http://www.adafruit.com/products/2050
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-/** NOT FOR USE WITH THE TOUCH SHIELD, ONLY FOR THE 3.5" BREAKOUT! **/
-
-#include // Core graphics library
-#include
-#include "Adafruit_HX8357.h"
-#include "TouchScreen.h"
-
-// These are the four touchscreen analog pins
-#define YP A2 // must be an analog pin, use "An" notation!
-#define XM A3 // must be an analog pin, use "An" notation!
-#define YM 7 // can be a digital pin
-#define XP 8 // can be a digital pin
-
-// This is calibration data for the raw touch data to the screen coordinates
-#define TS_MINX 110
-#define TS_MINY 80
-#define TS_MAXX 900
-#define TS_MAXY 940
-
-#define MINPRESSURE 10
-#define MAXPRESSURE 1000
-
-// The display uses hardware SPI, plus #9 & #10
-#define TFT_RST -1 // dont use a reset pin, tie to arduino RST if you like
-#define TFT_DC 9
-#define TFT_CS 10
-
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, TFT_RST);
-
-// For better pressure precision, we need to know the resistance
-// between X+ and X- Use any multimeter to read it
-// For the one we're using, its 300 ohms across the X plate
-TouchScreen ts = TouchScreen(XP, YP, XM, YM, 300);
-
-// Size of the color selection boxes and the paintbrush size
-#define BOXSIZE 40
-#define PENRADIUS 3
-int oldcolor, currentcolor;
-
-void setup(void) {
- while (!Serial); // used for leonardo debugging
-
- Serial.begin(115200);
- Serial.println(F("Touch Paint!"));
-
- tft.begin();
- tft.fillScreen(HX8357_BLACK);
-
- // make the color selection boxes
- tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);
- tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);
- tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);
- tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);
- tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
-
- // select the current color 'red'
- tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- currentcolor = HX8357_RED;
-}
-
-
-void loop()
-{
- // Retrieve a point
- TSPoint p = ts.getPoint();
-
- // we have some minimum pressure we consider 'valid'
- // pressure of 0 means no pressing!
- if (p.z < MINPRESSURE || p.z > MAXPRESSURE) {
- return;
- }
-
- Serial.print("X = "); Serial.print(p.x);
- Serial.print("\tY = "); Serial.print(p.y);
- Serial.print("\tPressure = "); Serial.println(p.z);
-
- // Scale from ~0->1000 to tft.width using the calibration #'s
- p.x = map(p.x, TS_MINX, TS_MAXX, 0, tft.width());
- p.y = map(p.y, TS_MINY, TS_MAXY, 0, tft.height());
-
-
- /*
- Serial.print("("); Serial.print(p.x);
- Serial.print(", "); Serial.print(p.y);
- Serial.println(")");
-*/
-
- if (p.y < BOXSIZE) {
- oldcolor = currentcolor;
-
- if (p.x < BOXSIZE) {
- currentcolor = HX8357_RED;
- tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*2) {
- currentcolor = HX8357_YELLOW;
- tft.drawRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*3) {
- currentcolor = HX8357_GREEN;
- tft.drawRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*4) {
- currentcolor = HX8357_CYAN;
- tft.drawRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*5) {
- currentcolor = HX8357_BLUE;
- tft.drawRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*6) {
- currentcolor = HX8357_MAGENTA;
- tft.drawRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*7) {
- currentcolor = HX8357_WHITE;
- tft.drawRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- } else if (p.x < BOXSIZE*8) {
- currentcolor = HX8357_BLACK;
- tft.drawRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- }
-
- if (oldcolor != currentcolor) {
- if (oldcolor == HX8357_RED)
- tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- if (oldcolor == HX8357_YELLOW)
- tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);
- if (oldcolor == HX8357_GREEN)
- tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);
- if (oldcolor == HX8357_CYAN)
- tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);
- if (oldcolor == HX8357_BLUE)
- tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);
- if (oldcolor == HX8357_MAGENTA)
- tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);
- if (oldcolor == HX8357_WHITE)
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- if (oldcolor == HX8357_BLACK)
- tft.fillRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);
- }
- }
- if (((p.y-PENRADIUS) > BOXSIZE) && ((p.y+PENRADIUS) < tft.height())) {
- tft.fillCircle(p.x, p.y, PENRADIUS, currentcolor);
- }
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest/graphicstest.ino b/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest/graphicstest.ino
deleted file mode 100644
index a9394cf..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest/graphicstest.ino
+++ /dev/null
@@ -1,324 +0,0 @@
-/***************************************************
- This is our library for the Adafruit HX8357D Breakout
- ----> http://www.adafruit.com/products/2050
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-#include
-#include "Adafruit_GFX.h"
-#include "Adafruit_HX8357.h"
-
-// These are 'flexible' lines that can be changed
-#define TFT_CS 10
-#define TFT_DC 9
-#define TFT_RST 8 // RST can be set to -1 if you tie it to Arduino's reset
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, TFT_RST);
-
-// SoftSPI - note that on some processors this might be *faster* than hardware SPI!
-//Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, MOSI, SCK, TFT_RST, MISO);
-
-
-
-void setup() {
- Serial.begin(9600);
- Serial.println("HX8357D Test!");
-
- tft.begin();
-
- // read diagnostics (optional but can help debug problems)
- uint8_t x = tft.readcommand8(HX8357_RDPOWMODE);
- Serial.print("Display Power Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDMADCTL);
- Serial.print("MADCTL Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDCOLMOD);
- Serial.print("Pixel Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDDIM);
- Serial.print("Image Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDDSDR);
- Serial.print("Self Diagnostic: 0x"); Serial.println(x, HEX);
-
- Serial.println(F("Benchmark Time (microseconds)"));
-
- tft.setRotation(1);
-
- Serial.print(F("Text "));
- Serial.println(testText());
- delay(500);
-
- Serial.print(F("Lines "));
- Serial.println(testLines(HX8357_CYAN));
- delay(500);
-
- Serial.print(F("Rectangles (outline) "));
- Serial.println(testRects(HX8357_GREEN));
- delay(500);
-
- tft.fillScreen(HX8357_BLACK);
- Serial.print(F("Circles (outline) "));
- Serial.println(testCircles(10, HX8357_RED));
- delay(500);
-
-
- Serial.print(F("Triangles (outline) "));
- Serial.println(testTriangles());
- delay(500);
-
- Serial.print(F("Triangles (filled) "));
- Serial.println(testFilledTriangles());
- delay(500);
-
-
- Serial.print(F("Rounded rects (outline) "));
- Serial.println(testRoundRects());
- delay(500);
-
- Serial.print(F("Rounded rects (filled) "));
- Serial.println(testFilledRoundRects());
- delay(500);
-
- Serial.println(F("Done!"));
-}
-
-
-void loop(void) {
- for(uint8_t rotation=0; rotation<4; rotation++) {
- tft.setRotation(rotation);
- testText();
- delay(1000);
- }
-}
-
-unsigned long testFillScreen() {
- unsigned long start = micros();
- tft.fillScreen(HX8357_RED);
- tft.fillScreen(HX8357_GREEN);
- tft.fillScreen(HX8357_BLUE);
- tft.fillScreen(HX8357_WHITE);
- return micros() - start;
-}
-
-
-unsigned long testText() {
- tft.fillScreen(HX8357_BLACK);
- unsigned long start = micros();
- tft.setCursor(0, 0);
- tft.setTextColor(HX8357_WHITE); tft.setTextSize(1);
- tft.println("Hello World!");
- tft.setTextColor(HX8357_YELLOW); tft.setTextSize(2);
- tft.println(1234.56);
- tft.setTextColor(HX8357_RED); tft.setTextSize(3);
- tft.println(0xDEADBEEF, HEX);
- tft.println();
- tft.setTextColor(HX8357_GREEN);
- tft.setTextSize(5);
- tft.println("Groop");
- tft.setTextSize(2);
- tft.println("I implore thee,");
- tft.setTextSize(1);
- tft.println("my foonting turlingdromes.");
- tft.println("And hooptiously drangle me");
- tft.println("with crinkly bindlewurdles,");
- tft.println("Or I will rend thee");
- tft.println("in the gobberwarts");
- tft.println("with my blurglecruncheon,");
- tft.println("see if I don't!");
-
- tft.setTextColor(HX8357_WHITE);
- tft.println(F("Alice was beginning to get very tired of sitting by her sister on the bank, and of having nothing to do: once or twice she had peeped into the book her sister was reading, but it had no pictures or conversations in it, 'and what is the use of a book,' thought Alice 'without pictures or conversations?'"));
-
-tft.println(F("So she was considering in her own mind (as well as she could, for the hot day made her feel very sleepy and stupid), whether the pleasure of making a daisy-chain would be worth the trouble of getting up and picking the daisies, when suddenly a White Rabbit with pink eyes ran close by her."));
-
-tft.println(F("There was nothing so very remarkable in that; nor did Alice think it so very much out of the way to hear the Rabbit say to itself, 'Oh dear! Oh dear! I shall be late!' (when she thought it over afterwards, it occurred to her that she ought to have wondered at this, but at the time it all seemed quite natural); but when the Rabbit actually took a watch out of its waistcoat-pocket, and looked at it, and then hurried on, Alice started to her feet, for it flashed across her mind that she had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it, and fortunately was just in time to see it pop down a large rabbit-hole under the hedge."));
-
-tft.println(F("In another moment down went Alice after it, never once considering how in the world she was to get out again."));
-
-tft.println(F("The rabbit-hole went straight on like a tunnel for some way, and then dipped suddenly down, so suddenly that Alice had not a moment to think about stopping herself before she found herself falling down a very deep well."));
-
-tft.println(F("Either the well was very deep, or she fell very slowly, for she had plenty of time as she went down to look about her and to wonder what was going to happen next. First, she tried to look down and make out what she was coming to, but it was too dark to see anything; then she looked at the sides of the well, and noticed that they were filled with cupboards and book-shelves; here and there she saw maps and pictures hung upon pegs. She took down a jar from one of the shelves as she passed; it was labelled 'ORANGE MARMALADE', but to her great disappointment it was empty: she did not like to drop the jar for fear of killing somebody, so managed to put it into one of the cupboards as she fell past it."));
-
- return micros() - start;
-}
-
-unsigned long testLines(uint16_t color) {
- unsigned long start, t;
- int x1, y1, x2, y2,
- w = tft.width(),
- h = tft.height();
-
- tft.fillScreen(HX8357_BLACK);
-
- x1 = y1 = 0;
- y2 = h - 1;
- start = micros();
- for(x2=0; x20; i-=6) {
- i2 = i / 2;
- start = micros();
- tft.fillRect(cx-i2, cy-i2, i, i, color1);
- t += micros() - start;
- // Outlines are not included in timing results
- tft.drawRect(cx-i2, cy-i2, i, i, color2);
- }
-
- return t;
-}
-
-unsigned long testFilledCircles(uint8_t radius, uint16_t color) {
- unsigned long start;
- int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;
-
- tft.fillScreen(HX8357_BLACK);
- start = micros();
- for(x=radius; x10; i-=5) {
- start = micros();
- tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(0, i, i));
- t += micros() - start;
- tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(i, i, 0));
- }
-
- return t;
-}
-
-unsigned long testRoundRects() {
- unsigned long start;
- int w, i, i2,
- cx = tft.width() / 2 ,
- cy = tft.height() / 2 ;
-
- tft.fillScreen(HX8357_BLACK);
- w = min(tft.width(), tft.height());
- start = micros();
- for(i=0; i25; i-=6) {
- i2 = i / 2;
- tft.fillRoundRect(cx-i2, cy-i2, i-20, i-20, i/8, tft.color565(100, i/2, 100));
- }
-
- return micros() - start;
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest_featherwing/.mega2560.test.skip b/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest_featherwing/.mega2560.test.skip
deleted file mode 100644
index e69de29..0000000
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest_featherwing/graphicstest_featherwing.ino b/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest_featherwing/graphicstest_featherwing.ino
deleted file mode 100644
index 365d66d..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/graphicstest_featherwing/graphicstest_featherwing.ino
+++ /dev/null
@@ -1,362 +0,0 @@
-/***************************************************
- This is our library for the Adafruit 3.5" TFT (HX8357) FeatherWing
- ----> http://www.adafruit.com/products/3651
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-#include
-#include "Adafruit_GFX.h"
-#include "Adafruit_HX8357.h"
-
-#ifdef ESP8266
- #define STMPE_CS 16
- #define TFT_CS 0
- #define TFT_DC 15
- #define SD_CS 2
-#endif
-#ifdef ESP32
- #define STMPE_CS 32
- #define TFT_CS 15
- #define TFT_DC 33
- #define SD_CS 14
-#endif
-#ifdef TEENSYDUINO
- #define TFT_DC 10
- #define TFT_CS 4
- #define STMPE_CS 3
- #define SD_CS 8
-#endif
-#ifdef ARDUINO_STM32_FEATHER
- #define TFT_DC PB4
- #define TFT_CS PA15
- #define STMPE_CS PC7
- #define SD_CS PC5
-#endif
-#ifdef ARDUINO_FEATHER52
- #define STMPE_CS 30
- #define TFT_CS 13
- #define TFT_DC 11
- #define SD_CS 27
-#endif
-#if defined(ARDUINO_MAX32620FTHR) || defined(ARDUINO_MAX32630FTHR)
- #define TFT_DC P5_4
- #define TFT_CS P5_3
- #define STMPE_CS P3_3
- #define SD_CS P3_2
-#endif
-
-// Anything else!
-#if defined (__AVR_ATmega32U4__) || defined(ARDUINO_SAMD_FEATHER_M0) || defined (__AVR_ATmega328P__) || defined(ARDUINO_SAMD_ZERO) || defined(__SAMD51__) || defined(__SAM3X8E__)
- #define STMPE_CS 6
- #define TFT_CS 9
- #define TFT_DC 10
- #define SD_CS 5
-#endif
-
-#define TFT_RST -1
-
-// Use hardware SPI and the above for CS/DC
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, TFT_RST);
-
-
-void setup() {
- Serial.begin(115200);
- Serial.println("HX8357D Test!");
-
- tft.begin();
-
- // read diagnostics (optional but can help debug problems)
- uint8_t x = tft.readcommand8(HX8357_RDPOWMODE);
- Serial.print("Display Power Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDMADCTL);
- Serial.print("MADCTL Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDCOLMOD);
- Serial.print("Pixel Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDDIM);
- Serial.print("Image Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(HX8357_RDDSDR);
- Serial.print("Self Diagnostic: 0x"); Serial.println(x, HEX);
-
- Serial.println(F("Benchmark Time (microseconds)"));
-
- tft.setRotation(1);
-
- Serial.print(F("Text "));
- Serial.println(testText());
- delay(500);
-
- Serial.print(F("Lines "));
- Serial.println(testLines(HX8357_CYAN));
- delay(500);
-
- Serial.print(F("Rectangles (outline) "));
- Serial.println(testRects(HX8357_GREEN));
- delay(500);
-
- tft.fillScreen(HX8357_BLACK);
- Serial.print(F("Circles (outline) "));
- Serial.println(testCircles(10, HX8357_RED));
- delay(500);
-
-
- Serial.print(F("Triangles (outline) "));
- Serial.println(testTriangles());
- delay(500);
-
- Serial.print(F("Triangles (filled) "));
- Serial.println(testFilledTriangles());
- delay(500);
-
-
- Serial.print(F("Rounded rects (outline) "));
- Serial.println(testRoundRects());
- delay(500);
-
- Serial.print(F("Rounded rects (filled) "));
- Serial.println(testFilledRoundRects());
- delay(500);
-
- Serial.println(F("Done!"));
-}
-
-
-void loop(void) {
- for(uint8_t rotation=0; rotation<4; rotation++) {
- tft.setRotation(rotation);
- testText();
- delay(1000);
- }
-}
-
-unsigned long testFillScreen() {
- unsigned long start = micros();
- tft.fillScreen(HX8357_RED);
- tft.fillScreen(HX8357_GREEN);
- tft.fillScreen(HX8357_BLUE);
- tft.fillScreen(HX8357_WHITE);
- return micros() - start;
-}
-
-
-unsigned long testText() {
- tft.fillScreen(HX8357_BLACK);
- unsigned long start = micros();
- tft.setCursor(0, 0);
- tft.setTextColor(HX8357_WHITE); tft.setTextSize(1);
- tft.println("Hello World!");
- tft.setTextColor(HX8357_YELLOW); tft.setTextSize(2);
- tft.println(1234.56);
- tft.setTextColor(HX8357_RED); tft.setTextSize(3);
- tft.println(0xDEADBEEF, HEX);
- tft.println();
- tft.setTextColor(HX8357_GREEN);
- tft.setTextSize(5);
- tft.println("Groop");
- tft.setTextSize(2);
- tft.println("I implore thee,");
- tft.setTextSize(1);
- tft.println("my foonting turlingdromes.");
- tft.println("And hooptiously drangle me");
- tft.println("with crinkly bindlewurdles,");
- tft.println("Or I will rend thee");
- tft.println("in the gobberwarts");
- tft.println("with my blurglecruncheon,");
- tft.println("see if I don't!");
-
- tft.setTextColor(HX8357_WHITE);
- tft.println(F("Alice was beginning to get very tired of sitting by her sister on the bank, and of having nothing to do: once or twice she had peeped into the book her sister was reading, but it had no pictures or conversations in it, 'and what is the use of a book,' thought Alice 'without pictures or conversations?'"));
-
-tft.println(F("So she was considering in her own mind (as well as she could, for the hot day made her feel very sleepy and stupid), whether the pleasure of making a daisy-chain would be worth the trouble of getting up and picking the daisies, when suddenly a White Rabbit with pink eyes ran close by her."));
-
-tft.println(F("There was nothing so very remarkable in that; nor did Alice think it so very much out of the way to hear the Rabbit say to itself, 'Oh dear! Oh dear! I shall be late!' (when she thought it over afterwards, it occurred to her that she ought to have wondered at this, but at the time it all seemed quite natural); but when the Rabbit actually took a watch out of its waistcoat-pocket, and looked at it, and then hurried on, Alice started to her feet, for it flashed across her mind that she had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it, and fortunately was just in time to see it pop down a large rabbit-hole under the hedge."));
-
-tft.println(F("In another moment down went Alice after it, never once considering how in the world she was to get out again."));
-
-tft.println(F("The rabbit-hole went straight on like a tunnel for some way, and then dipped suddenly down, so suddenly that Alice had not a moment to think about stopping herself before she found herself falling down a very deep well."));
-
-tft.println(F("Either the well was very deep, or she fell very slowly, for she had plenty of time as she went down to look about her and to wonder what was going to happen next. First, she tried to look down and make out what she was coming to, but it was too dark to see anything; then she looked at the sides of the well, and noticed that they were filled with cupboards and book-shelves; here and there she saw maps and pictures hung upon pegs. She took down a jar from one of the shelves as she passed; it was labelled 'ORANGE MARMALADE', but to her great disappointment it was empty: she did not like to drop the jar for fear of killing somebody, so managed to put it into one of the cupboards as she fell past it."));
-
- return micros() - start;
-}
-
-unsigned long testLines(uint16_t color) {
- unsigned long start, t;
- int x1, y1, x2, y2,
- w = tft.width(),
- h = tft.height();
-
- tft.fillScreen(HX8357_BLACK);
-
- x1 = y1 = 0;
- y2 = h - 1;
- start = micros();
- for(x2=0; x20; i-=6) {
- i2 = i / 2;
- start = micros();
- tft.fillRect(cx-i2, cy-i2, i, i, color1);
- t += micros() - start;
- // Outlines are not included in timing results
- tft.drawRect(cx-i2, cy-i2, i, i, color2);
- }
-
- return t;
-}
-
-unsigned long testFilledCircles(uint8_t radius, uint16_t color) {
- unsigned long start;
- int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;
-
- tft.fillScreen(HX8357_BLACK);
- start = micros();
- for(x=radius; x10; i-=5) {
- start = micros();
- tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(0, i, i));
- t += micros() - start;
- tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(i, i, 0));
- }
-
- return t;
-}
-
-unsigned long testRoundRects() {
- unsigned long start;
- int w, i, i2,
- cx = tft.width() / 2 ,
- cy = tft.height() / 2 ;
-
- tft.fillScreen(HX8357_BLACK);
- w = min(tft.width(), tft.height());
- start = micros();
- for(i=0; i25; i-=6) {
- i2 = i / 2;
- tft.fillRoundRect(cx-i2, cy-i2, i-20, i-20, i/8, tft.color565(100, i/2, 100));
- }
-
- return micros() - start;
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/mock_ili9341/mock_ili9341.ino b/KugleFirmware/Libraries/Devices/LCD/examples/mock_ili9341/mock_ili9341.ino
deleted file mode 100644
index 3154d40..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/mock_ili9341/mock_ili9341.ino
+++ /dev/null
@@ -1,365 +0,0 @@
-/***************************************************
- This is our GFX example for the Adafruit ILI9341 Breakout and Shield
- ----> http://www.adafruit.com/products/1651
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-
-#include "SPI.h"
-#include "Adafruit_GFX.h"
-#include "Adafruit_ILI9341.h"
-
-// For the Adafruit shield, these are the default.
-#define TFT_DC 9
-#define TFT_CS 10
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-Adafruit_ILI9341 tft = Adafruit_ILI9341(TFT_CS, TFT_DC);
-// If using the breakout, change pins as desired
-//Adafruit_ILI9341 tft = Adafruit_ILI9341(TFT_CS, TFT_DC, TFT_MOSI, TFT_CLK, TFT_RST, TFT_MISO);
-
-void setup() {
- Serial.begin(9600);
- Serial.println("ILI9341 Test!");
-
- tft.begin();
-
- // read diagnostics (optional but can help debug problems)
- uint8_t x = tft.readcommand8(ILI9341_RDMODE);
- Serial.print("Display Power Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(ILI9341_RDMADCTL);
- Serial.print("MADCTL Mode: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(ILI9341_RDPIXFMT);
- Serial.print("Pixel Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(ILI9341_RDIMGFMT);
- Serial.print("Image Format: 0x"); Serial.println(x, HEX);
- x = tft.readcommand8(ILI9341_RDSELFDIAG);
- Serial.print("Self Diagnostic: 0x"); Serial.println(x, HEX);
-
- Serial.println(F("Benchmark Time (microseconds)"));
- delay(10);
- Serial.print(F("Screen fill "));
- Serial.println(testFillScreen());
- delay(500);
-
- Serial.print(F("Text "));
- Serial.println(testText());
- delay(3000);
-
- Serial.print(F("Lines "));
- Serial.println(testLines(ILI9341_CYAN));
- delay(500);
-
- Serial.print(F("Horiz/Vert Lines "));
- Serial.println(testFastLines(ILI9341_RED, ILI9341_BLUE));
- delay(500);
-
- Serial.print(F("Rectangles (outline) "));
- Serial.println(testRects(ILI9341_GREEN));
- delay(500);
-
- Serial.print(F("Rectangles (filled) "));
- Serial.println(testFilledRects(ILI9341_YELLOW, ILI9341_MAGENTA));
- delay(500);
-
- Serial.print(F("Circles (filled) "));
- Serial.println(testFilledCircles(10, ILI9341_MAGENTA));
-
- Serial.print(F("Circles (outline) "));
- Serial.println(testCircles(10, ILI9341_WHITE));
- delay(500);
-
- Serial.print(F("Triangles (outline) "));
- Serial.println(testTriangles());
- delay(500);
-
- Serial.print(F("Triangles (filled) "));
- Serial.println(testFilledTriangles());
- delay(500);
-
- Serial.print(F("Rounded rects (outline) "));
- Serial.println(testRoundRects());
- delay(500);
-
- Serial.print(F("Rounded rects (filled) "));
- Serial.println(testFilledRoundRects());
- delay(500);
-
- Serial.println(F("Done!"));
-
-}
-
-
-void loop(void) {
- for(uint8_t rotation=0; rotation<4; rotation++) {
- tft.setRotation(rotation);
- testText();
- delay(1000);
- }
-}
-
-unsigned long testFillScreen() {
- unsigned long start = micros();
- tft.fillScreen(ILI9341_BLACK);
- yield();
- tft.fillScreen(ILI9341_RED);
- yield();
- tft.fillScreen(ILI9341_GREEN);
- yield();
- tft.fillScreen(ILI9341_BLUE);
- yield();
- tft.fillScreen(ILI9341_BLACK);
- yield();
- return micros() - start;
-}
-
-unsigned long testText() {
- tft.fillScreen(ILI9341_BLACK);
- unsigned long start = micros();
- tft.setCursor(0, 0);
- tft.setTextColor(ILI9341_WHITE); tft.setTextSize(1);
- tft.println("Hello World!");
- tft.setTextColor(ILI9341_YELLOW); tft.setTextSize(2);
- tft.println(1234.56);
- tft.setTextColor(ILI9341_RED); tft.setTextSize(3);
- tft.println(0xDEADBEEF, HEX);
- tft.println();
- tft.setTextColor(ILI9341_GREEN);
- tft.setTextSize(5);
- tft.println("Groop");
- tft.setTextSize(2);
- tft.println("I implore thee,");
- tft.setTextSize(1);
- tft.println("my foonting turlingdromes.");
- tft.println("And hooptiously drangle me");
- tft.println("with crinkly bindlewurdles,");
- tft.println("Or I will rend thee");
- tft.println("in the gobberwarts");
- tft.println("with my blurglecruncheon,");
- tft.println("see if I don't!");
- return micros() - start;
-}
-
-unsigned long testLines(uint16_t color) {
- unsigned long start, t;
- int x1, y1, x2, y2,
- w = tft.width(),
- h = tft.height();
-
- tft.fillScreen(ILI9341_BLACK);
- yield();
-
- x1 = y1 = 0;
- y2 = h - 1;
- start = micros();
- for(x2=0; x20; i-=6) {
- i2 = i / 2;
- start = micros();
- tft.fillRect(cx-i2, cy-i2, i, i, color1);
- t += micros() - start;
- // Outlines are not included in timing results
- tft.drawRect(cx-i2, cy-i2, i, i, color2);
- yield();
- }
-
- return t;
-}
-
-unsigned long testFilledCircles(uint8_t radius, uint16_t color) {
- unsigned long start;
- int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;
-
- tft.fillScreen(ILI9341_BLACK);
- start = micros();
- for(x=radius; x10; i-=5) {
- start = micros();
- tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(0, i*10, i*10));
- t += micros() - start;
- tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
- tft.color565(i*10, i*10, 0));
- yield();
- }
-
- return t;
-}
-
-unsigned long testRoundRects() {
- unsigned long start;
- int w, i, i2,
- cx = tft.width() / 2 - 1,
- cy = tft.height() / 2 - 1;
-
- tft.fillScreen(ILI9341_BLACK);
- w = min(tft.width(), tft.height());
- start = micros();
- for(i=0; i20; i-=6) {
- i2 = i / 2;
- tft.fillRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(0, i, 0));
- yield();
- }
-
- return micros() - start;
-}
\ No newline at end of file
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/spitftbitmap/spitftbitmap.ino b/KugleFirmware/Libraries/Devices/LCD/examples/spitftbitmap/spitftbitmap.ino
deleted file mode 100644
index 61967c1..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/spitftbitmap/spitftbitmap.ino
+++ /dev/null
@@ -1,196 +0,0 @@
-/***************************************************
- This is our Bitmap drawing example for the Adafruit HX8357 Breakout
- ----> http://www.adafruit.com/products/2050
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-
-#include // Core graphics library
-#include "Adafruit_HX8357.h"
-#include
-#include
-
-// TFT display and SD card will share the hardware SPI interface.
-// Hardware SPI pins are specific to the Arduino board type and
-// cannot be remapped to alternate pins. For Arduino Uno,
-// Duemilanove, etc., pin 11 = MOSI, pin 12 = MISO, pin 13 = SCK.
-
-#define TFT_DC 9
-#define TFT_CS 10
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC);
-
-#define SD_CS 4
-
-void setup(void) {
- Serial.begin(9600);
-
- tft.begin();
- tft.fillScreen(HX8357_BLUE);
-
- Serial.print("Initializing SD card...");
- if (!SD.begin(SD_CS)) {
- Serial.println("failed!");
- }
- Serial.println("OK!");
-
- bmpDraw("jumpers.bmp", 0, 0);
-}
-
-void loop() {
-}
-
-// This function opens a Windows Bitmap (BMP) file and
-// displays it at the given coordinates. It's sped up
-// by reading many pixels worth of data at a time
-// (rather than pixel by pixel). Increasing the buffer
-// size takes more of the Arduino's precious RAM but
-// makes loading a little faster. 20 pixels seems a
-// good balance.
-
-#define BUFFPIXEL 20
-
-void bmpDraw(char *filename, uint8_t x, uint16_t y) {
-
- File bmpFile;
- int bmpWidth, bmpHeight; // W+H in pixels
- uint8_t bmpDepth; // Bit depth (currently must be 24)
- uint32_t bmpImageoffset; // Start of image data in file
- uint32_t rowSize; // Not always = bmpWidth; may have padding
- uint8_t sdbuffer[3*BUFFPIXEL]; // pixel buffer (R+G+B per pixel)
- uint8_t buffidx = sizeof(sdbuffer); // Current position in sdbuffer
- boolean goodBmp = false; // Set to true on valid header parse
- boolean flip = true; // BMP is stored bottom-to-top
- int w, h, row, col;
- uint8_t r, g, b;
- uint32_t pos = 0, startTime = millis();
-
- if((x >= tft.width()) || (y >= tft.height())) return;
-
- Serial.println();
- Serial.print(F("Loading image '"));
- Serial.print(filename);
- Serial.println('\'');
-
- // Open requested file on SD card
- if ((bmpFile = SD.open(filename)) == NULL) {
- Serial.print(F("File not found"));
- return;
- }
-
- // Parse BMP header
- if(read16(bmpFile) == 0x4D42) { // BMP signature
- Serial.print(F("File size: ")); Serial.println(read32(bmpFile));
- (void)read32(bmpFile); // Read & ignore creator bytes
- bmpImageoffset = read32(bmpFile); // Start of image data
- Serial.print(F("Image Offset: ")); Serial.println(bmpImageoffset, DEC);
- // Read DIB header
- Serial.print(F("Header size: ")); Serial.println(read32(bmpFile));
- bmpWidth = read32(bmpFile);
- bmpHeight = read32(bmpFile);
- if(read16(bmpFile) == 1) { // # planes -- must be '1'
- bmpDepth = read16(bmpFile); // bits per pixel
- Serial.print(F("Bit Depth: ")); Serial.println(bmpDepth);
- if((bmpDepth == 24) && (read32(bmpFile) == 0)) { // 0 = uncompressed
-
- goodBmp = true; // Supported BMP format -- proceed!
- Serial.print(F("Image size: "));
- Serial.print(bmpWidth);
- Serial.print('x');
- Serial.println(bmpHeight);
-
- // BMP rows are padded (if needed) to 4-byte boundary
- rowSize = (bmpWidth * 3 + 3) & ~3;
-
- // If bmpHeight is negative, image is in top-down order.
- // This is not canon but has been observed in the wild.
- if(bmpHeight < 0) {
- bmpHeight = -bmpHeight;
- flip = false;
- }
-
- // Crop area to be loaded
- w = bmpWidth;
- h = bmpHeight;
- if((x+w-1) >= tft.width()) w = tft.width() - x;
- if((y+h-1) >= tft.height()) h = tft.height() - y;
-
- // Set TFT address window to clipped image bounds
- tft.startWrite(); // Start TFT transaction
- tft.setAddrWindow(x, y, w, h);
-
- for (row=0; row= sizeof(sdbuffer)) { // Indeed
- tft.endWrite(); // End TFT transaction
- bmpFile.read(sdbuffer, sizeof(sdbuffer));
- buffidx = 0; // Set index to beginning
- tft.startWrite(); // Start new TFT transaction
- }
-
- // Convert pixel from BMP to TFT format, push to display
- b = sdbuffer[buffidx++];
- g = sdbuffer[buffidx++];
- r = sdbuffer[buffidx++];
- tft.pushColor(tft.color565(r,g,b));
- } // end pixel
- } // end scanline
- tft.endWrite(); // End last TFT transaction
- Serial.print(F("Loaded in "));
- Serial.print(millis() - startTime);
- Serial.println(" ms");
- } // end goodBmp
- }
- }
-
- bmpFile.close();
- if(!goodBmp) Serial.println(F("BMP format not recognized."));
-}
-
-// These read 16- and 32-bit types from the SD card file.
-// BMP data is stored little-endian, Arduino is little-endian too.
-// May need to reverse subscript order if porting elsewhere.
-
-uint16_t read16(File &f) {
- uint16_t result;
- ((uint8_t *)&result)[0] = f.read(); // LSB
- ((uint8_t *)&result)[1] = f.read(); // MSB
- return result;
-}
-
-uint32_t read32(File &f) {
- uint32_t result;
- ((uint8_t *)&result)[0] = f.read(); // LSB
- ((uint8_t *)&result)[1] = f.read();
- ((uint8_t *)&result)[2] = f.read();
- ((uint8_t *)&result)[3] = f.read(); // MSB
- return result;
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/touchpaint_featherwing/.mega2560.test.skip b/KugleFirmware/Libraries/Devices/LCD/examples/touchpaint_featherwing/.mega2560.test.skip
deleted file mode 100644
index e69de29..0000000
diff --git a/KugleFirmware/Libraries/Devices/LCD/examples/touchpaint_featherwing/touchpaint_featherwing.ino b/KugleFirmware/Libraries/Devices/LCD/examples/touchpaint_featherwing/touchpaint_featherwing.ino
deleted file mode 100644
index d739622..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/examples/touchpaint_featherwing/touchpaint_featherwing.ino
+++ /dev/null
@@ -1,177 +0,0 @@
-/***************************************************
- This is our library for the Adafruit HX8357D Featherwing
- ----> http://www.adafruit.com/products/2050
-
- Check out the links above for our tutorials and wiring diagrams
- These displays use SPI to communicate, 4 or 5 pins are required to
- interface (RST is optional)
- Adafruit invests time and resources providing this open source code,
- please support Adafruit and open-source hardware by purchasing
- products from Adafruit!
-
- Written by Limor Fried/Ladyada for Adafruit Industries.
- MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-#include
-#include // Core graphics library
-#include
-#include
-
-#ifdef ESP8266
- #define STMPE_CS 16
- #define TFT_CS 0
- #define TFT_DC 15
- #define SD_CS 2
-#endif
-#ifdef ESP32
- #define STMPE_CS 32
- #define TFT_CS 15
- #define TFT_DC 33
- #define SD_CS 14
-#endif
-#ifdef TEENSYDUINO
- #define TFT_DC 10
- #define TFT_CS 4
- #define STMPE_CS 3
- #define SD_CS 8
-#endif
-#ifdef ARDUINO_STM32_FEATHER
- #define TFT_DC PB4
- #define TFT_CS PA15
- #define STMPE_CS PC7
- #define SD_CS PC5
-#endif
-#ifdef ARDUINO_FEATHER52
- #define STMPE_CS 30
- #define TFT_CS 13
- #define TFT_DC 11
- #define SD_CS 27
-#endif
-#if defined(ARDUINO_MAX32620FTHR) || defined(ARDUINO_MAX32630FTHR)
- #define TFT_DC P5_4
- #define TFT_CS P5_3
- #define STMPE_CS P3_3
- #define SD_CS P3_2
-#endif
-
-// Anything else!
-#if defined (__AVR_ATmega32U4__) || defined(ARDUINO_SAMD_FEATHER_M0) || defined (__AVR_ATmega328P__) || defined(ARDUINO_SAMD_ZERO) || defined(__SAMD51__) || defined(__SAM3X8E__)
- #define STMPE_CS 6
- #define TFT_CS 9
- #define TFT_DC 10
- #define SD_CS 5
-#endif
-
-#define TFT_RST -1
-
-// Init screen on hardware SPI, HX8357D type:
-Adafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, TFT_RST);
-Adafruit_STMPE610 ts = Adafruit_STMPE610(STMPE_CS);
-
-// This is calibration data for the raw touch data to the screen coordinates
-#define TS_MINX 3800
-#define TS_MAXX 100
-#define TS_MINY 100
-#define TS_MAXY 3750
-
-// Size of the color selection boxes and the paintbrush size
-#define BOXSIZE 40
-#define PENRADIUS 3
-int oldcolor, currentcolor;
-
-
-void setup() {
- Serial.begin(115200);
- //while (!Serial) delay(10);
-
- Serial.println("HX8357D Featherwing touch test!");
-
- if (!ts.begin()) {
- Serial.println("Couldn't start touchscreen controller");
- while (1);
- }
- Serial.println("Touchscreen started");
-
- tft.begin();
- tft.fillScreen(HX8357_BLACK);
- // make the color selection boxes
- tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);
- tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);
- tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);
- tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);
- tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
-
- // select the current color 'red'
- tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- currentcolor = HX8357_RED;
-}
-
-
-void loop(void) {
- // Retrieve a point
- TS_Point p = ts.getPoint();
-
- // Serial.print("X = "); Serial.print(p.x); Serial.print("\tY = "); Serial.print(p.y); Serial.print("\tPressure = "); Serial.println(p.z);
-
- // Scale from ~0->4000 to tft.width using the calibration #'s
- p.x = map(p.x, TS_MINX, TS_MAXX, tft.width(), 0);
- p.y = map(p.y, TS_MINY, TS_MAXY, 0, tft.height());
-
- if (p.y < BOXSIZE) {
- oldcolor = currentcolor;
-
- if (p.x < BOXSIZE) {
- currentcolor = HX8357_RED;
- tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*2) {
- currentcolor = HX8357_YELLOW;
- tft.drawRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*3) {
- currentcolor = HX8357_GREEN;
- tft.drawRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*4) {
- currentcolor = HX8357_CYAN;
- tft.drawRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*5) {
- currentcolor = HX8357_BLUE;
- tft.drawRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*6) {
- currentcolor = HX8357_MAGENTA;
- tft.drawRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- } else if (p.x < BOXSIZE*7) {
- currentcolor = HX8357_WHITE;
- tft.drawRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- } else if (p.x < BOXSIZE*8) {
- currentcolor = HX8357_BLACK;
- tft.drawRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- }
-
-
- if (oldcolor != currentcolor) {
- if (oldcolor == HX8357_RED)
- tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);
- if (oldcolor == HX8357_YELLOW)
- tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);
- if (oldcolor == HX8357_GREEN)
- tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);
- if (oldcolor == HX8357_CYAN)
- tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);
- if (oldcolor == HX8357_BLUE)
- tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);
- if (oldcolor == HX8357_MAGENTA)
- tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);
- if (oldcolor == HX8357_WHITE)
- tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);
- if (oldcolor == HX8357_BLACK)
- tft.fillRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);
- }
- }
-
- if (((p.y-PENRADIUS) > 0) && ((p.y+PENRADIUS) < tft.height())) {
- tft.fillCircle(p.x, p.y, PENRADIUS, currentcolor);
- }
-}
diff --git a/KugleFirmware/Libraries/Devices/LCD/fontconvert/Makefile b/KugleFirmware/Libraries/Devices/LCD/fontconvert/Makefile
deleted file mode 100644
index 47f5a0e..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/fontconvert/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-all: fontconvert
-
-CC = gcc
-CFLAGS = -Wall -I/usr/local/include/freetype2 -I/usr/include/freetype2 -I/usr/include
-LIBS = -lfreetype
-
-fontconvert: fontconvert.c
- $(CC) $(CFLAGS) $< $(LIBS) -o $@
- strip $@
-
-clean:
- rm -f fontconvert
diff --git a/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert.c b/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert.c
deleted file mode 100644
index d2ce0dc..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
-TrueType to Adafruit_GFX font converter. Derived from Peter Jakobs'
-Adafruit_ftGFX fork & makefont tool, and Paul Kourany's Adafruit_mfGFX.
-
-NOT AN ARDUINO SKETCH. This is a command-line tool for preprocessing
-fonts to be used with the Adafruit_GFX Arduino library.
-
-For UNIX-like systems. Outputs to stdout; redirect to header file, e.g.:
- ./fontconvert ~/Library/Fonts/FreeSans.ttf 18 > FreeSans18pt7b.h
-
-REQUIRES FREETYPE LIBRARY. www.freetype.org
-
-Currently this only extracts the printable 7-bit ASCII chars of a font.
-Will eventually extend with some int'l chars a la ftGFX, not there yet.
-Keep 7-bit fonts around as an option in that case, more compact.
-
-See notes at end for glyph nomenclature & other tidbits.
-*/
-#ifndef ARDUINO
-
-#include
-#include
-#include
-#include
-#include FT_GLYPH_H
-#include "../gfxfont.h" // Adafruit_GFX font structures
-
-#define DPI 141 // Approximate res. of Adafruit 2.8" TFT
-
-// Accumulate bits for output, with periodic hexadecimal byte write
-void enbit(uint8_t value) {
- static uint8_t row = 0, sum = 0, bit = 0x80, firstCall = 1;
- if(value) sum |= bit; // Set bit if needed
- if(!(bit >>= 1)) { // Advance to next bit, end of byte reached?
- if(!firstCall) { // Format output table nicely
- if(++row >= 12) { // Last entry on line?
- printf(",\n "); // Newline format output
- row = 0; // Reset row counter
- } else { // Not end of line
- printf(", "); // Simple comma delim
- }
- }
- printf("0x%02X", sum); // Write byte value
- sum = 0; // Clear for next byte
- bit = 0x80; // Reset bit counter
- firstCall = 0; // Formatting flag
- }
-}
-
-int main(int argc, char *argv[]) {
- int i, j, err, size, first=' ', last='~',
- bitmapOffset = 0, x, y, byte;
- char *fontName, c, *ptr;
- FT_Library library;
- FT_Face face;
- FT_Glyph glyph;
- FT_Bitmap *bitmap;
- FT_BitmapGlyphRec *g;
- GFXglyph *table;
- uint8_t bit;
-
- // Parse command line. Valid syntaxes are:
- // fontconvert [filename] [size]
- // fontconvert [filename] [size] [last char]
- // fontconvert [filename] [size] [first char] [last char]
- // Unless overridden, default first and last chars are
- // ' ' (space) and '~', respectively
-
- if(argc < 3) {
- fprintf(stderr, "Usage: %s fontfile size [first] [last]\n",
- argv[0]);
- return 1;
- }
-
- size = atoi(argv[2]);
-
- if(argc == 4) {
- last = atoi(argv[3]);
- } else if(argc == 5) {
- first = atoi(argv[3]);
- last = atoi(argv[4]);
- }
-
- if(last < first) {
- i = first;
- first = last;
- last = i;
- }
-
- ptr = strrchr(argv[1], '/'); // Find last slash in filename
- if(ptr) ptr++; // First character of filename (path stripped)
- else ptr = argv[1]; // No path; font in local dir.
-
- // Allocate space for font name and glyph table
- if((!(fontName = malloc(strlen(ptr) + 20))) ||
- (!(table = (GFXglyph *)malloc((last - first + 1) *
- sizeof(GFXglyph))))) {
- fprintf(stderr, "Malloc error\n");
- return 1;
- }
-
- // Derive font table names from filename. Period (filename
- // extension) is truncated and replaced with the font size & bits.
- strcpy(fontName, ptr);
- ptr = strrchr(fontName, '.'); // Find last period (file ext)
- if(!ptr) ptr = &fontName[strlen(fontName)]; // If none, append
- // Insert font size and 7/8 bit. fontName was alloc'd w/extra
- // space to allow this, we're not sprintfing into Forbidden Zone.
- sprintf(ptr, "%dpt%db", size, (last > 127) ? 8 : 7);
- // Space and punctuation chars in name replaced w/ underscores.
- for(i=0; (c=fontName[i]); i++) {
- if(isspace(c) || ispunct(c)) fontName[i] = '_';
- }
-
- // Init FreeType lib, load font
- if((err = FT_Init_FreeType(&library))) {
- fprintf(stderr, "FreeType init error: %d", err);
- return err;
- }
-
- // Use TrueType engine version 35, without subpixel rendering.
- // This improves clarity of fonts since this library does not
- // support rendering multiple levels of gray in a glyph.
- // See https://github.com/adafruit/Adafruit-GFX-Library/issues/103
- FT_UInt interpreter_version = TT_INTERPRETER_VERSION_35;
- FT_Property_Set( library, "truetype",
- "interpreter-version",
- &interpreter_version );
-
- if((err = FT_New_Face(library, argv[1], 0, &face))) {
- fprintf(stderr, "Font load error: %d", err);
- FT_Done_FreeType(library);
- return err;
- }
-
- // << 6 because '26dot6' fixed-point format
- FT_Set_Char_Size(face, size << 6, 0, DPI, 0);
-
- // Currently all symbols from 'first' to 'last' are processed.
- // Fonts may contain WAY more glyphs than that, but this code
- // will need to handle encoding stuff to deal with extracting
- // the right symbols, and that's not done yet.
- // fprintf(stderr, "%ld glyphs\n", face->num_glyphs);
-
- printf("const uint8_t %sBitmaps[] PROGMEM = {\n ", fontName);
-
- // Process glyphs and output huge bitmap data array
- for(i=first, j=0; i<=last; i++, j++) {
- // MONO renderer provides clean image with perfect crop
- // (no wasted pixels) via bitmap struct.
- if((err = FT_Load_Char(face, i, FT_LOAD_TARGET_MONO))) {
- fprintf(stderr, "Error %d loading char '%c'\n",
- err, i);
- continue;
- }
-
- if((err = FT_Render_Glyph(face->glyph,
- FT_RENDER_MODE_MONO))) {
- fprintf(stderr, "Error %d rendering char '%c'\n",
- err, i);
- continue;
- }
-
- if((err = FT_Get_Glyph(face->glyph, &glyph))) {
- fprintf(stderr, "Error %d getting glyph '%c'\n",
- err, i);
- continue;
- }
-
- bitmap = &face->glyph->bitmap;
- g = (FT_BitmapGlyphRec *)glyph;
-
- // Minimal font and per-glyph information is stored to
- // reduce flash space requirements. Glyph bitmaps are
- // fully bit-packed; no per-scanline pad, though end of
- // each character may be padded to next byte boundary
- // when needed. 16-bit offset means 64K max for bitmaps,
- // code currently doesn't check for overflow. (Doesn't
- // check that size & offsets are within bounds either for
- // that matter...please convert fonts responsibly.)
- table[j].bitmapOffset = bitmapOffset;
- table[j].width = bitmap->width;
- table[j].height = bitmap->rows;
- table[j].xAdvance = face->glyph->advance.x >> 6;
- table[j].xOffset = g->left;
- table[j].yOffset = 1 - g->top;
-
- for(y=0; y < bitmap->rows; y++) {
- for(x=0;x < bitmap->width; x++) {
- byte = x / 8;
- bit = 0x80 >> (x & 7);
- enbit(bitmap->buffer[
- y * bitmap->pitch + byte] & bit);
- }
- }
-
- // Pad end of char bitmap to next byte boundary if needed
- int n = (bitmap->width * bitmap->rows) & 7;
- if(n) { // Pixel count not an even multiple of 8?
- n = 8 - n; // # bits to next multiple
- while(n--) enbit(0);
- }
- bitmapOffset += (bitmap->width * bitmap->rows + 7) / 8;
-
- FT_Done_Glyph(glyph);
- }
-
- printf(" };\n\n"); // End bitmap array
-
- // Output glyph attributes table (one per character)
- printf("const GFXglyph %sGlyphs[] PROGMEM = {\n", fontName);
- for(i=first, j=0; i<=last; i++, j++) {
- printf(" { %5d, %3d, %3d, %3d, %4d, %4d }",
- table[j].bitmapOffset,
- table[j].width,
- table[j].height,
- table[j].xAdvance,
- table[j].xOffset,
- table[j].yOffset);
- if(i < last) {
- printf(", // 0x%02X", i);
- if((i >= ' ') && (i <= '~')) {
- printf(" '%c'", i);
- }
- putchar('\n');
- }
- }
- printf(" }; // 0x%02X", last);
- if((last >= ' ') && (last <= '~')) printf(" '%c'", last);
- printf("\n\n");
-
- // Output font structure
- printf("const GFXfont %s PROGMEM = {\n", fontName);
- printf(" (uint8_t *)%sBitmaps,\n", fontName);
- printf(" (GFXglyph *)%sGlyphs,\n", fontName);
- if (face->size->metrics.height == 0) {
- // No face height info, assume fixed width and get from a glyph.
- printf(" 0x%02X, 0x%02X, %d };\n\n",
- first, last, table[0].height);
- } else {
- printf(" 0x%02X, 0x%02X, %ld };\n\n",
- first, last, face->size->metrics.height >> 6);
- }
- printf("// Approx. %d bytes\n",
- bitmapOffset + (last - first + 1) * 7 + 7);
- // Size estimate is based on AVR struct and pointer sizes;
- // actual size may vary.
-
- FT_Done_FreeType(library);
-
- return 0;
-}
-
-/* -------------------------------------------------------------------------
-
-Character metrics are slightly different from classic GFX & ftGFX.
-In classic GFX: cursor position is the upper-left pixel of each 5x7
-character; lower extent of most glyphs (except those w/descenders)
-is +6 pixels in Y direction.
-W/new GFX fonts: cursor position is on baseline, where baseline is
-'inclusive' (containing the bottom-most row of pixels in most symbols,
-except those with descenders; ftGFX is one pixel lower).
-
-Cursor Y will be moved automatically when switching between classic
-and new fonts. If you switch fonts, any print() calls will continue
-along the same baseline.
-
- ...........#####.. -- yOffset
- ..........######..
- ..........######..
- .........#######..
- ........#########.
- * = Cursor pos. ........#########.
- .......##########.
- ......#####..####.
- ......#####..####.
- *.#.. .....#####...####.
- .#.#. ....##############
- #...# ...###############
- #...# ...###############
- ##### ..#####......#####
- #...# .#####.......#####
-====== #...# ====== #*###.........#### ======= Baseline
- || xOffset
-
-glyph->xOffset and yOffset are pixel offsets, in GFX coordinate space
-(+Y is down), from the cursor position to the top-left pixel of the
-glyph bitmap. i.e. yOffset is typically negative, xOffset is typically
-zero but a few glyphs will have other values (even negative xOffsets
-sometimes, totally normal). glyph->xAdvance is the distance to move
-the cursor on the X axis after drawing the corresponding symbol.
-
-There's also some changes with regard to 'background' color and new GFX
-fonts (classic fonts unchanged). See Adafruit_GFX.cpp for explanation.
-*/
-
-#endif /* !ARDUINO */
diff --git a/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert_win.md b/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert_win.md
deleted file mode 100644
index 361078b..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/fontconvert/fontconvert_win.md
+++ /dev/null
@@ -1,88 +0,0 @@
-### A short guide to use fontconvert.c to create your own fonts using MinGW.
-
-#### STEP 1: INSTALL MinGW
-
-Install MinGW (Minimalist GNU for Windows) from [MinGW.org](http://www.mingw.org/).
-Please read carefully the instructions found on [Getting started page](http://www.mingw.org/wiki/Getting_Started).
-I suggest installing with the "Graphical User Interface Installer".
-To complete your initial installation you should further install some "packages".
-For our purpose you should only install the "Basic Setup" packages.
-To do that:
-
-1. Open the MinGW Installation Manager
-2. From the left panel click "Basic Setup".
-3. On the right panel choose "mingw32-base", "mingw-gcc-g++", "mingw-gcc-objc" and "msys-base"
-and click "Mark for installation"
-4. From the Menu click "Installation" and then "Apply changes". In the pop-up window select "Apply".
-
-
-#### STEP 2: INSTALL Freetype Library
-
-To read about the freetype project visit [freetype.org](https://www.freetype.org/).
-To Download the latest version of freetype go to [download page](http://download.savannah.gnu.org/releases/freetype/)
-and choose "freetype-2.7.tar.gz" file (or a newer version if available).
-To avoid long cd commands later in the command prompt, I suggest you unzip the file in the C:\ directory.
-(I also renamed the folder to "ft27")
-Before you build the library it's good to read these articles:
-* [Using MSYS with MinGW](http://www.mingw.org/wiki/MSYS)
-* [Installation and Use of Supplementary Libraries with MinGW](http://www.mingw.org/wiki/LibraryPathHOWTO)
-* [Include Path](http://www.mingw.org/wiki/IncludePathHOWTO)
-
-Inside the unzipped folder there is another folder named "docs". Open it and read the INSTALL.UNIX (using notepad).
-Pay attention to paragraph 3 (Build and Install the Library). So, let's begin the installation.
-To give the appropriate commands we will use the MSYS command prompt (not cmd.exe of windows) which is UNIX like.
-Follow the path C:\MinGW\msys\1.0 and double click "msys.bat". The command prompt environment appears.
-Enter "ft27" directory using the cd commands:
-```
-cd /c
-cd ft27
-```
-
-and then type one by one the commands:
-```
-./configure --prefix=/mingw
-make
-make install
-```
-Once you're finished, go inside "C:\MinGW\include" and there should be a new folder named "freetype2".
-That, hopefully, means that you have installed the library correctly !!
-
-#### STEP 3: Build fontconvert.c
-
-Before proceeding I suggest you make a copy of Adafruit_GFX_library folder in C:\ directory.
-Then, inside "fontconvert" folder open the "makefile" with an editor ( I used notepad++).
-Change the commands so in the end the program looks like :
-```
-all: fontconvert
-
-CC = gcc
-CFLAGS = -Wall -I c:/mingw/include/freetype2
-LIBS = -lfreetype
-
-fontconvert: fontconvert.c
- $(CC) $(CFLAGS) $< $(LIBS) -o $@
-
-clean:
- rm -f fontconvert
-```
-Go back in the command prompt and with a cd command enter the fontconvert directory.
-```
-cd /c/adafruit_gfx_library\fontconvert
-```
-Give the command:
-```
-make
-```
-This command will, eventually, create a "fontconvert.exe" file inside fontconvert directory.
-
-#### STEP 4: Create your own font header files
-
-Now that you have an executable file, you can use it to create your own fonts to work with Adafruit GFX lib.
-So, if we suppose that you already have a .ttf file with your favorite fonts, jump to the command prompt and type:
-```
-./fontconvert yourfonts.ttf 9 > yourfonts9pt7b.h
-```
-You can read more details at: [learn.adafruit](https://learn.adafruit.com/adafruit-gfx-graphics-library/using-fonts).
-
-Taraaaaaammm !! you've just created your new font header file. Put it inside the "Fonts" folder, grab a cup of coffee
-and start playing with your Arduino (or whatever else ....)+ display module project.
diff --git a/KugleFirmware/Libraries/Devices/LCD/fontconvert/makefonts.sh b/KugleFirmware/Libraries/Devices/LCD/fontconvert/makefonts.sh
deleted file mode 100644
index 35f07ea..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/fontconvert/makefonts.sh
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/bash
-
-# Ugly little Bash script, generates a set of .h files for GFX using
-# GNU FreeFont sources. There are three fonts: 'Mono' (Courier-like),
-# 'Sans' (Helvetica-like) and 'Serif' (Times-like); four styles: regular,
-# bold, oblique or italic, and bold+oblique or bold+italic; and four
-# sizes: 9, 12, 18 and 24 point. No real error checking or anything,
-# this just powers through all the combinations, calling the fontconvert
-# utility and redirecting the output to a .h file for each combo.
-
-# Adafruit_GFX repository does not include the source outline fonts
-# (huge zipfile, different license) but they're easily acquired:
-# http://savannah.gnu.org/projects/freefont/
-
-convert=./fontconvert
-inpath=~/Desktop/freefont/
-outpath=../Fonts/
-fonts=(FreeMono FreeSans FreeSerif)
-styles=("" Bold Italic BoldItalic Oblique BoldOblique)
-sizes=(9 12 18 24)
-
-for f in ${fonts[*]}
-do
- for index in ${!styles[*]}
- do
- st=${styles[$index]}
- for si in ${sizes[*]}
- do
- infile=$inpath$f$st".ttf"
- if [ -f $infile ] # Does source combination exist?
- then
- outfile=$outpath$f$st$si"pt7b.h"
-# printf "%s %s %s > %s\n" $convert $infile $si $outfile
- $convert $infile $si > $outfile
- fi
- done
- done
-done
diff --git a/KugleFirmware/Libraries/Devices/LCD/gfxfont.h b/KugleFirmware/Libraries/Devices/LCD/gfxfont.h
deleted file mode 100644
index c691de6..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/gfxfont.h
+++ /dev/null
@@ -1,29 +0,0 @@
-// Font structures for newer Adafruit_GFX (1.1 and later).
-// Example fonts are included in 'Fonts' directory.
-// To use a font in your Arduino sketch, #include the corresponding .h
-// file and pass address of GFXfont struct to setFont(). Pass NULL to
-// revert to 'classic' fixed-space bitmap font.
-
-#ifndef _GFXFONT_H_
-#define _GFXFONT_H_
-
-/// Font data stored PER GLYPH
-typedef struct {
- uint16_t bitmapOffset; ///< Pointer into GFXfont->bitmap
- uint8_t width; ///< Bitmap dimensions in pixels
- uint8_t height; ///< Bitmap dimensions in pixels
- uint8_t xAdvance; ///< Distance to advance cursor (x axis)
- int8_t xOffset; ///< X dist from cursor pos to UL corner
- int8_t yOffset; ///< Y dist from cursor pos to UL corner
-} GFXglyph;
-
-/// Data stored for FONT AS A WHOLE
-typedef struct {
- uint8_t *bitmap; ///< Glyph bitmaps, concatenated
- GFXglyph *glyph; ///< Glyph array
- uint8_t first; ///< ASCII extents (first char)
- uint8_t last; ///< ASCII extents (last char)
- uint8_t yAdvance; ///< Newline distance (y axis)
-} GFXfont;
-
-#endif // _GFXFONT_H_
diff --git a/KugleFirmware/Libraries/Devices/LCD/glcdfont.c b/KugleFirmware/Libraries/Devices/LCD/glcdfont.c
deleted file mode 100644
index 6f88bd2..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/glcdfont.c
+++ /dev/null
@@ -1,276 +0,0 @@
-// This is the 'classic' fixed-space bitmap font for Adafruit_GFX since 1.0.
-// See gfxfont.h for newer custom bitmap font info.
-
-#ifndef FONT5X7_H
-#define FONT5X7_H
-
-#ifdef __AVR__
- #include
- #include
-#elif defined(ESP8266)
- #include
-#else
- #define PROGMEM
-#endif
-
-// Standard ASCII 5x7 font
-
-static const unsigned char font[] PROGMEM = {
- 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x3E, 0x5B, 0x4F, 0x5B, 0x3E,
- 0x3E, 0x6B, 0x4F, 0x6B, 0x3E,
- 0x1C, 0x3E, 0x7C, 0x3E, 0x1C,
- 0x18, 0x3C, 0x7E, 0x3C, 0x18,
- 0x1C, 0x57, 0x7D, 0x57, 0x1C,
- 0x1C, 0x5E, 0x7F, 0x5E, 0x1C,
- 0x00, 0x18, 0x3C, 0x18, 0x00,
- 0xFF, 0xE7, 0xC3, 0xE7, 0xFF,
- 0x00, 0x18, 0x24, 0x18, 0x00,
- 0xFF, 0xE7, 0xDB, 0xE7, 0xFF,
- 0x30, 0x48, 0x3A, 0x06, 0x0E,
- 0x26, 0x29, 0x79, 0x29, 0x26,
- 0x40, 0x7F, 0x05, 0x05, 0x07,
- 0x40, 0x7F, 0x05, 0x25, 0x3F,
- 0x5A, 0x3C, 0xE7, 0x3C, 0x5A,
- 0x7F, 0x3E, 0x1C, 0x1C, 0x08,
- 0x08, 0x1C, 0x1C, 0x3E, 0x7F,
- 0x14, 0x22, 0x7F, 0x22, 0x14,
- 0x5F, 0x5F, 0x00, 0x5F, 0x5F,
- 0x06, 0x09, 0x7F, 0x01, 0x7F,
- 0x00, 0x66, 0x89, 0x95, 0x6A,
- 0x60, 0x60, 0x60, 0x60, 0x60,
- 0x94, 0xA2, 0xFF, 0xA2, 0x94,
- 0x08, 0x04, 0x7E, 0x04, 0x08,
- 0x10, 0x20, 0x7E, 0x20, 0x10,
- 0x08, 0x08, 0x2A, 0x1C, 0x08,
- 0x08, 0x1C, 0x2A, 0x08, 0x08,
- 0x1E, 0x10, 0x10, 0x10, 0x10,
- 0x0C, 0x1E, 0x0C, 0x1E, 0x0C,
- 0x30, 0x38, 0x3E, 0x38, 0x30,
- 0x06, 0x0E, 0x3E, 0x0E, 0x06,
- 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x5F, 0x00, 0x00,
- 0x00, 0x07, 0x00, 0x07, 0x00,
- 0x14, 0x7F, 0x14, 0x7F, 0x14,
- 0x24, 0x2A, 0x7F, 0x2A, 0x12,
- 0x23, 0x13, 0x08, 0x64, 0x62,
- 0x36, 0x49, 0x56, 0x20, 0x50,
- 0x00, 0x08, 0x07, 0x03, 0x00,
- 0x00, 0x1C, 0x22, 0x41, 0x00,
- 0x00, 0x41, 0x22, 0x1C, 0x00,
- 0x2A, 0x1C, 0x7F, 0x1C, 0x2A,
- 0x08, 0x08, 0x3E, 0x08, 0x08,
- 0x00, 0x80, 0x70, 0x30, 0x00,
- 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x00, 0x00, 0x60, 0x60, 0x00,
- 0x20, 0x10, 0x08, 0x04, 0x02,
- 0x3E, 0x51, 0x49, 0x45, 0x3E,
- 0x00, 0x42, 0x7F, 0x40, 0x00,
- 0x72, 0x49, 0x49, 0x49, 0x46,
- 0x21, 0x41, 0x49, 0x4D, 0x33,
- 0x18, 0x14, 0x12, 0x7F, 0x10,
- 0x27, 0x45, 0x45, 0x45, 0x39,
- 0x3C, 0x4A, 0x49, 0x49, 0x31,
- 0x41, 0x21, 0x11, 0x09, 0x07,
- 0x36, 0x49, 0x49, 0x49, 0x36,
- 0x46, 0x49, 0x49, 0x29, 0x1E,
- 0x00, 0x00, 0x14, 0x00, 0x00,
- 0x00, 0x40, 0x34, 0x00, 0x00,
- 0x00, 0x08, 0x14, 0x22, 0x41,
- 0x14, 0x14, 0x14, 0x14, 0x14,
- 0x00, 0x41, 0x22, 0x14, 0x08,
- 0x02, 0x01, 0x59, 0x09, 0x06,
- 0x3E, 0x41, 0x5D, 0x59, 0x4E,
- 0x7C, 0x12, 0x11, 0x12, 0x7C,
- 0x7F, 0x49, 0x49, 0x49, 0x36,
- 0x3E, 0x41, 0x41, 0x41, 0x22,
- 0x7F, 0x41, 0x41, 0x41, 0x3E,
- 0x7F, 0x49, 0x49, 0x49, 0x41,
- 0x7F, 0x09, 0x09, 0x09, 0x01,
- 0x3E, 0x41, 0x41, 0x51, 0x73,
- 0x7F, 0x08, 0x08, 0x08, 0x7F,
- 0x00, 0x41, 0x7F, 0x41, 0x00,
- 0x20, 0x40, 0x41, 0x3F, 0x01,
- 0x7F, 0x08, 0x14, 0x22, 0x41,
- 0x7F, 0x40, 0x40, 0x40, 0x40,
- 0x7F, 0x02, 0x1C, 0x02, 0x7F,
- 0x7F, 0x04, 0x08, 0x10, 0x7F,
- 0x3E, 0x41, 0x41, 0x41, 0x3E,
- 0x7F, 0x09, 0x09, 0x09, 0x06,
- 0x3E, 0x41, 0x51, 0x21, 0x5E,
- 0x7F, 0x09, 0x19, 0x29, 0x46,
- 0x26, 0x49, 0x49, 0x49, 0x32,
- 0x03, 0x01, 0x7F, 0x01, 0x03,
- 0x3F, 0x40, 0x40, 0x40, 0x3F,
- 0x1F, 0x20, 0x40, 0x20, 0x1F,
- 0x3F, 0x40, 0x38, 0x40, 0x3F,
- 0x63, 0x14, 0x08, 0x14, 0x63,
- 0x03, 0x04, 0x78, 0x04, 0x03,
- 0x61, 0x59, 0x49, 0x4D, 0x43,
- 0x00, 0x7F, 0x41, 0x41, 0x41,
- 0x02, 0x04, 0x08, 0x10, 0x20,
- 0x00, 0x41, 0x41, 0x41, 0x7F,
- 0x04, 0x02, 0x01, 0x02, 0x04,
- 0x40, 0x40, 0x40, 0x40, 0x40,
- 0x00, 0x03, 0x07, 0x08, 0x00,
- 0x20, 0x54, 0x54, 0x78, 0x40,
- 0x7F, 0x28, 0x44, 0x44, 0x38,
- 0x38, 0x44, 0x44, 0x44, 0x28,
- 0x38, 0x44, 0x44, 0x28, 0x7F,
- 0x38, 0x54, 0x54, 0x54, 0x18,
- 0x00, 0x08, 0x7E, 0x09, 0x02,
- 0x18, 0xA4, 0xA4, 0x9C, 0x78,
- 0x7F, 0x08, 0x04, 0x04, 0x78,
- 0x00, 0x44, 0x7D, 0x40, 0x00,
- 0x20, 0x40, 0x40, 0x3D, 0x00,
- 0x7F, 0x10, 0x28, 0x44, 0x00,
- 0x00, 0x41, 0x7F, 0x40, 0x00,
- 0x7C, 0x04, 0x78, 0x04, 0x78,
- 0x7C, 0x08, 0x04, 0x04, 0x78,
- 0x38, 0x44, 0x44, 0x44, 0x38,
- 0xFC, 0x18, 0x24, 0x24, 0x18,
- 0x18, 0x24, 0x24, 0x18, 0xFC,
- 0x7C, 0x08, 0x04, 0x04, 0x08,
- 0x48, 0x54, 0x54, 0x54, 0x24,
- 0x04, 0x04, 0x3F, 0x44, 0x24,
- 0x3C, 0x40, 0x40, 0x20, 0x7C,
- 0x1C, 0x20, 0x40, 0x20, 0x1C,
- 0x3C, 0x40, 0x30, 0x40, 0x3C,
- 0x44, 0x28, 0x10, 0x28, 0x44,
- 0x4C, 0x90, 0x90, 0x90, 0x7C,
- 0x44, 0x64, 0x54, 0x4C, 0x44,
- 0x00, 0x08, 0x36, 0x41, 0x00,
- 0x00, 0x00, 0x77, 0x00, 0x00,
- 0x00, 0x41, 0x36, 0x08, 0x00,
- 0x02, 0x01, 0x02, 0x04, 0x02,
- 0x3C, 0x26, 0x23, 0x26, 0x3C,
- 0x1E, 0xA1, 0xA1, 0x61, 0x12,
- 0x3A, 0x40, 0x40, 0x20, 0x7A,
- 0x38, 0x54, 0x54, 0x55, 0x59,
- 0x21, 0x55, 0x55, 0x79, 0x41,
- 0x22, 0x54, 0x54, 0x78, 0x42, // a-umlaut
- 0x21, 0x55, 0x54, 0x78, 0x40,
- 0x20, 0x54, 0x55, 0x79, 0x40,
- 0x0C, 0x1E, 0x52, 0x72, 0x12,
- 0x39, 0x55, 0x55, 0x55, 0x59,
- 0x39, 0x54, 0x54, 0x54, 0x59,
- 0x39, 0x55, 0x54, 0x54, 0x58,
- 0x00, 0x00, 0x45, 0x7C, 0x41,
- 0x00, 0x02, 0x45, 0x7D, 0x42,
- 0x00, 0x01, 0x45, 0x7C, 0x40,
- 0x7D, 0x12, 0x11, 0x12, 0x7D, // A-umlaut
- 0xF0, 0x28, 0x25, 0x28, 0xF0,
- 0x7C, 0x54, 0x55, 0x45, 0x00,
- 0x20, 0x54, 0x54, 0x7C, 0x54,
- 0x7C, 0x0A, 0x09, 0x7F, 0x49,
- 0x32, 0x49, 0x49, 0x49, 0x32,
- 0x3A, 0x44, 0x44, 0x44, 0x3A, // o-umlaut
- 0x32, 0x4A, 0x48, 0x48, 0x30,
- 0x3A, 0x41, 0x41, 0x21, 0x7A,
- 0x3A, 0x42, 0x40, 0x20, 0x78,
- 0x00, 0x9D, 0xA0, 0xA0, 0x7D,
- 0x3D, 0x42, 0x42, 0x42, 0x3D, // O-umlaut
- 0x3D, 0x40, 0x40, 0x40, 0x3D,
- 0x3C, 0x24, 0xFF, 0x24, 0x24,
- 0x48, 0x7E, 0x49, 0x43, 0x66,
- 0x2B, 0x2F, 0xFC, 0x2F, 0x2B,
- 0xFF, 0x09, 0x29, 0xF6, 0x20,
- 0xC0, 0x88, 0x7E, 0x09, 0x03,
- 0x20, 0x54, 0x54, 0x79, 0x41,
- 0x00, 0x00, 0x44, 0x7D, 0x41,
- 0x30, 0x48, 0x48, 0x4A, 0x32,
- 0x38, 0x40, 0x40, 0x22, 0x7A,
- 0x00, 0x7A, 0x0A, 0x0A, 0x72,
- 0x7D, 0x0D, 0x19, 0x31, 0x7D,
- 0x26, 0x29, 0x29, 0x2F, 0x28,
- 0x26, 0x29, 0x29, 0x29, 0x26,
- 0x30, 0x48, 0x4D, 0x40, 0x20,
- 0x38, 0x08, 0x08, 0x08, 0x08,
- 0x08, 0x08, 0x08, 0x08, 0x38,
- 0x2F, 0x10, 0xC8, 0xAC, 0xBA,
- 0x2F, 0x10, 0x28, 0x34, 0xFA,
- 0x00, 0x00, 0x7B, 0x00, 0x00,
- 0x08, 0x14, 0x2A, 0x14, 0x22,
- 0x22, 0x14, 0x2A, 0x14, 0x08,
- 0x55, 0x00, 0x55, 0x00, 0x55, // #176 (25% block) missing in old code
- 0xAA, 0x55, 0xAA, 0x55, 0xAA, // 50% block
- 0xFF, 0x55, 0xFF, 0x55, 0xFF, // 75% block
- 0x00, 0x00, 0x00, 0xFF, 0x00,
- 0x10, 0x10, 0x10, 0xFF, 0x00,
- 0x14, 0x14, 0x14, 0xFF, 0x00,
- 0x10, 0x10, 0xFF, 0x00, 0xFF,
- 0x10, 0x10, 0xF0, 0x10, 0xF0,
- 0x14, 0x14, 0x14, 0xFC, 0x00,
- 0x14, 0x14, 0xF7, 0x00, 0xFF,
- 0x00, 0x00, 0xFF, 0x00, 0xFF,
- 0x14, 0x14, 0xF4, 0x04, 0xFC,
- 0x14, 0x14, 0x17, 0x10, 0x1F,
- 0x10, 0x10, 0x1F, 0x10, 0x1F,
- 0x14, 0x14, 0x14, 0x1F, 0x00,
- 0x10, 0x10, 0x10, 0xF0, 0x00,
- 0x00, 0x00, 0x00, 0x1F, 0x10,
- 0x10, 0x10, 0x10, 0x1F, 0x10,
- 0x10, 0x10, 0x10, 0xF0, 0x10,
- 0x00, 0x00, 0x00, 0xFF, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10,
- 0x10, 0x10, 0x10, 0xFF, 0x10,
- 0x00, 0x00, 0x00, 0xFF, 0x14,
- 0x00, 0x00, 0xFF, 0x00, 0xFF,
- 0x00, 0x00, 0x1F, 0x10, 0x17,
- 0x00, 0x00, 0xFC, 0x04, 0xF4,
- 0x14, 0x14, 0x17, 0x10, 0x17,
- 0x14, 0x14, 0xF4, 0x04, 0xF4,
- 0x00, 0x00, 0xFF, 0x00, 0xF7,
- 0x14, 0x14, 0x14, 0x14, 0x14,
- 0x14, 0x14, 0xF7, 0x00, 0xF7,
- 0x14, 0x14, 0x14, 0x17, 0x14,
- 0x10, 0x10, 0x1F, 0x10, 0x1F,
- 0x14, 0x14, 0x14, 0xF4, 0x14,
- 0x10, 0x10, 0xF0, 0x10, 0xF0,
- 0x00, 0x00, 0x1F, 0x10, 0x1F,
- 0x00, 0x00, 0x00, 0x1F, 0x14,
- 0x00, 0x00, 0x00, 0xFC, 0x14,
- 0x00, 0x00, 0xF0, 0x10, 0xF0,
- 0x10, 0x10, 0xFF, 0x10, 0xFF,
- 0x14, 0x14, 0x14, 0xFF, 0x14,
- 0x10, 0x10, 0x10, 0x1F, 0x00,
- 0x00, 0x00, 0x00, 0xF0, 0x10,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
- 0xFF, 0xFF, 0xFF, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xFF, 0xFF,
- 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x38, 0x44, 0x44, 0x38, 0x44,
- 0xFC, 0x4A, 0x4A, 0x4A, 0x34, // sharp-s or beta
- 0x7E, 0x02, 0x02, 0x06, 0x06,
- 0x02, 0x7E, 0x02, 0x7E, 0x02,
- 0x63, 0x55, 0x49, 0x41, 0x63,
- 0x38, 0x44, 0x44, 0x3C, 0x04,
- 0x40, 0x7E, 0x20, 0x1E, 0x20,
- 0x06, 0x02, 0x7E, 0x02, 0x02,
- 0x99, 0xA5, 0xE7, 0xA5, 0x99,
- 0x1C, 0x2A, 0x49, 0x2A, 0x1C,
- 0x4C, 0x72, 0x01, 0x72, 0x4C,
- 0x30, 0x4A, 0x4D, 0x4D, 0x30,
- 0x30, 0x48, 0x78, 0x48, 0x30,
- 0xBC, 0x62, 0x5A, 0x46, 0x3D,
- 0x3E, 0x49, 0x49, 0x49, 0x00,
- 0x7E, 0x01, 0x01, 0x01, 0x7E,
- 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
- 0x44, 0x44, 0x5F, 0x44, 0x44,
- 0x40, 0x51, 0x4A, 0x44, 0x40,
- 0x40, 0x44, 0x4A, 0x51, 0x40,
- 0x00, 0x00, 0xFF, 0x01, 0x03,
- 0xE0, 0x80, 0xFF, 0x00, 0x00,
- 0x08, 0x08, 0x6B, 0x6B, 0x08,
- 0x36, 0x12, 0x36, 0x24, 0x36,
- 0x06, 0x0F, 0x09, 0x0F, 0x06,
- 0x00, 0x00, 0x18, 0x18, 0x00,
- 0x00, 0x00, 0x10, 0x10, 0x00,
- 0x30, 0x40, 0xFF, 0x01, 0x01,
- 0x00, 0x1F, 0x01, 0x01, 0x1E,
- 0x00, 0x19, 0x1D, 0x17, 0x12,
- 0x00, 0x3C, 0x3C, 0x3C, 0x3C,
- 0x00, 0x00, 0x00, 0x00, 0x00 // #255 NBSP
-};
-#endif // FONT5X7_H
diff --git a/KugleFirmware/Libraries/Devices/LCD/jumpers.bmp b/KugleFirmware/Libraries/Devices/LCD/jumpers.bmp
deleted file mode 100644
index 07dbd16..0000000
Binary files a/KugleFirmware/Libraries/Devices/LCD/jumpers.bmp and /dev/null differ
diff --git a/KugleFirmware/Libraries/Devices/LCD/library.properties b/KugleFirmware/Libraries/Devices/LCD/library.properties
deleted file mode 100644
index 4c17842..0000000
--- a/KugleFirmware/Libraries/Devices/LCD/library.properties
+++ /dev/null
@@ -1,9 +0,0 @@
-name=Adafruit HX8357 Library
-version=1.0.8
-author=Adafruit
-maintainer=Adafruit
-sentence=Adafruit HX8357 3.5" display library.
-paragraph=Adafruit HX8357 3.5" display library.
-category=Display
-url=https://github.com/adafruit/Adafruit_HX8357_Library
-architectures=*
diff --git a/KugleFirmware/Libraries/Devices/LSPC/LSPC.hpp b/KugleFirmware/Libraries/Devices/LSPC/LSPC.hpp
deleted file mode 100644
index 5cd7b5f..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/LSPC.hpp
+++ /dev/null
@@ -1,171 +0,0 @@
-#ifndef LSPC_TEMPLATED_HPP
-#define LSPC_TEMPLATED_HPP
-
-#include "Packet.hpp"
-#include "Serializable.hpp"
-#include "SocketBase.hpp"
-#include "Debug.h"
-#include "cmsis_os.h" // for task creation
-#include "USBCDC.h"
-#include "UART.h"
-#include "MessageTypes.h"
-
-#define LSPC_MAX_ASYNCHRONOUS_PACKAGE_SIZE 100 // bytes
-#define LSPC_MAXIMUM_PACKAGE_LENGTH 250
-#define LSPC_ASYNCHRONOUS_QUEUE_LENGTH 100 // maximum 100 asynchronous packages in queue
-#define LSPC_RX_PROCESSING_THREAD_STACK_SIZE 1024
-#define LSPC_TX_TRANSMITTER_THREAD_STACK_SIZE 512
-
-namespace lspc
-{
-
-typedef struct LSPC_Async_Package_t {
- uint8_t type;
- std::vector * payloadPtr;
-} LSPC_Async_Package_t;
-
-template
-class Socket : public SocketBase
-{
-public:
- Socket(COM * com, uint32_t processingTaskPriority, uint32_t transmitterTaskPriority) : com(com), _processingTaskHandle(0), _transmitterTaskHandle(0)
- {
- _TXqueue = xQueueCreate( LSPC_ASYNCHRONOUS_QUEUE_LENGTH, sizeof(LSPC_Async_Package_t) );
- if (_TXqueue == NULL) {
- ERROR("Could not create asynchronous LSPC TX queue");
- return;
- }
- vQueueAddToRegistry(_TXqueue, "LSPC TX");
-
- xTaskCreate(Socket::ProcessingThread, (char *)"LSPC processing", LSPC_RX_PROCESSING_THREAD_STACK_SIZE, (void*) this, processingTaskPriority, &_processingTaskHandle);
- xTaskCreate(Socket::TransmitterThread, (char *)"LSPC transmitter", LSPC_TX_TRANSMITTER_THREAD_STACK_SIZE, (void*) this, transmitterTaskPriority, &_transmitterTaskHandle);
- };
-
-private:
- using SocketBase::send;
-
- // Send a package with lspc
- //
- // @brief Sends a packaged buffer over the USB serial link.
- //
- // @param type The message type. This is user specific; any type between 1-255.
- // @param payload A vector with the serialized payload to be sent.
- //
- // @return True if the packet was sent.
- bool send(uint8_t type, const std::vector &payload) override
- {
- Packet outPacket(type, payload);
-
- // Send it
- if (outPacket.encodedDataSize() ==
- com->Write(outPacket.encodedDataPtr(), outPacket.encodedDataSize()))
- return true;
- else
- return false;
- };
-
-
- // Process incoming data on serial link
- //
- // @brief Reads the serial buffer and dispatches the received payload to the
- // relevant message handling callback function.
- void processSerial()
- {
- int16_t readChar = 0;
- while (com->Available())
- {
- readChar = com->Read();
- if (readChar >= 0)
- processIncomingByte(readChar);
- }
- return;
- };
-
-
-public:
- void TransmitAsync(uint8_t type, const uint8_t * payload, uint16_t payloadLength)
- {
- LSPC_Async_Package_t package;
- if (payloadLength > LSPC_MAXIMUM_PACKAGE_LENGTH) return; // payload size is too big
- if (uxQueueSpacesAvailable(_TXqueue) == 0) {
- return; // no space in queue
- }
-
- package.type = type;
- package.payloadPtr = new std::vector(payloadLength);
- if (!package.payloadPtr) return;
- memcpy(package.payloadPtr->data(), payload, payloadLength);
- if (xQueueSend(_TXqueue, (void *)&package, (TickType_t) 0) != pdTRUE) {
- delete(package.payloadPtr); // could not add package to queue, probably because it is full
- }
- }
-
- bool Connected(void)
- {
- return com->Connected();
- }
-
-
-private:
- static void ProcessingThread(void * pvParameters)
- {
- Socket * lspc = (Socket *)pvParameters;
-
- lspc->incoming_data.reserve(LSPC_MAXIMUM_PACKAGE_LENGTH);
-
- // LSPC incoming data processing loop
- while (1)
- {
- if (lspc->com->WaitForNewData(portMAX_DELAY))
- lspc->processSerial();
- }
- }
-
- static void TransmitterThread(void * pvParameters)
- {
- Socket * lspc = (Socket *)pvParameters;
- LSPC_Async_Package_t package;
-
- while (1)
- {
- if (lspc->Connected()) {
- // LSPC outgoing (transmission) data loop
- while (lspc->Connected())
- {
- if ( xQueueReceive( lspc->_TXqueue, &package, ( TickType_t ) portMAX_DELAY ) == pdPASS ) {
- // Send it if possible
- Packet * outPacket = new Packet(package.type, *package.payloadPtr);
- if (!outPacket) continue;
-
- if (outPacket->encodedDataSize() ==
- lspc->com->WriteBlocking(outPacket->encodedDataPtr(), outPacket->encodedDataSize())) {
- delete(package.payloadPtr); // clear memory used for payload data
- }
- else { // if not, re-add it to the queue
- //xQueueSend(lspc->_TXqueue, (void *)&package, (TickType_t) 1); // re-add it to the queue is probably not a good idea
- delete(package.payloadPtr); // clear memory used for payload data
- }
- delete(outPacket);
- }
- }
- }
- osDelay(100);
- }
- }
-
-public:
- COM * com;
-
-private:
- TaskHandle_t _processingTaskHandle;
- TaskHandle_t _transmitterTaskHandle;
- SemaphoreHandle_t _newTransmitDataSemaphore;
- QueueHandle_t _TXqueue;
-
-};
-
-} // namespace lspc
-
-using LSPC = lspc::Socket; // define whether to use USB or UART
-
-#endif // LSPC_TEMPLATED_HPP
diff --git a/KugleFirmware/Libraries/Devices/LSPC/MessageTypes.h b/KugleFirmware/Libraries/Devices/LSPC/MessageTypes.h
deleted file mode 100644
index 0c025c6..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/MessageTypes.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/* Copyright (C) 2018-2019 Thomas Jespersen, TKJ Electronics. All rights reserved.
- *
- * This program is free software: you can redistribute it and/or modify it
- * under the terms of the MIT License
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the MIT License for further details.
- *
- * Contact information
- * ------------------------------------------
- * Thomas Jespersen, TKJ Electronics
- * Web : http://www.tkjelectronics.dk
- * e-mail : thomasj@tkjelectronics.dk
- * ------------------------------------------
- */
-
-/* OBS. Remember to keep this file consistent across the Embedded Firmware (Kugle-Embedded) and ROS Driver (Kugle-ROS) */
-
-#ifndef LSPC_MESSAGE_TYPES_HPP
-#define LSPC_MESSAGE_TYPES_HPP
-
-#include
-
-namespace lspc
-{
- namespace ParameterLookup {
- typedef enum: uint8_t
- {
- _unknown = 0x00,
- _bool = 0x01,
- _float,
- _uint8,
- _uint16,
- _uint32
- } ValueType_t;
- typedef enum: uint8_t
- {
- unknown = 0x00,
- debug = 0x01,
- behavioural,
- controller,
- estimator,
- model,
- test
- } type_t;
-
- typedef enum: uint8_t
- {
- EnableDumpMessages = 0x01,
- EnableRawSensorOutput,
- UseFilteredIMUinRawSensorOutput,
- DisableMotorOutput
- } debug_t;
-
- typedef enum: uint8_t
- {
- IndependentHeading = 0x01,
- YawVelocityBraking,
- StepTestEnabled,
- SineTestEnabled,
- CircleTestEnabled,
- PowerButtonMode
- } behavioural_t;
-
- typedef enum: uint8_t
- {
- ControllerSampleRate = 0x01,
- type,
- mode,
- EnableTorqueLPF,
- TorqueLPFtau,
- MotorFailureDetection,
- EnableTorqueSaturation,
- TorqueMax,
- TorqueRampUp,
- TorqueRampUpTime,
- DisableQdot,
- DisableQdotInEquivalentControl,
- DisableOmegaXYInEquivalentControl,
- AngularVelocityClampsEnabled,
- AngularVelocityClamps,
- ManifoldType,
- K,
- Kx,
- Ky,
- Kz,
- Kv_x,
- Kv_y,
- Kvi_x,
- Kvi_y,
- gamma,
- ContinousSwitching,
- EquivalentControl,
- eta,
- epsilon,
- LQR_K,
- LQR_MaxYawError,
- VelocityControl_AccelerationLimit,
- VelocityControl_UseOmegaRef,
- VelocityController_MaxTilt,
- VelocityController_MaxIntegralCorrection,
- VelocityController_VelocityClamp,
- VelocityController_IntegralGain,
- VelocityController_AngleLPFtau,
- VelocityController_OmegaLPFtau
- } controller_t;
-
- typedef enum: uint8_t
- {
- EstimatorSampleRate = 0x01,
- EnableSensorLPFfilters,
- EnableSoftwareLPFfilters,
- SoftwareLPFcoeffs_a,
- SoftwareLPFcoeffs_b,
- CreateQdotFromQDifference,
- UseMadgwick,
- EstimateBias,
- SensorDrivenQEKF,
- UseCoRvelocity,
- UseVelocityEstimator,
- EnableVelocityLPF,
- EnableWheelSlipDetector,
- UseQdotInVelocityEstimator,
- EstimateCOM,
- EstimateCOMminVelocity,
- MaxCOMDeviation,
- MadgwickBeta,
- GyroCov_Tuning_Factor,
- AccelCov_Tuning_Factor,
- cov_gyro_mpu,
- cov_acc_mpu,
- sigma2_bias,
- sigma2_omega,
- sigma2_heading,
- GyroscopeTrustFactor,
- eta_encoder,
- eta_accelerometer,
- var_acc_bias,
- var_acceleration
- } estimator_t;
-
- typedef enum: uint8_t
- {
- l = 0x01,
- COM_X,
- COM_Y,
- COM_Z,
- CoR,
- g,
- rk,
- Mk,
- Jk,
- rw,
- Mw,
- i_gear,
- Jow,
- Jm,
- Jw,
- Mb,
- Jbx,
- Jby,
- Jbz,
- Bvk,
- Bvm,
- Bvb,
- EncoderTicksPrRev,
- TicksPrRev,
- SaturationTorqueOfMaxOutputTorque
- } model_t;
-
- typedef enum: uint8_t
- {
- tmp = 0x01,
- tmp2
- } test_t;
- }
-
- namespace ParameterTypes {
- typedef enum: uint8_t {
- UNKNOWN_CONTROLLER = 0x00,
- LQR_CONTROLLER = 0x01,
- SLIDING_MODE_CONTROLLER
- } controllerType_t;
-
- typedef enum: uint8_t {
- OFF = 0x00,
- QUATERNION_CONTROL,
- VELOCITY_CONTROL,
- PATH_FOLLOWING,
- UNKNOWN_MODE = 0xFF
- } controllerMode_t;
-
- typedef enum: uint8_t {
- POWER_OFF = 0x00, // default
- START_STOP_QUATERNION_CONTROL,
- START_STOP_VELOCITY_CONTROL,
- UNKNOWN_BUTTON_MODE = 0xFF
- } powerButtonMode_t;
-
- typedef enum: uint8_t {
- Q_DOT_INERTIAL_MANIFOLD = 0x00,
- Q_DOT_BODY_MANIFOLD,
- OMEGA_INERTIAL_MANIFOLD,
- OMEGA_BODY_MANIFOLD, // default/suggested
- VELOCITY_AND_Q_DOT_MANIFOLD,
- UNKNOWN_MANIFOLD = 0xFF
- } slidingManifoldType_t;
-
- typedef enum: uint8_t {
- BODY_FRAME = 0x00,
- INERTIAL_FRAME,
- HEADING_FRAME,
- UNKNOWN_FRAME = 0xFF
- } referenceFrame_t;
- }
-
- namespace MessageTypesFromPC
- {
- typedef enum MessageTypesFromPC: uint8_t
- {
- Test = 0x01,
- GetParameter = 0x02,
- SetParameter = 0x03,
- StoreParameters = 0x04,
- DumpParameters = 0x05,
- SystemSettings = 0x10,
- EstimatorSettings = 0x11,
- ControllerSettings = 0x12,
- YawCorrection = 0x20,
- PositionCorrection = 0x21,
- QuaternionReference = 0x30,
- AngularVelocityReference = 0x31,
- BalanceControllerReference = 0x32,
- VelocityReference = 0x33,
- MPCpathReference = 0x34,
- CalibrateIMU = 0xE0,
- CPUload = 0xE1,
- RestartController = 0xE2,
- EnterBootloader = 0xF0,
- Reboot = 0xF1,
- Debug = 0xFF
- } MessageTypesFromPC_t;
-
- typedef struct
- {
- ParameterLookup::type_t type;
- uint8_t param;
- } GetParameter_t;
-
- typedef struct
- {
- ParameterLookup::type_t type;
- uint8_t param;
- ParameterLookup::ValueType_t valueType;
- uint8_t arraySize;
- //void * valuePtr; // after arraySize the parameter values are inserted in little-endian format with value[0] first (if array)
- } SetParameter_t;
-
- typedef struct
- {
- uint16_t estimate_msg_prescaler;
- } EstimatorSettings_t;
-
- typedef struct
- {
- ParameterTypes::controllerMode_t mode;
- ParameterTypes::controllerType_t type;
- } ControllerSettings_t;
-
- typedef struct
- {
- float yaw;
- } YawCorrection_t;
-
- typedef struct
- {
- float x;
- float y;
- } PositionCorrection_t;
-
- typedef struct
- {
- struct q_t
- {
- float w;
- float x;
- float y;
- float z;
- } q;
- } QuaternionReference_t;
-
- typedef struct
- {
- ParameterTypes::referenceFrame_t frame;
- struct omega_t
- {
- float x;
- float y;
- float z;
- } omega;
- } AngularVelocityReference_t;
-
- typedef struct
- {
- ParameterTypes::referenceFrame_t frame; // defines the frame of the angular velocity
- struct q_t
- {
- float w;
- float x;
- float y;
- float z;
- } q;
- struct omega_t
- {
- float x;
- float y;
- float z;
- } omega;
- } BalanceControllerReference_t;
-
- typedef struct
- {
- ParameterTypes::referenceFrame_t frame;
- struct vel_t
- {
- float x;
- float y;
- float yaw;
- } vel;
- } VelocityReference_t;
-
- typedef struct
- {
- float desired_velocity;
- float desired_heading;
- float path_length;
- float coeffs_x[10];
- float coeffs_y[10];
- } MPCpathReference_t;
-
- typedef struct
- {
- uint32_t magic_key;
- bool calibrate_accelerometer;
- } CalibrateIMU_t;
-
- typedef struct
- {
- uint32_t magic_key;
- } RestartController_t;
-
- typedef struct
- {
- uint32_t magic_key;
- } EnterBootloader_t;
-
- typedef struct
- {
- uint32_t magic_key;
- } Reboot_t;
- }
-
- namespace MessageTypesToPC
- {
- typedef enum MessageTypesToPC: uint8_t
- {
- Test = 0x01,
- GetParameter = 0x02,
- SetParameterAck = 0x03,
- StoreParametersAck = 0x04,
- DumpParameters = 0x05,
- SystemInfo = 0x10,
- StateEstimates = 0x11,
- ControllerInfo = 0x12,
- AttitudeControllerInfo = 0x13,
- VelocityControllerInfo = 0x14,
- ControllerDebug = 0x15,
- MPCinfo = 0x20,
- PredictedMPCtrajectory = 0x21,
- RawSensor_IMU_MPU9250 = 0x30,
- RawSensor_IMU_MTI200 = 0x31,
- RawSensor_Encoders = 0x32,
- RawSensor_Battery = 0x33,
- CalibrateIMUAck = 0xE0,
- CPUload = 0xE1,
- RestartControllerAck = 0xE2,
- MathDump = 0xFA, // publish array of floats (parsed by PC and dumped into tabulated .txt file in "~/kugle_dump/")
- SensorDump = 0xFB,
- CovarianceDump = 0xFC,
- Debug = 0xFF
- } MessageTypesToPC_t;
-
- typedef struct
- {
- ParameterLookup::type_t type;
- uint8_t param;
- ParameterLookup::ValueType_t valueType;
- uint8_t arraySize;
- //void * valuePtr; // after arraySize the parameter values are inserted in little-endian format with value[0] first (if array)
- } GetParameter_t;
-
- typedef struct
- {
- ParameterLookup::type_t type;
- uint8_t param;
- bool acknowledged;
- } SetParameterAck_t;
-
- typedef struct
- {
- bool acknowledged;
- } StoreParametersAck_t;
-
- typedef struct
- {
- uint16_t parameters_size_bytes;
- uint8_t packages_to_follow;
- } DumpParameters_t;
-
- typedef struct
- {
- float time;
- float battery_pct;
- float current_consumption;
- } SystemInfo_t;
-
- typedef struct
- {
- float time;
- struct q_t
- {
- float w;
- float x;
- float y;
- float z;
- } q;
- struct dq_t
- {
- float w;
- float x;
- float y;
- float z;
- } dq;
- struct pos_t
- {
- float x;
- float y;
- } pos;
- struct vel_t
- {
- float x;
- float y;
- } vel;
- struct COM_t
- {
- float x;
- float y;
- float z;
- } COM;
- } StateEstimates_t;
-
- typedef struct
- {
- float time;
- ParameterTypes::controllerType_t type;
- ParameterTypes::controllerMode_t mode;
- float torque1;
- float torque2;
- float torque3;
- float compute_time;
- float delivered_torque1;
- float delivered_torque2;
- float delivered_torque3;
- } ControllerInfo_t;
-
- typedef struct
- {
- float time;
- } AttitudeControllerInfo_t;
-
- typedef struct
- {
- float time;
- } VelocityControllerInfo_t;
-
- typedef struct
- {
- float time;
- struct orient_t
- {
- float roll;
- float pitch;
- float yaw;
- } orient;
- struct orient_ref_t
- {
- float roll;
- float pitch;
- float yaw;
- } orient_ref;
- struct orient_integral_t
- {
- float roll;
- float pitch;
- float yaw;
- } orient_integral;
- struct omega_t
- {
- float x;
- float y;
- float z;
- } omega;
- struct omega_ref_t
- {
- float x;
- float y;
- float z;
- } omega_ref;
- struct vel_t
- {
- float x;
- float y;
- } vel;
- struct vel_kinematics_t
- {
- float x;
- float y;
- } vel_kinematics;
- struct vel_ref_t
- {
- float x;
- float y;
- } vel_ref;
- float torque[3];
- float S[3];
- } ControllerDebug_t;
-
- typedef struct
- {
- float time;
- } MPCinfo_t;
-
- typedef struct
- {
- float time;
- uint8_t horizon_index;
- struct q_t
- {
- float w;
- float x;
- float y;
- float z;
- } q;
- struct dq_t
- {
- float w;
- float x;
- float y;
- float z;
- } dq;
- struct pos_t
- {
- float x;
- float y;
- } pos;
- struct vel_t
- {
- float x;
- float y;
- } vel;
- } PredictedMPCtrajectory_t;
-
- typedef struct
- {
- float time;
- struct accelerometer_t
- {
- float x;
- float y;
- float z;
- float cov[9]; // stored in row-major format
- } accelerometer;
- struct gyroscope_t
- {
- float x;
- float y;
- float z;
- float cov[9]; // stored in row-major format
- } gyroscope;
- struct magnetometer_t
- {
- float x;
- float y;
- float z;
- float cov[9]; // stored in row-major format
- } magnetometer;
- } RawSensor_IMU_MPU9250_t;
-
- typedef struct
- {
- float time;
- struct accelerometer_t
- {
- float x;
- float y;
- float z;
- } accelerometer;
- struct gyroscope_t
- {
- float x;
- float y;
- float z;
- } gyroscope;
- struct magnetometer_t
- {
- float x;
- float y;
- float z;
- } magnetometer;
- } RawSensor_IMU_MTI200_t;
-
- typedef struct
- {
- float time;
- float angle1;
- float angle2;
- float angle3;
- } RawSensor_Encoders_t;
-
- typedef struct
- {
- float time;
- float vbat1;
- float vbat2;
- float current1;
- float current2;
- float pct1;
- float pct2;
- } RawSensor_Battery_t;
-
- typedef struct
- {
- bool acknowledged;
- } CalibrateIMUAck_t;
-
- typedef struct
- {
- bool acknowledged;
- } RestartControllerAck_t;
- }
-
-} // namespace lspc
-
-#endif // LSPC_MESSAGE_TYPES_HPP
diff --git a/KugleFirmware/Libraries/Devices/LSPC/Packet.hpp b/KugleFirmware/Libraries/Devices/LSPC/Packet.hpp
deleted file mode 100644
index 0781d74..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/Packet.hpp
+++ /dev/null
@@ -1,217 +0,0 @@
-#ifndef LSPC_PACKET_HPP
-#define LSPC_PACKET_HPP
-
-#include
-#include
-#include
-
-#ifdef __EXCEPTIONS
-#include
-#endif
-
-namespace lspc
-{
-
-class Packet
-{
- std::vector encoded_buffer_;
- std::vector decoded_payload_;
- uint8_t packet_type_;
- bool degenerate_ = false;
-
- // Encode the payload with COBS
- //
- // @param input A buffer with the raw unencoded data.
- //
- // @return True if encoding succeeded, false if if the input is more than 254
- // bytes.
- void encodePayload(const std::vector &input)
- {
- size_t output_offset = 3;
- size_t code_idx = output_offset;
- uint8_t code = 1;
-
- for (size_t b = 0; b < input.size(); ++b, ++code)
- {
- if (0x00 == input[b])
- {
- encoded_buffer_[code_idx] = code;
- code_idx = b + 1 + output_offset;
- code = 0;
- }
- else
- {
- encoded_buffer_[b + 1 + output_offset] = input[b];
- }
- }
- encoded_buffer_[code_idx] = code;
-
- return;
- };
-
- // Decode a downstream buffer with COBS.
- //
- // @param input COBS encoded byte-string.
- // @param output A decoded buffer of (input_size - 1) bytes, because the
- // decoder removes one byte of overhead.
- //
- // @return True if decoding succeded, false if the input is zero-size or
- // wrongly encoded.
- bool decodePayload(std::vector &output)
- {
- size_t dec_payload_size = encoded_buffer_.size() - 4;
- output.resize(dec_payload_size);
-
- size_t in_index = 3; // the byte after start byte, type and length
- uint8_t code = encoded_buffer_[in_index];
- size_t code_accumulator = code;
- ++in_index;
-
- // Go through the buffer, copying it to the packet. Inside each code block,
- // copy the byte verbatim, then get the offset code and write a 0x00 instead.
- for (size_t out_index = 0; out_index < dec_payload_size; ++out_index, ++in_index)
- {
- for (int i = 1; i < code && out_index < dec_payload_size; ++i, ++out_index, ++in_index)
- {
- output[out_index] = encoded_buffer_[in_index];
- }
- if (out_index >= dec_payload_size)
- break;
- output[out_index] = 0x00;
- code = encoded_buffer_[in_index];
- code_accumulator += code;
- };
-
- // The accumulated codes should equate to the length of the input. If this is
- // not true, something has gone wrong.
- if (code_accumulator != dec_payload_size + 1)
- {
- return false;
- }
-
- return true;
- };
-
- public:
- // Initialize from encoded buffer
- Packet(const std::vector& buffer)
- {
- encoded_buffer_ = buffer;
- if (encoded_buffer_.size() < 4)
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::length_error("Encoded buffer too small.");
- #endif
- }
-
- if (encoded_buffer_.size() > 258)
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::length_error("Encoded buffer too big.");
- #endif
- }
-
- packet_type_ = encoded_buffer_[1];
- if (packet_type_ == 0x00)
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::runtime_error("Received packet with type 0x00.");
- #endif
- }
-
- if (encoded_buffer_.size() != size_t(encoded_buffer_[2] + 3))
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::runtime_error("Packet length field does not match buffer size.");
- #endif
- }
-
- if (! decodePayload(decoded_payload_))
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::runtime_error("Decoding failed.");
- #endif
- }
- }
-
- // Initialize from serialized payload
- Packet(uint8_t package_type, const std::vector& payload)
- {
- decoded_payload_ = payload;
-
- // Encoding the packet:
- // Make space for the content plus header
- encoded_buffer_.resize(payload.size() + 4);
- // The package starts out with a 0x00
- encoded_buffer_[0] = 0x00;
-
- // The type comes next. It can be 0x01-0xFF but not 0x00.
- packet_type_ = package_type;
- if (package_type == 0x00)
- {
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::runtime_error("Constructed LSPC packet with type 0x00.");
- #endif
- }
- encoded_buffer_[1] = package_type;
-
- // The size of the payload is one longer due to COBS encoding. So the
- // payload can be no more than 254 bytes. If it is longer, the rest of the
- // payload is discarded.
- if (payload.size() > 254)
- {
- encoded_buffer_[2] = 255;
- degenerate_ = true;
- #ifdef __EXCEPTIONS
- throw std::length_error("Payload longer than 254 bytes.");
- #endif
- }
- else
- {
- encoded_buffer_[2] = payload.size() + 1;
- }
-
- // Encode the payload
- encodePayload(payload);
- }
-
- uint8_t* encodedDataPtr()
- {
- return encoded_buffer_.data();
- }
-
- size_t encodedDataSize()
- {
- return encoded_buffer_.size();
- }
-
- std::vector encodedBuffer()
- {
- return encoded_buffer_;
- }
-
- uint8_t packetType()
- {
- return packet_type_;
- }
-
- bool isDegenerate()
- {
- return degenerate_;
- }
-
- std::vector payload()
- {
- return decoded_payload_;
- }
-};
-
-} // namespace LSPC
-
-#endif // LSPC_PACKET_HPP
\ No newline at end of file
diff --git a/KugleFirmware/Libraries/Devices/LSPC/README b/KugleFirmware/Libraries/Devices/LSPC/README
deleted file mode 100644
index b0640c5..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/README
+++ /dev/null
@@ -1 +0,0 @@
-Based on a modified version of the LSPC library from: https://github.com/kdhansen/LSPC
diff --git a/KugleFirmware/Libraries/Devices/LSPC/Serializable.hpp b/KugleFirmware/Libraries/Devices/LSPC/Serializable.hpp
deleted file mode 100644
index 4f271b5..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/Serializable.hpp
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef LSPC_SERIALIZABLE_HPP
-#define LSPC_SERIALIZABLE_HPP
-
-#include
-#include
-
-namespace lspc
-{
-
-class Serializable
-{
-public:
- virtual std::vector serialize() const = 0;
- virtual uint8_t type() const = 0;
-};
-
-} // namespace lspc
-
-#endif // LSPC_SERIALIZABLE_HPP
\ No newline at end of file
diff --git a/KugleFirmware/Libraries/Devices/LSPC/SocketBase.hpp b/KugleFirmware/Libraries/Devices/LSPC/SocketBase.hpp
deleted file mode 100644
index f6e1fb6..0000000
--- a/KugleFirmware/Libraries/Devices/LSPC/SocketBase.hpp
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef LSPC_SOCKETBASE_HPP
-#define LSPC_SOCKETBASE_HPP
-
-#include "Packet.hpp"
-#include "Serializable.hpp"
-
-#include
-#include
-#include
-#include